Release v1.2.8
diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md
index f1c9ff0..3c72d78 100644
--- a/CONTRIBUTING.md
+++ b/CONTRIBUTING.md
@@ -5,9 +5,9 @@
This guide mainly focuses on the proper use of Git.
### 1. Before opening an issue
-To report a bug/request please file an issue in the right repository
-(example for [stm32f7xx_hal_driver](https://github.com/STMicroelectronics/stm32f7xx_hal_driver/issues/new/choose)).
-But check the following boxes before posting an issue:
+In order to centralize your bug reports and requests and to ease their tracking please file an issue into the firmware repository [STM32CubeF7](https://github.com/STMicroelectronics/STM32CubeF7/issues/new/choose).
+
+Please check the following boxes before posting an issue:
- [ ] `Make sure you are using the latest commit (major releases are Tagged, but corrections are available as new commits).`
- [ ] `Make sure your issue is a question/feedback/suggestions RELATED TO the software provided in this repo.` Otherwise, it should be discussed on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
@@ -15,7 +15,7 @@
### 2. Posting the issue
-When you have checked the previous boxes. You will find two templates Issues (Bug Report or Other Issue) available in the **Issues** tab of the repo
+Once you have checked the previous boxes, you will find two templates for issues (Bug Report or Other Issue) available in the **Issues** tab of the firmware repository.
### 3. Pull Requests
-For the moment, the Pull Request feature is not deployed. STMicrolectronics is working on a Contributor License Agreement procedure
+For the moment, the Pull Request feature is not deployed. STMicrolectronics is working on a Contributor License Agreement (CLA) procedure.
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index 889db8f..90767ed 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -7,7 +7,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -236,6 +236,16 @@
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
+#if defined(STM32G4) || defined(STM32H7)
+#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
+#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
+#endif
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4)
+#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
+#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
+#endif
+
/**
* @}
*/
@@ -296,8 +306,17 @@
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
+#endif
+
#endif /* STM32L4 */
+#if defined(STM32G0)
+#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
+#endif
+
#if defined(STM32H7)
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
@@ -355,6 +374,9 @@
#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
+#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
+#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
+
#endif /* STM32H7 */
/**
@@ -450,7 +472,9 @@
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
-#endif
+#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
+#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
+#endif /* STM32H7 */
/**
* @}
@@ -486,6 +510,13 @@
#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
+#if defined(STM32G4)
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster
+#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
+#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
+#endif /* STM32G4 */
/**
* @}
*/
@@ -494,7 +525,7 @@
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
* @{
*/
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
@@ -547,18 +578,25 @@
#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
-#endif
+
+#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \
+ defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
+#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
+#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
+#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
+#endif /* STM32H7 */
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32H7)
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32H7*/
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/
#if defined(STM32L1)
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
@@ -599,6 +637,185 @@
#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
+
+#if defined(STM32G4)
+#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
+#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
+#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
+#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
+#endif /* STM32G4 */
+
+#if defined(STM32H7)
+#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+
+#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+#endif /* STM32H7 */
+
+#if defined(STM32F3)
+/** @brief Constants defining available sources associated to external events.
+ */
+#define HRTIM_EVENTSRC_1 (0x00000000U)
+#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
+#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
+#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
+
+/** @brief Constants defining the events that can be selected to configure the
+ * set/reset crossbar of a timer output
+ */
+#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
+#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
+#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
+#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
+#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
+#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
+#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
+#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
+#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
+
+#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
+#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
+#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
+#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
+#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
+#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
+#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
+#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
+#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
+
+/** @brief Constants defining the event filtering applied to external events
+ * by a timer
+ */
+#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+
+/** @brief Constants defining the DLL calibration periods (in micro seconds)
+ */
+#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
+#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
+#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
+#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
+
+#endif /* STM32F3 */
/**
* @}
*/
@@ -738,6 +955,12 @@
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7)
+#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
+#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
+#endif
+
+
/**
* @}
*/
@@ -753,7 +976,6 @@
#define I2S_FLAG_TXE I2S_FLAG_TXP
#define I2S_FLAG_RXNE I2S_FLAG_RXP
- #define I2S_FLAG_FRE I2S_FLAG_TIFRE
#endif
#if defined(STM32F7)
@@ -824,6 +1046,16 @@
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
+#if defined(STM32H7)
+#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
+#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
+
+#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
+#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
+#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
+#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
+#endif /* STM32H7 */
+
/**
* @}
*/
@@ -971,6 +1203,24 @@
#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
#endif
+#if defined(STM32H7)
+#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1
+#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2
+#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1
+#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2
+#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1
+#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2
+#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1
+#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1
+#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2
+#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1
+#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2
+#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2
+#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1
+#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2
+#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
+#endif
+
/**
* @}
*/
@@ -1199,6 +1449,30 @@
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
+
+#if defined(STM32L4) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+
+#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
+#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
+#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
+#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
+
+#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
+#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
+#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
+#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
+#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
+#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
+#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
+#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
+#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
+#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
+
+#endif /* STM32L4 || STM32F4 || STM32F7 || STM32H7 */
/**
* @}
*/
@@ -1221,6 +1495,13 @@
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
+#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
+#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
+#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
+#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
+#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */
+
/**
* @}
*/
@@ -1250,16 +1531,18 @@
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7)
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
-#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 */
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
#if defined(STM32F4)
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
@@ -1278,6 +1561,13 @@
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
* @{
*/
+
+#if defined(STM32G0)
+#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
+#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
+#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
+#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
+#endif
#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
@@ -1350,14 +1640,14 @@
#define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
-#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0)
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
-#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */
+#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
/**
* @}
*/
@@ -2476,12 +2766,28 @@
#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
+
+#if defined(STM32H7)
+#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE
+#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
+
+#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/
+#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
+
+
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
+#endif
+
#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
+
#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
@@ -2814,6 +3120,15 @@
#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
+#if defined(STM32L1)
+#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#endif /* STM32L1 */
+
#if defined(STM32F4)
#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
@@ -2930,7 +3245,7 @@
#if defined(STM32L4)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
-#elif defined(STM32WB) || defined(STM32G0)
+#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif
@@ -3058,7 +3373,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3174,14 +3489,14 @@
#define SDIO_IRQHandler SDMMC1_IRQHandler
#endif
-#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2)
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
#endif
-#if defined(STM32H7)
+#if defined(STM32H7) || defined(STM32L5)
#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
@@ -3421,18 +3736,28 @@
/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
* @{
*/
-#if defined (STM32H7) || defined (STM32F3)
-#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
-#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
-#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
-#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
-#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
-#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
+#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
+#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
+#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
+#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
+#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
+#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
+#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
#endif
/**
* @}
*/
+/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7)
+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
+#endif /* STM32L4 || STM32F4 || STM32F7 */
+/**
+ * @}
+ */
+
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
* @{
*/
diff --git a/Inc/Legacy/stm32f7xx_hal_can_legacy.h b/Inc/Legacy/stm32f7xx_hal_can_legacy.h
index c095def..4984a1c 100644
--- a/Inc/Legacy/stm32f7xx_hal_can_legacy.h
+++ b/Inc/Legacy/stm32f7xx_hal_can_legacy.h
@@ -6,13 +6,29 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
diff --git a/Inc/stm32f7xx_hal_adc.h b/Inc/stm32f7xx_hal_adc.h
index 6d493df..2d882c0 100644
--- a/Inc/stm32f7xx_hal_adc.h
+++ b/Inc/stm32f7xx_hal_adc.h
@@ -18,8 +18,8 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_ADC_H
-#define __STM32F7xx_ADC_H
+#ifndef STM32F7xx_ADC_H
+#define STM32F7xx_ADC_H
#ifdef __cplusplus
extern "C" {
@@ -416,8 +416,10 @@
#define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
#define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
+#define ADC_INTERNAL_NONE 0x80000000U
#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
+#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)(ADC_CHANNEL_18 | 0x10000000U))
/**
* @}
*/
@@ -732,6 +734,10 @@
*/
#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18) || \
+ ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
+ ((CHANNEL) == ADC_INTERNAL_NONE))
#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
@@ -947,7 +953,7 @@
}
#endif
-#endif /*__STM32F7xx_ADC_H */
+#endif /* STM32F7xx_ADC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f7xx_hal_adc_ex.h b/Inc/stm32f7xx_hal_adc_ex.h
index c2da1af..cef8f49 100644
--- a/Inc/stm32f7xx_hal_adc_ex.h
+++ b/Inc/stm32f7xx_hal_adc_ex.h
@@ -18,8 +18,8 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_ADC_EX_H
-#define __STM32F7xx_ADC_EX_H
+#ifndef STM32F7xx_ADC_EX_H
+#define STM32F7xx_ADC_EX_H
#ifdef __cplusplus
extern "C" {
@@ -210,7 +210,7 @@
/** @defgroup ADCEx_channels ADC Specific Channels
* @{
*/
-#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | 0x10000000U)
+
/**
* @}
*/
@@ -274,8 +274,6 @@
/** @defgroup ADCEx_Private_Macros ADC Private Macros
* @{
*/
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18) || \
- ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR))
#define IS_ADC_MODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \
((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
@@ -352,7 +350,7 @@
}
#endif
-#endif /*__STM32F7xx_ADC_EX_H */
+#endif /* STM32F7xx_ADC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f7xx_hal_cryp.h b/Inc/stm32f7xx_hal_cryp.h
index a8f8baf..076d2cd 100644
--- a/Inc/stm32f7xx_hal_cryp.h
+++ b/Inc/stm32f7xx_hal_cryp.h
@@ -6,23 +6,23 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
+ * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_HAL_CRYP_H
#define __STM32F7xx_HAL_CRYP_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
@@ -51,87 +51,97 @@
{
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
This parameter can be a value of @ref CRYP_Data_Type */
- uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
+ uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */
- uint32_t* pKey; /*!< The key used for encryption/decryption */
- uint32_t* pInitVect; /*!< The initialization vector used also as initialization
+ uint32_t *pKey; /*!< The key used for encryption/decryption */
+ uint32_t *pInitVect; /*!< The initialization vector used also as initialization
counter in CTR mode */
- uint32_t Algorithm; /*!< DES/ TDES Algorithm ECB/CBC
+ uint32_t Algorithm; /*!< DES/ TDES Algorithm ECB/CBC
AES Algorithm ECB/CBC/CTR/GCM or CCM
This parameter can be a value of @ref CRYP_Algorithm_Mode */
- uint32_t* Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
+ uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
GCM : also known as Additional Authentication Data
CCM : named B1 composed of the associated data length and Associated Data. */
uint32_t HeaderSize; /*!< The size of header buffer in word */
- uint32_t* B0; /*!< B0 is first authentication block used only in AES CCM mode */
+ uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
+ uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
+ Vector only once and to skip configuration for consecutive processings.
+ This parameter can be a value of @ref CRYP_Configuration_Skip */
-}CRYP_ConfigTypeDef;
+} CRYP_ConfigTypeDef;
/**
* @brief CRYP State Structure definition
*/
-
+
typedef enum
{
HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */
HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */
HAL_CRYP_STATE_BUSY = 0x02U /*!< CRYP BUSY, internal processing is ongoing */
-}HAL_CRYP_STATETypeDef;
-
+} HAL_CRYP_STATETypeDef;
+
/**
* @brief CRYP handle Structure definition
*/
-
+
typedef struct __CRYP_HandleTypeDef
{
#if defined (CRYP)
- CRYP_TypeDef *Instance; /*!< CRYP registers base address */
+ CRYP_TypeDef *Instance; /*!< CRYP registers base address */
#else /* AES*/
- AES_TypeDef *Instance; /*!< AES Register base address */
+ AES_TypeDef *Instance; /*!< AES Register base address */
#endif /* End AES or CRYP */
- CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */
-
- FunctionalState AutoKeyDerivation; /*!< Used only in TinyAES to allows to bypass or not key write-up before decryption.
- This parameter can be a value of ENABLE/DISABLE */
-
- uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+ CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */
- uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+ FunctionalState AutoKeyDerivation; /*!< Used only in TinyAES to allows to bypass or not key write-up before decryption.
+ This parameter can be a value of ENABLE/DISABLE */
- __IO uint16_t CrypHeaderCount; /*!< Counter of header data */
-
- __IO uint16_t CrypInCount; /*!< Counter of input data */
+ uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
- __IO uint16_t CrypOutCount; /*!< Counter of output data */
-
- uint16_t Size; /*!< length of input data in word */
+ uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
- uint32_t Phase; /*!< CRYP peripheral phase */
+ __IO uint16_t CrypHeaderCount; /*!< Counter of header data */
- DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
+ __IO uint16_t CrypInCount; /*!< Counter of input data */
- DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
+ __IO uint16_t CrypOutCount; /*!< Counter of output data */
- HAL_LockTypeDef Lock; /*!< CRYP locking object */
+ uint16_t Size; /*!< length of input data in word */
- __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
-
- __IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
-
+ uint32_t Phase; /*!< CRYP peripheral phase */
+
+ DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< CRYP locking object */
+
+ __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
+
+ __IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
+
+ uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag, used when
+ configuration can be skipped */
+
+ uint32_t SizesSum; /*!< Sum of successive payloads lengths (in bytes), stored
+ for a single signature computation after several
+ messages processing */
+
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
- void (*InCpltCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Input FIFO transfer completed callback */
- void (*OutCpltCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Output FIFO transfer completed callback */
- void (*ErrorCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Error callback */
-
- void (* MspInitCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp Init callback */
- void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp DeInit callback */
+ void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Input FIFO transfer completed callback */
+ void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Output FIFO transfer completed callback */
+ void (*ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Error callback */
-#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
-}CRYP_HandleTypeDef;
+ void (* MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp Init callback */
+ void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp DeInit callback */
+
+#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
+} CRYP_HandleTypeDef;
/**
@@ -152,7 +162,7 @@
HAL_CRYP_MSPINIT_CB_ID = 0x04U, /*!< CRYP MspInit callback ID */
HAL_CRYP_MSPDEINIT_CB_ID = 0x05U /*!< CRYP MspDeInit callback ID */
-}HAL_CRYP_CallbackIDTypeDef;
+} HAL_CRYP_CallbackIDTypeDef;
/**
* @}
*/
@@ -162,7 +172,7 @@
* @{
*/
-typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< pointer to a common CRYP callback function */
+typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< pointer to a common CRYP callback function */
/**
* @}
@@ -181,7 +191,7 @@
#define HAL_CRYP_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_CRYP_ERROR_WRITE 0x00000001U /*!< Write error */
#define HAL_CRYP_ERROR_READ 0x00000002U /*!< Read error */
-#define HAL_CRYP_ERROR_DMA 0x00000004U /*!< DMA error */
+#define HAL_CRYP_ERROR_DMA 0x00000004U /*!< DMA error */
#define HAL_CRYP_ERROR_BUSY 0x00000008U /*!< Busy flag error */
#define HAL_CRYP_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */
#define HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U /*!< Not supported mode */
@@ -189,21 +199,21 @@
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
#define HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid Callback error */
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
-/**
+/**
* @}
*/
-/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
+/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
* @{
*/
#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */
-#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is word */
+#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is word */
-/**
+/**
* @}
- */
-
+ */
+
/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
* @{
*/
@@ -212,14 +222,14 @@
#define CRYP_DES_ECB CRYP_CR_ALGOMODE_DES_ECB
#define CRYP_DES_CBC CRYP_CR_ALGOMODE_DES_CBC
#define CRYP_TDES_ECB CRYP_CR_ALGOMODE_TDES_ECB
-#define CRYP_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC
+#define CRYP_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC
#define CRYP_AES_ECB CRYP_CR_ALGOMODE_AES_ECB
#define CRYP_AES_CBC CRYP_CR_ALGOMODE_AES_CBC
#define CRYP_AES_CTR CRYP_CR_ALGOMODE_AES_CTR
-#define CRYP_AES_GCM CRYP_CR_ALGOMODE_AES_GCM
+#define CRYP_AES_GCM CRYP_CR_ALGOMODE_AES_GCM
#define CRYP_AES_CCM CRYP_CR_ALGOMODE_AES_CCM
-
+
#else /* AES*/
#define CRYP_AES_ECB 0x00000000U /*!< Electronic codebook chaining algorithm */
#define CRYP_AES_CBC AES_CR_CHMOD_0 /*!< Cipher block chaining algorithm */
@@ -228,7 +238,7 @@
#define CRYP_AES_CCM AES_CR_CHMOD_2 /*!< Counter with Cipher Mode */
#endif /* End AES or CRYP */
-/**
+/**
* @}
*/
@@ -240,10 +250,10 @@
#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0
#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1
#else /* AES*/
-#define CRYP_KEYSIZE_128B 0x00000000U /*!< 128-bit long key */
-#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */
+#define CRYP_KEYSIZE_128B 0x00000000U /*!< 128-bit long key */
+#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */
#endif /* End AES or CRYP */
-/**
+/**
* @}
*/
@@ -261,15 +271,15 @@
#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1 /*!< 8-bit data type (byte swapping) */
#define CRYP_DATATYPE_1B AES_CR_DATATYPE /*!< 1-bit data type (bit swapping) */
#endif /* End AES or CRYP */
-
-/**
+
+/**
* @}
*/
/** @defgroup CRYP_Interrupt CRYP Interrupt
* @{
*/
-#if defined (CRYP)
+#if defined (CRYP)
#define CRYP_IT_INI CRYP_IMSCR_INIM /*!< Input FIFO Interrupt */
#define CRYP_IT_OUTI CRYP_IMSCR_OUTIM /*!< Output FIFO Interrupt */
#else /* AES*/
@@ -297,7 +307,7 @@
or a key preparation (for AES decryption). */
/* Flags in the RISR register */
#define CRYP_FLAG_OUTRIS 0x01000002U /*!< Output FIFO service raw interrupt status */
-#define CRYP_FLAG_INRIS 0x01000001U /*!< Input FIFO service raw interrupt status*/
+#define CRYP_FLAG_INRIS 0x01000001U /*!< Input FIFO service raw interrupt status*/
#else /* AES*/
/* status flags */
#define CRYP_FLAG_BUSY AES_SR_BUSY /*!< GCM process suspension forbidden */
@@ -312,7 +322,18 @@
/**
* @}
*/
-
+
+/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode
+ * @{
+ */
+
+#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration to do systematically */
+#define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration to do only once */
+
+/**
+ * @}
+ */
+
/**
* @}
@@ -336,7 +357,7 @@
#else
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET)
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
-
+
/**
* @brief Enable/Disable the CRYP peripheral.
* @param __HANDLE__: specifies the CRYP handle.
@@ -345,33 +366,33 @@
#if defined(CRYP)
#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN)
#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CRYP_CR_CRYPEN)
-#else /* AES*/
+#else /* AES*/
#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= AES_CR_EN)
#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~AES_CR_EN)
-#endif /* End AES or CRYP */
+#endif /* End AES or CRYP */
/** @brief Check whether the specified CRYP status flag is set or not.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values for TinyAES:
- * @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
- * @arg @ref CRYP_IT_WRERR Write Error
- * @arg @ref CRYP_IT_RDERR Read Error
- * @arg @ref CRYP_IT_CCF Computation Complete
+ * @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
+ * @arg @ref CRYP_IT_WRERR Write Error
+ * @arg @ref CRYP_IT_RDERR Read Error
+ * @arg @ref CRYP_IT_CCF Computation Complete
* This parameter can be one of the following values for CRYP:
- * @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
- * or a key preparation (for AES decryption).
+ * @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
+ * or a key preparation (for AES decryption).
* @arg CRYP_FLAG_IFEM: Input FIFO is empty
* @arg CRYP_FLAG_IFNF: Input FIFO is not full
* @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
* @arg CRYP_FLAG_OFNE: Output FIFO is not empty
* @arg CRYP_FLAG_OFFU: Output FIFO is full
- * @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
- * @retval The state of __FLAG__ (TRUE or FALSE).
+ * @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
+ * @retval The state of __FLAG__ (TRUE or FALSE).
*/
#define CRYP_FLAG_MASK 0x0000001FU
-#if defined(CRYP)
+#if defined(CRYP)
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
- ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
+ ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
#else /* AES*/
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
#endif /* End AES or CRYP */
@@ -380,12 +401,12 @@
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
- * @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
+ * @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
* @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
-#if defined(AES)
+#if defined(AES)
#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))
@@ -393,37 +414,39 @@
* @param __INTERRUPT__: CRYP interrupt source to check
* This parameter can be one of the following values for TinyAES:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
- * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
+ * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
* @param __HANDLE__: specifies the CRYP handle.
* @retval State of interruption (TRUE or FALSE).
*/
-#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\
+ & (__INTERRUPT__)) == (__INTERRUPT__))
#endif /* AES */
/** @brief Check whether the specified CRYP interrupt is set or not.
* @param __INTERRUPT__: specifies the interrupt to check.
* This parameter can be one of the following values for TinyAES:
- * @arg @ref CRYP_IT_WRERR Write Error
- * @arg @ref CRYP_IT_RDERR Read Error
- * @arg @ref CRYP_IT_CCF Computation Complete
+ * @arg @ref CRYP_IT_WRERR Write Error
+ * @arg @ref CRYP_IT_RDERR Read Error
+ * @arg @ref CRYP_IT_CCF Computation Complete
* This parameter can be one of the following values for CRYP:
* @arg CRYP_IT_INI: Input FIFO service masked interrupt status
* @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status
* @param __HANDLE__: specifies the CRYP handle.
* @retval The state of __INTERRUPT__ (TRUE or FALSE).
*/
-#if defined(CRYP)
-#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
+#if defined(CRYP)
+#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR\
+ & (__INTERRUPT__)) == (__INTERRUPT__))
#else /* AES*/
#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
#endif /* End AES or CRYP */
/**
- * @brief Enable the CRYP interrupt.
+ * @brief Enable the CRYP interrupt.
* @param __INTERRUPT__: CRYP Interrupt.
- * This parameter can be one of the following values for TinyAES:
+ * This parameter can be one of the following values for TinyAES:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
* This parameter can be one of the following values for CRYP:
@@ -432,16 +455,16 @@
* @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
-#if defined(CRYP)
+#if defined(CRYP)
#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
-#else /* AES*/
+#else /* AES*/
#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
#endif /* End AES or CRYP */
/**
* @brief Disable the CRYP interrupt.
* @param __INTERRUPT__: CRYP Interrupt.
- * This parameter can be one of the following values for TinyAES:
+ * This parameter can be one of the following values for TinyAES:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
* This parameter can be one of the following values for CRYP:
@@ -450,9 +473,9 @@
* @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
-#if defined(CRYP)
+#if defined(CRYP)
#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
-#else /* AES*/
+#else /* AES*/
#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
#endif /* End AES or CRYP */
@@ -468,28 +491,31 @@
/** @addtogroup CRYP_Exported_Functions_Group1
* @{
- */
+ */
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
-HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf );
-HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf );
+HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
+HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
+ pCRYP_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
/**
* @}
- */
+ */
/** @addtogroup CRYP_Exported_Functions_Group2
* @{
- */
+ */
/* encryption/decryption ***********************************/
-HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
+ uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
@@ -497,12 +523,12 @@
/**
* @}
- */
+ */
/** @addtogroup CRYP_Exported_Functions_Group3
* @{
- */
+ */
/* Interrupt Handler functions **********************************************/
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
@@ -513,8 +539,8 @@
/**
* @}
- */
-
+ */
+
/**
* @}
*/
@@ -529,23 +555,23 @@
*/
#if defined(CRYP)
#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_DES_ECB) || \
- ((ALGORITHM) == CRYP_DES_CBC) || \
- ((ALGORITHM) == CRYP_TDES_ECB) || \
- ((ALGORITHM) == CRYP_TDES_CBC) || \
- ((ALGORITHM) == CRYP_AES_ECB) || \
- ((ALGORITHM) == CRYP_AES_CBC) || \
- ((ALGORITHM) == CRYP_AES_CTR) || \
- ((ALGORITHM) == CRYP_AES_GCM) || \
- ((ALGORITHM) == CRYP_AES_CCM))
+ ((ALGORITHM) == CRYP_DES_CBC) || \
+ ((ALGORITHM) == CRYP_TDES_ECB) || \
+ ((ALGORITHM) == CRYP_TDES_CBC) || \
+ ((ALGORITHM) == CRYP_AES_ECB) || \
+ ((ALGORITHM) == CRYP_AES_CBC) || \
+ ((ALGORITHM) == CRYP_AES_CTR) || \
+ ((ALGORITHM) == CRYP_AES_GCM) || \
+ ((ALGORITHM) == CRYP_AES_CCM))
#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \
((KEYSIZE) == CRYP_KEYSIZE_192B) || \
((KEYSIZE) == CRYP_KEYSIZE_256B))
-#else /* AES*/
+#else /* AES*/
#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB) || \
- ((ALGORITHM) == CRYP_AES_CBC) || \
- ((ALGORITHM) == CRYP_AES_CTR) || \
- ((ALGORITHM) == CRYP_AES_GCM_GMAC)|| \
- ((ALGORITHM) == CRYP_AES_CCM))
+ ((ALGORITHM) == CRYP_AES_CBC) || \
+ ((ALGORITHM) == CRYP_AES_CTR) || \
+ ((ALGORITHM) == CRYP_AES_GCM_GMAC)|| \
+ ((ALGORITHM) == CRYP_AES_CCM))
#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \
@@ -557,6 +583,8 @@
((DATATYPE) == CRYP_DATATYPE_8B) || \
((DATATYPE) == CRYP_DATATYPE_1B))
+#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
+ ((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
/**
* @}
*/
@@ -573,7 +601,7 @@
/**
* @}
- */
+ */
/* Private defines -----------------------------------------------------------*/
/** @defgroup CRYP_Private_Defines CRYP Private Defines
* @{
@@ -581,8 +609,8 @@
/**
* @}
- */
-
+ */
+
/* Private variables ---------------------------------------------------------*/
/** @defgroup CRYP_Private_Variables CRYP Private Variables
* @{
@@ -590,7 +618,7 @@
/**
* @}
- */
+ */
/* Private functions prototypes ----------------------------------------------*/
/** @defgroup CRYP_Private_Functions_Prototypes CRYP Private Functions Prototypes
* @{
@@ -608,21 +636,21 @@
/**
* @}
*/
-
-
-/**
- * @}
- */
/**
* @}
- */
+ */
+
+
+/**
+ * @}
+ */
#endif /* TinyAES or CRYP*/
/**
* @}
- */
+ */
#ifdef __cplusplus
}
diff --git a/Inc/stm32f7xx_hal_cryp_ex.h b/Inc/stm32f7xx_hal_cryp_ex.h
index 856862e..d9fa776 100644
--- a/Inc/stm32f7xx_hal_cryp_ex.h
+++ b/Inc/stm32f7xx_hal_cryp_ex.h
@@ -6,23 +6,23 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
+ * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_HAL_CRYP_EX_H
#define __STM32F7xx_HAL_CRYP_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -35,14 +35,14 @@
/** @addtogroup CRYPEx
* @{
*/
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/** @defgroup CRYPEx_Exported_Types CRYPEx Exported types
* @{
*/
/**
* @}
- */
+ */
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRYPEx_Exported_Constants CRYPEx Exported constants
* @{
@@ -50,8 +50,8 @@
/**
* @}
- */
-
+ */
+
/* Private types -------------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Types CRYPEx Private Types
* @{
@@ -59,7 +59,7 @@
/**
* @}
- */
+ */
/* Private variables ---------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
@@ -68,7 +68,7 @@
/**
* @}
- */
+ */
/* Private constants ---------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
@@ -77,17 +77,17 @@
/**
* @}
- */
+ */
/* Private macros ------------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
* @{
*/
- /**
+/**
* @}
- */
-
+ */
+
/* Private functions ---------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
* @{
@@ -104,7 +104,7 @@
#if defined (CRYP) || defined (AES)
/** @addtogroup CRYPEx_Exported_Functions_Group1
* @{
- */
+ */
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
/**
@@ -112,10 +112,10 @@
*/
#endif /* CRYP||AES */
-#if defined (AES)
+#if defined (AES)
/** @addtogroup CRYPEx_Exported_Functions_Group2
* @{
- */
+ */
void HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
/**
@@ -125,16 +125,16 @@
/**
* @}
- */
-
-/**
- * @}
- */
+ */
/**
* @}
- */
-
+ */
+
+/**
+ * @}
+ */
+
#ifdef __cplusplus
}
#endif
diff --git a/Inc/stm32f7xx_hal_dcmi.h b/Inc/stm32f7xx_hal_dcmi.h
index 1e398e2..7882198 100644
--- a/Inc/stm32f7xx_hal_dcmi.h
+++ b/Inc/stm32f7xx_hal_dcmi.h
@@ -18,18 +18,18 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_DCMI_H
-#define __STM32F7xx_HAL_DCMI_H
+#ifndef STM32F7xx_HAL_DCMI_H
+#define STM32F7xx_HAL_DCMI_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
#if defined (DCMI)
-
+
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
@@ -37,15 +37,15 @@
/** @addtogroup DCMI DCMI
* @brief DCMI HAL module driver
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
/** @defgroup DCMI_Exported_Types DCMI Exported Types
* @{
*/
-/**
+/**
* @brief HAL DCMI State structures definition
- */
+ */
typedef enum
{
HAL_DCMI_STATE_RESET = 0x00U, /*!< DCMI not yet initialized or disabled */
@@ -53,23 +53,33 @@
HAL_DCMI_STATE_BUSY = 0x02U, /*!< DCMI internal processing is ongoing */
HAL_DCMI_STATE_TIMEOUT = 0x03U, /*!< DCMI timeout state */
HAL_DCMI_STATE_ERROR = 0x04U, /*!< DCMI error state */
- HAL_DCMI_STATE_SUSPENDED = 0x05U /*!< DCMI suspend state */
-}HAL_DCMI_StateTypeDef;
+ HAL_DCMI_STATE_SUSPENDED = 0x05U /*!< DCMI suspend state */
+} HAL_DCMI_StateTypeDef;
-/**
+/**
* @brief DCMIEx Embedded Synchronisation CODE Init structure definition
- */
+ */
typedef struct
{
uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */
uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */
uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
-}DCMI_CodesInitTypeDef;
+} DCMI_CodesInitTypeDef;
-/**
+/**
+ * @brief DCMI Embedded Synchronisation CODE Init structure definition
+ */
+typedef struct
+{
+ uint8_t FrameStartUnmask; /*!< Specifies the frame start delimiter unmask. */
+ uint8_t LineStartUnmask; /*!< Specifies the line start delimiter unmask. */
+ uint8_t LineEndUnmask; /*!< Specifies the line end delimiter unmask. */
+ uint8_t FrameEndUnmask; /*!< Specifies the frame end delimiter unmask. */
+} DCMI_SyncUnmaskTypeDef;
+/**
* @brief DCMI Init structure definition
- */
+ */
typedef struct
{
uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.
@@ -93,23 +103,25 @@
DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the line/frame start delimiter and the
line/frame end delimiter */
- uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode.
+ uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode.
This parameter can be a value of @ref DCMI_MODE_JPEG */
- uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface
+#ifdef DCMI_CR_BSM
+ uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface
This parameter can be a value of @ref DCMI_Byte_Select_Mode */
-
+
uint32_t ByteSelectStart; /*!< Specifies if the data to be captured by the interface is even or odd
This parameter can be a value of @ref DCMI_Byte_Select_Start */
- uint32_t LineSelectMode; /*!< Specifies the line of data to be captured by the interface
+ uint32_t LineSelectMode; /*!< Specifies the line of data to be captured by the interface
This parameter can be a value of @ref DCMI_Line_Select_Mode */
-
+
uint32_t LineSelectStart; /*!< Specifies if the line of data to be captured by the interface is even or odd
This parameter can be a value of @ref DCMI_Line_Select_Start */
-}DCMI_InitTypeDef;
+#endif
+} DCMI_InitTypeDef;
-/**
+/**
* @brief DCMI handle Structure definition
*/
typedef struct __DCMI_HandleTypeDef
@@ -134,27 +146,27 @@
__IO uint32_t ErrorCode; /*!< DCMI Error code */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
- void (* FrameEventCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Frame Event Callback */
- void (* VsyncEventCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Vsync Event Callback */
- void (* LineEventCallback ) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Line Event Callback */
- void (* ErrorCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Error Callback */
- void (* MspInitCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp Init callback */
- void (* MspDeInitCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp DeInit callback */
-#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
-}DCMI_HandleTypeDef;
+ void (* FrameEventCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Frame Event Callback */
+ void (* VsyncEventCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Vsync Event Callback */
+ void (* LineEventCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Line Event Callback */
+ void (* ErrorCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Error Callback */
+ void (* MspInitCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp Init callback */
+ void (* MspDeInitCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp DeInit callback */
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+} DCMI_HandleTypeDef;
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
typedef enum
{
HAL_DCMI_FRAME_EVENT_CB_ID = 0x00U, /*!< DCMI Frame Event Callback ID */
HAL_DCMI_VSYNC_EVENT_CB_ID = 0x01U, /*!< DCMI Vsync Event Callback ID */
- HAL_DCMI_LINE_EVENT_CB_ID = 0x02U, /*!< DCMI Line Event Callback ID */
+ HAL_DCMI_LINE_EVENT_CB_ID = 0x02U, /*!< DCMI Line Event Callback ID */
HAL_DCMI_ERROR_CB_ID = 0x03U, /*!< DCMI Error Callback ID */
HAL_DCMI_MSPINIT_CB_ID = 0x04U, /*!< DCMI MspInit callback ID */
HAL_DCMI_MSPDEINIT_CB_ID = 0x05U /*!< DCMI MspDeInit callback ID */
-
-}HAL_DCMI_CallbackIDTypeDef;
-
+
+} HAL_DCMI_CallbackIDTypeDef;
+
typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
@@ -185,7 +197,7 @@
/** @defgroup DCMI_Capture_Mode DCMI Capture Mode
* @{
- */
+ */
#define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000U) /*!< The received data are transferred continuously
into the destination memory through the DMA */
#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of
@@ -196,7 +208,7 @@
/** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
* @{
- */
+ */
#define DCMI_SYNCHRO_HARDWARE ((uint32_t)0x00000000U) /*!< Hardware synchronization data capture (frame/line start/stop)
is synchronized with the HSYNC/VSYNC signals */
#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with
@@ -228,7 +240,7 @@
/** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
* @{
- */
+ */
#define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000U) /*!< Horizontal synchronization active Low */
#define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */
@@ -269,7 +281,7 @@
* @}
*/
-/** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
+/** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
* @{
*/
#define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFFU) /*!< Window coordinate */
@@ -280,7 +292,7 @@
/** @defgroup DCMI_Window_Height DCMI Window Height
* @{
- */
+ */
#define DCMI_WINDOW_HEIGHT ((uint32_t)0x1FFFU) /*!< Window Height */
/**
@@ -303,31 +315,31 @@
* @{
*/
-/**
+/**
* @brief DCMI SR register
- */
+ */
#define DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization between lines) */
#define DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization between frames) */
#define DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE) /*!< FIFO not empty flag */
-/**
- * @brief DCMI RIS register
- */
-#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RIS_FRAME_RIS) /*!< Frame capture complete interrupt flag */
-#define DCMI_FLAG_OVRRI ((uint32_t)DCMI_RIS_OVR_RIS) /*!< Overrun interrupt flag */
-#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RIS_ERR_RIS) /*!< Synchronization error interrupt flag */
-#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RIS_VSYNC_RIS) /*!< VSYNC interrupt flag */
-#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RIS_LINE_RIS) /*!< Line interrupt flag */
-/**
- * @brief DCMI MIS register
- */
-#define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS) /*!< DCMI Frame capture complete masked interrupt status */
-#define DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS ) /*!< DCMI Overrun masked interrupt status */
-#define DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS ) /*!< DCMI Synchronization error masked interrupt status */
-#define DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS) /*!< DCMI VSYNC masked interrupt status */
-#define DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS ) /*!< DCMI Line masked interrupt status */
+/**
+ * @brief DCMI RIS register
+ */
+#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RIS_FRAME_RIS) /*!< Frame capture complete interrupt flag */
+#define DCMI_FLAG_OVRRI ((uint32_t)DCMI_RIS_OVR_RIS) /*!< Overrun interrupt flag */
+#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RIS_ERR_RIS) /*!< Synchronization error interrupt flag */
+#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RIS_VSYNC_RIS) /*!< VSYNC interrupt flag */
+#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RIS_LINE_RIS) /*!< Line interrupt flag */
+/**
+ * @brief DCMI MIS register
+ */
+#define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS) /*!< DCMI Frame capture complete masked interrupt status */
+#define DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS ) /*!< DCMI Overrun masked interrupt status */
+#define DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS ) /*!< DCMI Synchronization error masked interrupt status */
+#define DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS) /*!< DCMI VSYNC masked interrupt status */
+#define DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS ) /*!< DCMI Line masked interrupt status */
/**
* @}
- */
+ */
/** @defgroup DCMI_Byte_Select_Mode DCMI Byte Select Mode
* @{
@@ -343,7 +355,7 @@
/** @defgroup DCMI_Byte_Select_Start DCMI Byte Select Start
* @{
- */
+ */
#define DCMI_OEBS_ODD ((uint32_t)0x00000000U) /*!< Interface captures first data from the frame/line start, second one being dropped */
#define DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */
@@ -363,23 +375,23 @@
/** @defgroup DCMI_Line_Select_Start DCMI Line Select Start
* @{
- */
+ */
#define DCMI_OELS_ODD ((uint32_t)0x00000000U) /*!< Interface captures first line from the frame start, second one being dropped */
#define DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */
/**
* @}
*/
-
+
/**
* @}
*/
-
+
/* Exported macro ------------------------------------------------------------*/
/** @defgroup DCMI_Exported_Macros DCMI Exported Macros
* @{
*/
-
+
/** @brief Reset DCMI handle state
* @param __HANDLE__ specifies the DCMI handle.
* @retval None
@@ -410,19 +422,19 @@
* @param __HANDLE__ DCMI handle
* @param __FLAG__ Get the specified flag.
* This parameter can be one of the following values (no combination allowed)
- * @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)
- * @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames)
- * @arg DCMI_FLAG_FNE: FIFO empty flag
+ * @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)
+ * @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames)
+ * @arg DCMI_FLAG_FNE: FIFO empty flag
* @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
* @arg DCMI_FLAG_OVRRI: Overrun flag mask
* @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
* @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
* @arg DCMI_FLAG_LINERI: Line flag mask
- * @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status
- * @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status
- * @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status
- * @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status
- * @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status
+ * @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status
+ * @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status
+ * @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status
+ * @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status
+ * @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status
* @retval The state of FLAG.
*/
#define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\
@@ -446,7 +458,7 @@
/**
* @brief Enable the specified DCMI interrupts.
* @param __HANDLE__ DCMI handle
- * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.
+ * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
* @arg DCMI_IT_OVF: Overflow interrupt mask
@@ -460,7 +472,7 @@
/**
* @brief Disable the specified DCMI interrupts.
* @param __HANDLE__ DCMI handle
- * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.
+ * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
* @arg DCMI_IT_OVF: Overflow interrupt mask
@@ -488,7 +500,7 @@
/**
* @}
*/
-
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DCMI_Exported_Functions DCMI Exported Functions
* @{
@@ -500,26 +512,26 @@
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
-void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);
-void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
+void HAL_DCMI_MspInit(DCMI_HandleTypeDef *hdcmi);
+void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef *hdcmi);
/* Callbacks Register/UnRegister functions ***********************************/
-#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
/**
* @}
*/
-
+
/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
-HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);
-HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi);
-HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi);
+HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
@@ -528,7 +540,7 @@
/**
* @}
*/
-
+
/** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
@@ -536,11 +548,12 @@
HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask);
/**
* @}
*/
-
+
/** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions
* @{
*/
@@ -562,41 +575,41 @@
* @{
*/
#define DCMI_MIS_INDEX ((uint32_t)0x1000) /*!< DCMI MIS register index */
-#define DCMI_SR_INDEX ((uint32_t)0x2000) /*!< DCMI SR register index */
+#define DCMI_SR_INDEX ((uint32_t)0x2000) /*!< DCMI SR register index */
/**
* @}
- */
+ */
/* Private macro -------------------------------------------------------------*/
/** @defgroup DCMI_Private_Macros DCMI Private Macros
* @{
*/
#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
((MODE) == DCMI_MODE_SNAPSHOT))
-
+
#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
((MODE) == DCMI_SYNCHRO_EMBEDDED))
-
+
#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
((POLARITY) == DCMI_PCKPOLARITY_RISING))
-
+
#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
((POLARITY) == DCMI_VSPOLARITY_HIGH))
-
+
#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
((POLARITY) == DCMI_HSPOLARITY_HIGH))
-
+
#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
((JPEG_MODE) == DCMI_JPEG_ENABLE))
-
+
#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME) || \
((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
-
+
#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B) || \
((DATA) == DCMI_EXTEND_DATA_10B) || \
((DATA) == DCMI_EXTEND_DATA_12B) || \
((DATA) == DCMI_EXTEND_DATA_14B))
-
+
#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
@@ -605,13 +618,13 @@
((MODE) == DCMI_BSM_OTHER) || \
((MODE) == DCMI_BSM_ALTERNATE_4) || \
((MODE) == DCMI_BSM_ALTERNATE_2))
-
+
#define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \
((POLARITY) == DCMI_OEBS_EVEN))
-
+
#define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \
((MODE) == DCMI_LSM_ALTERNATE_2))
-
+
#define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \
((POLARITY) == DCMI_OELS_EVEN))
@@ -623,23 +636,23 @@
/** @addtogroup DCMI_Private_Functions DCMI Private Functions
* @{
*/
-
+
/**
* @}
*/
-
+
/**
* @}
*/
/**
* @}
- */
+ */
#endif /* DCMI */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F7xx_HAL_DCMI_H */
+#endif /* STM32F7xx_HAL_DCMI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f7xx_hal_dcmi_ex.h b/Inc/stm32f7xx_hal_dcmi_ex.h
index b4ff34b..506ce46 100644
--- a/Inc/stm32f7xx_hal_dcmi_ex.h
+++ b/Inc/stm32f7xx_hal_dcmi_ex.h
@@ -24,11 +24,11 @@
/* Includes ------------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
diff --git a/Inc/stm32f7xx_hal_exti.h b/Inc/stm32f7xx_hal_exti.h
index 1d94a5f..e64414f 100644
--- a/Inc/stm32f7xx_hal_exti.h
+++ b/Inc/stm32f7xx_hal_exti.h
@@ -18,8 +18,8 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_EXTI_H
-#define __STM32F7xx_HAL_EXTI_H
+#ifndef STM32F7xx_HAL_EXTI_H
+#define STM32F7xx_HAL_EXTI_H
#ifdef __cplusplus
extern "C" {
@@ -38,14 +38,13 @@
*/
/* Exported types ------------------------------------------------------------*/
+
/** @defgroup EXTI_Exported_Types EXTI Exported Types
* @{
*/
typedef enum
{
- HAL_EXTI_COMMON_CB_ID = 0x00U,
- HAL_EXTI_RISING_CB_ID = 0x01U,
- HAL_EXTI_FALLING_CB_ID = 0x02U,
+ HAL_EXTI_COMMON_CB_ID = 0x00U
} EXTI_CallbackIDTypeDef;
/**
@@ -68,6 +67,9 @@
This parameter can be a combination of @ref EXTI_Mode */
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
can be a value of @ref EXTI_Trigger */
+ uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
+ This parameter is only possible for line 0 to 15. It
+ can be a value of @ref EXTI_GPIOSel */
} EXTI_ConfigTypeDef;
/**
@@ -82,48 +84,36 @@
/** @defgroup EXTI_Line EXTI Line
* @{
*/
-#define EXTI_LINE_0 EXTI_IMR_IM0 /*!< External interrupt line 0 */
-#define EXTI_LINE_1 EXTI_IMR_IM1 /*!< External interrupt line 1 */
-#define EXTI_LINE_2 EXTI_IMR_IM2 /*!< External interrupt line 2 */
-#define EXTI_LINE_3 EXTI_IMR_IM3 /*!< External interrupt line 3 */
-#define EXTI_LINE_4 EXTI_IMR_IM4 /*!< External interrupt line 4 */
-#define EXTI_LINE_5 EXTI_IMR_IM5 /*!< External interrupt line 5 */
-#define EXTI_LINE_6 EXTI_IMR_IM6 /*!< External interrupt line 6 */
-#define EXTI_LINE_7 EXTI_IMR_IM7 /*!< External interrupt line 7 */
-#define EXTI_LINE_8 EXTI_IMR_IM8 /*!< External interrupt line 8 */
-#define EXTI_LINE_9 EXTI_IMR_IM9 /*!< External interrupt line 9 */
-#define EXTI_LINE_10 EXTI_IMR_IM10 /*!< External interrupt line 10 */
-#define EXTI_LINE_11 EXTI_IMR_IM11 /*!< External interrupt line 11 */
-#define EXTI_LINE_12 EXTI_IMR_IM12 /*!< External interrupt line 12 */
-#define EXTI_LINE_13 EXTI_IMR_IM13 /*!< External interrupt line 13 */
-#define EXTI_LINE_14 EXTI_IMR_IM14 /*!< External interrupt line 14 */
-#define EXTI_LINE_15 EXTI_IMR_IM15 /*!< External interrupt line 15 */
-#if defined(EXTI_IMR_IM16)
-#define EXTI_LINE_16 EXTI_IMR_IM16 /*!< External interrupt line 16 Connected to the PVD Output */
-#endif /* EXTI_IMR_IM16 */
-#if defined(EXTI_IMR_IM17)
-#define EXTI_LINE_17 EXTI_IMR_IM17 /*!< External interrupt line 17 Connected to the RTC Alarm event */
-#endif /* EXTI_IMR_IM17 */
-#if defined(EXTI_IMR_IM18)
-#define EXTI_LINE_18 EXTI_IMR_IM18 /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
-#endif /* EXTI_IMR_IM18 */
-#if defined(EXTI_IMR_IM19)
-#define EXTI_LINE_19 EXTI_IMR_IM19 /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
-#endif /* EXTI_IMR_IM19 */
-#if defined(EXTI_IMR_IM20)
-#define EXTI_LINE_20 EXTI_IMR_IM20 /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
-#endif /* EXTI_IMR_IM20 */
-#if defined(EXTI_IMR_IM21)
-#define EXTI_LINE_21 EXTI_IMR_IM21 /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
-#endif /* EXTI_IMR_IM21 */
-#if defined(EXTI_IMR_IM22)
-#define EXTI_LINE_22 EXTI_IMR_IM22 /*!< External interrupt line 22 Connected to the RTC Wakeup event */
-#endif /* EXTI_IMR_IM22 */
-#if defined(EXTI_IMR_IM23)
-#define EXTI_LINE_23 EXTI_IMR_IM23 /*!< External interrupt line 23 Connected to the LPTIM Wakeup event */
-#endif /* EXTI_IMR_IM23 */
+#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */
+#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */
+#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */
+#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */
+#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */
+#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */
+#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */
+#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */
+#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */
+#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */
+#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */
+#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */
+#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */
+#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */
+#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */
+#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */
+#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */
+#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
+#if defined(ETH)
+#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
+#else
+#define EXTI_LINE_19 (EXTI_RESERVED | 0x13u) /*!< No interrupt supported in this line */
+#endif /* ETH */
+#define EXTI_LINE_20 (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
+#define EXTI_LINE_21 (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
+#define EXTI_LINE_22 (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the RTC Wakeup event */
+#define EXTI_LINE_23 (EXTI_CONFIG | 0x17u) /*!< External interrupt line 23 Connected to the LPTIM Wakeup event */
#if defined(EXTI_IMR_IM24)
-#define EXTI_LINE_24 EXTI_IMR_IM24 /*!< External interrupt line 24 Connected to the MDIO Slave global Interrupt Wakeup event */
+#define EXTI_LINE_24 (EXTI_CONFIG | 0x18u) /*!< External interrupt line 24 Connected to the MDIO Slave global Interrupt Wakeup event */
#endif /* EXTI_IMR_IM24 */
/**
* @}
@@ -142,6 +132,7 @@
/** @defgroup EXTI_Trigger EXTI Trigger
* @{
*/
+
#define EXTI_TRIGGER_NONE 0x00000000u
#define EXTI_TRIGGER_RISING 0x00000001u
#define EXTI_TRIGGER_FALLING 0x00000002u
@@ -150,6 +141,24 @@
* @}
*/
+/** @defgroup EXTI_GPIOSel EXTI GPIOSel
+ * @brief
+ * @{
+ */
+#define EXTI_GPIOA 0x00000000u
+#define EXTI_GPIOB 0x00000001u
+#define EXTI_GPIOC 0x00000002u
+#define EXTI_GPIOD 0x00000003u
+#define EXTI_GPIOE 0x00000004u
+#define EXTI_GPIOF 0x00000005u
+#define EXTI_GPIOG 0x00000006u
+#define EXTI_GPIOH 0x00000007u
+#define EXTI_GPIOI 0x00000008u
+#define EXTI_GPIOJ 0x00000009u
+#if defined (GPIOK)
+#define EXTI_GPIOK 0x0000000Au
+#endif /* GPIOK */
+
/**
* @}
*/
@@ -168,6 +177,20 @@
* @{
*/
/**
+ * @brief EXTI Line property definition
+ */
+#define EXTI_PROPERTY_SHIFT 24u
+#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
+#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO)
+
+/**
+ * @brief EXTI bit usage
+ */
+#define EXTI_PIN_MASK 0x0000001Fu
+
+/**
* @brief EXTI Mask for interrupt & event mode
*/
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
@@ -175,12 +198,17 @@
/**
* @brief EXTI Mask for trigger possibilities
*/
-#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING | EXTI_TRIGGER_RISING_FALLING)
+#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @brief EXTI Line number
*/
+#if defined(EXTI_IMR_IM24)
#define EXTI_LINE_NB 25u
+#else
+#define EXTI_LINE_NB 24u
+#endif /* EXTI_IMR_IM24 */
+
/**
* @}
@@ -190,16 +218,47 @@
/** @defgroup EXTI_Private_Macros EXTI Private Macros
* @{
*/
-#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~EXTI_IMR_IM) == 0x00U) && (__LINE__))
+#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
+ ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
+ (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
+ (((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
-#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & ~EXTI_MODE_MASK) == 0x00U))
+#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \
+ (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))
-#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)
+#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
#define IS_EXTI_PENDING_EDGE(__LINE__) (((__LINE__) == EXTI_TRIGGER_FALLING) || \
((__LINE__) == EXTI_TRIGGER_RISING) || \
((__LINE__) == EXTI_TRIGGER_RISING_FALLING))
+#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
+
+#if defined (GPIOK)
+#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
+ ((__PORT__) == EXTI_GPIOB) || \
+ ((__PORT__) == EXTI_GPIOC) || \
+ ((__PORT__) == EXTI_GPIOD) || \
+ ((__PORT__) == EXTI_GPIOE) || \
+ ((__PORT__) == EXTI_GPIOF) || \
+ ((__PORT__) == EXTI_GPIOG) || \
+ ((__PORT__) == EXTI_GPIOH) || \
+ ((__PORT__) == EXTI_GPIOI) || \
+ ((__PORT__) == EXTI_GPIOJ) || \
+ ((__PORT__) == EXTI_GPIOK))
+#else
+#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
+ ((__PORT__) == EXTI_GPIOB) || \
+ ((__PORT__) == EXTI_GPIOC) || \
+ ((__PORT__) == EXTI_GPIOD) || \
+ ((__PORT__) == EXTI_GPIOE) || \
+ ((__PORT__) == EXTI_GPIOF) || \
+ ((__PORT__) == EXTI_GPIOG) || \
+ ((__PORT__) == EXTI_GPIOH) || \
+ ((__PORT__) == EXTI_GPIOI) || \
+ ((__PORT__) == EXTI_GPIOJ))
+#endif /* GPIOK */
+
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U)
/**
* @}
@@ -255,6 +314,6 @@
}
#endif
-#endif /* __STM32F7xx_HAL_EXTI_H */
+#endif /* STM32F7xx_HAL_EXTI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f7xx_hal_gpio.h b/Inc/stm32f7xx_hal_gpio.h
index 78f1b7c..46a6498 100644
--- a/Inc/stm32f7xx_hal_gpio.h
+++ b/Inc/stm32f7xx_hal_gpio.h
@@ -262,7 +262,7 @@
* @{
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
-#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00))
+#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U))
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
((MODE) == GPIO_MODE_OUTPUT_PP) ||\
((MODE) == GPIO_MODE_OUTPUT_OD) ||\
diff --git a/Inc/stm32f7xx_hal_hash.h b/Inc/stm32f7xx_hal_hash.h
index 3cf5c25..93177b7 100644
--- a/Inc/stm32f7xx_hal_hash.h
+++ b/Inc/stm32f7xx_hal_hash.h
@@ -152,6 +152,8 @@
__IO uint32_t ErrorCode; /*!< HASH Error code */
+ __IO uint32_t Accumulation; /*!< HASH multi buffers accumulation flag */
+
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
void (* InCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH input completion callback */
@@ -226,11 +228,11 @@
/** @defgroup HASH_flags_definition HASH flags definitions
* @{
*/
-#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : a new block can be entered in the IP */
-#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
-#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
-#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */
-#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : the input buffer contains at least one word of data */
+#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : a new block can be entered in the Peripheral */
+#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
+#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
+#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */
+#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : the input buffer contains at least one word of data */
/**
* @}
@@ -276,7 +278,7 @@
*/
/** @brief Check whether or not the specified HASH flag is set.
- * @param __FLAG__: specifies the flag to check.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
* @arg @ref HASH_FLAG_DCIS Digest calculation complete.
@@ -291,7 +293,7 @@
/** @brief Clear the specified HASH flag.
- * @param __FLAG__: specifies the flag to clear.
+ * @param __FLAG__ specifies the flag to clear.
* This parameter can be one of the following values:
* @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
* @arg @ref HASH_FLAG_DCIS Digest calculation complete
@@ -301,7 +303,7 @@
/** @brief Enable the specified HASH interrupt.
- * @param __INTERRUPT__: specifies the HASH interrupt source to enable.
+ * @param __INTERRUPT__ specifies the HASH interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
* @arg @ref HASH_IT_DCI Digest calculation complete
@@ -310,7 +312,7 @@
#define __HAL_HASH_ENABLE_IT(__INTERRUPT__) SET_BIT(HASH->IMR, (__INTERRUPT__))
/** @brief Disable the specified HASH interrupt.
- * @param __INTERRUPT__: specifies the HASH interrupt source to disable.
+ * @param __INTERRUPT__ specifies the HASH interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
* @arg @ref HASH_IT_DCI Digest calculation complete
@@ -319,7 +321,7 @@
#define __HAL_HASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(HASH->IMR, (__INTERRUPT__))
/** @brief Reset HASH handle state.
- * @param __HANDLE__: HASH handle.
+ * @param __HANDLE__ HASH handle.
* @retval None
*/
@@ -335,7 +337,7 @@
/** @brief Reset HASH handle status.
- * @param __HANDLE__: HASH handle.
+ * @param __HANDLE__ HASH handle.
* @retval None
*/
#define __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK)
@@ -362,7 +364,7 @@
/**
* @brief Set the number of valid bits in the last word written in data register DIN.
- * @param __SIZE__: size in bytes of last data written in Data register.
+ * @param __SIZE__ size in bytes of last data written in Data register.
* @retval None
*/
#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U))
@@ -397,7 +399,7 @@
/**
* @brief Ensure that HASH input data type is valid.
- * @param __DATATYPE__: HASH input data type.
+ * @param __DATATYPE__ HASH input data type.
* @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
*/
#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
@@ -405,21 +407,11 @@
((__DATATYPE__) == HASH_DATATYPE_8B) || \
((__DATATYPE__) == HASH_DATATYPE_1B))
-
-
-/**
- * @brief Ensure that input data buffer size is valid for multi-buffer HASH
- * processing in polling mode.
- * @note This check is valid only for multi-buffer HASH processing in polling mode.
- * @param __SIZE__: input data buffer size.
- * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
- */
-#define IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__) (((__SIZE__) % 4U) == 0U)
/**
* @brief Ensure that input data buffer size is valid for multi-buffer HASH
* processing in DMA mode.
* @note This check is valid only for multi-buffer HASH processing in DMA mode.
- * @param __SIZE__: input data buffer size.
+ * @param __SIZE__ input data buffer size.
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
*/
#define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == 0U) || (((__SIZE__) % 4U) == 0U))
@@ -428,21 +420,21 @@
* @brief Ensure that input data buffer size is valid for multi-buffer HMAC
* processing in DMA mode.
* @note This check is valid only for multi-buffer HMAC processing in DMA mode.
- * @param __HANDLE__: HASH handle.
- * @param __SIZE__: input data buffer size.
+ * @param __HANDLE__ HASH handle.
+ * @param __SIZE__ input data buffer size.
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
*/
#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4U) == 0U))
/**
* @brief Ensure that handle phase is set to HASH processing.
- * @param __HANDLE__: HASH handle.
+ * @param __HANDLE__ HASH handle.
* @retval SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing)
*/
#define IS_HASH_PROCESSING(__HANDLE__) ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)
/**
* @brief Ensure that handle phase is set to HMAC processing.
- * @param __HANDLE__: HASH handle.
+ * @param __HANDLE__ HASH handle.
* @retval SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing)
*/
#define IS_HMAC_PROCESSING(__HANDLE__) (((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \
@@ -492,8 +484,11 @@
/* HASH processing using polling *********************************************/
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+
/**
* @}
@@ -505,7 +500,11 @@
/* HASH processing using IT **************************************************/
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
/**
* @}
@@ -591,6 +590,7 @@
/* Private functions */
HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
diff --git a/Inc/stm32f7xx_hal_hash_ex.h b/Inc/stm32f7xx_hal_hash_ex.h
index 6c0fc99..60717df 100644
--- a/Inc/stm32f7xx_hal_hash_ex.h
+++ b/Inc/stm32f7xx_hal_hash_ex.h
@@ -52,9 +52,11 @@
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
/**
* @}
@@ -65,7 +67,11 @@
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
/**
* @}
diff --git a/Inc/stm32f7xx_hal_hcd.h b/Inc/stm32f7xx_hal_hcd.h
index 7488da7..28c578e 100644
--- a/Inc/stm32f7xx_hal_hcd.h
+++ b/Inc/stm32f7xx_hal_hcd.h
@@ -108,9 +108,10 @@
/** @defgroup HCD_Speed HCD Speed
* @{
*/
-#define HCD_SPEED_HIGH 0U
-#define HCD_SPEED_LOW 2U
-#define HCD_SPEED_FULL 3U
+#define HCD_SPEED_HIGH USBH_HS_SPEED
+#define HCD_SPEED_FULL USBH_FSLS_SPEED
+#define HCD_SPEED_LOW USBH_FSLS_SPEED
+
/**
* @}
*/
@@ -169,19 +170,15 @@
/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
-HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num,
- uint8_t epnum,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps);
+HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
+ uint8_t epnum, uint8_t dev_address,
+ uint8_t speed, uint8_t ep_type, uint16_t mps);
-HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
-void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
+void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition
@@ -190,14 +187,14 @@
*/
typedef enum
{
- HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */
- HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */
- HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */
- HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */
- HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */
+ HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */
+ HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */
+ HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */
+ HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */
+ HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */
- HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */
- HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */
+ HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */
+ HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */
} HAL_HCD_CallbackIDTypeDef;
/**
@@ -231,25 +228,20 @@
/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
-HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num,
- uint8_t direction,
- uint8_t ep_type,
- uint8_t token,
- uint8_t *pbuff,
- uint16_t length,
- uint8_t do_ping);
+HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
+ uint8_t direction, uint8_t ep_type,
+ uint8_t token, uint8_t *pbuff,
+ uint16_t length, uint8_t do_ping);
/* Non-Blocking mode: Interrupt */
-void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
- uint8_t chnum,
- HCD_URBStateTypeDef urb_state);
+void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum,
+ HCD_URBStateTypeDef urb_state);
/**
* @}
*/
@@ -258,9 +250,9 @@
/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
-HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
/**
* @}
*/
@@ -271,8 +263,8 @@
*/
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
/**
diff --git a/Inc/stm32f7xx_hal_i2c_ex.h b/Inc/stm32f7xx_hal_i2c_ex.h
index f377d81..f45be67 100644
--- a/Inc/stm32f7xx_hal_i2c_ex.h
+++ b/Inc/stm32f7xx_hal_i2c_ex.h
@@ -167,6 +167,9 @@
(((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))
#endif /* SYSCFG_PMC_I2C1_FMP && SYSCFG_PMC_I2C2_FMP && SYSCFG_PMC_I2C3_FMP && SYSCFG_PMC_I2C4_FMP */
+
+
+
/**
* @}
*/
diff --git a/Inc/stm32f7xx_hal_irda.h b/Inc/stm32f7xx_hal_irda.h
index f382d73..09baf21 100644
--- a/Inc/stm32f7xx_hal_irda.h
+++ b/Inc/stm32f7xx_hal_irda.h
@@ -434,8 +434,8 @@
*/
/**
- * @}
- */
+ * @}
+ */
/* Exported macros -----------------------------------------------------------*/
/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
@@ -465,10 +465,10 @@
* @retval None
*/
#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \
- do{ \
- SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
- SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
- } while(0U)
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
+ SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
+ } while(0U)
/** @brief Clear the specified IRDA pending flag.
* @param __HANDLE__ specifies the IRDA Handle.
@@ -582,7 +582,8 @@
* @arg @ref IRDA_IT_PE Parity Error interrupt
* @retval The new state of __IT__ (SET or RESET).
*/
-#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)
+#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
+ & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified IRDA interrupt source is enabled or not.
* @param __HANDLE__ specifies the IRDA Handle.
@@ -597,8 +598,8 @@
* @retval The new state of __IT__ (SET or RESET).
*/
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
- (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
- (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
+ (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the IRDA Handle.
@@ -636,7 +637,8 @@
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
-#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
+ &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
/** @brief Enable UART/USART associated to IRDA Handle.
* @param __HANDLE__ specifies the IRDA Handle.
@@ -683,7 +685,8 @@
* @param __MODE__ IRDA communication mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
-#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
+#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\
+ & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
/** @brief Ensure that IRDA power mode is valid.
* @param __MODE__ IRDA power mode.
@@ -735,8 +738,8 @@
((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
/**
- * @}
- */
+ * @}
+ */
/* Include IRDA HAL Extended module */
#include "stm32f7xx_hal_irda_ex.h"
@@ -758,7 +761,8 @@
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
-HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
+ pIRDA_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
diff --git a/Inc/stm32f7xx_hal_irda_ex.h b/Inc/stm32f7xx_hal_irda_ex.h
index 247cb74..7e95fd6 100644
--- a/Inc/stm32f7xx_hal_irda_ex.h
+++ b/Inc/stm32f7xx_hal_irda_ex.h
@@ -32,7 +32,8 @@
* @{
*/
-/** @addtogroup IRDAEx
+/** @defgroup IRDAEx IRDAEx
+ * @brief IRDA Extended HAL module driver
* @{
*/
@@ -73,8 +74,8 @@
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
break; \
@@ -90,12 +91,12 @@
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
@@ -111,12 +112,12 @@
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
- switch(__HAL_RCC_GET_USART3_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
@@ -132,12 +133,12 @@
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == UART4) \
{ \
- switch(__HAL_RCC_GET_UART4_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_UART4_SOURCE()) \
+ { \
case RCC_UART4CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
@@ -153,12 +154,12 @@
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if ((__HANDLE__)->Instance == UART5) \
{ \
- switch(__HAL_RCC_GET_UART5_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_UART5_SOURCE()) \
+ { \
case RCC_UART5CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
@@ -174,12 +175,12 @@
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART6) \
{ \
- switch(__HAL_RCC_GET_USART6_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART6_SOURCE()) \
+ { \
case RCC_USART6CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
break; \
@@ -195,12 +196,12 @@
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if ((__HANDLE__)->Instance == UART7) \
{ \
- switch(__HAL_RCC_GET_UART7_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_UART7_SOURCE()) \
+ { \
case RCC_UART7CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
@@ -216,12 +217,12 @@
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if ((__HANDLE__)->Instance == UART8) \
{ \
- switch(__HAL_RCC_GET_UART8_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_UART8_SOURCE()) \
+ { \
case RCC_UART8CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
@@ -237,7 +238,7 @@
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else \
{ \
@@ -252,44 +253,44 @@
*/
#define IRDA_MASK_COMPUTATION(__HANDLE__) \
do { \
- if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
- { \
- if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
- { \
+ if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
+ { \
(__HANDLE__)->Mask = 0x01FFU ; \
- } \
- else \
- { \
+ } \
+ else \
+ { \
(__HANDLE__)->Mask = 0x00FFU ; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
- { \
- if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
- { \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
+ { \
(__HANDLE__)->Mask = 0x00FFU ; \
- } \
- else \
- { \
+ } \
+ else \
+ { \
(__HANDLE__)->Mask = 0x007FU ; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
- { \
- if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
- { \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
+ { \
(__HANDLE__)->Mask = 0x007FU ; \
- } \
- else \
- { \
+ } \
+ else \
+ { \
(__HANDLE__)->Mask = 0x003FU ; \
- } \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x0000U; \
- } \
-} while(0U)
+ } \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x0000U; \
+ } \
+ } while(0U)
/** @brief Ensure that IRDA frame length is valid.
* @param __LENGTH__ IRDA frame length.
diff --git a/Inc/stm32f7xx_hal_lptim.h b/Inc/stm32f7xx_hal_lptim.h
index f2faade..9241b88 100644
--- a/Inc/stm32f7xx_hal_lptim.h
+++ b/Inc/stm32f7xx_hal_lptim.h
@@ -15,14 +15,14 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_LPTIM_H
-#define __STM32F7xx_HAL_LPTIM_H
+#ifndef STM32F7xx_HAL_LPTIM_H
+#define STM32F7xx_HAL_LPTIM_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -32,26 +32,20 @@
* @{
*/
-/** @defgroup LPTIM LPTIM
- * @brief LPTIM HAL module driver
+#if defined (LPTIM1)
+
+/** @addtogroup LPTIM
* @{
*/
-
-/* Exported types ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
/** @defgroup LPTIM_Exported_Types LPTIM Exported Types
* @{
*/
+#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR_MR23 /*!< External interrupt line 23 Connected to the LPTIM EXTI Line */
-/** @defgroup LPTIM_WAKEUPTIMER_EXTILINE LPTIM WAKEUP Timer EXTI Line
- * @{
- */
-#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR23) /*!< External interrupt line 23 Connected to the LPTIM EXTI Line */
/**
- * @}
- */
-
-/**
- * @brief LPTIM Clock configuration definition
+ * @brief LPTIM Clock configuration definition
*/
typedef struct
{
@@ -60,11 +54,11 @@
uint32_t Prescaler; /*!< Specifies the counter clock Prescaler.
This parameter can be a value of @ref LPTIM_Clock_Prescaler */
-
-}LPTIM_ClockConfigTypeDef;
-/**
- * @brief LPTIM Clock configuration definition
+} LPTIM_ClockConfigTypeDef;
+
+/**
+ * @brief LPTIM Clock configuration definition
*/
typedef struct
{
@@ -73,92 +67,97 @@
Note: This parameter is used only when Ultra low power clock source is used.
Note: If the polarity is configured on 'both edges', an auxiliary clock
(one of the Low power oscillator) must be active.
- This parameter can be a value of @ref LPTIM_Clock_Polarity */
-
+ This parameter can be a value of @ref LPTIM_Clock_Polarity */
+
uint32_t SampleTime; /*!< Selects the clock sampling time to configure the clock glitch filter.
Note: This parameter is used only when Ultra low power clock source is used.
- This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
-
-}LPTIM_ULPClockConfigTypeDef;
+ This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
-/**
- * @brief LPTIM Trigger configuration definition
+} LPTIM_ULPClockConfigTypeDef;
+
+/**
+ * @brief LPTIM Trigger configuration definition
*/
typedef struct
{
uint32_t Source; /*!< Selects the Trigger source.
This parameter can be a value of @ref LPTIM_Trigger_Source */
-
+
uint32_t ActiveEdge; /*!< Selects the Trigger active edge.
Note: This parameter is used only when an external trigger is used.
This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
-
+
uint32_t SampleTime; /*!< Selects the trigger sampling time to configure the clock glitch filter.
Note: This parameter is used only when an external trigger is used.
- This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */
-}LPTIM_TriggerConfigTypeDef;
+ This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */
+} LPTIM_TriggerConfigTypeDef;
-/**
- * @brief LPTIM Initialization Structure definition
+/**
+ * @brief LPTIM Initialization Structure definition
*/
typedef struct
-{
+{
LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */
-
+
LPTIM_ULPClockConfigTypeDef UltraLowPowerClock; /*!< Specifies the Ultra Low Power clock parameters */
-
+
LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */
-
+
uint32_t OutputPolarity; /*!< Specifies the Output polarity.
This parameter can be a value of @ref LPTIM_Output_Polarity */
-
- uint32_t UpdateMode; /*!< Specifies whether the update of the autorelaod and the compare
+
+ uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare
values is done immediately or after the end of current period.
This parameter can be a value of @ref LPTIM_Updating_Mode */
uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event
or each external event.
- This parameter can be a value of @ref LPTIM_Counter_Source */
-
-}LPTIM_InitTypeDef;
+ This parameter can be a value of @ref LPTIM_Counter_Source */
+} LPTIM_InitTypeDef;
-/**
- * @brief HAL LPTIM State structure definition
- */
-typedef enum __HAL_LPTIM_StateTypeDef
+/**
+ * @brief HAL LPTIM State structure definition
+ */
+typedef enum
{
HAL_LPTIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
HAL_LPTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_LPTIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
- HAL_LPTIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
- HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */
-}HAL_LPTIM_StateTypeDef;
+ HAL_LPTIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
+ HAL_LPTIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
+ HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */
+} HAL_LPTIM_StateTypeDef;
-/**
- * @brief LPTIM handle Structure definition
- */
+/**
+ * @brief LPTIM handle Structure definition
+ */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
typedef struct __LPTIM_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
{
- LPTIM_TypeDef *Instance; /*!< Register base address */
- LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */
- HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */
- HAL_LockTypeDef Lock; /*!< LPTIM locking object */
- __IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */
+ LPTIM_TypeDef *Instance; /*!< Register base address */
+
+ LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */
+
+ HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */
+
+ HAL_LockTypeDef Lock; /*!< LPTIM locking object */
+
+ __IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
- void (* MspInitCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Msp Init Callback */
- void (* MspDeInitCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Msp DeInit Callback */
-
- void (* CompareMatchCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Compare Match Callback */
- void (* AutoReloadMatchCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Auto Reload Match Callback */
- void (* TriggerCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Trigger Callback */
- void (* CompareWriteCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Compare Write Callback */
- void (* AutoReloadWriteCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Auto Reload Write Callback */
- void (* DirectionUpCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Direction Up Callback */
- void (* DirectionDownCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Direction Down Callback */
+ void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp Init Callback */
+ void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp DeInit Callback */
+ void (* CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare match Callback */
+ void (* AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload match Callback */
+ void (* TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< External trigger event detection Callback */
+ void (* CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare register write complete Callback */
+ void (* AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload register write complete Callback */
+ void (* DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Up-counting direction change Callback */
+ void (* DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Down-counting direction change Callback */
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-
-}LPTIM_HandleTypeDef;
+} LPTIM_HandleTypeDef;
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
/**
@@ -166,28 +165,26 @@
*/
typedef enum
{
- HAL_LPTIM_MSPINIT_CB_ID = 0x00U, /*!< LPTIM MspInit Callback ID */
- HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, /*!< LPTIM MspDeInit Callback ID */
-
- HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, /*!< LPTIM Compare Match Callback ID */
- HAL_LPTIM_AUTO_RELOAD_MATCH_CB_ID = 0x03U, /*!< LPTIM Auto Reload Match Callback ID */
- HAL_LPTIM_TRIGGER_CB_ID = 0x04U, /*!< LPTIM Trigger Callback ID */
- HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, /*!< LPTIM Compare Write Callback ID */
- HAL_LPTIM_AUTO_RELOAD_WRITE_CB_ID = 0x06U, /*!< LPTIM Auto Reload Write Callback ID */
- HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U, /*!< LPTIM Direction Up Callback ID */
- HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U, /*!< LPTIM Direction Down Callback ID */
-}HAL_LPTIM_CallbackIDTypeDef;
+ HAL_LPTIM_MSPINIT_CB_ID = 0x00U, /*!< LPTIM Base Msp Init Callback ID */
+ HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, /*!< LPTIM Base Msp DeInit Callback ID */
+ HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, /*!< Compare match Callback ID */
+ HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U, /*!< Auto-reload match Callback ID */
+ HAL_LPTIM_TRIGGER_CB_ID = 0x04U, /*!< External trigger event detection Callback ID */
+ HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, /*!< Compare register write complete Callback ID */
+ HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U, /*!< Auto-reload register write complete Callback ID */
+ HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U, /*!< Up-counting direction change Callback ID */
+ HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U, /*!< Down-counting direction change Callback ID */
+} HAL_LPTIM_CallbackIDTypeDef;
/**
- * @brief HAL LPTIM Callback pointer definition
+ * @brief HAL TIM Callback pointer definition
*/
-typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< pointer to the LPTIM callback function */
+typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< pointer to the LPTIM callback function */
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-
/**
* @}
- */
+ */
/* Exported constants --------------------------------------------------------*/
/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
@@ -197,33 +194,33 @@
/** @defgroup LPTIM_Clock_Source LPTIM Clock Source
* @{
*/
-#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00U)
-#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
-/**
+#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U
+#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
+/**
* @}
*/
/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
* @{
*/
-#define LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000U)
+#define LPTIM_PRESCALER_DIV1 0x00000000U
#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
-#define LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))
+#define LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)
#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
-#define LPTIM_PRESCALER_DIV32 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))
-#define LPTIM_PRESCALER_DIV64 ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))
-#define LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFGR_PRESC)
+#define LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)
+#define LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)
+#define LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC
/**
* @}
- */
+ */
/** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
* @{
*/
-#define LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000U)
-#define LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL)
+#define LPTIM_OUTPUTPOLARITY_HIGH 0x00000000U
+#define LPTIM_OUTPUTPOLARITY_LOW LPTIM_CFGR_WAVPOL
/**
* @}
*/
@@ -231,10 +228,10 @@
/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
* @{
*/
-#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)
-#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
-#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
-#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U
+#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
+#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
+#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
/**
* @}
*/
@@ -242,10 +239,9 @@
/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
* @{
*/
-
-#define LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000U)
-#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
-#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
+#define LPTIM_CLOCKPOLARITY_RISING 0x00000000U
+#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
+#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
/**
* @}
*/
@@ -253,13 +249,13 @@
/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
* @{
*/
-#define LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFFU)
-#define LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000U)
-#define LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0)
+#define LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU
+#define LPTIM_TRIGSOURCE_0 0x00000000U
+#define LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0
#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
-#define LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
+#define LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
-#define LPTIM_TRIGSOURCE_5 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
+#define LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
/**
* @}
*/
@@ -277,7 +273,7 @@
/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
* @{
*/
-#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U
#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT
@@ -289,7 +285,7 @@
* @{
*/
-#define LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000U)
+#define LPTIM_UPDATE_IMMEDIATE 0x00000000U
#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
/**
* @}
@@ -299,13 +295,13 @@
* @{
*/
-#define LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000U)
+#define LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U
#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE
/**
* @}
*/
-
-/** @defgroup LPTIM_Flag_Definition LPTIM Flag Definition
+
+/** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition
* @{
*/
@@ -323,7 +319,6 @@
/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
* @{
*/
-
#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE
#define LPTIM_IT_UP LPTIM_IER_UPIE
#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE
@@ -339,54 +334,79 @@
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
* @{
*/
-/** @brief Reset LPTIM handle state
+/** @brief Reset LPTIM handle state.
* @param __HANDLE__ LPTIM handle
* @retval None
*/
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
/**
- * @brief Enable/Disable the LPTIM peripheral.
+ * @brief Enable the LPTIM peripheral.
* @param __HANDLE__ LPTIM handle
* @retval None
*/
-#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
-#define __HAL_LPTIM_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE))
+#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
/**
- * @brief Starts the LPTIM peripheral in Continuous or in single mode.
- * @param __HANDLE__ DMA handle
+ * @brief Disable the LPTIM peripheral.
+ * @param __HANDLE__ LPTIM handle
+ * @note The following sequence is required to solve LPTIM disable HW limitation.
+ * Please check Errata Sheet ES0335 for more details under "MCU may remain
+ * stuck in LPTIM interrupt when entering Stop mode" section.
+ * @note Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to
+ * check for TIMEOUT.
+ * @retval None
+ */
+#define __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__)
+
+/**
+ * @brief Start the LPTIM peripheral in Continuous mode.
+ * @param __HANDLE__ LPTIM handle
* @retval None
*/
#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
-#define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
-
-
/**
- * @brief Writes the passed parameter in the Autoreload register.
+ * @brief Start the LPTIM peripheral in single mode.
* @param __HANDLE__ LPTIM handle
- * @param __VALUE__ Autoreload value
* @retval None
*/
+#define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
+
+/**
+ * @brief Write the passed parameter in the Autoreload register.
+ * @param __HANDLE__ LPTIM handle
+ * @param __VALUE__ Autoreload value
+ * @retval None
+ * @note The ARR register can only be modified when the LPTIM instance is enabled.
+ */
#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
/**
- * @brief Writes the passed parameter in the Compare register.
+ * @brief Write the passed parameter in the Compare register.
* @param __HANDLE__ LPTIM handle
- * @param __VALUE__ Compare value
+ * @param __VALUE__ Compare value
* @retval None
+ * @note The CMP register can only be modified when the LPTIM instance is enabled.
*/
#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
/**
- * @brief Checks whether the specified LPTIM flag is set or not.
+ * @brief Check whether the specified LPTIM flag is set or not.
* @param __HANDLE__ LPTIM handle
- * @param __FLAG__ LPTIM flag to check
+ * @param __FLAG__ LPTIM flag to check
* This parameter can be a value of:
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
@@ -400,9 +420,9 @@
#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
/**
- * @brief Clears the specified LPTIM flag.
+ * @brief Clear the specified LPTIM flag.
* @param __HANDLE__ LPTIM handle.
- * @param __FLAG__ LPTIM flag to clear.
+ * @param __FLAG__ LPTIM flag to clear.
* This parameter can be a value of:
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
@@ -413,12 +433,12 @@
* @arg LPTIM_FLAG_CMPM : Compare match Flag.
* @retval None.
*/
-#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/**
* @brief Enable the specified LPTIM interrupt.
- * @param __HANDLE__ LPTIM handle.
- * @param __INTERRUPT__ LPTIM interrupt to set.
+ * @param __HANDLE__ LPTIM handle.
+ * @param __INTERRUPT__ LPTIM interrupt to set.
* This parameter can be a value of:
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
@@ -428,13 +448,14 @@
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
* @retval None.
+ * @note The LPTIM interrupts can only be enabled when the LPTIM instance is disabled.
*/
-#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
- /**
+/**
* @brief Disable the specified LPTIM interrupt.
- * @param __HANDLE__ LPTIM handle.
- * @param __INTERRUPT__ LPTIM interrupt to set.
+ * @param __HANDLE__ LPTIM handle.
+ * @param __INTERRUPT__ LPTIM interrupt to set.
* This parameter can be a value of:
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
@@ -444,13 +465,14 @@
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
* @retval None.
+ * @note The LPTIM interrupts can only be disabled when the LPTIM instance is disabled.
*/
-#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
+#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
- /**
- * @brief Checks whether the specified LPTIM interrupt is set or not.
- * @param __HANDLE__ LPTIM handle.
- * @param __INTERRUPT__ LPTIM interrupt to check.
+/**
+ * @brief Check whether the specified LPTIM interrupt source is enabled or not.
+ * @param __HANDLE__ LPTIM handle.
+ * @param __INTERRUPT__ LPTIM interrupt to check.
* This parameter can be a value of:
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
@@ -461,7 +483,7 @@
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
* @retval Interrupt status.
*/
-
+
#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/**
@@ -489,7 +511,7 @@
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
/**
- * @brief Enable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
+ * @brief Enable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
@@ -522,7 +544,6 @@
/**
* @brief Disable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
- * This parameter can be:
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\
@@ -550,12 +571,16 @@
/**
* @}
*/
-
+
/* Exported functions --------------------------------------------------------*/
/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
* @{
*/
+/** @addtogroup LPTIM_Exported_Functions_Group1
+ * @brief Initialization and Configuration functions.
+ * @{
+ */
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
@@ -563,7 +588,14 @@
/* MSP functions *************************************************************/
void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
+/**
+ * @}
+ */
+/** @addtogroup LPTIM_Exported_Functions_Group2
+ * @brief Start-Stop operation functions.
+ * @{
+ */
/* Start/Stop operation functions *********************************************/
/* ################################# PWM Mode ################################*/
/* Blocking mode: Polling */
@@ -612,12 +644,26 @@
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+/**
+ * @}
+ */
+/** @addtogroup LPTIM_Exported_Functions_Group3
+ * @brief Read operation functions.
+ * @{
+ */
/* Reading operation functions ************************************************/
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
+/**
+ * @}
+ */
+/** @addtogroup LPTIM_Exported_Functions_Group4
+ * @brief LPTIM IRQ handler and callback functions.
+ * @{
+ */
/* LPTIM IRQ functions *******************************************************/
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
@@ -632,17 +678,27 @@
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+/** @addtogroup LPTIM_Group5
+ * @brief Peripheral State functions.
+ * @{
+ */
/* Peripheral State functions ************************************************/
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
+/**
+ * @}
+ */
/**
* @}
*/
-
+
/* Private types -------------------------------------------------------------*/
/** @defgroup LPTIM_Private_Types LPTIM Private Types
* @{
@@ -650,16 +706,16 @@
/**
* @}
- */
+ */
/* Private variables ---------------------------------------------------------*/
/** @defgroup LPTIM_Private_Variables LPTIM Private Variables
* @{
*/
-
+
/**
* @}
- */
+ */
/* Private constants ---------------------------------------------------------*/
/** @defgroup LPTIM_Private_Constants LPTIM Private Constants
@@ -668,94 +724,97 @@
/**
* @}
- */
+ */
/* Private macros ------------------------------------------------------------*/
/** @defgroup LPTIM_Private_Macros LPTIM Private Macros
* @{
*/
-
-#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
- ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
-
-#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \
- ((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \
- ((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \
- ((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || \
- ((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || \
- ((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || \
- ((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || \
- ((__PRESCALER__) == LPTIM_PRESCALER_DIV128))
-#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
-#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
- ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
-
-#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
- ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || \
- ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || \
- ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
+#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
+ ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
-#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || \
- ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
- ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
-#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
- ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
- ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
- ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
- ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
- ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
- ((__TRIG__) == LPTIM_TRIGSOURCE_5))
+#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV128))
-#define IS_LPTIM_EXT_TRG_POLARITY(__POLAR__) (((__POLAR__) == LPTIM_ACTIVEEDGE_RISING ) || \
- ((__POLAR__) == LPTIM_ACTIVEEDGE_FALLING ) || \
- ((__POLAR__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
+#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
-#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
- ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \
- ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \
- ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS ))
+#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
+ ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
-#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
- ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
+#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
+ ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || \
+ ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || \
+ ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
-#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
- ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
+#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || \
+ ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
+ ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
-#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFU)
+#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_5))
-#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFU)
-
-#define IS_LPTIM_PERIOD(PERIOD) ((PERIOD) <= 0x0000FFFFU)
+#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING ) || \
+ ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING ) || \
+ ((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
-#define IS_LPTIM_PULSE(PULSE) ((PULSE) <= 0x0000FFFFU)
+#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
+ ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \
+ ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \
+ ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS ))
+
+#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
+ ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
+
+#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
+ ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
+
+#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFUL)
+
+#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)
+
+#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFFUL)
+
+#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL)
/**
* @}
- */
+ */
/* Private functions ---------------------------------------------------------*/
/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
* @{
*/
-
+void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim);
/**
* @}
*/
-
-/**
- * @}
- */
/**
* @}
- */
-
+ */
+
+#endif /* LPTIM1 */
+/**
+ * @}
+ */
+
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F7xx_HAL_LPTIM_H */
+#endif /* STM32F7xx_HAL_LPTIM_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f7xx_hal_mmc.h b/Inc/stm32f7xx_hal_mmc.h
index 0850b6a..2d3878f 100644
--- a/Inc/stm32f7xx_hal_mmc.h
+++ b/Inc/stm32f7xx_hal_mmc.h
@@ -12,14 +12,16 @@
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_MMC_H
-#define __STM32F7xx_HAL_MMC_H
+#ifndef STM32F7xx_HAL_MMC_H
+#define STM32F7xx_HAL_MMC_H
+
+#if defined(SDMMC1)
#ifdef __cplusplus
extern "C" {
@@ -46,14 +48,14 @@
*/
typedef enum
{
- HAL_MMC_STATE_RESET = ((uint32_t)0x00000000U), /*!< MMC not yet initialized or disabled */
- HAL_MMC_STATE_READY = ((uint32_t)0x00000001U), /*!< MMC initialized and ready for use */
- HAL_MMC_STATE_TIMEOUT = ((uint32_t)0x00000002U), /*!< MMC Timeout state */
- HAL_MMC_STATE_BUSY = ((uint32_t)0x00000003U), /*!< MMC process ongoing */
- HAL_MMC_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< MMC Programming State */
- HAL_MMC_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< MMC Receinving State */
- HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< MMC Transfert State */
- HAL_MMC_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< MMC is in error state */
+ HAL_MMC_STATE_RESET = 0x00000000U, /*!< MMC not yet initialized or disabled */
+ HAL_MMC_STATE_READY = 0x00000001U, /*!< MMC initialized and ready for use */
+ HAL_MMC_STATE_TIMEOUT = 0x00000002U, /*!< MMC Timeout state */
+ HAL_MMC_STATE_BUSY = 0x00000003U, /*!< MMC process ongoing */
+ HAL_MMC_STATE_PROGRAMMING = 0x00000004U, /*!< MMC Programming State */
+ HAL_MMC_STATE_RECEIVING = 0x00000005U, /*!< MMC Receinving State */
+ HAL_MMC_STATE_TRANSFER = 0x00000006U, /*!< MMC Transfert State */
+ HAL_MMC_STATE_ERROR = 0x0000000FU /*!< MMC is in error state */
}HAL_MMC_StateTypeDef;
/**
* @}
@@ -62,18 +64,17 @@
/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure
* @{
*/
-typedef enum
-{
- HAL_MMC_CARD_READY = ((uint32_t)0x00000001U), /*!< Card state is ready */
- HAL_MMC_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), /*!< Card is in identification state */
- HAL_MMC_CARD_STANDBY = ((uint32_t)0x00000003U), /*!< Card is in standby state */
- HAL_MMC_CARD_TRANSFER = ((uint32_t)0x00000004U), /*!< Card is in transfer state */
- HAL_MMC_CARD_SENDING = ((uint32_t)0x00000005U), /*!< Card is sending an operation */
- HAL_MMC_CARD_RECEIVING = ((uint32_t)0x00000006U), /*!< Card is receiving operation information */
- HAL_MMC_CARD_PROGRAMMING = ((uint32_t)0x00000007U), /*!< Card is in programming state */
- HAL_MMC_CARD_DISCONNECTED = ((uint32_t)0x00000008U), /*!< Card is disconnected */
- HAL_MMC_CARD_ERROR = ((uint32_t)0x000000FFU) /*!< Card response Error */
-}HAL_MMC_CardStateTypeDef;
+typedef uint32_t HAL_MMC_CardStateTypeDef;
+
+#define HAL_MMC_CARD_READY 0x00000001U /*!< Card state is ready */
+#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */
+#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */
+#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */
+#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */
+#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */
+#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */
+#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */
+#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error */
/**
* @}
*/
@@ -114,23 +115,23 @@
typedef struct
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
{
- MMC_TypeDef *Instance; /*!< MMC registers base address */
+ MMC_TypeDef *Instance; /*!< MMC registers base address */
- MMC_InitTypeDef Init; /*!< MMC required parameters */
+ MMC_InitTypeDef Init; /*!< MMC required parameters */
HAL_LockTypeDef Lock; /*!< MMC locking object */
- uint32_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
+ uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
uint32_t TxXferSize; /*!< MMC Tx Transfer size */
- uint32_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */
+ uint8_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */
uint32_t RxXferSize; /*!< MMC Rx Transfer size */
__IO uint32_t Context; /*!< MMC transfer context */
- __IO HAL_MMC_StateTypeDef State; /*!< MMC card State */
+ __IO HAL_MMC_StateTypeDef State; /*!< MMC card State */
__IO uint32_t ErrorCode; /*!< MMC Card Error codes */
@@ -138,13 +139,13 @@
DMA_HandleTypeDef *hdmatx; /*!< MMC Tx DMA handle parameters */
- HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */
+ HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */
- uint32_t CSD[4]; /*!< MMC card specific data table */
+ uint32_t CSD[4U]; /*!< MMC card specific data table */
- uint32_t CID[4]; /*!< MMC card identification number table */
-
- #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ uint32_t CID[4U]; /*!< MMC card identification number table */
+
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
void (* TxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
void (* RxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
void (* ErrorCallback) (struct __MMC_HandleTypeDef *hmmc);
@@ -193,7 +194,7 @@
__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
__IO uint8_t Reserved3; /*!< Reserved */
__IO uint8_t ContentProtectAppli; /*!< Content protection application */
- __IO uint8_t FileFormatGrouop; /*!< File format group */
+ __IO uint8_t FileFormatGroup; /*!< File format group */
__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
__IO uint8_t PermWrProtect; /*!< Permanent write protection */
__IO uint8_t TempWrProtect; /*!< Temporary write protection */
@@ -227,8 +228,9 @@
/**
* @}
*/
+
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
-/** @defgroup MMC_Exported_Types_Group6 MMC Callback ID enumeration definition
+/** @defgroup MMC_Exported_Types_Group6 MMC Callback ID enumeration definition
* @{
*/
typedef enum
@@ -241,15 +243,15 @@
HAL_MMC_MSP_INIT_CB_ID = 0x10U, /*!< MMC MspInit Callback ID */
HAL_MMC_MSP_DEINIT_CB_ID = 0x11U /*!< MMC MspDeInit Callback ID */
}HAL_MMC_CallbackIDTypeDef;
-/**
+/**
* @}
*/
-/** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition
+/** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition
* @{
*/
typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
-/**
+/**
* @}
*/
#endif
@@ -262,8 +264,7 @@
* @{
*/
-#define BLOCKSIZE ((uint32_t)512U) /*!< Block size is 512 bytes */
-#define CAPACITY ((uint32_t)0x80000000U) /*!< 2 G bytes constant */
+#define MMC_BLOCKSIZE 512U /*!< Block size is 512 bytes */
/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition
* @{
@@ -304,6 +305,7 @@
#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
+
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
#endif
@@ -314,13 +316,13 @@
/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration
* @{
*/
-#define MMC_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */
-#define MMC_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */
-#define MMC_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */
-#define MMC_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */
-#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */
-#define MMC_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */
-#define MMC_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */
+#define MMC_CONTEXT_NONE 0x00000000U /*!< None */
+#define MMC_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
+#define MMC_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
+#define MMC_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
+#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
+#define MMC_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
+#define MMC_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
/**
* @}
@@ -344,8 +346,9 @@
/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards
* @{
*/
-#define MMC_HIGH_VOLTAGE_CARD ((uint32_t)0x00000000U)
-#define MMC_DUAL_VOLTAGE_CARD ((uint32_t)0x00000001U)
+#define MMC_LOW_CAPACITY_CARD 0x00000000U /*!< MMC Card Capacity <=2Gbytes */
+#define MMC_HIGH_CAPACITY_CARD 0x00000001U /*!< MMC Card Capacity >2Gbytes and <2Tbytes */
+
/**
* @}
*/
@@ -399,8 +402,8 @@
/**
* @brief Enable the MMC device interrupt.
- * @param __HANDLE__ MMC Handle
- * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
+ * @param __HANDLE__: MMC Handle
+ * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -410,7 +413,7 @@
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
@@ -430,8 +433,8 @@
/**
* @brief Disable the MMC device interrupt.
- * @param __HANDLE__ MMC Handle
- * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
+ * @param __HANDLE__: MMC Handle
+ * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -441,7 +444,7 @@
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
@@ -461,8 +464,8 @@
/**
* @brief Check whether the specified MMC flag is set or not.
- * @param __HANDLE__ MMC Handle
- * @param __FLAG__ specifies the flag to check.
+ * @param __HANDLE__: MMC Handle
+ * @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@@ -472,7 +475,7 @@
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDMMC_FLAG_CMDACT: Command transfer in progress
* @arg SDMMC_FLAG_TXACT: Data transmit in progress
@@ -492,8 +495,8 @@
/**
* @brief Clear the MMC's pending flags.
- * @param __HANDLE__ MMC Handle
- * @param __FLAG__ specifies the flag to clear.
+ * @param __HANDLE__: MMC Handle
+ * @param __FLAG__: specifies the flag to clear.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@@ -503,7 +506,7 @@
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
* @retval None
@@ -512,8 +515,8 @@
/**
* @brief Check whether the specified MMC interrupt has occurred or not.
- * @param __HANDLE__ MMC Handle
- * @param __INTERRUPT__ specifies the SDMMC interrupt source to check.
+ * @param __HANDLE__: MMC Handle
+ * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
* This parameter can be one of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -523,7 +526,7 @@
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
@@ -537,14 +540,14 @@
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
- * @retval The new state of SD IT (SET or RESET).
+ * @retval The new state of MMC IT (SET or RESET).
*/
#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Clear the MMC's interrupt pending bits.
- * @param __HANDLE__ MMC Handle
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * @param __HANDLE__: MMC Handle
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -554,7 +557,12 @@
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
+ * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
* @retval None
*/
@@ -577,6 +585,7 @@
HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc);
void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc);
void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
+
/**
* @}
*/
@@ -624,9 +633,9 @@
* @{
*/
HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc);
-HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
-HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
-HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
+HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
+HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
+HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
/**
* @}
*/
@@ -725,12 +734,12 @@
* @}
*/
-
#ifdef __cplusplus
}
#endif
+#endif /* SDMMC1 */
-#endif /* __STM32F7xx_HAL_MMC_H */
+#endif /* STM32F7xx_HAL_MMC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f7xx_hal_pcd.h b/Inc/stm32f7xx_hal_pcd.h
index 4afcf41..650dfd5 100644
--- a/Inc/stm32f7xx_hal_pcd.h
+++ b/Inc/stm32f7xx_hal_pcd.h
@@ -96,16 +96,16 @@
typedef struct
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
- PCD_TypeDef *Instance; /*!< Register base address */
- PCD_InitTypeDef Init; /*!< PCD required parameters */
- __IO uint8_t USB_Address; /*!< USB Address */
- PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
- PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
- HAL_LockTypeDef Lock; /*!< PCD peripheral status */
- __IO PCD_StateTypeDef State; /*!< PCD communication state */
- __IO uint32_t ErrorCode; /*!< PCD Error code */
- uint32_t Setup[12]; /*!< Setup packet buffer */
- PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
+ PCD_TypeDef *Instance; /*!< Register base address */
+ PCD_InitTypeDef Init; /*!< PCD required parameters */
+ __IO uint8_t USB_Address; /*!< USB Address */
+ PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
+ PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
+ HAL_LockTypeDef Lock; /*!< PCD peripheral status */
+ __IO PCD_StateTypeDef State; /*!< PCD communication state */
+ __IO uint32_t ErrorCode; /*!< PCD Error code */
+ uint32_t Setup[12]; /*!< Setup packet buffer */
+ PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
uint32_t BESL;
@@ -148,9 +148,9 @@
/** @defgroup PCD_Speed PCD Speed
* @{
*/
-#define PCD_SPEED_HIGH 0U
-#define PCD_SPEED_HIGH_IN_FULL 1U
-#define PCD_SPEED_FULL 2U
+#define PCD_SPEED_HIGH USBD_HS_SPEED
+#define PCD_SPEED_HIGH_IN_FULL USBD_HSINFS_SPEED
+#define PCD_SPEED_FULL USBD_FS_SPEED
/**
* @}
*/
@@ -207,20 +207,20 @@
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
- do { \
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
+ do { \
EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \
- EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \
+ EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \
} while(0U)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
- do { \
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
+ do { \
EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
- EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
+ EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
} while(0U)
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
@@ -256,7 +256,7 @@
HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */
HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */
HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */
- HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
+ HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */
HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */
@@ -371,14 +371,6 @@
* @{
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U
-#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
-
-#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 0x08U
-#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
-#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
-
#define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */
#define USB_OTG_HS_WAKEUP_EXTI_LINE (0x1U << 20) /*!< USB HS EXTI Line WakeUp Interrupt */
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
diff --git a/Inc/stm32f7xx_hal_qspi.h b/Inc/stm32f7xx_hal_qspi.h
index 78de574..8d7f520 100644
--- a/Inc/stm32f7xx_hal_qspi.h
+++ b/Inc/stm32f7xx_hal_qspi.h
@@ -6,20 +6,20 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
+ * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_QSPI_H
-#define __STM32F7xx_HAL_QSPI_H
+#ifndef STM32F7xx_HAL_QSPI_H
+#define STM32F7xx_HAL_QSPI_H
#ifdef __cplusplus
extern "C" {
@@ -28,64 +28,58 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
+#if defined(QUADSPI)
+
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @addtogroup QSPI
* @{
- */
+ */
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/** @defgroup QSPI_Exported_Types QSPI Exported Types
* @{
*/
-
-/**
- * @brief QSPI Init structure definition
- */
+/**
+ * @brief QSPI Init structure definition
+ */
typedef struct
{
uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
- This parameter can be a number between 0 and 255 */
-
+ This parameter can be a number between 0 and 255 */
uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
This parameter can be a value between 1 and 32 */
-
- uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
+ uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
This parameter can be a value of @ref QSPI_SampleShifting */
-
- uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
- required to address the flash memory. The flash capacity can be up to 4GB
- (addressed using 32 bits) in indirect mode, but the addressable space in
+ uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
+ required to address the flash memory. The flash capacity can be up to 4GB
+ (addressed using 32 bits) in indirect mode, but the addressable space in
memory-mapped mode is limited to 256MB
This parameter can be a number between 0 and 31 */
-
- uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
+ uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
of clock cycles which the chip select must remain high between commands.
- This parameter can be a value of @ref QSPI_ChipSelectHighTime */
-
+ This parameter can be a value of @ref QSPI_ChipSelectHighTime */
uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
This parameter can be a value of @ref QSPI_ClockMode */
-
uint32_t FlashID; /* Specifies the Flash which will be used,
This parameter can be a value of @ref QSPI_Flash_Select */
-
uint32_t DualFlash; /* Specifies the Dual Flash Mode State
- This parameter can be a value of @ref QSPI_DualFlash_Mode */
+ This parameter can be a value of @ref QSPI_DualFlash_Mode */
}QSPI_InitTypeDef;
-/**
- * @brief HAL QSPI State structures definition
- */
+/**
+ * @brief HAL QSPI State structures definition
+ */
typedef enum
{
HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */
HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */
- HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */
- HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */
+ HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */
+ HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */
HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */
HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */
HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */
@@ -93,9 +87,9 @@
HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */
}HAL_QSPI_StateTypeDef;
-/**
- * @brief QSPI Handle Structure definition
- */
+/**
+ * @brief QSPI Handle Structure definition
+ */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
typedef struct __QSPI_HandleTypeDef
#else
@@ -132,8 +126,8 @@
#endif
}QSPI_HandleTypeDef;
-/**
- * @brief QSPI Command structure definition
+/**
+ * @brief QSPI Command structure definition
*/
typedef struct
{
@@ -157,26 +151,26 @@
This parameter can be a value of @ref QSPI_AlternateBytesMode */
uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
This parameter can be a value of @ref QSPI_DataMode */
- uint32_t NbData; /* Specifies the number of data to transfer.
- This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
+ uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes)
+ This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
until end of memory)*/
uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
This parameter can be a value of @ref QSPI_DdrMode */
- uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
- system clock in DDR mode.
+ uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data
+ output by one half of system clock in DDR mode.
This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
- uint32_t SIOOMode; /* Specifies the send instruction only once mode
+ uint32_t SIOOMode; /* Specifies the send instruction only once mode
This parameter can be a value of @ref QSPI_SIOOMode */
}QSPI_CommandTypeDef;
-/**
- * @brief QSPI Auto Polling mode configuration structure definition
+/**
+ * @brief QSPI Auto Polling mode configuration structure definition
*/
typedef struct
{
uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
This parameter can be any value between 0 and 0xFFFFFFFF */
- uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
+ uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
This parameter can be any value between 0 and 0xFFFFFFFF */
uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
This parameter can be any value between 0 and 0xFFFF */
@@ -187,15 +181,15 @@
uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
This parameter can be a value of @ref QSPI_AutomaticStop */
}QSPI_AutoPollingTypeDef;
-
-/**
- * @brief QSPI Memory Mapped mode configuration structure definition
+
+/**
+ * @brief QSPI Memory Mapped mode configuration structure definition
*/
typedef struct
{
uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
This parameter can be any value between 0 and 0xFFFF */
- uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select.
+ uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select.
This parameter can be a value of @ref QSPI_TimeOutActivation */
}QSPI_MemoryMappedTypeDef;
@@ -233,41 +227,42 @@
/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
* @{
*/
+
/** @defgroup QSPI_ErrorCode QSPI Error Code
* @{
- */
-#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
-#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */
-#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */
-#define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */
+ */
+#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */
+#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */
+#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */
+#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */
#endif
/**
* @}
- */
-
+ */
+
/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
* @{
*/
-#define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!<No clock cycle shift to sample data*/
-#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
+#define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/
+#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
/**
* @}
- */
+ */
-/** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time
+/** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
* @{
*/
-#define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000U) /*!<nCS stay high for at least 1 clock cycle between commands*/
-#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
-#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
-#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
-#define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/
-#define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
-#define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
-#define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/
+#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/
/**
* @}
*/
@@ -275,45 +270,45 @@
/** @defgroup QSPI_ClockMode QSPI Clock Mode
* @{
*/
-#define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U) /*!<Clk stays low while nCS is released*/
-#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
+#define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/
+#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
/**
* @}
*/
-
+
/** @defgroup QSPI_Flash_Select QSPI Flash Select
* @{
*/
-#define QSPI_FLASH_ID_1 ((uint32_t)0x00000000U)
-#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL)
+#define QSPI_FLASH_ID_1 0x00000000U /*!<FLASH 1 selected*/
+#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/
/**
* @}
- */
+ */
- /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
+ /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
* @{
*/
-#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM)
-#define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000U)
+#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/
+#define QSPI_DUALFLASH_DISABLE 0x00000000U /*!<Dual-flash mode disabled*/
/**
* @}
- */
+ */
-/** @defgroup QSPI_AddressSize QSPI Address Size
+/** @defgroup QSPI_AddressSize QSPI Address Size
* @{
*/
-#define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U) /*!<8-bit address*/
+#define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/
#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/
/**
* @}
- */
+ */
/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
* @{
*/
-#define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U) /*!<8-bit alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/
@@ -324,7 +319,7 @@
/** @defgroup QSPI_InstructionMode QSPI Instruction Mode
* @{
*/
-#define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U) /*!<No instruction*/
+#define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/
#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/
@@ -335,58 +330,58 @@
/** @defgroup QSPI_AddressMode QSPI Address Mode
* @{
*/
-#define QSPI_ADDRESS_NONE ((uint32_t)0x00000000U) /*!<No address*/
+#define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/
#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/
/**
* @}
- */
+ */
-/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
-* @{
+/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
+* @{
*/
-#define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U) /*!<No alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/
#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/
/**
* @}
- */
+ */
/** @defgroup QSPI_DataMode QSPI Data Mode
* @{
*/
-#define QSPI_DATA_NONE ((uint32_t)0X00000000) /*!<No data*/
+#define QSPI_DATA_NONE 0x00000000U /*!<No data*/
#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/
/**
* @}
- */
+ */
-/** @defgroup QSPI_DdrMode QSPI Ddr Mode
+/** @defgroup QSPI_DdrMode QSPI DDR Mode
* @{
*/
-#define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000U) /*!<Double data rate mode disabled*/
-#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
+#define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/
+#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
/**
* @}
*/
-/** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle
+/** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay
* @{
*/
-#define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000U) /*!<Delay the data output using analog delay in DDR mode*/
-#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
+#define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/
+#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by one half of system clock in DDR mode*/
/**
* @}
*/
-/** @defgroup QSPI_SIOOMode QSPI SIOO Mode
+/** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
* @{
*/
-#define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U) /*!<Send instruction on every transaction*/
+#define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/
#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
/**
* @}
@@ -395,31 +390,31 @@
/** @defgroup QSPI_MatchMode QSPI Match Mode
* @{
*/
-#define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000U) /*!<AND match mode between unmasked bits*/
-#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
+#define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/
+#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
/**
* @}
- */
+ */
/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
* @{
*/
-#define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U) /*!<AutoPolling stops only with abort or QSPI disabling*/
-#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
+#define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/
+#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
/**
* @}
- */
+ */
-/** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation
+/** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
* @{
*/
-#define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U) /*!<Timeout counter disabled, nCS remains active*/
-#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
+#define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/
+#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
/**
* @}
- */
+ */
-/** @defgroup QSPI_Flags QSPI Flags
+/** @defgroup QSPI_Flags QSPI Flags
* @{
*/
#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
@@ -432,26 +427,27 @@
* @}
*/
-/** @defgroup QSPI_Interrupts QSPI Interrupts
+/** @defgroup QSPI_Interrupts QSPI Interrupts
* @{
- */
-#define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
-#define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
-#define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
-#define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
-#define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
+ */
+#define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
+#define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
+#define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
+#define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
+#define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
/**
* @}
*/
/** @defgroup QSPI_Timeout_definition QSPI Timeout definition
+ * @brief QSPI Timeout definition
* @{
- */
-#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
+ */
+#define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */
/**
* @}
- */
-
+ */
+
/**
* @}
*/
@@ -460,9 +456,8 @@
/** @defgroup QSPI_Exported_Macros QSPI Exported Macros
* @{
*/
-
-/** @brief Reset QSPI handle state
- * @param __HANDLE__ QSPI handle.
+/** @brief Reset QSPI handle state.
+ * @param __HANDLE__ : QSPI handle.
* @retval None
*/
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
@@ -475,23 +470,23 @@
#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
#endif
-/** @brief Enable QSPI
- * @param __HANDLE__ specifies the QSPI Handle.
+/** @brief Enable the QSPI peripheral.
+ * @param __HANDLE__ : specifies the QSPI Handle.
* @retval None
- */
+ */
#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
-/** @brief Disable QSPI
- * @param __HANDLE__ specifies the QSPI Handle.
+/** @brief Disable the QSPI peripheral.
+ * @param __HANDLE__ : specifies the QSPI Handle.
* @retval None
*/
#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
-/** @brief Enables the specified QSPI interrupt.
- * @param __HANDLE__ specifies the QSPI Handle.
- * @param __INTERRUPT__ specifies the QSPI interrupt source to enable.
+/** @brief Enable the specified QSPI interrupt.
+ * @param __HANDLE__ : specifies the QSPI Handle.
+ * @param __INTERRUPT__ : specifies the QSPI interrupt source to enable.
* This parameter can be one of the following values:
- * @arg QSPI_IT_TO: QSPI Time out interrupt
+ * @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
@@ -501,9 +496,9 @@
#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
-/** @brief Disables the specified QSPI interrupt.
- * @param __HANDLE__ specifies the QSPI Handle.
- * @param __INTERRUPT__ specifies the QSPI interrupt source to disable.
+/** @brief Disable the specified QSPI interrupt.
+ * @param __HANDLE__ : specifies the QSPI Handle.
+ * @param __INTERRUPT__ : specifies the QSPI interrupt source to disable.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
@@ -514,39 +509,39 @@
*/
#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
-/** @brief Checks whether the specified QSPI interrupt source is enabled.
- * @param __HANDLE__ specifies the QSPI Handle.
- * @param __INTERRUPT__ specifies the QSPI interrupt source to check.
+/** @brief Check whether the specified QSPI interrupt source is enabled or not.
+ * @param __HANDLE__ : specifies the QSPI Handle.
+ * @param __INTERRUPT__ : specifies the QSPI interrupt source to check.
* This parameter can be one of the following values:
- * @arg QSPI_IT_TO: QSPI Time out interrupt
+ * @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
* @arg QSPI_IT_TE: QSPI Transfer error interrupt
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
/**
- * @brief Get the selected QSPI's flag status.
- * @param __HANDLE__ specifies the QSPI Handle.
- * @param __FLAG__ specifies the QSPI flag to check.
+ * @brief Check whether the selected QSPI flag is set or not.
+ * @param __HANDLE__ : specifies the QSPI Handle.
+ * @param __FLAG__ : specifies the QSPI flag to check.
* This parameter can be one of the following values:
* @arg QSPI_FLAG_BUSY: QSPI Busy flag
- * @arg QSPI_FLAG_TO: QSPI Time out flag
+ * @arg QSPI_FLAG_TO: QSPI Timeout flag
* @arg QSPI_FLAG_SM: QSPI Status match flag
* @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
* @arg QSPI_FLAG_TE: QSPI Transfer error flag
* @retval None
*/
-#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
+#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
/** @brief Clears the specified QSPI's flag status.
- * @param __HANDLE__ specifies the QSPI Handle.
- * @param __FLAG__ specifies the QSPI clear register flag that needs to be set
+ * @param __HANDLE__ : specifies the QSPI Handle.
+ * @param __FLAG__ : specifies the QSPI clear register flag that needs to be set
* This parameter can be one of the following values:
- * @arg QSPI_FLAG_TO: QSPI Time out flag
+ * @arg QSPI_FLAG_TO: QSPI Timeout flag
* @arg QSPI_FLAG_SM: QSPI Status match flag
* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
* @arg QSPI_FLAG_TE: QSPI Transfer error flag
@@ -556,7 +551,7 @@
/**
* @}
*/
-
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup QSPI_Exported_Functions
* @{
@@ -576,7 +571,7 @@
/** @addtogroup QSPI_Exported_Functions_Group2
* @{
- */
+ */
/* IO operation functions *****************************************************/
/* QSPI IRQ handler method */
void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
@@ -597,13 +592,7 @@
/* QSPI memory-mapped mode */
HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
-/**
- * @}
- */
-/** @addtogroup QSPI_Exported_Functions_Group3
- * @{
- */
/* Callback functions in non-blocking modes ***********************************/
void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi);
@@ -631,9 +620,9 @@
* @}
*/
-/** @addtogroup QSPI_Exported_Functions_Group4
+/** @addtogroup QSPI_Exported_Functions_Group3
* @{
- */
+ */
/* Peripheral Control and State functions ************************************/
HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
@@ -642,6 +631,7 @@
void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
+HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID);
/**
* @}
*/
@@ -649,161 +639,100 @@
/**
* @}
*/
+/* End of exported functions -------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup QSPI_Private_Macros QSPI Private Macros
* @{
*/
-/** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler
- * @{
- */
-#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF)
+#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
+
+#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U))
+
+#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
+ ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
+
+#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U))
+
+#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
+
+#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
+ ((CLKMODE) == QSPI_CLOCK_MODE_3))
+
+#define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \
+ ((FLASH_ID) == QSPI_FLASH_ID_2))
+
+#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
+ ((MODE) == QSPI_DUALFLASH_DISABLE))
+
+#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU)
+
+#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
+ ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
+ ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
+ ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
+
+#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
+ ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
+ ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
+ ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
+
+#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U)
+
+#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
+ ((MODE) == QSPI_INSTRUCTION_1_LINE) || \
+ ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
+ ((MODE) == QSPI_INSTRUCTION_4_LINES))
+
+#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
+ ((MODE) == QSPI_ADDRESS_1_LINE) || \
+ ((MODE) == QSPI_ADDRESS_2_LINES) || \
+ ((MODE) == QSPI_ADDRESS_4_LINES))
+
+#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
+ ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
+ ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
+ ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
+
+#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
+ ((MODE) == QSPI_DATA_1_LINE) || \
+ ((MODE) == QSPI_DATA_2_LINES) || \
+ ((MODE) == QSPI_DATA_4_LINES))
+
+#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
+ ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
+
+#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
+ ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
+
+#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
+ ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
+
+#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
+
+#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
+
+#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
+ ((MODE) == QSPI_MATCH_MODE_OR))
+
+#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
+ ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
+
+#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
+ ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
+
+#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
/**
- * @}
- */
-
-/** @defgroup QSPI_FifoThreshold QSPI Fifo Threshold
- * @{
- */
-#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 32))
-/**
- * @}
- */
-
-#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
- ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
-
-/** @defgroup QSPI_FlashSize QSPI Flash Size
- * @{
- */
-#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31))
-/**
- * @}
- */
-
-#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
-
-#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
- ((CLKMODE) == QSPI_CLOCK_MODE_3))
-
-#define IS_QSPI_FLASH_ID(FLA) (((FLA) == QSPI_FLASH_ID_1) || \
- ((FLA) == QSPI_FLASH_ID_2))
-
-#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
- ((MODE) == QSPI_DUALFLASH_DISABLE))
-
-
-/** @defgroup QSPI_Instruction QSPI Instruction
- * @{
- */
-#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF)
-/**
- * @}
- */
-
-#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
- ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
- ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
- ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
-
-#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
- ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
- ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
- ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
-
-
-/** @defgroup QSPI_DummyCycles QSPI Dummy Cycles
- * @{
- */
-#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31)
-/**
- * @}
- */
-
-#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
- ((MODE) == QSPI_INSTRUCTION_1_LINE) || \
- ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
- ((MODE) == QSPI_INSTRUCTION_4_LINES))
-
-#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
- ((MODE) == QSPI_ADDRESS_1_LINE) || \
- ((MODE) == QSPI_ADDRESS_2_LINES) || \
- ((MODE) == QSPI_ADDRESS_4_LINES))
-
-#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
- ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
- ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
- ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
-
-#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
- ((MODE) == QSPI_DATA_1_LINE) || \
- ((MODE) == QSPI_DATA_2_LINES) || \
- ((MODE) == QSPI_DATA_4_LINES))
-
-#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
- ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
-
-#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
- ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
-
-#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
- ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
-
-/** @defgroup QSPI_Interval QSPI Interval
- * @{
- */
-#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
-/**
- * @}
- */
-
-/** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size
- * @{
- */
-#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4))
-/**
- * @}
- */
-#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
- ((MODE) == QSPI_MATCH_MODE_OR))
-
-#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
- ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
-
-#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
- ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
-
-/** @defgroup QSPI_TimeOutPeriod QSPI TimeOut Period
- * @{
- */
-#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF)
-/**
- * @}
- */
-
-#define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_BUSY) || \
- ((FLAG) == QSPI_FLAG_TO) || \
- ((FLAG) == QSPI_FLAG_SM) || \
- ((FLAG) == QSPI_FLAG_FT) || \
- ((FLAG) == QSPI_FLAG_TC) || \
- ((FLAG) == QSPI_FLAG_TE))
-
-#define IS_QSPI_IT(IT) ((((IT) & (uint32_t)0xFFE0FFFFU) == 0x00000000U) && ((IT) != 0x00000000U))
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup QSPI_Private_Functions QSPI Private Functions
- * @{
- */
+* @}
+*/
+/* End of private macros -----------------------------------------------------*/
/**
* @}
@@ -811,16 +740,14 @@
/**
* @}
- */
+ */
-/**
- * @}
- */
-
+#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */
+
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F7xx_HAL_QSPI_H */
+#endif /* STM32F7xx_HAL_QSPI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f7xx_hal_sai.h b/Inc/stm32f7xx_hal_sai.h
index 5e384b9..3a32096 100644
--- a/Inc/stm32f7xx_hal_sai.h
+++ b/Inc/stm32f7xx_hal_sai.h
@@ -97,9 +97,10 @@
uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling.
This parameter can be a value of @ref SAI_Audio_Frequency */
- uint32_t Mckdiv; /*!< Specifies the master clock divider, the parameter will be used if for
- AudioFrequency the user choice
- This parameter must be a number between Min_Data = 0 and Max_Data = 15 */
+ uint32_t Mckdiv; /*!< Specifies the master clock divider.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 15.
+ @note This parameter is used only if AudioFrequency is set to
+ SAI_AUDIO_FREQUENCY_MCKDIV otherwise it is internally computed. */
uint32_t MonoStereoMode; /*!< Specifies if the mono or stereo mode is selected.
This parameter can be a value of @ref SAI_Mono_Stereo_Mode */
@@ -841,7 +842,7 @@
#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
-#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15)
+#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15U)
#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))
diff --git a/Inc/stm32f7xx_hal_sd.h b/Inc/stm32f7xx_hal_sd.h
index d02e38e..305f83a 100644
--- a/Inc/stm32f7xx_hal_sd.h
+++ b/Inc/stm32f7xx_hal_sd.h
@@ -12,19 +12,21 @@
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_SD_H
-#define __STM32F7xx_HAL_SD_H
+#ifndef STM32F7xx_HAL_SD_H
+#define STM32F7xx_HAL_SD_H
#ifdef __cplusplus
extern "C" {
#endif
+#if defined(SDMMC1)
+
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_ll_sdmmc.h"
@@ -47,14 +49,14 @@
*/
typedef enum
{
- HAL_SD_STATE_RESET = ((uint32_t)0x00000000U), /*!< SD not yet initialized or disabled */
- HAL_SD_STATE_READY = ((uint32_t)0x00000001U), /*!< SD initialized and ready for use */
- HAL_SD_STATE_TIMEOUT = ((uint32_t)0x00000002U), /*!< SD Timeout state */
- HAL_SD_STATE_BUSY = ((uint32_t)0x00000003U), /*!< SD process ongoing */
- HAL_SD_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< SD Programming State */
- HAL_SD_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< SD Receinving State */
- HAL_SD_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< SD Transfert State */
- HAL_SD_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< SD is in error state */
+ HAL_SD_STATE_RESET = 0x00000000U, /*!< SD not yet initialized or disabled */
+ HAL_SD_STATE_READY = 0x00000001U, /*!< SD initialized and ready for use */
+ HAL_SD_STATE_TIMEOUT = 0x00000002U, /*!< SD Timeout state */
+ HAL_SD_STATE_BUSY = 0x00000003U, /*!< SD process ongoing */
+ HAL_SD_STATE_PROGRAMMING = 0x00000004U, /*!< SD Programming State */
+ HAL_SD_STATE_RECEIVING = 0x00000005U, /*!< SD Receiving State */
+ HAL_SD_STATE_TRANSFER = 0x00000006U, /*!< SD Transfert State */
+ HAL_SD_STATE_ERROR = 0x0000000FU /*!< SD is in error state */
}HAL_SD_StateTypeDef;
/**
* @}
@@ -63,18 +65,17 @@
/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
* @{
*/
-typedef enum
-{
- HAL_SD_CARD_READY = ((uint32_t)0x00000001U), /*!< Card state is ready */
- HAL_SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), /*!< Card is in identification state */
- HAL_SD_CARD_STANDBY = ((uint32_t)0x00000003U), /*!< Card is in standby state */
- HAL_SD_CARD_TRANSFER = ((uint32_t)0x00000004U), /*!< Card is in transfer state */
- HAL_SD_CARD_SENDING = ((uint32_t)0x00000005U), /*!< Card is sending an operation */
- HAL_SD_CARD_RECEIVING = ((uint32_t)0x00000006U), /*!< Card is receiving operation information */
- HAL_SD_CARD_PROGRAMMING = ((uint32_t)0x00000007U), /*!< Card is in programming state */
- HAL_SD_CARD_DISCONNECTED = ((uint32_t)0x00000008U), /*!< Card is disconnected */
- HAL_SD_CARD_ERROR = ((uint32_t)0x000000FFU) /*!< Card response Error */
-}HAL_SD_CardStateTypeDef;
+typedef uint32_t HAL_SD_CardStateTypeDef;
+
+#define HAL_SD_CARD_READY 0x00000001U /*!< Card state is ready */
+#define HAL_SD_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */
+#define HAL_SD_CARD_STANDBY 0x00000003U /*!< Card is in standby state */
+#define HAL_SD_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */
+#define HAL_SD_CARD_SENDING 0x00000005U /*!< Card is sending an operation */
+#define HAL_SD_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */
+#define HAL_SD_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */
+#define HAL_SD_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */
+#define HAL_SD_CARD_ERROR 0x000000FFU /*!< Card response Error */
/**
* @}
*/
@@ -111,7 +112,11 @@
/**
* @brief SD handle Structure definition
*/
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
typedef struct __SD_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
{
SD_TypeDef *Instance; /*!< SD registers base address */
@@ -119,11 +124,11 @@
HAL_LockTypeDef Lock; /*!< SD locking object */
- uint32_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */
+ uint8_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */
uint32_t TxXferSize; /*!< SD Tx Transfer size */
- uint32_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */
+ uint8_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */
uint32_t RxXferSize; /*!< SD Rx Transfer size */
@@ -133,9 +138,9 @@
__IO uint32_t ErrorCode; /*!< SD Card Error codes */
- DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
-
DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */
@@ -143,7 +148,7 @@
uint32_t CID[4]; /*!< SD card identification number table */
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
void (* TxCpltCallback) (struct __SD_HandleTypeDef *hsd);
void (* RxCpltCallback) (struct __SD_HandleTypeDef *hsd);
void (* ErrorCallback) (struct __SD_HandleTypeDef *hsd);
@@ -151,7 +156,7 @@
void (* MspInitCallback) (struct __SD_HandleTypeDef *hsd);
void (* MspDeInitCallback) (struct __SD_HandleTypeDef *hsd);
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}SD_HandleTypeDef;
/**
@@ -192,7 +197,7 @@
__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
__IO uint8_t Reserved3; /*!< Reserved */
__IO uint8_t ContentProtectAppli; /*!< Content protection application */
- __IO uint8_t FileFormatGrouop; /*!< File format group */
+ __IO uint8_t FileFormatGroup; /*!< File format group */
__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
__IO uint8_t PermWrProtect; /*!< Permanent write protection */
__IO uint8_t TempWrProtect; /*!< Temporary write protection */
@@ -200,7 +205,6 @@
__IO uint8_t ECC; /*!< ECC code */
__IO uint8_t CSD_CRC; /*!< CSD CRC */
__IO uint8_t Reserved4; /*!< Always 1 */
-
}HAL_SD_CardCSDTypeDef;
/**
* @}
@@ -248,7 +252,7 @@
* @}
*/
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition
* @{
*/
@@ -273,7 +277,7 @@
/**
* @}
*/
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -283,7 +287,7 @@
* @{
*/
-#define BLOCKSIZE ((uint32_t)512U) /*!< Block size is 512 bytes */
+#define BLOCKSIZE 512U /*!< Block size is 512 bytes */
/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition
* @{
@@ -325,10 +329,9 @@
#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
#define HAL_SD_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
-#endif
-
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -336,13 +339,13 @@
/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
* @{
*/
-#define SD_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */
-#define SD_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */
-#define SD_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */
-#define SD_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */
-#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */
-#define SD_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */
-#define SD_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */
+#define SD_CONTEXT_NONE 0x00000000U /*!< None */
+#define SD_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
+#define SD_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
+#define SD_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
+#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
+#define SD_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
+#define SD_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
/**
* @}
@@ -351,9 +354,9 @@
/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
* @{
*/
-#define CARD_SDSC ((uint32_t)0x00000000U)
-#define CARD_SDHC_SDXC ((uint32_t)0x00000001U)
-#define CARD_SECURED ((uint32_t)0x00000003U)
+#define CARD_SDSC 0x00000000U /*!< SD Standard Capacity <2Go */
+#define CARD_SDHC_SDXC 0x00000001U /*!< SD High Capacity <32Go, SD Extended Capacity <2To */
+#define CARD_SECURED 0x00000003U
/**
* @}
@@ -362,8 +365,8 @@
/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
* @{
*/
-#define CARD_V1_X ((uint32_t)0x00000000U)
-#define CARD_V2_X ((uint32_t)0x00000001U)
+#define CARD_V1_X 0x00000000U
+#define CARD_V2_X 0x00000001U
/**
* @}
*/
@@ -381,7 +384,7 @@
* @param __HANDLE__ : SD handle.
* @retval None
*/
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_SD_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
@@ -389,7 +392,7 @@
} while(0)
#else
#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SD_STATE_RESET)
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
/**
* @brief Enable the SD device.
@@ -417,8 +420,8 @@
/**
* @brief Enable the SD device interrupt.
- * @param __HANDLE__ SD Handle
- * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
+ * @param __HANDLE__: SD Handle
+ * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -428,7 +431,7 @@
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
@@ -441,15 +444,15 @@
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Disable the SD device interrupt.
- * @param __HANDLE__ SD Handle
- * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
+ * @param __HANDLE__: SD Handle
+ * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -459,7 +462,7 @@
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
@@ -472,15 +475,15 @@
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Check whether the specified SD flag is set or not.
- * @param __HANDLE__ SD Handle
- * @param __FLAG__ specifies the flag to check.
+ * @param __HANDLE__: SD Handle
+ * @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@@ -490,7 +493,7 @@
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDMMC_FLAG_CMDACT: Command transfer in progress
* @arg SDMMC_FLAG_TXACT: Data transmit in progress
@@ -503,15 +506,15 @@
* @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
* @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO
* @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO
- * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received
* @retval The new state of SD FLAG (SET or RESET).
*/
#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
/**
* @brief Clear the SD's pending flags.
- * @param __HANDLE__ SD Handle
- * @param __FLAG__ specifies the flag to clear.
+ * @param __HANDLE__: SD Handle
+ * @param __FLAG__: specifies the flag to clear.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@@ -521,17 +524,17 @@
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received
* @retval None
*/
#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
/**
* @brief Check whether the specified SD interrupt has occurred or not.
- * @param __HANDLE__ SD Handle
- * @param __INTERRUPT__ specifies the SDMMC interrupt source to check.
+ * @param __HANDLE__: SD Handle
+ * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
* This parameter can be one of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -541,7 +544,7 @@
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
@@ -554,15 +557,15 @@
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
* @retval The new state of SD IT (SET or RESET).
*/
#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Clear the SD's interrupt pending bits.
- * @param __HANDLE__ SD Handle
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * @param __HANDLE__: SD Handle
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -572,8 +575,8 @@
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
- * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
+ * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
@@ -621,11 +624,12 @@
void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
/* SD callback registering/unregistering */
HAL_StatusTypeDef HAL_SD_RegisterCallback (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId, pSD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId);
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -745,12 +749,13 @@
* @}
*/
+#endif /* SDMMC1 */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F7xx_HAL_SD_H */
+#endif /* STM32F7xx_HAL_SD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f7xx_hal_smartcard.h b/Inc/stm32f7xx_hal_smartcard.h
index 6d0ae01..c14c584 100644
--- a/Inc/stm32f7xx_hal_smartcard.h
+++ b/Inc/stm32f7xx_hal_smartcard.h
@@ -524,15 +524,15 @@
*/
#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
- (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
+ (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
#else
#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
- (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
+ (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
} while(0U)
#endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
@@ -540,11 +540,11 @@
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
*/
-#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \
- do{ \
- SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
- SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
- } while(0U)
+#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
+ SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
+ } while(0U)
/** @brief Clear the specified SMARTCARD pending flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@@ -667,7 +667,8 @@
* @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
-#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET)
+#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
+ & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified SmartCard interrupt source is enabled or not.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@@ -685,8 +686,8 @@
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
- (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
- (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET)
+ (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@@ -726,7 +727,8 @@
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
*/
-#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
+ &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
/** @brief Enable the USART associated to the SMARTCARD Handle.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@@ -758,8 +760,8 @@
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
break; \
@@ -775,12 +777,12 @@
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
@@ -796,12 +798,12 @@
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
- switch(__HAL_RCC_GET_USART3_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
@@ -817,12 +819,12 @@
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART6) \
{ \
- switch(__HAL_RCC_GET_USART6_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART6_SOURCE()) \
+ { \
case RCC_USART6CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
break; \
@@ -838,7 +840,7 @@
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else \
{ \
@@ -905,7 +907,8 @@
* @param __CPOL__ SMARTCARD frame polarity.
* @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
*/
-#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
+#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW)\
+ || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
/** @brief Ensure that SMARTCARD frame phase is valid.
* @param __CPHA__ SMARTCARD frame phase.
@@ -1034,8 +1037,10 @@
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
-HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
+ HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
+ HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/**
@@ -1047,8 +1052,10 @@
* @{
*/
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout);
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
diff --git a/Inc/stm32f7xx_hal_smartcard_ex.h b/Inc/stm32f7xx_hal_smartcard_ex.h
index 061b0f4..ddae1b6 100644
--- a/Inc/stm32f7xx_hal_smartcard_ex.h
+++ b/Inc/stm32f7xx_hal_smartcard_ex.h
@@ -166,7 +166,7 @@
do { \
if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \
{ \
- (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
+ (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
} \
else \
{ \
@@ -243,15 +243,6 @@
* @}
*/
-/** @addtogroup SMARTCARDEx_Exported_Functions_Group3
- * @{
- */
-
-/* Peripheral Control functions ***********************************************/
-
-/**
- * @}
- */
/**
* @}
diff --git a/Inc/stm32f7xx_hal_tim.h b/Inc/stm32f7xx_hal_tim.h
index 1a3b50a..c77e99c 100644
--- a/Inc/stm32f7xx_hal_tim.h
+++ b/Inc/stm32f7xx_hal_tim.h
@@ -167,7 +167,7 @@
This parameter can be a value of @ref TIM_Encoder_Mode */
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+ This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
uint32_t IC1Selection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
@@ -179,7 +179,7 @@
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+ This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
uint32_t IC2Selection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
@@ -235,7 +235,12 @@
uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
uint32_t MasterSlaveMode; /*!< Master/slave mode selection
- This parameter can be a value of @ref TIM_Master_Slave_Mode */
+ This parameter can be a value of @ref TIM_Master_Slave_Mode
+ @note When the Master/slave mode is enabled, the effect of
+ an event on the trigger input (TRGI) is delayed to allow a
+ perfect synchronization between the current timer and its
+ slaves (through TRGO). It is not mandatory in case of timer
+ synchronization mode. */
} TIM_MasterConfigTypeDef;
/**
@@ -518,6 +523,15 @@
* @}
*/
+/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap
+ * @{
+ */
+#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */
+#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */
+/**
+ * @}
+ */
+
/** @defgroup TIM_ClockDivision TIM Clock Division
* @{
*/
@@ -611,6 +625,15 @@
* @}
*/
+/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
+ * @{
+ */
+#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */
+#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */
+/**
+ * @}
+ */
+
/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
* @{
*/
@@ -1119,15 +1142,15 @@
* @retval None
*/
#define __HAL_TIM_DISABLE(__HANDLE__) \
- do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
- { \
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
- { \
- (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
- } \
- } \
- } while(0)
+ do { \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+ { \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+ { \
+ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
+ } \
+ } \
+ } while(0)
/**
* @brief Disable the TIM main Output.
@@ -1136,15 +1159,15 @@
* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
*/
#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
- do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
- { \
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
- { \
- (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
- } \
- } \
- } while(0)
+ do { \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+ { \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+ { \
+ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
+ } \
+ } \
+ } while(0)
/**
* @brief Disable the TIM main Output.
@@ -1279,7 +1302,8 @@
* @arg TIM_IT_BREAK: Break interrupt
* @retval The state of TIM_IT (SET or RESET).
*/
-#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
+ == (__INTERRUPT__)) ? SET : RESET)
/** @brief Clear the TIM interrupt pending bits.
* @param __HANDLE__ TIM handle
@@ -1298,6 +1322,31 @@
#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
/**
+ * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
+ * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
+ * @param __HANDLE__ TIM handle.
+ * @retval None
+mode.
+ */
+#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
+
+/**
+ * @brief Disable update interrupt flag (UIF) remapping.
+ * @param __HANDLE__ TIM handle.
+ * @retval None
+mode.
+ */
+#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
+
+/**
+ * @brief Get update interrupt flag (UIF) copy status.
+ * @param __COUNTER__ Counter value.
+ * @retval The state of UIFCPY (TRUE or FALSE).
+mode.
+ */
+#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
+
+/**
* @brief Indicates whether or not the TIM Counter is used as downcounter.
* @param __HANDLE__ TIM handle.
* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
@@ -1316,6 +1365,8 @@
/**
* @brief Set the TIM Counter Register value on runtime.
+ * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance.
+ * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
* @param __HANDLE__ TIM handle.
* @param __COUNTER__ specifies the Counter register new value.
* @retval None
@@ -1327,8 +1378,7 @@
* @param __HANDLE__ TIM handle.
* @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
*/
-#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
- ((__HANDLE__)->Instance->CNT)
+#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
/**
* @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
@@ -1337,18 +1387,17 @@
* @retval None
*/
#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
- do{ \
- (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
- (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
- } while(0)
+ do{ \
+ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
+ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
+ } while(0)
/**
* @brief Get the TIM Autoreload Register value on runtime.
* @param __HANDLE__ TIM handle.
* @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
*/
-#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
- ((__HANDLE__)->Instance->ARR)
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
/**
* @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
@@ -1361,11 +1410,11 @@
* @retval None
*/
#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
- do{ \
- (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
- (__HANDLE__)->Instance->CR1 |= (__CKD__); \
- (__HANDLE__)->Init.ClockDivision = (__CKD__); \
- } while(0)
+ do{ \
+ (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
+ (__HANDLE__)->Instance->CR1 |= (__CKD__); \
+ (__HANDLE__)->Init.ClockDivision = (__CKD__); \
+ } while(0)
/**
* @brief Get the TIM Clock Division value on runtime.
@@ -1375,8 +1424,7 @@
* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
*/
-#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
- ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
/**
* @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
@@ -1396,10 +1444,10 @@
* @retval None
*/
#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
- do{ \
- TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
- TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
- } while(0)
+ do{ \
+ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+ } while(0)
/**
* @brief Get the TIM Input Capture prescaler on runtime.
@@ -1437,12 +1485,12 @@
* @retval None
*/
#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
- ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
+ ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
/**
* @brief Get the TIM Capture Compare Register value on runtime.
@@ -1458,12 +1506,12 @@
* @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
*/
#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
- ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
- ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
- ((__HANDLE__)->Instance->CCR6))
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
+ ((__HANDLE__)->Instance->CCR6))
/**
* @brief Set the TIM Output compare preload.
@@ -1479,12 +1527,12 @@
* @retval None
*/
#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
- ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
+ ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
/**
* @brief Reset the TIM Output compare preload.
@@ -1500,12 +1548,62 @@
* @retval None
*/
#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\
- ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
+ ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
+
+/**
+ * @brief Enable fast mode for a given channel.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @note When fast mode is enabled an active edge on the trigger input acts
+ * like a compare match on CCx output. Delay to sample the trigger
+ * input and to activate CCx output is reduced to 3 clock cycles.
+ * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
+ ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
+
+/**
+ * @brief Disable fast mode for a given channel.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @note When fast mode is disabled CCx output behaves normally depending
+ * on counter and CCRx values even when the trigger is ON. The minimum
+ * delay to activate CCx output when an active edge occurs on the
+ * trigger input is 5 clock cycles.
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
+ ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
/**
* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
@@ -1515,8 +1613,7 @@
* enabled)
* @retval None
*/
-#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
- ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
+#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
/**
* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
@@ -1529,8 +1626,7 @@
* _ Update generation through the slave mode controller
* @retval None
*/
-#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
- ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
+#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
/**
* @brief Set the TIM Capture x input polarity on runtime.
@@ -1548,10 +1644,10 @@
* @retval None
*/
#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
- do{ \
- TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
- TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
- }while(0)
+ do{ \
+ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
+ }while(0)
/**
* @}
@@ -1579,29 +1675,29 @@
((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
#if defined(TIM_AF1_BKINE)&&defined(TIM_AF2_BKINE)
-#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
- ((__BASE__) == TIM_DMABASE_CR2) || \
- ((__BASE__) == TIM_DMABASE_SMCR) || \
- ((__BASE__) == TIM_DMABASE_DIER) || \
- ((__BASE__) == TIM_DMABASE_SR) || \
- ((__BASE__) == TIM_DMABASE_EGR) || \
- ((__BASE__) == TIM_DMABASE_CCMR1) || \
- ((__BASE__) == TIM_DMABASE_CCMR2) || \
- ((__BASE__) == TIM_DMABASE_CCER) || \
- ((__BASE__) == TIM_DMABASE_CNT) || \
- ((__BASE__) == TIM_DMABASE_PSC) || \
- ((__BASE__) == TIM_DMABASE_ARR) || \
- ((__BASE__) == TIM_DMABASE_RCR) || \
- ((__BASE__) == TIM_DMABASE_CCR1) || \
- ((__BASE__) == TIM_DMABASE_CCR2) || \
- ((__BASE__) == TIM_DMABASE_CCR3) || \
- ((__BASE__) == TIM_DMABASE_CCR4) || \
- ((__BASE__) == TIM_DMABASE_BDTR) || \
- ((__BASE__) == TIM_DMABASE_OR) || \
- ((__BASE__) == TIM_DMABASE_CCMR3) || \
- ((__BASE__) == TIM_DMABASE_CCR5) || \
- ((__BASE__) == TIM_DMABASE_CCR6) || \
- ((__BASE__) == TIM_DMABASE_AF1) || \
+#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
+ ((__BASE__) == TIM_DMABASE_CR2) || \
+ ((__BASE__) == TIM_DMABASE_SMCR) || \
+ ((__BASE__) == TIM_DMABASE_DIER) || \
+ ((__BASE__) == TIM_DMABASE_SR) || \
+ ((__BASE__) == TIM_DMABASE_EGR) || \
+ ((__BASE__) == TIM_DMABASE_CCMR1) || \
+ ((__BASE__) == TIM_DMABASE_CCMR2) || \
+ ((__BASE__) == TIM_DMABASE_CCER) || \
+ ((__BASE__) == TIM_DMABASE_CNT) || \
+ ((__BASE__) == TIM_DMABASE_PSC) || \
+ ((__BASE__) == TIM_DMABASE_ARR) || \
+ ((__BASE__) == TIM_DMABASE_RCR) || \
+ ((__BASE__) == TIM_DMABASE_CCR1) || \
+ ((__BASE__) == TIM_DMABASE_CCR2) || \
+ ((__BASE__) == TIM_DMABASE_CCR3) || \
+ ((__BASE__) == TIM_DMABASE_CCR4) || \
+ ((__BASE__) == TIM_DMABASE_BDTR) || \
+ ((__BASE__) == TIM_DMABASE_OR) || \
+ ((__BASE__) == TIM_DMABASE_CCMR3) || \
+ ((__BASE__) == TIM_DMABASE_CCR5) || \
+ ((__BASE__) == TIM_DMABASE_CCR6) || \
+ ((__BASE__) == TIM_DMABASE_AF1) || \
((__BASE__) == TIM_DMABASE_AF2))
#else
#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
@@ -1636,6 +1732,9 @@
((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
+#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
+ ((__MODE__) == TIM_UIFREMAP_ENALE))
+
#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
((__DIV__) == TIM_CLOCKDIVISION_DIV4))
@@ -1658,6 +1757,9 @@
#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
((__STATE__) == TIM_OCNIDLESTATE_RESET))
+#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
+ ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
+
#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
@@ -1876,28 +1978,28 @@
((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
- ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
- ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
+ ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
- ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
+ ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
- ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+ ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
/**
* @}
@@ -2035,7 +2137,8 @@
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+ uint32_t *pData2, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
@@ -2059,17 +2162,19 @@
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel);
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
+ uint32_t OutputChannel, uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
+ uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
- uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
- uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
@@ -2095,7 +2200,8 @@
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+ pTIM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
@@ -2125,8 +2231,8 @@
/* Private functions----------------------------------------------------------*/
/** @defgroup TIM_Private_Functions TIM Private Functions
-* @{
-*/
+ * @{
+ */
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
@@ -2145,8 +2251,8 @@
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/**
-* @}
-*/
+ * @}
+ */
/* End of private functions --------------------------------------------------*/
/**
diff --git a/Inc/stm32f7xx_hal_tim_ex.h b/Inc/stm32f7xx_hal_tim_ex.h
index f0434c2..2897aca 100644
--- a/Inc/stm32f7xx_hal_tim_ex.h
+++ b/Inc/stm32f7xx_hal_tim_ex.h
@@ -201,9 +201,9 @@
*/
/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
- * @brief Timer Hall Sensor functions
- * @{
- */
+ * @brief Timer Hall Sensor functions
+ * @{
+ */
/* Timer Hall Sensor functions **********************************************/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
@@ -225,9 +225,9 @@
*/
/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
- * @brief Timer Complementary Output Compare functions
- * @{
- */
+ * @brief Timer Complementary Output Compare functions
+ * @{
+ */
/* Timer Complementary Output Compare functions *****************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
@@ -245,9 +245,9 @@
*/
/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
- * @brief Timer Complementary PWM functions
- * @{
- */
+ * @brief Timer Complementary PWM functions
+ * @{
+ */
/* Timer Complementary PWM functions ****************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
@@ -264,9 +264,9 @@
*/
/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
- * @brief Timer Complementary One Pulse functions
- * @{
- */
+ * @brief Timer Complementary One Pulse functions
+ * @{
+ */
/* Timer Complementary One Pulse functions **********************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
@@ -280,17 +280,23 @@
*/
/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
- * @brief Peripheral Control functions
- * @{
- */
+ * @brief Peripheral Control functions
+ * @{
+ */
/* Extended Control functions ************************************************/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig);
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+ TIM_MasterConfigTypeDef *sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+ TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
#if defined(TIM_BREAK_INPUT_SUPPORT)
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
+ TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
#endif /* TIM_BREAK_INPUT_SUPPORT */
HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
@@ -327,7 +333,7 @@
/* End of exported functions -------------------------------------------------*/
/* Private functions----------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
+/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
* @{
*/
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
diff --git a/Inc/stm32f7xx_hal_uart.h b/Inc/stm32f7xx_hal_uart.h
index 689092d..eb186d6 100644
--- a/Inc/stm32f7xx_hal_uart.h
+++ b/Inc/stm32f7xx_hal_uart.h
@@ -125,8 +125,6 @@
This parameter can be a value of @ref UART_MSB_First. */
} UART_AdvFeatureInitTypeDef;
-
-
/**
* @brief HAL UART State definition
* @note HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition).
@@ -206,10 +204,9 @@
uint16_t Mask; /*!< UART Rx RDR register mask */
+ void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
- void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
-
- void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
+ void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
@@ -313,8 +310,10 @@
#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
+#define HAL_UART_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver Timeout error */
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */
+#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
* @}
@@ -400,11 +399,11 @@
* @}
*/
-/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut
+/** @defgroup UART_Receiver_Timeout UART Receiver Timeout
* @{
*/
-#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART receiver timeout disable */
-#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART receiver timeout enable */
+#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */
+#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */
/**
* @}
*/
@@ -562,6 +561,17 @@
/**
* @}
*/
+#if defined(USART_CR1_UESM)
+
+/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable
+ * @{
+ */
+#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U /*!< UART stop mode disable */
+#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM /*!< UART stop mode enable */
+/**
+ * @}
+ */
+#endif /* USART_CR1_UESM */
/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable
* @{
@@ -579,6 +589,18 @@
/**
* @}
*/
+#if defined(USART_CR1_UESM)
+
+/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection
+ * @{
+ */
+#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */
+#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */
+#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register not empty or RXFIFO is not empty */
+/**
+ * @}
+ */
+#endif /* USART_CR1_UESM */
/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity
* @{
@@ -626,13 +648,20 @@
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
+#if defined(USART_ISR_REACK)
+#define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */
+#endif /* USART_ISR_REACK */
#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */
+#if defined(USART_CR1_UESM)
+#define UART_FLAG_WUF USART_ISR_WUF /*!< UART wake-up from stop mode flag */
+#endif /* USART_CR1_UESM */
#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */
#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */
#define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */
#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */
#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */
#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */
+#define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */
#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */
#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */
#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */
@@ -674,6 +703,10 @@
#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */
#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */
#define UART_IT_CM 0x112EU /*!< UART character match interruption */
+#if defined(USART_CR1_UESM)
+#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */
+#endif /* USART_CR1_UESM */
+#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */
#define UART_IT_ERR 0x0060U /*!< UART error interruption */
@@ -689,13 +722,17 @@
*/
#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
-#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */
+#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */
#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */
#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */
#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */
+#if defined(USART_CR1_UESM)
+#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */
+#endif /* USART_CR1_UESM */
+#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */
/**
* @}
*/
@@ -734,9 +771,9 @@
*/
#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \
do{ \
- SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
- SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
- } while(0U)
+ SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
+ SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
+ } while(0U)
/** @brief Clear the specified UART pending flag.
* @param __HANDLE__ specifies the UART Handle.
@@ -748,9 +785,13 @@
* @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
* @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
* @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
+ * @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag
* @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
* @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
* @arg @ref UART_CLEAR_CMF Character Match Clear Flag
+#if defined(USART_CR1_UESM)
+ * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag
+#endif
* @retval None
*/
#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
@@ -790,7 +831,13 @@
* @param __HANDLE__ specifies the UART Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
+#if defined(USART_ISR_REACK)
+ * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
+#endif
* @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
+ #if defined(USART_CR1_UESM)
+ * @arg @ref UART_FLAG_WUF Wake up from stop mode flag
+ #endif
* @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode)
* @arg @ref UART_FLAG_SBKF Send Break flag
* @arg @ref UART_FLAG_CMF Character match flag
@@ -802,6 +849,7 @@
* @arg @ref UART_FLAG_TXE Transmit data register empty flag
* @arg @ref UART_FLAG_TC Transmission Complete flag
* @arg @ref UART_FLAG_RXNE Receive data register not empty flag
+ * @arg @ref UART_FLAG_RTOF Receiver Timeout flag
* @arg @ref UART_FLAG_IDLE Idle Line detection flag
* @arg @ref UART_FLAG_ORE Overrun Error flag
* @arg @ref UART_FLAG_NE Noise Error flag
@@ -815,12 +863,16 @@
* @param __HANDLE__ specifies the UART Handle.
* @param __INTERRUPT__ specifies the UART interrupt source to enable.
* This parameter can be one of the following values:
+#if defined(USART_CR1_UESM)
+ * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
+#endif
* @arg @ref UART_IT_CM Character match interrupt
* @arg @ref UART_IT_CTS CTS change interrupt
* @arg @ref UART_IT_LBD LIN Break detection interrupt
* @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
* @arg @ref UART_IT_TC Transmission complete interrupt
* @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_RTO Receive Timeout interrupt
* @arg @ref UART_IT_IDLE Idle line detection interrupt
* @arg @ref UART_IT_PE Parity Error interrupt
* @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error)
@@ -835,12 +887,16 @@
* @param __HANDLE__ specifies the UART Handle.
* @param __INTERRUPT__ specifies the UART interrupt source to disable.
* This parameter can be one of the following values:
+#if defined(USART_CR1_UESM)
+ * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
+#endif
* @arg @ref UART_IT_CM Character match interrupt
* @arg @ref UART_IT_CTS CTS change interrupt
* @arg @ref UART_IT_LBD LIN Break detection interrupt
* @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
* @arg @ref UART_IT_TC Transmission complete interrupt
* @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_RTO Receive Timeout interrupt
* @arg @ref UART_IT_IDLE Idle line detection interrupt
* @arg @ref UART_IT_PE Parity Error interrupt
* @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
@@ -854,37 +910,46 @@
* @param __HANDLE__ specifies the UART Handle.
* @param __INTERRUPT__ specifies the UART interrupt to check.
* This parameter can be one of the following values:
+#if defined(USART_CR1_UESM)
+ * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
+#endif
* @arg @ref UART_IT_CM Character match interrupt
* @arg @ref UART_IT_CTS CTS change interrupt
* @arg @ref UART_IT_LBD LIN Break detection interrupt
* @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
* @arg @ref UART_IT_TC Transmission complete interrupt
* @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_RTO Receive Timeout interrupt
* @arg @ref UART_IT_IDLE Idle line detection interrupt
* @arg @ref UART_IT_PE Parity Error interrupt
* @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
-#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
+#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
+ & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
/** @brief Check whether the specified UART interrupt source is enabled or not.
* @param __HANDLE__ specifies the UART Handle.
* @param __INTERRUPT__ specifies the UART interrupt source to check.
* This parameter can be one of the following values:
+#if defined(USART_CR1_UESM)
+ * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
+#endif
* @arg @ref UART_IT_CM Character match interrupt
* @arg @ref UART_IT_CTS CTS change interrupt
* @arg @ref UART_IT_LBD LIN Break detection interrupt
* @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
* @arg @ref UART_IT_TC Transmission complete interrupt
* @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_RTO Receive Timeout interrupt
* @arg @ref UART_IT_IDLE Idle line detection interrupt
* @arg @ref UART_IT_PE Parity Error interrupt
* @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \
- (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \
- (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET)
+ (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET)
/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the UART Handle.
@@ -896,10 +961,14 @@
* @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
* @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
* @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
+ * @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag
* @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
* @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
* @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
* @arg @ref UART_CLEAR_CMF Character Match Clear Flag
+ #if defined(USART_CR1_UESM)
+ * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag
+#endif
* @retval None
*/
#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
@@ -1083,10 +1152,10 @@
* @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
*/
#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
- (((__CONTROL__) == UART_HWCONTROL_NONE) || \
- ((__CONTROL__) == UART_HWCONTROL_RTS) || \
- ((__CONTROL__) == UART_HWCONTROL_CTS) || \
- ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
+ (((__CONTROL__) == UART_HWCONTROL_NONE) || \
+ ((__CONTROL__) == UART_HWCONTROL_RTS) || \
+ ((__CONTROL__) == UART_HWCONTROL_CTS) || \
+ ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
/**
* @brief Ensure that UART communication mode is valid.
@@ -1134,8 +1203,15 @@
* @param __TIMEOUT__ UART receiver timeout setting.
* @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
*/
-#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
- ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
+#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
+ ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
+
+/** @brief Check the receiver timeout value.
+ * @note The maximum UART receiver timeout value is 0xFFFFFF.
+ * @param __TIMEOUTVALUE__ receiver timeout value.
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
/**
* @brief Ensure that UART LIN state is valid.
@@ -1275,6 +1351,16 @@
#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
+#if defined(USART_CR1_UESM)
+/**
+ * @brief Ensure that UART stop mode state is valid.
+ * @param __STOPMODE__ UART stop mode state.
+ * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
+ ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
+
+#endif /* USART_CR1_UESM */
/**
* @brief Ensure that UART mute mode state is valid.
* @param __MUTE__ UART mute mode state.
@@ -1282,6 +1368,17 @@
*/
#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
+#if defined(USART_CR1_UESM)
+
+/**
+ * @brief Ensure that UART wake-up selection is valid.
+ * @param __WAKE__ UART wake-up selection.
+ * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
+ */
+#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \
+ ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \
+ ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
+#endif /* USART_CR1_UESM */
/**
* @brief Ensure that UART driver enable polarity is valid.
@@ -1320,7 +1417,8 @@
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
+ pUART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
@@ -1369,6 +1467,10 @@
*/
/* Peripheral Control functions ************************************************/
+void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue);
+HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart);
+
HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
@@ -1405,7 +1507,8 @@
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout);
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
/**
diff --git a/Inc/stm32f7xx_hal_uart_ex.h b/Inc/stm32f7xx_hal_uart_ex.h
index 3917016..e99d8d6 100644
--- a/Inc/stm32f7xx_hal_uart_ex.h
+++ b/Inc/stm32f7xx_hal_uart_ex.h
@@ -41,7 +41,24 @@
* @{
*/
+#if defined(USART_CR1_UESM)
+/**
+ * @brief UART wake up from stop mode parameters
+ */
+typedef struct
+{
+ uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
+ This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
+ If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
+ be filled up. */
+ uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
+ This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */
+
+ uint8_t Address; /*!< UART/USART node address (7-bit long max). */
+} UART_WakeUpTypeDef;
+
+#endif /* USART_CR1_UESM */
/**
* @}
*/
@@ -54,9 +71,9 @@
/** @defgroup UARTEx_Word_Length UARTEx Word Length
* @{
*/
-#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */
-#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */
-#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */
+#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */
+#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */
+#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */
/**
* @}
*/
@@ -64,13 +81,12 @@
/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
* @{
*/
-#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */
-#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */
+#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */
+#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */
/**
* @}
*/
-
/**
* @}
*/
@@ -86,7 +102,8 @@
*/
/* Initialization and de-initialization functions ****************************/
-HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
+ uint32_t DeassertionTime);
/**
* @}
@@ -96,6 +113,10 @@
* @{
*/
+#if defined(USART_CR1_UESM)
+void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
+
+#endif /* USART_CR1_UESM */
/**
* @}
@@ -106,8 +127,20 @@
*/
/* Peripheral Control functions **********************************************/
+#if defined(USART_CR1_UESM)
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
+
+#endif/* USART_CR1_UESM */
+#if defined(USART_CR3_UCESM)
+HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart);
+
+#endif /* USART_CR3_UCESM */
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
+
/**
* @}
*/
@@ -126,12 +159,12 @@
* @param __CLOCKSOURCE__ output variable.
* @retval UART clocking source, written in __CLOCKSOURCE__.
*/
-#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
break; \
@@ -147,12 +180,12 @@
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
@@ -168,12 +201,12 @@
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
- switch(__HAL_RCC_GET_USART3_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
@@ -189,12 +222,12 @@
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == UART4) \
{ \
- switch(__HAL_RCC_GET_UART4_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_UART4_SOURCE()) \
+ { \
case RCC_UART4CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
@@ -210,12 +243,12 @@
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if ((__HANDLE__)->Instance == UART5) \
{ \
- switch(__HAL_RCC_GET_UART5_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_UART5_SOURCE()) \
+ { \
case RCC_UART5CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
@@ -231,12 +264,12 @@
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART6) \
{ \
- switch(__HAL_RCC_GET_USART6_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART6_SOURCE()) \
+ { \
case RCC_USART6CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
break; \
@@ -252,12 +285,12 @@
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if ((__HANDLE__)->Instance == UART7) \
{ \
- switch(__HAL_RCC_GET_UART7_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_UART7_SOURCE()) \
+ { \
case RCC_UART7CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
@@ -273,12 +306,12 @@
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if ((__HANDLE__)->Instance == UART8) \
{ \
- switch(__HAL_RCC_GET_UART8_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_UART8_SOURCE()) \
+ { \
case RCC_UART8CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
@@ -294,7 +327,7 @@
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else \
{ \
@@ -313,44 +346,44 @@
*/
#define UART_MASK_COMPUTATION(__HANDLE__) \
do { \
- if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
- { \
- if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
- { \
+ if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
(__HANDLE__)->Mask = 0x01FFU ; \
- } \
- else \
- { \
+ } \
+ else \
+ { \
(__HANDLE__)->Mask = 0x00FFU ; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
- { \
- if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
- { \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
(__HANDLE__)->Mask = 0x00FFU ; \
- } \
- else \
- { \
+ } \
+ else \
+ { \
(__HANDLE__)->Mask = 0x007FU ; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
- { \
- if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
- { \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
(__HANDLE__)->Mask = 0x007FU ; \
- } \
- else \
- { \
+ } \
+ else \
+ { \
(__HANDLE__)->Mask = 0x003FU ; \
- } \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x0000U; \
- } \
-} while(0U)
+ } \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x0000U; \
+ } \
+ } while(0U)
/**
* @brief Ensure that UART frame length is valid.
@@ -369,7 +402,6 @@
#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
-
/**
* @}
*/
diff --git a/Inc/stm32f7xx_hal_usart.h b/Inc/stm32f7xx_hal_usart.h
index 9f615f3..4707dfd 100644
--- a/Inc/stm32f7xx_hal_usart.h
+++ b/Inc/stm32f7xx_hal_usart.h
@@ -209,6 +209,7 @@
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
#define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+#define HAL_USART_ERROR_RTO ((uint32_t)0x00000080U) /*!< Receiver Timeout error */
/**
* @}
*/
@@ -304,9 +305,11 @@
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
+#define USART_FLAG_REACK USART_ISR_REACK /*!< USART receive enable acknowledge flag */
#define USART_FLAG_TEACK USART_ISR_TEACK /*!< USART transmit enable acknowledge flag */
#define USART_FLAG_BUSY USART_ISR_BUSY /*!< USART busy flag */
#define USART_FLAG_TXE USART_ISR_TXE /*!< USART transmit data register empty */
+#define USART_FLAG_RTOF USART_ISR_RTOF /*!< USART receiver timeout flag */
#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */
#define USART_FLAG_RXNE USART_ISR_RXNE /*!< USART read data register not empty */
#define USART_FLAG_IDLE USART_ISR_IDLE /*!< USART idle flag */
@@ -348,10 +351,11 @@
*/
#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
-#define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */
+#define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */
#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
+#define USART_CLEAR_RTOF USART_ICR_RTOCF /*!< USART receiver timeout clear flag */
/**
* @}
*/
@@ -383,10 +387,10 @@
*/
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_USART_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0U)
+ (__HANDLE__)->State = HAL_USART_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0U)
#else
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
@@ -395,11 +399,13 @@
* @param __HANDLE__ specifies the USART Handle
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
+ * @arg @ref USART_FLAG_REACK Receive enable acknowledge flag
* @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag
* @arg @ref USART_FLAG_BUSY Busy flag
* @arg @ref USART_FLAG_TXE Transmit data register empty flag
* @arg @ref USART_FLAG_TC Transmission Complete flag
* @arg @ref USART_FLAG_RXNE Receive data register not empty flag
+ * @arg @ref USART_FLAG_RTOF Receiver Timeout flag
* @arg @ref USART_FLAG_IDLE Idle Line detection flag
* @arg @ref USART_FLAG_ORE OverRun Error flag
* @arg @ref USART_FLAG_NE Noise Error flag
@@ -419,6 +425,7 @@
* @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag
* @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
* @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
+ * @arg @ref USART_CLEAR_RTOF Receiver Timeout clear flag
* @retval None
*/
#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
@@ -502,7 +509,8 @@
* @arg @ref USART_IT_PE Parity Error interrupt
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
-#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET)
+#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
+ & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified USART interrupt source is enabled or not.
* @param __HANDLE__ specifies the USART Handle.
@@ -519,8 +527,8 @@
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \
- (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \
- (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET)
+ (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag.
@@ -533,6 +541,7 @@
* @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
* @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag
* @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
+ * @arg @ref USART_CLEAR_RTOF Receiver timeout clear flag
* @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
* @retval None
*/
@@ -598,8 +607,8 @@
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \
break; \
@@ -615,12 +624,12 @@
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
@@ -636,12 +645,12 @@
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
- switch(__HAL_RCC_GET_USART3_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
@@ -657,12 +666,12 @@
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART6) \
{ \
- switch(__HAL_RCC_GET_USART6_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART6_SOURCE()) \
+ { \
case RCC_USART6CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \
break; \
@@ -678,7 +687,7 @@
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else \
{ \
@@ -789,7 +798,8 @@
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
+ pUSART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
@@ -804,13 +814,16 @@
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size);
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size);
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
diff --git a/Inc/stm32f7xx_hal_usart_ex.h b/Inc/stm32f7xx_hal_usart_ex.h
index e8dc9a9..47abbf4 100644
--- a/Inc/stm32f7xx_hal_usart_ex.h
+++ b/Inc/stm32f7xx_hal_usart_ex.h
@@ -46,14 +46,13 @@
* @{
*/
#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */
-#define USART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long USART frame */
+#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */
/**
* @}
*/
-
/**
* @}
*/
@@ -74,45 +73,44 @@
*/
#define USART_MASK_COMPUTATION(__HANDLE__) \
do { \
- if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
- { \
- if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
- { \
+ if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
(__HANDLE__)->Mask = 0x01FFU; \
- } \
- else \
- { \
+ } \
+ else \
+ { \
(__HANDLE__)->Mask = 0x00FFU; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
- { \
- if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
- { \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
(__HANDLE__)->Mask = 0x00FFU; \
- } \
- else \
- { \
+ } \
+ else \
+ { \
(__HANDLE__)->Mask = 0x007FU; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
- { \
- if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
- { \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
(__HANDLE__)->Mask = 0x007FU; \
- } \
- else \
- { \
+ } \
+ else \
+ { \
(__HANDLE__)->Mask = 0x003FU; \
- } \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x0000U; \
- } \
-} while(0U)
-
+ } \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x0000U; \
+ } \
+ } while(0U)
/**
* @brief Ensure that USART frame length is valid.
diff --git a/Inc/stm32f7xx_hal_wwdg.h b/Inc/stm32f7xx_hal_wwdg.h
index f6ccb4e..c0ce8e4 100644
--- a/Inc/stm32f7xx_hal_wwdg.h
+++ b/Inc/stm32f7xx_hal_wwdg.h
@@ -22,7 +22,7 @@
#define STM32F7xx_HAL_WWDG_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -89,12 +89,12 @@
{
HAL_WWDG_EWI_CB_ID = 0x00u, /*!< WWDG EWI callback ID */
HAL_WWDG_MSPINIT_CB_ID = 0x01u, /*!< WWDG MspInit callback ID */
-}HAL_WWDG_CallbackIDTypeDef;
+} HAL_WWDG_CallbackIDTypeDef;
/**
* @brief HAL WWDG Callback pointer definition
*/
-typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer to a WWDG common callback functions */
+typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */
#endif
/**
@@ -239,7 +239,8 @@
* @arg WWDG_IT_EWI: Early Wakeup Interrupt
* @retval state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\
+ & (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @}
@@ -294,6 +295,6 @@
}
#endif
-#endif /* __STM32F7xx_HAL_WWDG_H */
+#endif /* STM32F7xx_HAL_WWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f7xx_ll_adc.h b/Inc/stm32f7xx_ll_adc.h
index e857b56..77f0ea2 100644
--- a/Inc/stm32f7xx_ll_adc.h
+++ b/Inc/stm32f7xx_ll_adc.h
@@ -255,11 +255,11 @@
#define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
/* ADC internal channels related definitions */
/* Internal voltage reference VrefInt */
-#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FF0F44A)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define VREFINT_CAL_ADDR VREFINT_CAL_ADDR_CMSIS /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define VREFINT_CAL_VREF ( 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
/* Temperature sensor */
-#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FF0F44C)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FF0F44E)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL1_ADDR TEMPSENSOR_CAL1_ADDR_CMSIS /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL2_ADDR TEMPSENSOR_CAL2_ADDR_CMSIS /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define TEMPSENSOR_CAL_VREFANALOG ( 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
diff --git a/Inc/stm32f7xx_ll_lptim.h b/Inc/stm32f7xx_ll_lptim.h
index 395e00b..03baa91 100644
--- a/Inc/stm32f7xx_ll_lptim.h
+++ b/Inc/stm32f7xx_ll_lptim.h
@@ -18,8 +18,8 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_LL_LPTIM_H
-#define __STM32F7xx_LL_LPTIM_H
+#ifndef STM32F7xx_LL_LPTIM_H
+#define STM32F7xx_LL_LPTIM_H
#ifdef __cplusplus
extern "C" {
@@ -31,8 +31,9 @@
/** @addtogroup STM32F7xx_LL_Driver
* @{
*/
-#if defined (LPTIM1)
-
+
+#if defined (LPTIM1)
+
/** @defgroup LPTIM_LL LPTIM
* @{
*/
@@ -127,8 +128,8 @@
/** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
* @{
*/
-#define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
-#define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
+#define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
+#define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
/**
* @}
*/
@@ -136,8 +137,8 @@
/** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
* @{
*/
-#define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
-#define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
+#define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
+#define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
/**
* @}
*/
@@ -145,8 +146,8 @@
/** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
* @{
*/
-#define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
-#define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
+#define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
+#define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
/**
* @}
*/
@@ -154,8 +155,8 @@
/** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
* @{
*/
-#define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE*/
-#define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
+#define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE*/
+#define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
/**
* @}
*/
@@ -163,8 +164,8 @@
/** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
* @{
*/
-#define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
-#define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
+#define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
+#define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
/**
* @}
*/
@@ -187,14 +188,14 @@
/** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
* @{
*/
-#define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
-#define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
-#define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
-#define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
-#define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/
-#define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 3*/
-#define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/
-#define LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL /*!<External input trigger is connected to COMP2 output*/
+#define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
+#define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
+#define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
+#define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
+#define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/
+#define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 3*/
+#define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/
+#define LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL /*!<External input trigger is connected to COMP2 output*/
/**
* @}
*/
@@ -202,10 +203,10 @@
/** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
* @{
*/
-#define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
-#define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
-#define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
-#define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
+#define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
+#define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
+#define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
+#define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
/**
* @}
*/
@@ -213,9 +214,9 @@
/** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
* @{
*/
-#define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
-#define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
-#define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
+#define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
+#define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
+#define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
/**
* @}
*/
@@ -223,8 +224,8 @@
/** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
* @{
*/
-#define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
-#define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
+#define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
+#define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
/**
* @}
*/
@@ -232,10 +233,10 @@
/** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
* @{
*/
-#define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
-#define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
-#define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
-#define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
+#define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
+#define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
+#define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
+#define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
/**
* @}
*/
@@ -243,9 +244,9 @@
/** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
* @{
*/
-#define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
-#define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
-#define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
+#define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
+#define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
+#define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
/**
* @}
*/
@@ -253,14 +254,13 @@
/** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
* @{
*/
-#define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
-#define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
-#define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
+#define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
+#define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
+#define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
/**
* @}
*/
-
/**
* @}
*/
@@ -281,7 +281,7 @@
* @param __VALUE__ Value to be written in the register
* @retval None
*/
-#define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+#define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
/**
* @brief Read a value in LPTIM register
@@ -289,7 +289,7 @@
* @param __REG__ Register to be read
* @retval Register value
*/
-#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
/**
* @}
*/
@@ -298,12 +298,25 @@
* @}
*/
-
/* Exported functions --------------------------------------------------------*/
/** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
* @{
*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
+ * @{
+ */
+
+ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
+void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
+ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
+void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
/** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
* @{
*/
@@ -322,17 +335,6 @@
}
/**
- * @brief Disable the LPTIM instance
- * @rmtoll CR ENABLE LL_LPTIM_Disable
- * @param LPTIMx Low-Power Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
-{
- CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
-}
-
-/**
* @brief Indicates whether the LPTIM instance is enabled.
* @rmtoll CR ENABLE LL_LPTIM_IsEnabled
* @param LPTIMx Low-Power Timer instance
@@ -340,7 +342,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == (LPTIM_CR_ENABLE));
+ return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
}
/**
@@ -361,7 +363,6 @@
MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
}
-
/**
* @brief Set the LPTIM registers update mode (enable/disable register preload)
* @note This function must be called when the LPTIM instance is disabled.
@@ -395,7 +396,7 @@
* @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
* @note After a write to the LPTIMx_ARR register a new write operation to the
* same register can only be performed when the previous write operation
- * is completed. Any successive write before the ARROK flag be set, will
+ * is completed. Any successive write before the ARROK flag is set, will
* lead to unpredictable results.
* @note autoreload value be strictly greater than the compare value.
* @rmtoll ARR ARR LL_LPTIM_SetAutoReload
@@ -423,7 +424,7 @@
* @brief Set the compare value
* @note After a write to the LPTIMx_CMP register a new write operation to the
* same register can only be performed when the previous write operation
- * is completed. Any successive write before the CMPOK flag be set, will
+ * is completed. Any successive write before the CMPOK flag is set, will
* lead to unpredictable results.
* @rmtoll CMP CMP LL_LPTIM_SetCompare
* @param LPTIMx Low-Power Timer instance
@@ -609,7 +610,6 @@
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
}
-
/**
* @}
*/
@@ -657,7 +657,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == (LPTIM_CFGR_TIMOUT));
+ return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
}
/**
@@ -920,7 +920,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == (LPTIM_CFGR_ENC));
+ return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
}
/**
@@ -950,7 +950,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == (LPTIM_ISR_CMPM));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL));
}
/**
@@ -972,7 +972,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == (LPTIM_ISR_ARRM));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
}
/**
@@ -994,7 +994,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == (LPTIM_ISR_EXTTRIG));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
}
/**
@@ -1009,14 +1009,14 @@
}
/**
- * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed; If so, a new one can be initiated.
+ * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated.
* @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == (LPTIM_ISR_CMPOK));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL));
}
/**
@@ -1031,14 +1031,14 @@
}
/**
- * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed; If so, a new one can be initiated.
+ * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated.
* @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == (LPTIM_ISR_ARROK));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
}
/**
@@ -1060,7 +1060,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == (LPTIM_ISR_UP));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
}
/**
@@ -1082,7 +1082,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == (LPTIM_ISR_DOWN));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
}
/**
@@ -1123,7 +1123,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == (LPTIM_IER_CMPMIE));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL));
}
/**
@@ -1156,7 +1156,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == (LPTIM_IER_ARRMIE));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL));
}
/**
@@ -1189,7 +1189,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == (LPTIM_IER_EXTTRIGIE));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL));
}
/**
@@ -1222,7 +1222,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == (LPTIM_IER_CMPOKIE));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL));
}
/**
@@ -1251,11 +1251,11 @@
* @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
* @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
* @param LPTIMx Low-Power Timer instance
- * @retval State of bit (1 or 0).
+ * @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == (LPTIM_IER_ARROKIE));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL));
}
/**
@@ -1284,11 +1284,11 @@
* @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
* @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
* @param LPTIMx Low-Power Timer instance
- * @retval State of bit (1 or 0).
+ * @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == (LPTIM_IER_UPIE));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL));
}
/**
@@ -1317,30 +1317,17 @@
* @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
* @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
* @param LPTIMx Low-Power Timer instance
- * @retval State of bit (1 or 0).
+ * @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == (LPTIM_IER_DOWNIE));
+ return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL);
}
/**
* @}
*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
- * @{
- */
-
-ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
-void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
-ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
/**
* @}
*/
@@ -1359,6 +1346,6 @@
}
#endif
-#endif /* __STM32F7xx_LL_LPTIM_H */
+#endif /* STM32F7xx_LL_LPTIM_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f7xx_ll_sdmmc.h b/Inc/stm32f7xx_ll_sdmmc.h
index 4e38698..aa0d0ee 100644
--- a/Inc/stm32f7xx_ll_sdmmc.h
+++ b/Inc/stm32f7xx_ll_sdmmc.h
@@ -12,19 +12,21 @@
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_LL_SDMMC_H
-#define __STM32F7xx_LL_SDMMC_H
+#ifndef STM32F7xx_LL_SDMMC_H
+#define STM32F7xx_LL_SDMMC_H
#ifdef __cplusplus
extern "C" {
#endif
+#if defined(SDMMC1)
+
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
@@ -127,205 +129,206 @@
/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
* @{
*/
-#define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /*!< Command response received (but CRC check failed) */
-#define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /*!< Data block sent/received (CRC check failed) */
-#define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /*!< Command response timeout */
-#define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /*!< Data timeout */
-#define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */
-#define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */
-#define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */
-#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the
+#define SDMMC_ERROR_NONE 0x00000000U /*!< No error */
+#define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /*!< Command response received (but CRC check failed) */
+#define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /*!< Data block sent/received (CRC check failed) */
+#define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /*!< Command response timeout */
+#define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /*!< Data timeout */
+#define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /*!< Transmit FIFO underrun */
+#define SDMMC_ERROR_RX_OVERRUN 0x00000020U /*!< Receive FIFO overrun */
+#define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /*!< Misaligned address */
+#define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the
number of transferred bytes does not match the block length */
-#define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */
-#define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */
-#define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */
-#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock
+#define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /*!< An error in the sequence of erase command occurs */
+#define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /*!< An invalid selection for erase groups */
+#define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /*!< Attempt to program a write protect block */
+#define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock
command or if there was an attempt to access a locked card */
-#define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */
-#define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */
-#define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */
-#define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /*!< Internal card controller error */
-#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /*!< General or unknown error */
-#define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /*!< The card could not sustain data reading in stream rmode */
-#define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /*!< The card could not sustain data programming in stream mode */
-#define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */
-#define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */
-#define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */
-#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out
+#define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /*!< CRC check of the previous command failed */
+#define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /*!< Command is not legal for the card state */
+#define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /*!< Card internal ECC was applied but failed to correct the data */
+#define SDMMC_ERROR_CC_ERR 0x00008000U /*!< Internal card controller error */
+#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /*!< General or unknown error */
+#define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /*!< The card could not sustain data reading in stream rmode */
+#define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /*!< The card could not sustain data programming in stream mode */
+#define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /*!< CID/CSD overwrite error */
+#define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /*!< Only partial address space was erased */
+#define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /*!< Command has been executed without using internal ECC */
+#define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out
of erase sequence command was received */
-#define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */
-#define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */
-#define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */
-#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /*!< Error when command request is not applicable */
-#define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /*!< the used parameter is not valid */
-#define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /*!< Error when feature is not insupported */
-#define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /*!< Error when transfer process is busy */
-#define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */
-#define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */
+#define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /*!< Error in sequence of authentication */
+#define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /*!< Error in case of invalid voltage range */
+#define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /*!< Error when addressed block is out of range */
+#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /*!< Error when command request is not applicable */
+#define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /*!< the used parameter is not valid */
+#define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /*!< Error when feature is not insupported */
+#define SDMMC_ERROR_BUSY 0x20000000U /*!< Error when transfer process is busy */
+#define SDMMC_ERROR_DMA 0x40000000U /*!< Error while DMA transfer */
+#define SDMMC_ERROR_TIMEOUT 0x80000000U /*!< Timeout error */
/**
* @brief SDMMC Commands Index
*/
-#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */
-#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */
-#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
-#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */
-#define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */
-#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
- operating condition register (OCR) content in the response on the CMD line. */
-#define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
-#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */
-#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
- and asks the card whether card supports voltage. */
-#define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
-#define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */
-#define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) /*!< SD card doesn't support it. */
-#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */
-#define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */
-#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */
-#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */
-#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands
+#define SDMMC_CMD_GO_IDLE_STATE 0U /*!< Resets the SD memory card. */
+#define SDMMC_CMD_SEND_OP_COND 1U /*!< Sends host capacity support information and activates the card's initialization process. */
+#define SDMMC_CMD_ALL_SEND_CID 2U /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
+#define SDMMC_CMD_SET_REL_ADDR 3U /*!< Asks the card to publish a new relative address (RCA). */
+#define SDMMC_CMD_SET_DSR 4U /*!< Programs the DSR of all cards. */
+#define SDMMC_CMD_SDMMC_SEN_OP_COND 5U /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
+ operating condition register (OCR) content in the response on the CMD line. */
+#define SDMMC_CMD_HS_SWITCH 6U /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
+#define SDMMC_CMD_SEL_DESEL_CARD 7U /*!< Selects the card by its own relative address and gets deselected by any other address */
+#define SDMMC_CMD_HS_SEND_EXT_CSD 8U /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
+ and asks the card whether card supports voltage. */
+#define SDMMC_CMD_SEND_CSD 9U /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
+#define SDMMC_CMD_SEND_CID 10U /*!< Addressed card sends its card identification (CID) on the CMD line. */
+#define SDMMC_CMD_READ_DAT_UNTIL_STOP 11U /*!< SD card doesn't support it. */
+#define SDMMC_CMD_STOP_TRANSMISSION 12U /*!< Forces the card to stop transmission. */
+#define SDMMC_CMD_SEND_STATUS 13U /*!< Addressed card sends its status register. */
+#define SDMMC_CMD_HS_BUSTEST_READ 14U /*!< Reserved */
+#define SDMMC_CMD_GO_INACTIVE_STATE 15U /*!< Sends an addressed card into the inactive state. */
+#define SDMMC_CMD_SET_BLOCKLEN 16U /*!< Sets the block length (in bytes for SDSC) for all following block commands
(read, write, lock). Default block length is fixed to 512 Bytes. Not effective
for SDHS and SDXC. */
-#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
+#define SDMMC_CMD_READ_SINGLE_BLOCK 17U /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
fixed 512 bytes in case of SDHC and SDXC. */
-#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by
+#define SDMMC_CMD_READ_MULT_BLOCK 18U /*!< Continuously transfers data blocks from card to host until interrupted by
STOP_TRANSMISSION command. */
-#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
-#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */
-#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */
-#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
+#define SDMMC_CMD_HS_BUSTEST_WRITE 19U /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
+#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP 20U /*!< Speed class control command. */
+#define SDMMC_CMD_SET_BLOCK_COUNT 23U /*!< Specify block count for CMD18 and CMD25. */
+#define SDMMC_CMD_WRITE_SINGLE_BLOCK 24U /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
fixed 512 bytes in case of SDHC and SDXC. */
-#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
-#define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */
-#define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */
-#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */
-#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */
-#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */
-#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */
-#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */
-#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command
+#define SDMMC_CMD_WRITE_MULT_BLOCK 25U /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
+#define SDMMC_CMD_PROG_CID 26U /*!< Reserved for manufacturers. */
+#define SDMMC_CMD_PROG_CSD 27U /*!< Programming of the programmable bits of the CSD. */
+#define SDMMC_CMD_SET_WRITE_PROT 28U /*!< Sets the write protection bit of the addressed group. */
+#define SDMMC_CMD_CLR_WRITE_PROT 29U /*!< Clears the write protection bit of the addressed group. */
+#define SDMMC_CMD_SEND_WRITE_PROT 30U /*!< Asks the card to send the status of the write protection bits. */
+#define SDMMC_CMD_SD_ERASE_GRP_START 32U /*!< Sets the address of the first write block to be erased. (For SD card only). */
+#define SDMMC_CMD_SD_ERASE_GRP_END 33U /*!< Sets the address of the last write block of the continuous range to be erased. */
+#define SDMMC_CMD_ERASE_GRP_START 35U /*!< Sets the address of the first write block to be erased. Reserved for each command
system set by switch function command (CMD6). */
-#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased.
+#define SDMMC_CMD_ERASE_GRP_END 36U /*!< Sets the address of the last write block of the continuous range to be erased.
Reserved for each command system set by switch function command (CMD6). */
-#define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */
-#define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */
-#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */
-#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
+#define SDMMC_CMD_ERASE 38U /*!< Reserved for SD security applications. */
+#define SDMMC_CMD_FAST_IO 39U /*!< SD card doesn't support it (Reserved). */
+#define SDMMC_CMD_GO_IRQ_STATE 40U /*!< SD card doesn't support it (Reserved). */
+#define SDMMC_CMD_LOCK_UNLOCK 42U /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
the SET_BLOCK_LEN command. */
-#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather
+#define SDMMC_CMD_APP_CMD 55U /*!< Indicates to the card that the next command is an application specific command rather
than a standard command. */
-#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card
+#define SDMMC_CMD_GEN_CMD 56U /*!< Used either to transfer a data block to the card or to get a data block from the card
for general purpose/application specific commands. */
-#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */
+#define SDMMC_CMD_NO_CMD 64U /*!< No command */
/**
* @brief Following commands are SD Card Specific commands.
* SDMMC_APP_CMD should be sent before sending these commands.
*/
-#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
+#define SDMMC_CMD_APP_SD_SET_BUSWIDTH 6U /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
widths are given in SCR register. */
-#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */
-#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
+#define SDMMC_CMD_SD_APP_STATUS 13U /*!< (ACMD13) Sends the SD status. */
+#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS 22U /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
32bit+CRC data block. */
-#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
+#define SDMMC_CMD_SD_APP_OP_COND 41U /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
send its operating condition register (OCR) content in the response on the CMD line. */
-#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
-#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */
-#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */
-#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */
+#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT 42U /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
+#define SDMMC_CMD_SD_APP_SEND_SCR 51U /*!< Reads the SD Configuration Register (SCR). */
+#define SDMMC_CMD_SDMMC_RW_DIRECT 52U /*!< For SD I/O card only, reserved for security specification. */
+#define SDMMC_CMD_SDMMC_RW_EXTENDED 53U /*!< For SD I/O card only, reserved for security specification. */
/**
* @brief Following commands are SD Card Specific security commands.
* SDMMC_CMD_APP_CMD should be sent before sending these commands.
*/
-#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U)
-#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U)
-#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U)
-#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U)
-#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U)
-#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U)
-#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U)
-#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U)
-#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U)
-#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U)
-#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U)
+#define SDMMC_CMD_SD_APP_GET_MKB 43U
+#define SDMMC_CMD_SD_APP_GET_MID 44U
+#define SDMMC_CMD_SD_APP_SET_CER_RN1 45U
+#define SDMMC_CMD_SD_APP_GET_CER_RN2 46U
+#define SDMMC_CMD_SD_APP_SET_CER_RES2 47U
+#define SDMMC_CMD_SD_APP_GET_CER_RES1 48U
+#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK 18U
+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK 25U
+#define SDMMC_CMD_SD_APP_SECURE_ERASE 38U
+#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA 49U
+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB 48U
/**
* @brief Masks for errors Card Status R1 (OCR Register)
*/
-#define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U)
-#define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U)
-#define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U)
-#define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U)
-#define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U)
-#define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U)
-#define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U)
-#define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U)
-#define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U)
-#define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U)
-#define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U)
-#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U)
-#define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U)
-#define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U)
-#define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U)
-#define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U)
-#define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U)
-#define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U)
-#define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U)
-#define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U)
+#define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U
+#define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U
+#define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U
+#define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U
+#define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U
+#define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U
+#define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U
+#define SDMMC_OCR_COM_CRC_FAILED 0x00800000U
+#define SDMMC_OCR_ILLEGAL_CMD 0x00400000U
+#define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U
+#define SDMMC_OCR_CC_ERROR 0x00100000U
+#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U
+#define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U
+#define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U
+#define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U
+#define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U
+#define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U
+#define SDMMC_OCR_ERASE_RESET 0x00002000U
+#define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U
+#define SDMMC_OCR_ERRORBITS 0xFDFFE008U
/**
* @brief Masks for R6 Response
*/
-#define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U)
-#define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U)
-#define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U)
+#define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U
+#define SDMMC_R6_ILLEGAL_CMD 0x00004000U
+#define SDMMC_R6_COM_CRC_FAILED 0x00008000U
-#define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U)
-#define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U)
-#define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U)
-#define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU)
+#define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U
+#define SDMMC_HIGH_CAPACITY 0x40000000U
+#define SDMMC_STD_CAPACITY 0x00000000U
+#define SDMMC_CHECK_PATTERN 0x000001AAU
+#define SD_SWITCH_1_8V_CAPACITY 0x01000000U
-#define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU)
+#define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU
-#define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU)
+#define SDMMC_MAX_TRIAL 0x0000FFFFU
-#define SDMMC_ALLZERO ((uint32_t)0x00000000U)
+#define SDMMC_ALLZERO 0x00000000U
-#define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U)
-#define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U)
-#define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U)
+#define SDMMC_WIDE_BUS_SUPPORT 0x00040000U
+#define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U
+#define SDMMC_CARD_LOCKED 0x02000000U
-#define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU)
+#define SDMMC_DATATIMEOUT 0xFFFFFFFFU
-#define SDMMC_0TO7BITS ((uint32_t)0x000000FFU)
-#define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U)
-#define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U)
-#define SDMMC_24TO31BITS ((uint32_t)0xFF000000U)
-#define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU)
+#define SDMMC_0TO7BITS 0x000000FFU
+#define SDMMC_8TO15BITS 0x0000FF00U
+#define SDMMC_16TO23BITS 0x00FF0000U
+#define SDMMC_24TO31BITS 0xFF000000U
+#define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU
-#define SDMMC_HALFFIFO ((uint32_t)0x00000008U)
-#define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U)
+#define SDMMC_HALFFIFO 0x00000008U
+#define SDMMC_HALFFIFOBYTES 0x00000020U
/**
* @brief Command Class supported
*/
-#define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U)
+#define SDMMC_CCCC_ERASE 0x00000020U
-#define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */
-#define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */
-
+#define SDMMC_CMDTIMEOUT 5000U /* Command send and response timeout */
+#define SDMMC_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */
+#define SDMMC_STOPTRANSFERTIMEOUT 100000000U /* Timeout for STOP TRANSMISSION command */
/** @defgroup SDMMC_LL_Clock_Edge Clock Edge
* @{
*/
-#define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U)
+#define SDMMC_CLOCK_EDGE_RISING 0x00000000U
#define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE
#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \
- ((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
+ ((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
/**
* @}
*/
@@ -333,11 +336,11 @@
/** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass
* @{
*/
-#define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000U)
+#define SDMMC_CLOCK_BYPASS_DISABLE 0x00000000U
#define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS
#define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \
- ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))
+ ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))
/**
* @}
*/
@@ -345,11 +348,11 @@
/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
* @{
*/
-#define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U)
+#define SDMMC_CLOCK_POWER_SAVE_DISABLE 0x00000000U
#define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV
#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \
- ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
+ ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
/**
* @}
*/
@@ -357,13 +360,13 @@
/** @defgroup SDMMC_LL_Bus_Wide Bus Width
* @{
*/
-#define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U)
+#define SDMMC_BUS_WIDE_1B 0x00000000U
#define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0
#define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1
#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \
- ((WIDE) == SDMMC_BUS_WIDE_4B) || \
- ((WIDE) == SDMMC_BUS_WIDE_8B))
+ ((WIDE) == SDMMC_BUS_WIDE_4B) || \
+ ((WIDE) == SDMMC_BUS_WIDE_8B))
/**
* @}
*/
@@ -371,11 +374,11 @@
/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
* @{
*/
-#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U)
+#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U
#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN
#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \
- ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
+ ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
/**
* @}
*/
@@ -383,7 +386,7 @@
/** @defgroup SDMMC_LL_Clock_Division Clock Division
* @{
*/
-#define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFF)
+#define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFFU)
/**
* @}
*/
@@ -391,7 +394,7 @@
/** @defgroup SDMMC_LL_Command_Index Command Index
* @{
*/
-#define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40)
+#define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40U)
/**
* @}
*/
@@ -399,13 +402,13 @@
/** @defgroup SDMMC_LL_Response_Type Response Type
* @{
*/
-#define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U)
+#define SDMMC_RESPONSE_NO 0x00000000U
#define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0
#define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP
#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \
- ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \
- ((RESPONSE) == SDMMC_RESPONSE_LONG))
+ ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \
+ ((RESPONSE) == SDMMC_RESPONSE_LONG))
/**
* @}
*/
@@ -413,13 +416,13 @@
/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
* @{
*/
-#define SDMMC_WAIT_NO ((uint32_t)0x00000000U)
+#define SDMMC_WAIT_NO 0x00000000U
#define SDMMC_WAIT_IT SDMMC_CMD_WAITINT
#define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND
#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \
- ((WAIT) == SDMMC_WAIT_IT) || \
- ((WAIT) == SDMMC_WAIT_PEND))
+ ((WAIT) == SDMMC_WAIT_IT) || \
+ ((WAIT) == SDMMC_WAIT_PEND))
/**
* @}
*/
@@ -427,11 +430,11 @@
/** @defgroup SDMMC_LL_CPSM_State CPSM State
* @{
*/
-#define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U)
+#define SDMMC_CPSM_DISABLE 0x00000000U
#define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN
#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \
- ((CPSM) == SDMMC_CPSM_ENABLE))
+ ((CPSM) == SDMMC_CPSM_ENABLE))
/**
* @}
*/
@@ -439,15 +442,15 @@
/** @defgroup SDMMC_LL_Response_Registers Response Register
* @{
*/
-#define SDMMC_RESP1 ((uint32_t)0x00000000U)
-#define SDMMC_RESP2 ((uint32_t)0x00000004U)
-#define SDMMC_RESP3 ((uint32_t)0x00000008U)
-#define SDMMC_RESP4 ((uint32_t)0x0000000C)
+#define SDMMC_RESP1 0x00000000U
+#define SDMMC_RESP2 0x00000004U
+#define SDMMC_RESP3 0x00000008U
+#define SDMMC_RESP4 0x0000000CU
#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \
- ((RESP) == SDMMC_RESP2) || \
- ((RESP) == SDMMC_RESP3) || \
- ((RESP) == SDMMC_RESP4))
+ ((RESP) == SDMMC_RESP2) || \
+ ((RESP) == SDMMC_RESP3) || \
+ ((RESP) == SDMMC_RESP4))
/**
* @}
*/
@@ -455,7 +458,7 @@
/** @defgroup SDMMC_LL_Data_Length Data Lenght
* @{
*/
-#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
+#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
/**
* @}
*/
@@ -463,7 +466,7 @@
/** @defgroup SDMMC_LL_Data_Block_Size Data Block Size
* @{
*/
-#define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U)
+#define SDMMC_DATABLOCK_SIZE_1B 0x00000000U
#define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0
#define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1
#define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1)
@@ -480,20 +483,20 @@
#define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
/**
* @}
*/
@@ -501,11 +504,11 @@
/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
* @{
*/
-#define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U)
-#define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR
+#define SDMMC_TRANSFER_DIR_TO_CARD 0x00000000U
+#define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR
#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \
- ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
+ ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
/**
* @}
*/
@@ -513,11 +516,11 @@
/** @defgroup SDMMC_LL_Transfer_Type Transfer Type
* @{
*/
-#define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U)
+#define SDMMC_TRANSFER_MODE_BLOCK 0x00000000U
#define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE
#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \
- ((MODE) == SDMMC_TRANSFER_MODE_STREAM))
+ ((MODE) == SDMMC_TRANSFER_MODE_STREAM))
/**
* @}
*/
@@ -525,11 +528,11 @@
/** @defgroup SDMMC_LL_DPSM_State DPSM State
* @{
*/
-#define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U)
+#define SDMMC_DPSM_DISABLE 0x00000000U
#define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN
#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\
- ((DPSM) == SDMMC_DPSM_ENABLE))
+ ((DPSM) == SDMMC_DPSM_ENABLE))
/**
* @}
*/
@@ -537,11 +540,11 @@
/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
* @{
*/
-#define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U)
+#define SDMMC_READ_WAIT_MODE_DATA2 0x00000000U
#define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD)
#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \
- ((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
+ ((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
/**
* @}
*/
@@ -549,28 +552,28 @@
/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
* @{
*/
-#define SDMMC_IT_CCRCFAIL SDMMC_STA_CCRCFAIL
-#define SDMMC_IT_DCRCFAIL SDMMC_STA_DCRCFAIL
-#define SDMMC_IT_CTIMEOUT SDMMC_STA_CTIMEOUT
-#define SDMMC_IT_DTIMEOUT SDMMC_STA_DTIMEOUT
-#define SDMMC_IT_TXUNDERR SDMMC_STA_TXUNDERR
-#define SDMMC_IT_RXOVERR SDMMC_STA_RXOVERR
-#define SDMMC_IT_CMDREND SDMMC_STA_CMDREND
-#define SDMMC_IT_CMDSENT SDMMC_STA_CMDSENT
-#define SDMMC_IT_DATAEND SDMMC_STA_DATAEND
-#define SDMMC_IT_DBCKEND SDMMC_STA_DBCKEND
-#define SDMMC_IT_CMDACT SDMMC_STA_CMDACT
-#define SDMMC_IT_TXACT SDMMC_STA_TXACT
-#define SDMMC_IT_RXACT SDMMC_STA_RXACT
-#define SDMMC_IT_TXFIFOHE SDMMC_STA_TXFIFOHE
-#define SDMMC_IT_RXFIFOHF SDMMC_STA_RXFIFOHF
-#define SDMMC_IT_TXFIFOF SDMMC_STA_TXFIFOF
-#define SDMMC_IT_RXFIFOF SDMMC_STA_RXFIFOF
-#define SDMMC_IT_TXFIFOE SDMMC_STA_TXFIFOE
-#define SDMMC_IT_RXFIFOE SDMMC_STA_RXFIFOE
-#define SDMMC_IT_TXDAVL SDMMC_STA_TXDAVL
-#define SDMMC_IT_RXDAVL SDMMC_STA_RXDAVL
-#define SDMMC_IT_SDIOIT SDMMC_STA_SDIOIT
+#define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE
+#define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE
+#define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE
+#define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE
+#define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE
+#define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE
+#define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE
+#define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE
+#define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE
+#define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE
+#define SDMMC_IT_CMDACT SDMMC_MASK_CMDACTIE
+#define SDMMC_IT_TXACT SDMMC_MASK_TXACTIE
+#define SDMMC_IT_RXACT SDMMC_MASK_RXACTIE
+#define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE
+#define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE
+#define SDMMC_IT_TXFIFOF SDMMC_MASK_TXFIFOFIE
+#define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE
+#define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE
+#define SDMMC_IT_RXFIFOE SDMMC_MASK_RXFIFOEIE
+#define SDMMC_IT_TXDAVL SDMMC_MASK_TXDAVLIE
+#define SDMMC_IT_RXDAVL SDMMC_MASK_RXDAVLIE
+#define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE
/**
* @}
*/
@@ -603,7 +606,13 @@
#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\
SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\
- SDMMC_FLAG_DBCKEND))
+ SDMMC_FLAG_DBCKEND | SDMMC_FLAG_SDIOIT))
+
+#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\
+ SDMMC_FLAG_CMDSENT))
+
+#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\
+ SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DBCKEND))
/**
* @}
*/
@@ -616,7 +625,7 @@
/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
* @{
*/
-
+
/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
* @brief SDMMC_LL registers bit address in the alias region
* @{
@@ -640,11 +649,10 @@
SDMMC_CMD_CPSMEN | SDMMC_CMD_SDIOSUSPEND))
/* SDMMC Initialization Frequency (400KHz max) */
-#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76)
+#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */
/* SDMMC Data Transfer Frequency (25MHz max) */
-#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0)
-
+#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV + 2) < 25MHz */
/**
* @}
*/
@@ -656,35 +664,36 @@
/**
* @brief Enable the SDMMC device.
- * @param __INSTANCE__ SDMMC Instance
+ * @param __INSTANCE__: SDMMC Instance
* @retval None
- */
+ */
#define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN)
/**
* @brief Disable the SDMMC device.
- * @param __INSTANCE__ SDMMC Instance
+ * @param __INSTANCE__: SDMMC Instance
* @retval None
*/
#define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN)
/**
* @brief Enable the SDMMC DMA transfer.
- * @param __INSTANCE__ SDMMC Instance
+ * @param __INSTANCE__: SDMMC Instance
* @retval None
- */
+ */
#define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN)
+
/**
* @brief Disable the SDMMC DMA transfer.
- * @param __INSTANCE__ SDMMC Instance
+ * @param __INSTANCE__: SDMMC Instance
* @retval None
*/
#define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN)
/**
* @brief Enable the SDMMC device interrupt.
- * @param __INSTANCE__ Pointer to SDMMC register base
- * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
+ * @param __INSTANCE__ : Pointer to SDMMC register base
+ * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be enabled.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -694,7 +703,7 @@
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
@@ -707,15 +716,15 @@
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
/**
* @brief Disable the SDMMC device interrupt.
- * @param __INSTANCE__ Pointer to SDMMC register base
- * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
+ * @param __INSTANCE__ : Pointer to SDMMC register base
+ * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be disabled.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -725,7 +734,7 @@
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
@@ -738,15 +747,15 @@
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
/**
* @brief Checks whether the specified SDMMC flag is set or not.
- * @param __INSTANCE__ Pointer to SDMMC register base
- * @param __FLAG__ specifies the flag to check.
+ * @param __INSTANCE__ : Pointer to SDMMC register base
+ * @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@@ -756,7 +765,7 @@
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDMMC_FLAG_CMDACT: Command transfer in progress
* @arg SDMMC_FLAG_TXACT: Data transmit in progress
@@ -769,16 +778,16 @@
* @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
* @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO
* @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO
- * @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received
+ * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received
* @retval The new state of SDMMC_FLAG (SET or RESET).
*/
-#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
+#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U)
/**
* @brief Clears the SDMMC pending flags.
- * @param __INSTANCE__ Pointer to SDMMC register base
- * @param __FLAG__ specifies the flag to clear.
+ * @param __INSTANCE__ : Pointer to SDMMC register base
+ * @param __FLAG__: specifies the flag to clear.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@@ -788,17 +797,17 @@
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received
+ * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received
* @retval None
*/
#define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
/**
* @brief Checks whether the specified SDMMC interrupt has occurred or not.
- * @param __INSTANCE__ Pointer to SDMMC register base
- * @param __INTERRUPT__ specifies the SDMMC interrupt source to check.
+ * @param __INSTANCE__ : Pointer to SDMMC register base
+ * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
* This parameter can be one of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -808,7 +817,7 @@
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
@@ -821,15 +830,15 @@
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
* @retval The new state of SDMMC_IT (SET or RESET).
*/
#define __SDMMC_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
/**
* @brief Clears the SDMMC's interrupt pending bits.
- * @param __INSTANCE__ Pointer to SDMMC register base
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * @param __INSTANCE__ : Pointer to SDMMC register base
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -839,68 +848,68 @@
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
- * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
+ * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
/**
* @brief Enable Start the SD I/O Read Wait operation.
- * @param __INSTANCE__ Pointer to SDMMC register base
+ * @param __INSTANCE__ : Pointer to SDMMC register base
* @retval None
- */
+ */
#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART)
/**
* @brief Disable Start the SD I/O Read Wait operations.
- * @param __INSTANCE__ Pointer to SDMMC register base
+ * @param __INSTANCE__ : Pointer to SDMMC register base
* @retval None
- */
+ */
#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
/**
* @brief Enable Start the SD I/O Read Wait operation.
- * @param __INSTANCE__ Pointer to SDMMC register base
+ * @param __INSTANCE__ : Pointer to SDMMC register base
* @retval None
- */
+ */
#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP)
/**
* @brief Disable Stop the SD I/O Read Wait operations.
- * @param __INSTANCE__ Pointer to SDMMC register base
+ * @param __INSTANCE__ : Pointer to SDMMC register base
* @retval None
- */
+ */
#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
/**
* @brief Enable the SD I/O Mode Operation.
- * @param __INSTANCE__ Pointer to SDMMC register base
+ * @param __INSTANCE__ : Pointer to SDMMC register base
* @retval None
- */
-#define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN)
+ */
+#define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN)
/**
* @brief Disable the SD I/O Mode Operation.
- * @param __INSTANCE__ Pointer to SDMMC register base
+ * @param __INSTANCE__ : Pointer to SDMMC register base
* @retval None
- */
+ */
#define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN)
/**
* @brief Enable the SD I/O Suspend command sending.
- * @param __INSTANCE__ Pointer to SDMMC register base
+ * @param __INSTANCE__ : Pointer to SDMMC register base
* @retval None
- */
+ */
#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND)
/**
* @brief Disable the SD I/O Suspend command sending.
- * @param __INSTANCE__ Pointer to SDMMC register base
+ * @param __INSTANCE__ : Pointer to SDMMC register base
* @retval None
- */
+ */
#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND)
-
+
/**
* @}
*/
@@ -970,7 +979,7 @@
uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
-uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t SdType);
+uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth);
uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx);
@@ -997,10 +1006,12 @@
* @}
*/
+#endif /* SDMMC1 */
+
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F7xx_LL_SDMMC_H */
+#endif /* STM32F7xx_LL_SDMMC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f7xx_ll_tim.h b/Inc/stm32f7xx_ll_tim.h
index 3da5961..5750eef 100644
--- a/Inc/stm32f7xx_ll_tim.h
+++ b/Inc/stm32f7xx_ll_tim.h
@@ -121,17 +121,7 @@
#define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
/* Generic bit definitions for TIMx_AF1 register */
-#define TIMx_AF1_BKINE TIM1_AF1_BKINE /*!< BRK BKINE input enable */
-#if defined(DFSDM1_Channel0)
-#define TIMx_AF1_BKDFBKE TIM1_AF1_BKDFBKE /*!< BRK DFSDM1_BREAK[0] enable */
-#endif /* DFSDM1_Channel0 */
#define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
-/* Generic bit definitions for TIMx_AF2 register */
-#define TIMx_AF2_BK2INE TIM1_AF2_BK2INE /*!< BRK B2KINE input enable */
-#if defined(DFSDM1_Channel0)
-#define TIMx_AF2_BK2DFBKE TIM1_AF2_BK2DFBKE /*!< BRK DFSDM_BREAK[0] enable */
-#endif /* DFSDM1_Channel0 */
-#define TIMx_AF2_BK2INP TIM1_AF2_BK2INP /*!< BRK BK2IN input polarity */
#endif /* TIM_BREAK_INPUT_SUPPORT */
/* Remap mask definitions */
@@ -176,14 +166,14 @@
* @retval none
*/
#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
-(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
+ (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
/** @brief Calculate the deadtime sampling period(in ps).
* @param __TIMCLK__ timer input clock frequency (in Hz).
@@ -194,9 +184,9 @@
* @retval none
*/
#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
- (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
- ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
- ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
+ (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
+ ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
+ ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
/**
* @}
*/
@@ -235,13 +225,14 @@
This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
- uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
+ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
reaches zero, an update event is generated and counting restarts
from the RCR value (N).
This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
- This parameter must be a number between 0x00 and 0xFF.
+ GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+ Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
} LL_TIM_InitTypeDef;
@@ -1157,7 +1148,7 @@
* @retval UIF status bit
*/
#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
- (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
+ (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
/**
* @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
@@ -1171,11 +1162,11 @@
* @retval DTG[0:7]
*/
#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
- ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
- (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
- (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
- (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
- 0U)
+ ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
+ (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
+ (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
+ (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
+ 0U)
/**
* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
@@ -1185,7 +1176,7 @@
* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
- (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
+ (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
/**
* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
@@ -1196,7 +1187,7 @@
* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
- ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
+ ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
/**
* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
@@ -1207,8 +1198,8 @@
* @retval Compare value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
-((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
- / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+ ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
+ / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
/**
* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
@@ -1220,8 +1211,8 @@
* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
- ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
- + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
+ ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
+ + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
/**
* @brief HELPER macro retrieving the ratio of the input capture prescaler
@@ -1234,7 +1225,7 @@
* @retval Input capture prescaler ratio (1, 2, 4 or 8)
*/
#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
- ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
+ ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
/**
@@ -1383,7 +1374,7 @@
/**
* @brief Set the timer counter counting mode.
- * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+ * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
* check whether or not the counter mode selection feature is supported
* by a timer instance.
* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
@@ -1407,7 +1398,7 @@
/**
* @brief Get actual counter mode.
- * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+ * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
* check whether or not the counter mode selection feature is supported
* by a timer instance.
* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
@@ -1444,7 +1435,7 @@
*/
__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
{
- CLEAR_BIT(TIMx->CR1,TIM_CR1_ARPE);
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
}
/**
@@ -1460,7 +1451,7 @@
/**
* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
- * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
* whether or not the clock division feature is supported by the timer
* instance.
* @rmtoll CR1 CKD LL_TIM_SetClockDivision
@@ -1478,7 +1469,7 @@
/**
* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
- * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
* whether or not the clock division feature is supported by the timer
* instance.
* @rmtoll CR1 CKD LL_TIM_GetClockDivision
@@ -1495,7 +1486,7 @@
/**
* @brief Set the counter value.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @rmtoll CNT CNT LL_TIM_SetCounter
* @param TIMx Timer instance
@@ -1509,7 +1500,7 @@
/**
* @brief Get the counter value.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @rmtoll CNT CNT LL_TIM_GetCounter
* @param TIMx Timer instance
@@ -1563,7 +1554,7 @@
/**
* @brief Set the auto-reload value.
* @note The counter is blocked while the auto-reload value is null.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
* @rmtoll ARR ARR LL_TIM_SetAutoReload
@@ -1579,7 +1570,7 @@
/**
* @brief Get the auto-reload value.
* @rmtoll ARR ARR LL_TIM_GetAutoReload
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @param TIMx Timer instance
* @retval Auto-reload value
@@ -1592,11 +1583,11 @@
/**
* @brief Set the repetition counter value.
* @note For advanced timer instances RepetitionCounter can be up to 65535.
- * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a repetition counter.
* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
* @param TIMx Timer instance
- * @param RepetitionCounter between Min_Data=0 and Max_Data=255
+ * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
@@ -1606,7 +1597,7 @@
/**
* @brief Get the repetition counter value.
- * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a repetition counter.
* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
* @param TIMx Timer instance
@@ -1641,6 +1632,16 @@
}
/**
+ * @brief Indicate whether update interrupt flag (UIF) copy is set.
+ * @param Counter Counter value
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter)
+{
+ return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
+}
+
+/**
* @}
*/
@@ -1652,7 +1653,7 @@
* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
* they are updated only when a commutation event (COM) occurs.
* @note Only on channels that have a complementary output.
- * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
* @param TIMx Timer instance
@@ -1665,7 +1666,7 @@
/**
* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
- * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
* @param TIMx Timer instance
@@ -1678,7 +1679,7 @@
/**
* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
- * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
* @param TIMx Timer instance
@@ -1722,7 +1723,7 @@
/**
* @brief Set the lock level to freeze the
* configuration of several capture/compare parameters.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* the lock mechanism is supported by a timer instance.
* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
* @param TIMx Timer instance
@@ -2024,7 +2025,7 @@
/**
* @brief Set the IDLE state of an output channel
* @note This function is significant only for the timer instances
- * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
+ * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
* can be used to check whether or not a timer instance provides
* a break input.
* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
@@ -2248,7 +2249,7 @@
/**
* @brief Enable clearing the output channel on an external event.
* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
- * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can clear the OCxREF signal on an external event.
* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
@@ -2275,7 +2276,7 @@
/**
* @brief Disable clearing the output channel on an external event.
- * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can clear the OCxREF signal on an external event.
* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
@@ -2304,7 +2305,7 @@
* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
* @note This function enables clearing the output channel on an external event.
* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
- * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can clear the OCxREF signal on an external event.
* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
@@ -2332,7 +2333,7 @@
/**
* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* dead-time insertion feature is supported by a timer instance.
* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
@@ -2348,9 +2349,9 @@
/**
* @brief Set compare value for output channel 1 (TIMx_CCR1).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* output channel 1 is supported by a timer instance.
* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
* @param TIMx Timer instance
@@ -2365,9 +2366,9 @@
/**
* @brief Set compare value for output channel 2 (TIMx_CCR2).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* output channel 2 is supported by a timer instance.
* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
* @param TIMx Timer instance
@@ -2382,9 +2383,9 @@
/**
* @brief Set compare value for output channel 3 (TIMx_CCR3).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* output channel is supported by a timer instance.
* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
* @param TIMx Timer instance
@@ -2399,9 +2400,9 @@
/**
* @brief Set compare value for output channel 4 (TIMx_CCR4).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* output channel 4 is supported by a timer instance.
* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
* @param TIMx Timer instance
@@ -2415,7 +2416,7 @@
/**
* @brief Set compare value for output channel 5 (TIMx_CCR5).
- * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
* output channel 5 is supported by a timer instance.
* @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
* @param TIMx Timer instance
@@ -2429,7 +2430,7 @@
/**
* @brief Set compare value for output channel 6 (TIMx_CCR6).
- * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
* output channel 6 is supported by a timer instance.
* @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
* @param TIMx Timer instance
@@ -2444,9 +2445,9 @@
/**
* @brief Get compare value (TIMx_CCR1) set for output channel 1.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* output channel 1 is supported by a timer instance.
* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
* @param TIMx Timer instance
@@ -2460,9 +2461,9 @@
/**
* @brief Get compare value (TIMx_CCR2) set for output channel 2.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* output channel 2 is supported by a timer instance.
* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
* @param TIMx Timer instance
@@ -2476,9 +2477,9 @@
/**
* @brief Get compare value (TIMx_CCR3) set for output channel 3.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* output channel 3 is supported by a timer instance.
* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
* @param TIMx Timer instance
@@ -2492,9 +2493,9 @@
/**
* @brief Get compare value (TIMx_CCR4) set for output channel 4.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* output channel 4 is supported by a timer instance.
* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
* @param TIMx Timer instance
@@ -2507,7 +2508,7 @@
/**
* @brief Get compare value (TIMx_CCR5) set for output channel 5.
- * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
* output channel 5 is supported by a timer instance.
* @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
* @param TIMx Timer instance
@@ -2520,7 +2521,7 @@
/**
* @brief Get compare value (TIMx_CCR6) set for output channel 6.
- * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
* output channel 6 is supported by a timer instance.
* @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
* @param TIMx Timer instance
@@ -2533,7 +2534,7 @@
/**
* @brief Select on which reference signal the OC5REF is combined to.
- * @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the combined 3-phase PWM mode.
* @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
* CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
@@ -2837,7 +2838,7 @@
/**
* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
- * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an XOR input.
* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
* @param TIMx Timer instance
@@ -2850,7 +2851,7 @@
/**
* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
- * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an XOR input.
* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
* @param TIMx Timer instance
@@ -2863,7 +2864,7 @@
/**
* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
- * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an XOR input.
* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
* @param TIMx Timer instance
@@ -2877,9 +2878,9 @@
/**
* @brief Get captured value for input channel 1.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* input channel 1 is supported by a timer instance.
* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
* @param TIMx Timer instance
@@ -2893,9 +2894,9 @@
/**
* @brief Get captured value for input channel 2.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* input channel 2 is supported by a timer instance.
* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
* @param TIMx Timer instance
@@ -2909,9 +2910,9 @@
/**
* @brief Get captured value for input channel 3.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* input channel 3 is supported by a timer instance.
* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
* @param TIMx Timer instance
@@ -2925,9 +2926,9 @@
/**
* @brief Get captured value for input channel 4.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* input channel 4 is supported by a timer instance.
* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
* @param TIMx Timer instance
@@ -2948,7 +2949,7 @@
/**
* @brief Enable external clock mode 2.
* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
* @param TIMx Timer instance
@@ -2961,7 +2962,7 @@
/**
* @brief Disable external clock mode 2.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
* @param TIMx Timer instance
@@ -2974,7 +2975,7 @@
/**
* @brief Indicate whether external clock mode 2 is enabled.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
* @param TIMx Timer instance
@@ -2991,9 +2992,9 @@
* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
* function. This timer input must be configured by calling
* the @ref LL_TIM_IC_Config() function.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode1.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
* SMCR ECE LL_TIM_SetClockSource
@@ -3011,7 +3012,7 @@
/**
* @brief Set the encoder interface mode.
- * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the encoder mode.
* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
* @param TIMx Timer instance
@@ -3035,7 +3036,7 @@
*/
/**
* @brief Set the trigger output (TRGO) used for timer synchronization .
- * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance can operate as a master timer.
* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
* @param TIMx Timer instance
@@ -3057,7 +3058,7 @@
/**
* @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
- * @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance can be used for ADC synchronization.
* @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
* @param TIMx Timer Instance
@@ -3087,7 +3088,7 @@
/**
* @brief Set the synchronization mode of a slave timer.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
* @param TIMx Timer instance
@@ -3106,7 +3107,7 @@
/**
* @brief Set the selects the trigger input to be used to synchronize the counter.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR TS LL_TIM_SetTriggerInput
* @param TIMx Timer instance
@@ -3128,7 +3129,7 @@
/**
* @brief Enable the Master/Slave mode.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
* @param TIMx Timer instance
@@ -3141,7 +3142,7 @@
/**
* @brief Disable the Master/Slave mode.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
* @param TIMx Timer instance
@@ -3154,7 +3155,7 @@
/**
* @brief Indicates whether the Master/Slave mode is enabled.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
* @param TIMx Timer instance
@@ -3167,7 +3168,7 @@
/**
* @brief Configure the external trigger (ETR) input.
- * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an external trigger input.
* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
* SMCR ETPS LL_TIM_ConfigETR\n
@@ -3215,7 +3216,7 @@
*/
/**
* @brief Enable the break function.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR BKE LL_TIM_EnableBRK
* @param TIMx Timer instance
@@ -3230,7 +3231,7 @@
* @brief Disable the break function.
* @rmtoll BDTR BKE LL_TIM_DisableBRK
* @param TIMx Timer instance
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @retval None
*/
@@ -3241,7 +3242,7 @@
/**
* @brief Configure the break input.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
* BDTR BKF LL_TIM_ConfigBRK
@@ -3268,14 +3269,15 @@
* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
* @retval None
*/
-__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter)
+__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
+ uint32_t BreakFilter)
{
MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
}
/**
* @brief Enable the break 2 function.
- * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a second break input.
* @rmtoll BDTR BK2E LL_TIM_EnableBRK2
* @param TIMx Timer instance
@@ -3288,7 +3290,7 @@
/**
* @brief Disable the break 2 function.
- * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a second break input.
* @rmtoll BDTR BK2E LL_TIM_DisableBRK2
* @param TIMx Timer instance
@@ -3301,7 +3303,7 @@
/**
* @brief Configure the break 2 input.
- * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a second break input.
* @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
* BDTR BK2F LL_TIM_ConfigBRK2
@@ -3335,7 +3337,7 @@
/**
* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
* BDTR OSSR LL_TIM_SetOffStates
@@ -3355,7 +3357,7 @@
/**
* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
* @param TIMx Timer instance
@@ -3368,7 +3370,7 @@
/**
* @brief Disable automatic output (MOE can be set only by software).
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
* @param TIMx Timer instance
@@ -3381,7 +3383,7 @@
/**
* @brief Indicate whether automatic output is enabled.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
* @param TIMx Timer instance
@@ -3396,7 +3398,7 @@
* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
* software and is reset in case of break or break2 event
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
* @param TIMx Timer instance
@@ -3411,7 +3413,7 @@
* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
* software and is reset in case of break or break2 event.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
* @param TIMx Timer instance
@@ -3424,7 +3426,7 @@
/**
* @brief Indicates whether outputs are enabled.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
* @param TIMx Timer instance
@@ -3438,7 +3440,7 @@
#if defined(TIM_BREAK_INPUT_SUPPORT)
/**
* @brief Enable the signals connected to the designated timer break input.
- * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+ * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
* or not a timer instance allows for break input selection.
* @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
* AF1 BKDFBKE LL_TIM_EnableBreakInputSource\n
@@ -3461,7 +3463,7 @@
/**
* @brief Disable the signals connected to the designated timer break input.
- * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+ * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
* or not a timer instance allows for break input selection.
* @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
* AF1 BKDFBKE LL_TIM_DisableBreakInputSource\n
@@ -3484,7 +3486,7 @@
/**
* @brief Set the polarity of the break signal for the timer break input.
- * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+ * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
* or not a timer instance allows for break input selection.
* @rmtoll AF1 BKINE LL_TIM_SetBreakInputSourcePolarity\n
* AF1 BKDFBKE LL_TIM_SetBreakInputSourcePolarity\n
@@ -3518,7 +3520,7 @@
*/
/**
* @brief Configures the timer DMA burst feature.
- * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
+ * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
* not a timer instance supports the DMA burst mode.
* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
* DCR DBA LL_TIM_ConfigDMABurst
@@ -3584,7 +3586,7 @@
*/
/**
* @brief Remap TIM inputs (input channel, internal/external triggers).
- * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
* a some timer inputs can be remapped.
* @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
* TIM5_OR TI4_RMP LL_TIM_SetRemap\n
diff --git a/Inc/stm32f7xx_ll_usart.h b/Inc/stm32f7xx_ll_usart.h
index df5db5e..5a89688 100644
--- a/Inc/stm32f7xx_ll_usart.h
+++ b/Inc/stm32f7xx_ll_usart.h
@@ -42,13 +42,6 @@
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
-/** @defgroup USART_LL_Private_Constants USART Private Constants
- * @{
- */
-/**
- * @}
- */
-
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup USART_LL_Private_Macros USART Private Macros
@@ -156,18 +149,21 @@
*/
#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */
#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */
-#define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise error detected flag */
+#define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise error detected flag */
#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */
#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */
#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */
#if defined(USART_TCBGT_SUPPORT)
#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time flag */
-#endif
+#endif /* USART_TCBGT_SUPPORT */
#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection flag */
#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */
#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout flag */
#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block flag */
#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */
+#if defined(USART_CR1_UESM)
+#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */
+#endif /* USART_CR1_UESM */
/**
* @}
*/
@@ -195,10 +191,16 @@
#define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
#define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
#define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
+#if defined(USART_CR1_UESM)
+#define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
+#endif /* USART_CR1_UESM */
#define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
+#if defined(USART_ISR_REACK)
+#define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
+#endif /* USART_ISR_REACK */
#if defined(USART_TCBGT_SUPPORT)
#define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission complete before guard time completion flag */
-#endif
+#endif /* USART_TCBGT_SUPPORT */
/**
* @}
*/
@@ -218,9 +220,12 @@
#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */
#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
+#if defined(USART_CR1_UESM)
+#define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
+#endif /* USART_CR1_UESM */
#if defined(USART_TCBGT_SUPPORT)
#define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission complete before guard time interrupt enable */
-#endif
+#endif /* USART_TCBGT_SUPPORT */
/**
* @}
*/
@@ -400,6 +405,18 @@
* @}
*/
+#if defined(USART_CR1_UESM)
+/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
+ * @{
+ */
+#define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */
+#define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */
+#define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */
+/**
+ * @}
+ */
+
+#endif /* USART_CR1_UESM */
/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
* @{
*/
@@ -480,7 +497,8 @@
* @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
*/
-#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2U) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2U)\
+ + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
/**
* @brief Compute USARTDIV value according to Peripheral Clock and
@@ -545,6 +563,87 @@
return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
}
+#if defined(USART_CR1_UESM)
+/**
+ * @brief USART enabled in STOP Mode.
+ * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
+ * USART clock selection is HSI or LSE in RCC.
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 UESM LL_USART_EnableInStopMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+ * @brief USART disabled in STOP Mode.
+ * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 UESM LL_USART_DisableInStopMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+ * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
+}
+
+#if defined(USART_CR3_UCESM)
+/**
+ * @brief USART Clock enabled in STOP Mode
+ * @note When this function is called, USART Clock is enabled while in STOP mode
+ * @rmtoll CR3 UCESM LL_USART_EnableClockInStopMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableClockInStopMode(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_UCESM);
+}
+
+/**
+ * @brief USART clock disabled in STOP Mode
+ * @note When this function is called, USART Clock is disabled while in STOP mode
+ * @rmtoll CR3 UCESM LL_USART_DisableClockInStopMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableClockInStopMode(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_UCESM);
+}
+
+/**
+ * @brief Indicate if USART clock is enabled in STOP Mode
+ * @rmtoll CR3 UCESM LL_USART_IsClockEnabledInStopMode
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsClockEnabledInStopMode(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM));
+}
+
+#endif /* USART_CR3_UCESM */
+#endif /* USART_CR1_UESM*/
/**
* @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
* @rmtoll CR1 RE LL_USART_EnableDirectionRx
@@ -1461,6 +1560,41 @@
return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
}
+#if defined(USART_CR1_UESM)
+/**
+ * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 WUS LL_USART_SetWKUPType
+ * @param USARTx USART Instance
+ * @param Type This parameter can be one of the following values:
+ * @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+ * @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+ * @arg @ref LL_USART_WAKEUP_ON_RXNE
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
+{
+ MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
+}
+
+/**
+ * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 WUS LL_USART_GetWKUPType
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+ * @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+ * @arg @ref LL_USART_WAKEUP_ON_RXNE
+ */
+__STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
+}
+
+#endif /* USART_CR1_UESM */
/**
* @brief Configure USART BRR register for achieving expected Baud Rate value.
* @note Compute and set USARTDIV value in BRR Register (full BRR content)
@@ -1480,7 +1614,7 @@
__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,
uint32_t BaudRate)
{
- register uint32_t usartdiv;
+ uint32_t usartdiv;
register uint32_t brrtemp;
if (OverSampling == LL_USART_OVERSAMPLING_8)
@@ -2161,7 +2295,8 @@
{
/* In Asynchronous mode, the following bits must be kept cleared:
- LINEN, CLKEN bits in the USART_CR2 register,
- - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
+ - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
}
@@ -2197,7 +2332,8 @@
{
/* In Synchronous mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register,
- - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
+ - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
/* set the UART/USART in Synchronous mode */
@@ -2237,7 +2373,8 @@
{
/* In LIN mode, the following bits must be kept cleared:
- STOP and CLKEN bits in the USART_CR2 register,
- - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
+ - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
/* Set the UART/USART in LIN mode */
@@ -2275,7 +2412,8 @@
{
/* In Half Duplex mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN and IREN bits in the USART_CR3 register.*/
+ - SCEN and IREN bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
/* set the UART/USART in Half Duplex mode */
@@ -2315,7 +2453,8 @@
{
/* In Smartcard mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register,
- - IREN and HDSEL bits in the USART_CR3 register.*/
+ - IREN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
/* Configure Stop bits to 1.5 bits */
@@ -2358,7 +2497,8 @@
{
/* In IRDA mode, the following bits must be kept cleared:
- LINEN, STOP and CLKEN bits in the USART_CR2 register,
- - SCEN and HDSEL bits in the USART_CR3 register.*/
+ - SCEN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
/* set the UART/USART in IRDA mode */
@@ -2396,7 +2536,8 @@
{
/* In Multi Processor mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
+ - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
}
@@ -2630,6 +2771,21 @@
return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
}
+#if defined(USART_CR1_UESM)
+/**
+ * @brief Check if the USART Wake Up from stop mode Flag is set or not
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
+}
+
+#endif /* USART_CR1_UESM */
/**
* @brief Check if the USART Transmit Enable Acknowledge Flag is set or not
* @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK
@@ -2641,6 +2797,19 @@
return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
}
+#if defined(USART_ISR_REACK)
+/**
+ * @brief Check if the USART Receive Enable Acknowledge Flag is set or not
+ * @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
+}
+
+#endif/* USART_ISR_REACK */
#if defined(USART_TCBGT_SUPPORT)
/* Function available only on devices supporting Transmit Complete before Guard Time feature */
/**
@@ -2653,8 +2822,8 @@
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);
}
-#endif
+#endif /* USART_TCBGT_SUPPORT */
/**
* @brief Clear Parity Error Flag
* @rmtoll ICR PECF LL_USART_ClearFlag_PE
@@ -2733,7 +2902,7 @@
{
WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
}
-#endif
+#endif /* USART_TCBGT_SUPPORT */
/**
* @brief Clear LIN Break Detection Flag
@@ -2796,6 +2965,21 @@
WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
}
+#if defined(USART_CR1_UESM)
+/**
+ * @brief Clear Wake Up from stop mode Flag
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
+}
+
+#endif /* USART_CR1_UESM */
/**
* @}
*/
@@ -2935,6 +3119,21 @@
SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
}
+#if defined(USART_CR1_UESM)
+/**
+ * @brief Enable Wake Up from Stop Mode Interrupt
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+#endif /* USART_CR1_UESM */
#if defined(USART_TCBGT_SUPPORT)
/* Function available only on devices supporting Transmit Complete before Guard Time feature */
/**
@@ -2949,7 +3148,7 @@
{
SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
}
-#endif
+#endif /* USART_TCBGT_SUPPORT */
/**
* @brief Disable IDLE Interrupt
@@ -3082,6 +3281,21 @@
CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
}
+#if defined(USART_CR1_UESM)
+/**
+ * @brief Disable Wake Up from Stop Mode Interrupt
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+#endif /* USART_CR1_UESM */
#if defined(USART_TCBGT_SUPPORT)
/* Function available only on devices supporting Transmit Complete before Guard Time feature */
/**
@@ -3096,7 +3310,7 @@
{
CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
}
-#endif
+#endif /* USART_TCBGT_SUPPORT */
/**
* @brief Check if the USART IDLE Interrupt source is enabled or disabled.
@@ -3225,6 +3439,21 @@
return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
}
+#if defined(USART_CR1_UESM)
+/**
+ * @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
+}
+
+#endif /* USART_CR1_UESM */
#if defined(USART_TCBGT_SUPPORT)
/* Function available only on devices supporting Transmit Complete before Guard Time feature */
/**
@@ -3239,7 +3468,7 @@
{
return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL);
}
-#endif
+#endif /* USART_TCBGT_SUPPORT */
/**
* @}
@@ -3365,12 +3594,12 @@
if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
{
/* return address of TDR register */
- data_reg_addr = (uint32_t) & (USARTx->TDR);
+ data_reg_addr = (uint32_t) &(USARTx->TDR);
}
else
{
/* return address of RDR register */
- data_reg_addr = (uint32_t) & (USARTx->RDR);
+ data_reg_addr = (uint32_t) &(USARTx->RDR);
}
return data_reg_addr;
@@ -3392,7 +3621,7 @@
*/
__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
{
- return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
+ return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
}
/**
diff --git a/Inc/stm32f7xx_ll_usb.h b/Inc/stm32f7xx_ll_usb.h
index d53f10c..6d3769c 100644
--- a/Inc/stm32f7xx_ll_usb.h
+++ b/Inc/stm32f7xx_ll_usb.h
@@ -155,7 +155,7 @@
typedef struct
{
- uint8_t dev_addr ; /*!< USB device address.
+ uint8_t dev_addr; /*!< USB device address.
This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
uint8_t ch_num; /*!< Host channel number.
@@ -199,10 +199,10 @@
uint32_t ErrCnt; /*!< Host channel error count.*/
- USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
+ USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
- USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
+ USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
} USB_OTG_HCTypeDef;
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
@@ -234,6 +234,18 @@
* @}
*/
+/** @defgroup USB_LL Device Speed
+ * @{
+ */
+#define USBD_HS_SPEED 0U
+#define USBD_HSINFS_SPEED 1U
+#define USBH_HS_SPEED 0U
+#define USBD_FS_SPEED 2U
+#define USBH_FSLS_SPEED 1U
+/**
+ * @}
+ */
+
/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed
* @{
*/
@@ -252,7 +264,7 @@
#define USB_OTG_HS_EMBEDDED_PHY 3U
#if !defined (USB_HS_PHYC_TUNE_VALUE)
-#define USB_HS_PHYC_TUNE_VALUE 0x00000F13U /*!< Value of USB HS PHY Tune */
+#define USB_HS_PHYC_TUNE_VALUE 0x00000F13U /*!< Value of USB HS PHY Tune */
#endif /* USB_HS_PHYC_TUNE_VALUE */
/**
* @}
@@ -262,11 +274,11 @@
* @{
*/
#ifndef USBD_HS_TRDT_VALUE
-#define USBD_HS_TRDT_VALUE 9U
+#define USBD_HS_TRDT_VALUE 9U
#endif /* USBD_HS_TRDT_VALUE */
#ifndef USBD_FS_TRDT_VALUE
-#define USBD_FS_TRDT_VALUE 5U
-#define USBD_DEFAULT_TRDT_VALUE 9U
+#define USBD_FS_TRDT_VALUE 5U
+#define USBD_DEFAULT_TRDT_VALUE 9U
#endif /* USBD_HS_TRDT_VALUE */
/**
* @}
@@ -275,9 +287,9 @@
/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
* @{
*/
-#define USB_OTG_HS_MAX_PACKET_SIZE 512U
-#define USB_OTG_FS_MAX_PACKET_SIZE 64U
-#define USB_OTG_MAX_EP0_SIZE 64U
+#define USB_OTG_HS_MAX_PACKET_SIZE 512U
+#define USB_OTG_FS_MAX_PACKET_SIZE 64U
+#define USB_OTG_MAX_EP0_SIZE 64U
/**
* @}
*/
@@ -287,7 +299,6 @@
*/
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1)
#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1)
-#define DSTS_ENUMSPD_LS_PHY_6MHZ (2U << 1)
#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1)
/**
* @}
@@ -397,7 +408,7 @@
#define USBPHYC ((USBPHYC_GlobalTypeDef *)((uint32_t )USB_PHY_HS_CONTROLLER_BASE))
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
-#define EP_ADDR_MSK 0xFU
+#define EP_ADDR_MSK 0xFU
/**
* @}
*/
@@ -462,13 +473,9 @@
HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
- uint8_t ch_num,
- uint8_t epnum,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps);
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
+ uint8_t epnum, uint8_t dev_address, uint8_t speed,
+ uint8_t ep_type, uint16_t mps);
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
diff --git a/Inc/stm32f7xx_ll_wwdg.h b/Inc/stm32f7xx_ll_wwdg.h
index 620a524..1661630 100644
--- a/Inc/stm32f7xx_ll_wwdg.h
+++ b/Inc/stm32f7xx_ll_wwdg.h
@@ -58,8 +58,8 @@
*/
/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
-* @{
-*/
+ * @{
+ */
#define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
@@ -175,7 +175,7 @@
* @arg @ref LL_WWDG_PRESCALER_2
* @arg @ref LL_WWDG_PRESCALER_4
* @arg @ref LL_WWDG_PRESCALER_8
-* @retval None
+ * @retval None
*/
__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
{
@@ -314,6 +314,6 @@
}
#endif
-#endif /* __STM32F7xx_LL_WWDG_H */
+#endif /* STM32F7xx_LL_WWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/License.md b/License.md
index d95c1db..cadebec 100644
--- a/License.md
+++ b/License.md
@@ -1,3 +1,3 @@
# Copyright (c) 2017 STMicroelectronics
-This software component is licensed by STMicroelectronics under the **BSD 3-Clause** license. You may not use this file except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/BSD-3-Clause).
+This software component is licensed by STMicroelectronics under the **BSD-3-Clause** license. You may not use this file except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/BSD-3-Clause).
diff --git a/README.md b/README.md
index 31207c8..f955c4f 100644
--- a/README.md
+++ b/README.md
@@ -5,14 +5,14 @@
**STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost.
**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform, delivered for each STM32 series.
- * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product
- * The STM32 HAL-LL drivers : an abstraction drivers layer, the API ensuring maximized portability across the STM32 portfolio
- * The BSP Drivers of each evaluation or demonstration board provided by this STM32 series
- * A consistent set of middlewares components such as RTOS, USB, FatFS, Graphics, STM32_TouchSensing_Library ...
- * A full set of software projects (basic examples, applications or demonstrations) for each board provided by this STM32 series
+ * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product.
+ * The STM32 HAL-LL drivers : an abstraction drivers layer, the API ensuring maximized portability across the STM32 portfolio.
+ * The BSP Drivers of each evaluation or demonstration board provided by this STM32 series.
+ * A consistent set of middlewares components such as RTOS, USB, FatFS, Graphics, STM32_TouchSensing_Library...
+ * A full set of software projects (basic examples, applications or demonstrations) for each board provided by this STM32 series.
Two models of publication are proposed for the STM32Cube embedded software:
- * The monolithic **MCU Package** : all STM32Cube software modules of one STM32 series are present (Drivers, Middlewares, Projects, Utilities) in the repo (usual name **STM32Cubexx**, xx corresponding to the STM32 series)
+ * The monolithic **MCU Package** : all STM32Cube software modules of one STM32 series are present (Drivers, Middlewares, Projects, Utilities) in the repo (usual name **STM32Cubexx**, xx corresponding to the STM32 series).
* The **MCU component** : progressively from November 2019, each STM32Cube software module being part of the STM32Cube MCU Package, will be delivered as an individual repo, allowing the user to select and get only the required software functions.
## Description
@@ -23,9 +23,13 @@
Copyright (c) 2017 STMicroelectronics.
-This software component is licensed by STMicroelectronics under BSD 3-Clause license. You may not use this file except in compliance with the License.
+This software component is licensed by STMicroelectronics under BSD-3-Clause license. You may not use this file except in compliance with the License.
You may obtain a copy of the License [here](https://opensource.org/licenses/BSD-3-Clause).
+## Release note
+
+Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/stm32f7xx_hal_driver/blob/master/Release_Notes.html).
+
## Compatibility information
In this table, you can find the successive versions of this HAL-LL Driver component, in line with the corresponding versions of the full MCU package:
@@ -34,12 +38,13 @@
HAL Driver F7 | CMSIS Device F7 | CMSIS Core | Was delivered in the full MCU package
------------- | --------------- | ---------- | -------------------------------------
-Tag v1.2.7 | Tag v1.2.4 | Tag v5.4.0_cm7 | Tag v1.15.0 (and following, if any, till next new tag)
+Tag v1.2.7 | Tag v1.2.4 | Tag v5.4.0_cm7 | Tag v1.15.0 (and following, if any, till next tag)
+Tag v1.2.8 | Tag v1.2.5 | Tag v5.4.0_cm7 | Tag v1.16.0 (and following, if any, till next tag)
The full **STM32CubeF7** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeF7).
## Troubleshooting
-If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/stm32f7xx_hal_driver/issues/new).
+If you have any issue with the **Software content** of this repository, you can file an issue into the firmware repository [STM32CubeF7](https://github.com/STMicroelectronics/STM32CubeF7/issues/new/choose).
For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
diff --git a/Release_Notes.html b/Release_Notes.html
index 2801b71..2608ed2 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -652,7 +652,8 @@
{margin-bottom:0in;}
-->
</style><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman","serif";} </style> <![endif]--><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="7170"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]-->
-<meta content="MCD Application Team" name="author"></head><body link="blue" vlink="blue">
+<meta content="MCD Application Team" name="author"></head>
+<body link="blue" vlink="blue">
<div class="WordSection1">
<p class="MsoNormal"><span style="font-family: "Arial","sans-serif";"><o:p> </o:p></span></p>
<div align="center">
@@ -688,8 +689,138 @@
<tbody>
<tr>
<td style="padding: 0in;" valign="top">
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span>
- </h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 241px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.7/ 08-February-2019</span></h3>
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span>
+ </h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 241px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.8/ 13-February-2020</span></h3>
+ <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b><u><span style="color: black; font-family: Verdana; font-size: 10pt;">Main Changes</span></u></b></p>
+ <ul style="color: rgb(0, 0, 0); text-transform: none; text-indent: 0px; letter-spacing: normal; margin-top: 0cm; margin-bottom: 0in; word-spacing: 0px; white-space: normal;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">General updates to fix known defects and enhancements implementation</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL/LL GPIO </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;"><o:p></o:p></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update GPIO
+ initialization sequence<b> </b>to avoid unwanted pulse on GPIO Pin's</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL I2C </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;"><o:p></o:p></span></li><ul><li class="MsoNormal" style="color: black; margin-bottom: 0.0001pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update
+ HAL_I2C_EV_IRQHandler() API to fix I2C send break issue </span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li></ul><ul style="margin-top: 0cm;" type="disc"><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add
+ additional check on hi2c->hdmatx,
+ hdmatx->XferCpltCallback, hi2c->hdmarx,
+ hdmarx->XferCpltCallback in I2C_Master_SB() API to
+ avoid enabling DMA request when IT mode is used.</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li></ul></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update
+ HAL_I2C_ER_IRQHandler() API to fix acknowledge failure issue with
+ I2C memory IT processes</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li></ul><ul style="margin-top: 0cm;" type="disc"><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> Add stop
+ condition generation when NACK occurs.</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li></ul></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL_I2C_Init()
+ API to force software reset before setting new I2C configuration</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update
+ HAL I2C processes to report ErrorCode when wrong I2C start condition
+ occurs</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li></ul><ul style="margin-top: 0cm;" type="disc"><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> Add
+ new ErrorCode define: HAL_I2C_WRONG_START</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> Set ErrorCode
+ parameter in I2C handle to HAL_I2C_WRONG_START</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li></ul></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update I2C_DMAXferCplt(),
+ I2C_DMAError() and I2C_DMAAbort() APIs to fix hardfault issue when hdmatx
+ and hdmarx parameters in i2c handle aren't initialized (NULL pointer).</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li></ul><ul style="margin-top: 0cm;" type="disc"><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add
+ additional check on hi2c->hdmtx and hi2c->hdmarx before
+ resetting DMA Tx/Rx complete callback</span></li></ul></ul></ul>
+
+<ul style="color: rgb(0, 0, 0); text-transform: none; text-indent: 0px; letter-spacing: normal; margin-top: 0cm; margin-bottom: 0in; word-spacing: 0px; white-space: normal;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;"><span style="font-weight: bold;">HAL ADC </span>Update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">Add "ADC_INTERNAL_NONE" channel to disable the VBAT & TSVREFE channel.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;"><span style="font-weight: bold;">HAL DCMI </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">Add DCMI_SyncUnmaskTypeDef structure and HAL_DCMI_ConfigSyncUnmask() API to manage embedded synchronization delimiters unmasks</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;"><span style="font-weight: bold;">HAL EXTI</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">General update to enhance HAL EXTI driver robustness </span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">Add additional assert check on EXTI config lines</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">Update to compute EXTI line mask before read/write access to EXTI registers</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">Update EXTI callbacks management to be compliant with reference manual: only one PR register for rising and falling interrupts.</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">Update
+parameters in EXTI_HandleTypeDef structure: merge HAL EXTI
+RisingCallback and FallingCallback in only one PendingCallback.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">Remove HAL_EXTI_RISING_CB_ID and HAL_EXTI_FALLING_CB_ID values from EXTI_CallbackIDTypeDef enumeration.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">Update HAL_EXTI_IRQHandler() API to serve interrupts correctly.</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">Update to compute EXTI line mask before handle EXTI interrupt.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">Update to support GPIO port interrupts:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">Add new "GPIOSel" parameter in EXTI_ConfigTypeDef structure</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;"><span style="font-weight: bold;">HAL HASH </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="MsoNormal" style="font-family: "Verdana","sans-serif"; font-size: 10pt;"><span style="font-weight: bold;"></span></span><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;"><span style="font-weight: bold;"></span>Null pointer on handler "hhash" is now checked before accessing structure member "hhash->Init.DataType" in the following API:</span></li></ul><ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">HAL_HASH_Init()</span></li></ul></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">Following <span style="font-weight: bold;">interrupt-based</span>
+APIs have been added. Interrupt mode could allow the MCU to enter
+"Sleep" mode while a data block is being processed. Please refer to the
+"##### How to use this driver #####" section for details about their
+use.</span></li></ul><ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">HAL_HASH_SHA1_Accmlt_IT()</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">HAL_HASH_MD5_Accmlt_IT()</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">HAL_HASHEx_SHA224_Accmlt_IT()</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">HAL_HASHEx_SHA256_Accmlt_IT()</span></li></ul></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">Following <span style="font-weight: bold;">aliases</span> have been added (just <span style="font-weight: bold;">for clarity sake</span>) as they shall be used at the <span style="font-weight: bold;">end</span> of the computation of a multi-buffers message and not at the start:</span></li></ul><ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">HAL_HASH_SHA1_Accmlt_End() to be used instead of HAL_HASH_SHA1_Start()</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">HAL_HASH_MD5_Accmlt_End() to be used instead of HAL_HASH_MD5_Start()</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">HAL_HASH_SHA1_Accmlt_End_IT() to be used instead of HAL_HASH_SHA1_Start_IT()</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">HAL_HASH_MD5_Accmlt_End_IT() to be used instead of HAL_HASH_MD5_Start_IT()</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">HAL_HASHEx_SHA224_Accmlt_End() to be used instead of HAL_HASHEx_SHA224_Start()</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">HAL_HASHEx_SHA256_Accmlt_End() to be used instead of HAL_HASHEx_SHA256_Start()</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">HAL_HASHEx_SHA224_Accmlt_End_IT() to be used instead of HAL_HASHEx_SHA224_Start_IT()</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">HAL_HASHEx_SHA256_Accmlt_End_IT() to be used instead of HAL_HASHEx_SHA256_Start_IT()</span></li></ul></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">MISRAC-2012
+rule R.5.1 (identifiers shall be distinct in the first 31 characters)
+constrained the naming of the above listed aliases (e.g.
+HAL_HASHEx_SHA256_<span style="font-weight: bold;">Accmlt</span>_End() could not be named HAL_HASHEx_SHA256_<span style="font-weight: bold;">Accumulate</span>_End(). Otherwise the name would have conflicted with HAL_HASHEx_SHA256_<span style="font-weight: bold;">Accumulate</span>_End_IT()). In order to have aligned names following APIs have been renamed:</span></li></ul><ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">HAL_HASH_MD5_Accumulate() renamed HAL_HASH_MD5_Accmlt()</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">HAL_HASH_SHA1_Accumulate() renamed HAL_HASH_SHA1_Accmlt()</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">HAL_HASHEx_SHA224_Accumulate() renamed HAL_HASHEx_SHA224_Accmlt()</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">HAL_HASHEx_SHA256_Accumulate() renamed HAL_HASHEx_SHA256_Accmlt()</span></li></ul></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">HASH <span style="font-weight: bold;">handler</span> state is <span style="font-weight: bold;">no more</span> reset to HAL_HASH_STATE_READY <span style="font-weight: bold;">once DMA has been started</span> in the following APIs:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">HAL_HASH_MD5_Start_DMA()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">HAL_HMAC_MD5_Start_DMA()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">HAL_HASH_SHA1_Start_DMA()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">HAL_HMAC_SHA1_Start_DMA()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">HASH <span style="font-weight: bold;">phase</span> state is now set to HAL_HASH_PHASE_READY<span style="font-weight: bold;"> once the digest has been read</span> in the following APIs:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">HASH_IT()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">HMAC_Processing()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">HASH_Start()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">HASH_Finish()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">Case of a large buffer scattered around in memory each piece of which is <span style="font-weight: bold;">not</span> necessarily a <span style="font-weight: bold;">multiple of 4</span> bytes in length.</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">In
+section "##### How to use this driver #####", sub-section "*** Remarks
+on message length ***" added to provide recommendations to follow in
+such case.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">No modification of the driver as the root-cause is at design-level.<br></span></li></ul></ul></ul><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;"></span><ul style="color: rgb(0, 0, 0); text-transform: none; text-indent: 0px; letter-spacing: normal; margin-top: 0cm; margin-bottom: 0in; word-spacing: 0px; white-space: normal;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-weight: bold;"></span><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;"><span style="font-weight: bold;"><span style="font-weight: bold;">HAL SDMMC </span></span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">Fix typo in "FileFormatGroup" parameter in the HAL_MMC_CardCSDTypeDef and HAL_SD_CardCSDTypeDef structures.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">Fix an improve handle state and error management</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">Rename the defined MMC card capacity type to be more meaningful:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">Update <span style="font-weight: bold;">MMC_HIGH_VOLTAGE_CARD</span> to <span style="font-weight: bold;">MMC LOW_CAPACITY_CARD</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">Update <span style="font-weight: bold;">MMC_DUAL_VOLTAGE_CRAD</span> to <span style="font-weight: bold;">MMC_HIGH_CAPACITY_CARD</span></span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;"><span style="font-weight: bold;">HAL QSPI </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;">Remove Lock mechanism from HAL_QSPI_Init() and HAL_QSPI_DeInit() APIs</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b style="color: rgb(0, 0, 0); font-family: "Times New Roman",serif; font-size: 16px; font-style: normal; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">HAL LPTIM<span> </span></span></b><span style="color: rgb(0, 0, 0); font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: 10pt; font-family: Verdana,sans-serif;">update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add a polling mechanism to check on </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">LPTIM_FLAG_XXOK</span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span> </span>flags in different API </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add LPTIM_WaitForFlag()<span> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;">API<span> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;">to wait for flag set.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Perform new checks on HAL_LPTIM_STATE_TIMEOUT.</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Workaround to fix MCU slack in sleep mode<br></span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Update __HAL_LPTIM_DISABLE () macro used to disable LPTIM HW instance</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Remove the LPTIM_CR_ENABLE bit clear.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add a new API LPTIM_Disable() defined in hal_lptim.c</span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Update __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) macro by adding a specific .... when using callback register</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">__HAL_LPTIM_ENABLE</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Remove usseless check on LPTIM2 in the LL driver since F7 support only one instance of LPTIM.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Update the LL_LPTIM_DISABLE() API used to disable LPTIM HW instance</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Move API definition to ll_lptim.c</span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><b style="color: rgb(0, 0, 0); font-family: "Times New Roman",serif; font-size: 16px; font-style: normal; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">HAL TIM<span> </span></span></b><span style="color: rgb(0, 0, 0); font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: 10pt; font-family: Verdana,sans-serif;">update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add new macros to enable and disable the fast mode when using the one pulse mode to output a waveform with a minimum delay</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">_</span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">_HAL_TIM_ENABLE_OCxFAST() and __HAL_TIM_DISABLE_OCxFAST().</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">U</span><span style="color: rgb(0, 0, 0); font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: 10pt; font-family: Verdana,sans-serif;">pdate Encoder interface mode to keep </span><span style="color: rgb(0, 0, 0); font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: 10pt; font-family: Verdana,sans-serif;">TIM_CCER_CCxNP bits low</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;">TIM_ENCODERINPUTPOLARITY_RISING and TIM_ENCODERINPUTPOLARITY_FALLING</span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span> </span>definitions to determine encoder input polarity.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add<span> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;">IS_TIM_ENCODERINPUT_POLARITY()</span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span> </span>macro to check the encoder input polarity.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Update HAL_TIM_Encoder_Init() API </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Replace IS_TIM_IC_POLARITY() macro by IS_TIM_ENCODERINPUT_POLARITY() macro.</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Correct wrong
+ instance parameter check in encoder mode<o:p></o:p></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Replace
+ IS_TIM_CC2_INSTANCE by IS_TIM_ENCODER_INTERFACE_INSTANCE in encoder
+ interface : <o:p></o:p></span></li></ul><ul style="margin-top: 0cm;" type="disc"><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_TIM_Encoder_Start()<o:p></o:p></span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_TIM_Encoder_Stop()<o:p></o:p></span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_TIM_Encoder_Start_IT()<o:p></o:p></span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_TIM_Encoder_Stop_IT()<o:p></o:p></span></li></ul></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Replace
+ IS_TIM_DMA_CC_INSTANCE by IS_TIM_ENCODER_INTERFACE_INSTANCE in encoder
+ interface in DMA mode : <o:p></o:p></span></li></ul><ul style="margin-top: 0cm;" type="disc"><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_TIM_Encoder_Start_DMA()<o:p></o:p></span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_TIM_Encoder_Stop_DMA()<o:p></o:p></span></li></ul></ul></ul></ul>
+
+<ul><ul><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Update
+ HAL_TIMEx_MasterConfigSynchronization() API to avoid functional errors
+ and assert fails when using some TIM instances as input trigger.<o:p></o:p></span></li></ul></ul><ul style="margin-top: 0cm;" type="disc"><ul style="margin-top: 0cm;" type="disc"><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Replace IS_TIM_SYNCHRO_INSTANCE()
+ macro by IS_TIM_MASTER_INSTANCE() macro. <o:p></o:p></span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add IS_TIM_SLAVE_INSTANCE()
+ macro to check on TIM_SMCR_MSM bit.<o:p></o:p></span></li></ul></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Provide new
+ API to set and clear UIFREMAP<o:p></o:p></span></li></ul><ul style="margin-top: 0cm;" type="disc"><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add new
+ definition for TIM Update Interrupt Flag Remap<o:p></o:p></span></li></ul><ul style="margin-top: 0cm;" type="disc"><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">TIM_UIFREMAP_DISABLE<o:p></o:p></span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">TIM_UIFREMAP_ENABLE<o:p></o:p></span></li></ul></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add new macro
+ in HAL driver to enable and desable the Update Interrupt Flag
+ Remap<o:p></o:p></span></li></ul><ul style="margin-top: 0cm;" type="disc"><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"> __HAL_TIM_UIFREMAP_ENABLE()<o:p></o:p></span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">__HAL_TIM_UIFREMAP_DISABLE()/__HAL_TIM_GET_UIFCPY
+ macro<o:p></o:p></span></li></ul></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add new
+ mecanism to check whether the update interrupt flag (UIF) copy is
+ set or not <o:p></o:p></span></li></ul><ul style="margin-top: 0cm;" type="disc"><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add the
+ __HAL_TIM_GET_UIFCPY() macro in the HAL driver<o:p></o:p></span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add
+ LL_TIM_IsActiveUIFCPY() API in the LL driver<o:p></o:p></span></li></ul></ul></ul><ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add new macro
+ to check on the Update Interrupt Flag Remap mode<o:p></o:p></span></li></ul></ul><ul style="margin-top: 0cm;" type="disc"><ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">IS_TIM_UIFREMAP_MODE()<o:p></o:p></span></li></ul></ul></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Remove usseless
+ define in the LL driver <o:p></o:p></span></li></ul><ul style="margin-top: 0cm;" type="disc"><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">TIMx_AF1_BKINE
+ / TIMx_AF1_BKDFBKE / TIMx_AF2_BK2INE / TIMx_AF2_BK2DFBKE /
+ TIMx_AF2_BK2INP</span></li></ul></ul></ul><span style="font-size: 10pt; font-family: Verdana,sans-serif;"></span><ul style="color: rgb(0, 0, 0); text-transform: none; text-indent: 0px; letter-spacing: normal; margin-top: 0cm; margin-bottom: 0in; word-spacing: 0px; white-space: normal;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><b style="color: rgb(0, 0, 0); font-family: "Times New Roman",serif; font-size: 16px; font-style: normal; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">HAL </span></b><span style="font-size: 10pt; line-height: 106%; font-family: "Verdana",sans-serif;"><span style="font-weight: bold;">SMARTCARD</span> update</span><span style="color: rgb(0, 0, 0); font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: 10pt; font-family: Verdana,sans-serif;"></span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;"></span><span style="font-size: 10pt; line-height: 106%; font-family: "Verdana",sans-serif;">Update SMARTCARD_SetConfig() API.</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; line-height: 106%; font-family: "Verdana",sans-serif;">Split HAL_RCC_GetPCLK1Freq() and
+HAL_RCC_GetPCLK2Freq() macros from the BRR calculation.</span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black; font-weight: bold;"><span style="font-size: 10pt; line-height: 106%; font-family: "Verdana",sans-serif;">HAL </span><b style="color: rgb(0, 0, 0); font-family: "Times New Roman",serif; font-size: 16px; font-style: normal; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;"></span></b><span style="font-size: 10pt; line-height: 106%; font-family: "Verdana",sans-serif;"><span style="font-weight: bold;">IRDA </span><span style="font-weight: normal;">update</span></span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; line-height: 106%; font-family: "Verdana",sans-serif;">Update IRDA_SetConfig() API </span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; line-height: 106%; font-family: "Verdana",sans-serif;">Split HAL_RCC_GetPCLK1Freq() and
+HAL_RCC_GetPCLK2Freq() macros from the IRDA_DIV_SAMPLING16() macro.</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; line-height: 106%; font-family: "Verdana",sans-serif;">Update some API desciption</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; line-height: 106%; font-family: "Verdana",sans-serif;">HAL_IRDA_Transmit() / HAL_IRDA_Transmit_IT()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; line-height: 106%; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_IRDA_Receive() / HAL_IRDA_Receive_IT()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; line-height: 106%; font-family: "Verdana",sans-serif;">HAL_IRDA_Transmit_DMA() / HAL_IRDA_Receive_DMA()</span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><b><span style="font-size: 10pt; line-height: 106%; font-family: "Verdana",sans-serif;">HAL RCC </span></b><span style="font-size: 10pt; line-height: 106%; font-family: "Verdana",sans-serif;">update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; line-height: 106%; font-family: "Verdana",sans-serif;">Update the HAL_RCC_ClockConfig() and HAL_RCC_DeInit() API to don't overwrite the custom tick priority</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; line-height: 106%; font-family: "Verdana",sans-serif;">Update HAL_RCC_OscConfig() API to don't return HAL_ERROR if request repeats the current PLL configuration</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><b><span style="font-size: 10pt; line-height: 106%; font-family: "Verdana",sans-serif;">HAL/LL USART</span></b><span style="font-size: 10pt; line-height: 106%; font-family: "Verdana",sans-serif;"> update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; line-height: 106%; font-family: "Verdana",sans-serif;">Add support to the Receiver Timeout Interrupt in the
+HAL_USART_IRQHandler</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; line-height: 106%; font-family: "Verdana",sans-serif;">Update some API desciption </span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;">
+
+<p class="MsoNormal" style="margin: 2pt 0cm; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_USART_Transmit() / HAL_USART_Transmit_IT() </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></p></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;">
+
+
+
+<p class="MsoNormal" style="margin: 2pt 0cm 2pt 18pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_USART_Receive() / HAL_USART_Receive_IT() </span></p></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;">
+
+<p class="MsoNormal" style="margin: 2pt 0cm 2pt 18pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_USART_TransmitReceive() / HAL_USART_TransmitReceive_IT() </span></p></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><p class="MsoNormal" style="margin: 2pt 0cm 2pt 18pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_USART_Transmit_DMA() / HAL_USART_Receive_DMA() / HAL_USART_TransmitReceive_DMA()</span></p></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; line-height: 106%; font-family: "Verdana",sans-serif;">Update USART_SetConfig() API </span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; line-height: 106%; font-family: "Verdana",sans-serif;">Split HAL_RCC_GetPCLK1Freq() and
+HAL_RCC_GetPCLK2Freq() macros from the USART_DIV_SAMPLING8() macro</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; line-height: 106%; font-family: "Verdana",sans-serif;">Support Stop Mode functionalities in the USART
+driver </span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; line-height: 106%; font-family: "Verdana",sans-serif;">Add definition of USART_ISR_REACK USART,
+receive enable acknowledge flag in the HAL driver</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; line-height: 106%; font-family: "Verdana",sans-serif;">Add new flag definition in the LL driver </span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;">
+
+
+
+<p class="MsoNormal" style="margin: 2pt 0cm 2pt 18pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">LL_USART_ICR_WUCF Wakeup from Stop mode flag </span></p></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;">
+
+<p class="MsoNormal" style="margin: 2pt 0cm 2pt 18pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">LL_USART_ISR_WUF Wakeup from Stop mode flag </span></p></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;">
+
+<p class="MsoNormal" style="margin: 2pt 0cm 2pt 18pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">LL_USART_ISR_REACK Receive enable acknowledge flag </span></p></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><p class="MsoNormal" style="margin: 2pt 0cm 2pt 18pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">LL_USART_CR3_WUFIE Wakeup from Stop mode interrupt enable</span></p></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; line-height: 106%; font-family: "Verdana",sans-serif;">Add new definition of the different event which
+activates the wakeup from Stop mode flag</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; line-height: 106%; font-family: "Verdana",sans-serif;">LL_ </span><span style="font-size: 10pt; line-height: 106%; font-family: "Verdana",sans-serif;" lang="EN-US">USART_WAKEUP_ON_ADDRESS</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;">
+
+<p class="MsoNormal" style="margin: 2pt 0cm 2pt 18pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">LL_USART_WAKEUP_ON_STARTBIT</span></p></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;">
+
+<p class="MsoNormal" style="margin: 2pt 0cm 2pt 18pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">LL_USART_WAKEUP_ON_RXNE</span></p></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;">
+
+<p class="MsoNormal" style="margin: 2pt 0cm 2pt 18pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add new API in LL driver to support stop mode</span></p></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;">
+
+
+
+<p class="MsoNormal" style="margin: 2pt 0cm 2pt 18pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">LL_USART_EnableInStopMode() to enable the USART in stop mode</span></p></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;">
+
+<p class="MsoNormal" style="margin: 2pt 0cm 2pt 18pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">LL_USART_DisableInStopMode() to disable the USART in stop mode</span></p></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;">
+
+<p class="MsoNormal" style="margin: 2pt 0cm 2pt 18pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">LL_USART_IsEnabledInStopMode() to check if the USART is enabled or not
+in the stop mode</span></p></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;">
+
+<p class="MsoNormal" style="margin: 2pt 0cm 2pt 18pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">LL_USART_EnableClockInStopMode() to enable the USART clock in the stop
+mode</span></p></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;">
+
+<p class="MsoNormal" style="margin: 2pt 0cm 2pt 18pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">LL_USART_DisableClockInStopMode() to disable the USART clock in the stop
+mode</span></p></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><p class="MsoNormal" style="margin: 2pt 0cm 2pt 18pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">LL_USART_IsClockEnabledInStopMode() to check whether USART clock are
+enabled or not in the stop mode</span></p></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;">
+
+<p class="MsoNormal" style="margin: 2pt 0cm 2pt 18pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add new API in LL driver to manage event relisted to Wake UP Interrupt
+Flag</span></p></li></ul><ul><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;">
+
+
+
+<p class="MsoNormal" style="margin: 2pt 0cm 2pt 18pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">LL_USART_SetWKUPType() to select the event type for Wake UP Interrupt
+Flag</span></p></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;">
+
+<p class="MsoNormal" style="margin: 2pt 0cm 2pt 18pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">LL_USART_GetWKUPType() to get the event type for Wake UP Interrupt
+Flag</span></p></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;">
+
+<p class="MsoNormal" style="margin: 2pt 0cm 2pt 18pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">LL_USART_IsActiveFlag_WKUP() to Check if the USART Wake Up from stop
+mode Flag is set or not</span></p></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;">
+
+<p class="MsoNormal" style="margin: 2pt 0cm 2pt 18pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">LL_USART_IsActiveFlag_REACK() to Check if the USART Receive Enable
+Acknowledge Flag is set or not</span></p></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><p class="MsoNormal" style="margin: 2pt 0cm 2pt 18pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">LL_USART_ClearFlag_WKUP() Clear Wake Up from stop mode Flag</span></p></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;">
+
+<p class="MsoNormal" style="margin: 2pt 0cm 2pt 18pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add new API in LL driver to manage wake up from stop interruption</span></p></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;">
+
+
+
+<p class="MsoNormal" style="margin: 2pt 0cm 2pt 18pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">LL_USART_EnableIT_WKUP() to Enable Wake Up from Stop Mode Interrupt</span></p></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;">
+
+<p class="MsoNormal" style="margin: 2pt 0cm 2pt 18pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">LL_USART_DisableIT_WKUP() to Disable Wake Up from Stop Mode Interrupt</span></p></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><p class="MsoNormal" style="margin: 2pt 0cm 2pt 18pt; text-indent: -18pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">LL_USART_IsEnabledIT_WKUP() to Check if the USART Wake Up from Stop Mode
+Interrupt is enabled or not</span></p></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL/LL USB </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"> Add handling USB host babble error interrupt</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"> Fix Enabling ULPI interface for platforms that integrates USB HS PHY</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"> Fix Host data toggling for IN Iso transfers</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"> Ensure to disable USB EP during endpoint deactivation</span></li></ul></ul>
+<b style="color: rgb(0, 0, 0); font-family: "Times New Roman",serif; font-size: 16px; font-style: normal; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;"></span></b><span style="font-family: "Verdana","sans-serif"; font-size: 10pt;"></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 241px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.7/ 08-February-2019</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b><u><span style="color: black; font-family: Verdana; font-size: 10pt;">Main Changes</span></u></b></p>
<ul style="color: rgb(0, 0, 0); text-transform: none; text-indent: 0px; letter-spacing: normal; margin-top: 0cm; margin-bottom: 0in; word-spacing: 0px; white-space: normal;" type="square">
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">General updates to fix known defects and enhancements implementation</span></li>
@@ -875,11 +1006,11 @@
</ul>
<span style="font-family: "Verdana","sans-serif"; font-size: 10pt;"></span>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 241px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.6 / 29-June-2018</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; font-size: medium; font-family: "Times New Roman",serif; color: rgb(0, 0, 0); font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;"><b><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main Changes</span></u></b></p><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: "Times New Roman"; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; line-height: normal; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update to support STM32F730xx and STM32F750xx value lines</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL DMA<span> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">DMA_CHANNEL_8 to DMA_CHANNEL_15 are also defined in case of </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">STM32F730xx (</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">same features as STM32F733xx line</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">)</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL FLASH<span> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add support of<span> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">STM32F730xx with 4 FLash sectors of 16KB each</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add support of<span> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">STM32F750xx with 2 FLash sectors of 32KB each</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">.</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL GPIO<span> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add support of </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">STM32F730xx value line : same features as STM32F733xx line</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add support of </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">STM32F750xx value line : same features as STM32F756xx </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">line</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL RCC<span> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add support of </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">STM32F730xx value line : same features as STM32F733xx </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">line</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add support of </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">STM32F750xx value line : same features as STM32F756xx </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">line</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 241px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.5 / 02-February-2018</span></h3>
+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 241px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.6 / 29-June-2018</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; font-size: medium; font-family: "Times New Roman",serif; color: rgb(0, 0, 0); font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;"><b><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main Changes</span></u></b></p><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: "Times New Roman"; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; line-height: normal; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update to support STM32F730xx and STM32F750xx value lines</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL DMA<span> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">DMA_CHANNEL_8 to DMA_CHANNEL_15 are also defined in case of </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">STM32F730xx (</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">same features as STM32F733xx line</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">)</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL FLASH<span> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add support of<span> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">STM32F730xx with 4 FLash sectors of 16KB each</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add support of<span> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">STM32F750xx with 2 FLash sectors of 32KB each</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">.</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL GPIO<span> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add support of </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">STM32F730xx value line : same features as STM32F733xx line</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add support of </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">STM32F750xx value line : same features as STM32F756xx </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">line</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL RCC<span> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add support of </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">STM32F730xx value line : same features as STM32F733xx </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">line</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add support of </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">STM32F750xx value line : same features as STM32F756xx </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">line</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 241px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.5 / 02-February-2018</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">General updates to fix known defects and enhancements implementation</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new macro to get variable aligned on 32-bytes, required for cache maintenance purpose</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update UNUSED() macro implementation to avoid GCC warning</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">The warning is detected when the UNUSED() macro is called from C++ file</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SAI </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_SAI_DMAStop() and HAL_SAI_Abort() process to fix the lock/unlock audio issue </span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL PWR </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update
HAL_PWR_EnterSLEEPMode() and HAL_PWR_EnterSTOPMode() APIs to ensure
-that all instructions finished before entering STOP mode. </span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL HCD </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new callback to be used to handle usb device connection/disconnection</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_HCD_PortEnabled_Callback()</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_HCD_PortDisabled_Callback()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to prevent reactivate host interrrupt channel<br></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 241px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.4 / 22-December-2017</span></h3>
+that all instructions finished before entering STOP mode. </span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL HCD </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new callback to be used to handle usb device connection/disconnection</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_HCD_PortEnabled_Callback()</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_HCD_PortDisabled_Callback()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to prevent reactivate host interrrupt channel<br></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 241px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.4 / 22-December-2017</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">General updates to fix known defects and enhancements implementation</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">The following changes done on the HAL drivers require an update on the application code based on older HAL versions</span></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black; font-weight: bold;"><span style="font-size: 10pt; font-family: Verdana;">Rework of HAL CAN driver (compatibility break) </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">A
new HAL CAN driver has been redesigned with new APIs, to bypass
@@ -917,14 +1048,14 @@
status</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add checks for HSI, PLL and
PLLI2S ready before modifying RCC CFGR registers</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Clear all interrupt flags</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Initialize systick interrupt
period</span></li></ul></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL DMA </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span lang="fr"><font face="Courier New" size="2"></font></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add clean of callbacks in HAL_DMA_DeInit() API</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Fix wrong DMA_FLAG_FEIFO_4 and DMA_FLAGDMAEIFO_4 defines values </span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL I2C </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Update Interface APIs headers to remove confusing message about device address</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Update </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">I2C_WaitOnRXNEFlagUntilTimeout() to resolve a race condition between STOPF and RXNE Flags</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Update I2C_TransferConfig() to fix wrong bit management</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">LL USART<span> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add assert macros to check USART BaudRate register</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL ETH </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Do{..} While(0) </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">insured </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">in </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">multi statement macros</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> :</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">__HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">__HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER()</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> <br></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL FLASH<span> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_FLASH_Unlock() update to return state error when the FLASH is already unlocked</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL GPIO<span> </span></span>update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add missing define of GPIO_PIN_2 in GPIOK_PIN_AVAILABLE list</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL PCD<span> </span></span>update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Do{..} While(0) insured in multi statement macros</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">LL UTILS<span> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">stm32f7xx_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">ll_utils.h : Update LL_GetPackageType command to return uint32_t instead of uint16_t</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL TIM<span> </span></span>update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">stm32f7xx_hal_tim_ex.c : Update HAL_TIMEx_ConfigBreakDeadTime API to avoid to block timer behavior when <br>remains in the state HAL_TIM_STATE_BUSY.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"> </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">stm32f7xx_hal_tim.h : </span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Fix __HAL_TIM_SET_PRESCALER() macro</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Fix typos in some exported macros description </span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">LL FMC<span> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_SDRAM_SendCommand() API: </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Remove the timeout</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"> check</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL NAND<span> </span></span>update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Fix wrong check for NAND status</span></li></ul></ul>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.3 / 25-August-2017</span></h3>
+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.3 / 25-August-2017</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">General updates
to fix known defects and enhancements implementation</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Remove Date and Version from header files</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update HAL drivers to refer to the new CMSIS bit position defines instead of usage the </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">POSITION_VAL() macro</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CAN </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add missing unlock in HAL_CAN_Receive_IT() process</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL DCMI </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL DCMI driver clean-up: remove non referenced callback APIs: HAL_DCMI_VsyncCallback() and HAL_DCMI_HsyncCallback()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL DFSDM </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Fix cast issue on APIs that return signed integer value (uint32_t) </span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL DMA </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL DMA driver clean-up: remove non referenced callback APIs: HAL_DMA_CleanCallbacks()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL FLASH </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">FLASH_Program_DoubleWord() API: Replace 64-bit accesses with 2 double words operations</span></li></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL Generic </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update assert_param() macro definition to be in line with stm32_ll_utils.c driver</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL GPIO </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">GPIOK_PIN_AVAILABLE() assert macro update to allow possibility to configure GPIO_PIN_2</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL LTDC </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Rename HAL_LTDC_LineEvenCallback() API to </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_LTDC_LineEven<span style="font-weight: bold;">t</span>Callback()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL PCD </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL_PCD_IRQHandler() API to fix transfer issues when </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">USB HS is used with DMA enabled</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RCC </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL_RCC_GetOscConfig() API to:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">set PLLR in the RCC_OscInitStruct</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">check on null pointer<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL_RCC_ClockConfig() API to:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">check on null pointer</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">optimize code size by updating the handling method of the SWS bits</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update
to use __HAL_FLASH_GET_LATENCY() flash macro instead of using
direct register access to LATENCY bits in FLASH ACR register</span><span lang="fr">. </span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SAI </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL_SAI_DMAStop() API to flush fifo after disabling SAI</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL TIM </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_TIMEx_ConfigBreakInput() API to support BKINP/BKIN2P polarity bits.<br></span></li></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL DMA </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update
SET_BIT() access to LIFCR and HIFCR registers by WRITE_REG() to avoid
-read access that is not allowed when clearing DMA flags</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL I2C </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update LL_I2C_Init() API to avoid enabling own address1 when OwnAddress1 parameter value in the I2C_InitStruct is equal to 0.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL TIM </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update LL_TIM_EnableUpdateEvent() API to clear UDIS bit in CR1 register instead of setting it.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update LL_TIM_DisableUpdateEvent() API </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">to set UDIS bit in CR1 register instead of clearing it.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL USB </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update USB_EP0StartXfer() API to fix transfer issues when </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">USB HS is used with DMA enabled</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.2 / 14-April-2017</span></h3>
+read access that is not allowed when clearing DMA flags</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL I2C </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update LL_I2C_Init() API to avoid enabling own address1 when OwnAddress1 parameter value in the I2C_InitStruct is equal to 0.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL TIM </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update LL_TIM_EnableUpdateEvent() API to clear UDIS bit in CR1 register instead of setting it.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update LL_TIM_DisableUpdateEvent() API </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">to set UDIS bit in CR1 register instead of clearing it.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL USB </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update USB_EP0StartXfer() API to fix transfer issues when </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">USB HS is used with DMA enabled</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.2 / 14-April-2017</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">General updates
to fix known defects and enhancements implementation</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CAN </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add
@@ -933,12 +1064,12 @@
interrupt.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Fix message
lost issue with specific sequence of transmit requests.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Handle
transmission failure with error callback, when NART is enabled.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">Add __HAL_CAN_CANCEL_TRANSMIT() call to abort transmission when
- timeout is reached</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.1 / 24-March-2017</span></h3>
+ timeout is reached</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.1 / 24-March-2017</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana; font-size: 13.3333px; font-style: normal; font-variant: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Update CHM UserManuals to support LL drivers</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">General updates
to fix known defects and enhancements implementation</span></li></ul><ul style="margin-top: 0cm;" type="square"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL DMA </span>update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_DMA_Init() function to adjust the compatibility check between FIFO threshold and burst configuration</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL MMC </span>update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_MMC_InitCard() function with proper initialization sequence adding a delay after MMC clock enable</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update MMC_DMAError() function ignore DMA FIFO error as not impacting the data transfer</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SD </span>update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_SD_InitCard() function with proper initialization sequence adding a delay after SD clock enable</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update SD_DMAError() function ignore DMA FIFO error as not impacting the data transfer<br></span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL NAND </span>update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_NAND_Address_Inc() function implementation for proper plane number check</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;"></span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL SDMMC </span>update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update SDMMC_DATATIMEOUT value with appropriate value needed by reading and writing operations of SD and MMC cards</span><span style="font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;" dir="ltr"></span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL RTC </span>update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">LL_RTC_TIME_Get() and LL_RTC_DATE_Get() inline macros optimization</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL ADC </span>update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Fix wrong ADC group injected sequence configuration</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">LL_ADC_INJ_SetSequencerRanks()
and LL_ADC_INJ_GetSequencerRanks() API's update to take in
-consideration the ADC number of conversions</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update the </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">defined values for</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> ADC group injected seqencer ranks <br></span></li></ul></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.0 / 30-December-2016</span></h3>
+consideration the ADC number of conversions</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update the </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">defined values for</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> ADC group injected seqencer ranks <br></span></li></ul></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.0 / 30-December-2016</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Official release to add the support of <span style="font-weight: bold;">STM32F722xx, STM32F723xx, STM32F732xx</span> <span style="font-weight: bold;">and STM32F733xx</span> devices</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: bold; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Add Low Layer drivers allowing performance and footprint optimization</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Low
Layer drivers APIs provide register level programming: require deep
@@ -948,9 +1079,9 @@
USART, WWDG peripherals and additionnal Low Level Bus, System and
Utilities APIs.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Low Layer drivers APIs are implemented as static inline function in new<span class="Apple-converted-space"> </span><span style="font-style: italic;">Inc/stm32f7xx_ll_ppp.h</span><span class="Apple-converted-space"> </span>files for PPP peripherals, there is no configuration file and each<span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">stm32f7xx_ll_ppp.h</span><span class="Apple-converted-space"> </span>file must be included in user code.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">General updates
to fix known defects and enhancements implementation</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new HAL <span style="font-weight: bold;">MMC</span> and <span style="font-weight: bold;">SMBUS</span> drivers</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL Cortex</span> update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Move HAL_MPU_Disable() and HAL_MPU_Enable() from stm32f7xx_hal_cortex.h to stm32f7xx_hal_cortex.c</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Clear the whole MPU control register in </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_MPU_Disable() API</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CRYP</span> update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add support of AES</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL DMA</span> update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add a check on DMA stream instance in HAL_DMA_DeInit() API</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL ETH</span> update </span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Fix wrong definitions in driver header file stm32f7_hal_eth.h</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL FLASH</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Support OTP program operation</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add the support of PCROP feature</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update the clearing of error flags</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL I2C</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Align driver source code with other STM32 families<br></span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL JPEG</span> update </span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update the output data management when HAL_JPEG_Pause() is performed during the last data sending</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RCC </span>update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Enable PWR only if necessary for LSE configuration in HAL_RCC_OscConfig() API</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename RCC_LPTIM1CLKSOURCE_PCLK define to RCC_LPTIM1CLKSOURCE_PCLK1</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename RCC_DFSDM1CLKSOURCE_PCLK define to RCC_DFSDM1CLKSOURCE_PCLK2<br></span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SPI</span> update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Clear RX FIFO at the end of each transaction</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL UART</span> update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Remove </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">USART_CR2_LINEN bit </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">clearing when initializing in synchronous mode</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL USB</span> update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add support of embedded USB PHY Controller</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add support of Battery Charging Detector (BCD) feature</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL SDMMC</span> update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new SDMMC_CmdSDEraseStartAdd, SDMMC_CmdSDEraseEndAdd, SDMMC_CmdOpCondition and SDMMC_CmdSwitch functions</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL USB</span> update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update PENA bit clearing in OTG_HPRT0 register</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">The following changes done on the HAL drivers require an update on the
-application code based on older HAL versions</span></span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SD</span> update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana',sans-serif; font-size: 10pt;" lang="EN-US">Overall rework of the driver for a more efficient implementation</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana',sans-serif; font-size: 10pt;" lang="EN-US">Modify initialization API and structures</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana',sans-serif; font-size: 10pt;" lang="EN-US">Modify Read / Write sequences: separate transfer process and SD Cards state management </span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana',sans-serif; font-size: 10pt;" lang="EN-US">Adding interrupt mode for Read / Write operations</span></li></ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana',sans-serif; font-size: 10pt;" lang="EN-US">Update the HAL_SD_IRQHandler function by optimizing the management of interrupt errors<br></span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana',sans-serif; font-size: 10pt;" lang="EN-US">Refer to the following example to identify the changes: BSP example and USB_Device/MSC_Standalone application</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL TIM</span> update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new AutoReloadPreload field in TIM_Base_InitTypeDef structure</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana',sans-serif; font-size: 10pt;" lang="EN-US">Refer to the TIM examples to identify the changes</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;"> </span></span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL NAND</span> update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Modify NAND_AddressTypeDef, NAND_DeviceConfigTypeDef and NAND_HandleTypeDef structures fields</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new HAL_NAND_ConfigDevice API<br></span></li></ul></ul></ul><b style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: 16px; font-style: normal; font-variant: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px;"><span style="font-family: Verdana; color: black; font-size: 10pt;"></span></b><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.1 / 01-July-2016</span></h3>
+application code based on older HAL versions</span></span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SD</span> update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana',sans-serif; font-size: 10pt;" lang="EN-US">Overall rework of the driver for a more efficient implementation</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana',sans-serif; font-size: 10pt;" lang="EN-US">Modify initialization API and structures</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana',sans-serif; font-size: 10pt;" lang="EN-US">Modify Read / Write sequences: separate transfer process and SD Cards state management </span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana',sans-serif; font-size: 10pt;" lang="EN-US">Adding interrupt mode for Read / Write operations</span></li></ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana',sans-serif; font-size: 10pt;" lang="EN-US">Update the HAL_SD_IRQHandler function by optimizing the management of interrupt errors<br></span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana',sans-serif; font-size: 10pt;" lang="EN-US">Refer to the following example to identify the changes: BSP example and USB_Device/MSC_Standalone application</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL TIM</span> update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new AutoReloadPreload field in TIM_Base_InitTypeDef structure</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana',sans-serif; font-size: 10pt;" lang="EN-US">Refer to the TIM examples to identify the changes</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;"> </span></span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL NAND</span> update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Modify NAND_AddressTypeDef, NAND_DeviceConfigTypeDef and NAND_HandleTypeDef structures fields</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new HAL_NAND_ConfigDevice API<br></span></li></ul></ul></ul><b style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: 16px; font-style: normal; font-variant: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px;"><span style="font-family: Verdana; color: black; font-size: 10pt;"></span></b><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.1 / 01-July-2016</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL DMA</span> update </span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update HAL_DMA_PollForTransfer() function implementation to avoid early TIMEOUT error.</span> </li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL JPEG</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_JPEG_ConfigEncoding() function to properly set the ImageHeight and ImageWidth</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SPI</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update SPI_DMATransmitReceiveCplt() function to properly handle the CRC and avoid conditional statement duplication<br></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0 / 22-April-2016</span></h3>
+Changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL DMA</span> update </span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update HAL_DMA_PollForTransfer() function implementation to avoid early TIMEOUT error.</span> </li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL JPEG</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_JPEG_ConfigEncoding() function to properly set the ImageHeight and ImageWidth</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SPI</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update SPI_DMATransmitReceiveCplt() function to properly handle the CRC and avoid conditional statement duplication<br></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0 / 22-April-2016</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Official release to add the support of <span style="font-weight: bold;">STM32F765xx, STM32F767xx, STM32F768xx, STM32F769xx, STM32F777xx, STM32F778xx</span> <span style="font-weight: bold;">and STM32F779xx</span> devices<br></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">General updates
to fix known defects and enhancements implementation</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add new HAL drivers for<span class="Apple-converted-space"> </span><span style="font-weight: bold;">DFSDM, DSI<span class="Apple-converted-space">, JPEG </span></span>and<span class="Apple-converted-space"> </span><span style="font-weight: bold;">MDIOS<span class="Apple-converted-space"> </span></span>peripherals</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Enhance HAL delay and timebase implementation</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new
@@ -1150,12 +1281,12 @@
<ul style="margin-bottom: 0in;"><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add the management of SPI peripheral errors during DMA process. This requires the following updates in
the user application:</span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Configure and enable the SPI IRQ in HAL_SPI_MspInit() function</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">In stm32f7xx_it.c file, SPI_IRQHandler() function: add a call to HAL_SPI_IRQHandler() function</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add and customize the Error Callback API: HAL_SPI_ErrorCallback()</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Refer to the following example which describe the changes: SPI_FullDuplex_ComDMA<br></span></li></ul></ul>
</li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL TIM </span>update </span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_TIM_ConfigOCrefClear() function for proper configuration of the SMCR register</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new function HAL_TIMEx_ConfigBreakInput() to configure the break input source</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><b><span style="font-family: 'Verdana',sans-serif; font-size: 10pt;" lang="EN-US">HAL UART, USART, SMARTCARD and IRDA </span></b><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;"></span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;"></span>(referenced as <span style="font-style: italic;">PPP</span> here below)<span style="font-style: italic;"></span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;"> </span></span><span style="font-family: 'Verdana',sans-serif; font-size: 10pt;" lang="EN-US">update<b><o:p></o:p></b></span>
-</li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana',sans-serif; font-size: 10pt;" lang="EN-US">Update Polling management:</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana',sans-serif; font-size: 10pt;" lang="EN-US">The user Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update DMA process:</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update the m</span><span style="font-family: 'Verdana',sans-serif; font-size: 10pt;" lang="EN-US">anagement of PPP peripheral errors during DMA process. This requires the following updates in user application:</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana',sans-serif; font-size: 10pt;" lang="EN-US">Configure and enable the PPP IRQ in HAL_PPP_MspInit() function</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana',sans-serif; font-size: 10pt;" lang="EN-US">In stm32f7xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana',sans-serif; font-size: 10pt;" lang="EN-US">Add and customize the Error Callback API: HAL_PPP_ErrorCallback()<br></span></li></ul></ul></ul></ul><ul style="margin-top: 0cm;" type="square"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL WWDG </span>update </span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Overall rework of the driver for more efficient implementation</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Remove the following APIs:</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_WWDG_Start()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_WWDG_Start_IT()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_WWDG_MspDeInit()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_WWDG_GetState()</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update implementation:</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_WWDG_Init()</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">A new parameter in the Init Structure: EWIMode</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_WWDG_MspInit()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_WWDG_Refresh() </span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">This function insures the reload of the counter</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">The "counter" parameter has been removed</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_WWDG_IRQHandler()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_WWDG_EarlyWakeupCallback() is the new prototype of HAL_WWDG_WakeupCallback()<br></span></li></ul></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Refer to the following example to identify the changes: WWDG_Example</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.4 / 09-December-2015</span></h3>
+</li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana',sans-serif; font-size: 10pt;" lang="EN-US">Update Polling management:</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana',sans-serif; font-size: 10pt;" lang="EN-US">The user Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update DMA process:</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update the m</span><span style="font-family: 'Verdana',sans-serif; font-size: 10pt;" lang="EN-US">anagement of PPP peripheral errors during DMA process. This requires the following updates in user application:</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana',sans-serif; font-size: 10pt;" lang="EN-US">Configure and enable the PPP IRQ in HAL_PPP_MspInit() function</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana',sans-serif; font-size: 10pt;" lang="EN-US">In stm32f7xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana',sans-serif; font-size: 10pt;" lang="EN-US">Add and customize the Error Callback API: HAL_PPP_ErrorCallback()<br></span></li></ul></ul></ul></ul><ul style="margin-top: 0cm;" type="square"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL WWDG </span>update </span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Overall rework of the driver for more efficient implementation</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Remove the following APIs:</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_WWDG_Start()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_WWDG_Start_IT()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_WWDG_MspDeInit()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_WWDG_GetState()</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update implementation:</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_WWDG_Init()</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">A new parameter in the Init Structure: EWIMode</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_WWDG_MspInit()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_WWDG_Refresh() </span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">This function insures the reload of the counter</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">The "counter" parameter has been removed</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_WWDG_IRQHandler()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_WWDG_EarlyWakeupCallback() is the new prototype of HAL_WWDG_WakeupCallback()<br></span></li></ul></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Refer to the following example to identify the changes: WWDG_Example</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.4 / 09-December-2015</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL Generic </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL
weak empty callbacks to prevent unused argument compilation warnings with some
compilers by calling the following line:</span>
-</li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">UNUSED(hppp);</span></li></ul></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL ETH</span> update </span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_ETH_Init() function to add timeout on the Software reset management<br></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.3 / 13-November-2015</span></h3>
+</li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">UNUSED(hppp);</span></li></ul></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL ETH</span> update </span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_ETH_Init() function to add timeout on the Software reset management<br></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.3 / 13-November-2015</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">General updates
to fix known defects and enhancements implementation</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;"></span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">One change done on the HAL CRYP requires an update on
@@ -1169,7 +1300,7 @@
value for the ExternalTrigInjecConvEdge parameter in the ADC_InitTypeDef
structure to select the ADC software trigger mode.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CORTEX </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span>
</li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Remove duplication
-for __HAL_CORTEX_SYSTICKCLK_CONFIG() macro</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CRYP </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_CRYP_DESECB_Decrypt() API to fix the inverted pPlainData and pCypherData parameters issue </span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL FLASH </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update OB_IWDG_STOP_ACTIVE definition</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update OB_RDP_LEVEL_x definition by proper values</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update FLASH_MassErase() function to consider the voltage range parameter in the mass erase configuration <br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RCC</span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;"> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update values for LSE Drive capability defines</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update PLLN min value 50 instead of 100</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">add RCC_PLLI2SP_DIVx defines for PLLI2SP clock divider</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Update __HAL_RCC_USB_OTG_FS_CLK_DISABLE() macro to remove the disable of the SYSCFG</span><span style="font-family: Verdana; font-size: 10pt;"> </span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">Update HAL_RCCEx_GetPeriphCLKFreq() function for proper SAI clock configuration<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SAI </span></span><span style="font-weight: bold;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update for proper management of the external synchronization input selection</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update of HAL_SAI_Init () funciton</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update definition of SAI_Block_SyncExt and SAI_Block_Synchronization groups</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update SAI_SLOTACTIVE_X defines values</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_SAI_Init() function for proper companding mode management</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update SAI_Transmit_ITxxBit() functions to add the check on transfer counter before writing new data to SAIx_DR registers</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update SAI_FillFifo() function to avoid issue when the number of data to transmit is smaller than the FIFO size</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update HAL_SAI_EnableRxMuteMode() function for proper mute management</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update SAI_InitPCM() function to support 24bits configuration</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SD </span></span><span style="font-weight: bold;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">update HAL_SD_Get_CardInfo() to properly support high capacity cards</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;"><br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SPDIFRX </span></span><span style="font-weight: bold;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update SPDIFRX_DMARxCplt() function implementation to check on circular mode before disabling the DMA</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL TIM </span></span><span style="font-weight: bold;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_TIM_ConfigClockSource() function implementation for proper parameters check</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL UART</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">Update __HAL_UART_CLEAR_IT macro for proper functionning </span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">ll FMC</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">add FMC_PAGE_SIZE_512 define</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">ll SDMMC</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">update SDMMC_SetSDMMCReadWaitMode() function for proper functionning</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.2 / 21-September-2015</span></h3>
+for __HAL_CORTEX_SYSTICKCLK_CONFIG() macro</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CRYP </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_CRYP_DESECB_Decrypt() API to fix the inverted pPlainData and pCypherData parameters issue </span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL FLASH </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update OB_IWDG_STOP_ACTIVE definition</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update OB_RDP_LEVEL_x definition by proper values</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update FLASH_MassErase() function to consider the voltage range parameter in the mass erase configuration <br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RCC</span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;"> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update values for LSE Drive capability defines</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update PLLN min value 50 instead of 100</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">add RCC_PLLI2SP_DIVx defines for PLLI2SP clock divider</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Update __HAL_RCC_USB_OTG_FS_CLK_DISABLE() macro to remove the disable of the SYSCFG</span><span style="font-family: Verdana; font-size: 10pt;"> </span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">Update HAL_RCCEx_GetPeriphCLKFreq() function for proper SAI clock configuration<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SAI </span></span><span style="font-weight: bold;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update for proper management of the external synchronization input selection</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update of HAL_SAI_Init () funciton</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update definition of SAI_Block_SyncExt and SAI_Block_Synchronization groups</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update SAI_SLOTACTIVE_X defines values</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_SAI_Init() function for proper companding mode management</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update SAI_Transmit_ITxxBit() functions to add the check on transfer counter before writing new data to SAIx_DR registers</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update SAI_FillFifo() function to avoid issue when the number of data to transmit is smaller than the FIFO size</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update HAL_SAI_EnableRxMuteMode() function for proper mute management</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update SAI_InitPCM() function to support 24bits configuration</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SD </span></span><span style="font-weight: bold;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">update HAL_SD_Get_CardInfo() to properly support high capacity cards</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;"><br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SPDIFRX </span></span><span style="font-weight: bold;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update SPDIFRX_DMARxCplt() function implementation to check on circular mode before disabling the DMA</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL TIM </span></span><span style="font-weight: bold;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_TIM_ConfigClockSource() function implementation for proper parameters check</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL UART</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">Update __HAL_UART_CLEAR_IT macro for proper functionning </span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">ll FMC</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">add FMC_PAGE_SIZE_512 define</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">ll SDMMC</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">update SDMMC_SetSDMMCReadWaitMode() function for proper functionning</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.2 / 21-September-2015</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL Generic </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">stm32f7xx_hal.conf_template.h: update </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HSE_STARTUP_TIMEOUT</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">stm32f7xx_hal_def.h: update the</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> quotation marks used in #error"USE_RTOS should be 0 in the current HAL release"</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL DMA</span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;"> update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Overall
driver update for code optimization</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">add
@@ -1201,7 +1332,7 @@
HAL_HASH_PhaseTypeDef to HAL_HASHPhaseTypeDef</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RCC </span></span><span style="font-weight: bold;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">update</span><span style="font-weight: bold;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update values for LSE Drive capability defines</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update PLLN/PLLI2SN/PLLSAI VCO min value 100MHz instead of 192MHz</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">add __HAL_RCC_MCO1_CONFIG() and </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_RCC_MCO2_CONFIG() macros</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">update HAL_RCCEx_PeriphCLKConfig() function to reset the Backup domain only if the RTC Clock source selection is modified </span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL TIM</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">update the implementation of __HAL_TIM_SET_COMPARE() macro</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">remove useless assert() in HAL_TIM_PWM_ConfigChannel(), TIM_OC2_SetConfig() and HAL_TIM_PWM_ConfigChannel() </span><span style="font-family: Verdana; font-size: 10pt;">functions</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL CAN</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">add the clear flag ERRI bit in HAL_CAN_IRQHandler()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL I2S</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">update I2S HAL_I2S_Transmit() API to keep the check on busy flag only for the slave</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL QSPI</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">Add __HAL_QSPI_CLEAR_FLAG() before QSPI_Config()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL UART</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">Remove
enabling of ERR IT source and PE source from HAL_UART_Transmit_IT() and
remove the corresponding disabling ERR/PE IT from UART_EndTransmit_IT()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL PCD</span></span><span style="font-family: Verdana; font-size: 10pt;"> update</span><span style="font-weight: bold;"> </span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">Clean status phase received interrupt when DMA mode enabled </span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL HCD </span></span><span style="font-family: Verdana; font-size: 10pt;">update</span><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;"></span></span><span style="font-weight: bold;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to use local
-variable in USB Host channel re-activation</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">ll FMC</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">update the define FMC Write FIFO Disable/Enable: FMC_WRITE_FIFO_DISABLE and FMC_WRITE_FIFO_ENABLE</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">remove return HAL_ERROR from FMC_SDRAM_SendCommand() function</span></li></ul></ul><span style="font-family: Verdana; font-size: 10pt;"></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.1 / 25-June-2015</span></h3>
+variable in USB Host channel re-activation</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">ll FMC</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">update the define FMC Write FIFO Disable/Enable: FMC_WRITE_FIFO_DISABLE and FMC_WRITE_FIFO_ENABLE</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">remove return HAL_ERROR from FMC_SDRAM_SendCommand() function</span></li></ul></ul><span style="font-family: Verdana; font-size: 10pt;"></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.1 / 25-June-2015</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">General updates
to fix known defects and enhancements implementation</span><span style="font-family: Verdana; font-size: 10pt;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CRC </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">update __HAL_CRC_SET_IDR() macro implementation to use WRITE_REG() instead of MODIFY_REG()<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CEC </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">update timeout management in HAL_CEC_Transmit() and HAL_CEC_Receive() functions</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL Cortex </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">update HAL_MPU_ConfigRegion() function to be misra compliant</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL ETH </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Remove
@@ -1227,12 +1358,12 @@
</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to use local
variable in USB Host channel re-activation</span></li></ul></ul>
<b><u><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"></span></u></b>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 12-May-2015</span></h3>
+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 12-May-2015</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p><span style="font-family: Verdana; font-size: 10pt;"></span><span style="font-family: Verdana; font-size: 10pt;"></span><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-family: Verdana; font-size: 10pt;">First official release for</span><span style="font-family: Verdana; font-size: 10pt;"><span style="font-style: italic; font-weight: bold;"> STM32F756xx/746xx/745xx</span>
devices</span></li></ul>
<b><u><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"></span></u></b>
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
<div style="text-align: justify;">
<div style="text-align: justify;"><font size="-1"><span style="font-family: "Verdana","sans-serif";">Redistribution
and use in source and binary forms, with or without
diff --git a/Src/Legacy/stm32f7xx_hal_can.c b/Src/Legacy/stm32f7xx_hal_can.c
index 1262e4d..33c70e9 100644
--- a/Src/Legacy/stm32f7xx_hal_can.c
+++ b/Src/Legacy/stm32f7xx_hal_can.c
@@ -83,13 +83,29 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
diff --git a/Src/stm32f7xx_hal.c b/Src/stm32f7xx_hal.c
index 53f64b3..ce308e4 100644
--- a/Src/stm32f7xx_hal.c
+++ b/Src/stm32f7xx_hal.c
@@ -50,11 +50,11 @@
* @{
*/
/**
- * @brief STM32F7xx HAL Driver version number V1.2.7
+ * @brief STM32F7xx HAL Driver version number V1.2.8
*/
#define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
-#define __STM32F7xx_HAL_VERSION_SUB2 (0x07) /*!< [15:8] sub2 version */
+#define __STM32F7xx_HAL_VERSION_SUB2 (0x08) /*!< [15:8] sub2 version */
#define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\
|(__STM32F7xx_HAL_VERSION_SUB1 << 16)\
@@ -319,14 +319,26 @@
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
{
HAL_StatusTypeDef status = HAL_OK;
+ HAL_TickFreqTypeDef prevTickFreq;
+
assert_param(IS_TICKFREQ(Freq));
if (uwTickFreq != Freq)
{
+ /* Back up uwTickFreq frequency */
+ prevTickFreq = uwTickFreq;
+
+ /* Update uwTickFreq global variable used by HAL_InitTick() */
uwTickFreq = Freq;
/* Apply the new tick Freq */
status = HAL_InitTick(uwTickPrio);
+
+ if (status != HAL_OK)
+ {
+ /* Restore previous tick frequency */
+ uwTickFreq = prevTickFreq;
+ }
}
return status;
diff --git a/Src/stm32f7xx_hal_adc.c b/Src/stm32f7xx_hal_adc.c
index a0fde31..f6b64e7 100644
--- a/Src/stm32f7xx_hal_adc.c
+++ b/Src/stm32f7xx_hal_adc.c
@@ -131,6 +131,7 @@
*** Callback functions ***
==============================
+ [..]
(@) Callback functions must be implemented in user program:
(+@) HAL_ADC_ErrorCallback()
(+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
@@ -1631,23 +1632,23 @@
/* Process locked */
__HAL_LOCK(hadc);
-
- /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
- if (sConfig->Channel > ADC_CHANNEL_9)
- {
- /* Clear the old sample time */
- hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
+
+ /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
+ if ((sConfig->Channel > ADC_CHANNEL_9) && (sConfig->Channel != ADC_INTERNAL_NONE))
+ {
+ /* Clear the old sample time */
+ hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
- if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
- {
- /* Set the new sample time */
- hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18);
- }
- else
- {
- /* Set the new sample time */
- hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
- }
+ if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
+ {
+ /* Set the new sample time */
+ hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18);
+ }
+ else
+ {
+ /* Set the new sample time */
+ hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
+ }
}
else /* ADC_Channel include in ADC_Channel_[0..9] */
{
@@ -1686,6 +1687,13 @@
hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
}
+ /* if no internal channel selected */
+ if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_INTERNAL_NONE))
+ {
+ /* Disable the VBAT & TSVREFE channel*/
+ ADC->CCR &= ~(ADC_CCR_VBATE | ADC_CCR_TSVREFE);
+ }
+
/* if ADC1 Channel_18 is selected enable VBAT Channel */
if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
{
diff --git a/Src/stm32f7xx_hal_adc_ex.c b/Src/stm32f7xx_hal_adc_ex.c
index 27e4439..40f0587 100644
--- a/Src/stm32f7xx_hal_adc_ex.c
+++ b/Src/stm32f7xx_hal_adc_ex.c
@@ -5,7 +5,7 @@
* @brief This file provides firmware functions to manage the following
* functionalities of the ADC extension peripheral:
* + Extended features functions
- *
+ *
@verbatim
==============================================================================
##### How to use this driver #####
@@ -15,8 +15,8 @@
(##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
(##) ADC pins configuration
(+++) Enable the clock for the ADC GPIOs using the following function:
- __HAL_RCC_GPIOx_CLK_ENABLE()
- (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
+ __HAL_RCC_GPIOx_CLK_ENABLE()
+ (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
(##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
(+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
(+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
@@ -29,57 +29,45 @@
using __HAL_LINKDMA()
(+++) Configure the priority and enable the NVIC for the transfer complete
interrupt on the two DMA Streams. The output stream should have higher
- priority than the input stream.
- (#) Configure the ADC Prescaler, conversion resolution and data alignment
- using the HAL_ADC_Init() function.
-
+ priority than the input stream.
+ (#) Configure the ADC Prescaler, conversion resolution and data alignment
+ using the HAL_ADC_Init() function.
+
(#) Configure the ADC Injected channels group features, use HAL_ADC_Init()
and HAL_ADC_ConfigChannel() functions.
-
- (#) Three operation modes are available within this driver :
-
+
+ (#) Three operation modes are available within this driver :
+
*** Polling mode IO operation ***
=================================
- [..]
- (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart()
+ [..]
+ (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart()
(+) Wait for end of conversion using HAL_ADCEx_InjectedPollForConversion(), at this stage
- user can specify the value of timeout according to his end application
+ user can specify the value of timeout according to his end application
(+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() function.
(+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop()
-
- *** Interrupt mode IO operation ***
+
+ *** Interrupt mode IO operation ***
===================================
- [..]
- (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT()
+ [..]
+ (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT()
(+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
- (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
+ (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback
(+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
(+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT()
-
-
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_DMA(), at this stage the user specify the length
- of data to be transferred at each end of conversion
- (+) At The end of data transfer ba HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
- add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback
- (+) In case of transfer Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
- (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_DMA()
-
+
*** Multi mode ADCs Regular channels configuration ***
======================================================
- [..]
- (+) Select the Multi mode ADC regular channels features (dual or triple mode)
- and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions.
- (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length
- of data to be transferred at each end of conversion
+ [..]
+ (+) Select the Multi mode ADC regular channels features (dual or triple mode)
+ and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions.
+ (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length
+ of data to be transferred at each end of conversion
(+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function.
-
-
+
+
@endverbatim
******************************************************************************
* @attention
@@ -93,7 +81,7 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
diff --git a/Src/stm32f7xx_hal_can.c b/Src/stm32f7xx_hal_can.c
index a45b2a5..954f5ce 100644
--- a/Src/stm32f7xx_hal_can.c
+++ b/Src/stm32f7xx_hal_can.c
@@ -1556,7 +1556,7 @@
{
pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
}
- pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_RTR_Pos;
+ pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR);
pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
diff --git a/Src/stm32f7xx_hal_cryp.c b/Src/stm32f7xx_hal_cryp.c
index 36892d6..adc35bd 100644
--- a/Src/stm32f7xx_hal_cryp.c
+++ b/Src/stm32f7xx_hal_cryp.c
@@ -3,7 +3,7 @@
* @file stm32f7xx_hal_cryp.c
* @author MCD Application Team
* @brief CRYP HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Cryptography (CRYP) peripheral:
* + Initialization, de-initialization, set config and get config functions
* + DES/TDES, AES processing functions
@@ -64,6 +64,12 @@
(#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
+ (#)To process a single message with consecutive calls to HAL_CRYP_Encrypt() or HAL_CRYP_Decrypt()
+ without having to configure again the Key or the Initialization Vector between each API call,
+ the field KeyIVConfigSkip of the initialization structure must be set to CRYP_KEYIVCONFIG_ONCE.
+ Same is true for consecutive calls of HAL_CRYP_Encrypt_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_DMA()
+ or HAL_CRYP_Decrypt_DMA().
+
[..]
The cryptographic processor supports following standards:
(#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 IP:
@@ -237,16 +243,16 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
+ * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
@@ -254,9 +260,9 @@
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
-
+
#if defined (AES) || defined (CRYP)
-
+
/** @defgroup CRYP CRYP
* @brief CRYP HAL module driver.
* @{
@@ -276,36 +282,36 @@
#define CRYP_PHASE_READY 0x00000001U /*!< CRYP peripheral is ready for initialization. */
#define CRYP_PHASE_PROCESS 0x00000002U /*!< CRYP peripheral is in processing phase */
-
+
#if defined(AES)
#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode(Mode 1) */
#define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC decryptions (Mode 2) */
#define CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption (Mode 3) */
#define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE /*!< Key derivation and decryption only used when performing ECB and CBC decryptions (Mode 4) */
-#define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
-#define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */
-#define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */
-#define CRYP_PHASE_FINAL AES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */
+#define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
+#define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */
+#define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */
+#define CRYP_PHASE_FINAL AES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */
#else /* CRYP */
#define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
-#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0 /*!< GCM/GMAC or CCM header phase */
-#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1 /*!< GCM(/CCM) payload phase */
-#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH /*!< GCM/GMAC or CCM final phase */
+#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0 /*!< GCM/GMAC or CCM header phase */
+#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1 /*!< GCM(/CCM) payload phase */
+#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH /*!< GCM/GMAC or CCM final phase */
#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode */
#define CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR /*!< Decryption */
-#endif /* End CRYP or AES */
+#endif /* End CRYP or AES */
- /* CTR1 information to use in CCM algorithm */
-#define CRYP_CCM_CTR1_0 0x07FFFFFFU
-#define CRYP_CCM_CTR1_1 0xFFFFFF00U
-#define CRYP_CCM_CTR1_2 0x00000001U
+/* CTR1 information to use in CCM algorithm */
+#define CRYP_CCM_CTR1_0 0x07FFFFFFU
+#define CRYP_CCM_CTR1_1 0xFFFFFF00U
+#define CRYP_CCM_CTR1_2 0x00000001U
/**
* @}
*/
-
+
/* Private macro -------------------------------------------------------------*/
/** @addtogroup CRYP_Private_Macros
* @{
@@ -317,9 +323,9 @@
(__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
}while(0)
-#define HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)
-
-#else /*AES*/
+#define HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)
+
+#else /*AES*/
#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~AES_CR_GCMPH);\
(__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
}while(0)
@@ -328,14 +334,14 @@
/**
* @}
- */
-
+ */
+
/* Private struct -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup CRYP_Private_Functions_prototypes
* @{
- */
+ */
static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
@@ -350,7 +356,7 @@
static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp);
static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
-static HAL_StatusTypeDef CRYP_AESGCM_Process_IT (CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp);
@@ -376,7 +382,7 @@
/**
* @}
- */
+ */
/* Exported functions ---------------------------------------------------------*/
@@ -384,27 +390,27 @@
* @{
*/
-
-/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions.
- *
-@verbatim
+
+/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
========================================================================================
##### Initialization, de-initialization and Set and Get configuration functions #####
========================================================================================
[..] This section provides functions allowing to:
- (+) Initialize the CRYP
- (+) DeInitialize the CRYP
+ (+) Initialize the CRYP
+ (+) DeInitialize the CRYP
(+) Initialize the CRYP MSP
- (+) DeInitialize the CRYP MSP
+ (+) DeInitialize the CRYP MSP
(+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef
Parameters which are configured in This section are :
- (+) Key size
+ (+) Key size
(+) Data Type : 32,16, 8 or 1bit
- (+) AlgoMode :
- - for CRYP1 IP :
- ECB and CBC in DES/TDES Standard
- ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
+ (+) AlgoMode :
+ - for CRYP1 IP :
+ ECB and CBC in DES/TDES Standard
+ ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
- for TinyAES2 IP, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported.
(+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef
@@ -422,152 +428,155 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
-{
+{
/* Check the CRYP handle allocation */
- if(hcryp == NULL)
+ if (hcryp == NULL)
{
return HAL_ERROR;
- }
-
+ }
+
/* Check parameters */
assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
- assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
-
- #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
- if(hcryp->State == HAL_CRYP_STATE_RESET)
+ assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
+ assert_param(IS_CRYP_INIT(hcryp->Init.KeyIVConfigSkip));
+
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ if (hcryp->State == HAL_CRYP_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcryp->Lock = HAL_UNLOCKED;
-
+
hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
-
- if(hcryp->MspInitCallback == NULL)
+
+ if (hcryp->MspInitCallback == NULL)
{
hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak MspInit */
}
-
+
/* Init the low level hardware */
- hcryp->MspInitCallback(hcryp);
+ hcryp->MspInitCallback(hcryp);
}
#else
- if(hcryp->State == HAL_CRYP_STATE_RESET)
+ if (hcryp->State == HAL_CRYP_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcryp->Lock = HAL_UNLOCKED;
-
+
/* Init the low level hardware */
HAL_CRYP_MspInit(hcryp);
}
- #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
-
+#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
+
/* Set the key size(This bit field is donÂ’t care in the DES or TDES modes) data type and Algorithm */
#if defined (CRYP)
-
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE|CRYP_CR_KEYSIZE|CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
-
+
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
+ hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
+
#else /*AES*/
-
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_KEYSIZE|AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
-
+
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD,
+ hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
+
#endif /* End AES or CRYP*/
-
+
/* Reset Error Code field */
- hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
-
+ hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
+
/* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
+ hcryp->State = HAL_CRYP_STATE_READY;
+
/* Set the default CRYP phase */
hcryp->Phase = CRYP_PHASE_READY;
-
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief De-Initializes the CRYP peripheral.
+ * @brief De-Initializes the CRYP peripheral.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
{
/* Check the CRYP handle allocation */
- if(hcryp == NULL)
+ if (hcryp == NULL)
{
return HAL_ERROR;
}
-
+
/* Set the default CRYP phase */
hcryp->Phase = CRYP_PHASE_READY;
-
+
/* Reset CrypInCount and CrypOutCount */
hcryp->CrypInCount = 0;
hcryp->CrypOutCount = 0;
- hcryp->CrypHeaderCount =0;
-
+ hcryp->CrypHeaderCount = 0;
+
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
-
- if(hcryp->MspDeInitCallback == NULL)
+
+ if (hcryp->MspDeInitCallback == NULL)
{
hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak MspDeInit */
}
/* DeInit the low level hardware */
hcryp->MspDeInitCallback(hcryp);
-
+
#else
-
+
/* DeInit the low level hardware: CLOCK, NVIC.*/
HAL_CRYP_MspDeInit(hcryp);
-
+
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
-
+
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_RESET;
-
+
/* Release Lock */
__HAL_UNLOCK(hcryp);
-
+
/* Return function status */
return HAL_OK;
}
-
+
/**
* @brief Configure the CRYP according to the specified
- * parameters in the CRYP_ConfigTypeDef
+ * parameters in the CRYP_ConfigTypeDef
* @param hcryp: pointer to a CRYP_HandleTypeDef structure
* @param pConf: pointer to a CRYP_ConfigTypeDef structure that contains
* the configuration information for CRYP module
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf )
-{
+HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
+{
/* Check the CRYP handle allocation */
- if((hcryp == NULL)|| (pConf == NULL) )
+ if ((hcryp == NULL) || (pConf == NULL))
{
return HAL_ERROR;
}
-
+
/* Check parameters */
assert_param(IS_CRYP_KEYSIZE(pConf->KeySize));
assert_param(IS_CRYP_DATATYPE(pConf->DataType));
assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm));
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_BUSY;
-
+
/* Process locked */
- __HAL_LOCK(hcryp);
-
- /* Set CRYP parameters */
+ __HAL_LOCK(hcryp);
+
+ /* Set CRYP parameters */
hcryp->Init.DataType = pConf->DataType;
hcryp->Init.pKey = pConf->pKey;
hcryp->Init.Algorithm = pConf->Algorithm;
@@ -577,42 +586,44 @@
hcryp->Init.HeaderSize = pConf->HeaderSize;
hcryp->Init.B0 = pConf->B0;
hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
-
- /* Set the key size(This bit field is donÂ’t care in the DES or TDES modes) data type, AlgoMode and operating mode*/
-#if defined (CRYP)
-
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE|CRYP_CR_KEYSIZE|CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
-
+
+ /* Set the key size(This bit field is donÂ’t care in the DES or TDES modes) data type, AlgoMode and operating mode*/
+#if defined (CRYP)
+
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
+ hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
+
#else /*AES*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_KEYSIZE|AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
-
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD,
+ hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
+
/*clear error flags*/
- __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_ERR_CLEAR);
-
-#endif /* End AES or CRYP */
-
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR);
+
+#endif /* End AES or CRYP */
+
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
-
+
/* Reset Error Code field */
- hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
-
+ hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
+
/* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
+ hcryp->State = HAL_CRYP_STATE_READY;
+
/* Set the default CRYP phase */
hcryp->Phase = CRYP_PHASE_READY;
-
+
/* Return function status */
return HAL_OK;
}
else
{
/* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
+ __HAL_UNLOCK(hcryp);
+
/* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
return HAL_ERROR;
}
}
@@ -624,23 +635,23 @@
* the configuration information for CRYP module
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf )
-{
+HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
+{
/* Check the CRYP handle allocation */
- if((hcryp == NULL)|| (pConf == NULL) )
+ if ((hcryp == NULL) || (pConf == NULL))
{
return HAL_ERROR;
}
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_BUSY;
-
+
/* Process locked */
- __HAL_LOCK(hcryp);
-
- /* Get CRYP parameters */
+ __HAL_LOCK(hcryp);
+
+ /* Get CRYP parameters */
pConf->DataType = hcryp->Init.DataType;
pConf->pKey = hcryp->Init.pKey;
pConf->Algorithm = hcryp->Init.Algorithm;
@@ -650,23 +661,23 @@
pConf->HeaderSize = hcryp->Init.HeaderSize;
pConf->B0 = hcryp->Init.B0;
pConf->DataWidthUnit = hcryp->Init.DataWidthUnit;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
-
+
/* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
+ hcryp->State = HAL_CRYP_STATE_READY;
+
/* Return function status */
return HAL_OK;
}
else
{
/* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
+ __HAL_UNLOCK(hcryp);
+
/* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
return HAL_ERROR;
}
}
@@ -680,7 +691,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CRYP_MspInit could be implemented in the user file
*/
@@ -696,7 +707,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CRYP_MspDeInit could be implemented in the user file
*/
@@ -711,76 +722,77 @@
* This parameter can be one of the following values:
* @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
* @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
- * @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
* @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
+ pCRYP_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
-
- if(pCallback == NULL)
+
+ if (pCallback == NULL)
{
/* Update the error code */
hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
-
+
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hcryp);
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
{
switch (CallbackID)
{
- case HAL_CRYP_INPUT_COMPLETE_CB_ID :
- hcryp->InCpltCallback = pCallback;
- break;
-
- case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
- hcryp->OutCpltCallback = pCallback;
- break;
-
- case HAL_CRYP_ERROR_CB_ID :
- hcryp->ErrorCallback = pCallback;
- break;
-
- case HAL_CRYP_MSPINIT_CB_ID :
- hcryp->MspInitCallback = pCallback;
- break;
-
- case HAL_CRYP_MSPDEINIT_CB_ID :
- hcryp->MspDeInitCallback = pCallback;
- break;
-
- default :
- /* Update the error code */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
- /* Return error status */
- status = HAL_ERROR;
- break;
+ case HAL_CRYP_INPUT_COMPLETE_CB_ID :
+ hcryp->InCpltCallback = pCallback;
+ break;
+
+ case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
+ hcryp->OutCpltCallback = pCallback;
+ break;
+
+ case HAL_CRYP_ERROR_CB_ID :
+ hcryp->ErrorCallback = pCallback;
+ break;
+
+ case HAL_CRYP_MSPINIT_CB_ID :
+ hcryp->MspInitCallback = pCallback;
+ break;
+
+ case HAL_CRYP_MSPDEINIT_CB_ID :
+ hcryp->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(hcryp->State == HAL_CRYP_STATE_RESET)
+ else if (hcryp->State == HAL_CRYP_STATE_RESET)
{
switch (CallbackID)
{
- case HAL_CRYP_MSPINIT_CB_ID :
- hcryp->MspInitCallback = pCallback;
- break;
-
- case HAL_CRYP_MSPDEINIT_CB_ID :
- hcryp->MspDeInitCallback = pCallback;
- break;
-
- default :
- /* Update the error code */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
- /* Return error status */
- status = HAL_ERROR;
- break;
+ case HAL_CRYP_MSPINIT_CB_ID :
+ hcryp->MspInitCallback = pCallback;
+ break;
+
+ case HAL_CRYP_MSPDEINIT_CB_ID :
+ hcryp->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -790,10 +802,10 @@
/* Return error status */
status = HAL_ERROR;
}
-
+
/* Release Lock */
__HAL_UNLOCK(hcryp);
-
+
return status;
}
@@ -805,7 +817,7 @@
* This parameter can be one of the following values:
* @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
* @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
- * @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
* @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval status
@@ -813,60 +825,60 @@
HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
-
+
/* Process locked */
__HAL_LOCK(hcryp);
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
{
switch (CallbackID)
{
- case HAL_CRYP_INPUT_COMPLETE_CB_ID :
- hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
- break;
-
- case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
- hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
- break;
-
- case HAL_CRYP_ERROR_CB_ID :
- hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
- break;
-
- case HAL_CRYP_MSPINIT_CB_ID :
- hcryp->MspInitCallback = HAL_CRYP_MspInit;
- break;
-
- case HAL_CRYP_MSPDEINIT_CB_ID :
- hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
- break;
-
- default :
- /* Update the error code */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
- /* Return error status */
- status = HAL_ERROR;
- break;
+ case HAL_CRYP_INPUT_COMPLETE_CB_ID :
+ hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
+ break;
+
+ case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
+ hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
+ break;
+
+ case HAL_CRYP_ERROR_CB_ID :
+ hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_CRYP_MSPINIT_CB_ID :
+ hcryp->MspInitCallback = HAL_CRYP_MspInit;
+ break;
+
+ case HAL_CRYP_MSPDEINIT_CB_ID :
+ hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(hcryp->State == HAL_CRYP_STATE_RESET)
+ else if (hcryp->State == HAL_CRYP_STATE_RESET)
{
switch (CallbackID)
{
- case HAL_CRYP_MSPINIT_CB_ID :
- hcryp->MspInitCallback = HAL_CRYP_MspInit;
- break;
-
- case HAL_CRYP_MSPDEINIT_CB_ID :
- hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
- break;
-
- default :
- /* Update the error code */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
- /* Return error status */
- status = HAL_ERROR;
- break;
+ case HAL_CRYP_MSPINIT_CB_ID :
+ hcryp->MspInitCallback = HAL_CRYP_MspInit;
+ break;
+
+ case HAL_CRYP_MSPDEINIT_CB_ID :
+ hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -876,10 +888,10 @@
/* Return error status */
status = HAL_ERROR;
}
-
+
/* Release Lock */
__HAL_UNLOCK(hcryp);
-
+
return status;
}
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
@@ -887,16 +899,16 @@
* @}
*/
-/** @defgroup CRYP_Exported_Functions_Group2 Encrypt Decrypt functions
- * @brief processing functions.
- *
-@verbatim
+/** @defgroup CRYP_Exported_Functions_Group2 Encrypt Decrypt functions
+ * @brief processing functions.
+ *
+@verbatim
==============================================================================
##### Encrypt Decrypt functions #####
- ==============================================================================
- [..] This section provides API allowing to Encrypt/Decrypt Data following
+ ==============================================================================
+ [..] This section provides API allowing to Encrypt/Decrypt Data following
Standard DES/TDES or AES, and Algorithm configured by the user:
- (+) Standard DES/TDES only supported by CRYP1 IP, below list of Algorithm supported :
+ (+) Standard DES/TDES only supported by CRYP1 IP, below list of Algorithm supported :
- Electronic Code Book(ECB)
- Cipher Block Chaining (CBC)
(+) Standard AES supported by CRYP1 IP & TinyAES, list of Algorithm supported:
@@ -906,7 +918,7 @@
- Cipher Block Chaining (CBC)
- Counter mode (CTR)
- Galois/counter mode (GCM)
- - Counter with Cipher Block Chaining-Message(CCM)
+ - Counter with Cipher Block Chaining-Message(CCM)
[..] Three processing functions are available:
(+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
(+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
@@ -924,28 +936,29 @@
* @param Input: Pointer to the input buffer (plaintext)
* @param Size: Length of the plaintext buffer in word.
* @param Output: Pointer to the output buffer(ciphertext)
- * @param Timeout: Specify Timeout value
+ * @param Timeout: Specify Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
+ uint32_t Timeout)
{
uint32_t algo;
HAL_StatusTypeDef status;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
/* Change state Busy */
hcryp->State = HAL_CRYP_STATE_BUSY;
-
+
/* Process locked */
__HAL_LOCK(hcryp);
-
+
/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
hcryp->CrypInCount = 0U;
hcryp->CrypOutCount = 0U;
hcryp->pCrypInBuffPtr = Input;
hcryp->pCrypOutBuffPtr = Output;
-
+
/* Calculate Size parameter in Byte*/
if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
{
@@ -953,132 +966,140 @@
}
else
{
- hcryp->Size = Size;
+ hcryp->Size = Size;
}
-
-#if defined (CRYP)
- /* Set Encryption operating mode*/
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
-
- /* algo get algorithm selected */
+
+#if defined (CRYP)
+ /* Set Encryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
+
+ /* algo get algorithm selected */
algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
-
- switch(algo)
- {
- case CRYP_DES_ECB:
- case CRYP_DES_CBC:
- case CRYP_TDES_ECB:
- case CRYP_TDES_CBC:
-
- /*Set Key */
- hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
- if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
- hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
- }
-
- /*Set Initialization Vector (IV)*/
- if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- }
-
- /* Flush FIFO */
- HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Statrt DES/TDES encryption process */
- status = CRYP_TDES_Process(hcryp,Timeout);
- break;
-
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- /* AES encryption */
- status = CRYP_AES_Encrypt(hcryp, Timeout);
- break;
-
- case CRYP_AES_GCM:
-
- /* AES GCM encryption */
- status = CRYP_AESGCM_Process(hcryp, Timeout);
-
- break;
-
- case CRYP_AES_CCM:
-
- /* AES CCM encryption */
- status = CRYP_AESCCM_Process(hcryp,Timeout);
- break;
-
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- return HAL_ERROR;
- }
-
-#else /*AES*/
-
- /* Set the operating mode*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
-
- /* algo get algorithm selected */
- algo = hcryp->Instance->CR & AES_CR_CHMOD;
-
- switch(algo)
- {
-
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- /* AES encryption */
- status = CRYP_AES_Encrypt(hcryp, Timeout);
- break;
-
- case CRYP_AES_GCM_GMAC:
-
- /* AES GCM encryption */
- status = CRYP_AESGCM_Process (hcryp,Timeout) ;
- break;
-
- case CRYP_AES_CCM:
-
- /* AES CCM encryption */
- status = CRYP_AESCCM_Process(hcryp,Timeout);
- break;
-
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- return HAL_ERROR;
+
+ switch (algo)
+ {
+ case CRYP_DES_ECB:
+ case CRYP_DES_CBC:
+ case CRYP_TDES_ECB:
+ case CRYP_TDES_CBC:
+
+ /*Set Key */
+ hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
+ hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
+ if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
+ hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
+ hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
+ hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
+ }
+
+ /*Set Initialization Vector (IV)*/
+ if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ }
+
+ /* Flush FIFO */
+ HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Statrt DES/TDES encryption process */
+ status = CRYP_TDES_Process(hcryp, Timeout);
+ break;
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* AES encryption */
+ status = CRYP_AES_Encrypt(hcryp, Timeout);
+ break;
+
+ case CRYP_AES_GCM:
+
+ /* AES GCM encryption */
+ status = CRYP_AESGCM_Process(hcryp, Timeout);
+
+ break;
+
+ case CRYP_AES_CCM:
+
+ /* AES CCM encryption */
+ status = CRYP_AESCCM_Process(hcryp, Timeout);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
}
-#endif /*end AES or CRYP */
-
+
+#else /*AES*/
+
+ /* Set the operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
+
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
+
+ switch (algo)
+ {
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* AES encryption */
+ status = CRYP_AES_Encrypt(hcryp, Timeout);
+ break;
+
+ case CRYP_AES_GCM_GMAC:
+
+ /* AES GCM encryption */
+ status = CRYP_AESGCM_Process(hcryp, Timeout) ;
+ break;
+
+ case CRYP_AES_CCM:
+
+ /* AES CCM encryption */
+ status = CRYP_AESCCM_Process(hcryp, Timeout);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+#endif /*end AES or CRYP */
+
if (status == HAL_OK)
- {
+ {
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Process unlocked */
__HAL_UNLOCK(hcryp);
- }
+ }
}
else
{
/* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
return HAL_ERROR;
- }
-
+ }
+
/* Return function status */
- return HAL_OK;
+ return HAL_OK;
}
/**
@@ -1088,28 +1109,29 @@
* @param Input: Pointer to the input buffer (ciphertext )
* @param Size: Length of the plaintext buffer in word.
* @param Output: Pointer to the output buffer(plaintext)
- * @param Timeout: Specify Timeout value
+ * @param Timeout: Specify Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
+ uint32_t Timeout)
{
HAL_StatusTypeDef status;
- uint32_t algo;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
+ uint32_t algo;
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Change state Busy */
hcryp->State = HAL_CRYP_STATE_BUSY;
-
+
/* Process locked */
- __HAL_LOCK(hcryp);
-
+ __HAL_LOCK(hcryp);
+
/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
hcryp->CrypInCount = 0U;
hcryp->CrypOutCount = 0U;
hcryp->pCrypInBuffPtr = Input;
hcryp->pCrypOutBuffPtr = Output;
-
+
/* Calculate Size parameter in Byte*/
if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
{
@@ -1117,133 +1139,141 @@
}
else
{
- hcryp->Size = Size;
+ hcryp->Size = Size;
}
-
+
#if defined (CRYP)
-
+
/* Set Decryption operating mode*/
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
-
- /* algo get algorithm selected */
+
+ /* algo get algorithm selected */
algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
-
- switch(algo)
- {
- case CRYP_DES_ECB:
- case CRYP_DES_CBC:
- case CRYP_TDES_ECB:
- case CRYP_TDES_CBC:
-
- /*Set Key */
- hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
- if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
- hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
- }
-
- /*Set Initialization Vector (IV)*/
- if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- }
-
- /* Flush FIFO */
- HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Start DES/TDES decryption process */
- status = CRYP_TDES_Process(hcryp, Timeout);
-
- break;
-
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- /* AES decryption */
- status = CRYP_AES_Decrypt(hcryp, Timeout);
- break;
-
- case CRYP_AES_GCM:
-
- /* AES GCM decryption */
- status = CRYP_AESGCM_Process (hcryp, Timeout) ;
- break;
-
- case CRYP_AES_CCM:
-
- /* AES CCM decryption */
- status = CRYP_AESCCM_Process(hcryp, Timeout);
- break;
-
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- return HAL_ERROR;
- }
-
-#else /*AES*/
-
- /* Set Decryption operating mode*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
-
- /* algo get algorithm selected */
- algo = hcryp->Instance->CR & AES_CR_CHMOD;
-
- switch(algo)
- {
-
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- /* AES decryption */
- status = CRYP_AES_Decrypt(hcryp, Timeout);
- break;
-
- case CRYP_AES_GCM_GMAC:
-
- /* AES GCM decryption */
- status = CRYP_AESGCM_Process (hcryp, Timeout) ;
- break;
-
- case CRYP_AES_CCM:
-
- /* AES CCM decryption */
- status = CRYP_AESCCM_Process(hcryp, Timeout);
- break;
-
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- return HAL_ERROR;
+
+ switch (algo)
+ {
+ case CRYP_DES_ECB:
+ case CRYP_DES_CBC:
+ case CRYP_TDES_ECB:
+ case CRYP_TDES_CBC:
+
+ /*Set Key */
+ hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
+ hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
+ if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
+ hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
+ hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
+ hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
+ }
+
+ /*Set Initialization Vector (IV)*/
+ if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ }
+
+ /* Flush FIFO */
+ HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Start DES/TDES decryption process */
+ status = CRYP_TDES_Process(hcryp, Timeout);
+
+ break;
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* AES decryption */
+ status = CRYP_AES_Decrypt(hcryp, Timeout);
+ break;
+
+ case CRYP_AES_GCM:
+
+ /* AES GCM decryption */
+ status = CRYP_AESGCM_Process(hcryp, Timeout) ;
+ break;
+
+ case CRYP_AES_CCM:
+
+ /* AES CCM decryption */
+ status = CRYP_AESCCM_Process(hcryp, Timeout);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
}
-#endif /* End AES or CRYP */
-
+
+#else /*AES*/
+
+ /* Set Decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
+
+ switch (algo)
+ {
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* AES decryption */
+ status = CRYP_AES_Decrypt(hcryp, Timeout);
+ break;
+
+ case CRYP_AES_GCM_GMAC:
+
+ /* AES GCM decryption */
+ status = CRYP_AESGCM_Process(hcryp, Timeout) ;
+ break;
+
+ case CRYP_AES_CCM:
+
+ /* AES CCM decryption */
+ status = CRYP_AESCCM_Process(hcryp, Timeout);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+#endif /* End AES or CRYP */
+
if (status == HAL_OK)
- {
+ {
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Process unlocked */
__HAL_UNLOCK(hcryp);
- }
+ }
}
else
{
/* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
return HAL_ERROR;
}
-
+
/* Return function status */
- return HAL_OK;
+ return HAL_OK;
}
/**
@@ -1257,23 +1287,23 @@
*/
HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
{
- uint32_t algo;
+ uint32_t algo;
HAL_StatusTypeDef status = HAL_OK;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Change state Busy */
hcryp->State = HAL_CRYP_STATE_BUSY;
-
+
/* Process locked */
__HAL_LOCK(hcryp);
-
+
/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
hcryp->CrypInCount = 0U;
hcryp->CrypOutCount = 0U;
hcryp->pCrypInBuffPtr = Input;
- hcryp->pCrypOutBuffPtr = Output;
-
+ hcryp->pCrypOutBuffPtr = Output;
+
/* Calculate Size parameter in Byte*/
if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
{
@@ -1281,124 +1311,132 @@
}
else
{
- hcryp->Size = Size;
+ hcryp->Size = Size;
}
-
+
#if defined (CRYP)
-
- /* Set encryption operating mode*/
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
-
- /* algo get algorithm selected */
- algo = (hcryp->Instance->CR & CRYP_CR_ALGOMODE);
-
- switch(algo)
- {
- case CRYP_DES_ECB:
- case CRYP_DES_CBC:
- case CRYP_TDES_ECB:
- case CRYP_TDES_CBC:
-
- /*Set Key */
- hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
- if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
- hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
- }
- /* Set the Initialization Vector*/
- if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- }
-
- /* Flush FIFO */
- HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Enable interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-
- /* Enable CRYP to start DES/TDES process*/
- __HAL_CRYP_ENABLE(hcryp);
- break;
-
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- status = CRYP_AES_Encrypt_IT(hcryp);
- break;
-
- case CRYP_AES_GCM:
-
- status = CRYP_AESGCM_Process_IT (hcryp) ;
- break;
-
- case CRYP_AES_CCM:
-
- status = CRYP_AESCCM_Process_IT(hcryp);
- break;
-
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- status = HAL_ERROR;
- break;
- }
-
-#else /* AES */
-
+
/* Set encryption operating mode*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
-
- /* algo get algorithm selected */
- algo = hcryp->Instance->CR & AES_CR_CHMOD;
-
- switch(algo)
- {
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- /* AES encryption */
- status = CRYP_AES_Encrypt_IT(hcryp);
- break;
-
- case CRYP_AES_GCM_GMAC:
-
- /* AES GCM encryption */
- status = CRYP_AESGCM_Process_IT (hcryp) ;
- break;
-
- case CRYP_AES_CCM:
-
- /* AES CCM encryption */
- status = CRYP_AESCCM_Process_IT(hcryp);
- break;
-
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- status = HAL_ERROR;
- break;
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
+
+ /* algo get algorithm selected */
+ algo = (hcryp->Instance->CR & CRYP_CR_ALGOMODE);
+
+ switch (algo)
+ {
+ case CRYP_DES_ECB:
+ case CRYP_DES_CBC:
+ case CRYP_TDES_ECB:
+ case CRYP_TDES_CBC:
+
+ /*Set Key */
+ hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
+ hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
+ if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
+ hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
+ hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
+ hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
+ }
+ /* Set the Initialization Vector*/
+ if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ }
+
+ /* Flush FIFO */
+ HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Enable interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+ /* Enable CRYP to start DES/TDES process*/
+ __HAL_CRYP_ENABLE(hcryp);
+ break;
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ status = CRYP_AES_Encrypt_IT(hcryp);
+ break;
+
+ case CRYP_AES_GCM:
+
+ status = CRYP_AESGCM_Process_IT(hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+
+ status = CRYP_AESCCM_Process_IT(hcryp);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ status = HAL_ERROR;
+ break;
}
-#endif /*end AES or CRYP*/
-
+
+#else /* AES */
+
+ /* Set encryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
+
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
+
+ switch (algo)
+ {
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* AES encryption */
+ status = CRYP_AES_Encrypt_IT(hcryp);
+ break;
+
+ case CRYP_AES_GCM_GMAC:
+
+ /* AES GCM encryption */
+ status = CRYP_AESGCM_Process_IT(hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+
+ /* AES CCM encryption */
+ status = CRYP_AESCCM_Process_IT(hcryp);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ status = HAL_ERROR;
+ break;
+ }
+#endif /*end AES or CRYP*/
+
}
else
{
/* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
status = HAL_ERROR;
- }
-
+ }
+
/* Return function status */
- return status;
+ return status;
}
/**
@@ -1414,21 +1452,21 @@
{
uint32_t algo;
HAL_StatusTypeDef status = HAL_OK;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
/* Change state Busy */
hcryp->State = HAL_CRYP_STATE_BUSY;
-
+
/* Process locked */
- __HAL_LOCK(hcryp);
-
+ __HAL_LOCK(hcryp);
+
/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
hcryp->CrypInCount = 0U;
hcryp->CrypOutCount = 0U;
hcryp->pCrypInBuffPtr = Input;
hcryp->pCrypOutBuffPtr = Output;
-
+
/* Calculate Size parameter in Byte*/
if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
{
@@ -1436,128 +1474,136 @@
}
else
{
- hcryp->Size = Size;
+ hcryp->Size = Size;
}
-
+
#if defined (CRYP)
-
+
/* Set decryption operating mode*/
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR,CRYP_OPERATINGMODE_DECRYPT);
-
- /* algo get algorithm selected */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
+
+ /* algo get algorithm selected */
algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
-
- switch(algo)
- {
- case CRYP_DES_ECB:
- case CRYP_DES_CBC:
- case CRYP_TDES_ECB:
- case CRYP_TDES_CBC:
-
- /*Set Key */
- hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
- if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
- hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
- }
-
- /* Set the Initialization Vector*/
- if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- }
- /* Flush FIFO */
- HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Enable interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-
- /* Enable CRYP and start DES/TDES process*/
- __HAL_CRYP_ENABLE(hcryp);
-
- break;
-
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- /* AES decryption */
- status = CRYP_AES_Decrypt_IT(hcryp);
- break;
-
- case CRYP_AES_GCM:
-
- /* AES GCM decryption */
- status = CRYP_AESGCM_Process_IT (hcryp) ;
- break;
-
- case CRYP_AES_CCM:
-
- /* AES CCMdecryption */
- status = CRYP_AESCCM_Process_IT(hcryp);
- break;
-
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- status = HAL_ERROR;
- break;
+
+ switch (algo)
+ {
+ case CRYP_DES_ECB:
+ case CRYP_DES_CBC:
+ case CRYP_TDES_ECB:
+ case CRYP_TDES_CBC:
+
+ /*Set Key */
+ hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
+ hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
+ if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
+ hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
+ hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
+ hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
+ }
+
+ /* Set the Initialization Vector*/
+ if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ }
+ /* Flush FIFO */
+ HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Enable interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+ /* Enable CRYP and start DES/TDES process*/
+ __HAL_CRYP_ENABLE(hcryp);
+
+ break;
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* AES decryption */
+ status = CRYP_AES_Decrypt_IT(hcryp);
+ break;
+
+ case CRYP_AES_GCM:
+
+ /* AES GCM decryption */
+ status = CRYP_AESGCM_Process_IT(hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+
+ /* AES CCMdecryption */
+ status = CRYP_AESCCM_Process_IT(hcryp);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ status = HAL_ERROR;
+ break;
}
-
+
#else /*AES*/
-
+
/* Set decryption operating mode*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
-
- /* algo get algorithm selected */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+
+ /* algo get algorithm selected */
algo = hcryp->Instance->CR & AES_CR_CHMOD;
-
- switch(algo)
- {
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- /* AES decryption */
- status = CRYP_AES_Decrypt_IT(hcryp);
- break;
-
- case CRYP_AES_GCM_GMAC:
-
- /* AES GCM decryption */
- status = CRYP_AESGCM_Process_IT (hcryp) ;
- break;
-
- case CRYP_AES_CCM:
-
- /* AES CCM decryption */
- status = CRYP_AESCCM_Process_IT(hcryp);
- break;
-
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- status = HAL_ERROR;
- break;
+
+ switch (algo)
+ {
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* AES decryption */
+ status = CRYP_AES_Decrypt_IT(hcryp);
+ break;
+
+ case CRYP_AES_GCM_GMAC:
+
+ /* AES GCM decryption */
+ status = CRYP_AESGCM_Process_IT(hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+
+ /* AES CCM decryption */
+ status = CRYP_AESCCM_Process_IT(hcryp);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ status = HAL_ERROR;
+ break;
}
-#endif /* End AES or CRYP */
-
+#endif /* End AES or CRYP */
+
}
else
{
/* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
status = HAL_ERROR;
- }
-
+ }
+
/* Return function status */
- return status;
+ return status;
}
/**
@@ -1571,23 +1617,24 @@
*/
HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
{
- uint32_t algo;
+ uint32_t algo;
HAL_StatusTypeDef status = HAL_OK;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Change state Busy */
hcryp->State = HAL_CRYP_STATE_BUSY;
-
+
/* Process locked */
__HAL_LOCK(hcryp);
-
+
/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
hcryp->CrypInCount = 0U;
hcryp->CrypOutCount = 0U;
hcryp->pCrypInBuffPtr = Input;
hcryp->pCrypOutBuffPtr = Output;
-
+
/* Calculate Size parameter in Byte*/
if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
{
@@ -1595,150 +1642,200 @@
}
else
{
- hcryp->Size = Size;
+ hcryp->Size = Size;
}
-
+
#if defined (CRYP)
-
- /* Set encryption operating mode*/
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
-
- /* algo get algorithm selected */
- algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
-
- switch(algo)
- {
- case CRYP_DES_ECB:
- case CRYP_DES_CBC:
- case CRYP_TDES_ECB:
- case CRYP_TDES_CBC:
-
- /*Set Key */
- hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
- if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
- hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
- }
-
- /* Set the Initialization Vector*/
- if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- }
-
- /* Flush FIFO */
- HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Start DMA process transfer for DES/TDES */
- CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size)/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
- break;
-
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Set the Initialization Vector IV */
- if (hcryp->Init.Algorithm != CRYP_AES_ECB)
- {
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
- }
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Start DMA process transfer for AES */
- CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size)/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
- break;
-
- case CRYP_AES_GCM:
- /* AES GCM encryption */
- status = CRYP_AESGCM_Process_DMA (hcryp) ;
- break;
-
- case CRYP_AES_CCM:
- /* AES CCM encryption */
- status = CRYP_AESCCM_Process_DMA(hcryp);
- break;
-
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- status = HAL_ERROR;
- break;
- }
-
-#else /*AES*/
+
/* Set encryption operating mode*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
-
- /* algo get algorithm selected */
- algo = hcryp->Instance->CR & AES_CR_CHMOD;
-
- switch(algo)
- {
-
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Set the Initialization Vector*/
- if (hcryp->Init.Algorithm != CRYP_AES_ECB)
- {
- hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
- }
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Start DMA process transfer for AES */
- CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
- break;
-
- case CRYP_AES_GCM_GMAC:
- /* AES GCM encryption */
- status = CRYP_AESGCM_Process_DMA (hcryp) ;
- break;
-
- case CRYP_AES_CCM:
- /* AES CCM encryption */
- status = CRYP_AESCCM_Process_DMA(hcryp);
- break;
-
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- status = HAL_ERROR;
- break;
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
+
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
+
+ switch (algo)
+ {
+ case CRYP_DES_ECB:
+ case CRYP_DES_CBC:
+ case CRYP_TDES_ECB:
+ case CRYP_TDES_CBC:
+
+ /*Set Key */
+ hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
+ hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
+ if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
+ hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
+ hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
+ hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
+ }
+
+ /* Set the Initialization Vector*/
+ if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ }
+
+ /* Flush FIFO */
+ HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Start DMA process transfer for DES/TDES */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U),
+ (uint32_t)(hcryp->pCrypOutBuffPtr));
+ break;
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ {
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ }
+ }
+
+ if (DoKeyIVConfig == 1U)
+ {
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set the Initialization Vector*/
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
+ hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
+ hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
+ }
+ } /* if (DoKeyIVConfig == 1U) */
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Start DMA process transfer for AES */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U),
+ (uint32_t)(hcryp->pCrypOutBuffPtr));
+ break;
+
+ case CRYP_AES_GCM:
+ /* AES GCM encryption */
+ status = CRYP_AESGCM_Process_DMA(hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+ /* AES CCM encryption */
+ status = CRYP_AESCCM_Process_DMA(hcryp);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ status = HAL_ERROR;
+ break;
}
-#endif /* End AES or CRYP */
-
+
+#else /*AES*/
+ /* Set encryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
+
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
+
+ switch (algo)
+ {
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ {
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ }
+ }
+
+ if (DoKeyIVConfig == 1U)
+ {
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set the Initialization Vector*/
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+ }
+ } /* if (DoKeyIVConfig == 1U) */
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Start DMA process transfer for AES */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
+ break;
+
+ case CRYP_AES_GCM_GMAC:
+ /* AES GCM encryption */
+ status = CRYP_AESGCM_Process_DMA(hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+ /* AES CCM encryption */
+ status = CRYP_AESCCM_Process_DMA(hcryp);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ status = HAL_ERROR;
+ break;
+ }
+#endif /* End AES or CRYP */
+
}
else
{
/* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
status = HAL_ERROR;
- }
-
+ }
+
/* Return function status */
- return status;
+ return status;
}
/**
@@ -1752,24 +1849,24 @@
*/
HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
{
- uint32_t algo;
+ uint32_t algo;
HAL_StatusTypeDef status = HAL_OK;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
{
-
+
/* Change state Busy */
hcryp->State = HAL_CRYP_STATE_BUSY;
-
+
/* Process locked */
- __HAL_LOCK(hcryp);
-
+ __HAL_LOCK(hcryp);
+
/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
hcryp->CrypInCount = 0U;
hcryp->CrypOutCount = 0U;
hcryp->pCrypInBuffPtr = Input;
hcryp->pCrypOutBuffPtr = Output;
-
+
/* Calculate Size parameter in Byte*/
if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
{
@@ -1777,140 +1874,149 @@
}
else
{
- hcryp->Size = Size;
- }
-
+ hcryp->Size = Size;
+ }
+
#if defined (CRYP)
-
+
/* Set decryption operating mode*/
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
-
- /* algo get algorithm selected */
+
+ /* algo get algorithm selected */
algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
-
- switch(algo)
- {
- case CRYP_DES_ECB:
- case CRYP_DES_CBC:
- case CRYP_TDES_ECB:
- case CRYP_TDES_CBC:
-
- /*Set Key */
- hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
- if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
- hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
- }
-
- /* Set the Initialization Vector*/
- if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- }
-
- /* Flush FIFO */
- HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Start DMA process transfer for DES/TDES */
- CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size)/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
- break;
-
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- /* AES decryption */
- status = CRYP_AES_Decrypt_DMA(hcryp);
- break;
-
- case CRYP_AES_GCM:
- /* AES GCM decryption */
- status = CRYP_AESGCM_Process_DMA (hcryp) ;
- break;
-
- case CRYP_AES_CCM:
- /* AES CCM decryption */
- status = CRYP_AESCCM_Process_DMA(hcryp);
- break;
-
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- status = HAL_ERROR;
- break;
+
+ switch (algo)
+ {
+ case CRYP_DES_ECB:
+ case CRYP_DES_CBC:
+ case CRYP_TDES_ECB:
+ case CRYP_TDES_CBC:
+
+ /*Set Key */
+ hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
+ hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
+ if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
+ hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
+ hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
+ hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
+ }
+
+ /* Set the Initialization Vector*/
+ if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ }
+
+ /* Flush FIFO */
+ HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Start DMA process transfer for DES/TDES */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U),
+ (uint32_t)(hcryp->pCrypOutBuffPtr));
+ break;
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* AES decryption */
+ status = CRYP_AES_Decrypt_DMA(hcryp);
+ break;
+
+ case CRYP_AES_GCM:
+ /* AES GCM decryption */
+ status = CRYP_AESGCM_Process_DMA(hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+ /* AES CCM decryption */
+ status = CRYP_AESCCM_Process_DMA(hcryp);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ status = HAL_ERROR;
+ break;
}
-
+
#else /*AES*/
-
+
/* Set decryption operating mode*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
-
- /* algo get algorithm selected */
+
+ /* algo get algorithm selected */
algo = hcryp->Instance->CR & AES_CR_CHMOD;
-
- switch(algo)
- {
-
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- /* AES decryption */
- status = CRYP_AES_Decrypt_DMA(hcryp);
- break;
-
- case CRYP_AES_GCM_GMAC:
- /* AES GCM decryption */
- status = CRYP_AESGCM_Process_DMA (hcryp) ;
- break;
-
- case CRYP_AES_CCM:
- /* AES CCM decryption */
- status = CRYP_AESCCM_Process_DMA(hcryp);
- break;
-
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- status = HAL_ERROR;
- break;
+
+ switch (algo)
+ {
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* AES decryption */
+ status = CRYP_AES_Decrypt_DMA(hcryp);
+ break;
+
+ case CRYP_AES_GCM_GMAC:
+ /* AES GCM decryption */
+ status = CRYP_AESGCM_Process_DMA(hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+ /* AES CCM decryption */
+ status = CRYP_AESCCM_Process_DMA(hcryp);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ status = HAL_ERROR;
+ break;
}
-#endif /* End AES or CRYP */
+#endif /* End AES or CRYP */
}
else
{
/* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
status = HAL_ERROR;
}
-
+
/* Return function status */
- return status;
+ return status;
}
/**
* @}
*/
-/** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management
- * @brief CRYP IRQ handler.
- *
-@verbatim
+/** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management
+ * @brief CRYP IRQ handler.
+ *
+@verbatim
==============================================================================
##### CRYP IRQ handler management #####
- ==============================================================================
+ ==============================================================================
[..] This section provides CRYP IRQ handler and callback functions.
(+) HAL_CRYP_IRQHandler CRYP interrupt request
(+) HAL_CRYP_InCpltCallback input data transfer complete callback
(+) HAL_CRYP_OutCpltCallback output data transfer complete callback
(+) HAL_CRYP_ErrorCallback CRYP error callback
- (+) HAL_CRYP_GetState return the CRYP state
+ (+) HAL_CRYP_GetState return the CRYP state
(+) HAL_CRYP_GetError return the CRYP error code
@endverbatim
* @{
@@ -1924,28 +2030,32 @@
*/
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
{
-
+
#if defined (CRYP)
-
- if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U) || (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U))
+
+ uint32_t itstatus = hcryp->Instance->MISR;
+
+ if ((itstatus & (CRYP_IT_INI | CRYP_IT_OUTI)) != 0U)
{
- if ((hcryp->Init.Algorithm == CRYP_DES_ECB)|| (hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ if ((hcryp->Init.Algorithm == CRYP_DES_ECB) || (hcryp->Init.Algorithm == CRYP_DES_CBC)
+ || (hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
{
CRYP_TDES_IT(hcryp); /* DES or TDES*/
}
- else if((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC) || (hcryp->Init.Algorithm == CRYP_AES_CTR))
+ else if ((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC)
+ || (hcryp->Init.Algorithm == CRYP_AES_CTR))
{
CRYP_AES_IT(hcryp); /*AES*/
}
- else if((hcryp->Init.Algorithm == CRYP_AES_GCM) ||(hcryp->Init.Algorithm == CRYP_CR_ALGOMODE_AES_CCM) )
+ else if ((hcryp->Init.Algorithm == CRYP_AES_GCM) || (hcryp->Init.Algorithm == CRYP_CR_ALGOMODE_AES_CCM))
{
/* if header phase */
- if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER )
+ if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER)
{
CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
- }
- else /* if payload phase */
+ }
+ else /* if payload phase */
{
CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
}
@@ -1955,60 +2065,63 @@
{
/* Nothing to do */
}
- }
-
-#else /*AES*/
- if((__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_CCF) != 0x0U) && (__HAL_CRYP_GET_IT_SOURCE(hcryp,CRYP_IT_CCFIE) != 0x0U))
+ }
+
+#else /*AES*/
+ if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_CCF) != RESET)
{
-
- /* Clear computation complete flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CCF_CLEAR);
-
- if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET)
{
-
- /* if header phase */
- if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER )
+
+ /* Clear computation complete flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
{
- CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
- }
- else /* if payload phase */
+
+ /* if header phase */
+ if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER)
+ {
+ CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
+ }
+ else /* if payload phase */
+ {
+ CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
+ }
+ }
+ else if (hcryp->Init.Algorithm == CRYP_AES_CCM)
{
- CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
+ /* if header phase */
+ if (hcryp->Init.HeaderSize >= hcryp->CrypHeaderCount)
+ {
+ CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
+ }
+ else /* if payload phase */
+ {
+ CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
+ }
+ }
+ else /* AES Algorithm ECB,CBC or CTR*/
+ {
+ CRYP_AES_IT(hcryp);
}
}
- else if(hcryp->Init.Algorithm == CRYP_AES_CCM)
- {
- /* if header phase */
- if (hcryp->Init.HeaderSize >= hcryp->CrypHeaderCount )
- {
- CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
- }
- else /* if payload phase */
- {
- CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
- }
- }
- else /* AES Algorithm ECB,CBC or CTR*/
- {
- CRYP_AES_IT(hcryp);
- }
- }
+ }
/* Check if error occurred */
- if (__HAL_CRYP_GET_IT_SOURCE(hcryp,CRYP_IT_ERRIE) != RESET)
+ if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_ERRIE) != RESET)
{
/* If write Error occurred */
- if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_WRERR) != RESET)
+ if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_WRERR) != RESET)
{
hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE;
}
/* If read Error occurred */
- if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_RDERR) != RESET)
+ if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_RDERR) != RESET)
{
hcryp->ErrorCode |= HAL_CRYP_ERROR_READ;
}
}
-#endif /* End AES or CRYP */
+#endif /* End AES or CRYP */
}
/**
@@ -2043,10 +2156,10 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CRYP_InCpltCallback could be implemented in the user file
- */
+ */
}
/**
@@ -2059,7 +2172,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CRYP_OutCpltCallback could be implemented in the user file
*/
@@ -2071,14 +2184,14 @@
* the configuration information for CRYP module.
* @retval None
*/
- __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
+__weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CRYP_ErrorCallback could be implemented in the user file
- */
+ */
}
/**
* @}
@@ -2089,88 +2202,94 @@
* @{
*/
- #if defined (CRYP)
+#if defined (CRYP)
/**
* @brief Encryption in ECB/CBC Algorithm with DES/TDES standard.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Timeout: specify Timeout value
+ * the configuration information for CRYP module
+ * @param Timeout: specify Timeout value
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
- uint32_t temp; /* Temporary CrypOutBuff */
- uint16_t incount; /* Temporary CrypInCount Value */
+ uint32_t temp[2]; /* Temporary CrypOutBuff */
+ uint16_t incount; /* Temporary CrypInCount Value */
uint16_t outcount; /* Temporary CrypOutCount Value */
-
+ uint32_t i;
+
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
/*Temporary CrypOutCount Value*/
outcount = hcryp->CrypOutCount;
-
- /*Start processing*/
- while((hcryp->CrypInCount < (hcryp->Size/4U)) && (outcount < (hcryp->Size/4U)))
- {
- /* Temporary CrypInCount Value */
- incount = hcryp->CrypInCount;
+
+ /*Start processing*/
+ while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
+ {
+ /* Temporary CrypInCount Value */
+ incount = hcryp->CrypInCount;
/* Write plain data and get cipher data */
- if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != 0x0U) && (incount < (hcryp->Size/4U)))
+ if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
{
/* Write the input block in the IN FIFO */
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- }
-
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ }
+
/* Wait for OFNE flag to be raised */
- if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
- {
+ if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
+ {
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state & errorCode*/
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
-
+
/*Temporary CrypOutCount Value*/
outcount = hcryp->CrypOutCount;
-
- if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) && (outcount < (hcryp->Size/4U)))
+
+ if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
{
- /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
+ /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
+ for (i = 0U; i < 2U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUT;
+ }
+ i = 0U;
+ while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 2U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
}
/*Temporary CrypOutCount Value*/
outcount = hcryp->CrypOutCount;
}
/* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
+ __HAL_CRYP_DISABLE(hcryp);
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Return function status */
- return HAL_OK;
+ return HAL_OK;
}
-/**
+/**
* @brief CRYP block input/output data handling under interruption with DES/TDES standard.
* @note The function is called under interruption only, once
* interruptions have been enabled by CRYP_Decrypt_IT() and CRYP_Encrypt_IT().
@@ -2180,73 +2299,84 @@
*/
static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp)
{
- uint32_t temp; /* Temporary CrypOutBuff */
-
- if(hcryp->State == HAL_CRYP_STATE_BUSY)
- {
- if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U) && (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_INRIS) != 0x0U))
-
- {
- /* Write input block in the IN FIFO */
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
-
- if(hcryp->CrypInCount == ((uint16_t)(hcryp->Size)/4U))
- {
- /* Disable interruption */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the input data transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
- /*Call registered Input complete callback*/
- hcryp->InCpltCallback(hcryp);
+ uint32_t temp[2]; /* Temporary CrypOutBuff */
+ uint32_t i;
+
+ if (hcryp->State == HAL_CRYP_STATE_BUSY)
+ {
+ if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U)
+ {
+ if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_INRIS) != 0x0U)
+ {
+ /* Write input block in the IN FIFO */
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+
+ if (hcryp->CrypInCount == ((uint16_t)(hcryp->Size) / 4U))
+ {
+ /* Disable interruption */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+ /* Call the input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
#else
- /*Call legacy weak Input complete callback*/
- HAL_CRYP_InCpltCallback(hcryp);
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
}
}
- if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U)&& (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_OUTRIS) != 0x0U))
+ if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U)
{
- /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
- if(hcryp->CrypOutCount == ((uint16_t)(hcryp->Size)/4U))
+ if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_OUTRIS) != 0x0U)
{
- /* Disable interruption */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
-
- /* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call output transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
- /*Call registered Output complete callback*/
- hcryp->OutCpltCallback(hcryp);
+ /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
+ for (i = 0U; i < 2U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUT;
+ }
+ i = 0U;
+ while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 2U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
+ if (hcryp->CrypOutCount == ((uint16_t)(hcryp->Size) / 4U))
+ {
+ /* Disable interruption */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Call output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Output complete callback*/
+ hcryp->OutCpltCallback(hcryp);
#else
- /*Call legacy weak Output complete callback*/
- HAL_CRYP_OutCpltCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ /*Call legacy weak Output complete callback*/
+ HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
}
- }
+ }
}
else
{
/* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ __HAL_UNLOCK(hcryp);
/* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
@@ -2260,58 +2390,80 @@
/**
* @brief Encryption in ECB/CBC & CTR Algorithm with AES Standard
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure
- * @param Timeout: specify Timeout value
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure
+ * @param Timeout: specify Timeout value
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
-{
+{
uint16_t outcount; /* Temporary CrypOutCount Value */
-
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
- /* Set the Initialization Vector*/
-#if defined (AES)
- hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
-#else /* CRYP */
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
-#endif /* End AES or CRYP */
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ }
}
-
+
+ if (DoKeyIVConfig == 1U)
+ {
+
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector*/
+#if defined (AES)
+ hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+#else /* CRYP */
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+#endif /* End AES or CRYP */
+ }
+ } /* if (DoKeyIVConfig == 1U) */
+
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
-
+
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
-
+
/*Temporary CrypOutCount Value*/
outcount = hcryp->CrypOutCount;
-
- while((hcryp->CrypInCount < (hcryp->Size/4U)) && (outcount < (hcryp->Size/4U)))
- {
+
+ while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
+ {
/* Write plain Ddta and get cipher data */
- CRYP_AES_ProcessData(hcryp,Timeout);
+ CRYP_AES_ProcessData(hcryp, Timeout);
/*Temporary CrypOutCount Value*/
- outcount = hcryp->CrypOutCount;
- }
-
+ outcount = hcryp->CrypOutCount;
+ }
+
/* Disable CRYP */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Return function status */
- return HAL_OK;
+ return HAL_OK;
}
/**
@@ -2321,202 +2473,245 @@
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
-{
-
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+{
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
- /* Set the Initialization Vector*/
-#if defined (AES)
- hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
-
-#else /* CRYP */
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
-#endif /* End AES or CRYP */
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ }
}
+
+ if (DoKeyIVConfig == 1U)
+ {
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector*/
+#if defined (AES)
+ hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+
+#else /* CRYP */
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+#endif /* End AES or CRYP */
+ }
+ } /* if (DoKeyIVConfig == 1U) */
+
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
-
- if(hcryp->Size != 0U)
- {
-#if defined (AES)
-
+
+ if (hcryp->Size != 0U)
+ {
+#if defined (AES)
+
/* Enable computation complete flag and error interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE);
-
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
+
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
-
+
/* Write the input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
-
-#else /* CRYP */
-
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+
+#else /* CRYP */
+
/* Enable interrupts */
__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-
+
/* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
-
-#endif /* End AES or CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+#endif /* End AES or CRYP */
}
else
- {
+ {
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Process unlocked */
- __HAL_UNLOCK(hcryp);
- }
-
+ __HAL_UNLOCK(hcryp);
+ }
+
/* Return function status */
return HAL_OK;
}
/**
* @brief Decryption in ECB/CBC & CTR mode with AES Standard
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure
- * @param Timeout: Specify Timeout value
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure
+ * @param Timeout: Specify Timeout value
* @retval HAL status
*/
-static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout )
-{
+static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
uint16_t outcount; /* Temporary CrypOutCount Value */
-
- /* Key preparation for ECB/CBC */
- if (hcryp->Init.Algorithm != CRYP_AES_CTR)
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
-#if defined (AES)
- if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
- {
- /* Set key preparation for decryption operating mode*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
-
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ }
+ }
+
+ if (DoKeyIVConfig == 1U)
+ {
+ /* Key preparation for ECB/CBC */
+ if (hcryp->Init.Algorithm != CRYP_AES_CTR)
+ {
+#if defined (AES)
+ if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
+ {
+ /* Set key preparation for decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
+
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Wait for CCF flag to be raised */
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state & error code*/
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ /* Return to decryption operating mode(Mode 3)*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+ }
+ else /*Mode 4 : decryption & Key preparation*/
+ {
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set decryption & Key preparation operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
+ }
+#else /* CRYP */
+ /* change ALGOMODE to key preparation for decryption*/
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
+
/* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
-
- /* Wait for CCF flag to be raised */
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
+
+ /* Wait for BUSY flag to be raised */
+ if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
+ {
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
- /* Change state & error code*/
+
+ /* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
- /* Return to decryption operating mode(Mode 3)*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+ /* Turn back to ALGOMODE of the configuration */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
+
+#endif /* End AES or CRYP */
}
- else /*Mode 4 : decryption & Key preparation*/
+ else /*Algorithm CTR */
{
/* Set the Key*/
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Set decryption & Key preparation operating mode*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
- }
+ }
+
+ /* Set IV */
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector*/
+#if defined (AES)
+ hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
#else /* CRYP */
- /* change ALGOMODE to key preparation for decryption*/
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY );
-
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Wait for BUSY flag to be raised */
- if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- /* Turn back to ALGOMODE of the configuration */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm );
-
-#endif /* End AES or CRYP */
- }
- else /*Algorithm CTR */
- {
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- }
-
- /* Set IV */
- if (hcryp->Init.Algorithm != CRYP_AES_ECB)
- {
- /* Set the Initialization Vector*/
-#if defined (AES)
- hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
-#else /* CRYP */
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
#endif /* End AES or CRYP */
- }
+ }
+ } /* if (DoKeyIVConfig == 1U) */
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
-
+
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
-
- /*Temporary CrypOutCount Value*/
- outcount = hcryp->CrypOutCount;
-
- while((hcryp->CrypInCount < (hcryp->Size/4U)) && (outcount < (hcryp->Size/4U)))
- {
+
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
+
+ while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
+ {
/* Write plain data and get cipher data */
- CRYP_AES_ProcessData(hcryp,Timeout);
+ CRYP_AES_ProcessData(hcryp, Timeout);
/*Temporary CrypOutCount Value*/
outcount = hcryp->CrypOutCount;
- }
-
+ }
+
/* Disable CRYP */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Return function status */
- return HAL_OK;
+ return HAL_OK;
}
/**
* @brief Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
@@ -2527,156 +2722,176 @@
static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
{
__IO uint32_t count = 0U;
-
- /* Key preparation for ECB/CBC */
- if (hcryp->Init.Algorithm != CRYP_AES_CTR)
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
-#if defined (AES)
- if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
- {
- /* Set key preparation for decryption operating mode*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
-
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ }
+ }
+
+ if (DoKeyIVConfig == 1U)
+ {
+ /* Key preparation for ECB/CBC */
+ if (hcryp->Init.Algorithm != CRYP_AES_CTR)
+ {
+#if defined (AES)
+ if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
+ {
+ /* Set key preparation for decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
+
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Wait for CCF flag to be raised */
+ count = CRYP_TIMEOUT_KEYPREPARATION;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ /* Return to decryption operating mode(Mode 3)*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+ }
+ else /*Mode 4 : decryption & key preparation*/
+ {
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set decryption & key preparation operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
+ }
+#else /* CRYP */
+
+ /* change ALGOMODE to key preparation for decryption*/
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
+
/* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
-
- /* Wait for CCF flag to be raised */
+
+ /* Wait for BUSY flag to be raised */
count = CRYP_TIMEOUT_KEYPREPARATION;
do
{
count-- ;
- if(count == 0U)
+ if (count == 0U)
{
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- }
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
- /* Return to decryption operating mode(Mode 3)*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+ } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
+
+ /* Turn back to ALGOMODE of the configuration */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
+
+#endif /* End AES or CRYP */
}
- else /*Mode 4 : decryption & key preparation*/
+
+ else /*Algorithm CTR */
{
/* Set the Key*/
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Set decryption & key preparation operating mode*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
- }
-#else /* CRYP */
-
- /* change ALGOMODE to key preparation for decryption*/
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY );
-
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Wait for BUSY flag to be raised */
- count = CRYP_TIMEOUT_KEYPREPARATION;
- do
- {
- count-- ;
- if(count == 0U)
- {
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
}
- while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
-
- /* Turn back to ALGOMODE of the configuration */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm );
-
-#endif /* End AES or CRYP */
- }
-
- else /*Algorithm CTR */
- {
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- }
-
- /* Set IV */
- if (hcryp->Init.Algorithm != CRYP_AES_ECB)
- {
- /* Set the Initialization Vector*/
-#if defined (AES)
- hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
+
+ /* Set IV */
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector*/
+#if defined (AES)
+ hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
#else /* CRYP */
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
#endif /* End AES or CRYP */
- }
+ }
+ } /* if (DoKeyIVConfig == 1U) */
+
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
- if(hcryp->Size != 0U)
- {
-
-#if defined (AES)
-
+ if (hcryp->Size != 0U)
+ {
+
+#if defined (AES)
+
/* Enable computation complete flag and error interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE);
-
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
+
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
-
+
/* Write the input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
-
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+
#else /* CRYP */
-
+
/* Enable interrupts */
__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-
+
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
-
-#endif /* End AES or CRYP */
+
+#endif /* End AES or CRYP */
}
- else
+ else
{
/* Process locked */
__HAL_UNLOCK(hcryp);
-
+
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
- }
-
+ }
+
/* Return function status */
return HAL_OK;
}
@@ -2689,131 +2904,150 @@
static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
{
__IO uint32_t count = 0U;
-
- /* Key preparation for ECB/CBC */
- if (hcryp->Init.Algorithm != CRYP_AES_CTR)
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
-#if defined (AES)
- if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 key preparation*/
- {
- /* Set key preparation for decryption operating mode*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
-
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ }
+ }
+ if (DoKeyIVConfig == 1U)
+ {
+ /* Key preparation for ECB/CBC */
+ if (hcryp->Init.Algorithm != CRYP_AES_CTR)
+ {
+#if defined (AES)
+ if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 key preparation*/
+ {
+ /* Set key preparation for decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
+
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Wait for CCF flag to be raised */
+ count = CRYP_TIMEOUT_KEYPREPARATION;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ /* Return to decryption operating mode(Mode 3)*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+ }
+ else /*Mode 4 : decryption & key preparation*/
+ {
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set decryption & Key preparation operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
+ }
+#else /* CRYP */
+ /* change ALGOMODE to key preparation for decryption*/
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
+
/* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
-
- /* Wait for CCF flag to be raised */
+
+ /* Wait for BUSY flag to be raised */
count = CRYP_TIMEOUT_KEYPREPARATION;
do
{
count-- ;
- if(count == 0U)
+ if (count == 0U)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- }
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
- /* Return to decryption operating mode(Mode 3)*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+ } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
+
+ /* Turn back to ALGOMODE of the configuration */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
+
+#endif /* End AES or CRYP */
}
- else /*Mode 4 : decryption & key preparation*/
+ else /*Algorithm CTR */
{
/* Set the Key*/
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Set decryption & Key preparation operating mode*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
- }
-#else /* CRYP */
- /* change ALGOMODE to key preparation for decryption*/
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY );
-
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Wait for BUSY flag to be raised */
- count = CRYP_TIMEOUT_KEYPREPARATION;
- do
- {
- count-- ;
- if(count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
}
- while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
-
- /* Turn back to ALGOMODE of the configuration */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm );
-
-#endif /* End AES or CRYP */
- }
- else /*Algorithm CTR */
- {
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- }
-
- if (hcryp->Init.Algorithm != CRYP_AES_ECB)
- {
- /* Set the Initialization Vector*/
-#if defined (AES)
- hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
+
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector*/
+#if defined (AES)
+ hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
#else /* CRYP */
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
#endif /* End AES or CRYP */
- }
+ }
+ } /* if (DoKeyIVConfig == 1U) */
+
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
-
- if(hcryp->Size != 0U)
- {
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
+
+ if (hcryp->Size != 0U)
+ {
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
}
- else
+ else
{
/* Process unlocked */
__HAL_UNLOCK(hcryp);
-
+
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
- }
-
+ }
+
/* Return function status */
return HAL_OK;
}
@@ -2824,40 +3058,40 @@
* @param hdma: DMA handle
* @retval None
*/
-static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
+static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
+ CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
/* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
in the DMACR register */
-#if defined (CRYP)
- hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
-
+#if defined (CRYP)
+ hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
+
#else /* AES */
CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
-
+
/* TinyAES2, No output on CCM AES, unlock should be done when input data process complete */
- if((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM)
- {
+ if ((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM)
+ {
/* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CCF_CLEAR);
-
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
/* Change the CRYP state to ready */
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
}
-#endif /* End AES or CRYP */
-
+#endif /* End AES or CRYP */
+
/* Call input data transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
/**
@@ -2867,78 +3101,78 @@
*/
static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
+ CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
/* Disable the DMA transfer for output FIFO request by resetting
the DOEN bit in the DMACR register */
-
-#if defined (CRYP)
+
+#if defined (CRYP)
hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
- if((hcryp->Init.Algorithm & CRYP_AES_GCM) != CRYP_AES_GCM)
- {
+ if ((hcryp->Init.Algorithm & CRYP_AES_GCM) != CRYP_AES_GCM)
+ {
/* Disable CRYP (not allowed in GCM)*/
__HAL_CRYP_DISABLE(hcryp);
}
-#else /* AES */
-
+#else /* AES */
+
CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
-
+
/* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CCF_CLEAR);
-
- if((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
- {
- /* Disable CRYP (not allowed in GCM)*/
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ if ((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
+ {
+ /* Disable CRYP (not allowed in GCM)*/
__HAL_CRYP_DISABLE(hcryp);
- }
-#endif /* End AES or CRYP */
-
+ }
+#endif /* End AES or CRYP */
+
/* Change the CRYP state to ready */
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ __HAL_UNLOCK(hcryp);
/* Call output data transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered Output complete callback*/
hcryp->OutCpltCallback(hcryp);
#else
/*Call legacy weak Output complete callback*/
HAL_CRYP_OutCpltCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
/**
- * @brief DMA CRYP communication error callback.
+ * @brief DMA CRYP communication error callback.
* @param hdma: DMA handle
* @retval None
*/
static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Change the CRYP peripheral state */
- hcryp->State= HAL_CRYP_STATE_READY;
-
+ CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
/* DMA error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
-
-#if defined (AES)
-
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+
+#if defined (AES)
+
/* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CCF_CLEAR);
-
-#endif /* AES */
-
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+#endif /* AES */
+
/* Call error callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
/**
@@ -2954,44 +3188,44 @@
{
/* Set the CRYP DMA transfer complete callback */
hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
-
+
/* Set the DMA input error callback */
hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
-
+
/* Set the CRYP DMA transfer complete callback */
hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
-
+
/* Set the DMA output error callback */
hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
-
-#if defined (CRYP)
-
+
+#if defined (CRYP)
+
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
-
+
/* Enable the input DMA Stream */
- if ( HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DIN, Size)!=HAL_OK)
+ if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DIN, Size) != HAL_OK)
{
/* DMA error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
-
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+
/* Call error callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
/* Enable the output DMA Stream */
- if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size)!=HAL_OK)
+ if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size) != HAL_OK)
{
/* DMA error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
-
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+
/* Call error callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
@@ -3001,189 +3235,188 @@
}
/* Enable In/Out DMA request */
hcryp->Instance->DMACR = CRYP_DMACR_DOEN | CRYP_DMACR_DIEN;
-
+
#else /* AES */
-
- if(((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC) && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM))
- {
- /* Enable CRYP (not allowed in GCM & CCM)*/
+
+ if (((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
+ && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM))
+ {
+ /* Enable CRYP (not allowed in GCM & CCM)*/
__HAL_CRYP_ENABLE(hcryp);
- }
-
+ }
+
/* Enable the DMA input stream */
- if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size)!=HAL_OK)
+ if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size) != HAL_OK)
{
/* DMA error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
-
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+
/* Call error callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
+ }
/* Enable the DMA output stream */
- if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size)!=HAL_OK)
+ if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size) != HAL_OK)
{
/* DMA error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
-
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+
/* Call error callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
- /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
+ }
+ /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
/* Enable In and Out DMA requests */
- if((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM)
- {
+ if ((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM)
+ {
/* Enable only In DMA requests for CCM*/
- SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN ));
+ SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN));
}
else
{
/* Enable In and Out DMA requests */
SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
- }
+ }
#endif /* End AES or CRYP */
}
/**
- * @brief Process Data: Write Input data in polling mode and used in AES functions.
+ * @brief Process Data: Write Input data in polling mode and used in AES functions.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param Timeout: Specify Timeout value
+ * @param Timeout: Specify Timeout value
* @retval None
*/
static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
-
- uint32_t temp; /* Temporary CrypOutBuff */
+
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t i;
#if defined (CRYP)
uint16_t incount; /* Temporary CrypInCount Value */
uint16_t outcount; /* Temporary CrypOutCount Value */
-#endif
-
-#if defined (CRYP)
-
+#endif
+
+#if defined (CRYP)
+
/*Temporary CrypOutCount Value*/
- incount = hcryp->CrypInCount;
-
- if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != 0x0U) && (incount < (hcryp->Size/4U)))
+ incount = hcryp->CrypInCount;
+
+ if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
{
/* Write the input block in the IN FIFO */
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
}
-
+
/* Wait for OFNE flag to be raised */
- if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
- {
+ if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
+ {
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state & error code*/
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
-
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+
/*Temporary CrypOutCount Value*/
outcount = hcryp->CrypOutCount;
-
- if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) && (outcount < (hcryp->Size/4U)))
+
+ if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
{
- /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- }
-
+ /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+ for (i = 0U; i < 4U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUT;
+ }
+ i = 0U;
+ while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
+ }
+
#else /* AES */
-
+
/* Write the input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
-
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+
/* Wait for CCF flag to be raised */
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
-
+
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) =temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) =temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
-
+
+ /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
+ for (i = 0U; i < 4U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUTR;
+ }
+ i = 0U;
+ while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
#endif /* End AES or CRYP */
}
-/**
+/**
* @brief Handle CRYP block input/output data handling under interruption.
* @note The function is called under interruption only, once
* interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT.
@@ -3193,36 +3426,37 @@
*/
static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
{
- uint32_t temp; /* Temporary CrypOutBuff */
-#if defined (CRYP)
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t i;
+#if defined (CRYP)
uint16_t incount; /* Temporary CrypInCount Value */
uint16_t outcount; /* Temporary CrypOutCount Value */
-#endif
-
- if(hcryp->State == HAL_CRYP_STATE_BUSY)
- {
-#if defined (CRYP)
-
+#endif
+
+ if (hcryp->State == HAL_CRYP_STATE_BUSY)
+ {
+#if defined (CRYP)
+
/*Temporary CrypOutCount Value*/
incount = hcryp->CrypInCount;
- if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != 0x0U) && (incount < (hcryp->Size/4U)))
+ if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
{
/* Write the input block in the IN FIFO */
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- if(hcryp->CrypInCount == ((uint16_t)(hcryp->Size)/4U))
- {
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ if (hcryp->CrypInCount == ((uint16_t)(hcryp->Size) / 4U))
+ {
/* Disable interrupts */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-
+
/* Call the input data transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
@@ -3233,79 +3467,77 @@
}
/*Temporary CrypOutCount Value*/
outcount = hcryp->CrypOutCount;
-
- if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) && (outcount < (hcryp->Size/4U)))
+
+ if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
{
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- if(hcryp->CrypOutCount == ((uint16_t)(hcryp->Size)/4U))
+ /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+ for (i = 0U; i < 4U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUT;
+ }
+ i = 0U;
+ while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
+ if (hcryp->CrypOutCount == ((uint16_t)(hcryp->Size) / 4U))
{
/* Disable interrupts */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
-
+
/* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
+ hcryp->State = HAL_CRYP_STATE_READY;
+
/* Disable CRYP */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Process unlocked */
__HAL_UNLOCK(hcryp);
-
- /* Call Output transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
- /*Call registered Output complete callback*/
- hcryp->OutCpltCallback(hcryp);
+
+ /* Call Output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Output complete callback*/
+ hcryp->OutCpltCallback(hcryp);
#else
- /*Call legacy weak Output complete callback*/
- HAL_CRYP_OutCpltCallback(hcryp);
+ /*Call legacy weak Output complete callback*/
+ HAL_CRYP_OutCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
-
+
#else /*AES*/
-
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) =temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) =temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
-
- if(hcryp->CrypOutCount == (hcryp->Size/4U))
+
+ /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
+ for (i = 0U; i < 4U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUTR;
+ }
+ i = 0U;
+ while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
+
+ if (hcryp->CrypOutCount == (hcryp->Size / 4U))
{
/* Disable Computation Complete flag and errors interrupts */
- __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CCFIE|CRYP_IT_ERRIE);
-
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
+
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Disable CRYP */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
-
+
/* Call Output transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered Output complete callback*/
hcryp->OutCpltCallback(hcryp);
#else
@@ -3314,116 +3546,116 @@
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
else
- {
+ {
/* Write the input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
-
- if(hcryp->CrypInCount == (hcryp->Size/4U))
- {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+
+ if (hcryp->CrypInCount == (hcryp->Size / 4U))
+ {
/* Call Input transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
- }
+ }
+ }
#endif /* End AES or CRYP */
-
- }
+
+ }
else
{
/* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
-}
+}
/**
- * @brief Writes Key in Key registers.
+ * @brief Writes Key in Key registers.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param KeySize: Size of Key
* @retval None
*/
static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
-{
+{
#if defined (CRYP)
-
- switch(KeySize)
+
+ switch (KeySize)
{
- case CRYP_KEYSIZE_256B:
- hcryp->Instance->K0LR = *(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->K0RR = *(uint32_t*)(hcryp->Init.pKey+1);
- hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+4);
- hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+5);
- hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+6);
- hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+7);
- break;
- case CRYP_KEYSIZE_192B:
- hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
- hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
- hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
- break;
- case CRYP_KEYSIZE_128B:
- hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+1);
- hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+3);
-
- break;
- default:
- break;
+ case CRYP_KEYSIZE_256B:
+ hcryp->Instance->K0LR = *(uint32_t *)(hcryp->Init.pKey);
+ hcryp->Instance->K0RR = *(uint32_t *)(hcryp->Init.pKey + 1);
+ hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey + 2);
+ hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 3);
+ hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 4);
+ hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 5);
+ hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 6);
+ hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 7);
+ break;
+ case CRYP_KEYSIZE_192B:
+ hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
+ hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
+ hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
+ hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
+ hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
+ hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
+ break;
+ case CRYP_KEYSIZE_128B:
+ hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey);
+ hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 1);
+ hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 2);
+ hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 3);
+
+ break;
+ default:
+ break;
}
#else /*AES*/
- switch(KeySize)
+ switch (KeySize)
{
- case CRYP_KEYSIZE_256B:
- hcryp->Instance->KEYR7 =*(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->KEYR6 =*(uint32_t*)(hcryp->Init.pKey+1);
- hcryp->Instance->KEYR5 =*(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->KEYR4 =*(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->Instance->KEYR3 =*(uint32_t*)(hcryp->Init.pKey+4);
- hcryp->Instance->KEYR2 =*(uint32_t*)(hcryp->Init.pKey+5);
- hcryp->Instance->KEYR1 =*(uint32_t*)(hcryp->Init.pKey+6);
- hcryp->Instance->KEYR0 =*(uint32_t*)(hcryp->Init.pKey+7);
- break;
- case CRYP_KEYSIZE_128B:
- hcryp->Instance->KEYR3 =*(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->KEYR2 =*(uint32_t*)(hcryp->Init.pKey+1);
- hcryp->Instance->KEYR1 =*(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->KEYR0 =*(uint32_t*)(hcryp->Init.pKey+3);
-
- break;
- default:
- break;
+ case CRYP_KEYSIZE_256B:
+ hcryp->Instance->KEYR7 = *(uint32_t *)(hcryp->Init.pKey);
+ hcryp->Instance->KEYR6 = *(uint32_t *)(hcryp->Init.pKey + 1);
+ hcryp->Instance->KEYR5 = *(uint32_t *)(hcryp->Init.pKey + 2);
+ hcryp->Instance->KEYR4 = *(uint32_t *)(hcryp->Init.pKey + 3);
+ hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey + 4);
+ hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 5);
+ hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 6);
+ hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 7);
+ break;
+ case CRYP_KEYSIZE_128B:
+ hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey);
+ hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 1);
+ hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 2);
+ hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 3);
+
+ break;
+ default:
+ break;
}
#endif /* End AES or CRYP */
}
/**
- * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG
+ * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Timeout: Timeout duration
@@ -3432,164 +3664,191 @@
static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint32_t tickstart;
- uint32_t wordsize = (uint32_t)(hcryp->Size)/4U ;
+ uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U ;
uint16_t outcount; /* Temporary CrypOutCount Value */
-
- /* Reset CrypHeaderCount */
- hcryp->CrypHeaderCount = 0U;
-
- /****************************** Init phase **********************************/
-
- CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
-#if defined(CRYP)
-
- /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /*Wait for the CRYPEN bit to be cleared*/
- while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (hcryp->KeyIVConfig == 1U)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
}
}
-
-#else /* AES */
- /* Workaround 1 : only AES.
- Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re
- enabling the IP, datatype different from 32 bits can be configured.*/
- /* Select DATATYPE 32 */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
-
- /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
- hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* just wait for hash computation */
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked & return error */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
-#endif /* End AES or CRYP */
-
- /************************ Header phase *************************************/
-
- if(CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
+ else
{
- return HAL_ERROR;
+ hcryp->SizesSum = hcryp->Size;
}
-
- /*************************Payload phase ************************************/
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
-#if defined(CRYP)
-
- /* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Select payload phase once the header phase is performed */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
-#else /* AES */
-
- /* Select payload phase once the header phase is performed */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
-#endif /* End AES or CRYP */
-
- if ((hcryp->Size % 16U) != 0U)
+
+ if (DoKeyIVConfig == 1U)
{
- /* recalculate wordsize */
- wordsize = ((wordsize/4U)*4U) ;
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
+
+ /****************************** Init phase **********************************/
+
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+#if defined(CRYP)
+
+ /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /*Wait for the CRYPEN bit to be cleared*/
+ while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ }
+
+#else /* AES */
+ /* Workaround 1 : only AES.
+ Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re
+ enabling the IP, datatype different from 32 bits can be configured.*/
+ /* Select DATATYPE 32 */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
+
+ /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+ hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* just wait for hash computation */
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked & return error */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+#endif /* End AES or CRYP */
+
+ /************************ Header phase *************************************/
+
+ if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /*************************Payload phase ************************************/
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+#if defined(CRYP)
+
+ /* Disable the CRYP peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+#else /* AES */
+
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+#endif /* End AES or CRYP */
+ } /* if (DoKeyIVConfig == 1U) */
+
+ if ((hcryp->Size % 16U) != 0U)
+ {
+ /* recalculate wordsize */
+ wordsize = ((wordsize / 4U) * 4U) ;
}
-
+
/* Get tick */
tickstart = HAL_GetTick();
/*Temporary CrypOutCount Value*/
outcount = hcryp->CrypOutCount;
-
+
/* Write input data and get output Data */
- while((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
- {
+ while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
+ {
/* Write plain data and get cipher data */
- CRYP_AES_ProcessData(hcryp,Timeout);
-
+ CRYP_AES_ProcessData(hcryp, Timeout);
+
/*Temporary CrypOutCount Value*/
- outcount = hcryp->CrypOutCount;
-
+ outcount = hcryp->CrypOutCount;
+
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state & error code */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
}
-
- if ((hcryp->Size % 16U) != 0U)
+
+ if ((hcryp->Size % 16U) != 0U)
{
/* Workaround 2 : CRYP1 & AES generates correct TAG for GCM mode only when input block size is multiple of
128 bits. If lthe size of the last block of payload is inferior to 128 bits, when GCM encryption
- is selected, then the TAG message will be wrong.*/
- CRYP_Workaround(hcryp,Timeout);
+ is selected, then the TAG message will be wrong.*/
+ CRYP_Workaround(hcryp, Timeout);
}
-
+
/* Return function status */
return HAL_OK;
}
@@ -3603,246 +3862,272 @@
static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
{
__IO uint32_t count = 0U;
-#if defined(AES)
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+#if defined(AES)
uint32_t loopcounter;
- uint32_t lastwordsize;
+ uint32_t lastwordsize;
uint32_t npblb;
-#endif /* AES */
-
- /* Reset CrypHeaderCount */
- hcryp->CrypHeaderCount =0U;
-
- /******************************* Init phase *********************************/
-
- CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
-#if defined(CRYP)
- /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /*Wait for the CRYPEN bit to be cleared*/
- count = CRYP_TIMEOUT_GCMCCMINITPHASE;
- do
+#endif /* AES */
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
- count-- ;
- if(count == 0U)
+ if (hcryp->KeyIVConfig == 1U)
{
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
}
- }
- while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
-
-#else /* AES */
-
- /* Workaround 1 : only AES
- Datatype configuration must be 32 bits during INIT phase. Only, after INIT, and before re
- enabling the IP, datatype different from 32 bits can be configured.*/
- /* Select DATATYPE 32 */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
-
- /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
- hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* just wait for hash computation */
- count = CRYP_TIMEOUT_GCMCCMINITPHASE;
- do
- {
- count-- ;
- if(count == 0U)
+ else
{
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
}
}
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
-#endif /* End AES or CRYP */
-
- /***************************** Header phase *********************************/
-
-#if defined(CRYP)
-
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
- /* Enable interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
-
-#else /* AES */
-
- /* Workaround 1: only AES , before re-enabling the IP, datatype can be configured*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
-
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
- /* Enable computation complete flag and error interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- if(hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/
- {
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Select payload phase once the header phase is performed */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
-
- /* Write the payload Input block in the IN FIFO */
- if(hcryp->Size == 0U)
- {
- /* Disable interrupts */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE| CRYP_IT_ERRIE);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- }
- else if (hcryp->Size >= 16U)
- {
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- if(hcryp->CrypInCount == ( hcryp->Size/4U))
- {
- /* Call Input transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
- /*Call registered Input complete callback*/
- hcryp->InCpltCallback(hcryp);
-#else
- /*Call legacy weak Input complete callback*/
- HAL_CRYP_InCpltCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
- }
- else /* Size < 16Bytes : first block is the last block*/
- {
- /* Workaround not implemented*/
- /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
- Workaround is implemented in polling mode, so if last block of
- payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
-
- /* Compute the number of padding bytes in last block of payload */
- npblb = 16U- (uint32_t)(hcryp->Size);
-
- /* Number of valid words (lastwordsize) in last block */
- if ((npblb % 4U) ==0U)
- {
- lastwordsize = (16U-npblb)/4U;
- }
- else
- {
- lastwordsize = ((16U-npblb)/4U) +1U;
- }
-
- /* last block optionally pad the data with zeros*/
- for(loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
- {
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- }
- while(loopcounter < 4U )
- {
- /* pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0x0U;
- loopcounter++;
- }
- }
- }
- else if ((hcryp->Init.HeaderSize) < 4U)
- {
- for(loopcounter = 0U; loopcounter < hcryp->Init.HeaderSize ; loopcounter++)
- {
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- }
- while(loopcounter < 4U )
- {
- /* pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0x0U;
- loopcounter++;
- }
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Select payload phase once the header phase is performed */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Call Input transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
- /*Call registered Input complete callback*/
- hcryp->InCpltCallback(hcryp);
-#else
- /*Call legacy weak Input complete callback*/
- HAL_CRYP_InCpltCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
- else if ((hcryp->Init.HeaderSize) >= 4U)
- {
- /* Write the input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
- hcryp->CrypHeaderCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
- hcryp->CrypHeaderCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
- hcryp->CrypHeaderCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
- hcryp->CrypHeaderCount++;
- }
else
{
- /* Nothing to do */
- }
-
-#endif /* End AES or CRYP */
-
+ hcryp->SizesSum = hcryp->Size;
+ }
+
+ /* Configure Key, IV and process message (header and payload) */
+ if (DoKeyIVConfig == 1U)
+ {
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
+
+ /******************************* Init phase *********************************/
+
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+#if defined(CRYP)
+ /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /*Wait for the CRYPEN bit to be cleared*/
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
+
+#else /* AES */
+
+ /* Workaround 1 : only AES
+ Datatype configuration must be 32 bits during INIT phase. Only, after INIT, and before re
+ enabling the IP, datatype different from 32 bits can be configured.*/
+ /* Select DATATYPE 32 */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
+
+ /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+ hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* just wait for hash computation */
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+#endif /* End AES or CRYP */
+
+ /***************************** Header phase *********************************/
+
+#if defined(CRYP)
+
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ /* Enable interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+#else /* AES */
+
+ /* Workaround 1: only AES , before re-enabling the IP, datatype can be configured*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
+
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ /* Enable computation complete flag and error interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ if (hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/
+ {
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Select payload phase once the header phase is performed */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
+
+ /* Write the payload Input block in the IN FIFO */
+ if (hcryp->Size == 0U)
+ {
+ /* Disable interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ }
+ else if (hcryp->Size >= 16U)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ if (hcryp->CrypInCount == (hcryp->Size / 4U))
+ {
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
+ else /* Size < 16Bytes : first block is the last block*/
+ {
+ /* Workaround not implemented*/
+ /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
+ Workaround is implemented in polling mode, so if last block of
+ payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
+
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = 16U - (uint32_t)(hcryp->Size);
+
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) == 0U)
+ {
+ lastwordsize = (16U - npblb) / 4U;
+ }
+ else
+ {
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
+ }
+
+ /* last block optionally pad the data with zeros*/
+ for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ }
+ while (loopcounter < 4U)
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+ }
+ else if ((hcryp->Init.HeaderSize) < 4U)
+ {
+ for (loopcounter = 0U; loopcounter < hcryp->Init.HeaderSize ; loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ while (loopcounter < 4U)
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ else if ((hcryp->Init.HeaderSize) >= 4U)
+ {
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+#endif /* End AES or CRYP */
+ } /* end of if (DoKeyIVConfig == 1U) */
+
/* Return function status */
return HAL_OK;
}
@@ -3858,147 +4143,174 @@
{
__IO uint32_t count = 0U;
uint32_t wordsize;
-
- /* Reset CrypHeaderCount */
- hcryp->CrypHeaderCount = 0U;
-
- /*************************** Init phase ************************************/
-
- CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
-#if defined(CRYP)
- /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /*Wait for the CRYPEN bit to be cleared*/
- count = CRYP_TIMEOUT_GCMCCMINITPHASE;
- do
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
- count-- ;
- if(count == 0U)
+ if (hcryp->KeyIVConfig == 1U)
{
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
}
}
- while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
-
-#else /* AES */
-
- /*Workaround 1 : only AES
- Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re
- enabling the IP, datatype different from 32 bits can be configured.*/
- /* Select DATATYPE 32 */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
-
- /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
- hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* just wait for hash computation */
- count = CRYP_TIMEOUT_GCMCCMINITPHASE;
- do
+ else
{
- count-- ;
- if(count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
+ hcryp->SizesSum = hcryp->Size;
}
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
-#endif /* End AES or CRYP */
-
- /************************ Header phase *************************************/
-
- if(CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
+
+ if (DoKeyIVConfig == 1U)
{
- return HAL_ERROR;
- }
-
- /************************ Payload phase ************************************/
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
+
+ /*************************** Init phase ************************************/
+
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
#if defined(CRYP)
-
- /* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE(hcryp);
-
-#endif /* CRYP */
-
- /* Select payload phase once the header phase is performed */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- if(hcryp->Size != 0U)
- {
+ /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /*Wait for the CRYPEN bit to be cleared*/
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
+
+#else /* AES */
+
+ /*Workaround 1 : only AES
+ Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re
+ enabling the IP, datatype different from 32 bits can be configured.*/
+ /* Select DATATYPE 32 */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
+
+ /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+ hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* just wait for hash computation */
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+#endif /* End AES or CRYP */
+
+ /************************ Header phase *************************************/
+
+ if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /************************ Payload phase ************************************/
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+#if defined(CRYP)
+
+ /* Disable the CRYP peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
+
+#endif /* CRYP */
+
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ } /* if (DoKeyIVConfig == 1U) */
+
+ if (hcryp->Size != 0U)
+ {
/* CRYP1 IP V < 2.2.1 Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
- Workaround is implemented in polling mode, so if last block of
+ Workaround is implemented in polling mode, so if last block of
payload <128bit don't use DMA mode otherwise TAG is incorrectly generated . */
- /* Set the input and output addresses and start DMA transfer */
- if ((hcryp->Size % 16U) == 0U)
- {
- CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
+ /* Set the input and output addresses and start DMA transfer */
+ if ((hcryp->Size % 16U) == 0U)
+ {
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
}
else /*to compute last word<128bits, otherwise it will not be encrypted/decrypted */
{
- wordsize = (uint32_t)(hcryp->Size)+(16U-((uint32_t)(hcryp->Size)%16U)) ;
-
- /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */
- CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), ((uint16_t)wordsize/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
- }
+ wordsize = (uint32_t)(hcryp->Size) + (16U - ((uint32_t)(hcryp->Size) % 16U)) ;
+
+ /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)wordsize / 4U),
+ (uint32_t)(hcryp->pCrypOutBuffPtr));
+ }
}
- else
+ else
{
/* Process unLocked */
__HAL_UNLOCK(hcryp);
-
+
/* Change the CRYP state and phase */
hcryp->State = HAL_CRYP_STATE_READY;
- }
-
+ }
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief AES CCM encryption/decryption processing in polling mode
+ * @brief AES CCM encryption/decryption processing in polling mode
* for TinyAES IP, no encrypt/decrypt performed, only authentication preparation.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
@@ -4008,395 +4320,425 @@
static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint32_t tickstart;
- uint32_t wordsize= (uint32_t)(hcryp->Size)/4U;
- uint16_t outcount; /* Temporary CrypOutCount Value */
-#if defined(AES)
+ uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U;
+ uint16_t outcount; /* Temporary CrypOutCount Value */
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+#if defined(AES)
uint32_t loopcounter;
uint32_t npblb;
- uint32_t lastwordsize;
+ uint32_t lastwordsize;
#endif /* AES */
-
- /* Reset CrypHeaderCount */
- hcryp->CrypHeaderCount = 0U;
-
-#if defined(CRYP)
-
- /********************** Init phase ******************************************/
-
- CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Set the initialization vector (IV) with CTR1 information */
- hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
- hcryp->Instance->IV0RR = hcryp->Init.B0[1];
- hcryp->Instance->IV1LR = hcryp->Init.B0[2];
- hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1)| CRYP_CCM_CTR1_2;
-
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /*Write B0 packet into CRYP_DIN Register*/
- if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
- hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0));
- hcryp->Instance->DIN = __REV( *(uint32_t*)(hcryp->Init.B0+1));
- hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+2));
- hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+3));
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
- {
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0), 16);
- hcryp->Instance->DIN = __ROR( *(uint32_t*)(hcryp->Init.B0+1), 16);
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+2), 16);
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+3), 16);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
- {
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0));
- hcryp->Instance->DIN = __RBIT( *(uint32_t*)(hcryp->Init.B0+1));
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+2));
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+3));
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+ }
}
else
{
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0);
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+1);
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+2);
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+3);
+ hcryp->SizesSum = hcryp->Size;
}
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /*Wait for the CRYPEN bit to be cleared*/
- while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+
+ if (DoKeyIVConfig == 1U)
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
+
+#if defined(CRYP)
+
+ /********************** Init phase ******************************************/
+
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set the initialization vector (IV) with CTR1 information */
+ hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
+ hcryp->Instance->IV0RR = hcryp->Init.B0[1];
+ hcryp->Instance->IV1LR = hcryp->Init.B0[2];
+ hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
+
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /*Write B0 packet into CRYP_DIN Register*/
+ if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
}
- }
-#else /* AES */
- /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
- /* configured encryption mode */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Set the initialization vector with zero values*/
- hcryp->Instance->IVR3 = 0U;
- hcryp->Instance->IVR2 = 0U;
- hcryp->Instance->IVR1 = 0U;
- hcryp->Instance->IVR0 = 0U;
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /*Write the B0 packet into CRYP_DIN*/
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0);
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+1);
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+2);
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+3);
-
- /* wait until the end of computation */
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked & return error */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* From that point the whole message must be processed, first the Header then the payload.
- First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/
-
- if (hcryp->Init.HeaderSize != 0U)
- {
- if ((hcryp->Init.HeaderSize %4U )== 0U)
- {
- /* HeaderSize %4, no padding */
- for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4U)
- {
- /* Write the Input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
-
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- }
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
+ {
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
+ }
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
+ {
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
}
else
- {
- /*Write Header block in the IN FIFO without last block */
- for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+=4U)
+ {
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
+ }
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /*Wait for the CRYPEN bit to be cleared*/
+ while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
{
- /* Write the input block in the data input register */
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
-
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
}
- /* Last block optionally pad the data with zeros*/
- for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
- {
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- }
- while(loopcounter <4U )
- {
- /* Pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0x0U;
- loopcounter++;
- }
-
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
}
- }
+#else /* AES */
+ /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ /* configured encryption mode */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set the initialization vector with zero values*/
+ hcryp->Instance->IVR3 = 0U;
+ hcryp->Instance->IVR2 = 0U;
+ hcryp->Instance->IVR1 = 0U;
+ hcryp->Instance->IVR0 = 0U;
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /*Write the B0 packet into CRYP_DIN*/
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3);
+
+ /* wait until the end of computation */
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked & return error */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* From that point the whole message must be processed, first the Header then the payload.
+ First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/
+
+ if (hcryp->Init.HeaderSize != 0U)
+ {
+ if ((hcryp->Init.HeaderSize % 4U) == 0U)
+ {
+ /* HeaderSize %4, no padding */
+ for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
+ {
+ /* Write the Input block in the Data Input register */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+ }
+ else
+ {
+ /*Write Header block in the IN FIFO without last block */
+ for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
+ {
+ /* Write the input block in the data input register */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+ /* Last block optionally pad the data with zeros*/
+ for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ while (loopcounter < 4U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+ }
+ } /* if (DoKeyIVConfig == 1U) */
/* Then the payload: cleartext payload (not the ciphertext payload).
Write input Data, no output Data to get */
if (hcryp->Size != 0U)
{
- if ((hcryp->Size % 16U) != 0U)
+ if ((hcryp->Size % 16U) != 0U)
{
- /* recalculate wordsize */
- wordsize = ((wordsize/4U)*4U) ;
+ /* recalculate wordsize */
+ wordsize = ((wordsize / 4U) * 4U) ;
}
-
+
/* Get tick */
tickstart = HAL_GetTick();
/*Temporary CrypOutCount Value*/
outcount = hcryp->CrypOutCount;
-
- while((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
- {
+
+ while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
+ {
/* Write plain data and get cipher data */
- CRYP_AES_ProcessData(hcryp,Timeout);
-
- /*Temporary CrypOutCount Value*/
- outcount = hcryp->CrypOutCount;
-
+ CRYP_AES_ProcessData(hcryp, Timeout);
+
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
+
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
}
-
- if ((hcryp->Size % 16U) != 0U)
- {
+
+ if ((hcryp->Size % 16U) != 0U)
+ {
/* Compute the number of padding bytes in last block of payload */
- npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U)- (uint32_t)(hcryp->Size);
-
+ npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
+
/* Number of valid words (lastwordsize) in last block */
- if ((npblb%4U) ==0U)
- {
- lastwordsize = (16U-npblb)/4U;
- }
- else
+ if ((npblb % 4U) == 0U)
{
- lastwordsize = ((16U-npblb)/4U) +1U;
- }
- /* Last block optionally pad the data with zeros*/
- for(loopcounter=0U; loopcounter < lastwordsize; loopcounter ++)
+ lastwordsize = (16U - npblb) / 4U;
+ }
+ else
+ {
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
+ }
+ /* Last block optionally pad the data with zeros*/
+ for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++)
{
/* Write the last input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- }
- while(loopcounter < 4U)
+ }
+ while (loopcounter < 4U)
{
/* Pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0U;
- loopcounter++;
- }
+ loopcounter++;
+ }
/* Wait for CCF flag to be raised */
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
+
}
- }
+ }
#endif /* End AES or CRYP */
-
-#if defined(CRYP)
-
- /************************* Header phase *************************************/
- /* Header block(B1) : associated data length expressed in bytes concatenated
- with Associated Data (A)*/
-
- if(CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
+
+#if defined(CRYP)
+
+ /************************* Header phase *************************************/
+ /* Header block(B1) : associated data length expressed in bytes concatenated
+ with Associated Data (A)*/
+
+ if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /********************** Payload phase ***************************************/
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Disable the CRYP peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ } /* if (DoKeyIVConfig == 1U) */
+
+ if ((hcryp->Size % 16U) != 0U)
{
- return HAL_ERROR;
- }
-
- /********************** Payload phase ***************************************/
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Select payload phase once the header phase is performed */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- if ((hcryp->Size % 16U) != 0U)
- {
- /* recalculate wordsize */
- wordsize = ((wordsize/4U)*4U) ;
+ /* recalculate wordsize */
+ wordsize = ((wordsize / 4U) * 4U) ;
}
/* Get tick */
tickstart = HAL_GetTick();
/*Temporary CrypOutCount Value*/
outcount = hcryp->CrypOutCount;
-
+
/* Write input data and get output data */
- while((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
- {
+ while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
+ {
/* Write plain data and get cipher data */
- CRYP_AES_ProcessData(hcryp,Timeout);
-
+ CRYP_AES_ProcessData(hcryp, Timeout);
+
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
}
-
- if ((hcryp->Size % 16U) != 0U)
- {
+
+ if ((hcryp->Size % 16U) != 0U)
+ {
/* CRYP Workaround : CRYP1 generates correct TAG during CCM decryption only when ciphertext blocks size is multiple of
128 bits. If lthe size of the last block of payload is inferior to 128 bits, when CCM decryption
- is selected, then the TAG message will be wrong.*/
- CRYP_Workaround(hcryp,Timeout);
+ is selected, then the TAG message will be wrong.*/
+ CRYP_Workaround(hcryp, Timeout);
}
#endif /* CRYP */
-
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief AES CCM encryption/decryption process in interrupt mode
+ * @brief AES CCM encryption/decryption process in interrupt mode
* for TinyAES IP, no encrypt/decrypt performed, only authentication preparation.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
@@ -4404,310 +4746,565 @@
*/
static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
{
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
#if defined(CRYP)
__IO uint32_t count = 0U;
#endif /* CRYP */
-
- /* Reset CrypHeaderCount */
- hcryp->CrypHeaderCount = 0U;
-
-#if defined(CRYP)
-
- /************ Init phase ************/
-
- CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Set the initialization vector (IV) with CTR1 information */
- hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
- hcryp->Instance->IV0RR = hcryp->Init.B0[1];
- hcryp->Instance->IV1LR = hcryp->Init.B0[2];
- hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1)| CRYP_CCM_CTR1_2;
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /*Write the B0 packet into CRYP_DIN Register*/
- if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
- hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0));
- hcryp->Instance->DIN = __REV( *(uint32_t*)(hcryp->Init.B0+1));
- hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+2));
- hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+3));
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
- {
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0), 16);
- hcryp->Instance->DIN = __ROR( *(uint32_t*)(hcryp->Init.B0+1), 16);
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+2), 16);
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+3), 16);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
- {
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0));
- hcryp->Instance->DIN = __RBIT( *(uint32_t*)(hcryp->Init.B0+1));
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+2));
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+3));
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+ }
}
else
{
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0);
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+1);
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+2);
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+3);
+ hcryp->SizesSum = hcryp->Size;
}
- /*Wait for the CRYPEN bit to be cleared*/
- count = CRYP_TIMEOUT_GCMCCMINITPHASE;
- do
+
+ /* Configure Key, IV and process message (header and payload) */
+ if (DoKeyIVConfig == 1U)
{
- count-- ;
- if(count == 0U)
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
+
+#if defined(CRYP)
+
+ /************ Init phase ************/
+
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set the initialization vector (IV) with CTR1 information */
+ hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
+ hcryp->Instance->IV0RR = hcryp->Init.B0[1];
+ hcryp->Instance->IV1LR = hcryp->Init.B0[2];
+ hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /*Write the B0 packet into CRYP_DIN Register*/
+ if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
{
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
}
- }
- while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
-
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
+ {
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
+ }
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
+ {
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
+ }
+ else
+ {
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
+ }
+ /*Wait for the CRYPEN bit to be cleared*/
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
+
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ } /* end of if (DoKeyIVConfig == 1U) */
+
/* Enable interrupts */
__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
-
+
/* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
-
-#else /* AES */
-
- /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
- /* configured mode and encryption mode */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Set the initialization vector with zero values*/
- hcryp->Instance->IVR3 = 0U;
- hcryp->Instance->IVR2 = 0U;
- hcryp->Instance->IVR1 = 0U;
- hcryp->Instance->IVR0 = 0U;
-
- /* Enable interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE);
- /* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
-
- /*Write the B0 packet into CRYP_DIN*/
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0);
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+1);
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+2);
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+3);
-
+
+#else /* AES */
+
+ /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ /* configured mode and encryption mode */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set the initialization vector with zero values*/
+ hcryp->Instance->IVR3 = 0U;
+ hcryp->Instance->IVR2 = 0U;
+ hcryp->Instance->IVR1 = 0U;
+ hcryp->Instance->IVR0 = 0U;
+
+ /* Enable interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /*Write the B0 packet into CRYP_DIN*/
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3);
+
+ } /* end of if (DoKeyIVConfig == 1U) */
#endif /* End AES or CRYP */
-
+
/* Return function status */
- return HAL_OK;
+ return HAL_OK;
}
/**
- * @brief AES CCM encryption/decryption process in DMA mode
+ * @brief AES CCM encryption/decryption process in DMA mode
* for TinyAES IP, no encrypt/decrypt performed, only authentication preparation.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
-{
+{
uint32_t wordsize;
__IO uint32_t count = 0U;
-
- /* Reset CrypHeaderCount */
- hcryp->CrypHeaderCount = 0U;
-
-#if defined(CRYP)
-
- /************************** Init phase **************************************/
-
- CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Set the initialization vector (IV) with CTR1 information */
- hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
- hcryp->Instance->IV0RR = hcryp->Init.B0[1];
- hcryp->Instance->IV1LR = hcryp->Init.B0[2];
- hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1)| CRYP_CCM_CTR1_2;
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /*Write the B0 packet into CRYP_DIN Register*/
- if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+#if defined(AES)
+ uint32_t loopcounter;
+ uint32_t npblb;
+ uint32_t lastwordsize;
+#endif
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
- hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0));
- hcryp->Instance->DIN = __REV( *(uint32_t*)(hcryp->Init.B0+1));
- hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+2));
- hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+3));
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
- {
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0), 16);
- hcryp->Instance->DIN = __ROR( *(uint32_t*)(hcryp->Init.B0+1), 16);
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+2), 16);
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+3), 16);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
- {
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0));
- hcryp->Instance->DIN = __RBIT( *(uint32_t*)(hcryp->Init.B0+1));
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+2));
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+3));
- }
- else
- {
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0);
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+1);
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+2);
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+3);
- }
-
- /*Wait for the CRYPEN bit to be cleared*/
- count = CRYP_TIMEOUT_GCMCCMINITPHASE;
- do
- {
- count-- ;
- if(count == 0U)
+ if (hcryp->KeyIVConfig == 1U)
{
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
-
-#else /* AES */
-
- /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
- /* configured CCM chaining mode and encryption mode */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Set the initialization vector with zero values*/
- hcryp->Instance->IVR3 = 0U;
- hcryp->Instance->IVR2 = 0U;
- hcryp->Instance->IVR1 = 0U;
- hcryp->Instance->IVR0 = 0U;
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /*Write the B0 packet into CRYP_DIN*/
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0);
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+1);
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+2);
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+3);
-
- /* wait until the end of computation */
- count = CRYP_TIMEOUT_GCMCCMINITPHASE;
- do
- {
- count-- ;
- if(count == 0U)
-{
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
-}
- }
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
-#endif /* AES */
-
- /********************* Header phase *****************************************/
-
- if(CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /******************** Payload phase *****************************************/
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
-#if defined(CRYP)
-
- /* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Select payload phase once the header phase is performed */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
-#endif /* CRYP */
-
- if(hcryp->Size != 0U)
- {
- /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption & CCM Decryption
- Workaround is implemented in polling mode, so if last block of
- payload <128bit don't use HAL_CRYP_AESGCM_DMA otherwise TAG is incorrectly generated for GCM Encryption. */
- /* Set the input and output addresses and start DMA transfer */
- if ((hcryp->Size % 16U) == 0U)
- {
- CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), hcryp->Size/4U, (uint32_t)(hcryp->pCrypOutBuffPtr));
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
}
else
{
- wordsize = (uint32_t)(hcryp->Size)+16U-((uint32_t)(hcryp->Size) %16U) ;
-
- /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4*/
- CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (uint16_t)wordsize/4U, (uint32_t)(hcryp->pCrypOutBuffPtr));
- }
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+ }
+ }
+ else
+ {
+ hcryp->SizesSum = hcryp->Size;
+ }
+
+ if (DoKeyIVConfig == 1U)
+ {
+
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
+
+#if defined(CRYP)
+
+ /************************** Init phase **************************************/
+
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set the initialization vector (IV) with CTR1 information */
+ hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
+ hcryp->Instance->IV0RR = hcryp->Init.B0[1];
+ hcryp->Instance->IV1LR = hcryp->Init.B0[2];
+ hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /*Write the B0 packet into CRYP_DIN Register*/
+ if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ {
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
+ }
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
+ {
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
+ }
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
+ {
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
+ }
+ else
+ {
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
+ }
+
+ /*Wait for the CRYPEN bit to be cleared*/
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
+
+#else /* AES */
+
+ /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ /* configured encryption mode */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set the initialization vector with zero values*/
+ hcryp->Instance->IVR3 = 0U;
+ hcryp->Instance->IVR2 = 0U;
+ hcryp->Instance->IVR1 = 0U;
+ hcryp->Instance->IVR0 = 0U;
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /*Write the B0 packet into CRYP_DIN*/
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3);
+
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* From that point the whole message must be processed, first the Header then the payload.
+ First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/
+
+ if (hcryp->Init.HeaderSize != 0U)
+ {
+ if ((hcryp->Init.HeaderSize % 4U) == 0U)
+ {
+ /* HeaderSize %4, no padding */
+ for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
+ {
+ /* Write the Input block in the Data Input register */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ /* wait until the end of computation */
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+ }
+ else
+ {
+ /*Write Header block in the IN FIFO without last block */
+ for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
+ {
+ /* Write the input block in the data input register */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+ /* Last block optionally pad the data with zeros*/
+ for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ while (loopcounter < 4U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+ }
+ } /* if (DoKeyIVConfig == 1U) */
+ /* Then the payload: cleartext payload (not the ciphertext payload).
+ Write input Data, no output Data to get */
+ if (hcryp->Size != 0U)
+ {
+ if (hcryp->Size >= 16U)
+ {
+ if ((hcryp->Size % 16U) == 0U)
+ {
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
+ }
+ else /*to compute last word<128bits, otherwise it will not be encrypted/decrypted */
+ {
+ wordsize = (uint32_t)(hcryp->Size) + (16U - ((uint32_t)(hcryp->Size) % 16U)) ;
+
+ /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)wordsize / 4U),
+ (uint32_t)(hcryp->pCrypOutBuffPtr));
+ }
+ }
+ if ((hcryp->Size < 16U) != 0U)
+ {
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
+
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) == 0U)
+ {
+ lastwordsize = (16U - npblb) / 4U;
+ }
+ else
+ {
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
+ }
+ /* Last block optionally pad the data with zeros*/
+ for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++)
+ {
+ /* Write the last input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ }
+ while (loopcounter < 4U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0U;
+ loopcounter++;
+ }
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Change the CRYP state and phase */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ }
+ }
+ else
+ {
+ /* Process unLocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Change the CRYP state and phase */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ }
+#endif /* AES */
+#if defined(CRYP)
+ /********************* Header phase *****************************************/
+
+ if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /******************** Payload phase *****************************************/
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Disable the CRYP peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ } /* if (DoKeyIVConfig == 1U) */
+ if (hcryp->Size != 0U)
+ {
+ /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption & CCM Decryption
+ Workaround is implemented in polling mode, so if last block of
+ payload <128bit don't use HAL_CRYP_AESGCM_DMA otherwise TAG is incorrectly generated for GCM Encryption. */
+ /* Set the input and output addresses and start DMA transfer */
+ if ((hcryp->Size % 16U) == 0U)
+ {
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), hcryp->Size / 4U, (uint32_t)(hcryp->pCrypOutBuffPtr));
+ }
+ else
+ {
+ wordsize = (uint32_t)(hcryp->Size) + 16U - ((uint32_t)(hcryp->Size) % 16U) ;
+
+ /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4*/
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t)wordsize / 4U,
+ (uint32_t)(hcryp->pCrypOutBuffPtr));
+ }
}
else /*Size = 0*/
{
/* Process unlocked */
__HAL_UNLOCK(hcryp);
-
+
/* Change the CRYP state and phase */
hcryp->State = HAL_CRYP_STATE_READY;
- }
-
+ }
+#endif /* CRYP */
/* Return function status */
return HAL_OK;
}
@@ -4715,516 +5312,525 @@
/**
* @brief Sets the payload phase in iterrupt mode
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
+ * the configuration information for CRYP module
* @retval state
*/
static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
-{
+{
uint32_t loopcounter;
- uint32_t temp; /* Temporary CrypOutBuff */
- uint32_t lastwordsize;
- uint32_t npblb;
- #if defined(AES)
- uint16_t outcount; /* Temporary CrypOutCount Value */
-#endif /* AES */
-
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t lastwordsize;
+ uint32_t npblb;
+ uint32_t i;
+#if defined(AES)
+ uint16_t outcount; /* Temporary CrypOutCount Value */
+#endif /* AES */
+
/***************************** Payload phase *******************************/
-
-#if defined(CRYP)
- if(hcryp->Size == 0U)
- {
+
+#if defined(CRYP)
+ if (hcryp->Size == 0U)
+ {
/* Disable interrupts */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI| CRYP_IT_OUTI);
-
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
/* Process unlocked */
__HAL_UNLOCK(hcryp);
-
+
/* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- }
-
- else if (((hcryp->Size/4U) - (hcryp->CrypInCount)) >= 4U)
- {
+ hcryp->State = HAL_CRYP_STATE_READY;
+ }
+
+ else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
+ {
/* Write the input block in the IN FIFO */
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- if(((hcryp->Size/4U) == hcryp->CrypInCount) &&((hcryp->Size %16U )== 0U))
- {
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ if (((hcryp->Size / 4U) == hcryp->CrypInCount) && ((hcryp->Size % 16U) == 0U))
+ {
/* Disable interrupts */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-
+
/* Call the input data transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
- if(hcryp->CrypOutCount < (hcryp->Size/4U))
+ }
+ if (hcryp->CrypOutCount < (hcryp->Size / 4U))
{
- /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- if (((hcryp->Size/4U) == hcryp->CrypOutCount)&&((hcryp->Size %16U )== 0U))
- {
+ /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+ for (i = 0U; i < 4U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUT;
+ }
+ i = 0U;
+ while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
+ if (((hcryp->Size / 4U) == hcryp->CrypOutCount) && ((hcryp->Size % 16U) == 0U))
+ {
/* Disable interrupts */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
-
+
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Disable CRYP */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Process unlocked */
__HAL_UNLOCK(hcryp);
-
+
/* Call output transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered Output complete callback*/
hcryp->OutCpltCallback(hcryp);
#else
/*Call legacy weak Output complete callback*/
HAL_CRYP_OutCpltCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
- }
- }
- else if ((hcryp->Size %16U )!= 0U)
- {
- /* Size should be %4 in word and %16 in byte otherwise TAG will be incorrectly generated for GCM Encryption & CCM Decryption
- Workaround is implemented in polling mode, so if last block of
- payload <128bit don't use CRYP_AESGCM_Encrypt_IT otherwise TAG is incorrectly generated. */
-
- /* Compute the number of padding bytes in last block of payload */
- npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U)- (uint32_t)(hcryp->Size);
-
- /* Number of valid words (lastwordsize) in last block */
- if ((npblb%4U) ==0U)
- {
- lastwordsize = (16U-npblb)/4U;
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
}
- else
+ }
+ else if ((hcryp->Size % 16U) != 0U)
+ {
+ /* Size should be %4 in word and %16 in byte otherwise TAG will be incorrectly generated for GCM Encryption & CCM Decryption
+ Workaround is implemented in polling mode, so if last block of
+ payload <128bit don't use CRYP_AESGCM_Encrypt_IT otherwise TAG is incorrectly generated. */
+
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
+
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) == 0U)
{
- lastwordsize = ((16U-npblb)/4U) +1U;
- }
-
+ lastwordsize = (16U - npblb) / 4U;
+ }
+ else
+ {
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
+ }
+
/* Last block optionally pad the data with zeros*/
- for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+ for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
{
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
}
- while(loopcounter < 4U )
- {
- /* Pad the data with zeros to have a complete block */
- hcryp->Instance->DIN = 0x0U;
+ while (loopcounter < 4U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DIN = 0x0U;
loopcounter++;
}
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-
- if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U)
+
+ if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
{
- for(loopcounter = 0U; loopcounter < 4U; loopcounter++)
- {
- /* Read the output block from the output FIFO and put them in temporary buffer */
- temp= hcryp->Instance->DOUT;
-
- /*get CrypOutBuff from temporary buffer */
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))=temp;
- hcryp->CrypOutCount++;
- }
- }
- if(hcryp->CrypOutCount >= (hcryp->Size/4U))
- {
+ for (i = 0U; i < 4U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUT;
+ }
+ if (((hcryp->Size) / 4U) == 0U)
+ {
+ for (i = 0U; i < ((uint32_t)(hcryp->Size) % 4U); i++)
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ }
+ }
+ i = 0x0U;
+ while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
+ }
+ if (hcryp->CrypOutCount >= (hcryp->Size / 4U))
+ {
/* Disable interrupts */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI|CRYP_IT_INI);
-
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI | CRYP_IT_INI);
+
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Process unlocked */
__HAL_UNLOCK(hcryp);
-
+
/* Call output transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered Output complete callback*/
hcryp->OutCpltCallback(hcryp);
#else
/*Call legacy weak Output complete callback*/
HAL_CRYP_OutCpltCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
}
else
{
/* Nothing to do */
}
#else /* AES */
-
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) =temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) =temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
+
+ /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
+ for (i = 0U; i < 4U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUTR;
+ }
+ i = 0U;
+ while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
/*Temporary CrypOutCount Value*/
outcount = hcryp->CrypOutCount;
-
- if((hcryp->CrypOutCount >= (hcryp->Size/4U)) && ((outcount*4U) >= hcryp->Size) )
+
+ if ((hcryp->CrypOutCount >= (hcryp->Size / 4U)) && ((outcount * 4U) >= hcryp->Size))
{
/* Disable computation complete flag and errors interrupts */
- __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CCFIE|CRYP_IT_ERRIE);
-
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
+
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Process unlocked */
__HAL_UNLOCK(hcryp);
-
- /* Call output transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
- /*Call registered Output complete callback*/
- hcryp->OutCpltCallback(hcryp);
+
+ /* Call output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Output complete callback*/
+ hcryp->OutCpltCallback(hcryp);
#else
- /*Call legacy weak Output complete callback*/
- HAL_CRYP_OutCpltCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
-
- else if (((hcryp->Size/4U) - (hcryp->CrypInCount)) >= 4U)
- {
+ /*Call legacy weak Output complete callback*/
+ HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+
+ else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
+ {
/* Write the input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- if((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC))
- {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ if ((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC))
+ {
/* Call Input transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
}
else /* Last block of payload < 128bit*/
- {
+ {
/* Workaround not implemented, Size should be %4 otherwise Tag will be incorrectly
- generated for GCM Encryption & CCM Decryption. Workaround is implemented in polling mode, so if last block of
- payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption & CCM Decryption. */
-
+ generated for GCM Encryption & CCM Decryption. Workaround is implemented in polling mode, so if last block of
+ payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption & CCM Decryption. */
+
/* Compute the number of padding bytes in last block of payload */
- npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U) - (uint32_t)(hcryp->Size);
-
- /* Number of valid words (lastwordsize) in last block */
- if ((npblb%4U) ==0U)
- {
- lastwordsize = (16U-npblb)/4U;
+ npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
+
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) == 0U)
+ {
+ lastwordsize = (16U - npblb) / 4U;
}
- else
+ else
{
- lastwordsize = ((16U-npblb)/4U) +1U;
- }
-
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
+ }
+
/* Last block optionally pad the data with zeros*/
- for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+ for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
{
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
}
- while(loopcounter < 4U )
- {
- /* pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0x0U;
+ while (loopcounter < 4U)
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
- }
-#endif /* AES */
+ }
+#endif /* AES */
-}
+}
/**
* @brief Sets the header phase in polling mode
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module(Header & HeaderSize)
- * @param Timeout: Timeout value
+ * @param Timeout: Timeout value
* @retval state
*/
static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint32_t loopcounter;
-
+
/***************************** Header phase for GCM/GMAC or CCM *********************************/
-
- if((hcryp->Init.HeaderSize != 0U))
+
+ if ((hcryp->Init.HeaderSize != 0U))
{
-
-#if defined(CRYP)
-
+
+#if defined(CRYP)
+
/* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- if ((hcryp->Init.HeaderSize %4U )== 0U)
- {
- /* HeaderSize %4, no padding */
- for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4U)
- {
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
-
- /* Wait for IFEM to be raised */
- if(CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- }
- else
- {
- /*Write header block in the IN FIFO without last block */
- for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+= 4U)
- {
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
-
- /* Wait for IFEM to be raised */
- if(CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- /* Last block optionally pad the data with zeros*/
- for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
- {
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- }
- while(loopcounter <4U )
- {
- /* pad the data with zeros to have a complete block */
- hcryp->Instance->DIN = 0x0U;
- loopcounter++;
- }
- /* Wait for CCF IFEM to be raised */
- if(CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- /* Wait until the complete message has been processed */
- if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked & return error */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
-
-#else /* AES */
-
- if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ __HAL_CRYP_ENABLE(hcryp);
+
+ if ((hcryp->Init.HeaderSize % 4U) == 0U)
{
- /* Workaround 1 :only AES before re-enabling the IP, datatype can be configured.*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
-
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- }
- if ((hcryp->Init.HeaderSize %4U )== 0U)
- {
- /* HeaderSize %4, no padding */
- for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+= 4U)
- {
- /* Write the input block in the data input register */
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
-
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- }
- }
- else
- {
- /*Write header block in the IN FIFO without last block */
- for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+=4U)
+ /* HeaderSize %4, no padding */
+ for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
{
- /* Write the input block in the data input register */
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
-
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ /* Wait for IFEM to be raised */
+ if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
+ {
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ }
+ else
+ {
+ /*Write header block in the IN FIFO without last block */
+ for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
+ {
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ /* Wait for IFEM to be raised */
+ if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ /* Last block optionally pad the data with zeros*/
+ for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
+ {
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ while (loopcounter < 4U)
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DIN = 0x0U;
+ loopcounter++;
+ }
+ /* Wait for CCF IFEM to be raised */
+ if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ /* Wait until the complete message has been processed */
+ if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked & return error */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+
+#else /* AES */
+
+ if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ {
+ /* Workaround 1 :only AES before re-enabling the IP, datatype can be configured.*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
+
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ }
+ if ((hcryp->Init.HeaderSize % 4U) == 0U)
+ {
+ /* HeaderSize %4, no padding */
+ for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
+ {
+ /* Write the input block in the data input register */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
/* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+ }
+ else
+ {
+ /*Write header block in the IN FIFO without last block */
+ for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
+ {
+ /* Write the input block in the data input register */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
}
/* Last block optionally pad the data with zeros*/
- for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
+ for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
{
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
}
- while(loopcounter < 4U )
- {
- /*Pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0x0U;
+ while (loopcounter < 4U)
+ {
+ /*Pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
loopcounter++;
- }
-
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
+ }
+
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
/* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- }
-#endif /* End AES or CRYP */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+#endif /* End AES or CRYP */
}
else
{
-#if defined(AES)
- if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
- {
+#if defined(AES)
+ if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ {
/*Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
-
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
+
/* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
}
-#endif /* AES */
+#endif /* AES */
}
/* Return function status */
return HAL_OK;
@@ -5233,107 +5839,105 @@
/**
* @brief Sets the header phase when using DMA in process
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module(Header & HeaderSize)
+ * the configuration information for CRYP module(Header & HeaderSize)
* @retval None
*/
static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp)
{
__IO uint32_t count = 0U;
uint32_t loopcounter;
-
- /***************************** Header phase for GCM/GMAC or CCM *********************************/
- if((hcryp->Init.HeaderSize != 0U))
+
+ /***************************** Header phase for GCM/GMAC or CCM *********************************/
+ if ((hcryp->Init.HeaderSize != 0U))
{
-
-#if defined(CRYP)
-
+
+#if defined(CRYP)
+
/* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- if ((hcryp->Init.HeaderSize %4U )== 0U)
- {
- /* HeaderSize %4, no padding */
- for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4U)
- {
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ __HAL_CRYP_ENABLE(hcryp);
+
+ if ((hcryp->Init.HeaderSize % 4U) == 0U)
+ {
+ /* HeaderSize %4, no padding */
+ for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
+ {
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
-
+
/* Wait for IFEM to be raised */
count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
do
{
count-- ;
- if(count == 0U)
+ if (count == 0U)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- }
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
}
}
else
- {
+ {
/*Write header block in the IN FIFO without last block */
- for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+=4U)
- {
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
+ {
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
-
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
/* Wait for IFEM to be raised */
count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
do
{
count-- ;
- if(count == 0U)
+ if (count == 0U)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- }
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
}
/* Last block optionally pad the data with zeros*/
- for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
+ for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
{
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
}
- while(loopcounter < 4U )
- {
- /* Pad the data with zeros to have a complete block */
- hcryp->Instance->DIN = 0x0U;
+ while (loopcounter < 4U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DIN = 0x0U;
loopcounter++;
}
/* Wait for IFEM to be raised */
@@ -5341,189 +5945,184 @@
do
{
count-- ;
- if(count == 0U)
+ if (count == 0U)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- }
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
- }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
+ }
/* Wait until the complete message has been processed */
count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
do
{
count-- ;
- if(count == 0U)
+ if (count == 0U)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- }
- while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
-
-#else /* AES */
-
- if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
+
+#else /* AES */
+
+ if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
{
/* Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
-
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
+
/* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
}
- if ((hcryp->Init.HeaderSize %4U )== 0U)
- {
- /* HeaderSize %4, no padding */
- for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4U)
- {
+ if ((hcryp->Init.HeaderSize % 4U) == 0U)
+ {
+ /* HeaderSize %4, no padding */
+ for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
+ {
/* Write the input block in the data input register */
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
-
- /*Wait on CCF flag*/
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ /*Wait on CCF flag*/
count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
do
{
count-- ;
- if(count == 0U)
+ if (count == 0U)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- }
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
/* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
}
}
else
- {
+ {
/*Write header block in the IN FIFO without last block */
- for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+=4U)
+ for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
{
/* Write the Input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
-
- /*Wait on CCF flag*/
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ /*Wait on CCF flag*/
count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
do
{
count-- ;
- if(count == 0U)
+ if (count == 0U)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- }
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
/* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
}
/* Last block optionally pad the data with zeros*/
- for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
+ for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
{
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
}
- while(loopcounter <4U )
- {
- /* Pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0x0U;
+ while (loopcounter < 4U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
loopcounter++;
- }
-
- /*Wait on CCF flag*/
+ }
+
+ /*Wait on CCF flag*/
count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
do
{
count-- ;
- if(count == 0U)
+ if (count == 0U)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- }
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
/* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- }
-#endif /* End AES or CRYP */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+#endif /* End AES or CRYP */
}
else
{
-#if defined(AES)
- if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
- {
+#if defined(AES)
+ if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ {
/*Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
-
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
+
/* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
}
-#endif /* AES */
+#endif /* AES */
}
/* Return function status */
return HAL_OK;
@@ -5538,648 +6137,773 @@
static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
{
uint32_t loopcounter;
-#if defined(AES)
- uint32_t lastwordsize;
- uint32_t npblb;
-#endif
+#if defined(AES)
+ uint32_t lastwordsize;
+ uint32_t npblb;
+#endif
/***************************** Header phase *********************************/
-
-#if defined(CRYP)
- if(hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
- {
+
+#if defined(CRYP)
+ if (hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
+ {
/* Disable interrupts */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI );
-
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+
/* Disable the CRYP peripheral */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
-
+
/* Select payload phase once the header phase is performed */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI );
-
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
- }
+ __HAL_CRYP_ENABLE(hcryp);
+ }
else if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)
-
- { /* HeaderSize %4, no padding */
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount );
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+
+ {
+ /* HeaderSize %4, no padding */
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
}
else
- {
+ {
/* Last block optionally pad the data with zeros*/
- for(loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize %4U ); loopcounter++)
+ for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
{
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header+ hcryp->CrypHeaderCount);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
}
- while(loopcounter <4U )
- {
- /* Pad the data with zeros to have a complete block */
- hcryp->Instance->DIN = 0x0U;
+ while (loopcounter < 4U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DIN = 0x0U;
loopcounter++;
- }
- }
-#else /* AES */
-
- if(hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
+ }
+ }
+#else /* AES */
+
+ if (hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
{
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
-
+
/* Payload phase not supported in CCM AES2 */
- if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
{
/* Select payload phase once the header phase is performed */
MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
- }
- if(hcryp->Init.Algorithm == CRYP_AES_CCM)
+ }
+ if (hcryp->Init.Algorithm == CRYP_AES_CCM)
{
/* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */
- hcryp->CrypHeaderCount++;
- }
- /* Write the payload Input block in the IN FIFO */
- if(hcryp->Size == 0U)
- {
+ hcryp->CrypHeaderCount++;
+ }
+ /* Write the payload Input block in the IN FIFO */
+ if (hcryp->Size == 0U)
+ {
/* Disable interrupts */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE| CRYP_IT_ERRIE);
-
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
+
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Process unlocked */
__HAL_UNLOCK(hcryp);
- }
+ }
else if (hcryp->Size >= 16U)
- {
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
-
- if((hcryp->CrypInCount == (hcryp->Size/4U)) &&((hcryp->Size %16U )== 0U))
- {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+
+ if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
+ {
/* Call the input data transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
+ }
}
else /* Size < 4 words : first block is the last block*/
{
/* Workaround not implemented, Size should be %4 otherwise Tag will be incorrectly
- generated for GCM Encryption. Workaround is implemented in polling mode, so if last block of
+ generated for GCM Encryption. Workaround is implemented in polling mode, so if last block of
payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
-
+
/* Compute the number of padding bytes in last block of payload */
- npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U) - (uint32_t)(hcryp->Size);
-
+ npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
+
/* Number of valid words (lastwordsize) in last block */
- if ((npblb % 4U) ==0U)
- {
- lastwordsize = (16U-npblb)/4U;
+ if ((npblb % 4U) == 0U)
+ {
+ lastwordsize = (16U - npblb) / 4U;
}
- else
+ else
{
- lastwordsize = ((16U-npblb)/4U) +1U;
- }
-
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
+ }
+
/* Last block optionally pad the data with zeros*/
- for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+ for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
{
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
}
- while(loopcounter <4U )
- {
- /* Pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0x0U;
+ while (loopcounter < 4U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
}
- }
+ }
else if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)
- {
+ {
/* Write the input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
- hcryp->CrypHeaderCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
- hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
}
else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/
- {
+ {
/* Last block optionally pad the data with zeros*/
- for(loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize %4U ); loopcounter++)
+ for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
{
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
}
- while(loopcounter <4U )
- {
- /* pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0x0U;
+ while (loopcounter < 4U)
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
- }
-#endif /* End AES or CRYP */
-}
+ }
+#endif /* End AES or CRYP */
+}
/**
- * @brief Workaround used for GCM/CCM mode.
+ * @brief Workaround used for GCM/CCM mode.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param Timeout: specify Timeout value
+ * @param Timeout: specify Timeout value
* @retval None
*/
-static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout )
+static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint32_t lastwordsize;
- uint32_t npblb;
-#if defined(CRYP)
+ uint32_t npblb;
+#if defined(CRYP)
uint32_t iv1temp;
uint32_t temp[4] = {0};
- uint32_t temp2[4]= {0};
+ uint32_t temp2[4] = {0};
#endif /* CRYP */
- uint32_t intermediate_data[4]={0};
+ uint32_t intermediate_data[4] = {0};
uint32_t index;
-
- /* Compute the number of padding bytes in last block of payload */
- npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U)- (uint32_t)(hcryp->Size);
-
+
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
+
/* Number of valid words (lastwordsize) in last block */
- if ((npblb%4U) ==0U)
- { lastwordsize = (16U-npblb)/4U;
+ if ((npblb % 4U) == 0U)
+ {
+ lastwordsize = (16U - npblb) / 4U;
}
- else
- {lastwordsize = ((16U-npblb)/4U) +1U;
+ else
+ {
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
}
-
-#if defined(CRYP)
-
+
+#if defined(CRYP)
+
/* Workaround 2, case GCM encryption */
if (hcryp->Init.Algorithm == CRYP_AES_GCM)
{
- if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
- {/*Workaround in order to properly compute authentication tags while doing
- a GCM encryption with the last block of payload size inferior to 128 bits*/
+ if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
+ {
+ /*Workaround in order to properly compute authentication tags while doing
+ a GCM encryption with the last block of payload size inferior to 128 bits*/
/* Disable CRYP to start the final phase */
__HAL_CRYP_DISABLE(hcryp);
-
- /*Load CRYP_IV1R register content in a temporary variable. Decrement the value
- by 1 and reinsert the result in CRYP_IV1R register*/
- hcryp->Instance->IV1RR = 0x5U;
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
-
+
+ /*Update CRYP_IV1R register and ALGOMODE*/
+ hcryp->Instance->IV1RR = ((hcryp->Instance->CSGCMCCM7R) - 1U);
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
+
/* Enable CRYP to start the final phase */
__HAL_CRYP_ENABLE(hcryp);
}
- /* Last block optionally pad the data with zeros*/
- for(index=0; index < lastwordsize; index ++)
+ /* Last block optionally pad the data with zeros*/
+ for (index = 0; index < lastwordsize; index ++)
{
/* Write the last input block in the IN FIFO */
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- }
- while(index < 4U)
+ }
+ while (index < 4U)
{
/* Pad the data with zeros to have a complete block */
hcryp->Instance->DIN = 0U;
- index++;
- }
+ index++;
+ }
/* Wait for OFNE flag to be raised */
- if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
- {
+ if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
+ {
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
- if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U)
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
{
- for(index=0U; index< 4U;index++)
- {
+ for (index = 0U; index < 4U; index++)
+ {
/* Read the output block from the output FIFO */
- intermediate_data[index] = hcryp->Instance->DOUT;
-
+ intermediate_data[index] = hcryp->Instance->DOUT;
+
/* Intermediate data buffer to be used in for the workaround*/
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))=intermediate_data[index];
- hcryp->CrypOutCount++;
- }
- }
-
- if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index];
+ hcryp->CrypOutCount++;
+ }
+ }
+
+ if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
{
/*workaround in order to properly compute authentication tags while doing
a GCM encryption with the last block of payload size inferior to 128 bits*/
/* Change the AES mode to GCM mode and Select Final phase */
/* configured CHMOD GCM */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_GCM);
-
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_GCM);
+
/* configured final phase */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
-
- for (index=0U; index < lastwordsize; index ++)
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
+
+ if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_32B)
+ {
+ if ((npblb % 4U) == 1U)
+ {
+ intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U;
+ }
+ if ((npblb % 4U) == 2U)
+ {
+ intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U;
+ }
+ if ((npblb % 4U) == 3U)
+ {
+ intermediate_data[lastwordsize - 1U] &= 0xFF000000U;
+ }
+ }
+ else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_8B)
+ {
+ if ((npblb % 4U) == 1U)
+ {
+ intermediate_data[lastwordsize - 1U] &= __REV(0xFFFFFF00U);
+ }
+ if ((npblb % 4U) == 2U)
+ {
+ intermediate_data[lastwordsize - 1U] &= __REV(0xFFFF0000U);
+ }
+ if ((npblb % 4U) == 3U)
+ {
+ intermediate_data[lastwordsize - 1U] &= __REV(0xFF000000U);
+ }
+ }
+ else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_16B)
+ {
+ if ((npblb % 4U) == 1U)
+ {
+ intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFFFF00U), 16);
+ }
+ if ((npblb % 4U) == 2U)
+ {
+ intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFF0000U), 16);
+ }
+ if ((npblb % 4U) == 3U)
+ {
+ intermediate_data[lastwordsize - 1U] &= __ROR((0xFF000000U), 16);
+ }
+ }
+ else /*CRYP_DATATYPE_1B*/
+ {
+ if ((npblb % 4U) == 1U)
+ {
+ intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFFFF00U);
+ }
+ if ((npblb % 4U) == 2U)
+ {
+ intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFF0000U);
+ }
+ if ((npblb % 4U) == 3U)
+ {
+ intermediate_data[lastwordsize - 1U] &= __RBIT(0xFF000000U);
+ }
+ }
+ for (index = 0U; index < lastwordsize; index ++)
{
/*Write the intermediate_data in the IN FIFO */
- hcryp->Instance->DIN=intermediate_data[index];
- }
- while(index < 4U)
+ hcryp->Instance->DIN = intermediate_data[index];
+ }
+ while (index < 4U)
{
/* Pad the data with zeros to have a complete block */
hcryp->Instance->DIN = 0x0U;
- index++;
- }
+ index++;
+ }
/* Wait for OFNE flag to be raised */
- if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
- {
+ if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
+ {
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- hcryp->ErrorCallback(hcryp);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
#else
- /*Call legacy weak error callback*/
- HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
-
- if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U)
- {
- for( index=0U; index< 4U;index++)
- {
- intermediate_data[index]=hcryp->Instance->DOUT;
- }
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+
+ if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
+ {
+ for (index = 0U; index < 4U; index++)
+ {
+ intermediate_data[index] = hcryp->Instance->DOUT;
+ }
}
}
} /* End of GCM encryption */
- else{ /* Workaround 2, case CCM decryption, in order to properly compute
- authentication tags while doing a CCM decryption with the last block
- of payload size inferior to 128 bits*/
-
- if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
+ else
+ {
+ /* Workaround 2, case CCM decryption, in order to properly compute
+ authentication tags while doing a CCM decryption with the last block
+ of payload size inferior to 128 bits*/
+
+ if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
{
- iv1temp = hcryp->Instance->CSGCMCCM7R;
-
+ iv1temp = hcryp->Instance->CSGCMCCM7R;
+
/* Disable CRYP to start the final phase */
__HAL_CRYP_DISABLE(hcryp);
-
- temp[0]= hcryp->Instance->CSGCMCCM0R;
- temp[1]= hcryp->Instance->CSGCMCCM1R;
- temp[2]= hcryp->Instance->CSGCMCCM2R;
- temp[3]= hcryp->Instance->CSGCMCCM3R;
-
- hcryp->Instance->IV1RR= iv1temp;
-
+
+ temp[0] = hcryp->Instance->CSGCMCCM0R;
+ temp[1] = hcryp->Instance->CSGCMCCM1R;
+ temp[2] = hcryp->Instance->CSGCMCCM2R;
+ temp[3] = hcryp->Instance->CSGCMCCM3R;
+
+ hcryp->Instance->IV1RR = iv1temp;
+
/* Configured CHMOD CTR */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
-
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
+
/* Enable CRYP to start the final phase */
__HAL_CRYP_ENABLE(hcryp);
}
- /* Last block optionally pad the data with zeros*/
- for(index=0; index < lastwordsize; index ++)
+ /* Last block optionally pad the data with zeros*/
+ for (index = 0; index < lastwordsize; index ++)
{
/* Write the last Input block in the IN FIFO */
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- }
- while(index < 4U)
+ }
+ while (index < 4U)
{
/* Pad the data with zeros to have a complete block */
hcryp->Instance->DIN = 0U;
- index++;
+ index++;
}
/* Wait for OFNE flag to be raised */
- if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
- {
+ if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
+ {
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
-
- if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U)
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+
+ if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
{
- for(index=0U; index< 4U;index++)
- {
+ for (index = 0U; index < 4U; index++)
+ {
/* Read the Output block from the Output FIFO */
- intermediate_data[index] = hcryp->Instance->DOUT;
-
+ intermediate_data[index] = hcryp->Instance->DOUT;
+
/*intermediate data buffer to be used in for the workaround*/
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))=intermediate_data[index];
- hcryp->CrypOutCount++;
- }
- }
-
- if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
- {
- temp2[0]= hcryp->Instance->CSGCMCCM0R;
- temp2[1]= hcryp->Instance->CSGCMCCM1R;
- temp2[2]= hcryp->Instance->CSGCMCCM2R;
- temp2[3]= hcryp->Instance->CSGCMCCM3R;
-
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index];
+ hcryp->CrypOutCount++;
+ }
+ }
+
+ if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
+ {
+ temp2[0] = hcryp->Instance->CSGCMCCM0R;
+ temp2[1] = hcryp->Instance->CSGCMCCM1R;
+ temp2[2] = hcryp->Instance->CSGCMCCM2R;
+ temp2[3] = hcryp->Instance->CSGCMCCM3R;
+
/* configured CHMOD CCM */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CCM);
-
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CCM);
+
/* configured Header phase */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_HEADER);
-
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_HEADER);
+
/*set to zero the bits corresponding to the padded bits*/
- for(index = lastwordsize; index<4U; index ++)
+ for (index = lastwordsize; index < 4U; index ++)
{
- intermediate_data[index] =0U;
- }
- if ((npblb %4U)==1U)
- {
- intermediate_data[lastwordsize-1U] &= 0xFFFFFF00U;
+ intermediate_data[index] = 0U;
}
- if ((npblb %4U)==2U)
+ if ((npblb % 4U) == 1U)
{
- intermediate_data[lastwordsize-1U] &= 0xFFFF0000U;
+ intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U;
}
- if ((npblb %4U)==3U)
+ if ((npblb % 4U) == 2U)
{
- intermediate_data[lastwordsize-1U] &= 0xFF000000U;
+ intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U;
}
- for(index=0U; index < 4U ; index ++)
- {
+ if ((npblb % 4U) == 3U)
+ {
+ intermediate_data[lastwordsize - 1U] &= 0xFF000000U;
+ }
+ for (index = 0U; index < 4U ; index ++)
+ {
intermediate_data[index] ^= temp[index];
- intermediate_data[index] ^= temp2[index];
+ intermediate_data[index] ^= temp2[index];
}
- for(index = 0U; index < 4U; index ++)
+ for (index = 0U; index < 4U; index ++)
{
/* Write the last Input block in the IN FIFO */
hcryp->Instance->DIN = intermediate_data[index] ;
- }
-
+ }
+
/* Wait for BUSY flag to be raised */
- if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
- {
+ if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
+ {
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
- /*Call registered error callback*/
- hcryp->ErrorCallback(hcryp);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
#else
- /*Call legacy weak error callback*/
- HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
- } /* End of CCM WKA*/
-
+ } /* End of CCM WKA*/
+
/* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
+ __HAL_UNLOCK(hcryp);
+
#else /* AES */
-
- /*Workaround 2: case GCM encryption, during payload phase and before inserting
- the last block of paylaod, which size is inferior to 128 bits */
-
- if((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
+
+ /*Workaround 2: case GCM encryption, during payload phase and before inserting
+ the last block of paylaod, which size is inferior to 128 bits */
+
+ if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
{
/* configured CHMOD CTR */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_CTR);
- }
- /* last block optionally pad the data with zeros*/
- for(index = 0U; index < lastwordsize; index ++)
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_CTR);
+ }
+ /* last block optionally pad the data with zeros*/
+ for (index = 0U; index < lastwordsize; index ++)
{
/* Write the last Input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- }
- while(index < 4U)
+ }
+ while (index < 4U)
{
/* pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0U;
- index++;
- }
- /* Wait for CCF flag to be raised */
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
- /*Call registered error callback*/
- hcryp->ErrorCallback(hcryp);
-#else
- /*Call legacy weak error callback*/
- HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ index++;
}
-
+ /* Wait for CCF flag to be raised */
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
- for(index = 0U; index< 4U;index++)
- {
- /* Read the Output block from the Output FIFO */
- intermediate_data[index] = hcryp->Instance->DOUTR;
-
+
+ for (index = 0U; index < 4U; index++)
+ {
+ /* Read the Output block from the Output FIFO */
+ intermediate_data[index] = hcryp->Instance->DOUTR;
+
/*intermediate data buffer to be used in the workaround*/
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))= intermediate_data[index];
- hcryp->CrypOutCount++;
- }
-
- if((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
- {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index];
+ hcryp->CrypOutCount++;
+ }
+
+ if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
+ {
/* configured CHMOD GCM */
MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_GCM_GMAC);
-
+
/* Select final phase */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
-
- /*Write the intermediate_data in the IN FIFO */
- for(index = 0U; index < lastwordsize; index ++)
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
+
+ if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_32B)
+ {
+ if ((npblb % 4U) == 1U)
+ {
+ intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U;
+ }
+ if ((npblb % 4U) == 2U)
+ {
+ intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U;
+ }
+ if ((npblb % 4U) == 3U)
+ {
+ intermediate_data[lastwordsize - 1U] &= 0xFF000000U;
+ }
+ }
+ else if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_8B)
+ {
+ if ((npblb % 4U) == 1U)
+ {
+ intermediate_data[lastwordsize - 1U] &= __REV(0xFFFFFF00U);
+ }
+ if ((npblb % 4U) == 2U)
+ {
+ intermediate_data[lastwordsize - 1U] &= __REV(0xFFFF0000U);
+ }
+ if ((npblb % 4U) == 3U)
+ {
+ intermediate_data[lastwordsize - 1U] &= __REV(0xFF000000U);
+ }
+ }
+ else if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_16B)
+ {
+ if ((npblb % 4U) == 1U)
+ {
+ intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFFFF00U), 16);
+ }
+ if ((npblb % 4U) == 2U)
+ {
+ intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFF0000U), 16);
+ }
+ if ((npblb % 4U) == 3U)
+ {
+ intermediate_data[lastwordsize - 1U] &= __ROR((0xFF000000U), 16);
+ }
+ }
+ else /*CRYP_DATATYPE_1B*/
+ {
+ if ((npblb % 4U) == 1U)
+ {
+ intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFFFF00U);
+ }
+ if ((npblb % 4U) == 2U)
+ {
+ intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFF0000U);
+ }
+ if ((npblb % 4U) == 3U)
+ {
+ intermediate_data[lastwordsize - 1U] &= __RBIT(0xFF000000U);
+ }
+ }
+
+ /*Write the intermediate_data in the IN FIFO */
+ for (index = 0U; index < lastwordsize; index ++)
{
hcryp->Instance->DINR = intermediate_data[index];
- }
- while(index < 4U)
+ }
+ while (index < 4U)
{
/* pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0U;
- index++;
+ index++;
}
/* Wait for CCF flag to be raised */
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
- for( index = 0U; index< 4U;index++)
- {
- intermediate_data[index]=hcryp->Instance->DOUTR;
+
+ for (index = 0U; index < 4U; index++)
+ {
+ intermediate_data[index] = hcryp->Instance->DOUTR;
}
- }/*End of Workaround 2*/
-
-#endif /* End AES or CRYP */
+ }/*End of Workaround 2*/
+#endif /* End AES or CRYP */
}
-#if defined (CRYP)
+#if defined (CRYP)
/**
* @brief Handle CRYP hardware block Timeout when waiting for IFEM flag to be raised.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
+ * the configuration information for CRYP module.
* @param Timeout: Timeout duration.
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint32_t tickstart;
-
+
/* Get timeout */
tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
+
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
- {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
return HAL_ERROR;
}
}
- }
- return HAL_OK;
+ }
+ return HAL_OK;
}
/**
* @brief Handle CRYP hardware block Timeout when waiting for BUSY flag to be raised.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
+ * the configuration information for CRYP module.
* @param Timeout: Timeout duration.
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint32_t tickstart;
-
+
/* Get timeout */
tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
+
+ while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
- {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
return HAL_ERROR;
}
}
}
- return HAL_OK;
+ return HAL_OK;
}
/**
* @brief Handle CRYP hardware block Timeout when waiting for OFNE flag to be raised.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
+ * the configuration information for CRYP module.
* @param Timeout: Timeout duration.
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint32_t tickstart;
-
+
/* Get timeout */
tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
+
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
- {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
return HAL_ERROR;
}
}
}
- return HAL_OK;
+ return HAL_OK;
}
#else /* AES */
@@ -6187,29 +6911,29 @@
/**
* @brief Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
+ * the configuration information for CRYP module.
* @param Timeout: Timeout duration.
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint32_t tickstart;
-
+
/* Get timeout */
tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
- {
+
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
+ {
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U) )
- {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
return HAL_ERROR;
}
}
}
- return HAL_OK;
+ return HAL_OK;
}
#endif /* End AES or CRYP */
@@ -6217,8 +6941,8 @@
/**
* @}
- */
-
+ */
+
/**
diff --git a/Src/stm32f7xx_hal_cryp_ex.c b/Src/stm32f7xx_hal_cryp_ex.c
index 213ca74..1a7a6b9 100644
--- a/Src/stm32f7xx_hal_cryp_ex.c
+++ b/Src/stm32f7xx_hal_cryp_ex.c
@@ -3,17 +3,17 @@
* @file stm32f7xx_hal_cryp_ex.c
* @author MCD Application Team
* @brief Extended CRYP HAL module driver
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of CRYP extension peripheral:
- * + Extended AES processing functions
- *
+ * + Extended AES processing functions
+ *
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The CRYP extension HAL driver can be used as follows:
- (#)After AES-GCM or AES-CCM Encryption/Decryption user can start following API
+ (#)After AES-GCM or AES-CCM Encryption/Decryption user can start following API
to get the authentication messages :
(##) HAL_CRYPEx_AESGCM_GenerateAuthTAG
(##) HAL_CRYPEx_AESCCM_GenerateAuthTAG
@@ -22,16 +22,16 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
+ * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
@@ -55,10 +55,10 @@
* @{
*/
#if defined(AES)
-#define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
-#define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */
-#define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */
-#define CRYP_PHASE_FINAL AES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */
+#define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
+#define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */
+#define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */
+#define CRYP_PHASE_FINAL AES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */
#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode */
#define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC decryptions */
@@ -77,11 +77,11 @@
#endif /* End AES or CRYP */
#define CRYPEx_PHASE_PROCESS 0x02U /*!< CRYP peripheral is in processing phase */
-#define CRYPEx_PHASE_FINAL 0x03U /*!< CRYP peripheral is in final phase this is relevant only with CCM and GCM modes */
+#define CRYPEx_PHASE_FINAL 0x03U /*!< CRYP peripheral is in final phase this is relevant only with CCM and GCM modes */
- /* CTR0 information to use in CCM algorithm */
-#define CRYP_CCM_CTR0_0 0x07FFFFFFU
-#define CRYP_CCM_CTR0_3 0xFFFFFF00U
+/* CTR0 information to use in CCM algorithm */
+#define CRYP_CCM_CTR0_0 0x07FFFFFFU
+#define CRYP_CCM_CTR0_3 0xFFFFFF00U
/**
@@ -99,15 +99,15 @@
* @{
*/
-/** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
- * @brief Extended processing functions.
- *
-@verbatim
+/** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
+ * @brief Extended processing functions.
+ *
+@verbatim
==============================================================================
##### Extended AES processing functions #####
- ==============================================================================
- [..] This section provides functions allowing to generate the authentication
- TAG in Polling mode
+ ==============================================================================
+ [..] This section provides functions allowing to generate the authentication
+ TAG in Polling mode
(#)HAL_CRYPEx_AESGCM_GenerateAuthTAG
(#)HAL_CRYPEx_AESCCM_GenerateAuthTAG
they should be used after Encrypt/Decrypt operation.
@@ -127,79 +127,79 @@
*/
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
{
- uint32_t tickstart;
+ uint32_t tickstart;
uint64_t headerlength = (uint64_t)(hcryp->Init.HeaderSize) * 32U; /* Header length in bits */
- uint64_t inputlength = (uint64_t)(hcryp->Size) * 8U; /* input length in bits */
- uint32_t tagaddr = (uint32_t)AuthTag;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
+ uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* input length in bits */
+ uint32_t tagaddr = (uint32_t)AuthTag;
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
/* Process locked */
__HAL_LOCK(hcryp);
-
+
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_BUSY;
-
+
/* Check if initialization phase has already been performed */
- if(hcryp->Phase == CRYPEx_PHASE_PROCESS)
+ if (hcryp->Phase == CRYPEx_PHASE_PROCESS)
{
/* Change the CRYP phase */
hcryp->Phase = CRYPEx_PHASE_FINAL;
}
else /* Initialization phase has not been performed*/
- {
+ {
/* Disable the Peripheral */
__HAL_CRYP_DISABLE(hcryp);
-
- /* Sequence error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
-
+
+ /* Sequence error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
+
/* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
+ hcryp->State = HAL_CRYP_STATE_READY;
+
/* Process unlocked */
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
-
+
#if defined(CRYP)
-
+
/* Disable CRYP to start the final phase */
__HAL_CRYP_DISABLE(hcryp);
-
- /* Select final phase */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
-
- /*ALGODIR bit must be set to ‘0’.*/
+
+ /* Select final phase */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
+
+ /*ALGODIR bit must be set to ‘0’.*/
hcryp->Instance->CR &= ~CRYP_CR_ALGODIR;
-
+
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
-
+
/* Write the number of bits in header (64 bits) followed by the number of bits
in the payload */
- if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
+ if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
{
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = __RBIT((uint32_t)(headerlength));
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = __RBIT((uint32_t)(inputlength));
}
- else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
{
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = __REV((uint32_t)(headerlength));
hcryp->Instance->DIN = 0U;
- hcryp->Instance->DIN = __REV((uint32_t)(inputlength));
+ hcryp->Instance->DIN = __REV((uint32_t)(inputlength));
}
- else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
{
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = __ROR((uint32_t)headerlength, 16U);
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = __ROR((uint32_t)inputlength, 16U);
}
- else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_32B)
{
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = (uint32_t)(headerlength);
@@ -210,68 +210,68 @@
{
/* Nothing to do */
}
-
+
/* Wait for OFNE flag to be raised */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
- {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
/* Disable the CRYP Peripheral Clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
- }
-
+ }
+
/* Read the authentication TAG in the output FIFO */
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
-
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
+ tagaddr += 4U;
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
+ tagaddr += 4U;
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
+ tagaddr += 4U;
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
+
#else /* AES*/
-
+
/* Select final phase */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
-
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
+
/* Write the number of bits in header (64 bits) followed by the number of bits
- in the payload */
- if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
+ in the payload */
+ if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
{
hcryp->Instance->DINR = 0U;
hcryp->Instance->DINR = __RBIT((uint32_t)(headerlength));
hcryp->Instance->DINR = 0U;
hcryp->Instance->DINR = __RBIT((uint32_t)(inputlength));
}
- else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
{
hcryp->Instance->DINR = 0U;
hcryp->Instance->DINR = __REV((uint32_t)(headerlength));
hcryp->Instance->DINR = 0U;
- hcryp->Instance->DINR = __REV((uint32_t)(inputlength));
+ hcryp->Instance->DINR = __REV((uint32_t)(inputlength));
}
- else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
{
hcryp->Instance->DINR = 0U;
hcryp->Instance->DINR = __ROR((uint32_t)headerlength, 16U);
hcryp->Instance->DINR = 0U;
hcryp->Instance->DINR = __ROR((uint32_t)inputlength, 16U);
}
- else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_32B)
{
hcryp->Instance->DINR = 0U;
hcryp->Instance->DINR = (uint32_t)(headerlength);
@@ -284,56 +284,56 @@
}
/* Wait for CCF flag to be raised */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
- {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
- }
-
+ }
+
/* Read the authentication TAG in the output FIFO */
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
-
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr += 4U;
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr += 4U;
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr += 4U;
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
+
/* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
-#endif /* End AES or CRYP */
-
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+#endif /* End AES or CRYP */
+
/* Disable the peripheral */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
+ hcryp->State = HAL_CRYP_STATE_READY;
+
/* Process unlocked */
__HAL_UNLOCK(hcryp);
}
else
{
/* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
return HAL_ERROR;
- }
+ }
/* Return function status */
return HAL_OK;
}
@@ -349,11 +349,11 @@
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
{
uint32_t tagaddr = (uint32_t)AuthTag;
- uint32_t ctr0 [4]={0};
+ uint32_t ctr0 [4] = {0};
uint32_t ctr0addr = (uint32_t)ctr0;
uint32_t tickstart;
- if(hcryp->State == HAL_CRYP_STATE_READY)
+ if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Process locked */
__HAL_LOCK(hcryp);
@@ -362,7 +362,7 @@
hcryp->State = HAL_CRYP_STATE_BUSY;
/* Check if initialization phase has already been performed */
- if(hcryp->Phase == CRYPEx_PHASE_PROCESS)
+ if (hcryp->Phase == CRYPEx_PHASE_PROCESS)
{
/* Change the CRYP phase */
hcryp->Phase = CRYPEx_PHASE_FINAL;
@@ -383,72 +383,72 @@
return HAL_ERROR;
}
-#if defined(CRYP)
+#if defined(CRYP)
/* Disable CRYP to start the final phase */
__HAL_CRYP_DISABLE(hcryp);
/* Select final phase & ALGODIR bit must be set to ‘0’. */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH|CRYP_CR_ALGODIR, CRYP_PHASE_FINAL|CRYP_OPERATINGMODE_ENCRYPT);
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH | CRYP_CR_ALGODIR, CRYP_PHASE_FINAL | CRYP_OPERATINGMODE_ENCRYPT);
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
/* Write the counter block in the IN FIFO, CTR0 information from B0
data has to be swapped according to the DATATYPE*/
- ctr0[0]=(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0;
- ctr0[1]=hcryp->Init.B0[1];
- ctr0[2]=hcryp->Init.B0[2];
- ctr0[3]=hcryp->Init.B0[3] & CRYP_CCM_CTR0_3;
+ ctr0[0] = (hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0;
+ ctr0[1] = hcryp->Init.B0[1];
+ ctr0[2] = hcryp->Init.B0[2];
+ ctr0[3] = hcryp->Init.B0[3] & CRYP_CCM_CTR0_3;
- if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
{
- hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr));
- ctr0addr+=4U;
- hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr));
- ctr0addr+=4U;
- hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr));
- ctr0addr+=4U;
- hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr));
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
+ ctr0addr += 4U;
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
+ ctr0addr += 4U;
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
+ ctr0addr += 4U;
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
}
- else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
{
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U);
- ctr0addr+=4U;
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U);
- ctr0addr+=4U;
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U);
- ctr0addr+=4U;
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U);
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U);
+ ctr0addr += 4U;
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U);
+ ctr0addr += 4U;
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U);
+ ctr0addr += 4U;
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U);
}
- else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
{
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr));
- ctr0addr+=4U;
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr));
- ctr0addr+=4U;
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr));
- ctr0addr+=4U;
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr));
+ ctr0addr += 4U;
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr));
+ ctr0addr += 4U;
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr));
+ ctr0addr += 4U;
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr));
}
else
{
- hcryp->Instance->DIN = *(uint32_t*)(ctr0addr);
- ctr0addr+=4U;
- hcryp->Instance->DIN = *(uint32_t*)(ctr0addr);
- ctr0addr+=4U;
- hcryp->Instance->DIN = *(uint32_t*)(ctr0addr);
- ctr0addr+=4U;
- hcryp->Instance->DIN = *(uint32_t*)(ctr0addr);
+ hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
+ ctr0addr += 4U;
+ hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
+ ctr0addr += 4U;
+ hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
+ ctr0addr += 4U;
+ hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
}
/* Wait for OFNE flag to be raised */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP peripheral Clock */
__HAL_CRYP_DISABLE(hcryp);
@@ -465,13 +465,13 @@
}
/* Read the Auth TAG in the IN FIFO */
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
+ tagaddr += 4U;
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
+ tagaddr += 4U;
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
+ tagaddr += 4U;
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
#else /* AES */
@@ -480,75 +480,75 @@
/* Write the counter block in the IN FIFO, CTR0 information from B0
data has to be swapped according to the DATATYPE*/
- if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
{
- ctr0[0]=(__REV(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0);
- ctr0[1]=__REV(hcryp->Init.B0[1]);
- ctr0[2]=__REV(hcryp->Init.B0[2]);
- ctr0[3]=(__REV(hcryp->Init.B0[3])& CRYP_CCM_CTR0_3);
+ ctr0[0] = (__REV(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0);
+ ctr0[1] = __REV(hcryp->Init.B0[1]);
+ ctr0[2] = __REV(hcryp->Init.B0[2]);
+ ctr0[3] = (__REV(hcryp->Init.B0[3])& CRYP_CCM_CTR0_3);
- hcryp->Instance->DINR = __REV(*(uint32_t*)(ctr0addr));
- ctr0addr+=4U;
- hcryp->Instance->DINR = __REV(*(uint32_t*)(ctr0addr));
- ctr0addr+=4U;
- hcryp->Instance->DINR = __REV(*(uint32_t*)(ctr0addr));
- ctr0addr+=4U;
- hcryp->Instance->DINR = __REV(*(uint32_t*)(ctr0addr));
+ hcryp->Instance->DINR = __REV(*(uint32_t *)(ctr0addr));
+ ctr0addr += 4U;
+ hcryp->Instance->DINR = __REV(*(uint32_t *)(ctr0addr));
+ ctr0addr += 4U;
+ hcryp->Instance->DINR = __REV(*(uint32_t *)(ctr0addr));
+ ctr0addr += 4U;
+ hcryp->Instance->DINR = __REV(*(uint32_t *)(ctr0addr));
}
- else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
{
- ctr0[0]= ( __ROR((hcryp->Init.B0[0]), 16U)& CRYP_CCM_CTR0_0);
- ctr0[1]= __ROR((hcryp->Init.B0[1]), 16U);
- ctr0[2]= __ROR((hcryp->Init.B0[2]), 16U);
- ctr0[3]= ( __ROR((hcryp->Init.B0[3]), 16U)& CRYP_CCM_CTR0_3);
+ ctr0[0] = (__ROR((hcryp->Init.B0[0]), 16U)& CRYP_CCM_CTR0_0);
+ ctr0[1] = __ROR((hcryp->Init.B0[1]), 16U);
+ ctr0[2] = __ROR((hcryp->Init.B0[2]), 16U);
+ ctr0[3] = (__ROR((hcryp->Init.B0[3]), 16U)& CRYP_CCM_CTR0_3);
- hcryp->Instance->DINR = __ROR(*(uint32_t*)(ctr0addr), 16U);
- ctr0addr+=4U;
- hcryp->Instance->DINR = __ROR(*(uint32_t*)(ctr0addr), 16U);
- ctr0addr+=4U;
- hcryp->Instance->DINR = __ROR(*(uint32_t*)(ctr0addr), 16U);
- ctr0addr+=4U;
- hcryp->Instance->DINR = __ROR(*(uint32_t*)(ctr0addr), 16U);
+ hcryp->Instance->DINR = __ROR(*(uint32_t *)(ctr0addr), 16U);
+ ctr0addr += 4U;
+ hcryp->Instance->DINR = __ROR(*(uint32_t *)(ctr0addr), 16U);
+ ctr0addr += 4U;
+ hcryp->Instance->DINR = __ROR(*(uint32_t *)(ctr0addr), 16U);
+ ctr0addr += 4U;
+ hcryp->Instance->DINR = __ROR(*(uint32_t *)(ctr0addr), 16U);
}
- else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
{
- ctr0[0]=(__RBIT(hcryp->Init.B0[0])& CRYP_CCM_CTR0_0);
- ctr0[1]=__RBIT(hcryp->Init.B0[1]);
- ctr0[2]=__RBIT(hcryp->Init.B0[2]);
- ctr0[3]=(__RBIT(hcryp->Init.B0[3])& CRYP_CCM_CTR0_3);
+ ctr0[0] = (__RBIT(hcryp->Init.B0[0])& CRYP_CCM_CTR0_0);
+ ctr0[1] = __RBIT(hcryp->Init.B0[1]);
+ ctr0[2] = __RBIT(hcryp->Init.B0[2]);
+ ctr0[3] = (__RBIT(hcryp->Init.B0[3])& CRYP_CCM_CTR0_3);
- hcryp->Instance->DINR = __RBIT(*(uint32_t*)(ctr0addr));
- ctr0addr+=4U;
- hcryp->Instance->DINR = __RBIT(*(uint32_t*)(ctr0addr));
- ctr0addr+=4U;
- hcryp->Instance->DINR = __RBIT(*(uint32_t*)(ctr0addr));
- ctr0addr+=4U;
- hcryp->Instance->DINR = __RBIT(*(uint32_t*)(ctr0addr));
+ hcryp->Instance->DINR = __RBIT(*(uint32_t *)(ctr0addr));
+ ctr0addr += 4U;
+ hcryp->Instance->DINR = __RBIT(*(uint32_t *)(ctr0addr));
+ ctr0addr += 4U;
+ hcryp->Instance->DINR = __RBIT(*(uint32_t *)(ctr0addr));
+ ctr0addr += 4U;
+ hcryp->Instance->DINR = __RBIT(*(uint32_t *)(ctr0addr));
}
else
{
- ctr0[0]=(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0;
- ctr0[1]=hcryp->Init.B0[1];
- ctr0[2]=hcryp->Init.B0[2];
- ctr0[3]=hcryp->Init.B0[3] & CRYP_CCM_CTR0_3;
+ ctr0[0] = (hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0;
+ ctr0[1] = hcryp->Init.B0[1];
+ ctr0[2] = hcryp->Init.B0[2];
+ ctr0[3] = hcryp->Init.B0[3] & CRYP_CCM_CTR0_3;
- hcryp->Instance->DINR = *(uint32_t*)(ctr0addr);
- ctr0addr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(ctr0addr);
- ctr0addr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(ctr0addr);
- ctr0addr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(ctr0addr);
+ hcryp->Instance->DINR = *(uint32_t *)(ctr0addr);
+ ctr0addr += 4U;
+ hcryp->Instance->DINR = *(uint32_t *)(ctr0addr);
+ ctr0addr += 4U;
+ hcryp->Instance->DINR = *(uint32_t *)(ctr0addr);
+ ctr0addr += 4U;
+ hcryp->Instance->DINR = *(uint32_t *)(ctr0addr);
}
/* Wait for CCF flag to be raised */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP peripheral Clock */
__HAL_CRYP_DISABLE(hcryp);
@@ -565,13 +565,13 @@
}
/* Read the authentication TAG in the output FIFO */
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr += 4U;
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr += 4U;
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr += 4U;
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
@@ -594,7 +594,7 @@
return HAL_ERROR;
}
/* Return function status */
- return HAL_OK;
+ return HAL_OK;
}
/**
@@ -603,12 +603,12 @@
#if defined (AES)
/** @defgroup CRYPEx_Exported_Functions_Group2 Key Derivation functions
- * @brief AutoKeyDerivation functions
- *
+ * @brief AutoKeyDerivation functions
+ *
@verbatim
==============================================================================
##### Key Derivation functions #####
- ==============================================================================
+ ==============================================================================
[..] This section provides functions allowing to Enable or Disable the
the AutoKeyDerivation parameter in CRYP_HandleTypeDef structure
These function are allowed only in TinyAES IP.
@@ -624,15 +624,15 @@
*/
void HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp)
{
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
hcryp->AutoKeyDerivation = ENABLE;
}
else
{
/* Busy error code field */
- hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
- }
+ hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
+ }
}
/**
* @brief AES disable key derivation functions
@@ -641,22 +641,22 @@
*/
void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp)
{
- if(hcryp->State == HAL_CRYP_STATE_READY)
+ if (hcryp->State == HAL_CRYP_STATE_READY)
{
hcryp->AutoKeyDerivation = DISABLE;
}
else
{
/* Busy error code field */
- hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
- }
+ hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
+ }
}
/**
* @}
*/
-#endif /* AES */
+#endif /* AES */
#endif /* HAL_CRYP_MODULE_ENABLED */
/**
diff --git a/Src/stm32f7xx_hal_dcmi.c b/Src/stm32f7xx_hal_dcmi.c
index 1f8dcdc..29c22f6 100644
--- a/Src/stm32f7xx_hal_dcmi.c
+++ b/Src/stm32f7xx_hal_dcmi.c
@@ -3,13 +3,13 @@
* @file stm32f7xx_hal_dcmi.c
* @author MCD Application Team
* @brief DCMI HAL module driver
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Digital Camera Interface (DCMI) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State and Error functions
- *
+ * + Peripheral Control functions
+ * + Peripheral State and Error functions
+ *
@verbatim
==============================================================================
##### How to use this driver #####
@@ -23,18 +23,18 @@
(#) Program the required configuration through following parameters:
horizontal and vertical polarity, pixel clock polarity, Capture Rate,
- Synchronization Mode, code of the frame delimiter and data width
+ Synchronization Mode, code of the frame delimiter and data width
using HAL_DCMI_Init() function.
(#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR
register to the destination memory buffer.
(#) Program the required configuration through following parameters:
- DCMI mode, destination memory Buffer address and the data length
+ DCMI mode, destination memory Buffer address and the data length
and enable capture using HAL_DCMI_Start_DMA() function.
(#) Optionally, configure and Enable the CROP feature to select a rectangular
- window from the received image using HAL_DCMI_ConfigCrop()
+ window from the received image using HAL_DCMI_ConfigCrop()
and HAL_DCMI_EnableCROP() functions
(#) The capture can be stopped using HAL_DCMI_Stop() function.
@@ -42,10 +42,10 @@
(#) To control DCMI state you can use the function HAL_DCMI_GetState().
*** DCMI HAL driver macros list ***
- =============================================
+ =============================================
[..]
Below the list of most used macros in DCMI HAL driver.
-
+
(+) __HAL_DCMI_ENABLE: Enable the DCMI peripheral.
(+) __HAL_DCMI_DISABLE: Disable the DCMI peripheral.
(+) __HAL_DCMI_GET_FLAG: Get the DCMI pending flags.
@@ -53,10 +53,10 @@
(+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts.
(+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts.
(+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not.
-
- [..]
+
+ [..]
(@) You can refer to the DCMI HAL driver header file for more useful macros
-
+
*** Callback registration ***
=============================
@@ -106,7 +106,7 @@
When the compilation define USE_HAL_DCMI_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
-
+
@endverbatim
******************************************************************************
* @attention
@@ -155,18 +155,18 @@
/** @defgroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and Configuration functions #####
- ===============================================================================
+ ===============================================================================
[..] This section provides functions allowing to:
(+) Initialize and configure the DCMI
- (+) De-initialize the DCMI
+ (+) De-initialize the DCMI
@endverbatim
* @{
*/
-
+
/**
* @brief Initializes the DCMI according to the specified
* parameters in the DCMI_InitTypeDef and create the associated handle.
@@ -175,13 +175,13 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
-{
+{
/* Check the DCMI peripheral state */
- if(hdcmi == NULL)
+ if (hdcmi == NULL)
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
-
+
/* Check function parameters */
assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));
assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));
@@ -192,53 +192,74 @@
assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode));
assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode));
+#ifdef DCMI_CR_BSM
assert_param(IS_DCMI_BYTE_SELECT_MODE(hdcmi->Init.ByteSelectMode));
assert_param(IS_DCMI_BYTE_SELECT_START(hdcmi->Init.ByteSelectStart));
assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode));
assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart));
-
- if(hdcmi->State == HAL_DCMI_STATE_RESET)
+#endif
+
+ if (hdcmi->State == HAL_DCMI_STATE_RESET)
{
- /* Init the DCMI Callback settings */
+ /* Init the DCMI Callback settings */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
- hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */
- hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */
- hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */
- hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */
-
- if(hdcmi->MspInitCallback == NULL)
+ hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */
+ hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */
+ hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */
+ hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */
+
+ if (hdcmi->MspInitCallback == NULL)
{
/* Legacy weak MspInit Callback */
hdcmi->MspInitCallback = HAL_DCMI_MspInit;
}
/* Initialize the low level hardware (MSP) */
hdcmi->MspInitCallback(hdcmi);
-#else
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_DCMI_MspInit(hdcmi);
#endif /* (USE_HAL_DCMI_REGISTER_CALLBACKS) */
- }
-
+ }
+
/* Change the DCMI state */
- hdcmi->State = HAL_DCMI_STATE_BUSY;
- /* Configures the HS, VS, DE and PC polarity */
- hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 |\
- DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG |\
- DCMI_CR_ESS | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS |\
+ hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+#ifdef DCMI_CR_BSM
+ if (hdcmi->Init.ExtendedDataMode != DCMI_EXTEND_DATA_8B)
+ {
+ /* Byte select mode must be programmed to the reset value if the extended mode
+ is not set to 8-bit data capture on every pixel clock */
+ hdcmi->Init.ByteSelectMode = DCMI_BSM_ALL;
+ }
+#endif
+ /* Configures the HS, VS, DE and PC polarity */
+#ifdef DCMI_CR_BSM
+ hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 | \
+ DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG | \
+ DCMI_CR_ESS | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS | \
DCMI_CR_LSM | DCMI_CR_OELS);
- hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate |\
- hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity |\
- hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode |\
- hdcmi->Init.JPEGMode | hdcmi->Init.ByteSelectMode |\
- hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode |\
- hdcmi->Init.LineSelectStart);
-
- if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
+ hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate | \
+ hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity | \
+ hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode | \
+ hdcmi->Init.JPEGMode | hdcmi->Init.ByteSelectMode | \
+ hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode | \
+ hdcmi->Init.LineSelectStart);
+#else
+ hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 | \
+ DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG);
+
+ hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate | \
+ hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity | \
+ hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode | \
+ hdcmi->Init.JPEGMode);
+#endif
+
+ if (hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
{
- hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) |\
- ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_ESCR_LSC_Pos)|\
- ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_ESCR_LEC_Pos) |\
+ hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) | \
+ ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_ESCR_LSC_Pos) | \
+ ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_ESCR_LEC_Pos) | \
((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << DCMI_ESCR_FEC_Pos));
}
@@ -248,7 +269,7 @@
/* Update error code */
hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
-
+
/* Initialize the DCMI state*/
hdcmi->State = HAL_DCMI_STATE_READY;
@@ -265,8 +286,8 @@
HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
{
-#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
- if(hdcmi->MspDeInitCallback == NULL)
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+ if (hdcmi->MspDeInitCallback == NULL)
{
hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
}
@@ -295,14 +316,14 @@
* the configuration information for DCMI.
* @retval None
*/
-__weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi)
+__weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef *hdcmi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcmi);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DCMI_MspInit could be implemented in the user file
- */
+ */
}
/**
@@ -311,11 +332,11 @@
* the configuration information for DCMI.
* @retval None
*/
-__weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
+__weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef *hdcmi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcmi);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DCMI_MspDeInit could be implemented in the user file
*/
@@ -324,15 +345,15 @@
/**
* @}
*/
-/** @defgroup DCMI_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
+/** @defgroup DCMI_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
*
-@verbatim
+@verbatim
===============================================================================
##### IO operation functions #####
- ===============================================================================
+ ===============================================================================
[..] This section provides functions allowing to:
- (+) Configure destination address and data length and
+ (+) Configure destination address and data length and
Enables DCMI DMA request and enables DCMI capture
(+) Stop the DCMI capture.
(+) Handles DCMI interrupt request.
@@ -342,7 +363,7 @@
*/
/**
- * @brief Enables DCMI DMA request and enables DCMI capture
+ * @brief Enables DCMI DMA request and enables DCMI capture
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @param DCMI_Mode DCMI capture mode snapshot or continuous grab.
@@ -350,8 +371,8 @@
* @param Length The length of capture to be transferred.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
-{
+HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
+{
/* Initialize the second memory address */
uint32_t SecondMemAddress = 0;
@@ -360,16 +381,16 @@
/* Process Locked */
__HAL_LOCK(hdcmi);
-
+
/* Lock the DCMI peripheral state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
/* Enable DCMI by setting DCMIEN bit */
__HAL_DCMI_ENABLE(hdcmi);
-
+
/* Configure the DCMI Mode */
hdcmi->Instance->CR &= ~(DCMI_CR_CM);
- hdcmi->Instance->CR |= (uint32_t)(DCMI_Mode);
+ hdcmi->Instance->CR |= (uint32_t)(DCMI_Mode);
/* Set the DMA memory0 conversion complete callback */
hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAXferCplt;
@@ -380,43 +401,51 @@
/* Set the dma abort callback */
hdcmi->DMA_Handle->XferAbortCallback = NULL;
- /* Reset transfer counters value */
+ /* Reset transfer counters value */
hdcmi->XferCount = 0;
hdcmi->XferTransferNumber = 0;
-
- if(Length <= 0xFFFF)
+ hdcmi->XferSize = 0;
+ hdcmi->pBuffPtr = 0;
+
+ if (Length <= 0xFFFFU)
{
/* Enable the DMA Stream */
- HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length);
+ if (HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
}
else /* DCMI_DOUBLE_BUFFER Mode */
{
/* Set the DMA memory1 conversion complete callback */
- hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAXferCplt;
+ hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAXferCplt;
/* Initialize transfer parameters */
hdcmi->XferCount = 1;
hdcmi->XferSize = Length;
hdcmi->pBuffPtr = pData;
-
+
/* Get the number of buffer */
- while(hdcmi->XferSize > 0xFFFF)
+ while (hdcmi->XferSize > 0xFFFFU)
{
- hdcmi->XferSize = (hdcmi->XferSize/2);
- hdcmi->XferCount = hdcmi->XferCount*2;
+ hdcmi->XferSize = (hdcmi->XferSize / 2U);
+ hdcmi->XferCount = hdcmi->XferCount * 2U;
}
/* Update DCMI counter and transfer number*/
- hdcmi->XferCount = (hdcmi->XferCount - 2);
+ hdcmi->XferCount = (hdcmi->XferCount - 2U);
hdcmi->XferTransferNumber = hdcmi->XferCount;
/* Update second memory address */
- SecondMemAddress = (uint32_t)(pData + (4*hdcmi->XferSize));
+ SecondMemAddress = (uint32_t)(pData + (4 * hdcmi->XferSize));
/* Start DMA multi buffer transfer */
- HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize);
+ if (HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
}
-
+
/* Enable Capture */
hdcmi->Instance->CR |= DCMI_CR_CAPTURE;
@@ -428,19 +457,19 @@
}
/**
- * @brief Disable DCMI DMA request and Disable DCMI capture
+ * @brief Disable DCMI DMA request and Disable DCMI capture
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
- * the configuration information for DCMI.
- * @retval HAL status
+ * the configuration information for DCMI.
+ * @retval HAL status
*/
-HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
+HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef *hdcmi)
{
- register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock /8/1000);
+ register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U);
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hdcmi);
-
+
/* Lock the DCMI peripheral state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
@@ -450,22 +479,22 @@
/* Check if the DCMI capture effectively disabled */
do
{
- if (count-- == 0)
+ if (count-- == 0U)
{
/* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
-
+
status = HAL_TIMEOUT;
break;
- }
+ }
}
- while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0);
+ while ((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U);
/* Disable the DCMI */
__HAL_DCMI_DISABLE(hdcmi);
/* Disable the DMA */
- HAL_DMA_Abort(hdcmi->DMA_Handle);
+ (void)HAL_DMA_Abort(hdcmi->DMA_Handle);
/* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_NONE;
@@ -481,20 +510,20 @@
}
/**
- * @brief Suspend DCMI capture
+ * @brief Suspend DCMI capture
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
- * the configuration information for DCMI.
- * @retval HAL status
+ * the configuration information for DCMI.
+ * @retval HAL status
*/
-HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi)
+HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef *hdcmi)
{
- register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock /8/1000);
+ register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U);
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hdcmi);
- if(hdcmi->State == HAL_DCMI_STATE_BUSY)
+ if (hdcmi->State == HAL_DCMI_STATE_BUSY)
{
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_SUSPENDED;
@@ -505,49 +534,49 @@
/* Check if the DCMI capture effectively disabled */
do
{
- if (count-- == 0)
- {
+ if (count-- == 0U)
+ {
/* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
-
+
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_READY;
-
+
status = HAL_TIMEOUT;
break;
}
}
- while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0);
- }
+ while ((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U);
+ }
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
-
+
/* Return function status */
return status;
}
/**
- * @brief Resume DCMI capture
+ * @brief Resume DCMI capture
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
- * the configuration information for DCMI.
- * @retval HAL status
+ * the configuration information for DCMI.
+ * @retval HAL status
*/
-HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi)
+HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef *hdcmi)
{
/* Process locked */
__HAL_LOCK(hdcmi);
-
- if(hdcmi->State == HAL_DCMI_STATE_SUSPENDED)
+
+ if (hdcmi->State == HAL_DCMI_STATE_SUSPENDED)
{
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
-
+
/* Disable Capture */
hdcmi->Instance->CR |= DCMI_CR_CAPTURE;
- }
+ }
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
-
+
/* Return function status */
return HAL_OK;
}
@@ -559,96 +588,99 @@
* @retval None
*/
void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
-{
+{
uint32_t isr_value = READ_REG(hdcmi->Instance->MISR);
-
+
/* Synchronization error interrupt management *******************************/
- if((isr_value & DCMI_FLAG_ERRRI) == DCMI_FLAG_ERRRI)
+ if ((isr_value & DCMI_FLAG_ERRRI) == DCMI_FLAG_ERRRI)
{
/* Clear the Synchronization error flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI);
-
+
/* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC;
-
+
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_ERROR;
-
+
/* Set the synchronization error callback */
hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
-
+
/* Abort the DMA Transfer */
- HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
+ (void)HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
}
/* Overflow interrupt management ********************************************/
- if((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI)
+ if ((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI)
{
/* Clear the Overflow flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVRRI);
-
+
/* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVR;
-
+
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_ERROR;
-
+
/* Set the overflow callback */
hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
-
+
/* Abort the DMA Transfer */
- HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
+ if (HAL_DMA_Abort_IT(hdcmi->DMA_Handle) != HAL_OK)
+ {
+ DCMI_DMAError(hdcmi->DMA_Handle);
+ }
}
/* Line Interrupt management ************************************************/
- if((isr_value & DCMI_FLAG_LINERI) == DCMI_FLAG_LINERI)
+ if ((isr_value & DCMI_FLAG_LINERI) == DCMI_FLAG_LINERI)
{
- /* Clear the Line interrupt flag */
+ /* Clear the Line interrupt flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);
-
+
/* Line interrupt Callback */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
/*Call registered DCMI line event callback*/
hdcmi->LineEventCallback(hdcmi);
-#else
+#else
HAL_DCMI_LineEventCallback(hdcmi);
-#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
}
/* VSYNC interrupt management ***********************************************/
- if((isr_value & DCMI_FLAG_VSYNCRI) == DCMI_FLAG_VSYNCRI)
+ if ((isr_value & DCMI_FLAG_VSYNCRI) == DCMI_FLAG_VSYNCRI)
{
/* Clear the VSYNC flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);
-
+
/* VSYNC Callback */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
/*Call registered DCMI vsync event callback*/
hdcmi->VsyncEventCallback(hdcmi);
-#else
+#else
HAL_DCMI_VsyncEventCallback(hdcmi);
-#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
}
/* FRAME interrupt management ***********************************************/
- if((isr_value & DCMI_FLAG_FRAMERI) == DCMI_FLAG_FRAMERI)
+ if ((isr_value & DCMI_FLAG_FRAMERI) == DCMI_FLAG_FRAMERI)
{
/* When snapshot mode, disable Vsync, Error and Overrun interrupts */
- if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
- {
+ if ((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
+ {
/* Disable the Line, Vsync, Error and Overrun interrupts */
__HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
}
-
+
/* Disable the Frame interrupt */
__HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME);
-
+
/* Clear the End of Frame flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI);
-
+
/* Frame Callback */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
/*Call registered DCMI frame event callback*/
hdcmi->FrameEventCallback(hdcmi);
-#else
+#else
HAL_DCMI_FrameEventCallback(hdcmi);
-#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
}
}
@@ -662,7 +694,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcmi);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DCMI_ErrorCallback could be implemented in the user file
*/
@@ -691,7 +723,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcmi);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DCMI_VsyncEventCallback could be implemented in the user file
*/
@@ -707,7 +739,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcmi);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DCMI_FrameEventCallback could be implemented in the user file
*/
@@ -718,12 +750,12 @@
*/
/** @defgroup DCMI_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
+ * @brief Peripheral Control functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral Control functions #####
- ===============================================================================
+ ===============================================================================
[..] This section provides functions allowing to:
(+) Configure the CROP feature.
(+) Enable/Disable the CROP feature.
@@ -756,7 +788,7 @@
assert_param(IS_DCMI_WINDOW_HEIGHT(Y0));
assert_param(IS_DCMI_WINDOW_COORDINATE(XSize));
assert_param(IS_DCMI_WINDOW_COORDINATE(YSize));
-
+
/* Configure CROP */
hdcmi->Instance->CWSIZER = (XSize | (YSize << DCMI_CWSIZE_VLINE_Pos));
hdcmi->Instance->CWSTRTR = (X0 | (Y0 << DCMI_CWSTRT_VST_Pos));
@@ -785,15 +817,15 @@
hdcmi->State = HAL_DCMI_STATE_BUSY;
/* Disable DCMI Crop feature */
- hdcmi->Instance->CR &= ~(uint32_t)DCMI_CR_CROP;
+ hdcmi->Instance->CR &= ~(uint32_t)DCMI_CR_CROP;
/* Change the DCMI state*/
- hdcmi->State = HAL_DCMI_STATE_READY;
+ hdcmi->State = HAL_DCMI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
- return HAL_OK;
+ return HAL_OK;
}
/**
@@ -819,7 +851,38 @@
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
- return HAL_OK;
+ return HAL_OK;
+}
+
+/**
+ * @brief Set embedded synchronization delimiters unmasks.
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @param SyncUnmask pointer to a DCMI_SyncUnmaskTypeDef structure that contains
+ * the embedded synchronization delimiters unmasks.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask)
+{
+ /* Process Locked */
+ __HAL_LOCK(hdcmi);
+
+ /* Lock the DCMI peripheral state */
+ hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+ /* Write DCMI embedded synchronization unmask register */
+ hdcmi->Instance->ESUR = (((uint32_t)SyncUnmask->FrameStartUnmask) | \
+ ((uint32_t)SyncUnmask->LineStartUnmask << DCMI_ESUR_LSU_Pos) | \
+ ((uint32_t)SyncUnmask->LineEndUnmask << DCMI_ESUR_LEU_Pos) | \
+ ((uint32_t)SyncUnmask->FrameEndUnmask << DCMI_ESUR_FEU_Pos));
+
+ /* Change the DCMI state*/
+ hdcmi->State = HAL_DCMI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdcmi);
+
+ return HAL_OK;
}
/**
@@ -827,20 +890,20 @@
*/
/** @defgroup DCMI_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
+ * @brief Peripheral State functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
- ===============================================================================
+ ===============================================================================
[..]
This subsection provides functions allowing to
(+) Check the DCMI state.
- (+) Get the specific DCMI error flag.
+ (+) Get the specific DCMI error flag.
@endverbatim
* @{
- */
+ */
/**
* @brief Return the DCMI state
@@ -848,7 +911,7 @@
* the configuration information for DCMI.
* @retval HAL state
*/
-HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi)
+HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi)
{
return hdcmi->State;
}
@@ -876,70 +939,70 @@
HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
-
- if(pCallback == NULL)
+
+ if (pCallback == NULL)
{
/* update the error code */
- hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
else
{
- if(hdcmi->State == HAL_DCMI_STATE_READY)
+ if (hdcmi->State == HAL_DCMI_STATE_READY)
{
switch (CallbackID)
{
- case HAL_DCMI_FRAME_EVENT_CB_ID :
- hdcmi->FrameEventCallback = pCallback;
- break;
-
- case HAL_DCMI_VSYNC_EVENT_CB_ID :
- hdcmi->VsyncEventCallback = pCallback;
- break;
-
- case HAL_DCMI_LINE_EVENT_CB_ID :
- hdcmi->LineEventCallback = pCallback;
- break;
-
- case HAL_DCMI_ERROR_CB_ID :
- hdcmi->ErrorCallback = pCallback;
- break;
-
- case HAL_DCMI_MSPINIT_CB_ID :
- hdcmi->MspInitCallback = pCallback;
- break;
-
- case HAL_DCMI_MSPDEINIT_CB_ID :
- hdcmi->MspDeInitCallback = pCallback;
- break;
-
- default :
- /* Return error status */
- status = HAL_ERROR;
- break;
+ case HAL_DCMI_FRAME_EVENT_CB_ID :
+ hdcmi->FrameEventCallback = pCallback;
+ break;
+
+ case HAL_DCMI_VSYNC_EVENT_CB_ID :
+ hdcmi->VsyncEventCallback = pCallback;
+ break;
+
+ case HAL_DCMI_LINE_EVENT_CB_ID :
+ hdcmi->LineEventCallback = pCallback;
+ break;
+
+ case HAL_DCMI_ERROR_CB_ID :
+ hdcmi->ErrorCallback = pCallback;
+ break;
+
+ case HAL_DCMI_MSPINIT_CB_ID :
+ hdcmi->MspInitCallback = pCallback;
+ break;
+
+ case HAL_DCMI_MSPDEINIT_CB_ID :
+ hdcmi->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(hdcmi->State == HAL_DCMI_STATE_RESET)
+ else if (hdcmi->State == HAL_DCMI_STATE_RESET)
{
switch (CallbackID)
{
- case HAL_DCMI_MSPINIT_CB_ID :
- hdcmi->MspInitCallback = pCallback;
- break;
-
- case HAL_DCMI_MSPDEINIT_CB_ID :
- hdcmi->MspDeInitCallback = pCallback;
- break;
-
- default :
- /* update the error code */
- hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
- }
- }
+ case HAL_DCMI_MSPINIT_CB_ID :
+ hdcmi->MspInitCallback = pCallback;
+ break;
+
+ case HAL_DCMI_MSPDEINIT_CB_ID :
+ hdcmi->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* update the error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
else
{
/* update the error code */
@@ -948,7 +1011,7 @@
status = HAL_ERROR;
}
}
-
+
return status;
}
@@ -961,63 +1024,63 @@
HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
-
- if(hdcmi->State == HAL_DCMI_STATE_READY)
+
+ if (hdcmi->State == HAL_DCMI_STATE_READY)
{
switch (CallbackID)
{
- case HAL_DCMI_FRAME_EVENT_CB_ID :
- hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */
- break;
-
- case HAL_DCMI_VSYNC_EVENT_CB_ID :
- hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */
- break;
-
- case HAL_DCMI_LINE_EVENT_CB_ID :
- hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */
- break;
-
- case HAL_DCMI_ERROR_CB_ID :
- hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */
- break;
-
- case HAL_DCMI_MSPINIT_CB_ID :
- hdcmi->MspInitCallback = HAL_DCMI_MspInit;
- break;
-
- case HAL_DCMI_MSPDEINIT_CB_ID :
- hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
- break;
-
- default :
- /* update the error code */
- hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_DCMI_FRAME_EVENT_CB_ID :
+ hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */
+ break;
+
+ case HAL_DCMI_VSYNC_EVENT_CB_ID :
+ hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */
+ break;
+
+ case HAL_DCMI_LINE_EVENT_CB_ID :
+ hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */
+ break;
+
+ case HAL_DCMI_ERROR_CB_ID :
+ hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_DCMI_MSPINIT_CB_ID :
+ hdcmi->MspInitCallback = HAL_DCMI_MspInit;
+ break;
+
+ case HAL_DCMI_MSPDEINIT_CB_ID :
+ hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
+ break;
+
+ default :
+ /* update the error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(hdcmi->State == HAL_DCMI_STATE_RESET)
+ else if (hdcmi->State == HAL_DCMI_STATE_RESET)
{
switch (CallbackID)
{
- case HAL_DCMI_MSPINIT_CB_ID :
- hdcmi->MspInitCallback = HAL_DCMI_MspInit;
- break;
-
- case HAL_DCMI_MSPDEINIT_CB_ID :
- hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
- break;
-
- default :
- /* update the error code */
- hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
- }
- }
+ case HAL_DCMI_MSPINIT_CB_ID :
+ hdcmi->MspInitCallback = HAL_DCMI_MspInit;
+ break;
+
+ case HAL_DCMI_MSPDEINIT_CB_ID :
+ hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
+ break;
+
+ default :
+ /* update the error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
else
{
/* update the error code */
@@ -1025,7 +1088,7 @@
/* update return status */
status = HAL_ERROR;
}
-
+
return status;
}
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
@@ -1037,96 +1100,96 @@
/** @defgroup DCMI_Private_Functions DCMI Private Functions
* @{
*/
- /**
- * @brief DMA conversion complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
+/**
+* @brief DMA conversion complete callback.
+* @param hdma pointer to a DMA_HandleTypeDef structure that contains
+* the configuration information for the specified DMA module.
+* @retval None
+*/
static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
{
uint32_t tmp = 0;
- DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ DCMI_HandleTypeDef *hdcmi = (DCMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- if(hdcmi->XferCount != 0)
+ if (hdcmi->XferCount != 0)
{
/* Update memory 0 address location */
tmp = ((hdcmi->DMA_Handle->Instance->CR) & DMA_SxCR_CT);
- if(((hdcmi->XferCount % 2) == 0) && (tmp != 0))
+ if (((hdcmi->XferCount % 2) == 0) && (tmp != 0))
{
tmp = hdcmi->DMA_Handle->Instance->M0AR;
- HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8*hdcmi->XferSize)), MEMORY0);
+ HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8 * hdcmi->XferSize)), MEMORY0);
hdcmi->XferCount--;
}
/* Update memory 1 address location */
- else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0)
+ else if ((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0)
{
tmp = hdcmi->DMA_Handle->Instance->M1AR;
- HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8*hdcmi->XferSize)), MEMORY1);
+ HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8 * hdcmi->XferSize)), MEMORY1);
hdcmi->XferCount--;
}
}
/* Update memory 0 address location */
- else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) != 0)
+ else if ((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) != 0)
{
hdcmi->DMA_Handle->Instance->M0AR = hdcmi->pBuffPtr;
}
/* Update memory 1 address location */
- else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0)
+ else if ((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0)
{
tmp = hdcmi->pBuffPtr;
- hdcmi->DMA_Handle->Instance->M1AR = (tmp + (4*hdcmi->XferSize));
+ hdcmi->DMA_Handle->Instance->M1AR = (tmp + (4 * hdcmi->XferSize));
hdcmi->XferCount = hdcmi->XferTransferNumber;
}
/* Check if the frame is transferred */
- if(hdcmi->XferCount == hdcmi->XferTransferNumber)
+ if (hdcmi->XferCount == hdcmi->XferTransferNumber)
{
/* Enable the Frame interrupt */
__HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
-
+
/* When snapshot mode, set dcmi state to ready */
- if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
- {
- hdcmi->State= HAL_DCMI_STATE_READY;
+ if ((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
+ {
+ hdcmi->State = HAL_DCMI_STATE_READY;
}
- }
+ }
}
/**
- * @brief DMA error callback
+ * @brief DMA error callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
{
- DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- if(hdcmi->DMA_Handle->ErrorCode != HAL_DMA_ERROR_FE)
+ DCMI_HandleTypeDef *hdcmi = (DCMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdcmi->DMA_Handle->ErrorCode != HAL_DMA_ERROR_FE)
{
/* Initialize the DCMI state*/
hdcmi->State = HAL_DCMI_STATE_READY;
-
+
/* Set DCMI Error Code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA;
}
/* DCMI error Callback */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
- /*Call registered DCMI error callback*/
- hdcmi->ErrorCallback(hdcmi);
-#else
- HAL_DCMI_ErrorCallback(hdcmi);
-#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+ /*Call registered DCMI error callback*/
+ hdcmi->ErrorCallback(hdcmi);
+#else
+ HAL_DCMI_ErrorCallback(hdcmi);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
}
/**
* @}
*/
-
+
/**
* @}
*/
diff --git a/Src/stm32f7xx_hal_dcmi_ex.c b/Src/stm32f7xx_hal_dcmi_ex.c
index f49ff0a..9a059b1 100644
--- a/Src/stm32f7xx_hal_dcmi_ex.c
+++ b/Src/stm32f7xx_hal_dcmi_ex.c
@@ -4,9 +4,9 @@
* @author MCD Application Team
* @brief Empty file; This file is no longer used to handle the Black&White
* feature. Its content is now moved to common files
- * (stm32f7xx_hal_dcmi.c/.h) as there's no device's dependency within F7
- * family. It's just kept for compatibility reasons.
- *
+ * (stm32f7xx_hal_dcmi.c/.h) as there's no device's dependency within
+ * this family. It's just kept for compatibility reasons.
+ *
******************************************************************************
* @attention
*
diff --git a/Src/stm32f7xx_hal_dfsdm.c b/Src/stm32f7xx_hal_dfsdm.c
index daeb1f9..dd253e5 100644
--- a/Src/stm32f7xx_hal_dfsdm.c
+++ b/Src/stm32f7xx_hal_dfsdm.c
@@ -157,23 +157,26 @@
*** Callback registration ***
=============================
-
+ [..]
The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use functions @ref HAL_DFSDM_Channel_RegisterCallback(),
- @ref HAL_DFSDM_Filter_RegisterCallback() or
- @ref HAL_DFSDM_Filter_RegisterAwdCallback() to register a user callback.
+ Use functions HAL_DFSDM_Channel_RegisterCallback(),
+ HAL_DFSDM_Filter_RegisterCallback() or
+ HAL_DFSDM_Filter_RegisterAwdCallback() to register a user callback.
- Function @ref HAL_DFSDM_Channel_RegisterCallback() allows to register
+ [..]
+ Function HAL_DFSDM_Channel_RegisterCallback() allows to register
following callbacks:
(+) CkabCallback : DFSDM channel clock absence detection callback.
(+) ScdCallback : DFSDM channel short circuit detection callback.
(+) MspInitCallback : DFSDM channel MSP init callback.
(+) MspDeInitCallback : DFSDM channel MSP de-init callback.
+ [..]
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- Function @ref HAL_DFSDM_Filter_RegisterCallback() allows to register
+ [..]
+ Function HAL_DFSDM_Filter_RegisterCallback() allows to register
following callbacks:
(+) RegConvCpltCallback : DFSDM filter regular conversion complete callback.
(+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback.
@@ -182,26 +185,33 @@
(+) ErrorCallback : DFSDM filter error callback.
(+) MspInitCallback : DFSDM filter MSP init callback.
(+) MspDeInitCallback : DFSDM filter MSP de-init callback.
+ [..]
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
+ [..]
For specific DFSDM filter analog watchdog callback use dedicated register callback:
- @ref HAL_DFSDM_Filter_RegisterAwdCallback().
+ HAL_DFSDM_Filter_RegisterAwdCallback().
- Use functions @ref HAL_DFSDM_Channel_UnRegisterCallback() or
- @ref HAL_DFSDM_Filter_UnRegisterCallback() to reset a callback to the default
+ [..]
+ Use functions HAL_DFSDM_Channel_UnRegisterCallback() or
+ HAL_DFSDM_Filter_UnRegisterCallback() to reset a callback to the default
weak function.
- @ref HAL_DFSDM_Channel_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ [..]
+ HAL_DFSDM_Channel_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
+ [..]
This function allows to reset following callbacks:
(+) CkabCallback : DFSDM channel clock absence detection callback.
(+) ScdCallback : DFSDM channel short circuit detection callback.
(+) MspInitCallback : DFSDM channel MSP init callback.
(+) MspDeInitCallback : DFSDM channel MSP de-init callback.
- @ref HAL_DFSDM_Filter_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ [..]
+ HAL_DFSDM_Filter_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
+ [..]
This function allows to reset following callbacks:
(+) RegConvCpltCallback : DFSDM filter regular conversion complete callback.
(+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback.
@@ -211,29 +221,34 @@
(+) MspInitCallback : DFSDM filter MSP init callback.
(+) MspDeInitCallback : DFSDM filter MSP de-init callback.
+ [..]
For specific DFSDM filter analog watchdog callback use dedicated unregister callback:
- @ref HAL_DFSDM_Filter_UnRegisterAwdCallback().
+ HAL_DFSDM_Filter_UnRegisterAwdCallback().
+ [..]
By default, after the call of init function and if the state is RESET
all callbacks are reset to the corresponding legacy weak functions:
- examples @ref HAL_DFSDM_ChannelScdCallback(), @ref HAL_DFSDM_FilterErrorCallback().
+ examples HAL_DFSDM_ChannelScdCallback(), HAL_DFSDM_FilterErrorCallback().
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak functions in the init and de-init only when these
callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the init and de-init keep and use
the user MspInit/MspDeInit callbacks (registered beforehand)
+ [..]
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the init/de-init.
In that case first register the MspInit/MspDeInit user callbacks using
- @ref HAL_DFSDM_Channel_RegisterCallback() or
- @ref HAL_DFSDM_Filter_RegisterCallback() before calling init or de-init function.
+ HAL_DFSDM_Channel_RegisterCallback() or
+ HAL_DFSDM_Filter_RegisterCallback() before calling init or de-init function.
+ [..]
When The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
diff --git a/Src/stm32f7xx_hal_exti.c b/Src/stm32f7xx_hal_exti.c
index 1d87be4..d4fe089 100644
--- a/Src/stm32f7xx_hal_exti.c
+++ b/Src/stm32f7xx_hal_exti.c
@@ -85,7 +85,6 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
-#include "stm32f7xx_hal_exti.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
@@ -105,7 +104,7 @@
#ifdef HAL_EXTI_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
-/* Private defines ------------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
@@ -144,6 +143,8 @@
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
@@ -154,37 +155,77 @@
/* Check parameters */
assert_param(IS_EXTI_LINE(pExtiConfig->Line));
assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
- assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
-
+
/* Assign line number to handle */
hexti->Line = pExtiConfig->Line;
-
- /* Clear EXTI line configuration */
- EXTI->IMR &= ~pExtiConfig->Line;
- EXTI->EMR &= ~pExtiConfig->Line;
-
- /* Select the Mode for the selected external interrupts */
- regval = (uint32_t)EXTI_BASE;
- regval += pExtiConfig->Mode;
- *(__IO uint32_t *) regval |= pExtiConfig->Line;
-
- /* Clear Rising Falling edge configuration */
- EXTI->RTSR &= ~pExtiConfig->Line;
- EXTI->FTSR &= ~pExtiConfig->Line;
-
- /* Select the trigger for the selected external interrupts */
- if (pExtiConfig->Trigger == EXTI_TRIGGER_RISING_FALLING)
+
+ /* Compute line mask */
+ linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+ maskline = (1uL << linepos);
+
+ /* Configure triggers for configurable lines */
+ if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
{
- /* Rising Falling edge */
- EXTI->RTSR |= pExtiConfig->Line;
- EXTI->FTSR |= pExtiConfig->Line;
+ assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
+
+ /* Configure rising trigger */
+ /* Mask or set line */
+ if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
+ {
+ EXTI->RTSR |= maskline;
+ }
+ else
+ {
+ EXTI->RTSR &= ~maskline;
+ }
+
+ /* Configure falling trigger */
+ /* Mask or set line */
+ if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
+ {
+ EXTI->FTSR |= maskline;
+ }
+ else
+ {
+ EXTI->FTSR &= ~maskline;
+ }
+
+
+ /* Configure gpio port selection in case of gpio exti line */
+ if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+ {
+ assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
+ assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+ regval = SYSCFG->EXTICR[linepos >> 2u];
+ regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ SYSCFG->EXTICR[linepos >> 2u] = regval;
+ }
+ }
+
+ /* Configure interrupt mode : read current mode */
+ /* Mask or set line */
+ if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
+ {
+ EXTI->IMR |= maskline;
}
else
{
- regval = (uint32_t)EXTI_BASE;
- regval += pExtiConfig->Trigger;
- *(__IO uint32_t *) regval |= pExtiConfig->Line;
+ EXTI->IMR &= ~maskline;
}
+
+ /* Configure event mode : read current mode */
+ /* Mask or set line */
+ if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
+ {
+ EXTI->EMR |= maskline;
+ }
+ else
+ {
+ EXTI->EMR &= ~maskline;
+ }
+
return HAL_OK;
}
@@ -196,6 +237,10 @@
*/
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
+ uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
+
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
{
@@ -208,41 +253,67 @@
/* Store handle line number to configuration structure */
pExtiConfig->Line = hexti->Line;
- /* Get EXTI mode to configiguration structure */
- if ((EXTI->IMR & hexti->Line) == hexti->Line)
+ /* Compute line mask */
+ linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+ maskline = (1uL << linepos);
+
+ /* 1] Get core mode : interrupt */
+
+ /* Check if selected line is enable */
+ if ((EXTI->IMR & maskline) != 0x00u)
{
pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
}
- else if ((EXTI->EMR & hexti->Line) == hexti->Line)
- {
- pExtiConfig->Mode = EXTI_MODE_EVENT;
- }
else
{
- /* No MODE selected */
- pExtiConfig->Mode = 0x0Bu;
+ pExtiConfig->Mode = EXTI_MODE_NONE;
}
- /* Get EXTI Trigger to configiguration structure */
- if ((EXTI->RTSR & hexti->Line) == hexti->Line)
+ /* Get event mode */
+ /* Check if selected line is enable */
+ if ((EXTI->EMR & maskline) != 0x00u)
{
- if ((EXTI->FTSR & hexti->Line) == hexti->Line)
- {
- pExtiConfig->Trigger = EXTI_TRIGGER_RISING_FALLING;
- }
- else
+ pExtiConfig->Mode |= EXTI_MODE_EVENT;
+ }
+
+ /* 2] Get trigger for configurable lines : rising */
+ if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
+ {
+ /* Check if configuration of selected line is enable */
+ if ((EXTI->RTSR & maskline) != 0x00u)
{
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
}
- }
- else if ((EXTI->FTSR & hexti->Line) == hexti->Line)
- {
- pExtiConfig->Trigger = EXTI_TRIGGER_FALLING;
+ else
+ {
+ pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+ }
+
+ /* Get falling configuration */
+ /* Check if configuration of selected line is enable */
+ if ((EXTI->FTSR & maskline) != 0x00u)
+ {
+ pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
+ }
+
+ /* Get Gpio port selection for gpio lines */
+ if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+ {
+ assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+ regval = SYSCFG->EXTICR[linepos >> 2u];
+ pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
+ }
+ else
+ {
+ pExtiConfig->GPIOSel = 0x00u;
+ }
}
else
{
/* No Trigger selected */
- pExtiConfig->Trigger = 0x00u;
+ pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+ pExtiConfig->GPIOSel = 0x00u;
}
return HAL_OK;
@@ -255,6 +326,10 @@
*/
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
{
+ uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
+
/* Check null pointer */
if (hexti == NULL)
{
@@ -264,15 +339,32 @@
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
+ /* compute line mask */
+ linepos = (hexti->Line & EXTI_PIN_MASK);
+ maskline = (1uL << linepos);
+
/* 1] Clear interrupt mode */
- EXTI->IMR = (EXTI->IMR & ~hexti->Line);
+ EXTI->IMR = (EXTI->IMR & ~maskline);
/* 2] Clear event mode */
- EXTI->EMR = (EXTI->EMR & ~hexti->Line);
+ EXTI->EMR = (EXTI->EMR & ~maskline);
- /* 3] Clear triggers */
- EXTI->RTSR = (EXTI->RTSR & ~hexti->Line);
- EXTI->FTSR = (EXTI->FTSR & ~hexti->Line);
+ /* 3] Clear triggers in case of configurable lines */
+ if ((hexti->Line & EXTI_CONFIG) != 0x00u)
+ {
+ EXTI->RTSR = (EXTI->RTSR & ~maskline);
+ EXTI->FTSR = (EXTI->FTSR & ~maskline);
+
+ /* Get Gpio port selection for gpio lines */
+ if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
+ {
+ assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+ regval = SYSCFG->EXTICR[linepos >> 2u];
+ regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ SYSCFG->EXTICR[linepos >> 2u] = regval;
+ }
+ }
return HAL_OK;
}
@@ -352,17 +444,18 @@
*/
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
{
- __IO uint32_t *regaddr;
uint32_t regval;
+ uint32_t maskline;
+
+ /* Compute line mask */
+ maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
/* Get pending bit */
- regaddr = (&EXTI->PR);
- regval = (*regaddr & hexti->Line);
-
+ regval = (EXTI->PR & maskline);
if (regval != 0x00u)
{
/* Clear pending bit */
- *regaddr = hexti->Line;
+ EXTI->PR = maskline;
/* Call callback */
if (hexti->PendingCallback != NULL)
@@ -383,19 +476,21 @@
*/
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
- __IO uint32_t *regaddr;
uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
+ assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
- /* Get pending bit */
- regaddr = &EXTI->PR;
+ /* Compute line mask */
+ linepos = (hexti->Line & EXTI_PIN_MASK);
+ maskline = (1uL << linepos);
/* return 1 if bit is set else 0 */
- regval = ((*regaddr & hexti->Line) >> POSITION_VAL(hexti->Line));
-
+ regval = ((EXTI->PR & maskline) >> linepos);
return regval;
}
@@ -410,12 +505,18 @@
*/
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
+ uint32_t maskline;
+
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
+ assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
-
+
+ /* Compute line mask */
+ maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
/* Clear Pending bit */
- EXTI->PR = hexti->Line;
+ EXTI->PR = maskline;
}
/**
@@ -425,10 +526,17 @@
*/
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
{
+ uint32_t maskline;
+
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
+ assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
- EXTI->SWIER = hexti->Line;
+ /* Compute line mask */
+ maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+ /* Generate Software interrupt */
+ EXTI->SWIER = maskline;
}
/**
diff --git a/Src/stm32f7xx_hal_gpio.c b/Src/stm32f7xx_hal_gpio.c
index 02b729b..75e4b5b 100644
--- a/Src/stm32f7xx_hal_gpio.c
+++ b/Src/stm32f7xx_hal_gpio.c
@@ -190,25 +190,6 @@
if(iocurrent == ioposition)
{
/*--------------------- GPIO Mode Configuration ------------------------*/
- /* In case of Alternate function mode selection */
- if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- {
- /* Check the Alternate function parameter */
- assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
-
- /* Configure Alternate function mapped with the current IO */
- temp = GPIOx->AFR[position >> 3];
- temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
- temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
- GPIOx->AFR[position >> 3] = temp;
- }
-
- /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
- temp = GPIOx->MODER;
- temp &= ~(GPIO_MODER_MODER0 << (position * 2));
- temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
- GPIOx->MODER = temp;
-
/* In case of Output or Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
@@ -234,6 +215,25 @@
temp |= ((GPIO_Init->Pull) << (position * 2));
GPIOx->PUPDR = temp;
+ /* In case of Alternate function mode selection */
+ if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ {
+ /* Check the Alternate function parameter */
+ assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
+ /* Configure Alternate function mapped with the current IO */
+ temp = GPIOx->AFR[position >> 3];
+ temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
+ temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
+ GPIOx->AFR[position >> 3] = temp;
+ }
+
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+ temp = GPIOx->MODER;
+ temp &= ~(GPIO_MODER_MODER0 << (position * 2));
+ temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
+ GPIOx->MODER = temp;
+
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
@@ -300,7 +300,7 @@
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-
+
/* Configure the port pins */
for(position = 0; position < GPIO_NUMBER; position++)
{
@@ -316,10 +316,6 @@
tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))))
{
- /* Configure the External Interrupt or event for the current IO */
- tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
- SYSCFG->EXTICR[position >> 2] &= ~tmp;
-
/* Clear EXTI line configuration */
EXTI->IMR &= ~((uint32_t)iocurrent);
EXTI->EMR &= ~((uint32_t)iocurrent);
@@ -327,6 +323,10 @@
/* Clear Rising Falling edge configuration */
EXTI->RTSR &= ~((uint32_t)iocurrent);
EXTI->FTSR &= ~((uint32_t)iocurrent);
+
+ /* Configure the External Interrupt or event for the current IO */
+ tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
+ SYSCFG->EXTICR[position >> 2] &= ~tmp;
}
/*------------------------- GPIO Mode Configuration --------------------*/
/* Configure IO Direction in Input Floating Mode */
@@ -335,14 +335,14 @@
/* Configure the default Alternate Function in current IO */
GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
- /* Configure the default value for IO Speed */
- GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
+ /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
/* Configure the default value IO Output Type */
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
- /* Deactivate the Pull-up and Pull-down resistor for the current IO */
- GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
+ /* Configure the default value for IO Speed */
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
}
}
}
@@ -431,13 +431,13 @@
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
- if ((GPIOx->ODR & GPIO_Pin) == GPIO_Pin)
+ if ((GPIOx->ODR & GPIO_Pin) != 0X00u)
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
}
else
{
- GPIOx->BSRR = GPIO_Pin;
+ GPIOx->BSRR = (uint32_t)GPIO_Pin;
}
}
@@ -467,10 +467,11 @@
GPIOx->LCKR = GPIO_Pin;
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp;
- /* Read LCKK bit*/
+ /* Read LCKR register. This read is mandatory to complete key lock sequence */
tmp = GPIOx->LCKR;
- if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
+ /* Read again in order to confirm lock is active */
+ if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
{
return HAL_OK;
}
diff --git a/Src/stm32f7xx_hal_hash.c b/Src/stm32f7xx_hal_hash.c
index 69a8607..c752efa 100644
--- a/Src/stm32f7xx_hal_hash.c
+++ b/Src/stm32f7xx_hal_hash.c
@@ -57,24 +57,29 @@
(#)When the processing function is called after HAL_HASH_Init(), the HASH peripheral is
initialized and processes the buffer fed in input. When the input data have all been
- fed to the IP, the digest computation can start.
+ fed to the Peripheral, the digest computation can start.
- (#)Multi-buffer processing is possible in polling and DMA mode.
+ (#)Multi-buffer processing is possible in polling, interrupt and DMA modes.
(##) In polling mode, only multi-buffer HASH processing is possible.
API HAL_HASH_xxx_Accumulate() must be called for each input buffer, except for the last one.
- User must resort to HAL_HASH_xxx_Start() to enter the last one and retrieve as
+ User must resort to HAL_HASH_xxx_Accumulate_End() to enter the last one and retrieve as
+ well the computed digest.
+
+ (##) In interrupt mode, API HAL_HASH_xxx_Accumulate_IT() must be called for each input buffer,
+ except for the last one.
+ User must resort to HAL_HASH_xxx_Accumulate_End_IT() to enter the last one and retrieve as
well the computed digest.
(##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
(+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
- From that point, each buffer can be fed to the IP thru HAL_HASH_xxx_Start_DMA() API.
+ From that point, each buffer can be fed to the Peripheral thru HAL_HASH_xxx_Start_DMA() API.
Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
macro then wrap-up the HASH processing in feeding the last input buffer thru the
same API HAL_HASH_xxx_Start_DMA(). The digest can then be retrieved with a call to
API HAL_HASH_xxx_Finish().
(+++) HMAC processing (requires to resort to extended functions):
after initialization, the key and the first input buffer are entered
- in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
+ in the Peripheral with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
starts step 2.
The following buffers are next entered with the API HAL_HMACEx_xxx_Step2_DMA(). At this
point, the HMAC processing is still carrying out step 2.
@@ -90,16 +95,50 @@
(+++) HAL_HASH_DMAFeed_ProcessSuspend() when data are entered by DMA.
(##) When HASH or HMAC processing is suspended, HAL_HASH_ContextSaving() allows
- to save in memory the IP context. This context can be restored afterwards
+ to save in memory the Peripheral context. This context can be restored afterwards
to resume the HASH processing thanks to HAL_HASH_ContextRestoring().
- (##) Once the HASH IP has been restored to the same configuration as that at suspension
+ (##) Once the HASH Peripheral has been restored to the same configuration as that at suspension
time, processing can be restarted with the same API call (same API, same handle,
same parameters) as done before the suspension. Relevant parameters to restart at
the proper location are internally saved in the HASH handle.
(#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
+ *** Remarks on message length ***
+ ===================================
+ [..]
+ (#) HAL in interruption mode (interruptions driven)
+
+ (##)Due to HASH peripheral hardware design, the peripheral interruption is triggered every 64 bytes.
+ This is why, for driver implementation simplicity’s sake, user is requested to enter a message the
+ length of which is a multiple of 4 bytes.
+
+ (##) When the message length (in bytes) is not a multiple of words, a specific field exists in HASH_STR
+ to specify which bits to discard at the end of the complete message to process only the message bits
+ and not extra bits.
+
+ (##) If user needs to perform a hash computation of a large input buffer that is spread around various places
+ in memory and where each piece of this input buffer is not necessarily a multiple of 4 bytes in size, it
+ becomes necessary to use a temporary buffer to format the data accordingly before feeding them to the Peripheral.
+ It is advised to the user to
+ (+++) achieve the first formatting operation by software then enter the data
+ (+++) while the Peripheral is processing the first input set, carry out the second formatting operation by software, to be ready when DINIS occurs.
+ (+++) repeat step 2 until the whole message is processed.
+
+ [..]
+ (#) HAL in DMA mode
+
+ (##) Again, due to hardware design, the DMA transfer to feed the data can only be done on a word-basis.
+ The same field described above in HASH_STR is used to specify which bits to discard at the end of the DMA transfer
+ to process only the message bits and not extra bits. Due to hardware implementation, this is possible only at the
+ end of the complete message. When several DMA transfers are needed to enter the message, this is not applicable at
+ the end of the intermediary transfers.
+
+ (##) Similarly to the interruption-driven mode, it is suggested to the user to format the consecutive chunks of data
+ by software while the DMA transfer and processing is on-going for the first parts of the message. Due to the 32-bit alignment
+ required for the DMA transfer, it is underlined that the software formatting operation is more complex than in the IT mode.
+
*** Callback registration ***
===================================
[..]
@@ -260,7 +299,7 @@
[..] This section provides as well call back functions definitions for user
code to manage:
- (+) Input data transfer to IP completion
+ (+) Input data transfer to Peripheral completion
(+) Calculated digest retrieval completion
(+) Error management
@@ -273,25 +312,25 @@
/**
* @brief Initialize the HASH according to the specified parameters in the
HASH_HandleTypeDef and create the associated handle.
- * @note Only MDMAT and DATATYPE bits of HASH IP are set by HAL_HASH_Init(),
+ * @note Only MDMAT and DATATYPE bits of HASH Peripheral are set by HAL_HASH_Init(),
* other configuration bits are set by HASH or HMAC processing APIs.
* @note MDMAT bit is systematically reset by HAL_HASH_Init(). To set it for
* multi-buffer HASH processing, user needs to resort to
* __HAL_HASH_SET_MDMAT() macro. For HMAC multi-buffer processing, the
* relevant APIs manage themselves the MDMAT bit.
- * @param hhash: HASH handle
+ * @param hhash HASH handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
{
- /* Check the parameters */
- assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
-
/* Check the hash handle allocation */
if(hhash == NULL)
{
return HAL_ERROR;
}
+
+ /* Check the parameters */
+ assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
if (hhash->State == HAL_HASH_STATE_RESET)
@@ -334,6 +373,8 @@
hhash->DigestCalculationDisable = RESET;
/* Set phase to READY */
hhash->Phase = HAL_HASH_PHASE_READY;
+ /* Reset suspension request flag */
+ hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
/* Set the data type bit */
MODIFY_REG(HASH->CR, HASH_CR_DATATYPE, hhash->Init.DataType);
@@ -354,7 +395,7 @@
/**
* @brief DeInitialize the HASH peripheral.
- * @param hhash: HASH handle.
+ * @param hhash HASH handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
@@ -401,13 +442,16 @@
/* Initialise the error code */
hhash->ErrorCode = HAL_HASH_ERROR_NONE;
+ /* Reset multi buffers accumulation flag */
+ hhash->Accumulation = 0U;
+
/* Return function status */
return HAL_OK;
}
/**
* @brief Initialize the HASH MSP.
- * @param hhash: HASH handle.
+ * @param hhash HASH handle.
* @retval None
*/
__weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
@@ -422,7 +466,7 @@
/**
* @brief DeInitialize the HASH MSP.
- * @param hhash: HASH handle.
+ * @param hhash HASH handle.
* @retval None
*/
__weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
@@ -438,12 +482,12 @@
/**
* @brief Input data transfer complete call back.
* @note HAL_HASH_InCpltCallback() is called when the complete input message
- * has been fed to the IP. This API is invoked only when input data are
+ * has been fed to the Peripheral. This API is invoked only when input data are
* entered under interruption or thru DMA.
* @note In case of HASH or HMAC multi-buffer DMA feeding case (MDMAT bit set),
* HAL_HASH_InCpltCallback() is called at the end of each buffer feeding
- * to the IP.
- * @param hhash: HASH handle.
+ * to the Peripheral.
+ * @param hhash HASH handle.
* @retval None
*/
__weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
@@ -460,7 +504,7 @@
* @brief Digest computation complete call back.
* @note HAL_HASH_DgstCpltCallback() is used under interruption, is not
* relevant with DMA.
- * @param hhash: HASH handle.
+ * @param hhash HASH handle.
* @retval None
*/
__weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
@@ -477,7 +521,7 @@
* @brief Error callback.
* @note Code user can resort to hhash->Status (HAL_ERROR, HAL_TIMEOUT,...)
* to retrieve the error type.
- * @param hhash: HASH handle.
+ * @param hhash HASH handle.
* @retval None
*/
__weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
@@ -684,17 +728,19 @@
the hash value using one of the following algorithms:
(+) MD5
(++) HAL_HASH_MD5_Start()
- (++) HAL_HASH_MD5_Accumulate()
+ (++) HAL_HASH_MD5_Accmlt()
+ (++) HAL_HASH_MD5_Accmlt_End()
(+) SHA1
(++) HAL_HASH_SHA1_Start()
- (++) HAL_HASH_SHA1_Accumulate()
+ (++) HAL_HASH_SHA1_Accmlt()
+ (++) HAL_HASH_SHA1_Accmlt_End()
[..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().
[..] In case of multi-buffer HASH processing (a single digest is computed while
- several buffers are fed to the IP), the user can resort to successive calls
+ several buffers are fed to the Peripheral), the user can resort to successive calls
to HAL_HASH_xxx_Accumulate() and wrap-up the digest computation by a call
- to HAL_HASH_xxx_Start().
+ to HAL_HASH_xxx_Accumulate_End().
@endverbatim
* @{
@@ -704,11 +750,11 @@
* @brief Initialize the HASH peripheral in MD5 mode, next process pInBuffer then
* read the computed digest.
* @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
- * @param Timeout: Timeout value
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
+ * @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -719,37 +765,52 @@
/**
* @brief If not already done, initialize the HASH peripheral in MD5 mode then
* processes pInBuffer.
- * @note Consecutive calls to HAL_HASH_MD5_Accumulate() can be used to feed
- * several input buffers back-to-back to the IP that will yield a single
+ * @note Consecutive calls to HAL_HASH_MD5_Accmlt() can be used to feed
+ * several input buffers back-to-back to the Peripheral that will yield a single
* HASH signature once all buffers have been entered. Wrap-up of input
* buffers feeding and retrieval of digest is done by a call to
- * HAL_HASH_MD5_Start().
+ * HAL_HASH_MD5_Accmlt_End().
* @note Field hhash->Phase of HASH handle is tested to check whether or not
- * the IP has already been initialized.
- * @note Digest is not retrieved by this API, user must resort to HAL_HASH_MD5_Start()
- * to read it, feeding at the same time the last input buffer to the IP.
+ * the Peripheral has already been initialized.
+ * @note Digest is not retrieved by this API, user must resort to HAL_HASH_MD5_Accmlt_End()
+ * to read it, feeding at the same time the last input buffer to the Peripheral.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
- * HASH digest computation is corrupted. Only HAL_HASH_MD5_Start() is able
+ * HASH digest computation is corrupted. Only HAL_HASH_MD5_Accmlt_End() is able
* to manage the ending buffer with a length in bytes not a multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes, must be a multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_MD5);
}
/**
+ * @brief End computation of a single HASH signature after several calls to HAL_HASH_MD5_Accmlt() API.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
+ * @param Timeout Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
+}
+
+/**
* @brief Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then
* read the computed digest.
* @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
- * @param Timeout: Timeout value
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
+ * @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -760,28 +821,42 @@
/**
* @brief If not already done, initialize the HASH peripheral in SHA1 mode then
* processes pInBuffer.
- * @note Consecutive calls to HAL_HASH_SHA1_Accumulate() can be used to feed
- * several input buffers back-to-back to the IP that will yield a single
+ * @note Consecutive calls to HAL_HASH_SHA1_Accmlt() can be used to feed
+ * several input buffers back-to-back to the Peripheral that will yield a single
* HASH signature once all buffers have been entered. Wrap-up of input
* buffers feeding and retrieval of digest is done by a call to
- * HAL_HASH_SHA1_Start().
+ * HAL_HASH_SHA1_Accmlt_End().
* @note Field hhash->Phase of HASH handle is tested to check whether or not
- * the IP has already been initialized.
- * @note Digest is not retrieved by this API, user must resort to HAL_HASH_SHA1_Start()
- * to read it, feeding at the same time the last input buffer to the IP.
+ * the Peripheral has already been initialized.
+ * @note Digest is not retrieved by this API, user must resort to HAL_HASH_SHA1_Accmlt_End()
+ * to read it, feeding at the same time the last input buffer to the Peripheral.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
- * HASH digest computation is corrupted. Only HAL_HASH_SHA1_Start() is able
+ * HASH digest computation is corrupted. Only HAL_HASH_SHA1_Accmlt_End() is able
* to manage the ending buffer with a length in bytes not a multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes, must be a multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA1);
}
+/**
+ * @brief End computation of a single HASH signature after several calls to HAL_HASH_SHA1_Accmlt() API.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
+ * @param Timeout Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
+}
/**
* @}
@@ -798,12 +873,16 @@
the hash value using one of the following algorithms:
(+) MD5
(++) HAL_HASH_MD5_Start_IT()
+ (++) HAL_HASH_MD5_Accmlt_IT()
+ (++) HAL_HASH_MD5_Accmlt_End_IT()
(+) SHA1
(++) HAL_HASH_SHA1_Start_IT()
+ (++) HAL_HASH_SHA1_Accmlt_IT()
+ (++) HAL_HASH_SHA1_Accmlt_End_IT()
[..] API HAL_HASH_IRQHandler() manages each HASH interruption.
- [..] Note that HAL_HASH_IRQHandler() manages as well HASH IP interruptions when in
+ [..] Note that HAL_HASH_IRQHandler() manages as well HASH Peripheral interruptions when in
HMAC processing mode.
@@ -815,10 +894,10 @@
* @brief Initialize the HASH peripheral in MD5 mode, next process pInBuffer then
* read the computed digest in interruption mode.
* @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@@ -826,15 +905,51 @@
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_MD5);
}
+/**
+ * @brief If not already done, initialize the HASH peripheral in MD5 mode then
+ * processes pInBuffer in interruption mode.
+ * @note Consecutive calls to HAL_HASH_MD5_Accmlt_IT() can be used to feed
+ * several input buffers back-to-back to the Peripheral that will yield a single
+ * HASH signature once all buffers have been entered. Wrap-up of input
+ * buffers feeding and retrieval of digest is done by a call to
+ * HAL_HASH_MD5_Accmlt_End_IT().
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the Peripheral has already been initialized.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted. Only HAL_HASH_MD5_Accmlt_End_IT() is able
+ * to manage the ending buffer with a length in bytes not a multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_MD5);
+}
+
+/**
+ * @brief End computation of a single HASH signature after several calls to HAL_HASH_MD5_Accmlt_IT() API.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_MD5);
+}
/**
* @brief Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then
* read the computed digest in interruption mode.
* @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@@ -842,9 +957,47 @@
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA1);
}
+
+/**
+ * @brief If not already done, initialize the HASH peripheral in SHA1 mode then
+ * processes pInBuffer in interruption mode.
+ * @note Consecutive calls to HAL_HASH_SHA1_Accmlt_IT() can be used to feed
+ * several input buffers back-to-back to the Peripheral that will yield a single
+ * HASH signature once all buffers have been entered. Wrap-up of input
+ * buffers feeding and retrieval of digest is done by a call to
+ * HAL_HASH_SHA1_Accmlt_End_IT().
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the Peripheral has already been initialized.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted. Only HAL_HASH_SHA1_Accmlt_End_IT() is able
+ * to manage the ending buffer with a length in bytes not a multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+ * @brief End computation of a single HASH signature after several calls to HAL_HASH_SHA1_Accmlt_IT() API.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA1);
+}
+
/**
* @brief Handle HASH interrupt request.
- * @param hhash: HASH handle.
+ * @param hhash HASH handle.
* @note HAL_HASH_IRQHandler() handles interrupts in HMAC processing as well.
* @note In case of error reported during the HASH interruption processing,
* HAL_HASH_ErrorCallback() API is called so that user code can
@@ -887,7 +1040,7 @@
(++) HAL_HASH_SHA1_Start_DMA()
(++) HAL_HASH_SHA1_Finish()
- [..] When resorting to DMA mode to enter the data in the IP, user must resort
+ [..] When resorting to DMA mode to enter the data in the Peripheral, user must resort
to HAL_HASH_xxx_Start_DMA() then read the resulting digest with
HAL_HASH_xxx_Finish().
[..] In case of multi-buffer HASH processing, MDMAT bit must first be set before
@@ -901,12 +1054,12 @@
/**
* @brief Initialize the HASH peripheral in MD5 mode then initiate a DMA transfer
- * to feed the input buffer to the IP.
+ * to feed the input buffer to the Peripheral.
* @note Once the DMA transfer is finished, HAL_HASH_MD5_Finish() API must
* be called to retrieve the computed digest.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -919,9 +1072,9 @@
* @note The API waits for DCIS to be set then reads the computed digest.
* @note HAL_HASH_MD5_Finish() can be used as well to retrieve the digest in
* HMAC MD5 mode.
- * @param hhash: HASH handle.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
- * @param Timeout: Timeout value.
+ * @param hhash HASH handle.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
+ * @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -931,12 +1084,12 @@
/**
* @brief Initialize the HASH peripheral in SHA1 mode then initiate a DMA transfer
- * to feed the input buffer to the IP.
+ * to feed the input buffer to the Peripheral.
* @note Once the DMA transfer is finished, HAL_HASH_SHA1_Finish() API must
* be called to retrieve the computed digest.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -950,9 +1103,9 @@
* @note The API waits for DCIS to be set then reads the computed digest.
* @note HAL_HASH_SHA1_Finish() can be used as well to retrieve the digest in
* HMAC SHA1 mode.
- * @param hhash: HASH handle.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
- * @param Timeout: Timeout value.
+ * @param hhash HASH handle.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
+ * @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -989,11 +1142,11 @@
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
- * @param Timeout: Timeout value.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
+ * @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -1007,11 +1160,11 @@
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
- * @param Timeout: Timeout value.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
+ * @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -1049,10 +1202,10 @@
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@@ -1066,10 +1219,10 @@
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@@ -1097,7 +1250,7 @@
(+) SHA1
(++) HAL_HMAC_SHA1_Start_DMA()
- [..] When resorting to DMA mode to enter the data in the IP for HMAC processing,
+ [..] When resorting to DMA mode to enter the data in the Peripheral for HMAC processing,
user must resort to HAL_HMAC_xxx_Start_DMA() then read the resulting digest
with HAL_HASH_xxx_Finish().
@@ -1108,7 +1261,7 @@
/**
* @brief Initialize the HASH peripheral in HMAC MD5 mode then initiate the required
- * DMA transfers to feed the key and the input buffer to the IP.
+ * DMA transfers to feed the key and the input buffer to the Peripheral.
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASH_MD5_Finish() API must be called to retrieve
* the computed digest.
@@ -1120,9 +1273,9 @@
* For the processing of the last buffer of the thread, MDMAT bit must
* be reset and the buffer length (in bytes) doesn't have to be a
* multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -1133,7 +1286,7 @@
/**
* @brief Initialize the HASH peripheral in HMAC SHA1 mode then initiate the required
- * DMA transfers to feed the key and the input buffer to the IP.
+ * DMA transfers to feed the key and the input buffer to the Peripheral.
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASH_SHA1_Finish() API must be called to retrieve
* the computed digest.
@@ -1145,9 +1298,9 @@
* For the processing of the last buffer of the thread, MDMAT bit must
* be reset and the buffer length (in bytes) doesn't have to be a
* multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -1180,9 +1333,9 @@
[..]
This subsection provides functions allowing to suspend the HASH processing
- (+) when input are fed to the IP by software
+ (+) when input are fed to the Peripheral by software
(++) HAL_HASH_SwFeed_ProcessSuspend()
- (+) when input are fed to the IP by DMA
+ (+) when input are fed to the Peripheral by DMA
(++) HAL_HASH_DMAFeed_ProcessSuspend()
@@ -1194,7 +1347,7 @@
/**
* @brief Return the HASH handle state.
* @note The API yields the current state of the handle (BUSY, READY,...).
- * @param hhash: HASH handle.
+ * @param hhash HASH handle.
* @retval HAL HASH state
*/
HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
@@ -1207,7 +1360,7 @@
* @brief Return the HASH HAL status.
* @note The API yields the HAL status of the handle: it is the result of the
* latest HASH processing and allows to report any issue (e.g. HAL_TIMEOUT).
- * @param hhash: HASH handle.
+ * @param hhash HASH handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash)
@@ -1217,8 +1370,8 @@
/**
* @brief Save the HASH context in case of processing suspension.
- * @param hhash: HASH handle.
- * @param pMemBuffer: pointer to the memory buffer where the HASH context
+ * @param hhash HASH handle.
+ * @param pMemBuffer pointer to the memory buffer where the HASH context
* is saved.
* @note The IMR, STR, CR then all the CSR registers are saved
* in that order. Only the r/w bits are read to be restored later on.
@@ -1258,8 +1411,8 @@
/**
* @brief Restore the HASH context in case of processing resumption.
- * @param hhash: HASH handle.
- * @param pMemBuffer: pointer to the memory buffer where the HASH context
+ * @param hhash HASH handle.
+ * @param pMemBuffer pointer to the memory buffer where the HASH context
* is stored.
* @note The IMR, STR, CR then all the CSR registers are restored
* in that order. Only the r/w bits are restored.
@@ -1303,7 +1456,7 @@
/**
* @brief Initiate HASH processing suspension when in polling or interruption mode.
- * @param hhash: HASH handle.
+ * @param hhash HASH handle.
* @note Set the handle field SuspendRequest to the appropriate value so that
* the on-going HASH processing is suspended as soon as the required
* conditions are met. Note that the actual suspension is carried out
@@ -1319,9 +1472,9 @@
/**
* @brief Suspend the HASH processing when in DMA mode.
- * @param hhash: HASH handle.
+ * @param hhash HASH handle.
* @note When suspension attempt occurs at the very end of a DMA transfer and
- * all the data have already been entered in the IP, hhash->State is
+ * all the data have already been entered in the Peripheral, hhash->State is
* set to HAL_HASH_STATE_READY and the API returns HAL_ERROR. It is
* recommended to wrap-up the processing in reading the digest as usual.
* @retval HAL status
@@ -1349,7 +1502,7 @@
return HAL_ERROR;
}
- /* Wait for DMAS to be reset */
+ /* Wait for BUSY flag to be reset */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
{
return HAL_TIMEOUT;
@@ -1360,26 +1513,26 @@
return HAL_ERROR;
}
- /* Wait for DMAS to be set */
+ /* Wait for BUSY flag to be set */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, RESET, HASH_TIMEOUTVALUE) != HAL_OK)
{
return HAL_TIMEOUT;
}
-
/* Disable DMA channel */
- if (HAL_DMA_Abort(hhash->hdmain) ==HAL_OK)
- {
- /*
- Note that the Abort function will
+ /* Note that the Abort function will
- Clear the transfer error flags
- Unlock
- Set the State
- */
+ */
+ if (HAL_DMA_Abort(hhash->hdmain) !=HAL_OK)
+ {
+ return HAL_ERROR;
}
/* Clear DMAE bit */
CLEAR_BIT(HASH->CR,HASH_CR_DMAE);
+ /* Wait for BUSY flag to be reset */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
{
return HAL_TIMEOUT;
@@ -1413,8 +1566,8 @@
/* Compute how many words were supposed to be transferred by DMA */
tmp_initial_DMATransferSize_inWords = (((hhash->HashInCount%4U)!=0U) ? ((hhash->HashInCount+3U)/4U): (hhash->HashInCount/4U));
- /* If discrepancy between the number of words reported by DMA IP and the numbers of words entered as reported
- by HASH IP, correct it */
+ /* If discrepancy between the number of words reported by DMA Peripheral and the numbers of words entered as reported
+ by HASH Peripheral, correct it */
/* tmp_words_already_pushed reflects the number of words that were already pushed before
the start of DMA transfer (multi-buffer processing case) */
tmp_words_already_pushed = hhash->NbWordsAlreadyPushed;
@@ -1423,7 +1576,7 @@
tmp_remaining_DMATransferSize_inWords--; /* one less word to be transferred again */
}
- /* Accordingly, update the input pointer that points at the next word to be transferred to the IP by DMA */
+ /* Accordingly, update the input pointer that points at the next word to be transferred to the Peripheral by DMA */
hhash->pHashInBuffPtr += 4U * (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ;
/* And store in HashInCount the remaining size to transfer (in bytes) */
@@ -1441,7 +1594,7 @@
/**
* @brief Return the HASH handle error code.
- * @param hhash: pointer to a HASH_HandleTypeDef structure.
+ * @param hhash pointer to a HASH_HandleTypeDef structure.
* @retval HASH Error Code
*/
uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash)
@@ -1464,7 +1617,7 @@
/**
* @brief DMA HASH Input Data transfer completion callback.
- * @param hdma: DMA handle.
+ * @param hdma DMA handle.
* @note In case of HMAC processing, HASH_DMAXferCplt() initiates
* the next DMA transfer for the following HMAC step.
* @retval None
@@ -1475,42 +1628,42 @@
uint32_t inputaddr;
uint32_t buffersize;
HAL_StatusTypeDef status ;
-
+
if (hhash->State != HAL_HASH_STATE_SUSPENDED)
{
-
+
/* Disable the DMA transfer */
CLEAR_BIT(HASH->CR, HASH_CR_DMAE);
-
+
if (READ_BIT(HASH->CR, HASH_CR_MODE) == 0U)
{
/* If no HMAC processing, input data transfer is now over */
-
+
/* Change the HASH state to ready */
hhash->State = HAL_HASH_STATE_READY;
-
+
/* Call Input data transfer complete call back */
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
hhash->InCpltCallback(hhash);
#else
HAL_HASH_InCpltCallback(hhash);
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
-
+
}
else
{
/* HMAC processing: depending on the current HMAC step and whether or
not multi-buffer processing is on-going, the next step is initiated
and MDMAT bit is set. */
-
-
+
+
if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)
{
/* This is the end of HMAC processing */
-
+
/* Change the HASH state to ready */
hhash->State = HAL_HASH_STATE_READY;
-
+
/* Call Input data transfer complete call back
(note that the last DMA transfer was that of the key
for the outer HASH operation). */
@@ -1519,7 +1672,7 @@
#else
HAL_HASH_InCpltCallback(hhash);
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
-
+
return;
}
else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
@@ -1527,17 +1680,17 @@
inputaddr = (uint32_t)hhash->pHashMsgBuffPtr; /* DMA transfer start address */
buffersize = hhash->HashBuffSize; /* DMA transfer size (in bytes) */
hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; /* Move phase from Step 1 to Step 2 */
-
+
/* In case of suspension request, save the new starting parameters */
hhash->HashInCount = hhash->HashBuffSize; /* Initial DMA transfer size (in bytes) */
hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr ; /* DMA transfer start address */
-
+
hhash->NbWordsAlreadyPushed = 0U; /* Reset number of words already pushed */
/* Check whether or not digest calculation must be disabled (in case of multi-buffer HMAC processing) */
if (hhash->DigestCalculationDisable != RESET)
{
/* Digest calculation is disabled: Step 2 must start with MDMAT bit set,
- no digest calculation will be triggered at the end of the input buffer feeding to the IP */
+ no digest calculation will be triggered at the end of the input buffer feeding to the Peripheral */
__HAL_HASH_SET_MDMAT();
}
}
@@ -1545,7 +1698,7 @@
{
if (hhash->DigestCalculationDisable != RESET)
{
- /* No automatic move to Step 3 as a new message buffer will be fed to the IP
+ /* No automatic move to Step 3 as a new message buffer will be fed to the Peripheral
(case of multi-buffer HMAC processing):
DCAL must not be set.
Phase remains in Step 2, MDMAT remains set at this point.
@@ -1568,34 +1721,34 @@
/* In case of suspension request, save the new starting parameters */
hhash->HashInCount = hhash->Init.KeySize; /* Initial size for second DMA transfer (input data) */
hhash->pHashInBuffPtr = hhash->Init.pKey ; /* address passed to DMA, now entering data message */
-
+
hhash->NbWordsAlreadyPushed = 0U; /* Reset number of words already pushed */
}
}
-
+
/* Configure the Number of valid bits in last word of the message */
__HAL_HASH_SET_NBVALIDBITS(buffersize);
/* Set the HASH DMA transfert completion call back */
hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
-
+
/* Enable the DMA In DMA Stream */
status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((buffersize %4U)!=0U) ? ((buffersize+(4U-(buffersize %4U)))/4U):(buffersize/4U)));
/* Enable DMA requests */
SET_BIT(HASH->CR, HASH_CR_DMAE);
-
+
/* Return function status */
if (status != HAL_OK)
{
- /* Update DAC state machine to error */
- hhash->State = HAL_HASH_STATE_ERROR;
+ /* Update HASH state machine to error */
+ hhash->State = HAL_HASH_STATE_ERROR;
}
else
{
- /* Change DAC state */
+ /* Change HASH state */
hhash->State = HAL_HASH_STATE_READY;
- }
+ }
}
}
@@ -1604,7 +1757,7 @@
/**
* @brief DMA HASH communication error callback.
- * @param hdma: DMA handle.
+ * @param hdma DMA handle.
* @note HASH_DMAError() callback invokes HAL_HASH_ErrorCallback() that
* can contain user code to manage the error.
* @retval None
@@ -1633,13 +1786,13 @@
}
/**
- * @brief Feed the input buffer to the HASH IP.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to input buffer.
- * @param Size: the size of input buffer in bytes.
+ * @brief Feed the input buffer to the HASH Peripheral.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to input buffer.
+ * @param Size the size of input buffer in bytes.
* @note HASH_WriteData() regularly reads hhash->SuspendRequest to check whether
* or not the HASH processing must be suspended. If this is the case, the
- * processing is suspended when possible and the IP feeding point reached at
+ * processing is suspended when possible and the Peripheral feeding point reached at
* suspension time is stored in the handle for resumption later on.
* @retval HAL status
*/
@@ -1665,7 +1818,7 @@
/* Reset SuspendRequest */
hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
- /* Depending whether the key or the input data were fed to the IP, the feeding point
+ /* Depending whether the key or the input data were fed to the Peripheral, the feeding point
reached at suspension time is not saved in the same handle fields */
if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2))
{
@@ -1697,14 +1850,14 @@
} /* if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4) < Size)) */
} /* for(buffercounter = 0; buffercounter < Size; buffercounter+=4) */
- /* At this point, all the data have been entered to the IP: exit */
+ /* At this point, all the data have been entered to the Peripheral: exit */
return HAL_OK;
}
/**
* @brief Retrieve the message digest.
- * @param pMsgDigest: pointer to the computed digest.
- * @param Size: message digest size in bytes.
+ * @param pMsgDigest pointer to the computed digest.
+ * @param Size message digest size in bytes.
* @retval None
*/
static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
@@ -1775,10 +1928,10 @@
/**
* @brief Handle HASH processing Timeout.
- * @param hhash: HASH handle.
- * @param Flag: specifies the HASH flag to check.
- * @param Status: the Flag status (SET or RESET).
- * @param Timeout: Timeout duration.
+ * @param hhash HASH handle.
+ * @param Flag specifies the HASH flag to check.
+ * @param Status the Flag status (SET or RESET).
+ * @param Timeout Timeout duration.
* @retval HAL status
*/
static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
@@ -1836,10 +1989,10 @@
/**
* @brief HASH processing in interruption mode.
- * @param hhash: HASH handle.
+ * @param hhash HASH handle.
* @note HASH_IT() regularly reads hhash->SuspendRequest to check whether
* or not the HASH processing must be suspended. If this is the case, the
- * processing is suspended when possible and the IP feeding point reached at
+ * processing is suspended when possible and the Peripheral feeding point reached at
* suspension time is stored in the handle for resumption later on.
* @retval HAL status
*/
@@ -1860,7 +2013,7 @@
else if (hhash->HashITCounter == 1U)
{
/* This is the first call to HASH_IT, the first input data are about to be
- entered in the IP. A specific processing is carried out at this point to
+ entered in the Peripheral. A specific processing is carried out at this point to
start-up the processing. */
hhash->HashITCounter = 2U;
}
@@ -1881,6 +2034,8 @@
__HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_READY;
+ /* Reset HASH state machine */
+ hhash->Phase = HAL_HASH_PHASE_READY;
/* Call digest computation complete call back */
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
hhash->DgstCpltCallback(hhash);
@@ -1891,7 +2046,7 @@
return HAL_OK;
}
- /* If IP ready to accept new data */
+ /* If Peripheral ready to accept new data */
if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
{
@@ -1911,7 +2066,7 @@
return HAL_OK;
}
- /* Enter input data in the IP thru HASH_Write_Block_Data() call and
+ /* Enter input data in the Peripheral thru HASH_Write_Block_Data() call and
check whether the digest calculation has been triggered */
if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED)
{
@@ -1925,7 +2080,7 @@
if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
{
- /* Wait until IP is not busy anymore */
+ /* Wait until Peripheral is not busy anymore */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
{
/* Disable Interrupts */
@@ -1942,7 +2097,7 @@
}
else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
{
- /* Wait until IP is not busy anymore */
+ /* Wait until Peripheral is not busy anymore */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
{
/* Disable Interrupts */
@@ -1975,8 +2130,8 @@
/**
- * @brief Write a block of data in HASH IP in interruption mode.
- * @param hhash: HASH handle.
+ * @brief Write a block of data in HASH Peripheral in interruption mode.
+ * @param hhash HASH handle.
* @note HASH_Write_Block_Data() is called under interruption by HASH_IT().
* @retval HAL status
*/
@@ -2005,7 +2160,7 @@
HASH->DIN = *(uint32_t*)inputaddr;
if(hhash->HashInCount >= 68U)
{
- /* There are still data waiting to be entered in the IP.
+ /* There are still data waiting to be entered in the Peripheral.
Decrement buffer counter and set pointer to the proper
memory location for the next data entering round. */
hhash->HashInCount -= 68U;
@@ -2044,13 +2199,33 @@
HASH->DIN = *(uint32_t*)inputaddr;
inputaddr+=4U;
}
- /* Start the Digest calculation */
- __HAL_HASH_START_DIGEST();
- /* Return indication that digest calculation has started:
- this return value triggers the call to Input data transfer
- complete call back as well as the proper transition from
- one step to another in HMAC mode. */
- ret = HASH_DIGEST_CALCULATION_STARTED;
+
+ if (hhash->Accumulation == 1U)
+ {
+ /* Field accumulation is set, API only feeds data to the Peripheral and under interruption.
+ The digest computation will be started when the last buffer data are entered. */
+
+ /* Reset multi buffers accumulation flag */
+ hhash->Accumulation = 0U;
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+ /* Call Input data transfer complete call back */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ hhash->InCpltCallback(hhash);
+#else
+ HAL_HASH_InCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Start the Digest calculation */
+ __HAL_HASH_START_DIGEST();
+ /* Return indication that digest calculation has started:
+ this return value triggers the call to Input data transfer
+ complete call back as well as the proper transition from
+ one step to another in HMAC mode. */
+ ret = HASH_DIGEST_CALCULATION_STARTED;
+ }
/* Reset buffer counter */
hhash->HashInCount = 0;
}
@@ -2061,8 +2236,8 @@
/**
* @brief HMAC processing in polling mode.
- * @param hhash: HASH handle.
- * @param Timeout: Timeout value.
+ * @param hhash HASH handle.
+ * @param Timeout Timeout value.
* @retval HAL status
*/
static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout)
@@ -2204,6 +2379,9 @@
/* Read the message digest */
HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH());
+
+ /* Reset HASH state machine */
+ hhash->Phase = HAL_HASH_PHASE_READY;
}
/* Change the HASH state */
@@ -2221,58 +2399,58 @@
* @brief Initialize the HASH peripheral, next process pInBuffer then
* read the computed digest.
* @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest.
- * @param Timeout: Timeout value.
- * @param Algorithm: HASH algorithm.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest.
+ * @param Timeout Timeout value.
+ * @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
{
uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */
uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */
- HAL_HASH_StateTypeDef State_tmp = hhash->State;
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
-
+
/* Initiate HASH processing in case of start or resumption */
if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
- {
+ {
/* Check input parameters */
- if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL))
+ if ((pInBuffer == NULL) || (pOutBuffer == NULL))
{
hhash->State = HAL_HASH_STATE_READY;
return HAL_ERROR;
}
-
+
/* Process Locked */
__HAL_LOCK(hhash);
-
+
/* Check if initialization phase has not been already performed */
if(hhash->Phase == HAL_HASH_PHASE_READY)
{
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_BUSY;
-
+
/* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
-
+
/* Configure the number of valid bits in last word of the message */
__HAL_HASH_SET_NBVALIDBITS(Size);
-
+
/* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
input parameters of HASH_WriteData() */
pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */
Size_tmp = Size; /* Size_tmp contains the input data size in bytes */
-
+
/* Set the phase */
hhash->Phase = HAL_HASH_PHASE_PROCESS;
}
else if (hhash->Phase == HAL_HASH_PHASE_PROCESS)
{
- /* if the IP has already been initialized, two cases are possible */
-
+ /* if the Peripheral has already been initialized, two cases are possible */
+
/* Process resumption time ... */
if (hhash->State == HAL_HASH_STATE_SUSPENDED)
{
@@ -2299,48 +2477,51 @@
{
/* Phase error */
hhash->State = HAL_HASH_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hhash);
-
+
/* Return function status */
return HAL_ERROR;
}
-
-
+
+
/* Write input buffer in Data register */
hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp);
if (hhash->Status != HAL_OK)
{
return hhash->Status;
}
-
+
/* If the process has not been suspended, carry on to digest calculation */
if (hhash->State != HAL_HASH_STATE_SUSPENDED)
{
/* Start the Digest calculation */
__HAL_HASH_START_DIGEST();
-
+
/* Wait for DCIS flag to be set */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
-
+
/* Read the message digest */
HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH());
-
+
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_READY;
-
+
+ /* Reset HASH state machine */
+ hhash->Phase = HAL_HASH_PHASE_READY;
+
}
-
+
/* Process Unlocked */
__HAL_UNLOCK(hhash);
-
+
/* Return function status */
return HAL_OK;
-
+
}
else
{
@@ -2353,27 +2534,30 @@
* @brief If not already done, initialize the HASH peripheral then
* processes pInBuffer.
* @note Field hhash->Phase of HASH handle is tested to check whether or not
- * the IP has already been initialized.
+ * the Peripheral has already been initialized.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes, must be a multiple of 4.
- * @param Algorithm: HASH algorithm.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
+ * @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
{
uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */
uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */
- HAL_HASH_StateTypeDef State_tmp = hhash->State;
-
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
+
/* Make sure the input buffer size (in bytes) is a multiple of 4 */
- assert_param(IS_HASH_POLLING_MULTIBUFFER_SIZE(Size));
+ if ((Size % 4U) != 0U)
+ {
+ return HAL_ERROR;
+ }
/* Initiate HASH processing in case of start or resumption */
if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
- {
+ {
/* Check input parameters */
if ((pInBuffer == NULL) || (Size == 0U))
{
@@ -2450,23 +2634,151 @@
/**
+ * @brief If not already done, initialize the HASH peripheral then
+ * processes pInBuffer in interruption mode.
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the Peripheral has already been initialized.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
+ * @param Algorithm HASH algorithm.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
+{
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
+ __IO uint32_t inputaddr = (uint32_t) pInBuffer;
+ uint32_t SizeVar = Size;
+
+ /* Make sure the input buffer size (in bytes) is a multiple of 4 */
+ if ((Size % 4U) != 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Initiate HASH processing in case of start or resumption */
+ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ {
+ /* Check input parameters */
+ if ((pInBuffer == NULL) || (Size == 0U))
+ {
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* If resuming the HASH processing */
+ if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+ }
+ else
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already be performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+ hhash->HashITCounter = 1;
+ }
+ else
+ {
+ hhash->HashITCounter = 3; /* 'cruise-speed' reached during a previous buffer processing */
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* If DINIS is equal to 0 (for example if an incomplete block has been previously
+ fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set.
+ Therefore, first words are manually entered until DINIS raises, or until there
+ is not more data to enter. */
+ while((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 0U))
+ {
+
+ /* Write input data 4 bytes at a time */
+ HASH->DIN = *(uint32_t*)inputaddr;
+ inputaddr+=4U;
+ SizeVar-=4U;
+ }
+
+ /* If DINIS is still not set or if all the data have been fed, stop here */
+ if ((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) || (SizeVar == 0U))
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+
+ /* otherwise, carry on in interrupt-mode */
+ hhash->HashInCount = SizeVar; /* Counter used to keep track of number of data
+ to be fed to the Peripheral */
+ hhash->pHashInBuffPtr = (uint8_t *)inputaddr; /* Points at data which will be fed to the Peripheral at
+ the next interruption */
+ /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain
+ the information describing where the HASH process is stopped.
+ These variables are used later on to resume the HASH processing at the
+ correct location. */
+
+ }
+
+ /* Set multi buffers accumulation flag */
+ hhash->Accumulation = 1U;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
+
+ /* Enable Data Input interrupt */
+ __HAL_HASH_ENABLE_IT(HASH_IT_DINI);
+
+ /* Return function status */
+ return HAL_OK;
+
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+
+}
+
+
+
+/**
* @brief Initialize the HASH peripheral, next process pInBuffer then
* read the computed digest in interruption mode.
* @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest.
- * @param Algorithm: HASH algorithm.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest.
+ * @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm)
{
HAL_HASH_StateTypeDef State_tmp = hhash->State;
+ __IO uint32_t inputaddr = (uint32_t) pInBuffer;
+ uint32_t polling_step = 0U;
+ uint32_t initialization_skipped = 0U;
+ uint32_t SizeVar = Size;
/* If State is ready or suspended, start or resume IT-based HASH processing */
if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
- {
+ {
/* Check input parameters */
if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL))
{
@@ -2490,12 +2802,12 @@
MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
/* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
+ __HAL_HASH_SET_NBVALIDBITS(SizeVar);
- hhash->HashInCount = Size; /* Counter used to keep track of number of data
- to be fed to the IP */
- hhash->pHashInBuffPtr = pInBuffer; /* Points at data which will be fed to the IP at
+ hhash->HashInCount = SizeVar; /* Counter used to keep track of number of data
+ to be fed to the Peripheral */
+ hhash->pHashInBuffPtr = pInBuffer; /* Points at data which will be fed to the Peripheral at
the next interruption */
/* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain
the information describing where the HASH process is stopped.
@@ -2504,10 +2816,82 @@
hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
}
+ else
+ {
+ initialization_skipped = 1; /* info user later on in case of multi-buffer */
+ }
/* Set the phase */
hhash->Phase = HAL_HASH_PHASE_PROCESS;
+ /* If DINIS is equal to 0 (for example if an incomplete block has been previously
+ fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set.
+ Therefore, first words are manually entered until DINIS raises. */
+ while((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 3U))
+ {
+ polling_step = 1U; /* note that some words are entered before enabling the interrupt */
+
+ /* Write input data 4 bytes at a time */
+ HASH->DIN = *(uint32_t*)inputaddr;
+ inputaddr+=4U;
+ SizeVar-=4U;
+ }
+
+ if (polling_step == 1U)
+ {
+ if (SizeVar == 0U)
+ {
+ /* If all the data have been entered at this point, it only remains to
+ read the digest */
+ hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
+
+ /* Start the Digest calculation */
+ __HAL_HASH_START_DIGEST();
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
+
+ /* Enable Interrupts */
+ __HAL_HASH_ENABLE_IT(HASH_IT_DCI);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+ {
+ /* It remains data to enter and the Peripheral is ready to trigger DINIE,
+ carry on as usual.
+ Update HashInCount and pHashInBuffPtr accordingly. */
+ hhash->HashInCount = SizeVar;
+ hhash->pHashInBuffPtr = (uint8_t *)inputaddr;
+ __HAL_HASH_SET_NBVALIDBITS(SizeVar); /* Update the configuration of the number of valid bits in last word of the message */
+ hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
+ if (initialization_skipped == 1U)
+ {
+ hhash->HashITCounter = 3; /* 'cruise-speed' reached during a previous buffer processing */
+ }
+ }
+ else
+ {
+ /* DINIS is not set but it remains a few data to enter (not enough for a full word).
+ Manually enter the last bytes before enabling DCIE. */
+ __HAL_HASH_SET_NBVALIDBITS(SizeVar);
+ HASH->DIN = *(uint32_t*)inputaddr;
+
+ /* Start the Digest calculation */
+ hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
+ __HAL_HASH_START_DIGEST();
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
+
+ /* Enable Interrupts */
+ __HAL_HASH_ENABLE_IT(HASH_IT_DCI);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ } /* if (polling_step == 1) */
+
+
/* Process Unlock */
__HAL_UNLOCK(hhash);
@@ -2527,17 +2911,17 @@
/**
* @brief Initialize the HASH peripheral then initiate a DMA transfer
- * to feed the input buffer to the IP.
+ * to feed the input buffer to the Peripheral.
* @note If MDMAT bit is set before calling this function (multi-buffer
* HASH processing case), the input buffer size (in bytes) must be
* a multiple of 4 otherwise, the HASH digest computation is corrupted.
* For the processing of the last buffer of the thread, MDMAT bit must
* be reset and the buffer length (in bytes) doesn't have to be a
* multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param Algorithm: HASH algorithm.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
@@ -2554,7 +2938,7 @@
/* If State is ready or suspended, start or resume polling-based HASH processing */
if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
- {
+ {
/* Check input parameters */
if ( (pInBuffer == NULL ) || (Size == 0U) ||
/* Check phase coherency. Phase must be
@@ -2624,39 +3008,34 @@
/* Enable the DMA In DMA Stream */
status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U)));
-
+
/* Enable DMA requests */
SET_BIT(HASH->CR, HASH_CR_DMAE);
-
+
/* Process Unlock */
__HAL_UNLOCK(hhash);
-
+
/* Return function status */
if (status != HAL_OK)
{
/* Update HASH state machine to error */
- hhash->State = HAL_HASH_STATE_ERROR;
+ hhash->State = HAL_HASH_STATE_ERROR;
}
- else
- {
- /* Change HASH state */
- hhash->State = HAL_HASH_STATE_READY;
- }
-
+
return status;
}
else
{
return HAL_BUSY;
- }
+ }
}
/**
* @brief Return the computed digest.
* @note The API waits for DCIS to be set then reads the computed digest.
- * @param hhash: HASH handle.
- * @param pOutBuffer: pointer to the computed digest.
- * @param Timeout: Timeout value.
+ * @param hhash HASH handle.
+ * @param pOutBuffer pointer to the computed digest.
+ * @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -2688,6 +3067,9 @@
/* Change the HASH state to ready */
hhash->State = HAL_HASH_STATE_READY;
+ /* Reset HASH state machine */
+ hhash->Phase = HAL_HASH_PHASE_READY;
+
/* Process UnLock */
__HAL_UNLOCK(hhash);
@@ -2709,21 +3091,21 @@
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest.
- * @param Timeout: Timeout value.
- * @param Algorithm: HASH algorithm.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest.
+ * @param Timeout Timeout value.
+ * @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
{
- HAL_HASH_StateTypeDef State_tmp = hhash->State;
-
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
+
/* If State is ready or suspended, start or resume polling-based HASH processing */
if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
- {
+ {
/* Check input parameters */
if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL))
{
@@ -2751,7 +3133,7 @@
}
/* Set the phase to Step 1 */
hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
- /* Resort to hhash internal fields to feed the IP.
+ /* Resort to hhash internal fields to feed the Peripheral.
Parameters will be updated in case of suspension to contain the proper
information at resumption time. */
hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */
@@ -2780,20 +3162,20 @@
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest.
- * @param Algorithm: HASH algorithm.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest.
+ * @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm)
{
- HAL_HASH_StateTypeDef State_tmp = hhash->State;
-
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
+
/* If State is ready or suspended, start or resume IT-based HASH processing */
if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
- {
+ {
/* Check input parameters */
if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL))
{
@@ -2824,7 +3206,7 @@
}
/* Resort to hhash internal fields hhash->pHashInBuffPtr and hhash->HashInCount
- to feed the IP whatever the HMAC step.
+ to feed the Peripheral whatever the HMAC step.
Lines below are set to start HMAC Step 1 processing where key is entered first. */
hhash->HashInCount = hhash->Init.KeySize; /* Key size */
hhash->pHashInBuffPtr = hhash->Init.pKey ; /* Key address */
@@ -2881,17 +3263,17 @@
/**
* @brief Initialize the HASH peripheral in HMAC mode then initiate the required
- * DMA transfers to feed the key and the input buffer to the IP.
+ * DMA transfers to feed the key and the input buffer to the Peripheral.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note In case of multi-buffer HMAC processing, the input buffer size (in bytes) must
* be a multiple of 4 otherwise, the HASH digest computation is corrupted.
* Only the length of the last buffer of the thread doesn't have to be a
* multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param Algorithm: HASH algorithm.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
@@ -2899,13 +3281,13 @@
uint32_t inputaddr;
uint32_t inputSize;
HAL_StatusTypeDef status ;
- HAL_HASH_StateTypeDef State_tmp = hhash->State;
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
/* Make sure the input buffer size (in bytes) is a multiple of 4 when digest calculation
is disabled (multi-buffer HMAC processing, MDMAT bit to be set) */
assert_param(IS_HMAC_DMA_MULTIBUFFER_SIZE(hhash, Size));
/* If State is ready or suspended, start or resume DMA-based HASH processing */
if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
- {
+ {
/* Check input parameters */
if ((pInBuffer == NULL ) || (Size == 0U) || (hhash->Init.pKey == NULL ) || (hhash->Init.KeySize == 0U) ||
/* Check phase coherency. Phase must be
@@ -3020,20 +3402,16 @@
/* Process Unlocked */
__HAL_UNLOCK(hhash);
-
+
/* Return function status */
if (status != HAL_OK)
{
/* Update HASH state machine to error */
hhash->State = HAL_HASH_STATE_ERROR;
}
- else
- {
- /* Change HASH state */
- hhash->State = HAL_HASH_STATE_READY;
- }
+
/* Return function status */
- return status;
+ return status;
}
else
{
diff --git a/Src/stm32f7xx_hal_hash_ex.c b/Src/stm32f7xx_hal_hash_ex.c
index e666d0a..fd61814 100644
--- a/Src/stm32f7xx_hal_hash_ex.c
+++ b/Src/stm32f7xx_hal_hash_ex.c
@@ -33,16 +33,21 @@
e.g. HAL_HASHEx_xxx_Start_DMA(). Note that in DMA mode, a call to
HAL_HASHEx_xxx_Finish() is then required to retrieve the digest.
- (#)Multi-buffer processing is possible in polling and DMA mode.
+ (#)Multi-buffer processing is possible in polling, interrupt and DMA modes.
(##) In polling mode, only multi-buffer HASH processing is possible.
API HAL_HASHEx_xxx_Accumulate() must be called for each input buffer, except for the last one.
- User must resort to HAL_HASHEx_xxx_Start() to enter the last one and retrieve as
+ User must resort to HAL_HASHEx_xxx_Accumulate_End() to enter the last one and retrieve as
+ well the computed digest.
+
+ (##) In interrupt mode, API HAL_HASHEx_xxx_Accumulate_IT() must be called for each input buffer,
+ except for the last one.
+ User must resort to HAL_HASHEx_xxx_Accumulate_End_IT() to enter the last one and retrieve as
well the computed digest.
(##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
(+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
- From that point, each buffer can be fed to the IP thru HAL_HASHEx_xxx_Start_DMA() API.
+ From that point, each buffer can be fed to the Peripheral thru HAL_HASHEx_xxx_Start_DMA() API.
Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
macro then wrap-up the HASH processing in feeding the last input buffer thru the
same API HAL_HASHEx_xxx_Start_DMA(). The digest can then be retrieved with a call to
@@ -50,7 +55,7 @@
(+++) HMAC processing (MD-5, SHA-1, SHA-224 and SHA-256 must all resort to
extended functions): after initialization, the key and the first input buffer are entered
- in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
+ in the Peripheral with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
starts step 2.
The following buffers are next entered with the API HAL_HMACEx_xxx_Step2_DMA(). At this
point, the HMAC processing is still carrying out step 2.
@@ -112,17 +117,19 @@
the hash value using one of the following algorithms:
(+) SHA224
(++) HAL_HASHEx_SHA224_Start()
- (++) HAL_HASHEx_SHA224_Accumulate()
+ (++) HAL_HASHEx_SHA224_Accmlt()
+ (++) HAL_HASHEx_SHA224_Accmlt_End()
(+) SHA256
(++) HAL_HASHEx_SHA256_Start()
- (++) HAL_HASHEx_SHA256_Accumulate()
+ (++) HAL_HASHEx_SHA256_Accmlt()
+ (++) HAL_HASHEx_SHA256_Accmlt_End()
[..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().
[..] In case of multi-buffer HASH processing (a single digest is computed while
- several buffers are fed to the IP), the user can resort to successive calls
+ several buffers are fed to the Peripheral), the user can resort to successive calls
to HAL_HASHEx_xxx_Accumulate() and wrap-up the digest computation by a call
- to HAL_HASHEx_xxx_Start().
+ to HAL_HASHEx_xxx_Accumulate_End().
@endverbatim
* @{
@@ -133,11 +140,11 @@
* @brief Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then
* read the computed digest.
* @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
- * @param Timeout: Timeout value
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
+ * @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -148,37 +155,52 @@
/**
* @brief If not already done, initialize the HASH peripheral in SHA224 mode then
* processes pInBuffer.
- * @note Consecutive calls to HAL_HASHEx_SHA224_Accumulate() can be used to feed
- * several input buffers back-to-back to the IP that will yield a single
+ * @note Consecutive calls to HAL_HASHEx_SHA224_Accmlt() can be used to feed
+ * several input buffers back-to-back to the Peripheral that will yield a single
* HASH signature once all buffers have been entered. Wrap-up of input
* buffers feeding and retrieval of digest is done by a call to
- * HAL_HASHEx_SHA224_Start().
+ * HAL_HASHEx_SHA224_Accmlt_End().
* @note Field hhash->Phase of HASH handle is tested to check whether or not
- * the IP has already been initialized.
- * @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA224_Start()
- * to read it, feeding at the same time the last input buffer to the IP.
+ * the Peripheral has already been initialized.
+ * @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA224_Accmlt_End()
+ * to read it, feeding at the same time the last input buffer to the Peripheral.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
- * HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Start() is able
+ * HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Accmlt_End() is able
* to manage the ending buffer with a length in bytes not a multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes, must be a multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224);
}
/**
+ * @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA224_Accmlt() API.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
+ * @param Timeout Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
+}
+
+/**
* @brief Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then
* read the computed digest.
* @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
- * @param Timeout: Timeout value
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
+ * @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -189,28 +211,42 @@
/**
* @brief If not already done, initialize the HASH peripheral in SHA256 mode then
* processes pInBuffer.
- * @note Consecutive calls to HAL_HASHEx_SHA256_Accumulate() can be used to feed
- * several input buffers back-to-back to the IP that will yield a single
+ * @note Consecutive calls to HAL_HASHEx_SHA256_Accmlt() can be used to feed
+ * several input buffers back-to-back to the Peripheral that will yield a single
* HASH signature once all buffers have been entered. Wrap-up of input
* buffers feeding and retrieval of digest is done by a call to
- * HAL_HASHEx_SHA256_Start().
+ * HAL_HASHEx_SHA256_Accmlt_End().
* @note Field hhash->Phase of HASH handle is tested to check whether or not
- * the IP has already been initialized.
- * @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA256_Start()
- * to read it, feeding at the same time the last input buffer to the IP.
+ * the Peripheral has already been initialized.
+ * @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA256_Accmlt_End()
+ * to read it, feeding at the same time the last input buffer to the Peripheral.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
- * HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Start() is able
+ * HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Accmlt_End() is able
* to manage the ending buffer with a length in bytes not a multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes, must be a multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256);
}
+/**
+ * @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA256_Accmlt() API.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
+ * @param Timeout Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
+}
/**
* @}
@@ -227,8 +263,12 @@
the hash value using one of the following algorithms:
(+) SHA224
(++) HAL_HASHEx_SHA224_Start_IT()
+ (++) HAL_HASHEx_SHA224_Accmlt_IT()
+ (++) HAL_HASHEx_SHA224_Accmlt_End_IT()
(+) SHA256
(++) HAL_HASHEx_SHA256_Start_IT()
+ (++) HAL_HASHEx_SHA256_Accmlt_IT()
+ (++) HAL_HASHEx_SHA256_Accmlt_End_IT()
@endverbatim
* @{
@@ -239,10 +279,10 @@
* @brief Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then
* read the computed digest in interruption mode.
* @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@@ -251,13 +291,50 @@
}
/**
+ * @brief If not already done, initialize the HASH peripheral in SHA224 mode then
+ * processes pInBuffer in interruption mode.
+ * @note Consecutive calls to HAL_HASHEx_SHA224_Accmlt_IT() can be used to feed
+ * several input buffers back-to-back to the Peripheral that will yield a single
+ * HASH signature once all buffers have been entered. Wrap-up of input
+ * buffers feeding and retrieval of digest is done by a call to
+ * HAL_HASHEx_SHA224_Accmlt_End_IT().
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the Peripheral has already been initialized.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Accmlt_End_IT() is able
+ * to manage the ending buffer with a length in bytes not a multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224);
+}
+
+/**
+ * @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA224_Accmlt_IT() API.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224);
+}
+
+/**
* @brief Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then
* read the computed digest in interruption mode.
* @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@@ -266,6 +343,43 @@
}
/**
+ * @brief If not already done, initialize the HASH peripheral in SHA256 mode then
+ * processes pInBuffer in interruption mode.
+ * @note Consecutive calls to HAL_HASHEx_SHA256_Accmlt_IT() can be used to feed
+ * several input buffers back-to-back to the Peripheral that will yield a single
+ * HASH signature once all buffers have been entered. Wrap-up of input
+ * buffers feeding and retrieval of digest is done by a call to
+ * HAL_HASHEx_SHA256_Accmlt_End_IT().
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the Peripheral has already been initialized.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Accmlt_End_IT() is able
+ * to manage the ending buffer with a length in bytes not a multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256);
+}
+
+/**
+ * @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA256_Accmlt_IT() API.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256);
+}
+
+/**
* @}
*/
@@ -285,7 +399,7 @@
(++) HAL_HASHEx_SHA256_Start_DMA()
(++) HAL_HASHEx_SHA256_Finish()
- [..] When resorting to DMA mode to enter the data in the IP, user must resort
+ [..] When resorting to DMA mode to enter the data in the Peripheral, user must resort
to HAL_HASHEx_xxx_Start_DMA() then read the resulting digest with
HAL_HASHEx_xxx_Finish().
@@ -303,12 +417,12 @@
/**
* @brief Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer
- * to feed the input buffer to the IP.
+ * to feed the input buffer to the Peripheral.
* @note Once the DMA transfer is finished, HAL_HASHEx_SHA224_Finish() API must
* be called to retrieve the computed digest.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -321,9 +435,9 @@
* @note The API waits for DCIS to be set then reads the computed digest.
* @note HAL_HASHEx_SHA224_Finish() can be used as well to retrieve the digest in
* HMAC SHA224 mode.
- * @param hhash: HASH handle.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
- * @param Timeout: Timeout value.
+ * @param hhash HASH handle.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
+ * @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -333,12 +447,12 @@
/**
* @brief Initialize the HASH peripheral in SHA256 mode then initiate a DMA transfer
- * to feed the input buffer to the IP.
+ * to feed the input buffer to the Peripheral.
* @note Once the DMA transfer is finished, HAL_HASHEx_SHA256_Finish() API must
* be called to retrieve the computed digest.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -351,9 +465,9 @@
* @note The API waits for DCIS to be set then reads the computed digest.
* @note HAL_HASHEx_SHA256_Finish() can be used as well to retrieve the digest in
* HMAC SHA256 mode.
- * @param hhash: HASH handle.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
- * @param Timeout: Timeout value.
+ * @param hhash HASH handle.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
+ * @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -391,11 +505,11 @@
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
- * @param Timeout: Timeout value.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
+ * @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -409,11 +523,11 @@
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
- * @param Timeout: Timeout value.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
+ * @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -452,10 +566,10 @@
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@@ -469,10 +583,10 @@
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@@ -502,7 +616,7 @@
(+) SHA256
(++) HAL_HMACEx_SHA256_Start_DMA()
- [..] When resorting to DMA mode to enter the data in the IP for HMAC processing,
+ [..] When resorting to DMA mode to enter the data in the Peripheral for HMAC processing,
user must resort to HAL_HMACEx_xxx_Start_DMA() then read the resulting digest
with HAL_HASHEx_xxx_Finish().
@@ -515,7 +629,7 @@
/**
* @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required
- * DMA transfers to feed the key and the input buffer to the IP.
+ * DMA transfers to feed the key and the input buffer to the Peripheral.
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA224_Finish() API must be called to retrieve
* the computed digest.
@@ -527,9 +641,9 @@
* For the processing of the last buffer of the thread, MDMAT bit must
* be reset and the buffer length (in bytes) doesn't have to be a
* multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -539,7 +653,7 @@
/**
* @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required
- * DMA transfers to feed the key and the input buffer to the IP.
+ * DMA transfers to feed the key and the input buffer to the Peripheral.
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
@@ -551,9 +665,9 @@
* For the processing of the last buffer of the thread, MDMAT bit must
* be reset and the buffer length (in bytes) doesn't have to be a
* multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -597,13 +711,13 @@
calling HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
intiates step 2 with the first input buffer.
- [..] The following buffers are next fed to the IP with a call to the API
+ [..] The following buffers are next fed to the Peripheral with a call to the API
HAL_HMACEx_xxx_Step2_DMA(). There may be several consecutive calls
to this API.
[..] Multi-buffer DMA-based HMAC computation is wrapped up by a call to
HAL_HMACEx_xxx_Step2_3_DMA(). This finishes step 2 in feeding the last input
- buffer to the IP then carries out step 3.
+ buffer to the Peripheral then carries out step 3.
[..] Digest is retrieved by a call to HAL_HASH_xxx_Finish() for MD-5 or
SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 or SHA-256.
@@ -618,18 +732,18 @@
/**
* @brief MD5 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
- * @note Step 1 consists in writing the inner hash function key in the IP,
+ * @note Step 1 consists in writing the inner hash function key in the Peripheral,
* step 2 consists in writing the message text.
* @note The API carries out the HMAC step 1 then starts step 2 with
- * the first buffer entered to the IP. DCAL bit is not automatically set after
+ * the first buffer entered to the Peripheral. DCAL bit is not automatically set after
* the message buffer feeding, allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -640,7 +754,7 @@
/**
* @brief MD5 HMAC step 2 in multi-buffer DMA mode.
- * @note Step 2 consists in writing the message text in the IP.
+ * @note Step 2 consists in writing the message text in the Peripheral.
* @note The API carries on the HMAC step 2, applied to the buffer entered as input
* parameter. DCAL bit is not automatically set after the message buffer feeding,
* allowing other messages DMA transfers to occur.
@@ -648,9 +762,9 @@
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -664,7 +778,7 @@
/**
* @brief MD5 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
- * @note Step 2 consists in writing the message text in the IP,
+ * @note Step 2 consists in writing the message text in the Peripheral,
* step 3 consists in writing the outer hash function key.
* @note The API wraps up the HMAC step 2 in processing the buffer entered as input
* parameter (the input buffer must be the last one of the multi-buffer thread)
@@ -674,9 +788,9 @@
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -688,18 +802,18 @@
/**
* @brief SHA1 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
- * @note Step 1 consists in writing the inner hash function key in the IP,
+ * @note Step 1 consists in writing the inner hash function key in the Peripheral,
* step 2 consists in writing the message text.
* @note The API carries out the HMAC step 1 then starts step 2 with
- * the first buffer entered to the IP. DCAL bit is not automatically set after
+ * the first buffer entered to the Peripheral. DCAL bit is not automatically set after
* the message buffer feeding, allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -710,7 +824,7 @@
/**
* @brief SHA1 HMAC step 2 in multi-buffer DMA mode.
- * @note Step 2 consists in writing the message text in the IP.
+ * @note Step 2 consists in writing the message text in the Peripheral.
* @note The API carries on the HMAC step 2, applied to the buffer entered as input
* parameter. DCAL bit is not automatically set after the message buffer feeding,
* allowing other messages DMA transfers to occur.
@@ -718,9 +832,9 @@
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -734,7 +848,7 @@
/**
* @brief SHA1 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
- * @note Step 2 consists in writing the message text in the IP,
+ * @note Step 2 consists in writing the message text in the Peripheral,
* step 3 consists in writing the outer hash function key.
* @note The API wraps up the HMAC step 2 in processing the buffer entered as input
* parameter (the input buffer must be the last one of the multi-buffer thread)
@@ -744,9 +858,9 @@
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -757,18 +871,18 @@
/**
* @brief SHA224 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
- * @note Step 1 consists in writing the inner hash function key in the IP,
+ * @note Step 1 consists in writing the inner hash function key in the Peripheral,
* step 2 consists in writing the message text.
* @note The API carries out the HMAC step 1 then starts step 2 with
- * the first buffer entered to the IP. DCAL bit is not automatically set after
+ * the first buffer entered to the Peripheral. DCAL bit is not automatically set after
* the message buffer feeding, allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -779,7 +893,7 @@
/**
* @brief SHA224 HMAC step 2 in multi-buffer DMA mode.
- * @note Step 2 consists in writing the message text in the IP.
+ * @note Step 2 consists in writing the message text in the Peripheral.
* @note The API carries on the HMAC step 2, applied to the buffer entered as input
* parameter. DCAL bit is not automatically set after the message buffer feeding,
* allowing other messages DMA transfers to occur.
@@ -787,9 +901,9 @@
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -803,7 +917,7 @@
/**
* @brief SHA224 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
- * @note Step 2 consists in writing the message text in the IP,
+ * @note Step 2 consists in writing the message text in the Peripheral,
* step 3 consists in writing the outer hash function key.
* @note The API wraps up the HMAC step 2 in processing the buffer entered as input
* parameter (the input buffer must be the last one of the multi-buffer thread)
@@ -813,9 +927,9 @@
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -826,18 +940,18 @@
/**
* @brief SHA256 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
- * @note Step 1 consists in writing the inner hash function key in the IP,
+ * @note Step 1 consists in writing the inner hash function key in the Peripheral,
* step 2 consists in writing the message text.
* @note The API carries out the HMAC step 1 then starts step 2 with
- * the first buffer entered to the IP. DCAL bit is not automatically set after
+ * the first buffer entered to the Peripheral. DCAL bit is not automatically set after
* the message buffer feeding, allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -848,7 +962,7 @@
/**
* @brief SHA256 HMAC step 2 in multi-buffer DMA mode.
- * @note Step 2 consists in writing the message text in the IP.
+ * @note Step 2 consists in writing the message text in the Peripheral.
* @note The API carries on the HMAC step 2, applied to the buffer entered as input
* parameter. DCAL bit is not automatically set after the message buffer feeding,
* allowing other messages DMA transfers to occur.
@@ -856,9 +970,9 @@
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -872,7 +986,7 @@
/**
* @brief SHA256 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
- * @note Step 2 consists in writing the message text in the IP,
+ * @note Step 2 consists in writing the message text in the Peripheral,
* step 3 consists in writing the outer hash function key.
* @note The API wraps up the HMAC step 2 in processing the buffer entered as input
* parameter (the input buffer must be the last one of the multi-buffer thread)
@@ -882,9 +996,9 @@
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
diff --git a/Src/stm32f7xx_hal_hcd.c b/Src/stm32f7xx_hal_hcd.c
index 92a6277..735d7d1 100644
--- a/Src/stm32f7xx_hal_hcd.c
+++ b/Src/stm32f7xx_hal_hcd.c
@@ -42,11 +42,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * @attention
- *
- * <h2><center>© Copyright (c) YYYY STMicroelectronics.
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -114,6 +110,8 @@
*/
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
{
+ USB_OTG_GlobalTypeDef *USBx;
+
/* Check the HCD handle allocation */
if (hhcd == NULL)
{
@@ -123,6 +121,8 @@
/* Check the parameters */
assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
+ USBx = hhcd->Instance;
+
if (hhcd->State == HAL_HCD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@@ -151,6 +151,12 @@
hhcd->State = HAL_HCD_STATE_BUSY;
+ /* Disable DMA mode for FS instance */
+ if ((USBx->CID & (0x1U << 8)) == 0U)
+ {
+ hhcd->Init.dma_enable = 0U;
+ }
+
/* Disable the Interrupts */
__HAL_HCD_DISABLE(hhcd);
@@ -367,14 +373,13 @@
uint16_t length,
uint8_t do_ping)
{
- UNUSED(do_ping);
-
hhcd->hc[ch_num].ep_is_in = direction;
hhcd->hc[ch_num].ep_type = ep_type;
if (token == 0U)
{
hhcd->hc[ch_num].data_pid = HC_PID_SETUP;
+ hhcd->hc[ch_num].do_ping = do_ping;
}
else
{
@@ -528,20 +533,19 @@
/* Handle Host Disconnect Interrupts */
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
{
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
- /* Cleanup HPRT */
- USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \
- USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
-
- /* Handle Host Port Disconnect Interrupt */
+ if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U)
+ {
+ /* Handle Host Port Disconnect Interrupt */
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
- hhcd->DisconnectCallback(hhcd);
+ hhcd->DisconnectCallback(hhcd);
#else
- HAL_HCD_Disconnect_Callback(hhcd);
+ HAL_HCD_Disconnect_Callback(hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
- (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
- __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
+ (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
+ }
}
/* Handle Host Port Interrupts */
@@ -1003,6 +1007,7 @@
__HAL_HCD_ENABLE(hhcd);
(void)USB_DriveVbus(hhcd->Instance, 1U);
__HAL_UNLOCK(hhcd);
+
return HAL_OK;
}
@@ -1017,6 +1022,7 @@
__HAL_LOCK(hhcd);
(void)USB_StopHost(hhcd->Instance);
__HAL_UNLOCK(hhcd);
+
return HAL_OK;
}
@@ -1164,6 +1170,13 @@
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
}
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_BBERR) == USB_OTG_HCINT_BBERR)
+ {
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_BBERR);
+ hhcd->hc[ch_num].state = HC_BBLERR;
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ }
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK);
@@ -1225,6 +1238,17 @@
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
+ else if (hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC)
+ {
+ hhcd->hc[ch_num].urb_state = URB_DONE;
+ hhcd->hc[ch_num].toggle_in ^= 1U;
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#else
+ HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+ }
else
{
/* ... */
@@ -1273,6 +1297,11 @@
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(ch_num)->HCCHAR = tmpreg;
}
+ else if (hhcd->hc[ch_num].state == HC_BBLERR)
+ {
+ hhcd->hc[ch_num].ErrCnt++;
+ hhcd->hc[ch_num].urb_state = URB_ERROR;
+ }
else
{
/* ... */
@@ -1300,6 +1329,7 @@
(hhcd->hc[ch_num].ep_type == EP_TYPE_BULK))
{
hhcd->hc[ch_num].ErrCnt = 0U;
+
if (hhcd->Init.dma_enable == 0U)
{
hhcd->hc[ch_num].state = HC_NAK;
@@ -1548,8 +1578,6 @@
{
if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
{
- USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
-
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->ConnectCallback(hhcd);
#else
@@ -1586,10 +1614,8 @@
}
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->PortEnabledCallback(hhcd);
- hhcd->ConnectCallback(hhcd);
#else
HAL_HCD_PortEnabled_Callback(hhcd);
- HAL_HCD_Connect_Callback(hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
@@ -1600,12 +1626,6 @@
#else
HAL_HCD_PortDisabled_Callback(hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
-
- /* Cleanup HPRT */
- USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \
- USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
-
- USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
}
}
diff --git a/Src/stm32f7xx_hal_i2c.c b/Src/stm32f7xx_hal_i2c.c
index d74bb1d..4b3cee4 100644
--- a/Src/stm32f7xx_hal_i2c.c
+++ b/Src/stm32f7xx_hal_i2c.c
@@ -223,12 +223,12 @@
*** Callback registration ***
=============================================
-
+ [..]
The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()
to register an interrupt callback.
-
+ [..]
Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:
(+) MasterTxCpltCallback : callback for Master transmission end of transfer.
(+) MasterRxCpltCallback : callback for Master reception end of transfer.
@@ -243,9 +243,9 @@
(+) MspDeInitCallback : callback for Msp DeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
-
+ [..]
For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().
-
+ [..]
Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default
weak function.
@ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
@@ -262,9 +262,9 @@
(+) AbortCpltCallback : callback for abort completion process.
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
-
+ [..]
For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().
-
+ [..]
By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().
@@ -273,7 +273,7 @@
these callbacks are null (not registered beforehand).
If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
-
+ [..]
Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
@@ -281,7 +281,7 @@
Then, the user first registers the MspInit/MspDeInit user callbacks
using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()
or @ref HAL_I2C_Init() function.
-
+ [..]
When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@@ -4737,6 +4737,13 @@
/* Process locked */
__HAL_LOCK(hi2c);
+ /* Check if STOPF is set */
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ {
+ /* Call I2C Slave complete process */
+ I2C_ITSlaveCplt(hi2c, tmpITFlags);
+ }
+
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
@@ -4788,9 +4795,6 @@
{
if (hi2c->XferCount > 0U)
{
- /* Remove RXNE flag on temporary variable as read done */
- tmpITFlags &= ~I2C_FLAG_RXNE;
-
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
@@ -4844,13 +4848,6 @@
/* Nothing to do */
}
- /* Check if STOPF is set */
- if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
- {
- /* Call I2C Slave complete process */
- I2C_ITSlaveCplt(hi2c, tmpITFlags);
- }
-
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -5008,6 +5005,13 @@
/* Process locked */
__HAL_LOCK(hi2c);
+ /* Check if STOPF is set */
+ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ {
+ /* Call I2C Slave complete process */
+ I2C_ITSlaveCplt(hi2c, ITFlags);
+ }
+
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
@@ -5092,11 +5096,6 @@
{
I2C_ITAddrCplt(hi2c, ITFlags);
}
- else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
- {
- /* Call I2C Slave complete process */
- I2C_ITSlaveCplt(hi2c, ITFlags);
- }
else
{
/* Nothing to do */
diff --git a/Src/stm32f7xx_hal_irda.c b/Src/stm32f7xx_hal_irda.c
index e79476f..03675cb 100644
--- a/Src/stm32f7xx_hal_irda.c
+++ b/Src/stm32f7xx_hal_irda.c
@@ -206,7 +206,7 @@
#define IRDA_TEACK_REACK_TIMEOUT 1000U /*!< IRDA TX or RX enable acknowledge time-out value */
#define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
- | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
+ | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */
@@ -239,7 +239,8 @@
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout);
static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
@@ -475,7 +476,8 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
+ pIRDA_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -714,6 +716,7 @@
While receiving data, transmission should be avoided as the data to be transmitted
could be corrupted.
+ [..]
(#) There are two modes of transfer:
(++) Blocking mode: the communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
@@ -751,28 +754,28 @@
(++) HAL_IRDA_ErrorCallback()
(#) Non-Blocking mode transfers could be aborted using Abort API's :
- (+) HAL_IRDA_Abort()
- (+) HAL_IRDA_AbortTransmit()
- (+) HAL_IRDA_AbortReceive()
- (+) HAL_IRDA_Abort_IT()
- (+) HAL_IRDA_AbortTransmit_IT()
- (+) HAL_IRDA_AbortReceive_IT()
+ (++) HAL_IRDA_Abort()
+ (++) HAL_IRDA_AbortTransmit()
+ (++) HAL_IRDA_AbortReceive()
+ (++) HAL_IRDA_Abort_IT()
+ (++) HAL_IRDA_AbortTransmit_IT()
+ (++) HAL_IRDA_AbortReceive_IT()
(#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
- (+) HAL_IRDA_AbortCpltCallback()
- (+) HAL_IRDA_AbortTransmitCpltCallback()
- (+) HAL_IRDA_AbortReceiveCpltCallback()
+ (++) HAL_IRDA_AbortCpltCallback()
+ (++) HAL_IRDA_AbortTransmitCpltCallback()
+ (++) HAL_IRDA_AbortReceiveCpltCallback()
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
- (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
- and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
- If user wants to abort it, Abort services should be called by user.
- (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
- This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
+ (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
+ If user wants to abort it, Abort services should be called by user.
+ (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
@endverbatim
* @{
@@ -780,10 +783,13 @@
/**
* @brief Send an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be sent.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
* @param Timeout Specify timeout value.
* @retval HAL status
*/
@@ -866,10 +872,13 @@
/**
* @brief Receive an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @param Timeout Specify timeout value.
* @retval HAL status
*/
@@ -954,10 +963,13 @@
/**
* @brief Send an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be sent.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@@ -996,10 +1008,13 @@
/**
* @brief Receive an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@@ -1045,10 +1060,13 @@
/**
* @brief Send an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be sent.
+ * @param pData pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@@ -1120,12 +1138,15 @@
/**
* @brief Receive an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
* @note When the IRDA parity is enabled (PCE = 1), the received data contains
* the parity bit (MSB position).
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@@ -1353,7 +1374,7 @@
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
{
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
@@ -1439,7 +1460,7 @@
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
{
/* Disable TXEIE and TCIE interrupts */
@@ -1491,7 +1512,7 @@
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
@@ -1549,7 +1570,7 @@
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
{
uint32_t abortcplt = 1U;
@@ -1681,7 +1702,7 @@
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
{
/* Disable TXEIE and TCIE interrupts */
@@ -1759,7 +1780,7 @@
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
@@ -2150,7 +2171,8 @@
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
{
/* Return IRDA handle state */
- uint32_t temp1, temp2;
+ uint32_t temp1;
+ uint32_t temp2;
temp1 = (uint32_t)hirda->gState;
temp2 = (uint32_t)hirda->RxState;
@@ -2212,6 +2234,7 @@
uint32_t tmpreg;
IRDA_ClockSourceTypeDef clocksource;
HAL_StatusTypeDef ret = HAL_OK;
+ uint32_t pclk;
/* Check the communication parameters */
assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
@@ -2235,7 +2258,7 @@
/*-------------------------- USART GTPR Configuration ----------------------*/
- MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, hirda->Init.Prescaler);
+ MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)hirda->Init.Prescaler);
/*-------------------------- USART BRR Configuration -----------------------*/
IRDA_GETCLOCKSOURCE(hirda, clocksource);
@@ -2243,16 +2266,19 @@
switch (clocksource)
{
case IRDA_CLOCKSOURCE_PCLK1:
- tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate));
+ pclk = HAL_RCC_GetPCLK1Freq();
+ tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate));
break;
case IRDA_CLOCKSOURCE_PCLK2:
- tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate));
+ pclk = HAL_RCC_GetPCLK2Freq();
+ tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate));
break;
case IRDA_CLOCKSOURCE_HSI:
tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate));
break;
case IRDA_CLOCKSOURCE_SYSCLK:
- tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), hirda->Init.BaudRate));
+ pclk = HAL_RCC_GetSysClockFreq();
+ tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate));
break;
case IRDA_CLOCKSOURCE_LSE:
tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate));
@@ -2322,7 +2348,8 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
while ((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
diff --git a/Src/stm32f7xx_hal_lptim.c b/Src/stm32f7xx_hal_lptim.c
index 1b9a014..09fed9a 100644
--- a/Src/stm32f7xx_hal_lptim.c
+++ b/Src/stm32f7xx_hal_lptim.c
@@ -3,14 +3,14 @@
* @file stm32f7xx_hal_lptim.c
* @author MCD Application Team
* @brief LPTIM HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Low Power Timer (LPTIM) peripheral:
* + Initialization and de-initialization functions.
* + Start/Stop operation functions in polling mode.
* + Start/Stop operation functions in interrupt mode.
* + Reading operation functions.
* + Peripheral State functions.
- *
+ *
@verbatim
==============================================================================
##### How to use this driver #####
@@ -20,116 +20,120 @@
(#)Initialize the LPTIM low level resources by implementing the
HAL_LPTIM_MspInit():
- (##) Enable the LPTIM interface clock using __LPTIMx_CLK_ENABLE().
- (##) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
+ (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE().
+ (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
(+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
(+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
(+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
-
+
(#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
configures mainly:
- (##) The instance: LPTIM1.
- (##) Clock: the counter clock.
- (+++) Source: it can be either the ULPTIM input (IN1) or one of
+ (++) The instance: LPTIM1.
+ (++) Clock: the counter clock.
+ (+++) Source : it can be either the ULPTIM input (IN1) or one of
the internal clock; (APB, LSE, LSI or MSI).
- (+++) Prescaler: select the clock divider.
- (##) UltraLowPowerClock : To be used only if the ULPTIM is selected
+ (+++) Prescaler: select the clock divider.
+ (++) UltraLowPowerClock : To be used only if the ULPTIM is selected
as counter clock source.
- (+++) Polarity: polarity of the active edge for the counter unit
+ (+++) Polarity: polarity of the active edge for the counter unit
if the ULPTIM input is selected.
- (+++) SampleTime: clock sampling time to configure the clock glitch
- filter.
- (##) Trigger: How the counter start.
- (+++) Source: trigger can be software or one of the hardware triggers.
- (+++) ActiveEdge: only for hardware trigger.
- (+++) SampleTime: trigger sampling time to configure the trigger
+ (+++) SampleTime: clock sampling time to configure the clock glitch
+ filter.
+ (++) Trigger: How the counter start.
+ (+++) Source: trigger can be software or one of the hardware triggers.
+ (+++) ActiveEdge : only for hardware trigger.
+ (+++) SampleTime : trigger sampling time to configure the trigger
glitch filter.
- (##) OutputPolarity: 2 opposite polarities are possibles.
- (##) UpdateMode: specifies whether the update of the autoreload and
+ (++) OutputPolarity : 2 opposite polarities are possible.
+ (++) UpdateMode: specifies whether the update of the autoreload and
the compare values is done immediately or after the end of current
- period.
-
+ period.
+
(#)Six modes are available:
-
- (##) PWM Mode: To generate a PWM signal with specified period and pulse,
+
+ (++) PWM Mode: To generate a PWM signal with specified period and pulse,
call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
mode.
-
- (##) One Pulse Mode: To generate pulse with specified width in response
+
+ (++) One Pulse Mode: To generate pulse with specified width in response
to a stimulus, call HAL_LPTIM_OnePulse_Start() or
HAL_LPTIM_OnePulse_Start_IT() for interruption mode.
-
- (##) Set once Mode: In this mode, the output changes the level (from
+
+ (++) Set once Mode: In this mode, the output changes the level (from
low level to high level if the output polarity is configured high, else
- the opposite) when a compare match occurs. To start this mode, call
+ the opposite) when a compare match occurs. To start this mode, call
HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
interruption mode.
-
- (##) Encoder Mode: To use the encoder interface call
- HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
- interruption mode.
-
- (##) Time out Mode: an active edge on one selected trigger input rests
+
+ (++) Encoder Mode: To use the encoder interface call
+ HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
+ interruption mode. Only available for LPTIM1 instance.
+
+ (++) Time out Mode: an active edge on one selected trigger input rests
the counter. The first trigger event will start the timer, any
successive trigger event will reset the counter and the timer will
- restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
+ restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
HAL_LPTIM_TimeOut_Start_IT() for interruption mode.
-
- (##) Counter Mode: counter can be used to count external events on
- the LPTIM Input1 or it can be used to count internal clock cycles.
- To start this mode, call HAL_LPTIM_Counter_Start() or
- HAL_LPTIM_Counter_Start_IT() for interruption mode.
-
+ (++) Counter Mode: counter can be used to count external events on
+ the LPTIM Input1 or it can be used to count internal clock cycles.
+ To start this mode, call HAL_LPTIM_Counter_Start() or
+ HAL_LPTIM_Counter_Start_IT() for interruption mode.
+
+
(#) User can stop any process by calling the corresponding API:
HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
already started in interruption mode.
-
- (#) Call HAL_LPTIM_DeInit() to deinitialize the LPTIM peripheral.
- *** Callback registration ***
+ (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit().
+
+ *** Callback registration ***
=============================================
-
- The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
+ [..]
+ The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
-
+ [..]
Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback.
@ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
the Callback ID and a pointer to the user callback function.
-
- Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the default
- weak function.
+ [..]
+ Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the
+ default weak function.
@ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
-
+ [..]
These functions allow to register/unregister following callbacks:
- (+) MspInitCallback : LPTIM Msp Init Callback.
- (+) MspDeInitCallback : LPTIM Msp DeInit Callback.
- (+) CompareMatchCallback : LPTIM Compare Match Init Callback.
- (+) AutoReloadMatchCallback : LPTIM Auto Reload Match Callback.
- (+) TriggerCallback : LPTIM Trigger Callback.
- (+) CompareWriteCallback : LPTIM Compare Write Callback.
- (+) AutoReloadWriteCallback : LPTIM Auto Reload Write Callback.
- (+) DirectionUpCallback : LPTIM Direction Up Callback.
- (+) DirectionDownCallback : LPTIM Direction Down Callback.
- By default, after the @ref HAL_LPTIM_Init and when the state is HAL_LPTIM_STATE_RESET
+ (+) MspInitCallback : LPTIM Base Msp Init Callback.
+ (+) MspDeInitCallback : LPTIM Base Msp DeInit Callback.
+ (+) CompareMatchCallback : Compare match Callback.
+ (+) AutoReloadMatchCallback : Auto-reload match Callback.
+ (+) TriggerCallback : External trigger event detection Callback.
+ (+) CompareWriteCallback : Compare register write complete Callback.
+ (+) AutoReloadWriteCallback : Auto-reload register write complete Callback.
+ (+) DirectionUpCallback : Up-counting direction change Callback.
+ (+) DirectionDownCallback : Down-counting direction change Callback.
+
+ [..]
+ By default, after the Init and when the state is HAL_LPTIM_STATE_RESET
all interrupt callbacks are set to the corresponding weak functions:
- examples @ref HAL_LPTIM_CompareMatchCallback(), @ref HAL_LPTIM_AutoReloadMatchCallback().
+ examples @ref HAL_LPTIM_TriggerCallback(), @ref HAL_LPTIM_CompareMatchCallback().
+ [..]
Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
- functionalities in the @ref HAL_LPTIM_Init/@ref HAL_LPTIM_DeInit only when these
- callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null,
- the @ref HAL_LPTIM_Init/@ref HAL_LPTIM_DeInit keep and use the user MspInit/MspDeInit
- callbacks (registered beforehand)
+ functionalities in the Init/DeInit only when these callbacks are null
+ (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+ [..]
Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only.
Exception done MspInit/MspDeInit that can be registered/unregistered
- in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state, thus registered (user)
- MspInit/DeInit callbacks can be used during the @ref HAL_LPTIM_Init/@ref HAL_LPTIM_DeInit.
- In that case first register the MspInit/MspDeInit user callbacks using
- @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
+ in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
+ [..]
When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@@ -138,16 +142,16 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
+ * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
@@ -162,229 +166,207 @@
*/
#ifdef HAL_LPTIM_MODULE_ENABLED
-/* Private types -------------------------------------------------------------*/
-/** @defgroup LPTIM_Private_Types LPTIM Private Types
+
+#if defined (LPTIM1)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup LPTIM_Private_Constants
* @{
*/
-
-/**
- * @}
- */
-
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup LPTIM_Private_Defines LPTIM Private Defines
- * @{
- */
-
+#define TIMEOUT 1000UL /* Timeout is 1s */
/**
* @}
*/
+/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-/** @addtogroup LPTIM_Private_Variables LPTIM Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup LPTIM_Private_Constants LPTIM Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup LPTIM_Private_Macros LPTIM Private Macros
- * @{
- */
-
-/**
- * @}
- */
-
/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup LPTIM_Private_Functions_Prototypes LPTIM Private Functions Prototypes
- * @{
- */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag);
-/**
- * @}
- */
+/* Exported functions --------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup LPTIM_Private_Functions LPTIM Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
* @{
*/
-/** @defgroup LPTIM_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions.
+/** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions.
*
-@verbatim
+@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Initialize the LPTIM according to the specified parameters in the
- LPTIM_InitTypeDef and creates the associated handle.
+ LPTIM_InitTypeDef and initialize the associated handle.
(+) DeInitialize the LPTIM peripheral.
(+) Initialize the LPTIM MSP.
- (+) DeInitialize LPTIM MSP.
-
+ (+) DeInitialize the LPTIM MSP.
+
@endverbatim
* @{
*/
/**
- * @brief Initializes the LPTIM according to the specified parameters in the
- * LPTIM_InitTypeDef and creates the associated handle.
+ * @brief Initialize the LPTIM according to the specified parameters in the
+ * LPTIM_InitTypeDef and initialize the associated handle.
* @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
{
- uint32_t tmpcfgr = 0;
+ uint32_t tmpcfgr;
/* Check the LPTIM handle allocation */
- if(hlptim == NULL)
+ if (hlptim == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
+
assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
- assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
- if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
+ assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
{
assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
- assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
- }
+ }
assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
+ }
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
{
assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
- assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
- }
- assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
+ assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
+ }
+ assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
- if(hlptim->State == HAL_LPTIM_STATE_RESET)
+ if (hlptim->State == HAL_LPTIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hlptim->Lock = HAL_UNLOCKED;
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
- /* Reset the LPTIM callback to the legacy weak callbacks */
- hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
- hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
- hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
- hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
- hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
- hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
- hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ LPTIM_ResetCallback(hlptim);
- if(hlptim->MspInitCallback == NULL)
+ if (hlptim->MspInitCallback == NULL)
{
hlptim->MspInitCallback = HAL_LPTIM_MspInit;
}
+
/* Init the low level hardware : GPIO, CLOCK, NVIC */
hlptim->MspInitCallback(hlptim);
#else
- /* Init the low level hardware */
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_LPTIM_MspInit(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
+
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
-
+
/* Get the LPTIMx CFGR value */
tmpcfgr = hlptim->Instance->CFGR;
-
- if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
+
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
{
- tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL));
}
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
{
- tmpcfgr &= (uint32_t)(~ (LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRIGSEL));
}
-
- /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
- tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
- LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE ));
-
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
+ {
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_CKFLT));
+ }
+
+ /* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_CKPOL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
+ LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE));
+
/* Set initialization parameters */
tmpcfgr |= (hlptim->Init.Clock.Source |
hlptim->Init.Clock.Prescaler |
hlptim->Init.OutputPolarity |
hlptim->Init.UpdateMode |
hlptim->Init.CounterSource);
-
- if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
+
+ /* Glitch filters for internal triggers and external inputs are configured
+ * only if an internal clock source is provided to the LPTIM
+ */
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
{
- tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
+ tmpcfgr |= (hlptim->Init.Trigger.SampleTime |
hlptim->Init.UltraLowPowerClock.SampleTime);
- }
-
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ }
+
+ /* Configure the active edge or edges used by the counter only if LPTIM is
+ * clocked by an external clock source
+ */
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ {
+ tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity);
+ }
+
+ if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Enable External trigger and set the trigger source */
- tmpcfgr |= (hlptim->Init.Trigger.Source |
- hlptim->Init.Trigger.ActiveEdge |
- hlptim->Init.Trigger.SampleTime);
+ tmpcfgr |= (hlptim->Init.Trigger.Source |
+ hlptim->Init.Trigger.ActiveEdge);
}
-
+
/* Write to LPTIMx CFGR */
hlptim->Instance->CFGR = tmpcfgr;
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief DeInitializes the LPTIM peripheral.
+ * @brief DeInitialize the LPTIM peripheral.
* @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
{
/* Check the LPTIM handle allocation */
- if(hlptim == NULL)
+ if (hlptim == NULL)
{
return HAL_ERROR;
}
-
+
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
-
+
/* Disable the LPTIM Peripheral Clock */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
- if(hlptim->MspDeInitCallback == NULL)
+ if (hlptim->MspDeInitCallback == NULL)
{
hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
}
- /* DeInit the low level hardware */
+
+ /* DeInit the low level hardware: CLOCK, NVIC.*/
hlptim->MspDeInitCallback(hlptim);
#else
/* DeInit the low level hardware: CLOCK, NVIC.*/
@@ -393,16 +375,16 @@
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_RESET;
-
+
/* Release Lock */
__HAL_UNLOCK(hlptim);
-
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Initializes the LPTIM MSP.
+ * @brief Initialize the LPTIM MSP.
* @param hlptim LPTIM handle
* @retval None
*/
@@ -410,14 +392,14 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_MspInit could be implemented in the user file
*/
}
/**
- * @brief DeInitializes LPTIM MSP.
+ * @brief DeInitialize LPTIM MSP.
* @param hlptim LPTIM handle
* @retval None
*/
@@ -425,8 +407,8 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_MspDeInit could be implemented in the user file
*/
}
@@ -435,13 +417,13 @@
* @}
*/
-/** @defgroup LPTIM_Group2 LPTIM Start-Stop operation functions
- * @brief Start-Stop operation functions.
+/** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
+ * @brief Start-Stop operation functions.
*
-@verbatim
+@verbatim
==============================================================================
##### LPTIM Start Stop operation functions #####
- ==============================================================================
+ ==============================================================================
[..] This section provides functions allowing to:
(+) Start the PWM mode.
(+) Stop the PWM mode.
@@ -452,21 +434,21 @@
(+) Start the Encoder mode.
(+) Stop the Encoder mode.
(+) Start the Timeout mode.
- (+) Stop the Timeout mode.
+ (+) Stop the Timeout mode.
(+) Start the Counter mode.
(+) Stop the Counter mode.
-
+
@endverbatim
* @{
*/
-
+
/**
- * @brief Starts the LPTIM PWM generation.
- * @param hlptim LPTIM handle
- * @param Period Specifies the Autoreload value.
+ * @brief Start the LPTIM PWM generation.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Pulse Specifies the compare value.
+ * @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -476,61 +458,84 @@
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
assert_param(IS_LPTIM_PERIOD(Period));
assert_param(IS_LPTIM_PULSE(Pulse));
-
+
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
/* Reset WAVE bit to set PWM mode */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
-
+
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
-
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
+
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+
/* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
-
+
+ /* Wait for the completion of the write operation to the LPTIM_CMP register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
-
+
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the LPTIM PWM generation.
- * @param hlptim LPTIM handle
+ * @brief Stop the LPTIM PWM generation.
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
+
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Starts the LPTIM PWM generation in interrupt mode.
- * @param hlptim LPTIM handle
- * @param Period Specifies the Autoreload value.
+ * @brief Start the LPTIM PWM generation in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF
- * @param Pulse Specifies the compare value.
+ * @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF
* @retval HAL status
*/
@@ -540,99 +545,133 @@
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
assert_param(IS_LPTIM_PERIOD(Period));
assert_param(IS_LPTIM_PULSE(Pulse));
-
+
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
/* Reset WAVE bit to set PWM mode */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
-
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+
+ /* Load the pulse value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+
+ /* Wait for the completion of the write operation to the LPTIM_CMP register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Enable Autoreload write complete interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
-
+
/* Enable Compare write complete interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
-
+
/* Enable Autoreload match interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
-
+
/* Enable Compare match interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
-
+
/* If external trigger source is used, then enable external trigger interrupt */
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Enable external trigger interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
- }
-
+ }
+
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
-
- /* Load the period value in the autoreload register */
- __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
- /* Load the pulse value in the compare register */
- __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
-
+
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
-
+
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the LPTIM PWM generation in interrupt mode.
- * @param hlptim LPTIM handle
+ * @brief Stop the LPTIM PWM generation in interrupt mode.
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
+
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
-
- /* Disable Autoreload write complete interrupt */
+
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable Autoreload write complete interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
-
+
/* Disable Compare write complete interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
-
+
/* Disable Autoreload match interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
-
+
/* Disable Compare match interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
-
+
/* If external trigger source is used, then disable external trigger interrupt */
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Disable external trigger interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
- }
+ }
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Starts the LPTIM One pulse generation.
- * @param hlptim LPTIM handle
- * @param Period Specifies the Autoreload value.
+ * @brief Start the LPTIM One pulse generation.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Pulse Specifies the compare value.
+ * @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -642,61 +681,84 @@
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
assert_param(IS_LPTIM_PERIOD(Period));
assert_param(IS_LPTIM_PULSE(Pulse));
-
+
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
/* Reset WAVE bit to set one pulse mode */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
-
+
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
-
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
+
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+
/* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
-
- /* Start timer in continuous mode */
+
+ /* Wait for the completion of the write operation to the LPTIM_CMP register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
-
+
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the LPTIM One pulse generation.
- * @param hlptim LPTIM handle
+ * @brief Stop the LPTIM One pulse generation.
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
+
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Starts the LPTIM One pulse generation in interrupt mode.
- * @param hlptim LPTIM handle
- * @param Period Specifies the Autoreload value.
+ * @brief Start the LPTIM One pulse generation in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Pulse Specifies the compare value.
+ * @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -706,99 +768,133 @@
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
assert_param(IS_LPTIM_PERIOD(Period));
assert_param(IS_LPTIM_PULSE(Pulse));
-
+
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
/* Reset WAVE bit to set one pulse mode */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
-
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+
+ /* Load the pulse value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+
+ /* Wait for the completion of the write operation to the LPTIM_CMP register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Enable Autoreload write complete interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
-
+
/* Enable Compare write complete interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
-
+
/* Enable Autoreload match interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
-
+
/* Enable Compare match interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
-
+
/* If external trigger source is used, then enable external trigger interrupt */
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Enable external trigger interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
}
-
+
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
-
- /* Load the period value in the autoreload register */
- __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
- /* Load the pulse value in the compare register */
- __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
-
- /* Start timer in continuous mode */
+
+ /* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
-
+
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the LPTIM One pulse generation in interrupt mode.
- * @param hlptim LPTIM handle
+ * @brief Stop the LPTIM One pulse generation in interrupt mode.
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
+
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
-
+
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Disable Autoreload write complete interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
-
+
/* Disable Compare write complete interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
-
+
/* Disable Autoreload match interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
-
+
/* Disable Compare match interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
-
+
/* If external trigger source is used, then disable external trigger interrupt */
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Disable external trigger interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
}
-
+
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Starts the LPTIM in Set once mode.
- * @param hlptim LPTIM handle
- * @param Period Specifies the Autoreload value.
+ * @brief Start the LPTIM in Set once mode.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Pulse Specifies the compare value.
+ * @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -808,61 +904,84 @@
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
assert_param(IS_LPTIM_PERIOD(Period));
assert_param(IS_LPTIM_PULSE(Pulse));
-
+
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
/* Set WAVE bit to enable the set once mode */
hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
-
+
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
-
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
+
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+
/* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
-
- /* Start timer in continuous mode */
+
+ /* Wait for the completion of the write operation to the LPTIM_CMP register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
-
+
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the LPTIM Set once mode.
- * @param hlptim LPTIM handle
+ * @brief Stop the LPTIM Set once mode.
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
+
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Starts the LPTIM Set once mode in interrupt mode.
- * @param hlptim LPTIM handle
- * @param Period Specifies the Autoreload value.
+ * @brief Start the LPTIM Set once mode in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Pulse Specifies the compare value.
+ * @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -872,103 +991,137 @@
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
assert_param(IS_LPTIM_PERIOD(Period));
assert_param(IS_LPTIM_PULSE(Pulse));
-
+
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
/* Set WAVE bit to enable the set once mode */
hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
-
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+
+ /* Load the pulse value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+
+ /* Wait for the completion of the write operation to the LPTIM_CMP register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Enable Autoreload write complete interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
-
+
/* Enable Compare write complete interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
-
+
/* Enable Autoreload match interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
-
+
/* Enable Compare match interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
-
+
/* If external trigger source is used, then enable external trigger interrupt */
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Enable external trigger interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
- }
-
+ }
+
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
-
- /* Load the period value in the autoreload register */
- __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
- /* Load the pulse value in the compare register */
- __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
-
- /* Start timer in continuous mode */
+
+ /* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
-
+
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the LPTIM Set once mode in interrupt mode.
- * @param hlptim LPTIM handle
+ * @brief Stop the LPTIM Set once mode in interrupt mode.
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
+
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Disable Autoreload write complete interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
-
+
/* Disable Compare write complete interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
-
+
/* Disable Autoreload match interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
-
+
/* Disable Compare match interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
-
+
/* If external trigger source is used, then disable external trigger interrupt */
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Disable external trigger interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
- }
-
+ }
+
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Starts the Encoder interface.
- * @param hlptim LPTIM handle
- * @param Period Specifies the Autoreload value.
+ * @brief Start the Encoder interface.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
{
- uint32_t tmpcfgr = 0;
+ uint32_t tmpcfgr;
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
@@ -978,7 +1131,7 @@
assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Get the LPTIMx CFGR value */
tmpcfgr = hlptim->Instance->CFGR;
@@ -998,55 +1151,69 @@
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
+ hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the Encoder interface.
- * @param hlptim LPTIM handle
+ * @brief Stop the Encoder interface.
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
+
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
-
+
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Reset ENC bit to disable the encoder interface */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
-
+
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Starts the Encoder interface in interrupt mode.
- * @param hlptim LPTIM handle
- * @param Period Specifies the Autoreload value.
+ * @brief Start the Encoder interface in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
{
- uint32_t tmpcfgr = 0;
+ uint32_t tmpcfgr;
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
@@ -1056,8 +1223,8 @@
assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
/* Configure edge sensitivity for encoder mode */
/* Get the LPTIMx CFGR value */
tmpcfgr = hlptim->Instance->CFGR;
@@ -1074,68 +1241,93 @@
/* Set ENC bit to enable the encoder interface */
hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Enable "switch to down direction" interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN);
/* Enable "switch to up direction" interrupt */
- __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP);
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP);
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
- /* Load the period value in the autoreload register */
- __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
+ hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the Encoder interface in interrupt mode.
- * @param hlptim LPTIM handle
+ * @brief Stop the Encoder interface in interrupt mode.
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
+
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
-
+
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Reset ENC bit to disable the encoder interface */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
-
+
/* Disable "switch to down direction" interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_DOWN);
-
+
/* Disable "switch to up direction" interrupt */
- __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP);
-
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP);
+
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Starts the Timeout function. The first trigger event will start the
- * timer, any successive trigger event will reset the counter and
- * the timer restarts.
- * @param hlptim LPTIM handle
- * @param Period Specifies the Autoreload value.
+ * @brief Start the Timeout function.
+ * @note The first trigger event will start the timer, any successive
+ * trigger event will reset the counter and the timer restarts.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Timeout Specifies the TimeOut value to rest the counter.
+ * @param Timeout Specifies the TimeOut value to reset the counter.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -1145,66 +1337,89 @@
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
assert_param(IS_LPTIM_PERIOD(Period));
assert_param(IS_LPTIM_PULSE(Timeout));
-
+
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
/* Set TIMOUT bit to enable the timeout function */
hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
-
+
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
-
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
+
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+
/* Load the Timeout value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
-
+
+ /* Wait for the completion of the write operation to the LPTIM_CMP register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
-
+
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the Timeout function.
- * @param hlptim LPTIM handle
+ * @brief Stop the Timeout function.
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
+
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
-
+
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Reset TIMOUT bit to enable the timeout function */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
-
+
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Starts the Timeout function in interrupt mode. The first trigger
- * event will start the timer, any successive trigger event will reset
- * the counter and the timer restarts.
- * @param hlptim LPTIM handle
- * @param Period Specifies the Autoreload value.
+ * @brief Start the Timeout function in interrupt mode.
+ * @note The first trigger event will start the timer, any successive
+ * trigger event will reset the counter and the timer restarts.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Timeout Specifies the TimeOut value to rest the counter.
+ * @param Timeout Specifies the TimeOut value to reset the counter.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -1214,80 +1429,112 @@
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
assert_param(IS_LPTIM_PERIOD(Period));
assert_param(IS_LPTIM_PULSE(Timeout));
-
+
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
/* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
- __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT();
-
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT();
/* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
-
+
/* Set TIMOUT bit to enable the timeout function */
hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
-
- /* Enable Compare match interrupt */
- __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
-
+
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
-
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
+
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+
/* Load the Timeout value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
-
+
+ /* Wait for the completion of the write operation to the LPTIM_CMP register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Enable Compare match interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
-
+
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the Timeout function in interrupt mode.
- * @param hlptim LPTIM handle
+ * @brief Stop the Timeout function in interrupt mode.
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
+
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
- /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+ /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();
-
+
/* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
- __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT();
-
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT();
+
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
-
+
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Reset TIMOUT bit to enable the timeout function */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
-
+
/* Disable Compare match interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
-
+
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Starts the Counter mode.
- * @param hlptim LPTIM handle
- * @param Period Specifies the Autoreload value.
+ * @brief Start the Counter mode.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -1296,12 +1543,12 @@
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
assert_param(IS_LPTIM_PERIOD(Period));
-
+
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
/* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
- if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+ if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
/* Check if clock is prescaled */
assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
@@ -1311,47 +1558,61 @@
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
-
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
+
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
-
+
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the Counter mode.
- * @param hlptim LPTIM handle
+ * @brief Stop the Counter mode.
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
+
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
-
+
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Starts the Counter mode in interrupt mode.
- * @param hlptim LPTIM handle
- * @param Period Specifies the Autoreload value.
+ * @brief Start the Counter mode in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -1360,78 +1621,100 @@
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
assert_param(IS_LPTIM_PERIOD(Period));
-
+
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
- __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT();
-
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT();
/* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */
- __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
-
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
+
/* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
- if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+ if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
/* Check if clock is prescaled */
assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
/* Set clock prescaler to 0 */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
}
-
- /* Enable Autoreload write complete interrupt */
- __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
-
- /* Enable Autoreload match interrupt */
- __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
-
+
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
-
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
+
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Enable Autoreload write complete interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
+
+ /* Enable Autoreload match interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
-
+
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the Counter mode in interrupt mode.
- * @param hlptim LPTIM handle
+ * @brief Stop the Counter mode in interrupt mode.
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
+
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
- /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+ /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();
-
+
/* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
- __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT();
-
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT();
+
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
-
+
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Disable Autoreload write complete interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
-
+
/* Disable Autoreload match interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
-
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
/* Return function status */
return HAL_OK;
}
@@ -1440,13 +1723,13 @@
* @}
*/
-/** @defgroup LPTIM_Group3 LPTIM Read operation functions
+/** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
* @brief Read operation functions.
*
-@verbatim
+@verbatim
==============================================================================
##### LPTIM Read operation functions #####
- ==============================================================================
+ ==============================================================================
[..] This section provides LPTIM Reading functions.
(+) Read the counter value.
(+) Read the period (Auto-reload) value.
@@ -1456,41 +1739,41 @@
*/
/**
- * @brief This function returns the current counter value.
+ * @brief Return the current counter value.
* @param hlptim LPTIM handle
* @retval Counter value.
*/
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)
{
- /* Check the parameters */
+ /* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
+
return (hlptim->Instance->CNT);
}
/**
- * @brief This function return the current Autoreload (Period) value.
+ * @brief Return the current Autoreload (Period) value.
* @param hlptim LPTIM handle
* @retval Autoreload value.
*/
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)
{
- /* Check the parameters */
+ /* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
+
return (hlptim->Instance->ARR);
}
/**
- * @brief This function return the current Compare (Pulse) value.
+ * @brief Return the current Compare (Pulse) value.
* @param hlptim LPTIM handle
* @retval Compare value.
*/
uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)
{
- /* Check the parameters */
+ /* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
+
return (hlptim->Instance->CMP);
}
@@ -1498,339 +1781,355 @@
* @}
*/
-
-
-/** @defgroup LPTIM_Group4 LPTIM IRQ handler
+/** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
* @brief LPTIM IRQ handler.
*
-@verbatim
+@verbatim
==============================================================================
- ##### LPTIM IRQ handler #####
- ==============================================================================
-[..] This section provides LPTIM IRQ handler function.
+ ##### LPTIM IRQ handler and callbacks #####
+ ==============================================================================
+[..] This section provides LPTIM IRQ handler and callback functions called within
+ the IRQ handler:
+ (+) LPTIM interrupt request handler
+ (+) Compare match Callback
+ (+) Auto-reload match Callback
+ (+) External trigger event detection Callback
+ (+) Compare register write complete Callback
+ (+) Auto-reload register write complete Callback
+ (+) Up-counting direction change Callback
+ (+) Down-counting direction change Callback
@endverbatim
* @{
*/
/**
- * @brief This function handles LPTIM interrupt request.
+ * @brief Handle LPTIM interrupt request.
* @param hlptim LPTIM handle
* @retval None
*/
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
{
/* Compare match interrupt */
- if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET)
- {
- if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) !=RESET)
- {
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET)
+ {
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) != RESET)
+ {
/* Clear Compare match flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM);
+
/* Compare match Callback */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
hlptim->CompareMatchCallback(hlptim);
#else
- HAL_LPTIM_CompareMatchCallback(hlptim);
+ HAL_LPTIM_CompareMatchCallback(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
-
+
/* Autoreload match interrupt */
- if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
- {
- if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) !=RESET)
- {
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
+ {
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) != RESET)
+ {
/* Clear Autoreload match flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
+
/* Autoreload match Callback */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
hlptim->AutoReloadMatchCallback(hlptim);
#else
- HAL_LPTIM_AutoReloadMatchCallback(hlptim);
+ HAL_LPTIM_AutoReloadMatchCallback(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
-
+
/* Trigger detected interrupt */
- if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
- {
- if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) !=RESET)
- {
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
+ {
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) != RESET)
+ {
/* Clear Trigger detected flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
+
/* Trigger detected callback */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
hlptim->TriggerCallback(hlptim);
#else
- HAL_LPTIM_TriggerCallback(hlptim);
+ HAL_LPTIM_TriggerCallback(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
-
+
/* Compare write interrupt */
- if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET)
- {
- if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CMPM) !=RESET)
- {
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET)
+ {
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPOK) != RESET)
+ {
/* Clear Compare write flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+
/* Compare write Callback */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
hlptim->CompareWriteCallback(hlptim);
#else
- HAL_LPTIM_CompareWriteCallback(hlptim);
+ HAL_LPTIM_CompareWriteCallback(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
-
+
/* Autoreload write interrupt */
- if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
- {
- if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) !=RESET)
- {
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
+ {
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) != RESET)
+ {
/* Clear Autoreload write flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
/* Autoreload write Callback */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
hlptim->AutoReloadWriteCallback(hlptim);
#else
- HAL_LPTIM_AutoReloadWriteCallback(hlptim);
+ HAL_LPTIM_AutoReloadWriteCallback(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
-
+
/* Direction counter changed from Down to Up interrupt */
- if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
- {
- if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) !=RESET)
- {
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
+ {
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) != RESET)
+ {
/* Clear Direction counter changed from Down to Up flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
+
/* Direction counter changed from Down to Up Callback */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
hlptim->DirectionUpCallback(hlptim);
#else
- HAL_LPTIM_DirectionUpCallback(hlptim);
+ HAL_LPTIM_DirectionUpCallback(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
-
+
/* Direction counter changed from Up to Down interrupt */
- if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
- {
- if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) !=RESET)
- {
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
+ {
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) != RESET)
+ {
/* Clear Direction counter changed from Up to Down flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
+
/* Direction counter changed from Up to Down Callback */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
hlptim->DirectionDownCallback(hlptim);
#else
- HAL_LPTIM_DirectionDownCallback(hlptim);
+ HAL_LPTIM_DirectionDownCallback(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
-
__HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG();
}
/**
- * @brief Compare match callback in non blocking mode
- * @param hlptim LPTIM handle
+ * @brief Compare match callback in non-blocking mode.
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
- */
+ */
}
/**
- * @brief Autoreload match callback in non blocking mode
- * @param hlptim LPTIM handle
+ * @brief Autoreload match callback in non-blocking mode.
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
- */
+ */
}
/**
- * @brief Trigger detected callback in non blocking mode
- * @param hlptim LPTIM handle
+ * @brief Trigger detected callback in non-blocking mode.
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_TriggerCallback could be implemented in the user file
- */
+ */
}
/**
- * @brief Compare write callback in non blocking mode
- * @param hlptim LPTIM handle
+ * @brief Compare write callback in non-blocking mode.
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
- */
+ */
}
/**
- * @brief Autoreload write callback in non blocking mode
- * @param hlptim LPTIM handle
+ * @brief Autoreload write callback in non-blocking mode.
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
- */
+ */
}
/**
- * @brief Direction counter changed from Down to Up callback in non blocking mode
- * @param hlptim LPTIM handle
+ * @brief Direction counter changed from Down to Up callback in non-blocking mode.
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
- */
+ */
}
/**
- * @brief Direction counter changed from Up to Down callback in non blocking mode
- * @param hlptim LPTIM handle
+ * @brief Direction counter changed from Up to Down callback in non-blocking mode.
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
- */
+ */
}
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
/**
- * @brief Register user LPTIM callback to be used instead of the weak predefined callback
- * @param hlptim lptim handle
- * @param CallbackID ID of the callback to be registered
- * This parameter can be one of the following values:
- * @arg @ref HAL_LPTIM_MSPINIT_CB_ID MspInit Callback ID
- * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID MspDeInit Callback ID
- * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare Match Callback ID
- * @arg @ref HAL_LPTIM_AUTO_RELOAD_MATCH_CB_ID Auto Reload Match Callback ID
- * @arg @ref HAL_LPTIM_TRIGGER_CB_ID Trigger Callback ID
- * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare Write Callback ID
- * @arg @ref HAL_LPTIM_AUTO_RELOAD_WRITE_CB_ID Auto Reload Write Callback ID
- * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Direction UP Callback ID
- * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Direction Down Callback ID
+ * @brief Register a User LPTIM callback to be used instead of the weak predefined callback
+ * @param hlptim LPTIM handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
+ * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
+ * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
+ * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
+ * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
+ * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
+ * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
+ * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
+ * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
* @param pCallback pointer to the callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim,
+ HAL_LPTIM_CallbackIDTypeDef CallbackID,
+ pLPTIM_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
return HAL_ERROR;
}
+
/* Process locked */
__HAL_LOCK(hlptim);
- if(hlptim->State == HAL_LPTIM_STATE_READY)
+ if (hlptim->State == HAL_LPTIM_STATE_READY)
{
switch (CallbackID)
{
- case HAL_LPTIM_MSPINIT_CB_ID :
- hlptim->MspInitCallback = pCallback;
- break;
+ case HAL_LPTIM_MSPINIT_CB_ID :
+ hlptim->MspInitCallback = pCallback;
+ break;
- case HAL_LPTIM_MSPDEINIT_CB_ID :
- hlptim->MspDeInitCallback = pCallback;
- break;
+ case HAL_LPTIM_MSPDEINIT_CB_ID :
+ hlptim->MspDeInitCallback = pCallback;
+ break;
- case HAL_LPTIM_COMPARE_MATCH_CB_ID :
- hlptim->CompareMatchCallback = pCallback;
- break;
+ case HAL_LPTIM_COMPARE_MATCH_CB_ID :
+ hlptim->CompareMatchCallback = pCallback;
+ break;
- case HAL_LPTIM_AUTO_RELOAD_MATCH_CB_ID :
- hlptim->AutoReloadMatchCallback = pCallback;
- break;
+ case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
+ hlptim->AutoReloadMatchCallback = pCallback;
+ break;
- case HAL_LPTIM_TRIGGER_CB_ID :
- hlptim->TriggerCallback = pCallback;
- break;
+ case HAL_LPTIM_TRIGGER_CB_ID :
+ hlptim->TriggerCallback = pCallback;
+ break;
- case HAL_LPTIM_COMPARE_WRITE_CB_ID :
- hlptim->CompareWriteCallback = pCallback;
- break;
+ case HAL_LPTIM_COMPARE_WRITE_CB_ID :
+ hlptim->CompareWriteCallback = pCallback;
+ break;
- case HAL_LPTIM_AUTO_RELOAD_WRITE_CB_ID :
- hlptim->AutoReloadWriteCallback = pCallback;
- break;
+ case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
+ hlptim->AutoReloadWriteCallback = pCallback;
+ break;
- case HAL_LPTIM_DIRECTION_UP_CB_ID :
- hlptim->DirectionUpCallback = pCallback;
- break;
+ case HAL_LPTIM_DIRECTION_UP_CB_ID :
+ hlptim->DirectionUpCallback = pCallback;
+ break;
- case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
- hlptim->DirectionDownCallback = pCallback;
- break;
+ case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
+ hlptim->DirectionDownCallback = pCallback;
+ break;
- default :
- /* Return error status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(hlptim->State == HAL_LPTIM_STATE_RESET)
+ else if (hlptim->State == HAL_LPTIM_STATE_RESET)
{
switch (CallbackID)
{
- case HAL_LPTIM_MSPINIT_CB_ID :
- hlptim->MspInitCallback = pCallback;
- break;
+ case HAL_LPTIM_MSPINIT_CB_ID :
+ hlptim->MspInitCallback = pCallback;
+ break;
- case HAL_LPTIM_MSPDEINIT_CB_ID :
- hlptim->MspDeInitCallback = pCallback;
- break;
+ case HAL_LPTIM_MSPDEINIT_CB_ID :
+ hlptim->MspDeInitCallback = pCallback;
+ break;
- default :
- /* Return error status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -1846,91 +2145,92 @@
}
/**
- * @brief UnRegister user LPTIM callback
- * LPTIM callback is redirected to the weak predefined callback
- * @param hlptim lptim handle
- * @param CallbackID ID of the callback to be unregistered
-+ * This parameter can be one of the following values:
-+ * @arg @ref HAL_LPTIM_MSPINIT_CB_ID MspInit Callback ID
-+ * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID MspDeInit Callback ID
-+ * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare Match Callback ID
-+ * @arg @ref HAL_LPTIM_AUTO_RELOAD_MATCH_CB_ID Auto Reload Match Callback ID
-+ * @arg @ref HAL_LPTIM_TRIGGER_CB_ID Trigger Callback ID
-+ * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare Write Callback ID
-+ * @arg @ref HAL_LPTIM_AUTO_RELOAD_WRITE_CB_ID Auto Reload Write Callback ID
-+ * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Direction UP Callback ID
-+ * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Direction Down Callback ID
+ * @brief Unregister a LPTIM callback
+ * LLPTIM callback is redirected to the weak predefined callback
+ * @param hlptim LPTIM handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
+ * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
+ * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
+ * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
+ * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
+ * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
+ * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
+ * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
+ * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
* @retval status
*/
-HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID)
+HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim,
+ HAL_LPTIM_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hlptim);
- if(hlptim->State == HAL_LPTIM_STATE_READY)
+ if (hlptim->State == HAL_LPTIM_STATE_READY)
{
switch (CallbackID)
{
- case HAL_LPTIM_MSPINIT_CB_ID :
- hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */
- break;
+ case HAL_LPTIM_MSPINIT_CB_ID :
+ hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */
+ break;
- case HAL_LPTIM_MSPDEINIT_CB_ID :
- hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak MspDeInit Callback */
- break;
+ case HAL_LPTIM_MSPDEINIT_CB_ID :
+ hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak Msp DeInit Callback */
+ break;
- case HAL_LPTIM_COMPARE_MATCH_CB_ID :
- hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Legacy weak Compare Match Callback */
- break;
+ case HAL_LPTIM_COMPARE_MATCH_CB_ID :
+ hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Legacy weak Compare match Callback */
+ break;
- case HAL_LPTIM_AUTO_RELOAD_MATCH_CB_ID :
- hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Legacy weak Auto Reload Match Callback */
- break;
+ case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
+ hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Legacy weak Auto-reload match Callback */
+ break;
- case HAL_LPTIM_TRIGGER_CB_ID :
- hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* Legacy weak Trigger Callback */
- break;
+ case HAL_LPTIM_TRIGGER_CB_ID :
+ hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* Legacy weak External trigger event detection Callback */
+ break;
- case HAL_LPTIM_COMPARE_WRITE_CB_ID :
- hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Legacy weak Compare Write Callback */
- break;
+ case HAL_LPTIM_COMPARE_WRITE_CB_ID :
+ hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Legacy weak Compare register write complete Callback */
+ break;
- case HAL_LPTIM_AUTO_RELOAD_WRITE_CB_ID :
- hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Legacy weak Auto Reload Write Callback */
- break;
+ case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
+ hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Legacy weak Auto-reload register write complete Callback */
+ break;
- case HAL_LPTIM_DIRECTION_UP_CB_ID :
- hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Legacy weak Direction Up Callback */
- break;
+ case HAL_LPTIM_DIRECTION_UP_CB_ID :
+ hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Legacy weak Up-counting direction change Callback */
+ break;
- case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
- hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Legacy weak Direction Down Callback */
- break;
+ case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
+ hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Legacy weak Down-counting direction change Callback */
+ break;
- default :
- /* Return error status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(hlptim->State == HAL_LPTIM_STATE_RESET)
+ else if (hlptim->State == HAL_LPTIM_STATE_RESET)
{
switch (CallbackID)
{
- case HAL_LPTIM_MSPINIT_CB_ID :
- hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */
- break;
+ case HAL_LPTIM_MSPINIT_CB_ID :
+ hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */
+ break;
- case HAL_LPTIM_MSPDEINIT_CB_ID :
- hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak MspDeInit Callback */
- break;
+ case HAL_LPTIM_MSPDEINIT_CB_ID :
+ hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak Msp DeInit Callback */
+ break;
- default :
- /* Return error status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -1950,13 +2250,13 @@
* @}
*/
-/** @defgroup LPTIM_Group5 Peripheral State functions
- * @brief Peripheral State functions.
+/** @defgroup LPTIM_Group5 Peripheral State functions
+ * @brief Peripheral State functions.
*
-@verbatim
+@verbatim
==============================================================================
##### Peripheral State functions #####
- ==============================================================================
+ ==============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral.
@@ -1965,12 +2265,13 @@
*/
/**
- * @brief Returns the LPTIM state.
+ * @brief Return the LPTIM handle state.
* @param hlptim LPTIM handle
* @retval HAL state
*/
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
{
+ /* Return LPTIM handle state */
return hlptim->State;
}
@@ -1983,6 +2284,167 @@
* @}
*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
+ * @{
+ */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Reset interrupt callbacks to the legacy weak callbacks.
+ * @param lptim pointer to a LPTIM_HandleTypeDef structure that contains
+ * the configuration information for LPTIM module.
+ * @retval None
+ */
+static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim)
+{
+ /* Reset the LPTIM callback to the legacy weak callbacks */
+ lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Compare match Callback */
+ lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Auto-reload match Callback */
+ lptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* External trigger event detection Callback */
+ lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Compare register write complete Callback */
+ lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Auto-reload register write complete Callback */
+ lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Up-counting direction change Callback */
+ lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Down-counting direction change Callback */
+}
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+
+/**
+ * @brief LPTimer Wait for flag set
+ * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
+ * the configuration information for LPTIM module.
+ * @param flag The lptim flag
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag)
+{
+ HAL_StatusTypeDef result = HAL_OK;
+ uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);
+ do
+ {
+ count--;
+ if (count == 0UL)
+ {
+ result = HAL_TIMEOUT;
+ }
+ }
+ while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
+
+ return result;
+}
+
+/**
+ * @brief Disable LPTIM HW instance.
+ * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
+ * the configuration information for LPTIM module.
+ * @note The following sequence is required to solve LPTIM disable HW limitation.
+ * Please check Errata Sheet ES0335 for more details under "MCU may remain
+ * stuck in LPTIM interrupt when entering Stop mode" section.
+ * @retval None
+ */
+void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim)
+{
+ uint32_t tmpclksource = 0;
+ uint32_t tmpIER;
+ uint32_t tmpCFGR;
+ uint32_t tmpCMP;
+ uint32_t tmpARR;
+
+ __disable_irq();
+
+ /*********** Save LPTIM Config ***********/
+ /* Save LPTIM source clock */
+ switch ((uint32_t)hlptim->Instance)
+ {
+ case LPTIM1_BASE:
+ tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE();
+ break;
+ default:
+ break;
+ }
+
+ /* Save LPTIM configuration registers */
+ tmpIER = hlptim->Instance->IER;
+ tmpCFGR = hlptim->Instance->CFGR;
+ tmpCMP = hlptim->Instance->CMP;
+ tmpARR = hlptim->Instance->ARR;
+
+ /*********** Reset LPTIM ***********/
+ switch ((uint32_t)hlptim->Instance)
+ {
+ case LPTIM1_BASE:
+ __HAL_RCC_LPTIM1_FORCE_RESET();
+ __HAL_RCC_LPTIM1_RELEASE_RESET();
+ break;
+ default:
+ break;
+ }
+
+ /*********** Restore LPTIM Config ***********/
+ if ((tmpCMP != 0UL) || (tmpARR != 0UL))
+ {
+ /* Force LPTIM source kernel clock from APB */
+ switch ((uint32_t)hlptim->Instance)
+ {
+ case LPTIM1_BASE:
+ __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1);
+ break;
+ default:
+ break;
+ }
+
+ if (tmpCMP != 0UL)
+ {
+ /* Restore CMP register (LPTIM should be enabled first) */
+ hlptim->Instance->CR |= LPTIM_CR_ENABLE;
+ hlptim->Instance->CMP = tmpCMP;
+
+ /* Wait for the completion of the write operation to the LPTIM_CMP register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
+ {
+ hlptim->State = HAL_LPTIM_STATE_TIMEOUT;
+ }
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+ }
+
+ if (tmpARR != 0UL)
+ {
+ /* Restore ARR register (LPTIM should be enabled first) */
+ hlptim->Instance->CR |= LPTIM_CR_ENABLE;
+ hlptim->Instance->ARR = tmpARR;
+
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ hlptim->State = HAL_LPTIM_STATE_TIMEOUT;
+ }
+
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+ }
+
+ /* Restore LPTIM source kernel clock */
+ switch ((uint32_t)hlptim->Instance)
+ {
+ case LPTIM1_BASE:
+ __HAL_RCC_LPTIM1_CONFIG(tmpclksource);
+ break;
+ default:
+ break;
+ }
+ }
+
+ /* Restore configuration registers (LPTIM should be disabled first) */
+ hlptim->Instance->CR &= ~(LPTIM_CR_ENABLE);
+ hlptim->Instance->IER = tmpIER;
+ hlptim->Instance->CFGR = tmpCFGR;
+
+ __enable_irq();
+}
+/**
+ * @}
+ */
+#endif /* LPTIM1 */
+
#endif /* HAL_LPTIM_MODULE_ENABLED */
/**
* @}
diff --git a/Src/stm32f7xx_hal_mmc.c b/Src/stm32f7xx_hal_mmc.c
index e0e44fc..1550019 100644
--- a/Src/stm32f7xx_hal_mmc.c
+++ b/Src/stm32f7xx_hal_mmc.c
@@ -3,34 +3,34 @@
* @file stm32f7xx_hal_mmc.c
* @author MCD Application Team
* @brief MMC card HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Secure Digital (MMC) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
- * + Peripheral Control functions
+ * + Peripheral Control functions
* + MMC card Control functions
- *
+ *
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
- This driver implements a high level communication layer for read and write from/to
- this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
- the user in HAL_MMC_MspInit() function (MSP layer).
- Basically, the MSP layer configuration should be the same as we provide in the
+ This driver implements a high level communication layer for read and write from/to
+ this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
+ the user in HAL_MMC_MspInit() function (MSP layer).
+ Basically, the MSP layer configuration should be the same as we provide in the
examples.
You can easily tailor this configuration according to hardware resources.
[..]
- This driver is a generic layered driver for SDMMC memories which uses the HAL
- SDMMC driver functions to interface with MMC and eMMC cards devices.
+ This driver is a generic layered driver for SDMMC memories which uses the HAL
+ SDMMC driver functions to interface with MMC and eMMC cards devices.
It is used as follows:
-
+
(#)Initialize the SDMMC low level resources by implement the HAL_MMC_MspInit() API:
- (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
+ (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
(##) SDMMC pins configuration for MMC card
- (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
+ (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
(+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
and according to your pin assignment;
(##) DMA Configuration if you need to use DMA process (HAL_MMC_ReadBlocks_DMA()
@@ -38,8 +38,8 @@
(+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
(+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
(##) NVIC configuration if you need to use interrupt process when using DMA transfer.
- (+++) Configure the SDMMC and DMA interrupt priorities using functions
- HAL_NVIC_SetPriority(); DMA priority is superior to SDMMC's priority
+ (+++) Configure the SDMMC and DMA interrupt priorities using function HAL_NVIC_SetPriority();
+ DMA priority is superior to SDMMC's priority
(+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ()
(+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT()
and __HAL_MMC_DISABLE_IT() inside the communication process.
@@ -47,70 +47,71 @@
and __HAL_MMC_CLEAR_IT()
(##) NVIC configuration if you need to use interrupt process (HAL_MMC_ReadBlocks_IT()
and HAL_MMC_WriteBlocks_IT() APIs).
- (+++) Configure the SDMMC interrupt priorities using function
- HAL_NVIC_SetPriority();
+ (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority();
(+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
- (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT()
+ (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT()
and __HAL_MMC_DISABLE_IT() inside the communication process.
(+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT()
and __HAL_MMC_CLEAR_IT()
- (#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization
+ (#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization
-
+
*** MMC Card Initialization and configuration ***
- ================================================
+ ================================================
[..]
- To initialize the MMC Card, use the HAL_MMC_Init() function. It Initializes
- SDMMC IP (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer).
+ To initialize the MMC Card, use the HAL_MMC_Init() function. It Initializes
+ SDMMC Peripheral (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer).
This function provide the following operations:
(#) Initialize the SDMMC peripheral interface with defaullt configuration.
- The initialization process is done at 400KHz. You can change or adapt
- this frequency by adjusting the "ClockDiv" field.
+ The initialization process is done at 400KHz. You can change or adapt
+ this frequency by adjusting the "ClockDiv" field.
The MMC Card frequency (SDMMC_CK) is computed as follows:
-
+
SDMMC_CK = SDMMCCLK / (ClockDiv + 2)
-
- In initialization mode and according to the MMC Card standard,
+
+ In initialization mode and according to the MMC Card standard,
make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
- This phase of initialization is done through SDMMC_Init() and
+ This phase of initialization is done through SDMMC_Init() and
SDMMC_PowerState_ON() SDMMC low level APIs.
(#) Initialize the MMC card. The API used is HAL_MMC_InitCard().
- This phase allows the card initialization and identification
+ This phase allows the card initialization and identification
and check the MMC Card type (Standard Capacity or High Capacity)
The initialization flow is compatible with MMC standard.
- This API (HAL_MMC_InitCard()) could be used also to reinitialize the card in case
+ This API (HAL_MMC_InitCard()) could be used also to reinitialize the card in case
of plug-off plug-in.
- (#) Configure the MMC Card Data transfer frequency. By Default, the card transfer
+ (#) Configure the MMC Card Data transfer frequency. By Default, the card transfer
frequency is set to 24MHz. You can change or adapt this frequency by adjusting
the "ClockDiv" field.
- In transfer mode and according to the MMC Card standard, make sure that the
+ In transfer mode and according to the MMC Card standard, make sure that the
SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
- To be able to use a frequency higher than 24MHz, you should use the SDMMC
- peripheral in bypass mode. Refer to the corresponding reference manual
+ To be able to use a frequency higher than 24MHz, you should use the SDMMC
+ peripheral in bypass mode. Refer to the corresponding reference manual
for more details.
-
+
(#) Select the corresponding MMC Card according to the address read with the step 2.
-
+
(#) Configure the MMC Card in wide bus mode: 4-bits data.
-
+
*** MMC Card Read operation ***
==============================
- [..]
- (+) You can read from MMC card in polling mode by using function HAL_MMC_ReadBlocks().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
+ [..]
+ (+) You can read from MMC card in polling mode by using function HAL_MMC_ReadBlocks().
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
(+) You can read from MMC card in DMA mode by using function HAL_MMC_ReadBlocks_DMA().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
@@ -123,20 +124,22 @@
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
You could also check the IT transfer process through the MMC Rx interrupt event.
-
+
*** MMC Card Write operation ***
- ===============================
- [..]
- (+) You can write to MMC card in polling mode by using function HAL_MMC_WriteBlocks().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
+ ===============================
+ [..]
+ (+) You can write to MMC card in polling mode by using function HAL_MMC_WriteBlocks().
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
(+) You can write to MMC card in DMA mode by using function HAL_MMC_WriteBlocks_DMA().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 byte).
+ You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
@@ -173,7 +176,7 @@
==================================
[..]
Below the list of most used macros in MMC HAL driver.
-
+
(+) __HAL_MMC_ENABLE : Enable the MMC device
(+) __HAL_MMC_DISABLE : Disable the MMC device
(+) __HAL_MMC_DMA_ENABLE: Enable the SDMMC DMA transfer
@@ -184,8 +187,8 @@
(+) __HAL_MMC_CLEAR_FLAG: Clear the MMC's pending flags
[..]
- (@) You can refer to the MMC HAL driver header file for more useful macros
-
+ (@) You can refer to the MMC HAL driver header file for more useful macros
+
*** Callback registration ***
=============================================
[..]
@@ -216,7 +219,7 @@
By default, after the @ref HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_MMC_Init
+ reset to the legacy weak (surcharged) functions in the @ref HAL_MMC_Init
and @ref HAL_MMC_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the @ref HAL_MMC_Init and @ref HAL_MMC_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -226,12 +229,13 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL__RegisterCallback before calling @ref HAL_MMC_DeInit
+ using @ref HAL_MMC_RegisterCallback before calling @ref HAL_MMC_DeInit
or @ref HAL_MMC_Init function.
When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registering feature is not available
+ not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
@@ -242,10 +246,10 @@
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
@@ -261,16 +265,18 @@
#ifdef HAL_MMC_MODULE_ENABLED
+#if defined(SDMMC1)
+
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup MMC_Private_Defines
* @{
*/
-
+
/**
* @}
*/
-
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -281,31 +287,30 @@
static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc);
static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc);
static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus);
-static HAL_StatusTypeDef MMC_PowerOFF(MMC_HandleTypeDef *hmmc);
-static HAL_StatusTypeDef MMC_Write_IT(MMC_HandleTypeDef *hmmc);
-static HAL_StatusTypeDef MMC_Read_IT(MMC_HandleTypeDef *hmmc);
-static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void MMC_DMAError(DMA_HandleTypeDef *hdma);
-static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma);
-static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma);
+static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc);
+static void MMC_Write_IT(MMC_HandleTypeDef *hmmc);
+static void MMC_Read_IT(MMC_HandleTypeDef *hmmc);
+static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void MMC_DMAError(DMA_HandleTypeDef *hdma);
+static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma);
+static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma);
/**
* @}
*/
-
/* Exported functions --------------------------------------------------------*/
/** @addtogroup MMC_Exported_Functions
* @{
*/
/** @addtogroup MMC_Exported_Functions_Group1
- * @brief Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
*
-@verbatim
+@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
- [..]
+ [..]
This section provides functions allowing to initialize/de-initialize the MMC
card device to be ready for use.
@@ -314,9 +319,9 @@
*/
/**
- * @brief Initializes the MMC according to the specified parameters in the
+ * @brief Initializes the MMC according to the specified parameters in the
MMC_HandleTypeDef and create the associated handle.
- * @param hmmc Pointer to the MMC handle
+ * @param hmmc: Pointer to the MMC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc)
@@ -340,7 +345,7 @@
{
/* Allocate lock resource and initialize it */
hmmc->Lock = HAL_UNLOCKED;
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
/* Reset Callback pointers in HAL_MMC_STATE_RESET only */
hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback;
hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback;
@@ -357,20 +362,23 @@
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_MMC_MspInit(hmmc);
-#endif
+#endif
}
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize the Card parameters */
- HAL_MMC_InitCard(hmmc);
+ if(HAL_MMC_InitCard(hmmc) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
/* Initialize the error code */
hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
+
/* Initialize the MMC operation */
hmmc->Context = MMC_CONTEXT_NONE;
-
+
/* Initialize the MMC state */
hmmc->State = HAL_MMC_STATE_READY;
@@ -379,15 +387,16 @@
/**
* @brief Initializes the MMC Card.
- * @param hmmc Pointer to MMC handle
- * @note This function initializes the MMC card. It could be used when a card
+ * @param hmmc: Pointer to MMC handle
+ * @note This function initializes the MMC card. It could be used when a card
re-initialization is needed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc)
{
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
+ uint32_t errorstate;
MMC_InitTypeDef Init;
+ HAL_StatusTypeDef status;
/* Default SDMMC peripheral configuration for MMC card initialization */
Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
@@ -398,20 +407,25 @@
Init.ClockDiv = SDMMC_INIT_CLK_DIV;
/* Initialize SDMMC peripheral interface with default configuration */
- SDMMC_Init(hmmc->Instance, Init);
+ status = SDMMC_Init(hmmc->Instance, Init);
+ if(status == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
/* Disable SDMMC Clock */
__HAL_MMC_DISABLE(hmmc);
/* Set Power State to ON */
- SDMMC_PowerState_ON(hmmc->Instance);
-
+ status = SDMMC_PowerState_ON(hmmc->Instance);
+ if(status == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
/* Enable MMC Clock */
__HAL_MMC_ENABLE(hmmc);
-
- /* Required power up waiting time before starting the SD initialization sequence */
- HAL_Delay(2);
-
+
/* Identify card operating voltage */
errorstate = MMC_PowerON(hmmc);
if(errorstate != HAL_MMC_ERROR_NONE)
@@ -435,7 +449,7 @@
/**
* @brief De-Initializes the MMC card.
- * @param hmmc Pointer to MMC handle
+ * @param hmmc: Pointer to MMC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc)
@@ -445,16 +459,16 @@
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_SDMMC_ALL_INSTANCE(hmmc->Instance));
hmmc->State = HAL_MMC_STATE_BUSY;
-
- /* Set MMC power state to off */
+
+ /* Set MMC power state to off */
MMC_PowerOFF(hmmc);
-
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
if(hmmc->MspDeInitCallback == NULL)
{
hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
@@ -466,24 +480,24 @@
/* De-Initialize the MSP layer */
HAL_MMC_MspDeInit(hmmc);
#endif
-
+
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
hmmc->State = HAL_MMC_STATE_RESET;
-
+
return HAL_OK;
}
/**
* @brief Initializes the MMC MSP.
- * @param hmmc Pointer to MMC handle
+ * @param hmmc: Pointer to MMC handle
* @retval None
*/
__weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmmc);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_MMC_MspInit could be implemented in the user file
*/
@@ -491,14 +505,14 @@
/**
* @brief De-Initialize MMC MSP.
- * @param hmmc Pointer to MMC handle
+ * @param hmmc: Pointer to MMC handle
* @retval None
*/
__weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmmc);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_MMC_MspDeInit could be implemented in the user file
*/
@@ -509,14 +523,14 @@
*/
/** @addtogroup MMC_Exported_Functions_Group2
- * @brief Data transfer functions
+ * @brief Data transfer functions
*
-@verbatim
+@verbatim
==============================================================================
##### IO operation functions #####
- ==============================================================================
+ ==============================================================================
[..]
- This subsection provides a set of functions allowing to manage the data
+ This subsection provides a set of functions allowing to manage the data
transfer from/to MMC card.
@endverbatim
@@ -524,85 +538,86 @@
*/
/**
- * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
* is managed by polling mode.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
- * @param hmmc Pointer to MMC handle
- * @param pData pointer to the buffer that will contain the received data
- * @param BlockAdd Block Address from where data is to be read
- * @param NumberOfBlocks Number of MMC blocks to read
- * @param Timeout Specify timeout value
+ * @param hmmc: Pointer to MMC handle
+ * @param pData: pointer to the buffer that will contain the received data
+ * @param BlockAdd: Block Address from where data is to be read
+ * @param NumberOfBlocks: Number of MMC blocks to read
+ * @param Timeout: Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
{
SDMMC_DataInitTypeDef config;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
+ uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
- uint32_t count = 0, *tempbuff = (uint32_t *)pData;
-
+ uint32_t count, data, dataremaining;
+ uint32_t add = BlockAdd;
+ uint8_t *tempbuff = pData;
+
if(NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
-
+
if(hmmc->State == HAL_MMC_STATE_READY)
{
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
- hmmc->State = HAL_MMC_STATE_BUSY;
-
- /* Initialize data control register */
- hmmc->Instance->DCTRL = 0;
- /* Check the Card capacity in term of Logical number of blocks */
- if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0U;
+
+ if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
- BlockAdd *= 512;
+ add *= 512U;
}
-
+
/* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
+ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
+
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = NumberOfBlocks * BLOCKSIZE;
+ config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_ENABLE;
- SDMMC_ConfigData(hmmc->Instance, &config);
-
+ (void)SDMMC_ConfigData(hmmc->Instance, &config);
+
/* Read block(s) in polling mode */
- if(NumberOfBlocks > 1)
+ if(NumberOfBlocks > 1U)
{
hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK;
-
- /* Read Multi Block command */
- errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, BlockAdd);
+
+ /* Read Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
}
else
{
hmmc->Context = MMC_CONTEXT_READ_SINGLE_BLOCK;
-
+
/* Read Single Block command */
- errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, BlockAdd);
+ errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
}
if(errorstate != HAL_MMC_ERROR_NONE)
{
@@ -612,21 +627,33 @@
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
+
/* Poll on SDMMC flags */
+ dataremaining = config.DataLength;
while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF))
+ if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining > 0U))
{
/* Read data from SDMMC Rx FIFO */
for(count = 0U; count < 8U; count++)
{
- *(tempbuff + count) = SDMMC_ReadFIFO(hmmc->Instance);
+ data = SDMMC_ReadFIFO(hmmc->Instance);
+ *tempbuff = (uint8_t)(data & 0xFFU);
+ tempbuff++;
+ dataremaining--;
+ *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+ tempbuff++;
+ dataremaining--;
+ *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+ tempbuff++;
+ dataremaining--;
+ *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+ tempbuff++;
+ dataremaining--;
}
- tempbuff += 8U;
}
-
- if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
+
+ if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -635,7 +662,7 @@
return HAL_TIMEOUT;
}
}
-
+
/* Send stop transmission command in case of multiblock read */
if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
{
@@ -650,7 +677,7 @@
return HAL_ERROR;
}
}
-
+
/* Get error state */
if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
{
@@ -676,14 +703,29 @@
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
- /* Empty FIFO if there is still any data */
- while ((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXDAVL)))
+ else
{
- *tempbuff = SDMMC_ReadFIFO(hmmc->Instance);
+ /* Nothing to do */
+ }
+
+ /* Empty FIFO if there is still any data */
+ while ((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXDAVL)) && (dataremaining > 0U))
+ {
+ data = SDMMC_ReadFIFO(hmmc->Instance);
+ *tempbuff = (uint8_t)(data & 0xFFU);
tempbuff++;
-
- if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
+ dataremaining--;
+ *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+ tempbuff++;
+ dataremaining--;
+ *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+ tempbuff++;
+ dataremaining--;
+ *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+ tempbuff++;
+ dataremaining--;
+
+ if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -692,12 +734,12 @@
return HAL_ERROR;
}
}
-
+
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
-
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
hmmc->State = HAL_MMC_STATE_READY;
-
+
return HAL_OK;
}
else
@@ -712,21 +754,22 @@
* transfer is managed by polling mode.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
- * @param hmmc Pointer to MMC handle
- * @param pData pointer to the buffer that will contain the data to transmit
- * @param BlockAdd Block Address where data will be written
- * @param NumberOfBlocks Number of MMC blocks to write
- * @param Timeout Specify timeout value
+ * @param hmmc: Pointer to MMC handle
+ * @param pData: pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd: Block Address where data will be written
+ * @param NumberOfBlocks: Number of MMC blocks to write
+ * @param Timeout: Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
{
SDMMC_DataInitTypeDef config;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
+ uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
- uint32_t count = 0;
- uint32_t *tempbuff = (uint32_t *)pData;
-
+ uint32_t count, data, dataremaining;
+ uint32_t add = BlockAdd;
+ uint8_t *tempbuff = pData;
+
if(NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
@@ -735,107 +778,118 @@
if(hmmc->State == HAL_MMC_STATE_READY)
{
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hmmc->State = HAL_MMC_STATE_BUSY;
-
+
/* Initialize data control register */
- hmmc->Instance->DCTRL = 0;
-
- /* Check the Card capacity in term of Logical number of blocks */
- if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
+ hmmc->Instance->DCTRL = 0U;
+
+ if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
- BlockAdd *= 512;
+ add *= 512U;
}
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
+
/* Write Blocks in Polling mode */
if(NumberOfBlocks > 1U)
{
hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK;
-
- /* Write Multi Block command */
- errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, BlockAdd);
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
}
else
{
hmmc->Context = MMC_CONTEXT_WRITE_SINGLE_BLOCK;
-
+
/* Write Single Block command */
- errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, BlockAdd);
+ errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
}
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
- /* Configure the MMC DPSM (Data Path State Machine) */
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = NumberOfBlocks * BLOCKSIZE;
+ config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_ENABLE;
- SDMMC_ConfigData(hmmc->Instance, &config);
-
+ (void)SDMMC_ConfigData(hmmc->Instance, &config);
+
/* Write block(s) in polling mode */
+ dataremaining = config.DataLength;
while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE))
+ if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining > 0U))
{
/* Write data to SDMMC Tx FIFO */
for(count = 0U; count < 8U; count++)
{
- SDMMC_WriteFIFO(hmmc->Instance, (tempbuff + count));
+ data = (uint32_t)(*tempbuff);
+ tempbuff++;
+ dataremaining--;
+ data |= ((uint32_t)(*tempbuff) << 8U);
+ tempbuff++;
+ dataremaining--;
+ data |= ((uint32_t)(*tempbuff) << 16U);
+ tempbuff++;
+ dataremaining--;
+ data |= ((uint32_t)(*tempbuff) << 24U);
+ tempbuff++;
+ dataremaining--;
+ (void)SDMMC_WriteFIFO(hmmc->Instance, &data);
}
- tempbuff += 8U;
}
-
- if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
+
+ if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_TIMEOUT;
}
}
-
+
/* Send stop transmission command in case of multiblock write */
if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
- {
+ {
/* Send stop transmission command */
errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
}
-
+
/* Get error state */
if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
{
@@ -849,7 +903,7 @@
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
@@ -861,12 +915,16 @@
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
+ else
+ {
+ /* Nothing to do */
+ }
+
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
-
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
hmmc->State = HAL_MMC_STATE_READY;
-
+
return HAL_OK;
}
else
@@ -877,99 +935,100 @@
}
/**
- * @brief Reads block(s) from a specified address in a card. The Data transfer
- * is managed in interrupt mode.
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed in interrupt mode.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
- * @note You could also check the IT transfer process through the MMC Rx
+ * @note You could also check the IT transfer process through the MMC Rx
* interrupt event.
- * @param hmmc Pointer to MMC handle
- * @param pData Pointer to the buffer that will contain the received data
- * @param BlockAdd Block Address from where data is to be read
- * @param NumberOfBlocks Number of blocks to read.
+ * @param hmmc: Pointer to MMC handle
+ * @param pData: Pointer to the buffer that will contain the received data
+ * @param BlockAdd: Block Address from where data is to be read
+ * @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
-
+ uint32_t errorstate;
+ uint32_t add = BlockAdd;
+
if(NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
-
+
if(hmmc->State == HAL_MMC_STATE_READY)
{
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hmmc->State = HAL_MMC_STATE_BUSY;
-
+
/* Initialize data control register */
hmmc->Instance->DCTRL = 0U;
-
- hmmc->pRxBuffPtr = (uint32_t *)pData;
- hmmc->RxXferSize = BLOCKSIZE * NumberOfBlocks;
-
+
+ hmmc->pRxBuffPtr = pData;
+ hmmc->RxXferSize = MMC_BLOCKSIZE * NumberOfBlocks;
+
__HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF));
-
- /* Check the Card capacity in term of Logical number of blocks */
- if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
+
+ if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
- BlockAdd *= 512;
+ add *= 512U;
}
-
- /* Configure the MMC DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
- config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
- config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- config.DPSM = SDMMC_DPSM_ENABLE;
- SDMMC_ConfigData(hmmc->Instance, &config);
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_ENABLE;
+ (void)SDMMC_ConfigData(hmmc->Instance, &config);
+
/* Read Blocks in IT mode */
if(NumberOfBlocks > 1U)
{
hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_IT);
-
+
/* Read Multi Block command */
- errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, BlockAdd);
+ errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
}
else
{
hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_IT);
-
+
/* Read Single Block command */
- errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, BlockAdd);
+ errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
}
+
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
+
return HAL_OK;
}
else
@@ -979,99 +1038,99 @@
}
/**
- * @brief Writes block(s) to a specified address in a card. The Data transfer
- * is managed in interrupt mode.
+ * @brief Writes block(s) to a specified address in a card. The Data transfer
+ * is managed in interrupt mode.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
- * @note You could also check the IT transfer process through the MMC Tx
- * interrupt event.
- * @param hmmc Pointer to MMC handle
- * @param pData Pointer to the buffer that will contain the data to transmit
- * @param BlockAdd Block Address where data will be written
- * @param NumberOfBlocks Number of blocks to write
+ * @note You could also check the IT transfer process through the MMC Tx
+ * interrupt event.
+ * @param hmmc: Pointer to MMC handle
+ * @param pData: Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd: Block Address where data will be written
+ * @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
-
+ uint32_t errorstate;
+ uint32_t add = BlockAdd;
+
if(NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
-
+
if(hmmc->State == HAL_MMC_STATE_READY)
{
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hmmc->State = HAL_MMC_STATE_BUSY;
-
+
/* Initialize data control register */
hmmc->Instance->DCTRL = 0U;
-
- hmmc->pTxBuffPtr = (uint32_t *)pData;
- hmmc->TxXferSize = BLOCKSIZE * NumberOfBlocks;
-
+
+ hmmc->pTxBuffPtr = pData;
+ hmmc->TxXferSize = MMC_BLOCKSIZE * NumberOfBlocks;
+
/* Enable transfer interrupts */
- __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE));
-
- /* Check the Card capacity in term of Logical number of blocks */
- if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
+ __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE));
+
+ if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
- BlockAdd *= 512;
+ add *= 512U;
}
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
+
/* Write Blocks in Polling mode */
if(NumberOfBlocks > 1U)
{
hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK| MMC_CONTEXT_IT);
-
- /* Write Multi Block command */
- errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, BlockAdd);
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
}
else
{
hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_IT);
-
- /* Write Single Block command */
- errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, BlockAdd);
+
+ /* Write Single Block command */
+ errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
}
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
+
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
+ config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_ENABLE;
- SDMMC_ConfigData(hmmc->Instance, &config);
+ (void)SDMMC_ConfigData(hmmc->Instance, &config);
return HAL_OK;
}
@@ -1082,112 +1141,122 @@
}
/**
- * @brief Reads block(s) from a specified address in a card. The Data transfer
- * is managed by DMA mode.
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed by DMA mode.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
- * @note You could also check the DMA transfer process through the MMC Rx
+ * @note You could also check the DMA transfer process through the MMC Rx
* interrupt event.
- * @param hmmc Pointer MMC handle
- * @param pData Pointer to the buffer that will contain the received data
- * @param BlockAdd Block Address from where data is to be read
- * @param NumberOfBlocks Number of blocks to read.
+ * @param hmmc: Pointer MMC handle
+ * @param pData: Pointer to the buffer that will contain the received data
+ * @param BlockAdd: Block Address from where data is to be read
+ * @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
-
+ uint32_t errorstate;
+ uint32_t add = BlockAdd;
+
if(NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
-
+
if(hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
+
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hmmc->State = HAL_MMC_STATE_BUSY;
-
+
/* Initialize data control register */
hmmc->Instance->DCTRL = 0U;
-
+
__HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
-
+
/* Set the DMA transfer complete callback */
hmmc->hdmarx->XferCpltCallback = MMC_DMAReceiveCplt;
-
+
/* Set the DMA error callback */
hmmc->hdmarx->XferErrorCallback = MMC_DMAError;
-
+
/* Set the DMA Abort callback */
hmmc->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA Channel */
- HAL_DMA_Start_IT(hmmc->hdmarx, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4);
-
- /* Enable MMC DMA transfer */
- __HAL_MMC_DMA_ENABLE(hmmc);
-
- /* Check the Card capacity in term of Logical number of blocks */
- if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
+
+ if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
- BlockAdd *= 512;
+ add *= 512U;
}
-
- /* Configure the MMC DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
- config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
- config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- config.DPSM = SDMMC_DPSM_ENABLE;
- SDMMC_ConfigData(hmmc->Instance, &config);
/* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
+ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
+ hmmc->ErrorCode = errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
- /* Read Blocks in DMA mode */
- if(NumberOfBlocks > 1U)
+
+ /* Enable the DMA Channel */
+ if(HAL_DMA_Start_IT(hmmc->hdmarx, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)pData, (uint32_t)(MMC_BLOCKSIZE * NumberOfBlocks)/4) != HAL_OK)
{
- hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
-
- /* Read Multi Block command */
- errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, BlockAdd);
+ __HAL_MMC_DISABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode = HAL_MMC_ERROR_DMA;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
}
else
{
- hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_DMA);
-
- /* Read Single Block command */
- errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, BlockAdd);
- }
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
+ /* Enable MMC DMA transfer */
+ __HAL_MMC_DMA_ENABLE(hmmc);
- return HAL_OK;
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_ENABLE;
+ (void)SDMMC_ConfigData(hmmc->Instance, &config);
+
+ /* Read Blocks in DMA mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
+
+ /* Read Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
+ }
+ else
+ {
+ hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_DMA);
+
+ /* Read Single Block command */
+ errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
+ }
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_DISABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
+ hmmc->ErrorCode = errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+ }
}
else
{
@@ -1196,113 +1265,123 @@
}
/**
- * @brief Writes block(s) to a specified address in a card. The Data transfer
- * is managed by DMA mode.
+ * @brief Writes block(s) to a specified address in a card. The Data transfer
+ * is managed by DMA mode.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
- * @note You could also check the DMA transfer process through the MMC Tx
+ * @note You could also check the DMA transfer process through the MMC Tx
* interrupt event.
- * @param hmmc Pointer to MMC handle
- * @param pData Pointer to the buffer that will contain the data to transmit
- * @param BlockAdd Block Address where data will be written
- * @param NumberOfBlocks Number of blocks to write
+ * @param hmmc: Pointer to MMC handle
+ * @param pData: Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd: Block Address where data will be written
+ * @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
-
+ uint32_t errorstate;
+ uint32_t add = BlockAdd;
+
if(NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
-
+
if(hmmc->State == HAL_MMC_STATE_READY)
{
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hmmc->State = HAL_MMC_STATE_BUSY;
-
+
/* Initialize data control register */
hmmc->Instance->DCTRL = 0U;
-
+
/* Enable MMC Error interrupts */
- __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR));
-
+ __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR));
+
/* Set the DMA transfer complete callback */
hmmc->hdmatx->XferCpltCallback = MMC_DMATransmitCplt;
-
+
/* Set the DMA error callback */
hmmc->hdmatx->XferErrorCallback = MMC_DMAError;
-
+
/* Set the DMA Abort callback */
hmmc->hdmatx->XferAbortCallback = NULL;
-
- /* Check the Card capacity in term of Logical number of blocks */
- if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
+
+ if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
- BlockAdd *= 512;
+ add *= 512U;
}
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
+
/* Write Blocks in Polling mode */
if(NumberOfBlocks > 1U)
{
hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
-
- /* Write Multi Block command */
- errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, BlockAdd);
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
}
else
{
hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_DMA);
-
+
/* Write Single Block command */
- errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, BlockAdd);
+ errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
}
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_DISABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND));
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
+
/* Enable SDMMC DMA transfer */
__HAL_MMC_DMA_ENABLE(hmmc);
-
+
/* Enable the DMA Channel */
- HAL_DMA_Start_IT(hmmc->hdmatx, (uint32_t)pData, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4);
-
- /* Configure the MMC DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
- config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
- config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- config.DPSM = SDMMC_DPSM_ENABLE;
- SDMMC_ConfigData(hmmc->Instance, &config);
-
- return HAL_OK;
+ if(HAL_DMA_Start_IT(hmmc->hdmatx, (uint32_t)pData, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)(MMC_BLOCKSIZE * NumberOfBlocks)/4) != HAL_OK)
+ {
+ __HAL_MMC_DISABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND));
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DMA;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_ENABLE;
+ (void)SDMMC_ConfigData(hmmc->Instance, &config);
+
+ return HAL_OK;
+ }
}
else
{
@@ -1314,33 +1393,35 @@
* @brief Erases the specified memory area of the given MMC card.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
- * @param hmmc Pointer to MMC handle
- * @param BlockStartAdd Start Block address
- * @param BlockEndAdd End Block address
+ * @param hmmc: Pointer to MMC handle
+ * @param BlockStartAdd: Start Block address
+ * @param BlockEndAdd: End Block address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
{
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
-
+ uint32_t errorstate;
+ uint32_t start_add = BlockStartAdd;
+ uint32_t end_add = BlockEndAdd;
+
if(hmmc->State == HAL_MMC_STATE_READY)
{
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if(BlockEndAdd < BlockStartAdd)
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
+ if(end_add < start_add)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
-
- if(BlockEndAdd > (hmmc->MmcCard.LogBlockNbr))
+
+ if(end_add > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hmmc->State = HAL_MMC_STATE_BUSY;
-
+
/* Check if the card command class supports erase command */
if(((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U)
{
@@ -1350,58 +1431,57 @@
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
+
if((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_LOCK_UNLOCK_FAILED;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
- /* Check the Card capacity in term of Logical number of blocks */
- if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
+
+ if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
- BlockStartAdd *= 512U;
- BlockEndAdd *= 512U;
+ start_add *= 512U;
+ end_add *= 512U;
}
/* Send CMD35 MMC_ERASE_GRP_START with argument as addr */
- errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, BlockStartAdd);
+ errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
+
/* Send CMD36 MMC_ERASE_GRP_END with argument as addr */
- errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, BlockEndAdd);
+ errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, end_add);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
+
/* Send CMD38 ERASE */
errorstate = SDMMC_CmdErase(hmmc->Instance);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
+
hmmc->State = HAL_MMC_STATE_READY;
-
+
return HAL_OK;
}
else
@@ -1412,74 +1492,46 @@
/**
* @brief This function handles MMC card interrupt request.
- * @param hmmc Pointer to MMC handle
+ * @param hmmc: Pointer to MMC handle
* @retval None
*/
void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
{
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
-
+ uint32_t errorstate;
+ uint32_t context = hmmc->Context;
+
/* Check for SDMMC interrupt flags */
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DATAEND) != RESET)
+ if((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & MMC_CONTEXT_IT) != 0U))
{
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DATAEND);
+ MMC_Read_IT(hmmc);
+ }
+
+ else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) != RESET)
+ {
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DATAEND);
+
+ __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT |\
+ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\
+ SDMMC_IT_RXFIFOHF);
- __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
- SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
-
- if((hmmc->Context & MMC_CONTEXT_IT) != RESET)
+ hmmc->Instance->DCTRL &= ~(SDMMC_DCTRL_DTEN);
+
+ if((context & MMC_CONTEXT_DMA) != 0U)
{
- if(((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != RESET) || ((hmmc->Context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET))
+ if((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
{
errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->ErrorCallback(hmmc);
#else
HAL_MMC_ErrorCallback(hmmc);
#endif
}
}
-
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
-
- hmmc->State = HAL_MMC_STATE_READY;
- if(((hmmc->Context & MMC_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != RESET))
- {
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
- hmmc->RxCpltCallback(hmmc);
-#else
- HAL_MMC_RxCpltCallback(hmmc);
-#endif
- }
- else
- {
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
- hmmc->TxCpltCallback(hmmc);
-#else
- HAL_MMC_TxCpltCallback(hmmc);
-#endif
- }
- }
- else if((hmmc->Context & MMC_CONTEXT_DMA) != RESET)
- {
- if((hmmc->Context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)
- {
- errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->ErrorCode |= errorstate;
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
- hmmc->ErrorCallback(hmmc);
-#else
- HAL_MMC_ErrorCallback(hmmc);
-#endif
- }
- }
- if(((hmmc->Context & MMC_CONTEXT_READ_SINGLE_BLOCK) == RESET) && ((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) == RESET))
+ if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) == 0U))
{
/* Disable the DMA transfer for transmit request by setting the DMAEN bit
in the MMC DCTRL register */
@@ -1487,57 +1539,102 @@
hmmc->State = HAL_MMC_STATE_READY;
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->TxCpltCallback(hmmc);
-#else
+#else
HAL_MMC_TxCpltCallback(hmmc);
#endif
}
}
+ else if((context & MMC_CONTEXT_IT) != 0U)
+ {
+ /* Stop Transfer for Write Multi blocks or Read Multi blocks */
+ if(((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+ {
+ errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ hmmc->ErrorCallback(hmmc);
+#else
+ HAL_MMC_ErrorCallback(hmmc);
+#endif
+ }
+ }
+
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
+ hmmc->State = HAL_MMC_STATE_READY;
+ if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+ {
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ hmmc->RxCpltCallback(hmmc);
+#else
+ HAL_MMC_RxCpltCallback(hmmc);
+#endif
+ }
+ else
+ {
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ hmmc->TxCpltCallback(hmmc);
+#else
+ HAL_MMC_TxCpltCallback(hmmc);
+#endif
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
}
-
- else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXFIFOHE) != RESET)
+
+ else if((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & MMC_CONTEXT_IT) != 0U))
{
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE);
-
MMC_Write_IT(hmmc);
}
-
- else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXFIFOHF) != RESET)
- {
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF);
-
- MMC_Read_IT(hmmc);
- }
-
- else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_TXUNDERR) != RESET)
+
+ else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET)
{
/* Set Error code */
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL) != RESET)
+ if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL) != RESET)
{
- hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
}
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DTIMEOUT) != RESET)
+ if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT) != RESET)
{
- hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
}
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXOVERR) != RESET)
+ if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR) != RESET)
{
- hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
+ hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
}
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXUNDERR) != RESET)
+ if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR) != RESET)
{
- hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
}
-
+
/* Clear All flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
/* Disable all interrupts */
__HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
-
- if((hmmc->Context & MMC_CONTEXT_DMA) != RESET)
+
+ hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance);
+
+ if((context & MMC_CONTEXT_IT) != 0U)
+ {
+ /* Set the MMC state to ready to be able to start again the process */
+ hmmc->State = HAL_MMC_STATE_READY;
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ hmmc->ErrorCallback(hmmc);
+#else
+ HAL_MMC_ErrorCallback(hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+ }
+ else if((context & MMC_CONTEXT_DMA) != 0U)
{
/* Abort the MMC DMA Streams */
if(hmmc->hdmatx != NULL)
@@ -1564,29 +1661,28 @@
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
hmmc->State = HAL_MMC_STATE_READY;
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->AbortCpltCallback(hmmc);
#else
HAL_MMC_AbortCallback(hmmc);
#endif
}
}
- else if((hmmc->Context & MMC_CONTEXT_IT) != RESET)
+ else
{
- /* Set the MMC state to ready to be able to start again the process */
- hmmc->State = HAL_MMC_STATE_READY;
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
- hmmc->ErrorCallback(hmmc);
-#else
- HAL_MMC_ErrorCallback(hmmc);
-#endif
+ /* Nothing to do */
}
- }
+ }
+
+ else
+ {
+ /* Nothing to do */
+ }
}
/**
* @brief return the MMC state
- * @param hmmc Pointer to mmc handle
+ * @param hmmc: Pointer to mmc handle
* @retval HAL state
*/
HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc)
@@ -1596,7 +1692,7 @@
/**
* @brief Return the MMC error code
-* @param hmmc Pointer to a MMC_HandleTypeDef structure that contains
+* @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains
* the configuration information.
* @retval MMC Error Code
*/
@@ -1607,10 +1703,10 @@
/**
* @brief Tx Transfer completed callbacks
- * @param hmmc Pointer to MMC handle
+ * @param hmmc: Pointer to MMC handle
* @retval None
*/
- __weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc)
+__weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmmc);
@@ -1622,14 +1718,14 @@
/**
* @brief Rx Transfer completed callbacks
- * @param hmmc Pointer MMC handle
+ * @param hmmc: Pointer MMC handle
* @retval None
*/
__weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmmc);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MMC_RxCpltCallback can be implemented in the user file
*/
@@ -1637,47 +1733,47 @@
/**
* @brief MMC error callbacks
- * @param hmmc Pointer MMC handle
+ * @param hmmc: Pointer MMC handle
* @retval None
*/
__weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmmc);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MMC_ErrorCallback can be implemented in the user file
- */
+ */
}
/**
* @brief MMC Abort callbacks
- * @param hmmc Pointer MMC handle
+ * @param hmmc: Pointer MMC handle
* @retval None
*/
__weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmmc);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_MMC_ErrorCallback can be implemented in the user file
- */
+ the HAL_MMC_AbortCallback can be implemented in the user file
+ */
}
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
/**
* @brief Register a User MMC Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used instead of the weak (surcharged) predefined callback
* @param hmmc : MMC handle
- * @param CallbackID : ID of the callback to be registered
+ * @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID
* @arg @ref HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID
* @arg @ref HAL_MMC_ERROR_CB_ID MMC Error Callback ID
* @arg @ref HAL_MMC_ABORT_CB_ID MMC Abort Callback ID
- * @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID
- * @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID
+ * @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID
+ * @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID
* @param pCallback : pointer to the Callback function
* @retval status
*/
@@ -1694,7 +1790,7 @@
/* Process locked */
__HAL_LOCK(hmmc);
-
+
if(hmmc->State == HAL_MMC_STATE_READY)
{
switch (CallbackId)
@@ -1719,7 +1815,7 @@
break;
default :
/* Update the error code */
- hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
@@ -1737,7 +1833,7 @@
break;
default :
/* Update the error code */
- hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
@@ -1746,7 +1842,7 @@
else
{
/* Update the error code */
- hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
@@ -1758,16 +1854,16 @@
/**
* @brief Unregister a User MMC Callback
- * MMC Callback is redirected to the weak (surcharged) predefined callback
+ * MMC Callback is redirected to the weak (surcharged) predefined callback
* @param hmmc : MMC handle
- * @param CallbackID : ID of the callback to be unregistered
+ * @param CallbackId : ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID
* @arg @ref HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID
* @arg @ref HAL_MMC_ERROR_CB_ID MMC Error Callback ID
* @arg @ref HAL_MMC_ABORT_CB_ID MMC Abort Callback ID
- * @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID
- * @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID
+ * @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID
+ * @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId)
@@ -1776,7 +1872,7 @@
/* Process locked */
__HAL_LOCK(hmmc);
-
+
if(hmmc->State == HAL_MMC_STATE_READY)
{
switch (CallbackId)
@@ -1801,7 +1897,7 @@
break;
default :
/* Update the error code */
- hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
@@ -1819,7 +1915,7 @@
break;
default :
/* Update the error code */
- hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
@@ -1828,7 +1924,7 @@
else
{
/* Update the error code */
- hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
@@ -1839,20 +1935,19 @@
}
#endif
-
/**
* @}
*/
/** @addtogroup MMC_Exported_Functions_Group3
- * @brief management functions
+ * @brief management functions
*
-@verbatim
+@verbatim
==============================================================================
##### Peripheral Control functions #####
- ==============================================================================
+ ==============================================================================
[..]
- This subsection provides a set of functions allowing to control the MMC card
+ This subsection provides a set of functions allowing to control the MMC card
operations and get the related information
@endverbatim
@@ -1862,80 +1957,32 @@
/**
* @brief Returns information the information of the card which are stored on
* the CID register.
- * @param hmmc Pointer to MMC handle
- * @param pCID Pointer to a HAL_MMC_CIDTypedef structure that
- * contains all CID register parameters
+ * @param hmmc: Pointer to MMC handle
+ * @param pCID: Pointer to a HAL_MMC_CIDTypedef structure that
+ * contains all CID register parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID)
{
- uint32_t tmp = 0;
-
- /* Byte 0 */
- tmp = (uint8_t)((hmmc->CID[0] & 0xFF000000U) >> 24);
- pCID->ManufacturerID = tmp;
-
- /* Byte 1 */
- tmp = (uint8_t)((hmmc->CID[0] & 0x00FF0000) >> 16);
- pCID->OEM_AppliID = tmp << 8;
-
- /* Byte 2 */
- tmp = (uint8_t)((hmmc->CID[0] & 0x000000FF00) >> 8);
- pCID->OEM_AppliID |= tmp;
-
- /* Byte 3 */
- tmp = (uint8_t)(hmmc->CID[0] & 0x000000FF);
- pCID->ProdName1 = tmp << 24;
-
- /* Byte 4 */
- tmp = (uint8_t)((hmmc->CID[1] & 0xFF000000U) >> 24);
- pCID->ProdName1 |= tmp << 16;
-
- /* Byte 5 */
- tmp = (uint8_t)((hmmc->CID[1] & 0x00FF0000) >> 16);
- pCID->ProdName1 |= tmp << 8;
-
- /* Byte 6 */
- tmp = (uint8_t)((hmmc->CID[1] & 0x0000FF00) >> 8);
- pCID->ProdName1 |= tmp;
-
- /* Byte 7 */
- tmp = (uint8_t)(hmmc->CID[1] & 0x000000FF);
- pCID->ProdName2 = tmp;
-
- /* Byte 8 */
- tmp = (uint8_t)((hmmc->CID[2] & 0xFF000000U) >> 24);
- pCID->ProdRev = tmp;
-
- /* Byte 9 */
- tmp = (uint8_t)((hmmc->CID[2] & 0x00FF0000) >> 16);
- pCID->ProdSN = tmp << 24;
-
- /* Byte 10 */
- tmp = (uint8_t)((hmmc->CID[2] & 0x0000FF00) >> 8);
- pCID->ProdSN |= tmp << 16;
-
- /* Byte 11 */
- tmp = (uint8_t)(hmmc->CID[2] & 0x000000FF);
- pCID->ProdSN |= tmp << 8;
-
- /* Byte 12 */
- tmp = (uint8_t)((hmmc->CID[3] & 0xFF000000U) >> 24);
- pCID->ProdSN |= tmp;
-
- /* Byte 13 */
- tmp = (uint8_t)((hmmc->CID[3] & 0x00FF0000) >> 16);
- pCID->Reserved1 |= (tmp & 0xF0) >> 4;
- pCID->ManufactDate = (tmp & 0x0F) << 8;
-
- /* Byte 14 */
- tmp = (uint8_t)((hmmc->CID[3] & 0x0000FF00) >> 8);
- pCID->ManufactDate |= tmp;
-
- /* Byte 15 */
- tmp = (uint8_t)(hmmc->CID[3] & 0x000000FF);
- pCID->CID_CRC = (tmp & 0xFE) >> 1;
- pCID->Reserved2 = 1;
+ pCID->ManufacturerID = (uint8_t)((hmmc->CID[0] & 0xFF000000U) >> 24U);
+
+ pCID->OEM_AppliID = (uint16_t)((hmmc->CID[0] & 0x00FFFF00U) >> 8U);
+
+ pCID->ProdName1 = (((hmmc->CID[0] & 0x000000FFU) << 24U) | ((hmmc->CID[1] & 0xFFFFFF00U) >> 8U));
+
+ pCID->ProdName2 = (uint8_t)(hmmc->CID[1] & 0x000000FFU);
+
+ pCID->ProdRev = (uint8_t)((hmmc->CID[2] & 0xFF000000U) >> 24U);
+
+ pCID->ProdSN = (((hmmc->CID[2] & 0x00FFFFFFU) << 8U) | ((hmmc->CID[3] & 0xFF000000U) >> 24U));
+
+ pCID->Reserved1 = (uint8_t)((hmmc->CID[3] & 0x00F00000U) >> 20U);
+
+ pCID->ManufactDate = (uint16_t)((hmmc->CID[3] & 0x000FFF00U) >> 8U);
+
+ pCID->CID_CRC = (uint8_t)((hmmc->CID[3] & 0x000000FEU) >> 1U);
+
+ pCID->Reserved2 = 1U;
return HAL_OK;
}
@@ -1943,123 +1990,102 @@
/**
* @brief Returns information the information of the card which are stored on
* the CSD register.
- * @param hmmc Pointer to MMC handle
- * @param pCSD Pointer to a HAL_MMC_CardInfoTypeDef structure that
- * contains all CSD register parameters
+ * @param hmmc: Pointer to MMC handle
+ * @param pCSD: Pointer to a HAL_MMC_CardCSDTypeDef structure that
+ * contains all CSD register parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD)
{
- uint32_t tmp = 0;
+ pCSD->CSDStruct = (uint8_t)((hmmc->CSD[0] & 0xC0000000U) >> 30U);
+
+ pCSD->SysSpecVersion = (uint8_t)((hmmc->CSD[0] & 0x3C000000U) >> 26U);
+
+ pCSD->Reserved1 = (uint8_t)((hmmc->CSD[0] & 0x03000000U) >> 24U);
+
+ pCSD->TAAC = (uint8_t)((hmmc->CSD[0] & 0x00FF0000U) >> 16U);
+
+ pCSD->NSAC = (uint8_t)((hmmc->CSD[0] & 0x0000FF00U) >> 8U);
+
+ pCSD->MaxBusClkFrec = (uint8_t)(hmmc->CSD[0] & 0x000000FFU);
+
+ pCSD->CardComdClasses = (uint16_t)((hmmc->CSD[1] & 0xFFF00000U) >> 20U);
+
+ pCSD->RdBlockLen = (uint8_t)((hmmc->CSD[1] & 0x000F0000U) >> 16U);
+
+ pCSD->PartBlockRead = (uint8_t)((hmmc->CSD[1] & 0x00008000U) >> 15U);
+
+ pCSD->WrBlockMisalign = (uint8_t)((hmmc->CSD[1] & 0x00004000U) >> 14U);
+
+ pCSD->RdBlockMisalign = (uint8_t)((hmmc->CSD[1] & 0x00002000U) >> 13U);
+
+ pCSD->DSRImpl = (uint8_t)((hmmc->CSD[1] & 0x00001000U) >> 12U);
+
+ pCSD->Reserved2 = 0U; /*!< Reserved */
+
+ pCSD->DeviceSize = (((hmmc->CSD[1] & 0x000003FFU) << 2U) | ((hmmc->CSD[2] & 0xC0000000U) >> 30U));
+
+ pCSD->MaxRdCurrentVDDMin = (uint8_t)((hmmc->CSD[2] & 0x38000000U) >> 27U);
+
+ pCSD->MaxRdCurrentVDDMax = (uint8_t)((hmmc->CSD[2] & 0x07000000U) >> 24U);
+
+ pCSD->MaxWrCurrentVDDMin = (uint8_t)((hmmc->CSD[2] & 0x00E00000U) >> 21U);
+
+ pCSD->MaxWrCurrentVDDMax = (uint8_t)((hmmc->CSD[2] & 0x001C0000U) >> 18U);
+
+ pCSD->DeviceSizeMul = (uint8_t)((hmmc->CSD[2] & 0x00038000U) >> 15U);
+
+ hmmc->MmcCard.BlockNbr = (pCSD->DeviceSize + 1U) ;
+ hmmc->MmcCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
+ hmmc->MmcCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
+
+ hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U);
+ hmmc->MmcCard.LogBlockSize = 512U;
- /* Byte 0 */
- tmp = (hmmc->CSD[0] & 0xFF000000U) >> 24;
- pCSD->CSDStruct = (uint8_t)((tmp & 0xC0) >> 6);
- pCSD->SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2);
- pCSD->Reserved1 = tmp & 0x03;
-
- /* Byte 1 */
- tmp = (hmmc->CSD[0] & 0x00FF0000) >> 16;
- pCSD->TAAC = (uint8_t)tmp;
-
- /* Byte 2 */
- tmp = (hmmc->CSD[0] & 0x0000FF00) >> 8;
- pCSD->NSAC = (uint8_t)tmp;
-
- /* Byte 3 */
- tmp = hmmc->CSD[0] & 0x000000FF;
- pCSD->MaxBusClkFrec = (uint8_t)tmp;
-
- /* Byte 4 */
- tmp = (hmmc->CSD[1] & 0xFF000000U) >> 24;
- pCSD->CardComdClasses = (uint16_t)(tmp << 4);
-
- /* Byte 5 */
- tmp = (hmmc->CSD[1] & 0x00FF0000U) >> 16;
- pCSD->CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4);
- pCSD->RdBlockLen = (uint8_t)(tmp & 0x0F);
-
- /* Byte 6 */
- tmp = (hmmc->CSD[1] & 0x0000FF00U) >> 8;
- pCSD->PartBlockRead = (uint8_t)((tmp & 0x80) >> 7);
- pCSD->WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6);
- pCSD->RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5);
- pCSD->DSRImpl = (uint8_t)((tmp & 0x10) >> 4);
- pCSD->Reserved2 = 0; /*!< Reserved */
-
- pCSD->DeviceSize = (tmp & 0x03) << 10;
-
- /* Byte 7 */
- tmp = (uint8_t)(hmmc->CSD[1] & 0x000000FFU);
- pCSD->DeviceSize |= (tmp) << 2;
-
- /* Byte 8 */
- tmp = (uint8_t)((hmmc->CSD[2] & 0xFF000000U) >> 24);
- pCSD->DeviceSize |= (tmp & 0xC0) >> 6;
-
- pCSD->MaxRdCurrentVDDMin = (tmp & 0x38) >> 3;
- pCSD->MaxRdCurrentVDDMax = (tmp & 0x07);
-
- /* Byte 9 */
- tmp = (uint8_t)((hmmc->CSD[2] & 0x00FF0000U) >> 16);
- pCSD->MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5;
- pCSD->MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2;
- pCSD->DeviceSizeMul = (tmp & 0x03) << 1;
- /* Byte 10 */
- tmp = (uint8_t)((hmmc->CSD[2] & 0x0000FF00U) >> 8);
- pCSD->DeviceSizeMul |= (tmp & 0x80) >> 7;
-
- hmmc->MmcCard.BlockNbr = (pCSD->DeviceSize + 1) ;
- hmmc->MmcCard.BlockNbr *= (1 << (pCSD->DeviceSizeMul + 2));
- hmmc->MmcCard.BlockSize = 1 << (pCSD->RdBlockLen);
-
- hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512);
- hmmc->MmcCard.LogBlockSize = 512;
-
- pCSD->EraseGrSize = (tmp & 0x40) >> 6;
- pCSD->EraseGrMul = (tmp & 0x3F) << 1;
-
- /* Byte 11 */
- tmp = (uint8_t)(hmmc->CSD[2] & 0x000000FF);
- pCSD->EraseGrMul |= (tmp & 0x80) >> 7;
- pCSD->WrProtectGrSize = (tmp & 0x7F);
-
- /* Byte 12 */
- tmp = (uint8_t)((hmmc->CSD[3] & 0xFF000000U) >> 24);
- pCSD->WrProtectGrEnable = (tmp & 0x80) >> 7;
- pCSD->ManDeflECC = (tmp & 0x60) >> 5;
- pCSD->WrSpeedFact = (tmp & 0x1C) >> 2;
- pCSD->MaxWrBlockLen = (tmp & 0x03) << 2;
-
- /* Byte 13 */
- tmp = (uint8_t)((hmmc->CSD[3] & 0x00FF0000) >> 16);
- pCSD->MaxWrBlockLen |= (tmp & 0xC0) >> 6;
- pCSD->WriteBlockPaPartial = (tmp & 0x20) >> 5;
- pCSD->Reserved3 = 0;
- pCSD->ContentProtectAppli = (tmp & 0x01);
-
- /* Byte 14 */
- tmp = (uint8_t)((hmmc->CSD[3] & 0x0000FF00) >> 8);
- pCSD->FileFormatGrouop = (tmp & 0x80) >> 7;
- pCSD->CopyFlag = (tmp & 0x40) >> 6;
- pCSD->PermWrProtect = (tmp & 0x20) >> 5;
- pCSD->TempWrProtect = (tmp & 0x10) >> 4;
- pCSD->FileFormat = (tmp & 0x0C) >> 2;
- pCSD->ECC = (tmp & 0x03);
-
- /* Byte 15 */
- tmp = (uint8_t)(hmmc->CSD[3] & 0x000000FF);
- pCSD->CSD_CRC = (tmp & 0xFE) >> 1;
+ pCSD->EraseGrSize = (uint8_t)((hmmc->CSD[2] & 0x00004000U) >> 14U);
+
+ pCSD->EraseGrMul = (uint8_t)((hmmc->CSD[2] & 0x00003F80U) >> 7U);
+
+ pCSD->WrProtectGrSize = (uint8_t)(hmmc->CSD[2] & 0x0000007FU);
+
+ pCSD->WrProtectGrEnable = (uint8_t)((hmmc->CSD[3] & 0x80000000U) >> 31U);
+
+ pCSD->ManDeflECC = (uint8_t)((hmmc->CSD[3] & 0x60000000U) >> 29U);
+
+ pCSD->WrSpeedFact = (uint8_t)((hmmc->CSD[3] & 0x1C000000U) >> 26U);
+
+ pCSD->MaxWrBlockLen= (uint8_t)((hmmc->CSD[3] & 0x03C00000U) >> 22U);
+
+ pCSD->WriteBlockPaPartial = (uint8_t)((hmmc->CSD[3] & 0x00200000U) >> 21U);
+
+ pCSD->Reserved3 = 0;
+
+ pCSD->ContentProtectAppli = (uint8_t)((hmmc->CSD[3] & 0x00010000U) >> 16U);
+
+ pCSD->FileFormatGroup = (uint8_t)((hmmc->CSD[3] & 0x00008000U) >> 15U);
+
+ pCSD->CopyFlag = (uint8_t)((hmmc->CSD[3] & 0x00004000U) >> 14U);
+
+ pCSD->PermWrProtect = (uint8_t)((hmmc->CSD[3] & 0x00002000U) >> 13U);
+
+ pCSD->TempWrProtect = (uint8_t)((hmmc->CSD[3] & 0x00001000U) >> 12U);
+
+ pCSD->FileFormat = (uint8_t)((hmmc->CSD[3] & 0x00000C00U) >> 10U);
+
+ pCSD->ECC= (uint8_t)((hmmc->CSD[3] & 0x00000300U) >> 8U);
+
+ pCSD->CSD_CRC = (uint8_t)((hmmc->CSD[3] & 0x000000FEU) >> 1U);
+
pCSD->Reserved4 = 1;
-
+
return HAL_OK;
}
/**
* @brief Gets the MMC card info.
- * @param hmmc Pointer to MMC handle
- * @param pCardInfo Pointer to the HAL_MMC_CardInfoTypeDef structure that
- * will contain the MMC card status information
+ * @param hmmc: Pointer to MMC handle
+ * @param pCardInfo: Pointer to the HAL_MMC_CardInfoTypeDef structure that
+ * will contain the MMC card status information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo)
@@ -2071,15 +2097,15 @@
pCardInfo->BlockSize = (uint32_t)(hmmc->MmcCard.BlockSize);
pCardInfo->LogBlockNbr = (uint32_t)(hmmc->MmcCard.LogBlockNbr);
pCardInfo->LogBlockSize = (uint32_t)(hmmc->MmcCard.LogBlockSize);
-
+
return HAL_OK;
}
/**
- * @brief Enables wide bus operation for the requested card if supported by
+ * @brief Enables wide bus operation for the requested card if supported by
* card.
- * @param hmmc Pointer to MMC handle
- * @param WideMode Specifies the MMC card wide bus mode
+ * @param hmmc: Pointer to MMC handle
+ * @param WideMode: Specifies the MMC card wide bus mode
* This parameter can be one of the following values:
* @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer
* @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer
@@ -2088,17 +2114,17 @@
*/
HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode)
{
- __IO uint32_t count = 0;
+ __IO uint32_t count = 0U;
SDMMC_InitTypeDef Init;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
- uint32_t response = 0, busy = 0;
-
- /* Check the parameters */
+ uint32_t errorstate;
+ uint32_t response = 0U, busy = 0U;
+
+ /* Check the parameters */
assert_param(IS_SDMMC_BUS_WIDE(WideMode));
-
+
/* Chnage Satte */
hmmc->State = HAL_MMC_STATE_BUSY;
-
+
/* Update Clock for Bus mode update */
Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
Init.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE;
@@ -2107,11 +2133,11 @@
Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
Init.ClockDiv = SDMMC_INIT_CLK_DIV;
/* Initialize SDMMC*/
- SDMMC_Init(hmmc->Instance, Init);
-
+ (void)SDMMC_Init(hmmc->Instance, Init);
+
if(WideMode == SDMMC_BUS_WIDE_8B)
{
- errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200);
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U);
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
@@ -2119,7 +2145,7 @@
}
else if(WideMode == SDMMC_BUS_WIDE_4B)
{
- errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100);
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U);
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
@@ -2127,7 +2153,7 @@
}
else if(WideMode == SDMMC_BUS_WIDE_1B)
{
- errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000);
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U);
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
@@ -2138,53 +2164,55 @@
/* WideMode is not a valid argument*/
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
}
-
+
/* Check for switch error and violation of the trial number of sending CMD 13 */
- while(busy == 0)
+ while(busy == 0U)
{
- if(count++ == SDMMC_MAX_TRIAL)
+ if(count == SDMMC_MAX_TRIAL)
{
hmmc->State = HAL_MMC_STATE_READY;
hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
return HAL_ERROR;
}
-
+ count++;
+
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
- errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16));
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
-
+
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
-
+
/* Get operating voltage*/
- busy = (((response >> 7) == 1) ? 0 : 1);
+ busy = (((response >> 7U) == 1U) ? 0U : 1U);
}
-
+
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
count = SDMMC_DATATIMEOUT;
- while((response & 0x00000100) == 0)
+ while((response & 0x00000100U) == 0U)
{
- if(count-- == 0)
+ if(count == 0U)
{
hmmc->State = HAL_MMC_STATE_READY;
hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
return HAL_ERROR;
}
-
+ count--;
+
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
- errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16));
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
-
+
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
}
-
+
if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
@@ -2201,55 +2229,54 @@
Init.BusWide = WideMode;
Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl;
Init.ClockDiv = hmmc->Init.ClockDiv;
- SDMMC_Init(hmmc->Instance, Init);
+ (void)SDMMC_Init(hmmc->Instance, Init);
}
/* Change State */
hmmc->State = HAL_MMC_STATE_READY;
-
+
return HAL_OK;
}
-
/**
* @brief Gets the current mmc card data state.
- * @param hmmc pointer to MMC handle
+ * @param hmmc: pointer to MMC handle
* @retval Card state
*/
HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc)
{
- HAL_MMC_CardStateTypeDef cardstate = HAL_MMC_CARD_TRANSFER;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
- uint32_t resp1 = 0;
-
+ uint32_t cardstate;
+ uint32_t errorstate;
+ uint32_t resp1 = 0U;
+
errorstate = MMC_SendStatus(hmmc, &resp1);
- if(errorstate != HAL_OK)
+ if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
- cardstate = (HAL_MMC_CardStateTypeDef)((resp1 >> 9) & 0x0F);
-
- return cardstate;
+ cardstate = ((resp1 >> 9U) & 0x0FU);
+
+ return (HAL_MMC_CardStateTypeDef)cardstate;
}
/**
* @brief Abort the current transfer and disable the MMC.
- * @param hmmc pointer to a MMC_HandleTypeDef structure that contains
+ * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
* the configuration information for MMC module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc)
{
HAL_MMC_CardStateTypeDef CardState;
-
+
/* DIsable All interrupts */
__HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
- SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
-
+ SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+
/* Clear All flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
-
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
if((hmmc->hdmatx != NULL) || (hmmc->hdmarx != NULL))
{
/* Disable the MMC DMA request */
@@ -2258,16 +2285,26 @@
/* Abort the MMC DMA Tx Stream */
if(hmmc->hdmatx != NULL)
{
- HAL_DMA_Abort(hmmc->hdmatx);
+ if(HAL_DMA_Abort(hmmc->hdmatx) != HAL_OK)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DMA;
+ }
}
/* Abort the MMC DMA Rx Stream */
if(hmmc->hdmarx != NULL)
{
- HAL_DMA_Abort(hmmc->hdmarx);
+ if(HAL_DMA_Abort(hmmc->hdmarx) != HAL_OK)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DMA;
+ }
}
}
-
+
hmmc->State = HAL_MMC_STATE_READY;
+
+ /* Initialize the MMC operation */
+ hmmc->Context = MMC_CONTEXT_NONE;
+
CardState = HAL_MMC_GetCardState(hmmc);
if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
{
@@ -2282,21 +2319,21 @@
/**
* @brief Abort the current transfer and disable the MMC (IT mode).
- * @param hmmc pointer to a MMC_HandleTypeDef structure that contains
+ * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
* the configuration information for MMC module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc)
{
HAL_MMC_CardStateTypeDef CardState;
-
+
/* DIsable All interrupts */
__HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
-
+
/* Clear All flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
-
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
if((hmmc->hdmatx != NULL) || (hmmc->hdmarx != NULL))
{
/* Disable the MMC DMA request */
@@ -2327,6 +2364,7 @@
{
CardState = HAL_MMC_GetCardState(hmmc);
hmmc->State = HAL_MMC_STATE_READY;
+
if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
{
hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
@@ -2337,29 +2375,33 @@
}
else
{
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ hmmc->AbortCpltCallback(hmmc);
+#else
HAL_MMC_AbortCallback(hmmc);
+#endif
}
}
-
+
return HAL_OK;
}
/**
* @}
*/
-
+
/**
* @}
*/
-
-/* Private function ----------------------------------------------------------*/
+
+/* Private function ----------------------------------------------------------*/
/** @addtogroup MMC_Private_Functions
* @{
*/
/**
* @brief DMA MMC transmit process complete callback
- * @param hdma DMA handle
+ * @param hdma: DMA handle
* @retval None
*/
static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma)
@@ -2372,13 +2414,13 @@
/**
* @brief DMA MMC receive process complete callback
- * @param hdma DMA handle
+ * @param hdma: DMA handle
* @retval None
*/
static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent);
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
+ uint32_t errorstate;
/* Send stop command in multiblock write */
if(hmmc->Context == (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA))
@@ -2387,7 +2429,7 @@
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->ErrorCallback(hmmc);
#else
HAL_MMC_ErrorCallback(hmmc);
@@ -2400,11 +2442,11 @@
hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN);
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
hmmc->State = HAL_MMC_STATE_READY;
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->RxCpltCallback(hmmc);
#else
HAL_MMC_RxCpltCallback(hmmc);
@@ -2413,18 +2455,21 @@
/**
* @brief DMA MMC communication error callback
- * @param hdma DMA handle
+ * @param hdma: DMA handle
* @retval None
*/
static void MMC_DMAError(DMA_HandleTypeDef *hdma)
{
MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent);
HAL_MMC_CardStateTypeDef CardState;
+ uint32_t RxErrorCode, TxErrorCode;
/* if DMA error is FIFO error ignore it */
if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
{
- if((hmmc->hdmarx->ErrorCode == HAL_DMA_ERROR_TE) || (hmmc->hdmatx->ErrorCode == HAL_DMA_ERROR_TE))
+ RxErrorCode = hmmc->hdmarx->ErrorCode;
+ TxErrorCode = hmmc->hdmatx->ErrorCode;
+ if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE))
{
/* Clear All flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -2443,18 +2488,17 @@
hmmc->State= HAL_MMC_STATE_READY;
}
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->ErrorCallback(hmmc);
#else
HAL_MMC_ErrorCallback(hmmc);
#endif
}
-
}
/**
* @brief DMA MMC Tx Abort callback
- * @param hdma DMA handle
+ * @param hdma: DMA handle
* @retval None
*/
static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma)
@@ -2479,11 +2523,15 @@
if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
{
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ hmmc->AbortCpltCallback(hmmc);
+#else
HAL_MMC_AbortCallback(hmmc);
+#endif
}
else
{
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->ErrorCallback(hmmc);
#else
HAL_MMC_ErrorCallback(hmmc);
@@ -2495,7 +2543,7 @@
/**
* @brief DMA MMC Rx Abort callback
- * @param hdma DMA handle
+ * @param hdma: DMA handle
* @retval None
*/
static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma)
@@ -2520,11 +2568,15 @@
if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
{
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ hmmc->AbortCpltCallback(hmmc);
+#else
HAL_MMC_AbortCallback(hmmc);
+#endif
}
else
{
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->ErrorCallback(hmmc);
#else
HAL_MMC_ErrorCallback(hmmc);
@@ -2534,25 +2586,24 @@
}
}
-
/**
* @brief Initializes the mmc card.
- * @param hmmc Pointer to MMC handle
+ * @param hmmc: Pointer to MMC handle
* @retval MMC Card error state
*/
static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc)
{
HAL_MMC_CardCSDTypeDef CSD;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
- uint16_t mmc_rca = 1;
-
+ uint32_t errorstate;
+ uint16_t mmc_rca = 1U;
+
/* Check the power State */
- if(SDMMC_GetPowerState(hmmc->Instance) == 0)
+ if(SDMMC_GetPowerState(hmmc->Instance) == 0U)
{
/* Power off */
return HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
}
-
+
/* Send CMD2 ALL_SEND_CID */
errorstate = SDMMC_CmdSendCID(hmmc->Instance);
if(errorstate != HAL_MMC_ERROR_NONE)
@@ -2562,12 +2613,12 @@
else
{
/* Get Card identification number data */
- hmmc->CID[0] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
- hmmc->CID[1] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2);
- hmmc->CID[2] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3);
- hmmc->CID[3] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4);
+ hmmc->CID[0U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+ hmmc->CID[1U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2);
+ hmmc->CID[2U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3);
+ hmmc->CID[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4);
}
-
+
/* Send CMD3 SET_REL_ADDR with argument 0 */
/* MMC Card publishes its RCA. */
errorstate = SDMMC_CmdSetRelAdd(hmmc->Instance, &mmc_rca);
@@ -2575,10 +2626,10 @@
{
return errorstate;
}
-
+
/* Get the MMC card RCA */
hmmc->MmcCard.RelCardAdd = mmc_rca;
-
+
/* Send CMD9 SEND_CSD with argument as card's RCA */
errorstate = SDMMC_CmdSendCSD(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U));
if(errorstate != HAL_MMC_ERROR_NONE)
@@ -2593,22 +2644,25 @@
hmmc->CSD[2U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3);
hmmc->CSD[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4);
}
-
+
/* Get the Card Class */
- hmmc->MmcCard.Class = (SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2) >> 20);
-
+ hmmc->MmcCard.Class = (SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2) >> 20U);
+
/* Get CSD parameters */
- HAL_MMC_GetCardCSD(hmmc, &CSD);
+ if (HAL_MMC_GetCardCSD(hmmc, &CSD) != HAL_OK)
+ {
+ return hmmc->ErrorCode;
+ }
/* Select the Card */
- errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16));
+ errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if(errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
}
- /* Configure SDMMC peripheral interface */
- SDMMC_Init(hmmc->Instance, hmmc->Init);
+ /* Configure SDMMC peripheral interface */
+ (void)SDMMC_Init(hmmc->Instance, hmmc->Init);
/* All cards are initialized */
return HAL_MMC_ERROR_NONE;
@@ -2618,152 +2672,180 @@
* @brief Enquires cards about their operating voltage and configures clock
* controls and stores MMC information that will be needed in future
* in the MMC handle.
- * @param hmmc Pointer to MMC handle
+ * @param hmmc: Pointer to MMC handle
* @retval error state
*/
static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc)
{
- __IO uint32_t count = 0;
- uint32_t response = 0, validvoltage = 0;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
-
+ __IO uint32_t count = 0U;
+ uint32_t response = 0U, validvoltage = 0U;
+ uint32_t errorstate;
+
/* CMD0: GO_IDLE_STATE */
errorstate = SDMMC_CmdGoIdleState(hmmc->Instance);
if(errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
}
-
- while(validvoltage == 0)
+
+ while(validvoltage == 0U)
{
if(count++ == SDMMC_MAX_VOLT_TRIAL)
{
return HAL_MMC_ERROR_INVALID_VOLTRANGE;
}
-
+
/* SEND CMD1 APP_CMD with MMC_HIGH_VOLTAGE_RANGE(0xC0FF8000) as argument */
errorstate = SDMMC_CmdOpCondition(hmmc->Instance, eMMC_HIGH_VOLTAGE_RANGE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
return HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
}
-
+
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
-
+
/* Get operating voltage*/
- validvoltage = (((response >> 31) == 1) ? 1 : 0);
+ validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
}
-
+
/* When power routine is finished and command returns valid voltage */
- if ((response & MMC_HIGH_VOLTAGE_RANGE) == MMC_HIGH_VOLTAGE_RANGE)
+ if (((response & (0xFF000000U)) >> 24U) == 0xC0U)
{
- /* When voltage range of the card is within 2.7V and 3.6V */
- hmmc->MmcCard.CardType = MMC_HIGH_VOLTAGE_CARD;
+ hmmc->MmcCard.CardType = MMC_HIGH_CAPACITY_CARD;
}
else
{
- /* When voltage range of the card is within 1.65V and 1.95V or 2.7V and 3.6V */
- hmmc->MmcCard.CardType = MMC_DUAL_VOLTAGE_CARD;
+ hmmc->MmcCard.CardType = MMC_LOW_CAPACITY_CARD;
}
-
+
return HAL_MMC_ERROR_NONE;
}
/**
* @brief Turns the SDMMC output signals off.
- * @param hmmc Pointer to MMC handle
- * @retval HAL status
+ * @param hmmc: Pointer to MMC handle
+ * @retval None
*/
-static HAL_StatusTypeDef MMC_PowerOFF(MMC_HandleTypeDef *hmmc)
+static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc)
{
/* Set Power State to OFF */
- SDMMC_PowerState_OFF(hmmc->Instance);
-
- return HAL_OK;
+ (void)SDMMC_PowerState_OFF(hmmc->Instance);
}
/**
* @brief Returns the current card's status.
- * @param hmmc Pointer to MMC handle
- * @param pCardStatus pointer to the buffer that will contain the MMC card
- * status (Card Status register)
+ * @param hmmc: Pointer to MMC handle
+ * @param pCardStatus: pointer to the buffer that will contain the MMC card
+ * status (Card Status register)
* @retval error state
*/
static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus)
{
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
-
+ uint32_t errorstate;
+
if(pCardStatus == NULL)
{
return HAL_MMC_ERROR_PARAM;
}
-
+
/* Send Status command */
- errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16));
- if(errorstate != HAL_OK)
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U));
+ if(errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
}
-
+
/* Get MMC card status */
*pCardStatus = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
-
+
return HAL_MMC_ERROR_NONE;
}
/**
* @brief Wrap up reading in non-blocking mode.
- * @param hmmc pointer to a MMC_HandleTypeDef structure that contains
+ * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
* the configuration information.
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef MMC_Read_IT(MMC_HandleTypeDef *hmmc)
+static void MMC_Read_IT(MMC_HandleTypeDef *hmmc)
{
- uint32_t count = 0;
- uint32_t* tmp;
+ uint32_t count, data, dataremaining;
+ uint8_t* tmp;
- tmp = (uint32_t*)hmmc->pRxBuffPtr;
-
- /* Read data from SDMMC Rx FIFO */
- for(count = 0; count < 8; count++)
+ tmp = hmmc->pRxBuffPtr;
+ dataremaining = hmmc->RxXferSize;
+
+ if (dataremaining > 0U)
{
- *(tmp + count) = SDMMC_ReadFIFO(hmmc->Instance);
+ /* Read data from SDMMC Rx FIFO */
+ for(count = 0U; count < 8U; count++)
+ {
+ data = SDMMC_ReadFIFO(hmmc->Instance);
+ *tmp = (uint8_t)(data & 0xFFU);
+ tmp++;
+ dataremaining--;
+ *tmp = (uint8_t)((data >> 8U) & 0xFFU);
+ tmp++;
+ dataremaining--;
+ *tmp = (uint8_t)((data >> 16U) & 0xFFU);
+ tmp++;
+ dataremaining--;
+ *tmp = (uint8_t)((data >> 24U) & 0xFFU);
+ tmp++;
+ dataremaining--;
+ }
+
+ hmmc->pRxBuffPtr = tmp;
+ hmmc->RxXferSize = dataremaining;
}
-
- hmmc->pRxBuffPtr += 8;
-
- return HAL_OK;
}
/**
* @brief Wrap up writing in non-blocking mode.
- * @param hmmc pointer to a MMC_HandleTypeDef structure that contains
+ * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
* the configuration information.
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef MMC_Write_IT(MMC_HandleTypeDef *hmmc)
+static void MMC_Write_IT(MMC_HandleTypeDef *hmmc)
{
- uint32_t count = 0;
- uint32_t* tmp;
-
- tmp = (uint32_t*)hmmc->pTxBuffPtr;
-
- /* Write data to SDMMC Tx FIFO */
- for(count = 0; count < 8; count++)
+ uint32_t count, data, dataremaining;
+ uint8_t* tmp;
+
+ tmp = hmmc->pTxBuffPtr;
+ dataremaining = hmmc->TxXferSize;
+
+ if (dataremaining > 0U)
{
- SDMMC_WriteFIFO(hmmc->Instance, (tmp + count));
+ /* Write data to SDMMC Tx FIFO */
+ for(count = 0U; count < 8U; count++)
+ {
+ data = (uint32_t)(*tmp);
+ tmp++;
+ dataremaining--;
+ data |= ((uint32_t)(*tmp) << 8U);
+ tmp++;
+ dataremaining--;
+ data |= ((uint32_t)(*tmp) << 16U);
+ tmp++;
+ dataremaining--;
+ data |= ((uint32_t)(*tmp) << 24U);
+ tmp++;
+ dataremaining--;
+ (void)SDMMC_WriteFIFO(hmmc->Instance, &data);
+ }
+
+ hmmc->pTxBuffPtr = tmp;
+ hmmc->TxXferSize = dataremaining;
}
-
- hmmc->pTxBuffPtr += 8;
-
- return HAL_OK;
}
/**
* @}
*/
+#endif /* SDMMC1 */
+
#endif /* HAL_MMC_MODULE_ENABLED */
/**
diff --git a/Src/stm32f7xx_hal_pcd.c b/Src/stm32f7xx_hal_pcd.c
index 5284b79..6ce4edd 100644
--- a/Src/stm32f7xx_hal_pcd.c
+++ b/Src/stm32f7xx_hal_pcd.c
@@ -122,6 +122,7 @@
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
+ USB_OTG_GlobalTypeDef *USBx;
uint8_t i;
/* Check the PCD handle allocation */
@@ -133,6 +134,8 @@
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
+ USBx = hpcd->Instance;
+
if (hpcd->State == HAL_PCD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@@ -166,6 +169,12 @@
hpcd->State = HAL_PCD_STATE_BUSY;
+ /* Disable DMA mode for FS instance */
+ if ((USBx->CID & (0x1U << 8)) == 0U)
+ {
+ hpcd->Init.dma_enable = 0U;
+ }
+
/* Disable the Interrupts */
__HAL_PCD_DISABLE(hpcd);
@@ -943,7 +952,7 @@
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t i, ep_intr, epint, epnum = 0U;
+ uint32_t i, ep_intr, epint, epnum;
uint32_t fifoemptymsk, temp;
USB_OTG_EPTypeDef *ep;
@@ -962,6 +971,38 @@
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
}
+ /* Handle RxQLevel Interrupt */
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
+ {
+ USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+
+ temp = USBx->GRXSTSP;
+
+ ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
+
+ if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
+ {
+ if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
+ {
+ (void)USB_ReadPacket(USBx, ep->xfer_buff,
+ (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4));
+
+ ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+ ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+ }
+ }
+ else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
+ {
+ (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
+ ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+ }
+ else
+ {
+ /* ... */
+ }
+ USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+ }
+
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
{
epnum = 0U;
@@ -983,9 +1024,9 @@
if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
{
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
/* Class B setup phase done for previous decoded setup */
(void)PCD_EP_OutSetupPacket_int(hpcd, epnum);
- CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
}
if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
@@ -996,10 +1037,6 @@
/* Clear Status Phase Received interrupt */
if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
{
- if (hpcd->Init.dma_enable == 1U)
- {
- (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
- }
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
}
@@ -1037,16 +1074,7 @@
if (hpcd->Init.dma_enable == 1U)
{
hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;
- }
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);
-#else
- HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
- if (hpcd->Init.dma_enable == 1U)
- {
/* this is ZLP, so prepare EP0 for next setup */
if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U))
{
@@ -1054,6 +1082,12 @@
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
}
}
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);
+#else
+ HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
{
@@ -1159,8 +1193,10 @@
{
USBx_INEP(i)->DIEPINT = 0xFB7FU;
USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
+ USBx_INEP(i)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
+ USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
}
USBx_DEVICE->DAINTMSK |= 0x10001U;
@@ -1201,15 +1237,7 @@
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
{
(void)USB_ActivateSetup(hpcd->Instance);
-
- if (USB_GetDevSpeed(hpcd->Instance) == USB_OTG_SPEED_HIGH)
- {
- hpcd->Init.speed = USB_OTG_SPEED_HIGH;
- }
- else
- {
- hpcd->Init.speed = USB_OTG_SPEED_FULL;
- }
+ hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance);
/* Set USB Turnaround time */
(void)USB_SetTurnaroundTime(hpcd->Instance,
@@ -1225,38 +1253,6 @@
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
}
- /* Handle RxQLevel Interrupt */
- if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
- {
- USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
-
- temp = USBx->GRXSTSP;
-
- ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
-
- if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
- {
- if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
- {
- (void)USB_ReadPacket(USBx, ep->xfer_buff,
- (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4));
-
- ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
- ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
- }
- }
- else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
- {
- (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
- ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
- }
- else
- {
- /* ... */
- }
- USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
- }
-
/* Handle SOF Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
{
@@ -1272,6 +1268,10 @@
/* Handle Incomplete ISO IN Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
{
+ /* Keep application checking the corresponding Iso IN endpoint
+ causing the incomplete Interrupt */
+ epnum = 0U;
+
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
#else
@@ -1284,6 +1284,10 @@
/* Handle Incomplete ISO OUT Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
{
+ /* Keep application checking the corresponding Iso OUT endpoint
+ causing the incomplete Interrupt */
+ epnum = 0U;
+
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
#else
@@ -1963,16 +1967,6 @@
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
}
-
- /* Inform the upper layer that a setup packet is available */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->SetupStageCallback(hpcd);
-#else
- HAL_PCD_SetupStageCallback(hpcd);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
- (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
- CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
}
else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */
{
@@ -1995,17 +1989,16 @@
hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
-#else
- HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
{
/* this is ZLP, so prepare EP0 for next setup */
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
}
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
+#else
+ HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
else
@@ -2038,6 +2031,12 @@
}
else
{
+ if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
+ {
+ /* this is ZLP, so prepare EP0 for next setup */
+ (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup);
+ }
+
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
#else
@@ -2063,22 +2062,10 @@
uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
- if (hpcd->Init.dma_enable == 1U)
+ if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
+ ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
{
- /* StupPktRcvd = 1 pending setup packet int */
- if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
- ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
- {
- CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
- }
- }
- else
- {
- if ((gSNPSiD == USB_OTG_CORE_ID_310A) &&
- ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
- {
- CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
- }
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
}
/* Inform the upper layer that a setup packet is available */
diff --git a/Src/stm32f7xx_hal_qspi.c b/Src/stm32f7xx_hal_qspi.c
index d95528f..be14334 100644
--- a/Src/stm32f7xx_hal_qspi.c
+++ b/Src/stm32f7xx_hal_qspi.c
@@ -3,7 +3,7 @@
* @file stm32f7xx_hal_qspi.c
* @author MCD Application Team
* @brief QSPI HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the QuadSPI interface (QSPI).
* + Initialization and de-initialization functions
* + Indirect functional mode management
@@ -24,14 +24,14 @@
[..]
(#) As prerequisite, fill in the HAL_QSPI_MspInit() :
(++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
- (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
+ (++) Reset QuadSPI Peripheral with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
(++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
(++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
(++) If interrupt mode is used, enable and configure QuadSPI global
interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
- (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
- with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
- link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
+ (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
+ with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
+ link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
(#) Configure the flash size, the clock prescaler, the fifo threshold, the
clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
@@ -39,47 +39,47 @@
*** Indirect functional mode ***
================================
[..]
- (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
+ (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
functions :
(++) Instruction phase : the mode used and if present the instruction opcode.
(++) Address phase : the mode used and if present the size and the address value.
- (++) Alternate-bytes phase : the mode used and if present the size and the alternate
+ (++) Alternate-bytes phase : the mode used and if present the size and the alternate
bytes values.
(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
(++) Data phase : the mode used and if present the number of bytes.
- (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
+ (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
if activated.
(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
(#) If no data is required for the command, it is sent directly to the memory :
(++) In polling mode, the output of the function is done when the transfer is complete.
(++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
- (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
+ (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
HAL_QSPI_Transmit_IT() after the command configuration :
(++) In polling mode, the output of the function is done when the transfer is complete.
- (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
+ (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
- (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
+ (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
- (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
+ (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
HAL_QSPI_Receive_IT() after the command configuration :
(++) In polling mode, the output of the function is done when the transfer is complete.
- (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
+ (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
- (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
+ (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
*** Auto-polling functional mode ***
====================================
[..]
- (#) Configure the command sequence and the auto-polling functional mode using the
+ (#) Configure the command sequence and the auto-polling functional mode using the
HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
(++) Instruction phase : the mode used and if present the instruction opcode.
(++) Address phase : the mode used and if present the size and the address value.
- (++) Alternate-bytes phase : the mode used and if present the size and the alternate
+ (++) Alternate-bytes phase : the mode used and if present the size and the alternate
bytes values.
(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
(++) Data phase : the mode used.
- (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
+ (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
if activated.
(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
(++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
@@ -92,31 +92,31 @@
*** Memory-mapped functional mode ***
=====================================
[..]
- (#) Configure the command sequence and the memory-mapped functional mode using the
+ (#) Configure the command sequence and the memory-mapped functional mode using the
HAL_QSPI_MemoryMapped() functions :
(++) Instruction phase : the mode used and if present the instruction opcode.
(++) Address phase : the mode used and the size.
- (++) Alternate-bytes phase : the mode used and if present the size and the alternate
+ (++) Alternate-bytes phase : the mode used and if present the size and the alternate
bytes values.
(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
(++) Data phase : the mode used.
- (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
+ (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
if activated.
(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
(++) The timeout activation and the timeout period.
- (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
+ (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
*** Errors management and abort functionality ***
- ==================================================
+ =================================================
[..]
(#) HAL_QSPI_GetError() function gives the error raised during the last operation.
- (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
+ (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
flushes the fifo :
- (++) In polling mode, the output of the function is done when the transfer
+ (++) In polling mode, the output of the function is done when the transfer
complete bit is set and the busy bit cleared.
- (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
- the transfer complete bi is set.
+ (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
+ the transfer complete bit is set.
*** Control functions ***
=========================
@@ -125,6 +125,7 @@
(#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
(#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
(#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
+ (#) HAL_QSPI_SetFlashID() function configures the index of the flash memory to be accessed.
*** Callback registration ***
=============================================
@@ -195,13 +196,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
+ * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -209,31 +210,34 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
+#if defined(QUADSPI)
+
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @defgroup QSPI QSPI
- * @brief HAL QSPI module driver
+ * @brief QSPI HAL module driver
* @{
*/
#ifdef HAL_QSPI_MODULE_ENABLED
-
+
/* Private typedef -----------------------------------------------------------*/
+
/* Private define ------------------------------------------------------------*/
-/** @addtogroup QSPI_Private_Constants
+/** @defgroup QSPI_Private_Constants QSPI Private Constants
* @{
*/
-#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000U) /*!<Indirect write mode*/
+#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE 0x00000000U /*!<Indirect write mode*/
#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE) /*!<Memory-mapped mode*/
/**
* @}
*/
-
+
/* Private macro -------------------------------------------------------------*/
-/** @addtogroup QSPI_Private_Macros QSPI Private Macros
+/** @defgroup QSPI_Private_Macros QSPI Private Macros
* @{
*/
#define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
@@ -243,34 +247,29 @@
/**
* @}
*/
-
+
/* Private variables ---------------------------------------------------------*/
+
/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup QSPI_Private_Functions QSPI Private Functions
- * @{
- */
static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
+static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t tickstart, uint32_t Timeout);
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout);
static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
/** @defgroup QSPI_Exported_Functions QSPI Exported Functions
* @{
*/
-/** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions
+/** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
@@ -278,22 +277,22 @@
This subsection provides a set of functions allowing to :
(+) Initialize the QuadSPI.
(+) De-initialize the QuadSPI.
-
+
@endverbatim
* @{
*/
/**
- * @brief Initializes the QSPI mode according to the specified parameters
- * in the QSPI_InitTypeDef and creates the associated handle.
- * @param hqspi qspi handle
+ * @brief Initialize the QSPI mode according to the specified parameters
+ * in the QSPI_InitTypeDef and initialize the associated handle.
+ * @param hqspi : QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
{
- HAL_StatusTypeDef status = HAL_ERROR;
+ HAL_StatusTypeDef status;
uint32_t tickstart = HAL_GetTick();
-
+
/* Check the QSPI handle allocation */
if(hqspi == NULL)
{
@@ -314,12 +313,9 @@
{
assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
}
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
+
if(hqspi->State == HAL_QSPI_STATE_RESET)
- {
+ {
/* Allocate lock resource and initialize it */
hqspi->Lock = HAL_UNLOCKED;
@@ -349,35 +345,38 @@
#endif
/* Configure the default timeout for the QSPI memory access */
- HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
+ HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE);
}
-
+
/* Configure QSPI FIFO Threshold */
- MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1) << 8));
+ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
+ ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
/* Wait till BUSY flag reset */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
if(status == HAL_OK)
{
-
/* Configure QSPI Clock Prescaler and Sample Shift */
- MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24)| hqspi->Init.SampleShifting | hqspi->Init.FlashID| hqspi->Init.DualFlash ));
-
+ MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM),
+ ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) |
+ hqspi->Init.SampleShifting | hqspi->Init.FlashID | hqspi->Init.DualFlash));
+
/* Configure QSPI Flash Size, CS High Time and Clock Mode */
- MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
- ((hqspi->Init.FlashSize << 16) | hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
-
+ MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
+ ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) |
+ hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
+
/* Enable the QSPI peripheral */
__HAL_QSPI_ENABLE(hqspi);
-
+
/* Set QSPI error code to none */
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
/* Initialize the QSPI state */
hqspi->State = HAL_QSPI_STATE_READY;
}
-
+
/* Release Lock */
__HAL_UNLOCK(hqspi);
@@ -386,8 +385,8 @@
}
/**
- * @brief DeInitializes the QSPI peripheral
- * @param hqspi qspi handle
+ * @brief De-Initialize the QSPI peripheral.
+ * @param hqspi : QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
@@ -398,9 +397,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hqspi);
-
/* Disable the QSPI Peripheral Clock */
__HAL_QSPI_DISABLE(hqspi);
@@ -430,47 +426,47 @@
}
/**
- * @brief QSPI MSP Init
- * @param hqspi QSPI handle
+ * @brief Initialize the QSPI MSP.
+ * @param hqspi : QSPI handle
* @retval None
*/
- __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
+__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_QSPI_MspInit can be implemented in the user file
- */
+ */
}
/**
- * @brief QSPI MSP DeInit
- * @param hqspi QSPI handle
+ * @brief DeInitialize the QSPI MSP.
+ * @param hqspi : QSPI handle
* @retval None
*/
- __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
+__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_QSPI_MspDeInit can be implemented in the user file
- */
+ */
}
/**
* @}
*/
-/** @defgroup QSPI_Exported_Functions_Group2 IO operation functions
- * @brief QSPI Transmit/Receive functions
+/** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions
+ * @brief QSPI Transmit/Receive functions
*
-@verbatim
+@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
- [..]
+ [..]
This subsection provides a set of functions allowing to :
(+) Handle the interrupts.
(+) Handle the command sequence.
@@ -484,9 +480,9 @@
*/
/**
- * @brief This function handles QSPI interrupt request.
- * @param hqspi QSPI handle
- * @retval None.
+ * @brief Handle QSPI interrupt request.
+ * @param hqspi : QSPI handle
+ * @retval None
*/
void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
{
@@ -495,19 +491,20 @@
uint32_t itsource = READ_REG(hqspi->Instance->CR);
/* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
- if(((flag & QSPI_FLAG_FT)!= RESET) && ((itsource & QSPI_IT_FT)!= RESET))
+ if(((flag & QSPI_FLAG_FT) != 0U) && ((itsource & QSPI_IT_FT) != 0U))
{
data_reg = &hqspi->Instance->DR;
if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
{
/* Transmission process */
- while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
+ while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
{
- if (hqspi->TxXferCount > 0)
+ if (hqspi->TxXferCount > 0U)
{
- /* Fill the FIFO until it is full */
- *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
+ /* Fill the FIFO until the threshold is reached */
+ *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;
+ hqspi->pTxBuffPtr++;
hqspi->TxXferCount--;
}
else
@@ -522,12 +519,13 @@
else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
{
/* Receiving Process */
- while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
+ while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
{
- if (hqspi->RxXferCount > 0)
+ if (hqspi->RxXferCount > 0U)
{
- /* Read the FIFO until it is empty */
- *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
+ /* Read the FIFO until the threshold is reached */
+ *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
+ hqspi->pRxBuffPtr++;
hqspi->RxXferCount--;
}
else
@@ -539,7 +537,11 @@
}
}
}
-
+ else
+ {
+ /* Nothing to do */
+ }
+
/* FIFO Threshold callback */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
hqspi->FifoThresholdCallback(hqspi);
@@ -549,31 +551,31 @@
}
/* QSPI Transfer Complete interrupt occurred -------------------------------*/
- else if(((flag & QSPI_FLAG_TC)!= RESET) && ((itsource & QSPI_IT_TC)!= RESET))
+ else if(((flag & QSPI_FLAG_TC) != 0U) && ((itsource & QSPI_IT_TC) != 0U))
{
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
/* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
-
+
/* Transfer complete callback */
if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
{
- if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
+
/* Disable the DMA channel */
__HAL_DMA_DISABLE(hqspi->hdma);
}
-#if defined(QSPI1_V1_0)
-/* Clear Busy bit */
+#if defined(QSPI1_V1_0)
+ /* Clear Busy bit */
HAL_QSPI_Abort_IT(hqspi);
#endif
-
+
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
@@ -586,23 +588,24 @@
}
else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
{
- if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
+
/* Disable the DMA channel */
__HAL_DMA_DISABLE(hqspi->hdma);
}
else
{
data_reg = &hqspi->Instance->DR;
- while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0)
+ while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U)
{
- if (hqspi->RxXferCount > 0)
+ if (hqspi->RxXferCount > 0U)
{
/* Read the last data received in the FIFO until it is empty */
- *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
+ *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
+ hqspi->pRxBuffPtr++;
hqspi->RxXferCount--;
}
else
@@ -612,11 +615,12 @@
}
}
}
-#if defined(QSPI1_V1_0)
+
+#if defined(QSPI1_V1_0)
/* Workaround - Extra data written in the FIFO at the end of a read transfer */
HAL_QSPI_Abort_IT(hqspi);
-#endif /* QSPI_V1_0*/
-
+#endif
+
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
@@ -641,6 +645,9 @@
}
else if(hqspi->State == HAL_QSPI_STATE_ABORT)
{
+ /* Reset functional mode configuration to indirect write mode by default */
+ CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
+
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
@@ -655,7 +662,7 @@
HAL_QSPI_AbortCpltCallback(hqspi);
#endif
}
- else
+ else
{
/* Abort due to an error (eg : DMA error) */
@@ -667,16 +674,20 @@
#endif
}
}
+ else
+ {
+ /* Nothing to do */
+ }
}
/* QSPI Status Match interrupt occurred ------------------------------------*/
- else if(((flag & QSPI_FLAG_SM)!= RESET) && ((itsource & QSPI_IT_SM)!= RESET))
+ else if(((flag & QSPI_FLAG_SM) != 0U) && ((itsource & QSPI_IT_SM) != 0U))
{
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
-
+
/* Check if the automatic poll mode stop is activated */
- if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0)
+ if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U)
{
/* Disable the QSPI Transfer Error and Status Match Interrupts */
__HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
@@ -694,22 +705,22 @@
}
/* QSPI Transfer Error interrupt occurred ----------------------------------*/
- else if(((flag & QSPI_FLAG_TE)!= RESET) && ((itsource & QSPI_IT_TE)!= RESET))
+ else if(((flag & QSPI_FLAG_TE) != 0U) && ((itsource & QSPI_IT_TE) != 0U))
{
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
-
+
/* Disable all the QSPI Interrupts */
__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
/* Set error code */
hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
-
- if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
+
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
+
/* Disable the DMA channel */
hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK)
@@ -732,7 +743,7 @@
{
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
-
+
/* Error callback */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
hqspi->ErrorCallback(hqspi);
@@ -743,33 +754,38 @@
}
/* QSPI Timeout interrupt occurred -----------------------------------------*/
- else if(((flag & QSPI_FLAG_TO)!= RESET) && ((itsource & QSPI_IT_TO)!= RESET))
+ else if(((flag & QSPI_FLAG_TO) != 0U) && ((itsource & QSPI_IT_TO) != 0U))
{
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
-
- /* Time out callback */
+
+ /* Timeout callback */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
hqspi->TimeOutCallback(hqspi);
#else
HAL_QSPI_TimeOutCallback(hqspi);
#endif
}
+
+ else
+ {
+ /* Nothing to do */
+ }
}
/**
- * @brief Sets the command configuration.
- * @param hqspi QSPI handle
- * @param cmd structure that contains the command configuration information
- * @param Timeout Time out duration
+ * @brief Set the command configuration.
+ * @param hqspi : QSPI handle
+ * @param cmd : structure that contains the command configuration information
+ * @param Timeout : Timeout duration
* @note This function is used only in Indirect Read or Write Modes
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
{
- HAL_StatusTypeDef status = HAL_ERROR;
+ HAL_StatusTypeDef status;
uint32_t tickstart = HAL_GetTick();
-
+
/* Check the parameters */
assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
@@ -795,52 +811,51 @@
assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
+
/* Process locked */
__HAL_LOCK(hqspi);
if(hqspi->State == HAL_QSPI_STATE_READY)
{
hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
+
/* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_BUSY;
-
+ hqspi->State = HAL_QSPI_STATE_BUSY;
+
/* Wait till BUSY flag reset */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
-
+
if (status == HAL_OK)
{
/* Call the configuration function */
QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
-
+
if (cmd->DataMode == QSPI_DATA_NONE)
{
- /* When there is no data phase, the transfer start as soon as the configuration is done
+ /* When there is no data phase, the transfer start as soon as the configuration is done
so wait until TC flag is set to go back in idle state */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
if (status == HAL_OK)
{
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
+
/* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_READY;
+ hqspi->State = HAL_QSPI_STATE_READY;
}
-
}
else
{
/* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_READY;
+ hqspi->State = HAL_QSPI_STATE_READY;
}
}
}
else
{
- status = HAL_BUSY;
+ status = HAL_BUSY;
}
-
+
/* Process unlocked */
__HAL_UNLOCK(hqspi);
@@ -849,17 +864,17 @@
}
/**
- * @brief Sets the command configuration in interrupt mode.
- * @param hqspi QSPI handle
- * @param cmd structure that contains the command configuration information
+ * @brief Set the command configuration in interrupt mode.
+ * @param hqspi : QSPI handle
+ * @param cmd : structure that contains the command configuration information
* @note This function is used only in Indirect Read or Write Modes
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
{
- HAL_StatusTypeDef status = HAL_ERROR;
+ HAL_StatusTypeDef status;
uint32_t tickstart = HAL_GetTick();
-
+
/* Check the parameters */
assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
@@ -885,20 +900,20 @@
assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
+
/* Process locked */
__HAL_LOCK(hqspi);
if(hqspi->State == HAL_QSPI_STATE_READY)
{
hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
+
/* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_BUSY;
-
+ hqspi->State = HAL_QSPI_STATE_BUSY;
+
/* Wait till BUSY flag reset */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
-
+
if (status == HAL_OK)
{
if (cmd->DataMode == QSPI_DATA_NONE)
@@ -906,13 +921,13 @@
/* Clear interrupt */
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
}
-
+
/* Call the configuration function */
QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
-
+
if (cmd->DataMode == QSPI_DATA_NONE)
{
- /* When there is no data phase, the transfer start as soon as the configuration is done
+ /* When there is no data phase, the transfer start as soon as the configuration is done
so activate TC and TE interrupts */
/* Process unlocked */
__HAL_UNLOCK(hqspi);
@@ -923,7 +938,7 @@
else
{
/* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_READY;
+ hqspi->State = HAL_QSPI_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hqspi);
@@ -937,27 +952,27 @@
}
else
{
- status = HAL_BUSY;
+ status = HAL_BUSY;
/* Process unlocked */
__HAL_UNLOCK(hqspi);
}
-
+
/* Return function status */
return status;
}
/**
- * @brief Transmit an amount of data in blocking mode.
- * @param hqspi QSPI handle
- * @param pData pointer to data buffer
- * @param Timeout Time out duration
+ * @brief Transmit an amount of data in blocking mode.
+ * @param hqspi : QSPI handle
+ * @param pData : pointer to data buffer
+ * @param Timeout : Timeout duration
* @note This function is used only in Indirect Write Mode
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
{
- HAL_StatusTypeDef status = HAL_OK;
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tickstart = HAL_GetTick();
__IO uint32_t *data_reg = &hqspi->Instance->DR;
@@ -972,29 +987,30 @@
{
/* Update state */
hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
-
+
/* Configure counters and size of the handle */
- hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
- hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
+ hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
+ hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
hqspi->pTxBuffPtr = pData;
-
+
/* Configure QSPI: CCR register with functional as indirect write */
MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
- while(hqspi->TxXferCount > 0)
+ while(hqspi->TxXferCount > 0U)
{
/* Wait until FT flag is set to send data */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);
if (status != HAL_OK)
- {
+ {
break;
}
- *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
+ *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;
+ hqspi->pTxBuffPtr++;
hqspi->TxXferCount--;
}
-
+
if (status == HAL_OK)
{
/* Wait until TC flag is set to go back in idle state */
@@ -1004,16 +1020,16 @@
{
/* Clear Transfer Complete bit */
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
-#if defined(QSPI1_V1_0)
+
+#if defined(QSPI1_V1_0)
/* Clear Busy bit */
status = HAL_QSPI_Abort(hqspi);
-#endif /* QSPI_V1_0 */
+#endif
}
}
-
+
/* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_READY;
+ hqspi->State = HAL_QSPI_STATE_READY;
}
else
{
@@ -1034,10 +1050,10 @@
/**
- * @brief Receive an amount of data in blocking mode
- * @param hqspi QSPI handle
- * @param pData pointer to data buffer
- * @param Timeout Time out duration
+ * @brief Receive an amount of data in blocking mode.
+ * @param hqspi : QSPI handle
+ * @param pData : pointer to data buffer
+ * @param Timeout : Timeout duration
* @note This function is used only in Indirect Read Mode
* @retval HAL status
*/
@@ -1050,18 +1066,19 @@
/* Process locked */
__HAL_LOCK(hqspi);
-
+
if(hqspi->State == HAL_QSPI_STATE_READY)
{
hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
if(pData != NULL )
{
/* Update state */
hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
-
+
/* Configure counters and size of the handle */
- hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
- hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
+ hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
+ hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
hqspi->pRxBuffPtr = pData;
/* Configure QSPI: CCR register with functional as indirect read */
@@ -1069,21 +1086,22 @@
/* Start the transfer by re-writing the address in AR register */
WRITE_REG(hqspi->Instance->AR, addr_reg);
-
- while(hqspi->RxXferCount > 0)
+
+ while(hqspi->RxXferCount > 0U)
{
/* Wait until FT or TC flag is set to read received data */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout);
if (status != HAL_OK)
- {
+ {
break;
}
- *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
+ *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
+ hqspi->pRxBuffPtr++;
hqspi->RxXferCount--;
}
-
+
if (status == HAL_OK)
{
/* Wait until TC flag is set to go back in idle state */
@@ -1093,16 +1111,16 @@
{
/* Clear Transfer Complete bit */
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
-#if defined(QSPI1_V1_0)
- /* Workaround - Extra data written in the FIFO at the end of a read transfer */
- status = HAL_QSPI_Abort(hqspi);
-#endif /* QSPI_V1_0 */
+
+#if defined(QSPI1_V1_0)
+ /* Workaround - Extra data written in the FIFO at the end of a read transfer */
+ status = HAL_QSPI_Abort(hqspi);
+#endif
}
}
/* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_READY;
+ hqspi->State = HAL_QSPI_STATE_READY;
}
else
{
@@ -1114,7 +1132,7 @@
{
status = HAL_BUSY;
}
-
+
/* Process unlocked */
__HAL_UNLOCK(hqspi);
@@ -1122,44 +1140,44 @@
}
/**
- * @brief Send an amount of data in interrupt mode
- * @param hqspi QSPI handle
- * @param pData pointer to data buffer
+ * @brief Send an amount of data in non-blocking mode with interrupt.
+ * @param hqspi : QSPI handle
+ * @param pData : pointer to data buffer
* @note This function is used only in Indirect Write Mode
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
-{
+{
HAL_StatusTypeDef status = HAL_OK;
-
+
/* Process locked */
__HAL_LOCK(hqspi);
if(hqspi->State == HAL_QSPI_STATE_READY)
{
hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
if(pData != NULL )
{
/* Update state */
hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
/* Configure counters and size of the handle */
- hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
- hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
+ hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
+ hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
hqspi->pTxBuffPtr = pData;
-
- /* Configure QSPI: CCR register with functional as indirect write */
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
-
+
/* Clear interrupt */
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
+ /* Configure QSPI: CCR register with functional as indirect write */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
/* Process unlocked */
__HAL_UNLOCK(hqspi);
-
+
/* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
-
}
else
{
@@ -1182,9 +1200,9 @@
}
/**
- * @brief Receive an amount of data in no-blocking mode with Interrupt
- * @param hqspi QSPI handle
- * @param pData pointer to data buffer
+ * @brief Receive an amount of data in non-blocking mode with interrupt.
+ * @param hqspi : QSPI handle
+ * @param pData : pointer to data buffer
* @note This function is used only in Indirect Read Mode
* @retval HAL status
*/
@@ -1192,33 +1210,33 @@
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
-
+
/* Process locked */
__HAL_LOCK(hqspi);
if(hqspi->State == HAL_QSPI_STATE_READY)
{
hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
+
if(pData != NULL )
{
/* Update state */
hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
-
+
/* Configure counters and size of the handle */
- hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
- hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
+ hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
+ hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
hqspi->pRxBuffPtr = pData;
+ /* Clear interrupt */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
+
/* Configure QSPI: CCR register with functional as indirect read */
MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
/* Start the transfer by re-writing the address in AR register */
WRITE_REG(hqspi->Instance->AR, addr_reg);
- /* Clear interrupt */
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
-
/* Process unlocked */
__HAL_UNLOCK(hqspi);
@@ -1236,7 +1254,7 @@
}
else
{
- status = HAL_BUSY;
+ status = HAL_BUSY;
/* Process unlocked */
__HAL_UNLOCK(hqspi);
@@ -1246,31 +1264,30 @@
}
/**
- * @brief Sends an amount of data in non blocking mode with DMA.
- * @param hqspi QSPI handle
- * @param pData pointer to data buffer
+ * @brief Send an amount of data in non-blocking mode with DMA.
+ * @param hqspi : QSPI handle
+ * @param pData : pointer to data buffer
* @note This function is used only in Indirect Write Mode
- * @note If DMA peripheral access is configured as halfword, the number
+ * @note If DMA peripheral access is configured as halfword, the number
* of data and the fifo threshold should be aligned on halfword
- * @note If DMA peripheral access is configured as word, the number
+ * @note If DMA peripheral access is configured as word, the number
* of data and the fifo threshold should be aligned on word
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
{
HAL_StatusTypeDef status = HAL_OK;
- uint32_t *tmp;
- uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1);
-
+ uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
+
/* Process locked */
__HAL_LOCK(hqspi);
-
+
if(hqspi->State == HAL_QSPI_STATE_READY)
{
- /* Clear the error code */
+ /* Clear the error code */
hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
- if(pData != NULL )
+
+ if(pData != NULL )
{
/* Configure counters of the handle */
if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
@@ -1279,89 +1296,100 @@
}
else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
{
- if (((data_size % 2) != 0) || ((hqspi->Init.FifoThreshold % 2) != 0))
+ if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U))
{
- /* The number of data or the fifo threshold is not aligned on halfword
+ /* The number of data or the fifo threshold is not aligned on halfword
=> no transfer possible with DMA peripheral access configured as halfword */
hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
status = HAL_ERROR;
-
+
/* Process unlocked */
__HAL_UNLOCK(hqspi);
}
else
{
- hqspi->TxXferCount = (data_size >> 1);
+ hqspi->TxXferCount = (data_size >> 1U);
}
}
else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
{
- if (((data_size % 4) != 0) || ((hqspi->Init.FifoThreshold % 4) != 0))
+ if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U))
{
- /* The number of data or the fifo threshold is not aligned on word
+ /* The number of data or the fifo threshold is not aligned on word
=> no transfer possible with DMA peripheral access configured as word */
hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
status = HAL_ERROR;
-
+
/* Process unlocked */
__HAL_UNLOCK(hqspi);
}
else
{
- hqspi->TxXferCount = (data_size >> 2);
+ hqspi->TxXferCount = (data_size >> 2U);
}
}
-
+ else
+ {
+ /* Nothing to do */
+ }
+
if (status == HAL_OK)
{
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
- /* Update state */
- hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
+ /* Clear interrupt */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
- /* Clear interrupt */
- __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
+ /* Configure size and pointer of the handle */
+ hqspi->TxXferSize = hqspi->TxXferCount;
+ hqspi->pTxBuffPtr = pData;
- /* Configure size and pointer of the handle */
- hqspi->TxXferSize = hqspi->TxXferCount;
- hqspi->pTxBuffPtr = pData;
-
- /* Configure QSPI: CCR register with functional mode as indirect write */
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
-
- /* Set the QSPI DMA transfer complete callback */
- hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
-
- /* Set the QSPI DMA Half transfer complete callback */
- hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
-
- /* Set the DMA error callback */
- hqspi->hdma->XferErrorCallback = QSPI_DMAError;
-
- /* Clear the DMA abort callback */
- hqspi->hdma->XferAbortCallback = NULL;
+ /* Configure QSPI: CCR register with functional mode as indirect write */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
- /* Configure the direction of the DMA */
- hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
- MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
+ /* Set the QSPI DMA transfer complete callback */
+ hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
- /* Enable the QSPI transmit DMA Channel */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);
+ /* Set the QSPI DMA Half transfer complete callback */
+ hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
+ /* Set the DMA error callback */
+ hqspi->hdma->XferErrorCallback = QSPI_DMAError;
- /* Enable the QSPI transfer error Interrupt */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
+ /* Clear the DMA abort callback */
+ hqspi->hdma->XferAbortCallback = NULL;
- /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
- SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
- }
+ /* Configure the direction of the DMA */
+ hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
+ MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
+
+ /* Enable the QSPI transmit DMA Channel */
+ if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize) == HAL_OK)
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Enable the QSPI transfer error Interrupt */
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
+
+ /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+ hqspi->State = HAL_QSPI_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+ }
+ }
}
else
{
hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
-
status = HAL_ERROR;
/* Process unlocked */
@@ -1370,7 +1398,7 @@
}
else
{
- status = HAL_BUSY;
+ status = HAL_BUSY;
/* Process unlocked */
__HAL_UNLOCK(hqspi);
@@ -1378,33 +1406,33 @@
return status;
}
-
+
/**
- * @brief Receives an amount of data in non blocking mode with DMA.
- * @param hqspi QSPI handle
- * @param pData pointer to data buffer.
+ * @brief Receive an amount of data in non-blocking mode with DMA.
+ * @param hqspi : QSPI handle
+ * @param pData : pointer to data buffer.
* @note This function is used only in Indirect Read Mode
- * @note If DMA peripheral access is configured as halfword, the number
+ * @note If DMA peripheral access is configured as halfword, the number
* of data and the fifo threshold should be aligned on halfword
- * @note If DMA peripheral access is configured as word, the number
+ * @note If DMA peripheral access is configured as word, the number
* of data and the fifo threshold should be aligned on word
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
{
HAL_StatusTypeDef status = HAL_OK;
- uint32_t *tmp;
uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
- uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1);
-
+ uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
+
/* Process locked */
__HAL_LOCK(hqspi);
-
+
if(hqspi->State == HAL_QSPI_STATE_READY)
{
+ /* Clear the error code */
hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
- if(pData != NULL )
+
+ if(pData != NULL )
{
/* Configure counters of the handle */
if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
@@ -1413,193 +1441,204 @@
}
else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
{
- if (((data_size % 2) != 0) || ((hqspi->Init.FifoThreshold % 2) != 0))
+ if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U))
{
- /* The number of data or the fifo threshold is not aligned on halfword
- => no transfer possible with DMA peripheral access configured as halfword */
+ /* The number of data or the fifo threshold is not aligned on halfword
+ => no transfer possible with DMA peripheral access configured as halfword */
hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
status = HAL_ERROR;
-
+
/* Process unlocked */
__HAL_UNLOCK(hqspi);
}
else
{
- hqspi->RxXferCount = (data_size >> 1);
+ hqspi->RxXferCount = (data_size >> 1U);
}
}
else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
{
- if (((data_size % 4) != 0) || ((hqspi->Init.FifoThreshold % 4) != 0))
+ if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U))
{
- /* The number of data or the fifo threshold is not aligned on word
- => no transfer possible with DMA peripheral access configured as word */
+ /* The number of data or the fifo threshold is not aligned on word
+ => no transfer possible with DMA peripheral access configured as word */
hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
status = HAL_ERROR;
-
+
/* Process unlocked */
__HAL_UNLOCK(hqspi);
}
else
{
- hqspi->RxXferCount = (data_size >> 2);
+ hqspi->RxXferCount = (data_size >> 2U);
}
}
-
+ else
+ {
+ /* Nothing to do */
+ }
+
if (status == HAL_OK)
{
-
/* Update state */
hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
-
+
/* Clear interrupt */
__HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
-
+
/* Configure size and pointer of the handle */
hqspi->RxXferSize = hqspi->RxXferCount;
hqspi->pRxBuffPtr = pData;
-
+
/* Set the QSPI DMA transfer complete callback */
hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
-
+
/* Set the QSPI DMA Half transfer complete callback */
hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
-
+
/* Set the DMA error callback */
hqspi->hdma->XferErrorCallback = QSPI_DMAError;
-
- /* Clear the DMA abort callback */
+
+ /* Clear the DMA abort callback */
hqspi->hdma->XferAbortCallback = NULL;
-
+
/* Configure the direction of the DMA */
hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
-
+
/* Enable the DMA Channel */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);
-
- /* Configure QSPI: CCR register with functional as indirect read */
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
-
- /* Start the transfer by re-writing the address in AR register */
- WRITE_REG(hqspi->Instance->AR, addr_reg);
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Enable the QSPI transfer error Interrupt */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
-
- /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
- SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+ if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize) == HAL_OK)
+ {
+ /* Configure QSPI: CCR register with functional as indirect read */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+
+ /* Start the transfer by re-writing the address in AR register */
+ WRITE_REG(hqspi->Instance->AR, addr_reg);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Enable the QSPI transfer error Interrupt */
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
+
+ /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+ hqspi->State = HAL_QSPI_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+ }
}
}
else
{
hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
status = HAL_ERROR;
-
+
/* Process unlocked */
__HAL_UNLOCK(hqspi);
}
}
else
{
- status = HAL_BUSY;
-
+ status = HAL_BUSY;
+
/* Process unlocked */
__HAL_UNLOCK(hqspi);
}
-
+
return status;
}
/**
- * @brief Configure the QSPI Automatic Polling Mode in blocking mode.
- * @param hqspi QSPI handle
- * @param cmd structure that contains the command configuration information.
- * @param cfg structure that contains the polling configuration information.
- * @param Timeout Time out duration
+ * @brief Configure the QSPI Automatic Polling Mode in blocking mode.
+ * @param hqspi : QSPI handle
+ * @param cmd : structure that contains the command configuration information.
+ * @param cfg : structure that contains the polling configuration information.
+ * @param Timeout : Timeout duration
* @note This function is used only in Automatic Polling Mode
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
{
- HAL_StatusTypeDef status = HAL_ERROR;
+ HAL_StatusTypeDef status;
uint32_t tickstart = HAL_GetTick();
-
+
/* Check the parameters */
assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
{
assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
}
-
+
assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
if (cmd->AddressMode != QSPI_ADDRESS_NONE)
{
assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
}
-
+
assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
{
assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
}
-
+
assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
-
+
assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
+
assert_param(IS_QSPI_INTERVAL(cfg->Interval));
assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
-
+
/* Process locked */
__HAL_LOCK(hqspi);
-
+
if(hqspi->State == HAL_QSPI_STATE_READY)
{
-
hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
+
/* Update state */
hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
-
+
/* Wait till BUSY flag reset */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
-
+
if (status == HAL_OK)
{
/* Configure QSPI: PSMAR register with the status match value */
WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
-
+
/* Configure QSPI: PSMKR register with the status mask value */
WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
-
+
/* Configure QSPI: PIR register with the interval value */
WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
-
- /* Configure QSPI: CR register with Match mode and Automatic stop enabled
+
+ /* Configure QSPI: CR register with Match mode and Automatic stop enabled
(otherwise there will be an infinite loop in blocking mode) */
- MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
+ MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
(cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
-
+
/* Call the configuration function */
cmd->NbData = cfg->StatusBytesSize;
QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
-
+
/* Wait until SM flag is set to go back in idle state */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);
if (status == HAL_OK)
{
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
-
+
/* Update state */
hqspi->State = HAL_QSPI_STATE_READY;
}
@@ -1607,97 +1646,98 @@
}
else
{
- status = HAL_BUSY;
+ status = HAL_BUSY;
}
+
/* Process unlocked */
__HAL_UNLOCK(hqspi);
-
+
/* Return function status */
- return status;
+ return status;
}
/**
- * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
- * @param hqspi QSPI handle
- * @param cmd structure that contains the command configuration information.
- * @param cfg structure that contains the polling configuration information.
+ * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
+ * @param hqspi : QSPI handle
+ * @param cmd : structure that contains the command configuration information.
+ * @param cfg : structure that contains the polling configuration information.
* @note This function is used only in Automatic Polling Mode
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
{
- HAL_StatusTypeDef status = HAL_ERROR;
+ HAL_StatusTypeDef status;
uint32_t tickstart = HAL_GetTick();
-
+
/* Check the parameters */
assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
{
assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
}
-
+
assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
if (cmd->AddressMode != QSPI_ADDRESS_NONE)
{
assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
}
-
+
assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
{
assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
}
-
+
assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
-
+
assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
+
assert_param(IS_QSPI_INTERVAL(cfg->Interval));
assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
-
+
/* Process locked */
__HAL_LOCK(hqspi);
-
+
if(hqspi->State == HAL_QSPI_STATE_READY)
{
hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
+
/* Update state */
hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
-
+
/* Wait till BUSY flag reset */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
-
+
if (status == HAL_OK)
{
/* Configure QSPI: PSMAR register with the status match value */
WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
-
+
/* Configure QSPI: PSMKR register with the status mask value */
WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
-
+
/* Configure QSPI: PIR register with the interval value */
WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
-
+
/* Configure QSPI: CR register with Match mode and Automatic stop mode */
- MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
+ MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
(cfg->MatchMode | cfg->AutomaticStop));
-
+
/* Clear interrupt */
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
-
+
/* Call the configuration function */
cmd->NbData = cfg->StatusBytesSize;
QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
/* Process unlocked */
__HAL_UNLOCK(hqspi);
-
+
/* Enable the QSPI Transfer Error and status match Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
@@ -1710,29 +1750,29 @@
}
else
{
- status = HAL_BUSY;
+ status = HAL_BUSY;
/* Process unlocked */
__HAL_UNLOCK(hqspi);
}
-
+
/* Return function status */
- return status;
+ return status;
}
/**
- * @brief Configure the Memory Mapped mode.
- * @param hqspi QSPI handle
- * @param cmd structure that contains the command configuration information.
- * @param cfg structure that contains the memory mapped configuration information.
+ * @brief Configure the Memory Mapped mode.
+ * @param hqspi : QSPI handle
+ * @param cmd : structure that contains the command configuration information.
+ * @param cfg : structure that contains the memory mapped configuration information.
* @note This function is used only in Memory mapped Mode
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
{
- HAL_StatusTypeDef status = HAL_ERROR;
+ HAL_StatusTypeDef status;
uint32_t tickstart = HAL_GetTick();
-
+
/* Check the parameters */
assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
@@ -1760,20 +1800,20 @@
assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
-
+
/* Process locked */
__HAL_LOCK(hqspi);
-
+
if(hqspi->State == HAL_QSPI_STATE_READY)
{
hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
+
/* Update state */
hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
-
+
/* Wait till BUSY flag reset */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
-
+
if (status == HAL_OK)
{
/* Configure QSPI: CR register with timeout counter enable */
@@ -1782,51 +1822,51 @@
if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
{
assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
-
+
/* Configure QSPI: LPTR register with the low-power timeout value */
WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
-
+
/* Clear interrupt */
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
/* Enable the QSPI TimeOut Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
}
-
+
/* Call the configuration function */
QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
}
}
else
{
- status = HAL_BUSY;
+ status = HAL_BUSY;
}
/* Process unlocked */
__HAL_UNLOCK(hqspi);
-
+
/* Return function status */
- return status;
+ return status;
}
/**
- * @brief Transfer Error callbacks
- * @param hqspi QSPI handle
+ * @brief Transfer Error callback.
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_QSPI_ErrorCallback could be implemented in the user file
*/
}
/**
* @brief Abort completed callback.
- * @param hqspi QSPI handle
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1841,120 +1881,120 @@
/**
* @brief Command completed callback.
- * @param hqspi QSPI handle
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
-
- /* NOTE: This function Should not be modified, when the callback is needed,
+
+ /* NOTE: This function should not be modified, when the callback is needed,
the HAL_QSPI_CmdCpltCallback could be implemented in the user file
*/
}
/**
- * @brief Rx Transfer completed callbacks.
- * @param hqspi QSPI handle
+ * @brief Rx Transfer completed callback.
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
-
- /* NOTE: This function Should not be modified, when the callback is needed,
+
+ /* NOTE: This function should not be modified, when the callback is needed,
the HAL_QSPI_RxCpltCallback could be implemented in the user file
*/
}
/**
- * @brief Tx Transfer completed callbacks.
- * @param hqspi QSPI handle
+ * @brief Tx Transfer completed callback.
+ * @param hqspi : QSPI handle
* @retval None
*/
- __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
+__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
-
- /* NOTE: This function Should not be modified, when the callback is needed,
+
+ /* NOTE: This function should not be modified, when the callback is needed,
the HAL_QSPI_TxCpltCallback could be implemented in the user file
- */
+ */
}
/**
- * @brief Rx Half Transfer completed callbacks.
- * @param hqspi QSPI handle
+ * @brief Rx Half Transfer completed callback.
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
-
- /* NOTE: This function Should not be modified, when the callback is needed,
+
+ /* NOTE: This function should not be modified, when the callback is needed,
the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
*/
}
/**
- * @brief Tx Half Transfer completed callbacks.
- * @param hqspi QSPI handle
+ * @brief Tx Half Transfer completed callback.
+ * @param hqspi : QSPI handle
* @retval None
*/
- __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
+__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
-
- /* NOTE: This function Should not be modified, when the callback is needed,
+
+ /* NOTE: This function should not be modified, when the callback is needed,
the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
- */
+ */
}
/**
- * @brief FIFO Threshold callbacks
- * @param hqspi QSPI handle
+ * @brief FIFO Threshold callback.
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
*/
}
/**
- * @brief Status Match callbacks
- * @param hqspi QSPI handle
+ * @brief Status Match callback.
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_QSPI_StatusMatchCallback could be implemented in the user file
*/
}
/**
- * @brief Timeout callbacks
- * @param hqspi QSPI handle
+ * @brief Timeout callback.
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_QSPI_TimeOutCallback could be implemented in the user file
*/
}
@@ -2184,26 +2224,27 @@
* @}
*/
-/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
- * @brief QSPI control and State functions
+/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
+ * @brief QSPI control and State functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral Control and State functions #####
- ===============================================================================
+ ===============================================================================
[..]
This subsection provides a set of functions allowing to :
- (+) Check in run-time the state of the driver.
+ (+) Check in run-time the state of the driver.
(+) Check the error code set during last operation.
(+) Abort any operation.
-.....
+
+
@endverbatim
* @{
*/
/**
* @brief Return the QSPI handle state.
- * @param hqspi QSPI handle
+ * @param hqspi : QSPI handle
* @retval HAL state
*/
HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
@@ -2213,8 +2254,8 @@
}
/**
-* @brief Return the QSPI error code
-* @param hqspi QSPI handle
+* @brief Return the QSPI error code.
+* @param hqspi : QSPI handle
* @retval QSPI Error Code
*/
uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
@@ -2223,50 +2264,53 @@
}
/**
-* @brief Abort the current transmission
-* @param hqspi QSPI handle
+* @brief Abort the current transmission.
+* @param hqspi : QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tickstart = HAL_GetTick();
-
+
/* Check if the state is in one of the busy states */
- if ((hqspi->State & 0x2) != 0)
+ if (((uint32_t)hqspi->State & 0x2U) != 0U)
{
/* Process unlocked */
__HAL_UNLOCK(hqspi);
- if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
+
/* Abort DMA channel */
status = HAL_DMA_Abort(hqspi->hdma);
if(status != HAL_OK)
{
hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
}
- }
-
+ }
+
/* Configure QSPI: CR register with Abort request */
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
-
+
/* Wait until TC flag is set to go back in idle state */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
- if(status == HAL_OK)
+ if (status == HAL_OK)
{
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
+
/* Wait until BUSY flag is reset */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
}
-
+
if (status == HAL_OK)
{
+ /* Reset functional mode configuration to indirect write mode by default */
+ CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
+
/* Update state */
hqspi->State = HAL_QSPI_STATE_READY;
}
@@ -2277,30 +2321,30 @@
/**
* @brief Abort the current transmission (non-blocking function)
-* @param hqspi QSPI handle
+* @param hqspi : QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
{
HAL_StatusTypeDef status = HAL_OK;
-
+
/* Check if the state is in one of the busy states */
- if ((hqspi->State & 0x2) != 0)
+ if (((uint32_t)hqspi->State & 0x2U) != 0U)
{
/* Process unlocked */
__HAL_UNLOCK(hqspi);
-
+
/* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_ABORT;
-
+ hqspi->State = HAL_QSPI_STATE_ABORT;
+
/* Disable all interrupts */
__HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));
-
- if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
+
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
+
/* Abort DMA channel */
hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK)
@@ -2320,21 +2364,20 @@
{
/* Clear interrupt */
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
+
/* Enable the QSPI Transfer Complete Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
-
+
/* Configure QSPI: CR register with Abort request */
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
}
}
-
return status;
}
-/** @brief Set QSPI timeout
- * @param hqspi QSPI handle.
- * @param Timeout Timeout for the QSPI memory access.
+/** @brief Set QSPI timeout.
+ * @param hqspi : QSPI handle.
+ * @param Timeout : Timeout for the QSPI memory access.
* @retval None
*/
void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
@@ -2343,8 +2386,8 @@
}
/** @brief Set QSPI Fifo threshold.
- * @param hqspi QSPI handle.
- * @param Threshold Threshold of the Fifo (value between 1 and 16).
+ * @param hqspi : QSPI handle.
+ * @param Threshold : Threshold of the Fifo (value between 1 and 16).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
@@ -2358,16 +2401,16 @@
{
/* Synchronize init structure with new FIFO threshold value */
hqspi->Init.FifoThreshold = Threshold;
-
+
/* Configure QSPI FIFO Threshold */
- MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
- ((hqspi->Init.FifoThreshold - 1) << QUADSPI_CR_FTHRES_Pos));
+ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
+ ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
}
else
{
- status = HAL_BUSY;
+ status = HAL_BUSY;
}
-
+
/* Process unlocked */
__HAL_UNLOCK(hqspi);
@@ -2376,56 +2419,99 @@
}
/** @brief Get QSPI Fifo threshold.
- * @param hqspi QSPI handle.
+ * @param hqspi : QSPI handle.
* @retval Fifo threshold (value between 1 and 16)
*/
uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
{
- return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1);
+ return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U);
+}
+
+/** @brief Set FlashID.
+ * @param hqspi : QSPI handle.
+ * @param FlashID : Index of the flash memory to be accessed.
+ * This parameter can be a value of @ref QSPI_Flash_Select.
+ * @note The FlashID is ignored when dual flash mode is enabled.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameter */
+ assert_param(IS_QSPI_FLASH_ID(FlashID));
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ /* Synchronize init structure with new FlashID value */
+ hqspi->Init.FlashID = FlashID;
+
+ /* Configure QSPI FlashID */
+ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FSEL, FlashID);
+ }
+ else
+ {
+ status = HAL_BUSY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Return function status */
+ return status;
}
/**
* @}
*/
-/* Private functions ---------------------------------------------------------*/
-
/**
- * @brief DMA QSPI receive process complete callback.
- * @param hdma DMA handle
+ * @}
+ */
+
+/** @defgroup QSPI_Private_Functions QSPI Private Functions
+ * @{
+ */
+
+/**
+ * @brief DMA QSPI receive process complete callback.
+ * @param hdma : DMA handle
* @retval None
*/
-static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
+static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
{
- QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hqspi->RxXferCount = 0;
-
+ QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
+ hqspi->RxXferCount = 0U;
+
/* Enable the QSPI transfer complete Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
}
/**
- * @brief DMA QSPI transmit process complete callback.
- * @param hdma DMA handle
+ * @brief DMA QSPI transmit process complete callback.
+ * @param hdma : DMA handle
* @retval None
*/
-static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
+static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
{
- QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hqspi->TxXferCount = 0;
-
+ QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
+ hqspi->TxXferCount = 0U;
+
/* Enable the QSPI transfer complete Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
}
/**
- * @brief DMA QSPI receive process half complete callback
- * @param hdma DMA handle
+ * @brief DMA QSPI receive process half complete callback.
+ * @param hdma : DMA handle
* @retval None
*/
static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
- QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
hqspi->RxHalfCpltCallback(hqspi);
@@ -2435,13 +2521,13 @@
}
/**
- * @brief DMA QSPI transmit process half complete callback
- * @param hdma DMA handle
+ * @brief DMA QSPI transmit process half complete callback.
+ * @param hdma : DMA handle
* @retval None
*/
static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
- QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
hqspi->TxHalfCpltCallback(hqspi);
@@ -2452,49 +2538,50 @@
/**
* @brief DMA QSPI communication error callback.
- * @param hdma DMA handle
+ * @param hdma : DMA handle
* @retval None
*/
-static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
+static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
{
- QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
+ QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent);
+
/* if DMA error is FIFO error ignore it */
if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
{
- hqspi->RxXferCount = 0;
- hqspi->TxXferCount = 0;
- hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
-
- /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
- CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
- /* Abort the QSPI */
- HAL_QSPI_Abort_IT(hqspi);
+ hqspi->RxXferCount = 0U;
+ hqspi->TxXferCount = 0U;
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+
+ /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+
+ /* Abort the QSPI */
+ (void)HAL_QSPI_Abort_IT(hqspi);
+
}
}
/**
* @brief DMA QSPI abort complete callback.
- * @param hdma DMA handle
+ * @param hdma : DMA handle
* @retval None
*/
-static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
+static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
{
- QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent);
- hqspi->RxXferCount = 0;
- hqspi->TxXferCount = 0;
+ hqspi->RxXferCount = 0U;
+ hqspi->TxXferCount = 0U;
if(hqspi->State == HAL_QSPI_STATE_ABORT)
{
/* DMA Abort called by QSPI abort */
/* Clear interrupt */
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
+
/* Enable the QSPI Transfer Complete Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
-
+
/* Configure QSPI: CR register with Abort request */
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
}
@@ -2503,7 +2590,7 @@
/* DMA Abort called due to a transfer error interrupt */
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
-
+
/* Error callback */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
hqspi->ErrorCallback(hqspi);
@@ -2515,27 +2602,27 @@
/**
* @brief Wait for a flag state until timeout.
- * @param hqspi QSPI handle
- * @param Flag Flag checked
- * @param State Value of the flag expected
- * @param tickstart Start tick value
- * @param Timeout Duration of the time out
+ * @param hqspi : QSPI handle
+ * @param Flag : Flag checked
+ * @param State : Value of the flag expected
+ * @param Tickstart : Tick start value
+ * @param Timeout : Duration of the timeout
* @retval HAL status
*/
-static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
- FlagStatus State, uint32_t tickstart, uint32_t Timeout)
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
+ FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
{
- /* Wait until flag is in expected state */
- while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
+ /* Wait until flag is in expected state */
+ while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
hqspi->State = HAL_QSPI_STATE_ERROR;
hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
-
+
return HAL_ERROR;
}
}
@@ -2545,9 +2632,9 @@
/**
* @brief Configure the communication registers.
- * @param hqspi QSPI handle
- * @param cmd structure that contains the command configuration information
- * @param FunctionalMode functional mode to configured
+ * @param hqspi : QSPI handle
+ * @param cmd : structure that contains the command configuration information
+ * @param FunctionalMode : functional mode to configured
* This parameter can be one of the following values:
* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
@@ -2562,9 +2649,9 @@
if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
{
/* Configure QSPI: DLR register with the number of data to read or write */
- WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1));
+ WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U));
}
-
+
if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
{
if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
@@ -2577,9 +2664,10 @@
/*---- Command with instruction, address and alternate bytes ----*/
/* Configure QSPI: CCR register with all communications parameters */
WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
- cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
- cmd->InstructionMode | cmd->Instruction | FunctionalMode));
+ cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+ cmd->AlternateBytesSize | cmd->AlternateByteMode |
+ cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
+ cmd->Instruction | FunctionalMode));
if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
{
@@ -2592,8 +2680,9 @@
/*---- Command with instruction and alternate bytes ----*/
/* Configure QSPI: CCR register with all communications parameters */
WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
- cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode |
+ cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+ cmd->AlternateBytesSize | cmd->AlternateByteMode |
+ cmd->AddressMode | cmd->InstructionMode |
cmd->Instruction | FunctionalMode));
}
}
@@ -2604,9 +2693,9 @@
/*---- Command with instruction and address ----*/
/* Configure QSPI: CCR register with all communications parameters */
WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
- cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
- cmd->Instruction | FunctionalMode));
+ cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+ cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
+ cmd->InstructionMode | cmd->Instruction | FunctionalMode));
if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
{
@@ -2619,9 +2708,9 @@
/*---- Command with only instruction ----*/
/* Configure QSPI: CCR register with all communications parameters */
WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
- cmd->AddressMode | cmd->InstructionMode | cmd->Instruction |
- FunctionalMode));
+ cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+ cmd->AlternateByteMode | cmd->AddressMode |
+ cmd->InstructionMode | cmd->Instruction | FunctionalMode));
}
}
}
@@ -2637,8 +2726,9 @@
/*---- Command with address and alternate bytes ----*/
/* Configure QSPI: CCR register with all communications parameters */
WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
- cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
+ cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+ cmd->AlternateBytesSize | cmd->AlternateByteMode |
+ cmd->AddressSize | cmd->AddressMode |
cmd->InstructionMode | FunctionalMode));
if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
@@ -2652,9 +2742,9 @@
/*---- Command with only alternate bytes ----*/
/* Configure QSPI: CCR register with all communications parameters */
WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
- cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode |
- FunctionalMode));
+ cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+ cmd->AlternateBytesSize | cmd->AlternateByteMode |
+ cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
}
}
else
@@ -2664,9 +2754,9 @@
/*---- Command with only address ----*/
/* Configure QSPI: CCR register with all communications parameters */
WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
- cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
- FunctionalMode));
+ cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+ cmd->AlternateByteMode | cmd->AddressSize |
+ cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
{
@@ -2681,13 +2771,19 @@
{
/* Configure QSPI: CCR register with all communications parameters */
WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
- cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
+ cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+ cmd->AlternateByteMode | cmd->AddressMode |
+ cmd->InstructionMode | FunctionalMode));
}
}
}
}
}
+
+/**
+ * @}
+ */
+
/**
* @}
*/
@@ -2701,4 +2797,6 @@
* @}
*/
+#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f7xx_hal_rcc.c b/Src/stm32f7xx_hal_rcc.c
index c8290a8..d7132c0 100644
--- a/Src/stm32f7xx_hal_rcc.c
+++ b/Src/stm32f7xx_hal_rcc.c
@@ -317,7 +317,7 @@
SystemCoreClock = HSI_VALUE;
/* Adapt Systick interrupt period */
- if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
+ if (HAL_InitTick(uwTickPrio) != HAL_OK)
{
return HAL_ERROR;
}
@@ -344,10 +344,11 @@
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
uint32_t tickstart;
+ uint32_t pll_config;
FlagStatus pwrclkchanged = RESET;
/* Check Null pointer */
- if(RCC_OscInitStruct == NULL)
+ if (RCC_OscInitStruct == NULL)
{
return HAL_ERROR;
}
@@ -356,15 +357,15 @@
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
- || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
+ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
+ || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
{
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
{
return HAL_ERROR;
}
@@ -375,15 +376,15 @@
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
/* Check the HSE State */
- if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till HSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
{
- if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -395,9 +396,9 @@
tickstart = HAL_GetTick();
/* Wait till HSE is bypassed or disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
{
- if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -406,18 +407,18 @@
}
}
/*----------------------------- HSI Configuration --------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
{
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
- || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
+ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
+ || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
{
/* When HSI is used as system clock it will not disabled */
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
+ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
{
return HAL_ERROR;
}
@@ -431,7 +432,7 @@
else
{
/* Check the HSI State */
- if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
+ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
@@ -440,9 +441,9 @@
tickstart = HAL_GetTick();
/* Wait till HSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
{
- if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -460,9 +461,9 @@
tickstart = HAL_GetTick();
/* Wait till HSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
{
- if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -471,13 +472,13 @@
}
}
/*------------------------------ LSI Configuration -------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
- if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
+ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
@@ -486,9 +487,9 @@
tickstart = HAL_GetTick();
/* Wait till LSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
{
- if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -503,9 +504,9 @@
tickstart = HAL_GetTick();
/* Wait till LSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
{
- if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -513,21 +514,21 @@
}
}
/*------------------------------ LSE Configuration -------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
{
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
- if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+ if (__HAL_RCC_PWR_IS_CLK_DISABLED())
{
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
pwrclkchanged = SET;
}
- if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
+ if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
{
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
@@ -535,9 +536,9 @@
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
+ while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
{
- if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -547,15 +548,15 @@
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
/* Check the LSE State */
- if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
+ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -567,9 +568,9 @@
tickstart = HAL_GetTick();
/* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
{
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -577,7 +578,7 @@
}
/* Restore clock configuration if changed */
- if(pwrclkchanged == SET)
+ if (pwrclkchanged == SET)
{
__HAL_RCC_PWR_CLK_DISABLE();
}
@@ -588,9 +589,9 @@
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
{
/* Check if the PLL is used as system clock or not */
- if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
{
- if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
{
/* Check the parameters */
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
@@ -609,9 +610,9 @@
tickstart = HAL_GetTick();
/* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
{
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -640,9 +641,9 @@
tickstart = HAL_GetTick();
/* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
{
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -657,9 +658,9 @@
tickstart = HAL_GetTick();
/* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
{
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -668,7 +669,27 @@
}
else
{
- return HAL_ERROR;
+ /* Do not return HAL_ERROR if request repeats the current configuration */
+ pll_config = RCC->PLLCFGR;
+#if defined (RCC_PLLCFGR_PLLR)
+ if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
+ (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+ (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
+ (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
+ (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
+ (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
+ (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
+#else
+ if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
+ (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+ (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
+ (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
+ (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
+ (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
+#endif
+ {
+ return HAL_ERROR;
+ }
}
}
return HAL_OK;
@@ -705,7 +726,7 @@
uint32_t tickstart = 0;
/* Check Null pointer */
- if(RCC_ClkInitStruct == NULL)
+ if (RCC_ClkInitStruct == NULL)
{
return HAL_ERROR;
}
@@ -719,30 +740,30 @@
(HCLK) and the supply voltage of the device. */
/* Increasing the CPU frequency */
- if(FLatency > __HAL_FLASH_GET_LATENCY())
+ if (FLatency > __HAL_FLASH_GET_LATENCY())
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
- if(__HAL_FLASH_GET_LATENCY() != FLatency)
+ if (__HAL_FLASH_GET_LATENCY() != FLatency)
{
return HAL_ERROR;
}
}
/*-------------------------- HCLK Configuration --------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
}
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
}
@@ -753,24 +774,24 @@
}
/*------------------------- SYSCLK Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
/* Check the HSE ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
{
return HAL_ERROR;
}
}
/* PLL is selected as System Clock Source */
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
{
/* Check the PLL ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
{
return HAL_ERROR;
}
@@ -779,7 +800,7 @@
else
{
/* Check the HSI ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
{
return HAL_ERROR;
}
@@ -800,38 +821,38 @@
}
/* Decreasing the number of wait states because of lower CPU frequency */
- if(FLatency < __HAL_FLASH_GET_LATENCY())
+ if (FLatency < __HAL_FLASH_GET_LATENCY())
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
- if(__HAL_FLASH_GET_LATENCY() != FLatency)
+ if (__HAL_FLASH_GET_LATENCY() != FLatency)
{
return HAL_ERROR;
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
}
/* Update the SystemCoreClock global variable */
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
+ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
/* Configure the source of time base considering new system clocks settings*/
- HAL_InitTick (TICK_INT_PRIORITY);
+ HAL_InitTick(uwTickPrio);
return HAL_OK;
}
@@ -888,7 +909,7 @@
assert_param(IS_RCC_MCO(RCC_MCOx));
assert_param(IS_RCC_MCODIV(RCC_MCODiv));
/* RCC_MCO1 */
- if(RCC_MCOx == RCC_MCO1)
+ if (RCC_MCOx == RCC_MCO1)
{
assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
@@ -990,7 +1011,7 @@
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
- break;
+ break;
}
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
{
@@ -1005,16 +1026,16 @@
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
{
/* HSE used as PLL clock source */
- pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
+ pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
}
else
{
/* HSI used as PLL clock source */
- pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
+ pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
}
- pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1 ) *2);
+ pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
- sysclockfreq = pllvco/pllp;
+ sysclockfreq = pllvco / pllp;
break;
}
default:
@@ -1047,7 +1068,7 @@
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
+ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
}
/**
@@ -1059,7 +1080,7 @@
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
+ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
}
/**
@@ -1075,11 +1096,11 @@
RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
/* Get the HSE configuration -----------------------------------------------*/
- if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+ if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
{
RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
}
- else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
+ else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
{
RCC_OscInitStruct->HSEState = RCC_HSE_ON;
}
@@ -1089,7 +1110,7 @@
}
/* Get the HSI configuration -----------------------------------------------*/
- if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
+ if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
{
RCC_OscInitStruct->HSIState = RCC_HSI_ON;
}
@@ -1098,14 +1119,14 @@
RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
}
- RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
+ RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
/* Get the LSE configuration -----------------------------------------------*/
- if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+ if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
{
RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
}
- else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+ else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
{
RCC_OscInitStruct->LSEState = RCC_LSE_ON;
}
@@ -1115,7 +1136,7 @@
}
/* Get the LSI configuration -----------------------------------------------*/
- if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
+ if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)
{
RCC_OscInitStruct->LSIState = RCC_LSI_ON;
}
@@ -1125,7 +1146,7 @@
}
/* Get the PLL configuration -----------------------------------------------*/
- if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
+ if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
{
RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
}
@@ -1180,7 +1201,7 @@
void HAL_RCC_NMI_IRQHandler(void)
{
/* Check RCC CSSF flag */
- if(__HAL_RCC_GET_IT(RCC_IT_CSS))
+ if (__HAL_RCC_GET_IT(RCC_IT_CSS))
{
/* RCC Clock Security System interrupt user callback */
HAL_RCC_CSSCallback();
diff --git a/Src/stm32f7xx_hal_rng.c b/Src/stm32f7xx_hal_rng.c
index 3e073e2..7094088 100644
--- a/Src/stm32f7xx_hal_rng.c
+++ b/Src/stm32f7xx_hal_rng.c
@@ -532,8 +532,16 @@
/**
* @brief Generates a 32-bit random number.
- * @note Each time the random number data is read the RNG_FLAG_DRDY flag
- * is automatically cleared.
+ * @note This function checks value of RNG_FLAG_DRDY flag to know if valid
+ * random number is available in the DR register (RNG_FLAG_DRDY flag set
+ * whenever a random number is available through the RNG_DR register).
+ * After transitioning from 0 to 1 (random number available),
+ * RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading
+ * four words from the RNG_DR register, i.e. further function calls
+ * will immediately return a new u32 random number (additional words are
+ * available and can be read by the application, till RNG_FLAG_DRDY flag remains high).
+ * @note When no more random number data is available in DR register, RNG_FLAG_DRDY
+ * flag is automatically cleared.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @param random32bit pointer to generated random number variable if successful.
@@ -697,13 +705,13 @@
if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET)
{
/* Update the error code */
- hrng->ErrorCode = HAL_RNG_ERROR_SEED;
+ hrng->ErrorCode = HAL_RNG_ERROR_CLOCK;
rngclockerror = 1U;
}
else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
{
/* Update the error code */
- hrng->ErrorCode = HAL_RNG_ERROR_CLOCK;
+ hrng->ErrorCode = HAL_RNG_ERROR_SEED;
rngclockerror = 1U;
}
else
@@ -768,6 +776,11 @@
/**
* @brief Data Ready callback in non-blocking mode.
+ * @note When RNG_FLAG_DRDY flag value is set, first random number has been read
+ * from DR register in IRQ Handler and is provided as callback parameter.
+ * Depending on valid data available in the conditioning output buffer,
+ * additional words can be read by the application from DR register till
+ * DRDY bit remains high.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @param random32bit generated random number.
diff --git a/Src/stm32f7xx_hal_rtc.c b/Src/stm32f7xx_hal_rtc.c
index de5a34a..dad8655 100644
--- a/Src/stm32f7xx_hal_rtc.c
+++ b/Src/stm32f7xx_hal_rtc.c
@@ -1586,10 +1586,11 @@
*/
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
{
- if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRA))
+ /* Get the AlarmA interrupt source enable status */
+ if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != (uint32_t)RESET)
{
- /* Get the status of the Interrupt */
- if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET)
+ /* Get the pending status of the AlarmA Interrupt */
+ if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != (uint32_t)RESET)
{
/* AlarmA callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
@@ -1598,15 +1599,16 @@
HAL_RTC_AlarmAEventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
- /* Clear the Alarm interrupt pending bit */
+ /* Clear the AlarmA interrupt pending bit */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);
}
}
- if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRB))
+ /* Get the AlarmB interrupt source enable status */
+ if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != (uint32_t)RESET)
{
- /* Get the status of the Interrupt */
- if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRB) != (uint32_t)RESET)
+ /* Get the pending status of the AlarmB Interrupt */
+ if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != (uint32_t)RESET)
{
/* AlarmB callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
@@ -1615,7 +1617,7 @@
HAL_RTCEx_AlarmBEventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
- /* Clear the Alarm interrupt pending bit */
+ /* Clear the AlarmB interrupt pending bit */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF);
}
}
diff --git a/Src/stm32f7xx_hal_rtc_ex.c b/Src/stm32f7xx_hal_rtc_ex.c
index c98f0af..9359280 100644
--- a/Src/stm32f7xx_hal_rtc_ex.c
+++ b/Src/stm32f7xx_hal_rtc_ex.c
@@ -656,10 +656,11 @@
*/
void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
{
- if(__HAL_RTC_TIMESTAMP_GET_IT(hrtc, RTC_IT_TS))
+ /* Get the TimeStamp interrupt source enable status */
+ if(__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != (uint32_t)RESET)
{
- /* Get the status of the Interrupt */
- if((uint32_t)(hrtc->Instance->CR & RTC_IT_TS) != (uint32_t)RESET)
+ /* Get the pending status of the TIMESTAMP Interrupt */
+ if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != (uint32_t)RESET)
{
/* TIMESTAMP callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
@@ -673,12 +674,11 @@
}
}
- /* Get the status of the Interrupt */
- if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== SET)
+ /* Get the Tamper1 interrupt source enable status */
+ if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != (uint32_t)RESET)
{
- /* Get the TAMPER Interrupt enable bit and pending bit */
- if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \
- (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP1IE)) != (uint32_t)RESET))
+ /* Get the pending status of the Tamper1 Interrupt */
+ if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != (uint32_t)RESET)
{
/* Tamper callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
@@ -692,12 +692,11 @@
}
}
- /* Get the status of the Interrupt */
- if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F)== SET)
+ /* Get the Tamper2 interrupt source enable status */
+ if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != (uint32_t)RESET)
{
- /* Get the TAMPER Interrupt enable bit and pending bit */
- if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \
- (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP2IE)) != (uint32_t)RESET))
+ /* Get the pending status of the Tamper2 Interrupt */
+ if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != (uint32_t)RESET)
{
/* Tamper callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
@@ -711,12 +710,11 @@
}
}
- /* Get the status of the Interrupt */
- if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F)== SET)
+ /* Get the Tamper3 interrupt source enable status */
+ if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != (uint32_t)RESET)
{
- /* Get the TAMPER Interrupt enable bit and pending bit */
- if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \
- (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP3IE)) != (uint32_t)RESET))
+ /* Get the pending status of the Tamper3 Interrupt */
+ if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != (uint32_t)RESET)
{
/* Tamper callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
@@ -1211,27 +1209,29 @@
/**
* @brief This function handles Wake Up Timer interrupt request.
+ * @note Unlike alarm interrupt line (shared by AlarmA and AlarmB) and tamper
+ * interrupt line (shared by timestamp and tampers) wakeup timer
+ * interrupt line is exclusive to the wakeup timer.
+ * There is no need in this case to check on the interrupt enable
+ * status via __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE().
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
{
- if(__HAL_RTC_WAKEUPTIMER_GET_IT(hrtc, RTC_IT_WUT))
+ /* Get the pending status of the WAKEUPTIMER Interrupt */
+ if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != (uint32_t)RESET)
{
- /* Get the status of the Interrupt */
- if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET)
- {
- /* WAKEUPTIMER callback */
+ /* WAKEUPTIMER callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- hrtc->WakeUpTimerEventCallback(hrtc);
+ hrtc->WakeUpTimerEventCallback(hrtc);
#else
- HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
+ HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
- /* Clear the WAKEUPTIMER interrupt pending bit */
- __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
- }
+ /* Clear the WAKEUPTIMER interrupt pending bit */
+ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
}
/* Clear the EXTI's line Flag for RTC WakeUpTimer */
diff --git a/Src/stm32f7xx_hal_sai.c b/Src/stm32f7xx_hal_sai.c
index 3c2cdde..e8022f4 100644
--- a/Src/stm32f7xx_hal_sai.c
+++ b/Src/stm32f7xx_hal_sai.c
@@ -132,12 +132,13 @@
*** Callback registration ***
=============================
-
+ [..]
The compilation define USE_HAL_SAI_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use functions @ref HAL_SAI_RegisterCallback() to register a user callback.
+ Use functions HAL_SAI_RegisterCallback() to register a user callback.
- Function @ref HAL_SAI_RegisterCallback() allows to register following callbacks:
+ [..]
+ Function HAL_SAI_RegisterCallback() allows to register following callbacks:
(+) RxCpltCallback : SAI receive complete.
(+) RxHalfCpltCallback : SAI receive half complete.
(+) TxCpltCallback : SAI transmit complete.
@@ -145,13 +146,16 @@
(+) ErrorCallback : SAI error.
(+) MspInitCallback : SAI MspInit.
(+) MspDeInitCallback : SAI MspDeInit.
+ [..]
This function takes as parameters the HAL peripheral handle, the callback ID
and a pointer to the user callback function.
- Use function @ref HAL_SAI_UnRegisterCallback() to reset a callback to the default
+ [..]
+ Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
- @ref HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the callback ID.
+ [..]
This function allows to reset following callbacks:
(+) RxCpltCallback : SAI receive complete.
(+) RxHalfCpltCallback : SAI receive half complete.
@@ -161,23 +165,26 @@
(+) MspInitCallback : SAI MspInit.
(+) MspDeInitCallback : SAI MspDeInit.
- By default, after the @ref HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
+ [..]
+ By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions:
- examples @ref HAL_SAI_RxCpltCallback(), @ref HAL_SAI_ErrorCallback().
+ examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback().
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_SAI_Init
- and @ref HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_SAI_Init and @ref HAL_SAI_DeInit
+ reset to the legacy weak (surcharged) functions in the HAL_SAI_Init
+ and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+ [..]
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_SAI_RegisterCallback before calling @ref HAL_SAI_DeInit
- or @ref HAL_SAI_Init function.
+ using HAL_SAI_RegisterCallback before calling HAL_SAI_DeInit
+ or HAL_SAI_Init function.
+ [..]
When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@@ -228,7 +235,6 @@
/** @defgroup SAI_Private_Constants SAI Private Constants
* @{
*/
-#define SAI_FIFO_SIZE 8
#define SAI_DEFAULT_TIMEOUT 4 /* 4ms */
/**
* @}
@@ -507,6 +513,8 @@
hsai->Init.Mckdiv+= 1;
}
}
+ /* Check the SAI Block master clock divider parameter */
+ assert_param(IS_SAI_BLOCK_MASTER_DIVIDER(hsai->Init.Mckdiv));
/* Compute CKSTR bits of SAI CR1 according ClockStrobing and AudioMode */
if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
@@ -2344,7 +2352,7 @@
{
SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef* )hdma)->Parent;
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+ if (hdma->Init.Mode != DMA_CIRCULAR)
{
hsai->XferCount = 0;
@@ -2390,7 +2398,7 @@
{
SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+ if (hdma->Init.Mode != DMA_CIRCULAR)
{
/* Disable Rx DMA Request */
hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
diff --git a/Src/stm32f7xx_hal_sd.c b/Src/stm32f7xx_hal_sd.c
index 781d588..33a0861 100644
--- a/Src/stm32f7xx_hal_sd.c
+++ b/Src/stm32f7xx_hal_sd.c
@@ -3,161 +3,165 @@
* @file stm32f7xx_hal_sd.c
* @author MCD Application Team
* @brief SD card HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Secure Digital (SD) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
- * + Peripheral Control functions
- * + SD card Control functions
- *
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
- This driver implements a high level communication layer for read and write from/to
- this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
- the user in HAL_SD_MspInit() function (MSP layer).
- Basically, the MSP layer configuration should be the same as we provide in the
+ This driver implements a high level communication layer for read and write from/to
+ this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
+ the user in HAL_SD_MspInit() function (MSP layer).
+ Basically, the MSP layer configuration should be the same as we provide in the
examples.
You can easily tailor this configuration according to hardware resources.
[..]
- This driver is a generic layered driver for SDMMC memories which uses the HAL
- SDMMC driver functions to interface with SD and uSD cards devices.
+ This driver is a generic layered driver for SDMMC memories which uses the HAL
+ SDMMC driver functions to interface with SD and uSD cards devices.
It is used as follows:
-
- (#)Initialize the SDMMC low level resources by implement the HAL_SD_MspInit() API:
- (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
+
+ (#)Initialize the SDMMC low level resources by implementing the HAL_SD_MspInit() API:
+ (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
(##) SDMMC pins configuration for SD card
- (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
+ (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
(+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
and according to your pin assignment;
- (##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
+ (##) DMA configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
and HAL_SD_WriteBlocks_DMA() APIs).
- (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
- (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
+ (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
+ (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
(##) NVIC configuration if you need to use interrupt process when using DMA transfer.
(+++) Configure the SDMMC and DMA interrupt priorities using functions
HAL_NVIC_SetPriority(); DMA priority is superior to SDMMC's priority
(+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ()
- (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT()
+ (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT()
and __HAL_SD_DISABLE_IT() inside the communication process.
(+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
and __HAL_SD_CLEAR_IT()
(##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT()
and HAL_SD_WriteBlocks_IT() APIs).
- (+++) Configure the SDMMC interrupt priorities using function
- HAL_NVIC_SetPriority();
+ (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority();
(+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
- (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT()
+ (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT()
and __HAL_SD_DISABLE_IT() inside the communication process.
(+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
and __HAL_SD_CLEAR_IT()
- (#) At this stage, you can perform SD read/write/erase operations after SD card initialization
+ (#) At this stage, you can perform SD read/write/erase operations after SD card initialization
-
+
*** SD Card Initialization and configuration ***
- ================================================
+ ================================================
[..]
- To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
- SDMMC IP (STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer).
+ To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
+ SDMMC Peripheral(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer).
This function provide the following operations:
- (#) Initialize the SDMMC peripheral interface with defaullt configuration.
- The initialization process is done at 400KHz. You can change or adapt
- this frequency by adjusting the "ClockDiv" field.
+ (#) Apply the SD Card initialization process at 400KHz and check the SD Card
+ type (Standard Capacity or High Capacity). You can change or adapt this
+ frequency by adjusting the "ClockDiv" field.
The SD Card frequency (SDMMC_CK) is computed as follows:
-
+
SDMMC_CK = SDMMCCLK / (ClockDiv + 2)
-
- In initialization mode and according to the SD Card standard,
+
+ In initialization mode and according to the SD Card standard,
make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
- This phase of initialization is done through SDMMC_Init() and
+ This phase of initialization is done through SDMMC_Init() and
SDMMC_PowerState_ON() SDMMC low level APIs.
(#) Initialize the SD card. The API used is HAL_SD_InitCard().
- This phase allows the card initialization and identification
+ This phase allows the card initialization and identification
and check the SD Card type (Standard Capacity or High Capacity)
The initialization flow is compatible with SD standard.
- This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case
+ This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case
of plug-off plug-in.
-
- (#) Configure the SD Card Data transfer frequency. By Default, the card transfer
- frequency is set to 24MHz. You can change or adapt this frequency by adjusting
- the "ClockDiv" field.
- In transfer mode and according to the SD Card standard, make sure that the
+
+ (#) Configure the SD Card Data transfer frequency. You can change or adapt this
+ frequency by adjusting the "ClockDiv" field.
+ In transfer mode and according to the SD Card standard, make sure that the
SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
- To be able to use a frequency higher than 24MHz, you should use the SDMMC
- peripheral in bypass mode. Refer to the corresponding reference manual
+ To be able to use a frequency higher than 24MHz, you should use the SDMMC
+ peripheral in bypass mode. Refer to the corresponding reference manual
for more details.
-
+
(#) Select the corresponding SD Card according to the address read with the step 2.
-
+
(#) Configure the SD Card in wide bus mode: 4-bits data.
-
+
*** SD Card Read operation ***
==============================
- [..]
- (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
+ [..]
+ (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_SD_GetCardState() function for SD card state.
(+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_SD_GetCardState() function for SD card state.
You could also check the DMA transfer process through the SD Rx interrupt event.
(+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_SD_GetCardState() function for SD card state.
You could also check the IT transfer process through the SD Rx interrupt event.
-
+
*** SD Card Write operation ***
- ===============================
- [..]
- (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
+ ===============================
+ [..]
+ (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_SD_GetCardState() function for SD card state.
(+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_SD_GetCardState() function for SD card state.
- You could also check the DMA transfer process through the SD Tx interrupt event.
+ You could also check the DMA transfer process through the SD Tx interrupt event.
(+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_SD_GetCardState() function for SD card state.
You could also check the IT transfer process through the SD Tx interrupt event.
-
+
*** SD card status ***
- ======================
+ ======================
[..]
- (+) The SD Status contains status bits that are related to the SD Memory
+ (+) The SD Status contains status bits that are related to the SD Memory
Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus().
*** SD card information ***
- ===========================
+ ===========================
[..]
(+) To get SD card information, you can use the function HAL_SD_GetCardInfo().
It returns useful information about the SD card such as block size, card type,
@@ -165,13 +169,11 @@
*** SD card CSD register ***
============================
- [..]
(+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register.
Some of the CSD parameters are useful for card initialization and identification.
*** SD card CID register ***
============================
- [..]
(+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register.
Some of the CSD parameters are useful for card initialization and identification.
@@ -179,7 +181,7 @@
==================================
[..]
Below the list of most used macros in SD HAL driver.
-
+
(+) __HAL_SD_ENABLE : Enable the SD device
(+) __HAL_SD_DISABLE : Disable the SD device
(+) __HAL_SD_DMA_ENABLE: Enable the SDMMC DMA transfer
@@ -189,9 +191,8 @@
(+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not
(+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags
- [..]
- (@) You can refer to the SD HAL driver header file for more useful macros
-
+ (@) You can refer to the SD HAL driver header file for more useful macros
+
*** Callback registration ***
=============================================
[..]
@@ -222,7 +223,7 @@
By default, after the @ref HAL_SD_Init and if the state is HAL_SD_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_SD_Init
+ reset to the legacy weak (surcharged) functions in the @ref HAL_SD_Init
and @ref HAL_SD_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the @ref HAL_SD_Init and @ref HAL_SD_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -232,11 +233,11 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_SD_RegisterCallback before calling @ref HAL_SD_DeInit
+ using @ref HAL_SD_RegisterCallback before calling @ref HAL_SD_DeInit
or @ref HAL_SD_Init function.
When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registering feature is not available
+ not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@endverbatim
@@ -249,19 +250,21 @@
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
+#if defined(SDMMC1)
+
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
-/** @addtogroup SD
+/** @addtogroup SD
* @{
*/
@@ -272,11 +275,11 @@
/** @addtogroup SD_Private_Defines
* @{
*/
-
+
/**
* @}
*/
-
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -285,15 +288,15 @@
* @{
*/
static uint32_t SD_InitCard(SD_HandleTypeDef *hsd);
-static uint32_t SD_PowerON(SD_HandleTypeDef *hsd);
+static uint32_t SD_PowerON(SD_HandleTypeDef *hsd);
static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd);
static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd);
static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);
-static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd);
-static HAL_StatusTypeDef SD_Write_IT(SD_HandleTypeDef *hsd);
-static HAL_StatusTypeDef SD_Read_IT(SD_HandleTypeDef *hsd);
+static void SD_PowerOFF(SD_HandleTypeDef *hsd);
+static void SD_Write_IT(SD_HandleTypeDef *hsd);
+static void SD_Read_IT(SD_HandleTypeDef *hsd);
static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void SD_DMAError(DMA_HandleTypeDef *hdma);
@@ -309,13 +312,13 @@
*/
/** @addtogroup SD_Exported_Functions_Group1
- * @brief Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
*
-@verbatim
+@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
- [..]
+ [..]
This section provides functions allowing to initialize/de-initialize the SD
card device to be ready for use.
@@ -324,9 +327,9 @@
*/
/**
- * @brief Initializes the SD according to the specified parameters in the
+ * @brief Initializes the SD according to the specified parameters in the
SD_HandleTypeDef and create the associated handle.
- * @param hsd Pointer to the SD handle
+ * @param hsd: Pointer to the SD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
@@ -350,7 +353,7 @@
{
/* Allocate lock resource and initialize it */
hsd->Lock = HAL_UNLOCKED;
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
/* Reset Callback pointers in HAL_SD_STATE_RESET only */
hsd->TxCpltCallback = HAL_SD_TxCpltCallback;
hsd->RxCpltCallback = HAL_SD_RxCpltCallback;
@@ -367,20 +370,23 @@
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_SD_MspInit(hsd);
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
hsd->State = HAL_SD_STATE_BUSY;
/* Initialize the Card parameters */
- HAL_SD_InitCard(hsd);
+ if (HAL_SD_InitCard(hsd) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Initialize the error code */
- hsd->ErrorCode = HAL_DMA_ERROR_NONE;
-
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
/* Initialize the SD operation */
hsd->Context = SD_CONTEXT_NONE;
-
+
/* Initialize the SD state */
hsd->State = HAL_SD_STATE_READY;
@@ -389,14 +395,15 @@
/**
* @brief Initializes the SD Card.
- * @param hsd Pointer to SD handle
- * @note This function initializes the SD card. It could be used when a card
+ * @param hsd: Pointer to SD handle
+ * @note This function initializes the SD card. It could be used when a card
re-initialization is needed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
{
- uint32_t errorstate = HAL_SD_ERROR_NONE;
+ uint32_t errorstate;
+ HAL_StatusTypeDef status;
SD_InitTypeDef Init;
/* Default SDMMC peripheral configuration for SD card initialization */
@@ -408,20 +415,21 @@
Init.ClockDiv = SDMMC_INIT_CLK_DIV;
/* Initialize SDMMC peripheral interface with default configuration */
- SDMMC_Init(hsd->Instance, Init);
+ status = SDMMC_Init(hsd->Instance, Init);
+ if(status != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Disable SDMMC Clock */
- __HAL_SD_DISABLE(hsd);
-
+ __HAL_SD_DISABLE(hsd);
+
/* Set Power State to ON */
- SDMMC_PowerState_ON(hsd->Instance);
-
+ (void)SDMMC_PowerState_ON(hsd->Instance);
+
/* Enable SDMMC Clock */
__HAL_SD_ENABLE(hsd);
-
- /* Required power up waiting time before starting the SD initialization sequence */
- HAL_Delay(2);
-
+
/* Identify card operating voltage */
errorstate = SD_PowerON(hsd);
if(errorstate != HAL_SD_ERROR_NONE)
@@ -445,7 +453,7 @@
/**
* @brief De-Initializes the SD card.
- * @param hsd Pointer to SD handle
+ * @param hsd: Pointer to SD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
@@ -455,16 +463,16 @@
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance));
hsd->State = HAL_SD_STATE_BUSY;
-
- /* Set SD power state to off */
+
+ /* Set SD power state to off */
SD_PowerOFF(hsd);
-
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
if(hsd->MspDeInitCallback == NULL)
{
hsd->MspDeInitCallback = HAL_SD_MspDeInit;
@@ -475,41 +483,41 @@
#else
/* De-Initialize the MSP layer */
HAL_SD_MspDeInit(hsd);
-#endif
-
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+
hsd->ErrorCode = HAL_SD_ERROR_NONE;
hsd->State = HAL_SD_STATE_RESET;
-
+
return HAL_OK;
}
/**
* @brief Initializes the SD MSP.
- * @param hsd Pointer to SD handle
+ * @param hsd: Pointer to SD handle
* @retval None
*/
__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsd);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_SD_MspInit could be implemented in the user file
*/
}
/**
* @brief De-Initialize SD MSP.
- * @param hsd Pointer to SD handle
+ * @param hsd: Pointer to SD handle
* @retval None
*/
__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsd);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_SD_MspDeInit could be implemented in the user file
*/
}
@@ -519,14 +527,14 @@
*/
/** @addtogroup SD_Exported_Functions_Group2
- * @brief Data transfer functions
+ * @brief Data transfer functions
*
-@verbatim
+@verbatim
==============================================================================
##### IO operation functions #####
- ==============================================================================
+ ==============================================================================
[..]
- This subsection provides a set of functions allowing to manage the data
+ This subsection provides a set of functions allowing to manage the data
transfer from/to SD card.
@endverbatim
@@ -534,120 +542,136 @@
*/
/**
- * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
* is managed by polling mode.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
- * @param hsd Pointer to SD handle
- * @param pData pointer to the buffer that will contain the received data
- * @param BlockAdd Block Address from where data is to be read
- * @param NumberOfBlocks Number of SD blocks to read
- * @param Timeout Specify timeout value
+ * @param hsd: Pointer to SD handle
+ * @param pData: pointer to the buffer that will contain the received data
+ * @param BlockAdd: Block Address from where data is to be read
+ * @param NumberOfBlocks: Number of SD blocks to read
+ * @param Timeout: Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
{
SDMMC_DataInitTypeDef config;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
+ uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
- uint32_t count = 0, *tempbuff = (uint32_t *)pData;
-
+ uint32_t count, data, dataremaining;
+ uint32_t add = BlockAdd;
+ uint8_t *tempbuff = pData;
+
if(NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
-
+
if(hsd->State == HAL_SD_STATE_READY)
{
- hsd->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+ if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hsd->State = HAL_SD_STATE_BUSY;
-
+
/* Initialize data control register */
- hsd->Instance->DCTRL = 0;
-
+ hsd->Instance->DCTRL = 0U;
+
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
- BlockAdd *= 512;
+ add *= 512U;
}
-
+
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Configure the SD DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = NumberOfBlocks * BLOCKSIZE;
- config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
- config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
- config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- config.DPSM = SDMMC_DPSM_ENABLE;
- SDMMC_ConfigData(hsd->Instance, &config);
-
- /* Read block(s) in polling mode */
- if(NumberOfBlocks > 1)
- {
- hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK;
-
- /* Read Multi Block command */
- errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd);
- }
- else
- {
- hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK;
-
- /* Read Single Block command */
- errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd);
- }
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = NumberOfBlocks * BLOCKSIZE;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_ENABLE;
+ (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+ /* Read block(s) in polling mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK;
+
+ /* Read Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+ }
+ else
+ {
+ hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK;
+
+ /* Read Single Block command */
+ errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
+ }
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ return HAL_ERROR;
+ }
+
/* Poll on SDMMC flags */
+ dataremaining = config.DataLength;
while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
+ if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining > 0U))
{
/* Read data from SDMMC Rx FIFO */
for(count = 0U; count < 8U; count++)
{
- *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance);
+ data = SDMMC_ReadFIFO(hsd->Instance);
+ *tempbuff = (uint8_t)(data & 0xFFU);
+ tempbuff++;
+ dataremaining--;
+ *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+ tempbuff++;
+ dataremaining--;
+ *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+ tempbuff++;
+ dataremaining--;
+ *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+ tempbuff++;
+ dataremaining--;
}
- tempbuff += 8U;
}
-
- if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
+
+ if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
hsd->State= HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
return HAL_TIMEOUT;
}
}
/* Send stop transmission command in case of multiblock read */
if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
- {
+ {
if(hsd->SdCard.CardType != CARD_SECURED)
{
/* Send stop transmission command */
@@ -658,11 +682,12 @@
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
}
}
-
+
/* Get error state */
if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
{
@@ -670,6 +695,7 @@
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
@@ -678,6 +704,7 @@
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
@@ -686,30 +713,47 @@
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
-
- /* Empty FIFO if there is still any data */
- while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)))
+ else
{
- *tempbuff = SDMMC_ReadFIFO(hsd->Instance);
+ /* Nothing to do */
+ }
+
+ /* Empty FIFO if there is still any data */
+ while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (dataremaining > 0U))
+ {
+ data = SDMMC_ReadFIFO(hsd->Instance);
+ *tempbuff = (uint8_t)(data & 0xFFU);
tempbuff++;
-
- if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
+ dataremaining--;
+ *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+ tempbuff++;
+ dataremaining--;
+ *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+ tempbuff++;
+ dataremaining--;
+ *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+ tempbuff++;
+ dataremaining--;
+
+ if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
hsd->State= HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
}
-
+
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
hsd->State = HAL_SD_STATE_READY;
-
+
return HAL_OK;
}
else
@@ -724,21 +768,22 @@
* transfer is managed by polling mode.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
- * @param hsd Pointer to SD handle
- * @param pData pointer to the buffer that will contain the data to transmit
- * @param BlockAdd Block Address where data will be written
- * @param NumberOfBlocks Number of SD blocks to write
- * @param Timeout Specify timeout value
+ * @param hsd: Pointer to SD handle
+ * @param pData: pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd: Block Address where data will be written
+ * @param NumberOfBlocks: Number of SD blocks to write
+ * @param Timeout: Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
{
SDMMC_DataInitTypeDef config;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
+ uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
- uint32_t count = 0;
- uint32_t *tempbuff = (uint32_t *)pData;
-
+ uint32_t count, data, dataremaining;
+ uint32_t add = BlockAdd;
+ uint8_t *tempbuff = pData;
+
if(NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
@@ -747,94 +792,108 @@
if(hsd->State == HAL_SD_STATE_READY)
{
- hsd->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+ if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hsd->State = HAL_SD_STATE_BUSY;
-
+
/* Initialize data control register */
- hsd->Instance->DCTRL = 0;
-
+ hsd->Instance->DCTRL = 0U;
+
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
- BlockAdd *= 512;
+ add *= 512U;
}
-
- /* Set Block Size for Card */
+
+ /* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
- /* Write Blocks in Polling mode */
- if(NumberOfBlocks > 1U)
- {
- hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK;
-
- /* Write Multi Block command */
- errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd);
- }
- else
- {
- hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK;
-
- /* Write Single Block command */
- errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd);
- }
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Configure the SD DPSM (Data Path State Machine) */
+
+ /* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = NumberOfBlocks * BLOCKSIZE;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_ENABLE;
- SDMMC_ConfigData(hsd->Instance, &config);
-
+ (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+ /* Write Blocks in Polling mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK;
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
+ }
+ else
+ {
+ hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK;
+
+ /* Write Single Block command */
+ errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
+ }
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ return HAL_ERROR;
+ }
+
/* Write block(s) in polling mode */
+ dataremaining = config.DataLength;
while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE))
+ if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining > 0U))
{
/* Write data to SDMMC Tx FIFO */
for(count = 0U; count < 8U; count++)
{
- SDMMC_WriteFIFO(hsd->Instance, (tempbuff + count));
+ data = (uint32_t)(*tempbuff);
+ tempbuff++;
+ dataremaining--;
+ data |= ((uint32_t)(*tempbuff) << 8U);
+ tempbuff++;
+ dataremaining--;
+ data |= ((uint32_t)(*tempbuff) << 16U);
+ tempbuff++;
+ dataremaining--;
+ data |= ((uint32_t)(*tempbuff) << 24U);
+ tempbuff++;
+ dataremaining--;
+ (void)SDMMC_WriteFIFO(hsd->Instance, &data);
}
- tempbuff += 8U;
}
-
- if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
+
+ if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
return HAL_TIMEOUT;
}
}
-
+
/* Send stop transmission command in case of multiblock write */
if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
- {
+ {
if(hsd->SdCard.CardType != CARD_SECURED)
{
/* Send stop transmission command */
@@ -842,14 +901,15 @@
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
}
}
-
+
/* Get error state */
if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
{
@@ -857,14 +917,16 @@
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR))
@@ -873,14 +935,19 @@
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
-
+ else
+ {
+ /* Nothing to do */
+ }
+
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
hsd->State = HAL_SD_STATE_READY;
-
+
return HAL_OK;
}
else
@@ -891,98 +958,100 @@
}
/**
- * @brief Reads block(s) from a specified address in a card. The Data transfer
- * is managed in interrupt mode.
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed in interrupt mode.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
- * @note You could also check the IT transfer process through the SD Rx
+ * @note You could also check the IT transfer process through the SD Rx
* interrupt event.
- * @param hsd Pointer to SD handle
- * @param pData Pointer to the buffer that will contain the received data
- * @param BlockAdd Block Address from where data is to be read
- * @param NumberOfBlocks Number of blocks to read.
+ * @param hsd: Pointer to SD handle
+ * @param pData: Pointer to the buffer that will contain the received data
+ * @param BlockAdd: Block Address from where data is to be read
+ * @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
+ uint32_t errorstate;
+ uint32_t add = BlockAdd;
+
if(NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
-
+
if(hsd->State == HAL_SD_STATE_READY)
{
- hsd->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+ if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hsd->State = HAL_SD_STATE_BUSY;
-
+
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
-
- hsd->pRxBuffPtr = (uint32_t *)pData;
+
+ hsd->pRxBuffPtr = pData;
hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
-
+
__HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF));
-
+
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
- BlockAdd *= 512U;
+ add *= 512U;
}
-
- /* Configure the SD DPSM (Data Path State Machine) */
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_ENABLE;
- SDMMC_ConfigData(hsd->Instance, &config);
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
+ (void)SDMMC_ConfigData(hsd->Instance, &config);
/* Read Blocks in IT mode */
if(NumberOfBlocks > 1U)
{
hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT);
-
+
/* Read Multi Block command */
- errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd);
+ errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
}
else
{
hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT);
-
+
/* Read Single Block command */
- errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd);
+ errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
}
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
-
+
return HAL_OK;
}
else
@@ -992,99 +1061,101 @@
}
/**
- * @brief Writes block(s) to a specified address in a card. The Data transfer
- * is managed in interrupt mode.
+ * @brief Writes block(s) to a specified address in a card. The Data transfer
+ * is managed in interrupt mode.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
- * @note You could also check the IT transfer process through the SD Tx
- * interrupt event.
- * @param hsd Pointer to SD handle
- * @param pData Pointer to the buffer that will contain the data to transmit
- * @param BlockAdd Block Address where data will be written
- * @param NumberOfBlocks Number of blocks to write
+ * @note You could also check the IT transfer process through the SD Tx
+ * interrupt event.
+ * @param hsd: Pointer to SD handle
+ * @param pData: Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd: Block Address where data will be written
+ * @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
+ uint32_t errorstate;
+ uint32_t add = BlockAdd;
+
if(NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
-
+
if(hsd->State == HAL_SD_STATE_READY)
{
- hsd->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+ if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hsd->State = HAL_SD_STATE_BUSY;
-
+
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
-
- hsd->pTxBuffPtr = (uint32_t *)pData;
+
+ hsd->pTxBuffPtr = pData;
hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
-
+
/* Enable transfer interrupts */
- __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE));
-
+ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE));
+
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
- BlockAdd *= 512U;
+ add *= 512U;
}
-
- /* Set Block Size for Card */
+
+ /* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
+
/* Write Blocks in Polling mode */
if(NumberOfBlocks > 1U)
{
hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT);
-
- /* Write Multi Block command */
- errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd);
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
}
else
{
hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT);
-
- /* Write Single Block command */
- errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd);
+
+ /* Write Single Block command */
+ errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
}
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
-
- /* Configure the SD DPSM (Data Path State Machine) */
+
+ /* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_ENABLE;
- SDMMC_ConfigData(hsd->Instance, &config);
-
+ (void)SDMMC_ConfigData(hsd->Instance, &config);
+
return HAL_OK;
}
else
@@ -1094,111 +1165,122 @@
}
/**
- * @brief Reads block(s) from a specified address in a card. The Data transfer
- * is managed by DMA mode.
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed by DMA mode.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
- * @note You could also check the DMA transfer process through the SD Rx
+ * @note You could also check the DMA transfer process through the SD Rx
* interrupt event.
- * @param hsd Pointer SD handle
- * @param pData Pointer to the buffer that will contain the received data
- * @param BlockAdd Block Address from where data is to be read
- * @param NumberOfBlocks Number of blocks to read.
+ * @param hsd: Pointer SD handle
+ * @param pData: Pointer to the buffer that will contain the received data
+ * @param BlockAdd: Block Address from where data is to be read
+ * @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
+ uint32_t errorstate;
+ uint32_t add = BlockAdd;
+
if(NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
-
+
if(hsd->State == HAL_SD_STATE_READY)
{
- hsd->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+ if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hsd->State = HAL_SD_STATE_BUSY;
-
+
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
-
+
__HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
-
+
/* Set the DMA transfer complete callback */
hsd->hdmarx->XferCpltCallback = SD_DMAReceiveCplt;
-
+
/* Set the DMA error callback */
hsd->hdmarx->XferErrorCallback = SD_DMAError;
-
+
/* Set the DMA Abort callback */
hsd->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA Channel */
- HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4);
-
- /* Enable SD DMA transfer */
- __HAL_SD_DMA_ENABLE(hsd);
-
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
- {
- BlockAdd *= 512U;
- }
-
- /* Configure the SD DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
- config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
- config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- config.DPSM = SDMMC_DPSM_ENABLE;
- SDMMC_ConfigData(hsd->Instance, &config);
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
+ /* Enable the DMA Channel */
+ if(HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK)
{
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
+ __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_DMA;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
- /* Read Blocks in DMA mode */
- if(NumberOfBlocks > 1U)
- {
- hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
-
- /* Read Multi Block command */
- errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd);
- }
else
{
- hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA);
-
- /* Read Single Block command */
- errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd);
- }
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
+ /* Enable SD DMA transfer */
+ __HAL_SD_DMA_ENABLE(hsd);
- return HAL_OK;
+ if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ {
+ add *= 512U;
+ }
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_ENABLE;
+ (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+ /* Read Blocks in DMA mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+
+ /* Read Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+ }
+ else
+ {
+ hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA);
+
+ /* Read Single Block command */
+ errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
+ }
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+ }
}
else
{
@@ -1207,112 +1289,124 @@
}
/**
- * @brief Writes block(s) to a specified address in a card. The Data transfer
- * is managed by DMA mode.
+ * @brief Writes block(s) to a specified address in a card. The Data transfer
+ * is managed by DMA mode.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
- * @note You could also check the DMA transfer process through the SD Tx
+ * @note You could also check the DMA transfer process through the SD Tx
* interrupt event.
- * @param hsd Pointer to SD handle
- * @param pData Pointer to the buffer that will contain the data to transmit
- * @param BlockAdd Block Address where data will be written
- * @param NumberOfBlocks Number of blocks to write
+ * @param hsd: Pointer to SD handle
+ * @param pData: Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd: Block Address where data will be written
+ * @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
+ uint32_t errorstate;
+ uint32_t add = BlockAdd;
+
if(NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
-
+
if(hsd->State == HAL_SD_STATE_READY)
{
- hsd->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+ if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hsd->State = HAL_SD_STATE_BUSY;
-
+
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
-
+
/* Enable SD Error interrupts */
- __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR));
-
+ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR));
+
/* Set the DMA transfer complete callback */
hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt;
-
+
/* Set the DMA error callback */
hsd->hdmatx->XferErrorCallback = SD_DMAError;
-
+
/* Set the DMA Abort callback */
hsd->hdmatx->XferAbortCallback = NULL;
-
+
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
- BlockAdd *= 512U;
+ add *= 512U;
}
-
- /* Set Block Size for Card */
+
+ /* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
+
/* Write Blocks in Polling mode */
if(NumberOfBlocks > 1U)
{
hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
-
- /* Write Multi Block command */
- errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd);
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
}
else
{
hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA);
-
+
/* Write Single Block command */
- errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd);
+ errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
}
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
-
+
/* Enable SDMMC DMA transfer */
__HAL_SD_DMA_ENABLE(hsd);
-
+
/* Enable the DMA Channel */
- HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4);
-
- /* Configure the SD DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
- config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
- config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- config.DPSM = SDMMC_DPSM_ENABLE;
- SDMMC_ConfigData(hsd->Instance, &config);
-
- return HAL_OK;
+ if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK)
+ {
+ __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR));
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_ENABLE;
+ (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+ return HAL_OK;
+ }
}
else
{
@@ -1324,33 +1418,35 @@
* @brief Erases the specified memory area of the given SD card.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
- * @param hsd Pointer to SD handle
- * @param BlockStartAdd Start Block address
- * @param BlockEndAdd End Block address
+ * @param hsd: Pointer to SD handle
+ * @param BlockStartAdd: Start Block address
+ * @param BlockEndAdd: End Block address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
{
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
+ uint32_t errorstate;
+ uint32_t start_add = BlockStartAdd;
+ uint32_t end_add = BlockEndAdd;
+
if(hsd->State == HAL_SD_STATE_READY)
{
- hsd->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if(BlockEndAdd < BlockStartAdd)
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+ if(end_add < start_add)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
-
- if(BlockEndAdd > (hsd->SdCard.LogBlockNbr))
+
+ if(end_add > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hsd->State = HAL_SD_STATE_BUSY;
-
+
/* Check if the card command class supports erase command */
if(((hsd->SdCard.Class) & SDMMC_CCCC_ERASE) == 0U)
{
@@ -1360,62 +1456,62 @@
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
+
if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
+
/* Get start and end block for high capacity cards */
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
- BlockStartAdd *= 512U;
- BlockEndAdd *= 512U;
+ start_add *= 512U;
+ end_add *= 512U;
}
-
+
/* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
if(hsd->SdCard.CardType != CARD_SECURED)
{
/* Send CMD32 SD_ERASE_GRP_START with argument as addr */
- errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, BlockStartAdd);
+ errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, start_add);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
+
/* Send CMD33 SD_ERASE_GRP_END with argument as addr */
- errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, BlockEndAdd);
+ errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, end_add);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
}
-
+
/* Send CMD38 ERASE */
errorstate = SDMMC_CmdErase(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
+
hsd->State = HAL_SD_STATE_READY;
-
+
return HAL_OK;
}
else
@@ -1426,135 +1522,153 @@
/**
* @brief This function handles SD card interrupt request.
- * @param hsd Pointer to SD handle
+ * @param hsd: Pointer to SD handle
* @retval None
*/
void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
{
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
+ uint32_t errorstate;
+ uint32_t context = hsd->Context;
+
/* Check for SDMMC interrupt flags */
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DATAEND) != RESET)
+ if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
{
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND);
+ SD_Read_IT(hsd);
+ }
+
+ else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) != RESET)
+ {
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND);
+
+ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
+ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\
+ SDMMC_IT_RXFIFOHF);
+
+ hsd->Instance->DCTRL &= ~(SDMMC_DCTRL_DTEN);
- __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
- SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
-
- if((hsd->Context & SD_CONTEXT_IT) != RESET)
+ if((context & SD_CONTEXT_IT) != 0U)
{
- if(((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET))
+ if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= errorstate;
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->ErrorCallback(hsd);
#else
HAL_SD_ErrorCallback(hsd);
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
}
-
+
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
hsd->State = HAL_SD_STATE_READY;
- if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET))
+ hsd->Context = SD_CONTEXT_NONE;
+ if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->RxCpltCallback(hsd);
#else
HAL_SD_RxCpltCallback(hsd);
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
else
{
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->TxCpltCallback(hsd);
-#else
+#else
HAL_SD_TxCpltCallback(hsd);
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
}
- else if((hsd->Context & SD_CONTEXT_DMA) != RESET)
+ else if((context & SD_CONTEXT_DMA) != 0U)
{
- if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)
+ if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
{
errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= errorstate;
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->ErrorCallback(hsd);
#else
HAL_SD_ErrorCallback(hsd);
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
}
- if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) == RESET) && ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == RESET))
+ if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == 0U))
{
/* Disable the DMA transfer for transmit request by setting the DMAEN bit
in the SD DCTRL register */
hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN);
-
+
hsd->State = HAL_SD_STATE_READY;
-
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->TxCpltCallback(hsd);
-#else
+#else
HAL_SD_TxCpltCallback(hsd);
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
}
+ else
+ {
+ /* Nothing to do */
+ }
}
-
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXFIFOHE) != RESET)
+
+ else if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
{
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_TXFIFOHE);
-
SD_Write_IT(hsd);
}
-
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXFIFOHF) != RESET)
- {
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXFIFOHF);
-
- SD_Read_IT(hsd);
- }
-
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_TXUNDERR) != RESET)
+
+ else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET)
{
/* Set Error code */
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL) != RESET)
+ if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL) != RESET)
{
- hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
}
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT) != RESET)
+ if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT) != RESET)
{
- hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
}
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXOVERR) != RESET)
+ if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR) != RESET)
{
- hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
+ hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
}
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXUNDERR) != RESET)
+ if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR) != RESET)
{
- hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
+ hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
}
/* Clear All flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
/* Disable all interrupts */
__HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
-
- if((hsd->Context & SD_CONTEXT_DMA) != RESET)
+
+ hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+
+ if((context & SD_CONTEXT_IT) != 0U)
{
- /* Abort the SD DMA Streams */
- if(hsd->hdmatx != NULL)
+ /* Set the SD state to ready to be able to start again the process */
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ hsd->ErrorCallback(hsd);
+#else
+ HAL_SD_ErrorCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ }
+ else if((context & SD_CONTEXT_DMA) != 0U)
+ {
+ /* Abort the SD DMA channel */
+ if(((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
/* Set the DMA Tx abort callback */
hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;
@@ -1564,7 +1678,7 @@
SD_DMATxAbort(hsd->hdmatx);
}
}
- else if(hsd->hdmarx != NULL)
+ else if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
/* Set the DMA Rx abort callback */
hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;
@@ -1578,29 +1692,28 @@
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
hsd->State = HAL_SD_STATE_READY;
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->Context = SD_CONTEXT_NONE;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->AbortCpltCallback(hsd);
#else
HAL_SD_AbortCallback(hsd);
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
}
- else if((hsd->Context & SD_CONTEXT_IT) != RESET)
+ else
{
- /* Set the SD state to ready to be able to start again the process */
- hsd->State = HAL_SD_STATE_READY;
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
- hsd->ErrorCallback(hsd);
-#else
- HAL_SD_ErrorCallback(hsd);
-#endif
+ /* Nothing to do */
}
}
+ else
+ {
+ /* Nothing to do */
+ }
}
/**
* @brief return the SD state
- * @param hsd Pointer to sd handle
+ * @param hsd: Pointer to sd handle
* @retval HAL state
*/
HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd)
@@ -1610,7 +1723,7 @@
/**
* @brief Return the SD error code
-* @param hsd Pointer to a SD_HandleTypeDef structure that contains
+* @param hsd : Pointer to a SD_HandleTypeDef structure that contains
* the configuration information.
* @retval SD Error Code
*/
@@ -1621,10 +1734,10 @@
/**
* @brief Tx Transfer completed callbacks
- * @param hsd Pointer to SD handle
+ * @param hsd: Pointer to SD handle
* @retval None
*/
- __weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
+__weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsd);
@@ -1636,14 +1749,14 @@
/**
* @brief Rx Transfer completed callbacks
- * @param hsd Pointer SD handle
+ * @param hsd: Pointer SD handle
* @retval None
*/
__weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsd);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SD_RxCpltCallback can be implemented in the user file
*/
@@ -1651,51 +1764,51 @@
/**
* @brief SD error callbacks
- * @param hsd Pointer SD handle
+ * @param hsd: Pointer SD handle
* @retval None
*/
__weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsd);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SD_ErrorCallback can be implemented in the user file
- */
+ */
}
/**
* @brief SD Abort callbacks
- * @param hsd Pointer SD handle
+ * @param hsd: Pointer SD handle
* @retval None
*/
__weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsd);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SD_ErrorCallback can be implemented in the user file
- */
+ the HAL_SD_AbortCallback can be implemented in the user file
+ */
}
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
/**
* @brief Register a User SD Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used instead of the weak (surcharged) predefined callback
* @param hsd : SD handle
- * @param CallbackId : Id of the callback to be registered
+ * @param CallbackID : ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID
* @arg @ref HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID
* @arg @ref HAL_SD_ERROR_CB_ID SD Error Callback ID
* @arg @ref HAL_SD_ABORT_CB_ID SD Abort Callback ID
- * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID
- * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
+ * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID
+ * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
* @param pCallback : pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId, pSD_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -1708,10 +1821,10 @@
/* Process locked */
__HAL_LOCK(hsd);
-
+
if(hsd->State == HAL_SD_STATE_READY)
{
- switch (CallbackId)
+ switch (CallbackID)
{
case HAL_SD_TX_CPLT_CB_ID :
hsd->TxCpltCallback = pCallback;
@@ -1733,7 +1846,7 @@
break;
default :
/* Update the error code */
- hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
@@ -1741,7 +1854,7 @@
}
else if (hsd->State == HAL_SD_STATE_RESET)
{
- switch (CallbackId)
+ switch (CallbackID)
{
case HAL_SD_MSP_INIT_CB_ID :
hsd->MspInitCallback = pCallback;
@@ -1751,7 +1864,7 @@
break;
default :
/* Update the error code */
- hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
@@ -1760,7 +1873,7 @@
else
{
/* Update the error code */
- hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
@@ -1772,28 +1885,28 @@
/**
* @brief Unregister a User SD Callback
- * SD Callback is redirected to the weak (surcharged) predefined callback
+ * SD Callback is redirected to the weak (surcharged) predefined callback
* @param hsd : SD handle
- * @param CallbackId : Id of the callback to be unregistered
+ * @param CallbackID : ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID
* @arg @ref HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID
* @arg @ref HAL_SD_ERROR_CB_ID SD Error Callback ID
* @arg @ref HAL_SD_ABORT_CB_ID SD Abort Callback ID
- * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID
- * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
+ * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID
+ * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
* @retval status
*/
-HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId)
+HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hsd);
-
+
if(hsd->State == HAL_SD_STATE_READY)
{
- switch (CallbackId)
+ switch (CallbackID)
{
case HAL_SD_TX_CPLT_CB_ID :
hsd->TxCpltCallback = HAL_SD_TxCpltCallback;
@@ -1815,7 +1928,7 @@
break;
default :
/* Update the error code */
- hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
@@ -1823,7 +1936,7 @@
}
else if (hsd->State == HAL_SD_STATE_RESET)
{
- switch (CallbackId)
+ switch (CallbackID)
{
case HAL_SD_MSP_INIT_CB_ID :
hsd->MspInitCallback = HAL_SD_MspInit;
@@ -1833,7 +1946,7 @@
break;
default :
/* Update the error code */
- hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
@@ -1842,7 +1955,7 @@
else
{
/* Update the error code */
- hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
@@ -1851,21 +1964,21 @@
__HAL_UNLOCK(hsd);
return status;
}
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup SD_Exported_Functions_Group3
- * @brief management functions
+ * @brief management functions
*
-@verbatim
+@verbatim
==============================================================================
##### Peripheral Control functions #####
- ==============================================================================
+ ==============================================================================
[..]
- This subsection provides a set of functions allowing to control the SD card
+ This subsection provides a set of functions allowing to control the SD card
operations and get the related information
@endverbatim
@@ -1875,80 +1988,32 @@
/**
* @brief Returns information the information of the card which are stored on
* the CID register.
- * @param hsd Pointer to SD handle
- * @param pCID Pointer to a HAL_SD_CardCIDTypeDef structure that
- * contains all CID register parameters
+ * @param hsd: Pointer to SD handle
+ * @param pCID: Pointer to a HAL_SD_CardCIDTypeDef structure that
+ * contains all CID register parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID)
{
- uint32_t tmp = 0;
-
- /* Byte 0 */
- tmp = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24);
- pCID->ManufacturerID = tmp;
-
- /* Byte 1 */
- tmp = (uint8_t)((hsd->CID[0] & 0x00FF0000) >> 16);
- pCID->OEM_AppliID = tmp << 8;
-
- /* Byte 2 */
- tmp = (uint8_t)((hsd->CID[0] & 0x000000FF00) >> 8);
- pCID->OEM_AppliID |= tmp;
-
- /* Byte 3 */
- tmp = (uint8_t)(hsd->CID[0] & 0x000000FF);
- pCID->ProdName1 = tmp << 24;
-
- /* Byte 4 */
- tmp = (uint8_t)((hsd->CID[1] & 0xFF000000U) >> 24);
- pCID->ProdName1 |= tmp << 16;
-
- /* Byte 5 */
- tmp = (uint8_t)((hsd->CID[1] & 0x00FF0000) >> 16);
- pCID->ProdName1 |= tmp << 8;
-
- /* Byte 6 */
- tmp = (uint8_t)((hsd->CID[1] & 0x0000FF00) >> 8);
- pCID->ProdName1 |= tmp;
-
- /* Byte 7 */
- tmp = (uint8_t)(hsd->CID[1] & 0x000000FF);
- pCID->ProdName2 = tmp;
-
- /* Byte 8 */
- tmp = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24);
- pCID->ProdRev = tmp;
-
- /* Byte 9 */
- tmp = (uint8_t)((hsd->CID[2] & 0x00FF0000) >> 16);
- pCID->ProdSN = tmp << 24;
-
- /* Byte 10 */
- tmp = (uint8_t)((hsd->CID[2] & 0x0000FF00) >> 8);
- pCID->ProdSN |= tmp << 16;
-
- /* Byte 11 */
- tmp = (uint8_t)(hsd->CID[2] & 0x000000FF);
- pCID->ProdSN |= tmp << 8;
-
- /* Byte 12 */
- tmp = (uint8_t)((hsd->CID[3] & 0xFF000000U) >> 24);
- pCID->ProdSN |= tmp;
-
- /* Byte 13 */
- tmp = (uint8_t)((hsd->CID[3] & 0x00FF0000) >> 16);
- pCID->Reserved1 |= (tmp & 0xF0) >> 4;
- pCID->ManufactDate = (tmp & 0x0F) << 8;
-
- /* Byte 14 */
- tmp = (uint8_t)((hsd->CID[3] & 0x0000FF00) >> 8);
- pCID->ManufactDate |= tmp;
-
- /* Byte 15 */
- tmp = (uint8_t)(hsd->CID[3] & 0x000000FF);
- pCID->CID_CRC = (tmp & 0xFE) >> 1;
- pCID->Reserved2 = 1;
+ pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U);
+
+ pCID->OEM_AppliID = (uint16_t)((hsd->CID[0] & 0x00FFFF00U) >> 8U);
+
+ pCID->ProdName1 = (((hsd->CID[0] & 0x000000FFU) << 24U) | ((hsd->CID[1] & 0xFFFFFF00U) >> 8U));
+
+ pCID->ProdName2 = (uint8_t)(hsd->CID[1] & 0x000000FFU);
+
+ pCID->ProdRev = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24U);
+
+ pCID->ProdSN = (((hsd->CID[2] & 0x00FFFFFFU) << 8U) | ((hsd->CID[3] & 0xFF000000U) >> 24U));
+
+ pCID->Reserved1 = (uint8_t)((hsd->CID[3] & 0x00F00000U) >> 20U);
+
+ pCID->ManufactDate = (uint16_t)((hsd->CID[3] & 0x000FFF00U) >> 8U);
+
+ pCID->CID_CRC = (uint8_t)((hsd->CID[3] & 0x000000FEU) >> 1U);
+
+ pCID->Reserved2 = 1U;
return HAL_OK;
}
@@ -1956,244 +2021,171 @@
/**
* @brief Returns information the information of the card which are stored on
* the CSD register.
- * @param hsd Pointer to SD handle
- * @param pCSD Pointer to a HAL_SD_CardCSDTypeDef structure that
- * contains all CSD register parameters
+ * @param hsd: Pointer to SD handle
+ * @param pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that
+ * contains all CSD register parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD)
{
- uint32_t tmp = 0;
-
- /* Byte 0 */
- tmp = (hsd->CSD[0] & 0xFF000000U) >> 24;
- pCSD->CSDStruct = (uint8_t)((tmp & 0xC0) >> 6);
- pCSD->SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2);
- pCSD->Reserved1 = tmp & 0x03;
-
- /* Byte 1 */
- tmp = (hsd->CSD[0] & 0x00FF0000) >> 16;
- pCSD->TAAC = (uint8_t)tmp;
-
- /* Byte 2 */
- tmp = (hsd->CSD[0] & 0x0000FF00) >> 8;
- pCSD->NSAC = (uint8_t)tmp;
-
- /* Byte 3 */
- tmp = hsd->CSD[0] & 0x000000FF;
- pCSD->MaxBusClkFrec = (uint8_t)tmp;
-
- /* Byte 4 */
- tmp = (hsd->CSD[1] & 0xFF000000U) >> 24;
- pCSD->CardComdClasses = (uint16_t)(tmp << 4);
-
- /* Byte 5 */
- tmp = (hsd->CSD[1] & 0x00FF0000U) >> 16;
- pCSD->CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4);
- pCSD->RdBlockLen = (uint8_t)(tmp & 0x0F);
-
- /* Byte 6 */
- tmp = (hsd->CSD[1] & 0x0000FF00U) >> 8;
- pCSD->PartBlockRead = (uint8_t)((tmp & 0x80) >> 7);
- pCSD->WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6);
- pCSD->RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5);
- pCSD->DSRImpl = (uint8_t)((tmp & 0x10) >> 4);
- pCSD->Reserved2 = 0; /*!< Reserved */
-
+ pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U);
+
+ pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U);
+
+ pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U);
+
+ pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U);
+
+ pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U);
+
+ pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU);
+
+ pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U);
+
+ pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U);
+
+ pCSD->PartBlockRead = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U);
+
+ pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U);
+
+ pCSD->RdBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00002000U) >> 13U);
+
+ pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U);
+
+ pCSD->Reserved2 = 0U; /*!< Reserved */
+
if(hsd->SdCard.CardType == CARD_SDSC)
{
- pCSD->DeviceSize = (tmp & 0x03) << 10;
-
- /* Byte 7 */
- tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU);
- pCSD->DeviceSize |= (tmp) << 2;
-
- /* Byte 8 */
- tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24);
- pCSD->DeviceSize |= (tmp & 0xC0) >> 6;
-
- pCSD->MaxRdCurrentVDDMin = (tmp & 0x38) >> 3;
- pCSD->MaxRdCurrentVDDMax = (tmp & 0x07);
-
- /* Byte 9 */
- tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16);
- pCSD->MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5;
- pCSD->MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2;
- pCSD->DeviceSizeMul = (tmp & 0x03) << 1;
- /* Byte 10 */
- tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8);
- pCSD->DeviceSizeMul |= (tmp & 0x80) >> 7;
-
- hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1) ;
- hsd->SdCard.BlockNbr *= (1 << (pCSD->DeviceSizeMul + 2));
- hsd->SdCard.BlockSize = 1 << (pCSD->RdBlockLen);
+ pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U));
- hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512);
- hsd->SdCard.LogBlockSize = 512;
+ pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U);
+
+ pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U);
+
+ pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U);
+
+ pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U);
+
+ pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U);
+
+ hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1U) ;
+ hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
+ hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
+
+ hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U);
+ hsd->SdCard.LogBlockSize = 512U;
}
else if(hsd->SdCard.CardType == CARD_SDHC_SDXC)
{
/* Byte 7 */
- tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU);
- pCSD->DeviceSize = (tmp & 0x3F) << 16;
-
- /* Byte 8 */
- tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24);
-
- pCSD->DeviceSize |= (tmp << 8);
-
- /* Byte 9 */
- tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16);
-
- pCSD->DeviceSize |= (tmp);
-
- /* Byte 10 */
- tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8);
-
- hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr = (((uint64_t)pCSD->DeviceSize + 1) * 1024);
- hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize = 512;
+ pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U));
+
+ hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U);
+ hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr;
+ hsd->SdCard.BlockSize = 512U;
+ hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize;
}
else
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
- pCSD->EraseGrSize = (tmp & 0x40) >> 6;
- pCSD->EraseGrMul = (tmp & 0x3F) << 1;
-
- /* Byte 11 */
- tmp = (uint8_t)(hsd->CSD[2] & 0x000000FF);
- pCSD->EraseGrMul |= (tmp & 0x80) >> 7;
- pCSD->WrProtectGrSize = (tmp & 0x7F);
-
- /* Byte 12 */
- tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000U) >> 24);
- pCSD->WrProtectGrEnable = (tmp & 0x80) >> 7;
- pCSD->ManDeflECC = (tmp & 0x60) >> 5;
- pCSD->WrSpeedFact = (tmp & 0x1C) >> 2;
- pCSD->MaxWrBlockLen = (tmp & 0x03) << 2;
-
- /* Byte 13 */
- tmp = (uint8_t)((hsd->CSD[3] & 0x00FF0000) >> 16);
- pCSD->MaxWrBlockLen |= (tmp & 0xC0) >> 6;
- pCSD->WriteBlockPaPartial = (tmp & 0x20) >> 5;
- pCSD->Reserved3 = 0;
- pCSD->ContentProtectAppli = (tmp & 0x01);
-
- /* Byte 14 */
- tmp = (uint8_t)((hsd->CSD[3] & 0x0000FF00) >> 8);
- pCSD->FileFormatGrouop = (tmp & 0x80) >> 7;
- pCSD->CopyFlag = (tmp & 0x40) >> 6;
- pCSD->PermWrProtect = (tmp & 0x20) >> 5;
- pCSD->TempWrProtect = (tmp & 0x10) >> 4;
- pCSD->FileFormat = (tmp & 0x0C) >> 2;
- pCSD->ECC = (tmp & 0x03);
-
- /* Byte 15 */
- tmp = (uint8_t)(hsd->CSD[3] & 0x000000FF);
- pCSD->CSD_CRC = (tmp & 0xFE) >> 1;
+
+ pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U);
+
+ pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U);
+
+ pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU);
+
+ pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U);
+
+ pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U);
+
+ pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U);
+
+ pCSD->MaxWrBlockLen= (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U);
+
+ pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U);
+
+ pCSD->Reserved3 = 0;
+
+ pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U);
+
+ pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U);
+
+ pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U);
+
+ pCSD->PermWrProtect = (uint8_t)((hsd->CSD[3] & 0x00002000U) >> 13U);
+
+ pCSD->TempWrProtect = (uint8_t)((hsd->CSD[3] & 0x00001000U) >> 12U);
+
+ pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U);
+
+ pCSD->ECC= (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U);
+
+ pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U);
+
pCSD->Reserved4 = 1;
-
+
return HAL_OK;
}
/**
* @brief Gets the SD status info.
- * @param hsd Pointer to SD handle
- * @param pStatus Pointer to the HAL_SD_CardStatusTypeDef structure that
- * will contain the SD card status information
+ * @param hsd: Pointer to SD handle
+ * @param pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that
+ * will contain the SD card status information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus)
{
- uint32_t tmp = 0;
uint32_t sd_status[16];
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
+ uint32_t errorstate;
+
errorstate = SD_SendSDStatus(hsd, sd_status);
- if(errorstate != HAL_OK)
+ if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
else
{
- /* Byte 0 */
- tmp = (sd_status[0] & 0xC0) >> 6;
- pStatus->DataBusWidth = (uint8_t)tmp;
-
- /* Byte 0 */
- tmp = (sd_status[0] & 0x20) >> 5;
- pStatus->SecuredMode = (uint8_t)tmp;
-
- /* Byte 2 */
- tmp = (sd_status[0] & 0x00FF0000U) >> 16;
- pStatus->CardType = (uint16_t)(tmp << 8);
-
- /* Byte 3 */
- tmp = (sd_status[0] & 0xFF000000U) >> 24;
- pStatus->CardType |= (uint16_t)tmp;
-
- /* Byte 4 */
- tmp = (sd_status[1] & 0xFF);
- pStatus->ProtectedAreaSize = (uint32_t)(tmp << 24);
-
- /* Byte 5 */
- tmp = (sd_status[1] & 0xFF00) >> 8;
- pStatus->ProtectedAreaSize |= (uint32_t)(tmp << 16);
-
- /* Byte 6 */
- tmp = (sd_status[1] & 0xFF0000) >> 16;
- pStatus->ProtectedAreaSize |= (uint32_t)(tmp << 8);
-
- /* Byte 7 */
- tmp = (sd_status[1] & 0xFF000000U) >> 24;
- pStatus->ProtectedAreaSize |= (uint32_t)tmp;
-
- /* Byte 8 */
- tmp = (sd_status[2] & 0xFF);
- pStatus->SpeedClass = (uint8_t)tmp;
-
- /* Byte 9 */
- tmp = (sd_status[2] & 0xFF00) >> 8;
- pStatus->PerformanceMove = (uint8_t)tmp;
-
- /* Byte 10 */
- tmp = (sd_status[2] & 0xF00000) >> 20;
- pStatus->AllocationUnitSize = (uint8_t)tmp;
-
- /* Byte 11 */
- tmp = (sd_status[2] & 0xFF000000U) >> 24;
- pStatus->EraseSize = (uint16_t)(tmp << 8);
-
- /* Byte 12 */
- tmp = (sd_status[3] & 0xFF);
- pStatus->EraseSize |= (uint16_t)tmp;
-
- /* Byte 13 */
- tmp = (sd_status[3] & 0xFC00) >> 10;
- pStatus->EraseTimeout = (uint8_t)tmp;
-
- /* Byte 13 */
- tmp = (sd_status[3] & 0x0300) >> 8;
- pStatus->EraseOffset = (uint8_t)tmp;
+ pStatus->DataBusWidth = (uint8_t)((sd_status[0] & 0xC0U) >> 6U);
+
+ pStatus->SecuredMode = (uint8_t)((sd_status[0] & 0x20U) >> 5U);
+
+ pStatus->CardType = (uint16_t)(((sd_status[0] & 0x00FF0000U) >> 8U) | ((sd_status[0] & 0xFF000000U) >> 24U));
+
+ pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U) | ((sd_status[1] & 0xFF00U) << 8U) |
+ ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U) >> 24U));
+
+ pStatus->SpeedClass = (uint8_t)(sd_status[2] & 0xFFU);
+
+ pStatus->PerformanceMove = (uint8_t)((sd_status[2] & 0xFF00U) >> 8U);
+
+ pStatus->AllocationUnitSize = (uint8_t)((sd_status[2] & 0xF00000U) >> 20U);
+
+ pStatus->EraseSize = (uint16_t)(((sd_status[2] & 0xFF000000U) >> 16U) | (sd_status[3] & 0xFFU));
+
+ pStatus->EraseTimeout = (uint8_t)((sd_status[3] & 0xFC00U) >> 10U);
+
+ pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U);
}
-
+
return HAL_OK;
}
/**
* @brief Gets the SD card info.
- * @param hsd Pointer to SD handle
- * @param pCardInfo Pointer to the HAL_SD_CardInfoTypeDef structure that
- * will contain the SD card status information
+ * @param hsd: Pointer to SD handle
+ * @param pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that
+ * will contain the SD card status information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
@@ -2206,15 +2198,15 @@
pCardInfo->BlockSize = (uint32_t)(hsd->SdCard.BlockSize);
pCardInfo->LogBlockNbr = (uint32_t)(hsd->SdCard.LogBlockNbr);
pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize);
-
+
return HAL_OK;
}
/**
- * @brief Enables wide bus operation for the requested card if supported by
+ * @brief Enables wide bus operation for the requested card if supported by
* card.
- * @param hsd Pointer to SD handle
- * @param WideMode Specifies the SD card wide bus mode
+ * @param hsd: Pointer to SD handle
+ * @param WideMode: Specifies the SD card wide bus mode
* This parameter can be one of the following values:
* @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer
* @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer
@@ -2224,15 +2216,15 @@
HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode)
{
SDMMC_InitTypeDef Init;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
+ uint32_t errorstate;
+
/* Check the parameters */
assert_param(IS_SDMMC_BUS_WIDE(WideMode));
-
- /* Chnage Satte */
+
+ /* Change State */
hsd->State = HAL_SD_STATE_BUSY;
-
- if(hsd->SdCard.CardType != CARD_SECURED)
+
+ if(hsd->SdCard.CardType != CARD_SECURED)
{
if(WideMode == SDMMC_BUS_WIDE_8B)
{
@@ -2241,13 +2233,13 @@
else if(WideMode == SDMMC_BUS_WIDE_4B)
{
errorstate = SD_WideBus_Enable(hsd);
-
+
hsd->ErrorCode |= errorstate;
}
else if(WideMode == SDMMC_BUS_WIDE_1B)
{
errorstate = SD_WideBus_Disable(hsd);
-
+
hsd->ErrorCode |= errorstate;
}
else
@@ -2255,13 +2247,13 @@
/* WideMode is not a valid argument*/
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
}
- }
+ }
else
{
/* MMC Card does not support this feature */
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
}
-
+
if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
@@ -2278,73 +2270,89 @@
Init.BusWide = WideMode;
Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
Init.ClockDiv = hsd->Init.ClockDiv;
- SDMMC_Init(hsd->Instance, Init);
+ (void)SDMMC_Init(hsd->Instance, Init);
}
/* Change State */
hsd->State = HAL_SD_STATE_READY;
-
+
return HAL_OK;
}
-
/**
* @brief Gets the current sd card data state.
- * @param hsd pointer to SD handle
+ * @param hsd: pointer to SD handle
* @retval Card state
*/
HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
{
- HAL_SD_CardStateTypeDef cardstate = HAL_SD_CARD_TRANSFER;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
+ uint32_t cardstate;
+ uint32_t errorstate;
uint32_t resp1 = 0;
-
+
errorstate = SD_SendStatus(hsd, &resp1);
- if(errorstate != HAL_OK)
+ if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= errorstate;
}
- cardstate = (HAL_SD_CardStateTypeDef)((resp1 >> 9) & 0x0F);
-
- return cardstate;
+ cardstate = ((resp1 >> 9U) & 0x0FU);
+
+ return (HAL_SD_CardStateTypeDef)cardstate;
}
/**
* @brief Abort the current transfer and disable the SD.
- * @param hsd pointer to a SD_HandleTypeDef structure that contains
+ * @param hsd: pointer to a SD_HandleTypeDef structure that contains
* the configuration information for SD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)
{
HAL_SD_CardStateTypeDef CardState;
-
+ uint32_t context = hsd->Context;
+
/* DIsable All interrupts */
__HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
-
+
/* Clear All flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-
- if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL))
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+ CLEAR_BIT(hsd->Instance->DCTRL, SDMMC_DCTRL_DTEN);
+
+ if ((context & SD_CONTEXT_DMA) != 0U)
{
/* Disable the SD DMA request */
hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN);
-
- /* Abort the SD DMA Tx Stream */
- if(hsd->hdmatx != NULL)
+
+ /* Abort the SD DMA Tx channel */
+ if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
- HAL_DMA_Abort(hsd->hdmatx);
+ if(HAL_DMA_Abort(hsd->hdmatx) != HAL_OK)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+ }
}
- /* Abort the SD DMA Rx Stream */
- if(hsd->hdmarx != NULL)
+ /* Abort the SD DMA Rx channel */
+ else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
- HAL_DMA_Abort(hsd->hdmarx);
+ if(HAL_DMA_Abort(hsd->hdmarx) != HAL_OK)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+ }
+ }
+ else
+ {
+ /* Nothing to do */
}
}
-
+
hsd->State = HAL_SD_STATE_READY;
+
+ /* Initialize the SD operation */
+ hsd->Context = SD_CONTEXT_NONE;
+
CardState = HAL_SD_GetCardState(hsd);
if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
{
@@ -2359,51 +2367,58 @@
/**
* @brief Abort the current transfer and disable the SD (IT mode).
- * @param hsd pointer to a SD_HandleTypeDef structure that contains
+ * @param hsd: pointer to a SD_HandleTypeDef structure that contains
* the configuration information for SD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
{
HAL_SD_CardStateTypeDef CardState;
-
- /* DIsable All interrupts */
+ uint32_t context = hsd->Context;
+
+ /* Disable All interrupts */
__HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
-
- /* Clear All flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-
- if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL))
+
+ CLEAR_BIT(hsd->Instance->DCTRL, SDMMC_DCTRL_DTEN);
+
+ if ((context & SD_CONTEXT_DMA) != 0U)
{
/* Disable the SD DMA request */
hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN);
-
- /* Abort the SD DMA Tx Stream */
- if(hsd->hdmatx != NULL)
+
+ /* Abort the SD DMA Tx channel */
+ if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
- hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;
+ hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;
if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
{
hsd->hdmatx = NULL;
}
}
- /* Abort the SD DMA Rx Stream */
- if(hsd->hdmarx != NULL)
+ /* Abort the SD DMA Rx channel */
+ else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
- hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;
+ hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;
if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
{
hsd->hdmarx = NULL;
}
}
+ else
+ {
+ /* Nothing to do */
+ }
}
-
/* No transfer ongoing on both DMA channels*/
- if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL))
+ else
{
+ /* Clear All flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
CardState = HAL_SD_GetCardState(hsd);
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
{
hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
@@ -2414,53 +2429,53 @@
}
else
{
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->AbortCpltCallback(hsd);
#else
HAL_SD_AbortCallback(hsd);
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
}
-
+
return HAL_OK;
}
/**
* @}
*/
-
+
/**
* @}
*/
-
-/* Private function ----------------------------------------------------------*/
+
+/* Private function ----------------------------------------------------------*/
/** @addtogroup SD_Private_Functions
* @{
*/
/**
- * @brief DMA SD transmit process complete callback
- * @param hdma DMA handle
+ * @brief DMA SD transmit process complete callback
+ * @param hdma: DMA handle
* @retval None
*/
-static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
-
+
/* Enable DATAEND Interrupt */
__HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DATAEND));
}
/**
- * @brief DMA SD receive process complete callback
- * @param hdma DMA handle
+ * @brief DMA SD receive process complete callback
+ * @param hdma: DMA handle
* @retval None
*/
-static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
+ uint32_t errorstate;
+
/* Send stop command in multiblock write */
if(hsd->Context == (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA))
{
@@ -2475,15 +2490,16 @@
#endif
}
}
-
+
/* Disable the DMA transfer for transmit request by setting the DMAEN bit
in the SD DCTRL register */
hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN);
-
+
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
hsd->RxCpltCallback(hsd);
@@ -2493,35 +2509,39 @@
}
/**
-* @brief DMA SD communication error callback
-* @param hdma DMA handle
-* @retval None
-*/
-static void SD_DMAError(DMA_HandleTypeDef *hdma)
+ * @brief DMA SD communication error callback
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void SD_DMAError(DMA_HandleTypeDef *hdma)
{
SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
HAL_SD_CardStateTypeDef CardState;
-
+ uint32_t RxErrorCode, TxErrorCode;
+
/* if DMA error is FIFO error ignore it */
if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
{
- if((hsd->hdmarx->ErrorCode == HAL_DMA_ERROR_TE) || (hsd->hdmatx->ErrorCode == HAL_DMA_ERROR_TE))
+ RxErrorCode = hsd->hdmarx->ErrorCode;
+ TxErrorCode = hsd->hdmatx->ErrorCode;
+ if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE))
{
/* Clear All flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-
+
/* Disable All interrupts */
__HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
-
+
hsd->ErrorCode |= HAL_SD_ERROR_DMA;
CardState = HAL_SD_GetCardState(hsd);
if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
{
hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
}
-
+
hsd->State= HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
}
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
@@ -2533,115 +2553,102 @@
}
/**
- * @brief DMA SD Tx Abort callback
- * @param hdma DMA handle
+ * @brief DMA SD Tx Abort callback
+ * @param hdma: DMA handle
* @retval None
*/
-static void SD_DMATxAbort(DMA_HandleTypeDef *hdma)
+static void SD_DMATxAbort(DMA_HandleTypeDef *hdma)
{
SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
HAL_SD_CardStateTypeDef CardState;
-
- if(hsd->hdmatx != NULL)
+
+ /* Clear All flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+ CardState = HAL_SD_GetCardState(hsd);
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
{
- hsd->hdmatx = NULL;
+ hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
}
-
- /* All DMA channels are aborted */
- if(hsd->hdmarx == NULL)
+
+ if(hsd->ErrorCode == HAL_SD_ERROR_NONE)
{
- CardState = HAL_SD_GetCardState(hsd);
- hsd->ErrorCode = HAL_SD_ERROR_NONE;
- hsd->State = HAL_SD_STATE_READY;
- if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
- {
- hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
-
- if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
- {
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
- hsd->AbortCpltCallback(hsd);
+ hsd->AbortCpltCallback(hsd);
#else
- HAL_SD_AbortCallback(hsd);
+ HAL_SD_AbortCallback(hsd);
#endif
- }
- else
- {
+ }
+ else
+ {
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
- hsd->ErrorCallback(hsd);
+ hsd->ErrorCallback(hsd);
#else
- HAL_SD_ErrorCallback(hsd);
+ HAL_SD_ErrorCallback(hsd);
#endif
- }
- }
}
}
/**
- * @brief DMA SD Rx Abort callback
- * @param hdma DMA handle
+ * @brief DMA SD Rx Abort callback
+ * @param hdma: DMA handle
* @retval None
*/
-static void SD_DMARxAbort(DMA_HandleTypeDef *hdma)
+static void SD_DMARxAbort(DMA_HandleTypeDef *hdma)
{
SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
HAL_SD_CardStateTypeDef CardState;
-
- if(hsd->hdmarx != NULL)
+
+ /* Clear All flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+ CardState = HAL_SD_GetCardState(hsd);
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
{
- hsd->hdmarx = NULL;
+ hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
}
-
- /* All DMA channels are aborted */
- if(hsd->hdmatx == NULL)
+
+ if(hsd->ErrorCode == HAL_SD_ERROR_NONE)
{
- CardState = HAL_SD_GetCardState(hsd);
- hsd->ErrorCode = HAL_SD_ERROR_NONE;
- hsd->State = HAL_SD_STATE_READY;
- if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
- {
- hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
-
- if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
- {
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
- hsd->AbortCpltCallback(hsd);
+ hsd->AbortCpltCallback(hsd);
#else
- HAL_SD_AbortCallback(hsd);
+ HAL_SD_AbortCallback(hsd);
#endif
- }
- else
- {
+ }
+ else
+ {
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
- hsd->ErrorCallback(hsd);
+ hsd->ErrorCallback(hsd);
#else
- HAL_SD_ErrorCallback(hsd);
+ HAL_SD_ErrorCallback(hsd);
#endif
- }
- }
}
}
-
/**
* @brief Initializes the sd card.
- * @param hsd Pointer to SD handle
+ * @param hsd: Pointer to SD handle
* @retval SD Card error state
*/
static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
{
HAL_SD_CardCSDTypeDef CSD;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
- uint16_t sd_rca = 1;
-
+ uint32_t errorstate;
+ uint16_t sd_rca = 1U;
+
/* Check the power State */
- if(SDMMC_GetPowerState(hsd->Instance) == 0)
+ if(SDMMC_GetPowerState(hsd->Instance) == 0U)
{
/* Power off */
return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
}
-
- if(hsd->SdCard.CardType != CARD_SECURED)
+
+ if(hsd->SdCard.CardType != CARD_SECURED)
{
/* Send CMD2 ALL_SEND_CID */
errorstate = SDMMC_CmdSendCID(hsd->Instance);
@@ -2652,14 +2659,14 @@
else
{
/* Get Card identification number data */
- hsd->CID[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
- hsd->CID[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
- hsd->CID[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
- hsd->CID[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
+ hsd->CID[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+ hsd->CID[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
+ hsd->CID[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
+ hsd->CID[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
}
}
-
- if(hsd->SdCard.CardType != CARD_SECURED)
+
+ if(hsd->SdCard.CardType != CARD_SECURED)
{
/* Send CMD3 SET_REL_ADDR with argument 0 */
/* SD Card publishes its RCA. */
@@ -2669,11 +2676,11 @@
return errorstate;
}
}
- if(hsd->SdCard.CardType != CARD_SECURED)
+ if(hsd->SdCard.CardType != CARD_SECURED)
{
/* Get the SD card RCA */
hsd->SdCard.RelCardAdd = sd_rca;
-
+
/* Send CMD9 SEND_CSD with argument as card's RCA */
errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
if(errorstate != HAL_SD_ERROR_NONE)
@@ -2689,22 +2696,25 @@
hsd->CSD[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
}
}
-
+
/* Get the Card Class */
- hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20);
-
+ hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20U);
+
/* Get CSD parameters */
- HAL_SD_GetCardCSD(hsd, &CSD);
+ if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK)
+ {
+ return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ }
/* Select the Card */
- errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16));
+ errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U));
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
- /* Configure SDMMC peripheral interface */
- SDMMC_Init(hsd->Instance, hsd->Init);
+ /* Configure SDMMC peripheral interface */
+ (void)SDMMC_Init(hsd->Instance, hsd->Init);
/* All cards are initialized */
return HAL_SD_ERROR_NONE;
@@ -2714,163 +2724,151 @@
* @brief Enquires cards about their operating voltage and configures clock
* controls and stores SD information that will be needed in future
* in the SD handle.
- * @param hsd Pointer to SD handle
+ * @param hsd: Pointer to SD handle
* @retval error state
*/
static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
{
- __IO uint32_t count = 0;
- uint32_t response = 0, validvoltage = 0;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
+ __IO uint32_t count = 0U;
+ uint32_t response = 0U, validvoltage = 0U;
+ uint32_t errorstate;
+
/* CMD0: GO_IDLE_STATE */
errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
-
+
/* CMD8: SEND_IF_COND: Command available only on V2.0 cards */
errorstate = SDMMC_CmdOperCond(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->SdCard.CardVersion = CARD_V1_X;
-
- /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
- while(validvoltage == 0)
+ /* CMD0: GO_IDLE_STATE */
+ errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
+ if(errorstate != HAL_SD_ERROR_NONE)
{
- if(count++ == SDMMC_MAX_VOLT_TRIAL)
- {
- return HAL_SD_ERROR_INVALID_VOLTRANGE;
- }
-
- /* SEND CMD55 APP_CMD with RCA as 0 */
- errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
- }
-
- /* Send CMD41 */
- errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_STD_CAPACITY);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
- }
-
- /* Get command response */
- response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
-
- /* Get operating voltage*/
- validvoltage = (((response >> 31) == 1) ? 1 : 0);
+ return errorstate;
}
- /* Card type is SDSC */
- hsd->SdCard.CardType = CARD_SDSC;
+
}
else
{
hsd->SdCard.CardVersion = CARD_V2_X;
-
- /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
- while(validvoltage == 0)
+ }
+
+ if( hsd->SdCard.CardVersion == CARD_V2_X)
+ {
+ /* SEND CMD55 APP_CMD with RCA as 0 */
+ errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
+ if(errorstate != HAL_SD_ERROR_NONE)
{
- if(count++ == SDMMC_MAX_VOLT_TRIAL)
- {
- return HAL_SD_ERROR_INVALID_VOLTRANGE;
- }
-
- /* SEND CMD55 APP_CMD with RCA as 0 */
- errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
-
- /* Send CMD41 */
- errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_HIGH_CAPACITY);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
-
- /* Get command response */
- response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
-
- /* Get operating voltage*/
- validvoltage = (((response >> 31) == 1) ? 1 : 0);
- }
-
- if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
- {
- hsd->SdCard.CardType = CARD_SDHC_SDXC;
- }
- else
- {
- hsd->SdCard.CardType = CARD_SDSC;
+ return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
}
}
-
+ /* SD CARD */
+ /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
+ while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U))
+ {
+ /* SEND CMD55 APP_CMD with RCA as 0 */
+ errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ /* Send CMD41 */
+ errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ }
+
+ /* Get command response */
+ response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+
+ /* Get operating voltage*/
+ validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
+
+ count++;
+ }
+
+ if(count >= SDMMC_MAX_VOLT_TRIAL)
+ {
+ return HAL_SD_ERROR_INVALID_VOLTRANGE;
+ }
+
+ if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
+ {
+ hsd->SdCard.CardType = CARD_SDHC_SDXC;
+ }
+ else
+ {
+ hsd->SdCard.CardType = CARD_SDSC;
+ }
+
+
return HAL_SD_ERROR_NONE;
}
/**
* @brief Turns the SDMMC output signals off.
- * @param hsd Pointer to SD handle
- * @retval HAL status
+ * @param hsd: Pointer to SD handle
+ * @retval None
*/
-static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd)
+static void SD_PowerOFF(SD_HandleTypeDef *hsd)
{
/* Set Power State to OFF */
- SDMMC_PowerState_OFF(hsd->Instance);
-
- return HAL_OK;
+ (void)SDMMC_PowerState_OFF(hsd->Instance);
}
/**
* @brief Send Status info command.
- * @param hsd pointer to SD handle
- * @param pSDstatus Pointer to the buffer that will contain the SD card status
+ * @param hsd: pointer to SD handle
+ * @param pSDstatus: Pointer to the buffer that will contain the SD card status
* SD Status register)
* @retval error state
*/
static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
{
SDMMC_DataInitTypeDef config;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
+ uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
- uint32_t count = 0;
-
+ uint32_t count;
+ uint32_t *pData = pSDstatus;
+
/* Check SD response */
if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
}
-
+
/* Set block size for card if it is not equal to current block size for card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64);
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= HAL_SD_ERROR_NONE;
return errorstate;
}
-
+
/* Send CMD55 */
- errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16));
+ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= HAL_SD_ERROR_NONE;
return errorstate;
}
-
- /* Configure the SD DPSM (Data Path State Machine) */
+
+ /* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = 64;
+ config.DataLength = 64U;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_ENABLE;
- SDMMC_ConfigData(hsd->Instance, &config);
-
+ (void)SDMMC_ConfigData(hsd->Instance, &config);
+
/* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */
errorstate = SDMMC_CmdStatusRegister(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
@@ -2878,26 +2876,25 @@
hsd->ErrorCode |= HAL_SD_ERROR_NONE;
return errorstate;
}
-
+
/* Get status data */
while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))
{
if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
{
- for(count = 0; count < 8; count++)
+ for(count = 0U; count < 8U; count++)
{
- *(pSDstatus + count) = SDMMC_ReadFIFO(hsd->Instance);
+ *pData = SDMMC_ReadFIFO(hsd->Instance);
+ pData++;
}
-
- pSDstatus += 8;
}
-
+
if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
}
-
+
if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
{
return HAL_SD_ERROR_DATA_TIMEOUT;
@@ -2910,88 +2907,92 @@
{
return HAL_SD_ERROR_RX_OVERRUN;
}
+ else
+ {
+ /* Nothing to do */
+ }
while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)))
{
- *pSDstatus = SDMMC_ReadFIFO(hsd->Instance);
- pSDstatus++;
-
+ *pData = SDMMC_ReadFIFO(hsd->Instance);
+ pData++;
+
if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
}
-
+
/* Clear all the static status flags*/
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
return HAL_SD_ERROR_NONE;
}
/**
* @brief Returns the current card's status.
- * @param hsd Pointer to SD handle
- * @param pCardStatus pointer to the buffer that will contain the SD card
- * status (Card Status register)
+ * @param hsd: Pointer to SD handle
+ * @param pCardStatus: pointer to the buffer that will contain the SD card
+ * status (Card Status register)
* @retval error state
*/
static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
{
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
+ uint32_t errorstate;
+
if(pCardStatus == NULL)
{
return HAL_SD_ERROR_PARAM;
}
-
+
/* Send Status command */
- errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16));
- if(errorstate != HAL_OK)
+ errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+ if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
-
+
/* Get SD card status */
*pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
-
+
return HAL_SD_ERROR_NONE;
}
/**
* @brief Enables the SDMMC wide bus mode.
- * @param hsd pointer to SD handle
+ * @param hsd: pointer to SD handle
* @retval error state
*/
static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)
{
- uint32_t scr[2] = {0, 0};
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
+ uint32_t scr[2U] = {0U, 0U};
+ uint32_t errorstate;
+
if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
}
-
+
/* Get SCR Register */
errorstate = SD_FindSCR(hsd, scr);
- if(errorstate != HAL_OK)
+ if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
-
+
/* If requested card supports wide bus operation */
- if((scr[1] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
+ if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
{
/* Send CMD55 APP_CMD with argument as card's RCA.*/
- errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16));
- if(errorstate != HAL_OK)
+ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+ if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
-
+
/* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
- errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2);
- if(errorstate != HAL_OK)
+ errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U);
+ if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
@@ -3006,43 +3007,43 @@
/**
* @brief Disables the SDMMC wide bus mode.
- * @param hsd Pointer to SD handle
+ * @param hsd: Pointer to SD handle
* @retval error state
*/
static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)
{
- uint32_t scr[2] = {0, 0};
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
+ uint32_t scr[2U] = {0U, 0U};
+ uint32_t errorstate;
+
if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
}
-
+
/* Get SCR Register */
errorstate = SD_FindSCR(hsd, scr);
- if(errorstate != HAL_OK)
+ if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
-
+
/* If requested card supports 1 bit mode operation */
- if((scr[1] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
+ if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
{
/* Send CMD55 APP_CMD with argument as card's RCA */
- errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16));
- if(errorstate != HAL_OK)
+ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+ if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
-
+
/* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
- errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0);
- if(errorstate != HAL_OK)
+ errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U);
+ if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
-
+
return HAL_SD_ERROR_NONE;
}
else
@@ -3050,51 +3051,52 @@
return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
}
}
-
-
+
+
/**
* @brief Finds the SD card SCR register value.
- * @param hsd Pointer to SD handle
- * @param pSCR pointer to the buffer that will contain the SCR value
+ * @param hsd: Pointer to SD handle
+ * @param pSCR: pointer to the buffer that will contain the SCR value
* @retval error state
*/
static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
{
SDMMC_DataInitTypeDef config;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
+ uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
- uint32_t index = 0;
- uint32_t tempscr[2] = {0, 0};
-
+ uint32_t index = 0U;
+ uint32_t tempscr[2U] = {0U, 0U};
+ uint32_t *scr = pSCR;
+
/* Set Block Size To 8 Bytes */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8);
- if(errorstate != HAL_OK)
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U);
+ if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* Send CMD55 APP_CMD with argument as card's RCA */
- errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16));
- if(errorstate != HAL_OK)
+ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U));
+ if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = 8;
+ config.DataLength = 8U;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_ENABLE;
- SDMMC_ConfigData(hsd->Instance, &config);
-
+ (void)SDMMC_ConfigData(hsd->Instance, &config);
+
/* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
errorstate = SDMMC_CmdSendSCR(hsd->Instance);
- if(errorstate != HAL_OK)
+ if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
-
+
while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))
{
if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))
@@ -3102,42 +3104,43 @@
*(tempscr + index) = SDMMC_ReadFIFO(hsd->Instance);
index++;
}
-
+
if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
}
-
+
if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
-
+
return HAL_SD_ERROR_DATA_TIMEOUT;
}
else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
-
+
return HAL_SD_ERROR_DATA_CRC_FAIL;
}
else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
-
+
return HAL_SD_ERROR_RX_OVERRUN;
}
else
{
/* No error flag set */
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-
- *(pSCR + 1) = ((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\
- ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24);
-
- *(pSCR) = ((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\
- ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+ *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\
+ ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24));
+ scr++;
+ *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\
+ ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24));
+
}
return HAL_SD_ERROR_NONE;
@@ -3145,50 +3148,80 @@
/**
* @brief Wrap up reading in non-blocking mode.
- * @param hsd pointer to a SD_HandleTypeDef structure that contains
+ * @param hsd: pointer to a SD_HandleTypeDef structure that contains
* the configuration information.
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef SD_Read_IT(SD_HandleTypeDef *hsd)
+static void SD_Read_IT(SD_HandleTypeDef *hsd)
{
- uint32_t count = 0;
- uint32_t* tmp;
+ uint32_t count, data, dataremaining;
+ uint8_t* tmp;
- tmp = (uint32_t*)hsd->pRxBuffPtr;
-
- /* Read data from SDMMC Rx FIFO */
- for(count = 0; count < 8; count++)
+ tmp = hsd->pRxBuffPtr;
+ dataremaining = hsd->RxXferSize;
+
+ if (dataremaining > 0U)
{
- *(tmp + count) = SDMMC_ReadFIFO(hsd->Instance);
+ /* Read data from SDMMC Rx FIFO */
+ for(count = 0U; count < 8U; count++)
+ {
+ data = SDMMC_ReadFIFO(hsd->Instance);
+ *tmp = (uint8_t)(data & 0xFFU);
+ tmp++;
+ dataremaining--;
+ *tmp = (uint8_t)((data >> 8U) & 0xFFU);
+ tmp++;
+ dataremaining--;
+ *tmp = (uint8_t)((data >> 16U) & 0xFFU);
+ tmp++;
+ dataremaining--;
+ *tmp = (uint8_t)((data >> 24U) & 0xFFU);
+ tmp++;
+ dataremaining--;
+ }
+
+ hsd->pRxBuffPtr = tmp;
+ hsd->RxXferSize = dataremaining;
}
-
- hsd->pRxBuffPtr += 8;
-
- return HAL_OK;
}
/**
* @brief Wrap up writing in non-blocking mode.
- * @param hsd pointer to a SD_HandleTypeDef structure that contains
+ * @param hsd: pointer to a SD_HandleTypeDef structure that contains
* the configuration information.
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef SD_Write_IT(SD_HandleTypeDef *hsd)
+static void SD_Write_IT(SD_HandleTypeDef *hsd)
{
- uint32_t count = 0;
- uint32_t* tmp;
-
- tmp = (uint32_t*)hsd->pTxBuffPtr;
-
- /* Write data to SDMMC Tx FIFO */
- for(count = 0; count < 8; count++)
+ uint32_t count, data, dataremaining;
+ uint8_t* tmp;
+
+ tmp = hsd->pTxBuffPtr;
+ dataremaining = hsd->TxXferSize;
+
+ if (dataremaining > 0U)
{
- SDMMC_WriteFIFO(hsd->Instance, (tmp + count));
+ /* Write data to SDMMC Tx FIFO */
+ for(count = 0U; count < 8U; count++)
+ {
+ data = (uint32_t)(*tmp);
+ tmp++;
+ dataremaining--;
+ data |= ((uint32_t)(*tmp) << 8U);
+ tmp++;
+ dataremaining--;
+ data |= ((uint32_t)(*tmp) << 16U);
+ tmp++;
+ dataremaining--;
+ data |= ((uint32_t)(*tmp) << 24U);
+ tmp++;
+ dataremaining--;
+ (void)SDMMC_WriteFIFO(hsd->Instance, &data);
+ }
+
+ hsd->pTxBuffPtr = tmp;
+ hsd->TxXferSize = dataremaining;
}
-
- hsd->pTxBuffPtr += 8;
-
- return HAL_OK;
}
/**
@@ -3205,4 +3238,6 @@
* @}
*/
+#endif /* SDMMC1 */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f7xx_hal_smartcard.c b/Src/stm32f7xx_hal_smartcard.c
index e475985..c964ad0 100644
--- a/Src/stm32f7xx_hal_smartcard.c
+++ b/Src/stm32f7xx_hal_smartcard.c
@@ -192,8 +192,8 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
- * @{
- */
+ * @{
+ */
#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */
#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
@@ -225,7 +225,8 @@
static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
-static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag,
+ FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
@@ -471,7 +472,8 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
+ HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -584,7 +586,8 @@
* @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
+HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
+ HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -728,29 +731,30 @@
(++) HAL_SMARTCARD_RxCpltCallback()
(++) HAL_SMARTCARD_ErrorCallback()
+ [..]
(#) Non-Blocking mode transfers could be aborted using Abort API's :
- (+) HAL_SMARTCARD_Abort()
- (+) HAL_SMARTCARD_AbortTransmit()
- (+) HAL_SMARTCARD_AbortReceive()
- (+) HAL_SMARTCARD_Abort_IT()
- (+) HAL_SMARTCARD_AbortTransmit_IT()
- (+) HAL_SMARTCARD_AbortReceive_IT()
+ (++) HAL_SMARTCARD_Abort()
+ (++) HAL_SMARTCARD_AbortTransmit()
+ (++) HAL_SMARTCARD_AbortReceive()
+ (++) HAL_SMARTCARD_Abort_IT()
+ (++) HAL_SMARTCARD_AbortTransmit_IT()
+ (++) HAL_SMARTCARD_AbortReceive_IT()
(#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
- (+) HAL_SMARTCARD_AbortCpltCallback()
- (+) HAL_SMARTCARD_AbortTransmitCpltCallback()
- (+) HAL_SMARTCARD_AbortReceiveCpltCallback()
+ (++) HAL_SMARTCARD_AbortCpltCallback()
+ (++) HAL_SMARTCARD_AbortTransmitCpltCallback()
+ (++) HAL_SMARTCARD_AbortReceiveCpltCallback()
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
- (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
- and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
- If user wants to abort it, Abort services should be called by user.
- (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
- This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
+ (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
+ If user wants to abort it, Abort services should be called by user.
+ (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
@endverbatim
* @{
@@ -765,7 +769,8 @@
* @param Timeout Timeout duration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout)
{
uint32_t tickstart;
uint8_t *ptmpdata = pData;
@@ -811,7 +816,8 @@
hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU);
ptmpdata++;
}
- if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, Timeout) != HAL_OK)
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart,
+ Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -848,7 +854,8 @@
* @param Timeout Timeout duration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout)
{
uint32_t tickstart;
uint8_t *ptmpdata = pData;
@@ -1059,7 +1066,8 @@
hsmartcard->hdmatx->XferAbortCallback = NULL;
/* Enable the SMARTCARD transmit DMA channel */
- if (HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, Size) == HAL_OK)
+ if (HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR,
+ Size) == HAL_OK)
{
/* Clear the TC flag in the ICR register */
CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF);
@@ -1135,7 +1143,8 @@
hsmartcard->hdmarx->XferAbortCallback = NULL;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, Size) == HAL_OK)
+ if (HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr,
+ Size) == HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
@@ -1188,7 +1197,8 @@
HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR1,
+ (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
/* Disable the SMARTCARD DMA Tx request if enabled */
@@ -1246,7 +1256,9 @@
hsmartcard->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
+ SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@@ -1375,7 +1387,9 @@
hsmartcard->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
+ SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@@ -1403,7 +1417,8 @@
uint32_t abortcplt = 1U;
/* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR1,
+ (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
/* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
@@ -1500,7 +1515,9 @@
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
+ SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@@ -1627,7 +1644,7 @@
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
@@ -1669,7 +1686,9 @@
hsmartcard->RxISR = NULL;
/* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
+ SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@@ -1693,7 +1712,9 @@
hsmartcard->RxISR = NULL;
/* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
+ SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@@ -1731,7 +1752,7 @@
{
/* SMARTCARD in mode Receiver ---------------------------------------------------*/
if (((isrflags & USART_ISR_RXNE) != 0U)
- && ((cr1its & USART_CR1_RXNEIE) != 0U))
+ && ((cr1its & USART_CR1_RXNEIE) != 0U))
{
if (hsmartcard->RxISR != NULL)
{
@@ -1793,7 +1814,7 @@
{
/* SMARTCARD in mode Receiver ---------------------------------------------------*/
if (((isrflags & USART_ISR_RXNE) != 0U)
- && ((cr1its & USART_CR1_RXNEIE) != 0U))
+ && ((cr1its & USART_CR1_RXNEIE) != 0U))
{
if (hsmartcard->RxISR != NULL)
{
@@ -1946,7 +1967,7 @@
/* SMARTCARD in mode Transmitter ------------------------------------------------*/
if (((isrflags & USART_ISR_TXE) != 0U)
- && ((cr1its & USART_CR1_TXEIE) != 0U))
+ && ((cr1its & USART_CR1_TXEIE) != 0U))
{
if (hsmartcard->TxISR != NULL)
{
@@ -1958,7 +1979,7 @@
/* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
if (__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)
{
- if(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)
+ if (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)
{
SMARTCARD_EndTransmit_IT(hsmartcard);
return;
@@ -2095,7 +2116,8 @@
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Return SMARTCARD handle state */
- uint32_t temp1, temp2;
+ uint32_t temp1;
+ uint32_t temp2;
temp1 = (uint32_t)hsmartcard->gState;
temp2 = (uint32_t)hsmartcard->RxState;
@@ -2155,6 +2177,7 @@
uint32_t tmpreg;
SMARTCARD_ClockSourceTypeDef clocksource;
HAL_StatusTypeDef ret = HAL_OK;
+ uint32_t pclk;
/* Check the parameters */
assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
@@ -2177,7 +2200,7 @@
* Configure the Parity and Mode:
* set PS bit according to hsmartcard->Init.Parity value
* set TE and RE bits according to hsmartcard->Init.Mode value */
- tmpreg = (uint32_t) (hsmartcard->Init.Parity | hsmartcard->Init.Mode | hsmartcard->Init.WordLength);
+ tmpreg = (uint32_t)(hsmartcard->Init.Parity | hsmartcard->Init.Mode | hsmartcard->Init.WordLength);
MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
/*-------------------------- USART CR2 Configuration -----------------------*/
@@ -2220,16 +2243,19 @@
switch (clocksource)
{
case SMARTCARD_CLOCKSOURCE_PCLK1:
- tmpreg = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ pclk = HAL_RCC_GetPCLK1Freq();
+ tmpreg = (uint16_t)((pclk + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_PCLK2:
- tmpreg = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ pclk = HAL_RCC_GetPCLK2Freq();
+ tmpreg = (uint16_t)((pclk + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_HSI:
tmpreg = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_SYSCLK:
- tmpreg = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ pclk = HAL_RCC_GetSysClockFreq();
+ tmpreg = (uint16_t)((pclk + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_LSE:
tmpreg = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
@@ -2340,7 +2366,8 @@
if ((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
{
/* Wait until TEACK flag is set */
- if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart,
+ SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
{
/* Timeout occurred */
return HAL_TIMEOUT;
@@ -2367,7 +2394,8 @@
* @param Timeout Timeout duration.
* @retval HAL status
*/
-static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag,
+ FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
while ((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status)
@@ -2491,7 +2519,7 @@
/* Stop SMARTCARD DMA Tx request if ongoing */
if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
{
- if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
{
hsmartcard->TxXferCount = 0U;
SMARTCARD_EndTxTransfer(hsmartcard);
@@ -2570,7 +2598,9 @@
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
+ SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@@ -2617,7 +2647,9 @@
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
+ SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@@ -2677,7 +2709,9 @@
hsmartcard->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
+ SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
diff --git a/Src/stm32f7xx_hal_smartcard_ex.c b/Src/stm32f7xx_hal_smartcard_ex.c
index a5881e2..c919c03 100644
--- a/Src/stm32f7xx_hal_smartcard_ex.c
+++ b/Src/stm32f7xx_hal_smartcard_ex.c
@@ -165,12 +165,6 @@
/** @defgroup SMARTCARDEx_Exported_Functions_Group2 Extended Peripheral IO operation functions
* @brief SMARTCARD Transmit and Receive functions
*
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
-@endverbatim
* @{
*/
@@ -178,28 +172,12 @@
* @}
*/
-/** @defgroup SMARTCARD_Exported_Functions_Group3 Extended Peripheral Peripheral Control functions
- * @brief SMARTCARD control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
-@endverbatim
- * @{
- */
-
/**
* @}
*/
-/**
- * @}
- */
-
-/** @defgroup SMARTCARDEx_Private_Functions SMARTCARD Extended private Functions
+/** @defgroup SMARTCARDEx_Private_Functions SMARTCARD Extended Private Functions
* @{
*/
diff --git a/Src/stm32f7xx_hal_smbus.c b/Src/stm32f7xx_hal_smbus.c
index f23105d..a01d9f8 100644
--- a/Src/stm32f7xx_hal_smbus.c
+++ b/Src/stm32f7xx_hal_smbus.c
@@ -89,12 +89,12 @@
*** Callback registration ***
=============================================
-
+ [..]
The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterAddrCallback()
to register an interrupt callback.
-
+ [..]
Function @ref HAL_SMBUS_RegisterCallback() allows to register following callbacks:
(+) MasterTxCpltCallback : callback for Master transmission end of transfer.
(+) MasterRxCpltCallback : callback for Master reception end of transfer.
@@ -106,9 +106,9 @@
(+) MspDeInitCallback : callback for Msp DeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
-
+ [..]
For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback.
-
+ [..]
Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default
weak function.
@ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
@@ -122,9 +122,9 @@
(+) ErrorCallback : callback for error detection.
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
-
+ [..]
For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback.
-
+ [..]
By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_I2C_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback().
@@ -133,7 +133,7 @@
these callbacks are null (not registered beforehand).
If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
-
+ [..]
Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
@@ -141,7 +141,7 @@
Then, the user first registers the MspInit/MspDeInit user callbacks
using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit()
or @ref HAL_SMBUS_Init() function.
-
+ [..]
When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
diff --git a/Src/stm32f7xx_hal_tim.c b/Src/stm32f7xx_hal_tim.c
index 5165128..b3365d6 100644
--- a/Src/stm32f7xx_hal_tim.c
+++ b/Src/stm32f7xx_hal_tim.c
@@ -98,18 +98,22 @@
*** Callback registration ***
=============================================
+ [..]
The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
+ [..]
Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
@ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
the Callback ID and a pointer to the user callback function.
+ [..]
Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
weak function.
@ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
+ [..]
These functions allow to register/unregister following callbacks:
(+) Base_MspInitCallback : TIM Base Msp Init Callback.
(+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
@@ -140,15 +144,18 @@
(+) BreakCallback : TIM Break Callback.
(+) Break2Callback : TIM Break2 Callback.
+ [..]
By default, after the Init and when the state is HAL_TIM_STATE_RESET
all interrupt callbacks are set to the corresponding weak functions:
examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
+ [..]
Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
functionalities in the Init / DeInit only when these callbacks are null
(not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
+ [..]
Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
Exception done MspInit / MspDeInit that can be registered / unregistered
in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
@@ -156,6 +163,7 @@
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
+ [..]
When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@@ -216,7 +224,7 @@
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef *sSlaveConfig);
+ TIM_SlaveConfigTypeDef *sSlaveConfig);
/**
* @}
*/
@@ -227,8 +235,8 @@
*/
/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
- * @brief Time Base functions
- *
+ * @brief Time Base functions
+ *
@verbatim
==============================================================================
##### Time Base functions #####
@@ -482,11 +490,11 @@
/* Check the parameters */
assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if ((pData == NULL) && (Length > 0U))
{
@@ -559,8 +567,8 @@
*/
/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
- * @brief TIM Output Compare functions
- *
+ * @brief TIM Output Compare functions
+ *
@verbatim
==============================================================================
##### TIM Output Compare functions #####
@@ -929,16 +937,16 @@
*/
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
- uint32_t tmpsmcr;
+ uint32_t tmpsmcr;
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if ((pData == NULL) && (Length > 0U))
{
@@ -1136,8 +1144,8 @@
*/
/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
- * @brief TIM PWM functions
- *
+ * @brief TIM PWM functions
+ *
@verbatim
==============================================================================
##### TIM PWM functions #####
@@ -1513,11 +1521,11 @@
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if ((pData == NULL) && (Length > 0U))
{
@@ -1714,8 +1722,8 @@
*/
/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
- * @brief TIM Input Capture functions
- *
+ * @brief TIM Input Capture functions
+ *
@verbatim
==============================================================================
##### TIM Input Capture functions #####
@@ -2061,11 +2069,11 @@
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if ((pData == NULL) && (Length > 0U))
{
@@ -2249,8 +2257,8 @@
*/
/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
- * @brief TIM One Pulse functions
- *
+ * @brief TIM One Pulse functions
+ *
@verbatim
==============================================================================
##### TIM One Pulse functions #####
@@ -2563,8 +2571,8 @@
*/
/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
- * @brief TIM Encoder functions
- *
+ * @brief TIM Encoder functions
+ *
@verbatim
==============================================================================
##### TIM Encoder functions #####
@@ -2609,15 +2617,15 @@
}
/* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
- assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
- assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
+ assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
+ assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
@@ -2775,7 +2783,7 @@
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Enable the encoder interface channels */
switch (Channel)
@@ -2819,7 +2827,7 @@
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
@@ -2865,7 +2873,7 @@
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Enable the encoder interface channels */
/* Enable the capture compare Interrupts 1 and/or 2 */
@@ -2915,7 +2923,7 @@
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
@@ -2966,16 +2974,17 @@
* @param Length The length of data to be transferred from TIM peripheral to memory.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+ uint32_t *pData2, uint16_t Length)
{
/* Check the parameters */
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
{
@@ -3103,7 +3112,7 @@
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
@@ -3149,8 +3158,8 @@
* @}
*/
/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
- * @brief TIM IRQ handler management
- *
+ * @brief TIM IRQ handler management
+ *
@verbatim
==============================================================================
##### IRQ handler management #####
@@ -3363,8 +3372,8 @@
*/
/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
- * @brief TIM Peripheral Control functions
- *
+ * @brief TIM Peripheral Control functions
+ *
@verbatim
==============================================================================
##### Peripheral Control functions #####
@@ -3738,9 +3747,14 @@
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @note To output a waveform with a minimum delay user can enable the fast
+ * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
+ * output is forced in response to the edge detection on TIx input,
+ * without taking in account the comparison.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
+ uint32_t OutputChannel, uint32_t InputChannel)
{
TIM_OC_InitTypeDef temp1;
@@ -3894,11 +3908,11 @@
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if ((BurstBuffer == NULL) && (BurstLength > 0U))
{
@@ -3941,7 +3955,8 @@
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{
return HAL_ERROR;
}
@@ -3957,7 +3972,8 @@
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{
return HAL_ERROR;
}
@@ -3973,7 +3989,8 @@
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{
return HAL_ERROR;
}
@@ -3989,7 +4006,8 @@
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{
return HAL_ERROR;
}
@@ -4005,7 +4023,8 @@
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{
return HAL_ERROR;
}
@@ -4021,7 +4040,8 @@
htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{
return HAL_ERROR;
}
@@ -4151,8 +4171,8 @@
* @note This function should be used only when BurstLength is equal to DMA data transfer length.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
- uint32_t *BurstBuffer, uint32_t BurstLength)
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
{
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
@@ -4160,11 +4180,11 @@
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if ((BurstBuffer == NULL) && (BurstLength > 0U))
{
@@ -4465,7 +4485,7 @@
/* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
{
- htim->State = HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
return HAL_ERROR;
}
@@ -4780,9 +4800,9 @@
htim->State = HAL_TIM_STATE_BUSY;
- if(TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+ if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
{
- htim->State = HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
return HAL_ERROR;
}
@@ -4810,7 +4830,7 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef *sSlaveConfig)
+ TIM_SlaveConfigTypeDef *sSlaveConfig)
{
/* Check the parameters */
assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
@@ -4821,9 +4841,9 @@
htim->State = HAL_TIM_STATE_BUSY;
- if(TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+ if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
{
- htim->State = HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
return HAL_ERROR;
}
@@ -4913,8 +4933,8 @@
*/
/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
- * @brief TIM Callbacks functions
- *
+ * @brief TIM Callbacks functions
+ *
@verbatim
==============================================================================
##### TIM Callbacks functions #####
@@ -5118,7 +5138,8 @@
* @param pCallback pointer to the callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+ pTIM_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -5578,8 +5599,8 @@
*/
/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
- * @brief TIM Peripheral State functions
- *
+ * @brief TIM Peripheral State functions
+ *
@verbatim
==============================================================================
##### Peripheral State functions #####
@@ -6365,7 +6386,7 @@
* @retval None
*/
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef *sSlaveConfig)
+ TIM_SlaveConfigTypeDef *sSlaveConfig)
{
uint32_t tmpsmcr;
uint32_t tmpccmr1;
diff --git a/Src/stm32f7xx_hal_tim_ex.c b/Src/stm32f7xx_hal_tim_ex.c
index 1895414..7dd91df 100644
--- a/Src/stm32f7xx_hal_tim_ex.c
+++ b/Src/stm32f7xx_hal_tim_ex.c
@@ -73,7 +73,7 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
-*/
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
@@ -397,11 +397,11 @@
/* Check the parameters */
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if (((uint32_t)pData == 0U) && (Length > 0U))
{
@@ -709,11 +709,11 @@
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if (((uint32_t)pData == 0U) && (Length > 0U))
{
@@ -1117,11 +1117,11 @@
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if (((uint32_t)pData == 0U) && (Length > 0U))
{
@@ -1466,7 +1466,8 @@
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource)
{
/* Check the parameters */
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
@@ -1521,7 +1522,8 @@
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource)
{
/* Check the parameters */
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
@@ -1577,7 +1579,8 @@
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource)
{
/* Check the parameters */
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
@@ -1632,7 +1635,7 @@
uint32_t tmpsmcr;
/* Check the parameters */
- assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
@@ -1665,16 +1668,19 @@
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
- /* Reset the MSM Bit */
- tmpsmcr &= ~TIM_SMCR_MSM;
- /* Set master mode */
- tmpsmcr |= sMasterConfig->MasterSlaveMode;
-
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
- /* Update TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ /* Reset the MSM Bit */
+ tmpsmcr &= ~TIM_SMCR_MSM;
+ /* Set master mode */
+ tmpsmcr |= sMasterConfig->MasterSlaveMode;
+
+ /* Update TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+ }
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
@@ -1690,6 +1696,9 @@
* @param htim TIM handle
* @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
* contains the BDTR Register configuration information for the TIM peripheral.
+ * @note Interrupts can be generated when an active level is detected on the
+ * break input, the break 2 input or the system break input. Break
+ * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
@@ -1763,10 +1772,10 @@
{
uint32_t tmporx;
- uint32_t bkin_enable_mask = 0U;
- uint32_t bkin_polarity_mask = 0U;
- uint32_t bkin_enable_bitpos = 0U;
- uint32_t bkin_polarity_bitpos = 0U;
+ uint32_t bkin_enable_mask;
+ uint32_t bkin_polarity_mask;
+ uint32_t bkin_enable_bitpos;
+ uint32_t bkin_polarity_bitpos;
/* Check the parameters */
assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
@@ -1800,11 +1809,19 @@
{
bkin_enable_mask = TIM1_AF1_BKDF1BKE;
bkin_enable_bitpos = 8;
+ bkin_polarity_mask = 0U;
+ bkin_polarity_bitpos = 0U;
break;
}
default:
+ {
+ bkin_enable_mask = 0U;
+ bkin_polarity_mask = 0U;
+ bkin_enable_bitpos = 0U;
+ bkin_polarity_bitpos = 0U;
break;
+ }
}
switch (BreakInput)
@@ -2054,7 +2071,7 @@
*/
/* Private functions ---------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
+/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
* @{
*/
diff --git a/Src/stm32f7xx_hal_uart.c b/Src/stm32f7xx_hal_uart.c
index 9b09bdb..0e557de 100644
--- a/Src/stm32f7xx_hal_uart.c
+++ b/Src/stm32f7xx_hal_uart.c
@@ -326,7 +326,6 @@
huart->gState = HAL_UART_STATE_BUSY;
- /* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
/* Set the UART Communication parameters */
@@ -346,7 +345,6 @@
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
- /* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
@@ -393,7 +391,6 @@
huart->gState = HAL_UART_STATE_BUSY;
- /* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
/* Set the UART Communication parameters */
@@ -416,7 +413,6 @@
/* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
- /* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
@@ -481,7 +477,6 @@
huart->gState = HAL_UART_STATE_BUSY;
- /* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
/* Set the UART Communication parameters */
@@ -507,7 +502,6 @@
/* Set the USART LIN Break detection length. */
MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
- /* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
@@ -567,7 +561,6 @@
huart->gState = HAL_UART_STATE_BUSY;
- /* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
/* Set the UART Communication parameters */
@@ -596,7 +589,6 @@
/* Set the wake up method by setting the WAKE bit in the CR1 register */
MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
- /* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
@@ -622,7 +614,6 @@
huart->gState = HAL_UART_STATE_BUSY;
- /* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
huart->Instance->CR1 = 0x0U;
@@ -645,7 +636,6 @@
huart->gState = HAL_UART_STATE_RESET;
huart->RxState = HAL_UART_STATE_RESET;
- /* Process Unlock */
__HAL_UNLOCK(huart);
return HAL_OK;
@@ -704,18 +694,18 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
+ pUART_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
- /* Update the error code */
huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
- /* Process locked */
+
__HAL_LOCK(huart);
if (huart->gState == HAL_UART_STATE_READY)
@@ -768,10 +758,8 @@
break;
default :
- /* Update the error code */
huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
- /* Return error status */
status = HAL_ERROR;
break;
}
@@ -789,24 +777,19 @@
break;
default :
- /* Update the error code */
huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
- /* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
- /* Update the error code */
huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
- /* Return error status */
status = HAL_ERROR;
}
- /* Release Lock */
__HAL_UNLOCK(huart);
return status;
@@ -837,7 +820,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
__HAL_LOCK(huart);
if (HAL_UART_STATE_READY == huart->gState)
@@ -876,6 +858,12 @@
huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
break;
+#if defined(USART_CR1_UESM)
+ case HAL_UART_WAKEUP_CB_ID :
+ huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */
+ break;
+
+#endif /* USART_CR1_UESM */
case HAL_UART_MSPINIT_CB_ID :
huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */
break;
@@ -885,10 +873,8 @@
break;
default :
- /* Update the error code */
huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
- /* Return error status */
status = HAL_ERROR;
break;
}
@@ -906,24 +892,19 @@
break;
default :
- /* Update the error code */
huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
- /* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
- /* Update the error code */
huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
- /* Return error status */
status = HAL_ERROR;
}
- /* Release Lock */
__HAL_UNLOCK(huart);
return status;
@@ -992,6 +973,11 @@
(+) HAL_UART_AbortCpltCallback()
(+) HAL_UART_AbortTransmitCpltCallback()
(+) HAL_UART_AbortReceiveCpltCallback()
+#if defined(USART_CR1_UESM)
+
+ (#) Wakeup from Stop mode Callback:
+ (+) HAL_UARTEx_WakeupCallback()
+#endif
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
@@ -1013,9 +999,12 @@
/**
* @brief Send an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pData.
* @param huart UART handle.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be sent.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
* @param Timeout Timeout duration.
* @retval HAL status
*/
@@ -1033,7 +1022,6 @@
return HAL_ERROR;
}
- /* Process Locked */
__HAL_LOCK(huart);
huart->ErrorCode = HAL_UART_ERROR_NONE;
@@ -1045,7 +1033,7 @@
huart->TxXferSize = Size;
huart->TxXferCount = Size;
- /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
+ /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
pdata8bits = NULL;
@@ -1057,6 +1045,8 @@
pdata16bits = NULL;
}
+ __HAL_UNLOCK(huart);
+
while (huart->TxXferCount > 0U)
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
@@ -1084,9 +1074,6 @@
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
return HAL_OK;
}
else
@@ -1097,9 +1084,12 @@
/**
* @brief Receive an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pData.
* @param huart UART handle.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @param Timeout Timeout duration.
* @retval HAL status
*/
@@ -1118,7 +1108,6 @@
return HAL_ERROR;
}
- /* Process Locked */
__HAL_LOCK(huart);
huart->ErrorCode = HAL_UART_ERROR_NONE;
@@ -1146,6 +1135,8 @@
pdata16bits = NULL;
}
+ __HAL_UNLOCK(huart);
+
/* as long as data have to be received */
while (huart->RxXferCount > 0U)
{
@@ -1169,9 +1160,6 @@
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
return HAL_OK;
}
else
@@ -1182,9 +1170,12 @@
/**
* @brief Send an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pData.
* @param huart UART handle.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be sent.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
@@ -1197,7 +1188,6 @@
return HAL_ERROR;
}
- /* Process Locked */
__HAL_LOCK(huart);
huart->pTxBuffPtr = pData;
@@ -1218,7 +1208,6 @@
huart->TxISR = UART_TxISR_8BIT;
}
- /* Process Unlocked */
__HAL_UNLOCK(huart);
/* Enable the Transmit Data Register Empty interrupt */
@@ -1234,9 +1223,12 @@
/**
* @brief Receive an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pData.
* @param huart UART handle.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
@@ -1249,7 +1241,6 @@
return HAL_ERROR;
}
- /* Process Locked */
__HAL_LOCK(huart);
huart->pRxBuffPtr = pData;
@@ -1276,7 +1267,6 @@
huart->RxISR = UART_RxISR_8BIT;
}
- /* Process Unlocked */
__HAL_UNLOCK(huart);
/* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
@@ -1292,9 +1282,12 @@
/**
* @brief Send an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pData.
* @param huart UART handle.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be sent.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
@@ -1307,7 +1300,6 @@
return HAL_ERROR;
}
- /* Process Locked */
__HAL_LOCK(huart);
huart->pTxBuffPtr = pData;
@@ -1337,7 +1329,6 @@
/* Set error code to DMA */
huart->ErrorCode = HAL_UART_ERROR_DMA;
- /* Process Unlocked */
__HAL_UNLOCK(huart);
/* Restore huart->gState to ready */
@@ -1349,7 +1340,6 @@
/* Clear the TC flag in the ICR register */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
- /* Process Unlocked */
__HAL_UNLOCK(huart);
/* Enable the DMA transfer for transmit request by setting the DMAT bit
@@ -1368,9 +1358,12 @@
* @brief Receive an amount of data in DMA mode.
* @note When the UART parity is enabled (PCE = 1), the received data contain
* the parity bit (MSB position).
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pData.
* @param huart UART handle.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
@@ -1383,7 +1376,6 @@
return HAL_ERROR;
}
- /* Process Locked */
__HAL_LOCK(huart);
huart->pRxBuffPtr = pData;
@@ -1412,7 +1404,6 @@
/* Set error code to DMA */
huart->ErrorCode = HAL_UART_ERROR_DMA;
- /* Process Unlocked */
__HAL_UNLOCK(huart);
/* Restore huart->gState to ready */
@@ -1421,7 +1412,6 @@
return HAL_ERROR;
}
}
- /* Process Unlocked */
__HAL_UNLOCK(huart);
/* Enable the UART Parity Error Interrupt */
@@ -1452,7 +1442,6 @@
const HAL_UART_StateTypeDef gstate = huart->gState;
const HAL_UART_StateTypeDef rxstate = huart->RxState;
- /* Process Locked */
__HAL_LOCK(huart);
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
@@ -1472,7 +1461,6 @@
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
}
- /* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
@@ -1485,7 +1473,6 @@
*/
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
{
- /* Process Locked */
__HAL_LOCK(huart);
if (huart->gState == HAL_UART_STATE_BUSY_TX)
@@ -1506,7 +1493,6 @@
SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
}
- /* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
@@ -1591,7 +1577,7 @@
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
{
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
@@ -1663,7 +1649,6 @@
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
- /* Reset Handle ErrorCode to No Error */
huart->ErrorCode = HAL_UART_ERROR_NONE;
return HAL_OK;
@@ -1680,7 +1665,7 @@
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
{
/* Disable TXEIE and TCIE interrupts */
@@ -1732,7 +1717,7 @@
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
@@ -1792,7 +1777,7 @@
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
{
uint32_t abortcplt = 1U;
@@ -1931,7 +1916,7 @@
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
{
/* Disable interrupts */
@@ -2015,7 +2000,7 @@
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
@@ -2110,7 +2095,7 @@
uint32_t errorcode;
/* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
if (errorflags == 0U)
{
/* UART in mode Receiver ---------------------------------------------------*/
@@ -2164,10 +2149,18 @@
huart->ErrorCode |= HAL_UART_ERROR_ORE;
}
- /* Call UART Error Call back function if need be --------------------------*/
+ /* UART Receiver Timeout interrupt occurred ---------------------------------*/
+ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_RTO;
+ }
+
+ /* Call UART Error Call back function if need be ----------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
{
- /* UART in mode Receiver ---------------------------------------------------*/
+ /* UART in mode Receiver --------------------------------------------------*/
if (((isrflags & USART_ISR_RXNE) != 0U)
&& ((cr1its & USART_CR1_RXNEIE) != 0U))
{
@@ -2177,11 +2170,14 @@
}
}
- /* If Overrun error occurs, or if any error occurs in DMA mode reception,
- consider error as blocking */
+ /* If Error is to be considered as blocking :
+ - Receiver Timeout error in Reception
+ - Overrun error in Reception
+ - any error occurs in DMA mode reception
+ */
errorcode = huart->ErrorCode;
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
- ((errorcode & HAL_UART_ERROR_ORE) != 0U))
+ ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
{
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
@@ -2249,6 +2245,26 @@
return;
} /* End if some error occurs */
+#if defined(USART_CR1_UESM)
+
+ /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
+ if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
+
+ /* UART Rx state is not reset as a reception process might be ongoing.
+ If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Wakeup Callback */
+ huart->WakeupCallback(huart);
+#else
+ /* Call legacy weak Wakeup Callback */
+ HAL_UARTEx_WakeupCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ return;
+ }
+#endif /* USART_CR1_UESM */
/* UART in mode Transmitter ------------------------------------------------*/
if (((isrflags & USART_ISR_TXE) != 0U)
@@ -2390,6 +2406,23 @@
*/
}
+#if defined(USART_CR1_UESM)
+/**
+ * @brief UART wakeup from Stop mode callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UARTEx_WakeupCallback can be implemented in the user file.
+ */
+}
+
+#endif /* USART_CR1_UESM */
/**
* @}
*/
@@ -2403,6 +2436,9 @@
===============================================================================
[..]
This subsection provides a set of functions allowing to control the UART.
+ (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly
+ (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature
+ (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature
(+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
(+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
(+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
@@ -2417,6 +2453,82 @@
*/
/**
+ * @brief Update on the fly the receiver timeout value in RTOR register.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @param TimeoutValue receiver timeout value in number of baud blocks. The timeout
+ * value must be less or equal to 0x0FFFFFFFF.
+ * @retval None
+ */
+void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue)
+{
+ assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue));
+ MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue);
+}
+
+/**
+ * @brief Enable the UART receiver timeout feature.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart)
+{
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Set the USART RTOEN bit */
+ SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Disable the UART receiver timeout feature.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart)
+{
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Clear the USART RTOEN bit */
+ CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
* @brief Enable UART in mute mode (does not mean UART enters mute mode;
* to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
* @param huart UART handle.
@@ -2424,7 +2536,6 @@
*/
HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
{
- /* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
@@ -2445,7 +2556,6 @@
*/
HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
{
- /* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
@@ -2476,7 +2586,6 @@
*/
HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
{
- /* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
@@ -2488,7 +2597,6 @@
huart->gState = HAL_UART_STATE_READY;
- /* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
@@ -2501,7 +2609,6 @@
*/
HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
{
- /* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
@@ -2513,7 +2620,6 @@
huart->gState = HAL_UART_STATE_READY;
- /* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
@@ -2530,7 +2636,6 @@
/* Check the parameters */
assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
- /* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
@@ -2540,7 +2645,6 @@
huart->gState = HAL_UART_STATE_READY;
- /* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
@@ -2551,8 +2655,8 @@
*/
/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
- * @brief UART Peripheral State functions
- *
+ * @brief UART Peripheral State functions
+ *
@verbatim
==============================================================================
##### Peripheral State and Error functions #####
@@ -2574,7 +2678,8 @@
*/
HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
{
- uint32_t temp1, temp2;
+ uint32_t temp1;
+ uint32_t temp2;
temp1 = huart->gState;
temp2 = huart->RxState;
@@ -2586,7 +2691,7 @@
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART.
* @retval UART Error Code
-*/
+ */
uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
{
return huart->ErrorCode;
@@ -2620,6 +2725,9 @@
huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+#if defined(USART_CR1_UESM)
+ huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */
+#endif /* USART_CR1_UESM */
}
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
@@ -2636,6 +2744,7 @@
UART_ClockSourceTypeDef clocksource;
uint32_t usartdiv = 0x00000000U;
HAL_StatusTypeDef ret = HAL_OK;
+ uint32_t pclk;
/* Check the parameters */
assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
@@ -2683,21 +2792,23 @@
switch (clocksource)
{
case UART_CLOCKSOURCE_PCLK1:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
+ pclk = HAL_RCC_GetPCLK1Freq();
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_PCLK2:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
+ pclk = HAL_RCC_GetPCLK2Freq();
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_HSI:
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_SYSCLK:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
+ pclk = HAL_RCC_GetSysClockFreq();
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_LSE:
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
break;
- case UART_CLOCKSOURCE_UNDEFINED:
default:
ret = HAL_ERROR;
break;
@@ -2720,21 +2831,23 @@
switch (clocksource)
{
case UART_CLOCKSOURCE_PCLK1:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
+ pclk = HAL_RCC_GetPCLK1Freq();
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_PCLK2:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
+ pclk = HAL_RCC_GetPCLK2Freq();
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_HSI:
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_SYSCLK:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
+ pclk = HAL_RCC_GetSysClockFreq();
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_LSE:
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
break;
- case UART_CLOCKSOURCE_UNDEFINED:
default:
ret = HAL_ERROR;
break;
@@ -2858,12 +2971,24 @@
return HAL_TIMEOUT;
}
}
+#if defined(USART_ISR_REACK)
+
+ /* Check if the Receiver is enabled */
+ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+#endif
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
- /* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
@@ -2878,7 +3003,8 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
@@ -2895,11 +3021,32 @@
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
- /* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_TIMEOUT;
}
+
+ if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
+ {
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
+ {
+ /* Clear Receiver Timeout flag*/
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ErrorCode = HAL_UART_ERROR_RTO;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
return HAL_OK;
diff --git a/Src/stm32f7xx_hal_uart_ex.c b/Src/stm32f7xx_hal_uart_ex.c
index 254fe25..cdc535c 100644
--- a/Src/stm32f7xx_hal_uart_ex.c
+++ b/Src/stm32f7xx_hal_uart_ex.c
@@ -57,6 +57,9 @@
/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
* @{
*/
+#if defined(USART_CR1_UESM)
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+#endif /* USART_CR1_UESM */
/**
* @}
*/
@@ -144,7 +147,8 @@
* oversampling rate).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
+ uint32_t DeassertionTime)
{
uint32_t temp;
@@ -224,42 +228,74 @@
* @}
*/
-/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions
- * @brief Extended functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- This subsection provides a set of Wakeup and FIFO mode related callback functions.
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @}
- */
/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
* @brief Extended Peripheral Control functions
- *
+ *
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..] This section provides the following functions:
+ (+) HAL_UARTEx_EnableClockStopMode() API enables the UART clock (HSI or LSE only) during stop mode
+ (+) HAL_UARTEx_DisableClockStopMode() API disables the above functionality
(+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
detection length to more than 4 bits for multiprocessor address mark wake up.
+#if defined(USART_CR1_UESM)
+ (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
+ trigger: address match, Start Bit detection or RXNE bit status.
+ (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
+ (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
+#endif
@endverbatim
* @{
*/
+#if defined(USART_CR3_UCESM)
+/**
+ * @brief Keep UART Clock enabled when in Stop Mode.
+ * @note When the USART clock source is configured to be LSE or HSI, it is possible to keep enabled
+ * this clock during STOP mode by setting the UCESM bit in USART_CR3 control register.
+ * @note When LPUART is used to wakeup from stop with LSE is selected as LPUART clock source,
+ * and desired baud rate is 9600 baud, the bit UCESM bit in LPUART_CR3 control register must be set.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+ /* Set UCESM bit */
+ SET_BIT(huart->Instance->CR3, USART_CR3_UCESM);
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable UART Clock when in Stop Mode.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ /* Clear UCESM bit */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_UCESM);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+#endif /* USART_CR3_UCESM */
/**
* @brief By default in multiprocessor mode, when the wake up method is set
* to address mark, the UART handles only 4-bit long addresses detection;
@@ -299,8 +335,108 @@
return (UART_CheckIdleState(huart));
}
+#if defined(USART_CR1_UESM)
+/**
+ * @brief Set Wakeup from Stop mode interrupt flag selection.
+ * @note It is the application responsibility to enable the interrupt used as
+ * usart_wkup interrupt source before entering low-power mode.
+ * @param huart UART handle.
+ * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_WAKEUP_ON_ADDRESS
+ * @arg @ref UART_WAKEUP_ON_STARTBIT
+ * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tickstart;
+ /* check the wake-up from stop mode UART instance */
+ assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
+ /* check the wake-up selection parameter */
+ assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the wake-up selection scheme */
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
+
+ if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
+ {
+ UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ /* Wait until REACK flag is set */
+ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ {
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Initialize the UART State */
+ huart->gState = HAL_UART_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return status;
+}
+
+/**
+ * @brief Enable UART Stop Mode.
+ * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ /* Set UESM bit */
+ SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable UART Stop Mode.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ /* Clear UESM bit */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+#endif /* USART_CR1_UESM */
/**
* @}
*/
@@ -312,6 +448,25 @@
/** @addtogroup UARTEx_Private_Functions
* @{
*/
+#if defined(USART_CR1_UESM)
+
+/**
+ * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
+ * @param huart UART handle.
+ * @param WakeUpSelection UART wake up from stop mode parameters.
+ * @retval None
+ */
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+ assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
+
+ /* Set the USART address length */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
+
+ /* Set the USART address node */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
+}
+#endif /* USART_CR1_UESM */
/**
* @}
diff --git a/Src/stm32f7xx_hal_usart.c b/Src/stm32f7xx_hal_usart.c
index a8969da..92f27ab 100644
--- a/Src/stm32f7xx_hal_usart.c
+++ b/Src/stm32f7xx_hal_usart.c
@@ -181,7 +181,8 @@
static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout);
static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
static void USART_TxISR_8BIT(USART_HandleTypeDef *husart);
@@ -303,14 +304,15 @@
/* In Synchronous mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register
- - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
+ - HDSEL, SCEN and IREN bits in the USART_CR3 register.
+ */
husart->Instance->CR2 &= ~USART_CR2_LINEN;
husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
/* Enable the Peripheral */
__HAL_USART_ENABLE(husart);
- /* TEACK to check before moving husart->State to Ready */
+ /* TEACK and/or REACK to check before moving husart->State to Ready */
return (USART_CheckIdleState(husart));
}
@@ -406,7 +408,8 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
+ */
-HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
+ pUSART_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -701,9 +704,12 @@
/**
* @brief Simplex send an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pTxData.
* @param husart USART handle.
- * @param pTxData Pointer to data buffer.
- * @param Size Amount of data to be sent.
+ * @param pTxData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
* @param Timeout Timeout duration.
* @retval HAL status
*/
@@ -794,10 +800,13 @@
/**
* @brief Receive an amount of data in blocking mode.
- * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pRxData.
* @param husart USART handle.
- * @param pRxData Pointer to data buffer.
- * @param Size Amount of data to be received.
+ * @param pRxData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @param Timeout Timeout duration.
* @retval HAL status
*/
@@ -896,14 +905,18 @@
/**
* @brief Full-Duplex Send and Receive an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+ * of u16 available through pTxData and through pRxData.
* @param husart USART handle.
- * @param pTxData pointer to TX data buffer.
- * @param pRxData pointer to RX data buffer.
- * @param Size amount of data to be sent (same amount to be received).
+ * @param pTxData pointer to TX data buffer (u8 or u16 data elements).
+ * @param pRxData pointer to RX data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received).
* @param Timeout Timeout duration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size, uint32_t Timeout)
{
uint8_t *prxdata8bits;
uint16_t *prxdata16bits;
@@ -1041,9 +1054,12 @@
/**
* @brief Send an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pTxData.
* @param husart USART handle.
- * @param pTxData pointer to data buffer.
- * @param Size amount of data to be sent.
+ * @param pTxData pointer to data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
@@ -1100,10 +1116,13 @@
/**
* @brief Receive an amount of data in interrupt mode.
- * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pRxData.
* @param husart USART handle.
- * @param pRxData pointer to data buffer.
- * @param Size amount of data to be received.
+ * @param pRxData pointer to data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
@@ -1168,13 +1187,17 @@
/**
* @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+ * of u16 available through pTxData and through pRxData.
* @param husart USART handle.
- * @param pTxData pointer to TX data buffer.
- * @param pRxData pointer to RX data buffer.
- * @param Size amount of data to be sent (same amount to be received).
+ * @param pTxData pointer to TX data buffer (u8 or u16 data elements).
+ * @param pRxData pointer to RX data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size)
{
if (husart->State == HAL_USART_STATE_READY)
@@ -1235,9 +1258,12 @@
/**
* @brief Send an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pTxData.
* @param husart USART handle.
- * @param pTxData pointer to data buffer.
- * @param Size amount of data to be sent.
+ * @param pTxData pointer to data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
@@ -1316,10 +1342,13 @@
* @brief Receive an amount of data in DMA mode.
* @note When the USART parity is enabled (PCE = 1), the received data contain
* the parity bit (MSB position).
- * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
+ * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pRxData.
* @param husart USART handle.
- * @param pRxData pointer to data buffer.
- * @param Size amount of data to be received.
+ * @param pRxData pointer to data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
@@ -1428,13 +1457,17 @@
/**
* @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
* @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+ * of u16 available through pTxData and through pRxData.
* @param husart USART handle.
- * @param pTxData pointer to TX data buffer.
- * @param pRxData pointer to RX data buffer.
- * @param Size amount of data to be received/sent.
+ * @param pTxData pointer to TX data buffer (u8 or u16 data elements).
+ * @param pRxData pointer to RX data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be received/sent.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size)
{
HAL_StatusTypeDef status;
uint32_t *tmp;
@@ -1700,7 +1733,7 @@
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
{
CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
@@ -1789,7 +1822,7 @@
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
{
uint32_t abortcplt = 1U;
@@ -1924,7 +1957,7 @@
uint32_t errorcode;
/* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
if (errorflags == 0U)
{
/* USART in mode Receiver ---------------------------------------------------*/
@@ -1978,6 +2011,14 @@
husart->ErrorCode |= HAL_USART_ERROR_ORE;
}
+ /* USART Receiver Timeout interrupt occurred ---------------------------------*/
+ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_RTOF);
+
+ husart->ErrorCode |= HAL_USART_ERROR_RTO;
+ }
+
/* Call USART Error Call back function if need be --------------------------*/
if (husart->ErrorCode != HAL_USART_ERROR_NONE)
@@ -2206,8 +2247,8 @@
*/
/** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions
- * @brief USART Peripheral State and Error functions
- *
+ * @brief USART Peripheral State and Error functions
+ *
@verbatim
==============================================================================
##### Peripheral State and Error functions #####
@@ -2253,8 +2294,8 @@
*/
/** @defgroup USART_Private_Functions USART Private Functions
- * @{
- */
+ * @{
+ */
/**
* @brief Initialize the callbacks to their default values.
@@ -2591,7 +2632,8 @@
* @param Timeout timeout duration.
* @retval HAL status
*/
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
@@ -2625,6 +2667,7 @@
HAL_StatusTypeDef ret = HAL_OK;
uint16_t brrtemp;
uint32_t usartdiv = 0x00000000;
+ uint32_t pclk;
/* Check the parameters */
assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
@@ -2666,16 +2709,19 @@
switch (clocksource)
{
case USART_CLOCKSOURCE_PCLK1:
- usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate));
+ pclk = HAL_RCC_GetPCLK1Freq();
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate));
break;
case USART_CLOCKSOURCE_PCLK2:
- usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate));
+ pclk = HAL_RCC_GetPCLK2Freq();
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate));
break;
case USART_CLOCKSOURCE_HSI:
usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate));
break;
case USART_CLOCKSOURCE_SYSCLK:
- usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), husart->Init.BaudRate));
+ pclk = HAL_RCC_GetSysClockFreq();
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate));
break;
case USART_CLOCKSOURCE_LSE:
usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate));
@@ -2730,6 +2776,18 @@
return HAL_TIMEOUT;
}
}
+#if defined(USART_ISR_REACK)
+ /* Check if the Receiver is enabled */
+ if ((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+#endif
/* Initialize the USART state*/
husart->State = HAL_USART_STATE_READY;
diff --git a/Src/stm32f7xx_hal_wwdg.c b/Src/stm32f7xx_hal_wwdg.c
index 5067af4..82af5e2 100644
--- a/Src/stm32f7xx_hal_wwdg.c
+++ b/Src/stm32f7xx_hal_wwdg.c
@@ -32,17 +32,19 @@
(++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
(++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
(+) Typical values:
- (++) Counter min (T[5;0] = 0x00) @56MHz (PCLK1) with zero prescaler:
- max timeout before reset: ~73.14µs
- (++) Counter max (T[5;0] = 0x3F) @56MHz (PCLK1) with prescaler dividing by 128:
- max timeout before reset: ~599.18ms
+ (++) Counter min (T[5;0] = 0x00) @54MHz (PCLK1) with zero prescaler:
+ max timeout before reset: approximately 75.85µs
+ (++) Counter max (T[5;0] = 0x3F) @54MHz (PCLK1) with prescaler dividing by 8:
+ max timeout before reset: approximately 38.83ms
==============================================================================
##### How to use this driver #####
==============================================================================
- [..]
+
*** Common driver usage ***
===========================
+
+ [..]
(+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
(+) Set the WWDG prescaler, refresh window and counter value
using HAL_WWDG_Init() function.
@@ -59,9 +61,10 @@
HAL_WWDG_Refresh() function. This operation must occur only when
the counter is lower than the refresh window value already programmed.
- [..]
*** Callback registration ***
=============================
+
+ [..]
The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
the user to configure dynamically the driver callbacks. Use Functions
@ref HAL_WWDG_RegisterCallback() to register a user callback.
@@ -80,13 +83,15 @@
(++) EwiCallback : callback for Early WakeUp Interrupt.
(++) MspInitCallback : WWDG MspInit.
+ [..]
When calling @ref HAL_WWDG_Init function, callbacks are reset to the
- corresponding legacy weak (surcharged) functions:
+ corresponding legacy weak (surcharged) functions:
@ref HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
not been registered before.
+ [..]
When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registering feature is not available
+ not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
*** WWDG HAL driver macros list ***
@@ -138,8 +143,8 @@
*/
/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions.
- *
+ * @brief Initialization and Configuration functions.
+ *
@verbatim
==============================================================================
##### Initialization and Configuration functions #####
@@ -178,12 +183,12 @@
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
/* Reset Callback pointers */
- if(hwwdg->EwiCallback == NULL)
+ if (hwwdg->EwiCallback == NULL)
{
hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
}
- if(hwwdg->MspInitCallback == NULL)
+ if (hwwdg->MspInitCallback == NULL)
{
hwwdg->MspInitCallback = HAL_WWDG_MspInit;
}
@@ -242,13 +247,13 @@
{
HAL_StatusTypeDef status = HAL_OK;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
status = HAL_ERROR;
}
else
{
- switch(CallbackID)
+ switch (CallbackID)
{
case HAL_WWDG_EWI_CB_ID:
hwwdg->EwiCallback = pCallback;
@@ -270,7 +275,7 @@
/**
* @brief Unregister a WWDG Callback
- * WWDG Callback is redirected to the weak (surcharged) predefined callback
+ * WWDG Callback is redirected to the weak (surcharged) predefined callback
* @param hwwdg WWDG handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -282,7 +287,7 @@
{
HAL_StatusTypeDef status = HAL_OK;
- switch(CallbackID)
+ switch (CallbackID)
{
case HAL_WWDG_EWI_CB_ID:
hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
@@ -306,8 +311,8 @@
*/
/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
- *
+ * @brief IO operation functions
+ *
@verbatim
==============================================================================
##### IO operation functions #####
diff --git a/Src/stm32f7xx_ll_gpio.c b/Src/stm32f7xx_ll_gpio.c
index ba55800..86f9996 100644
--- a/Src/stm32f7xx_ll_gpio.c
+++ b/Src/stm32f7xx_ll_gpio.c
@@ -220,9 +220,6 @@
if (currentpin)
{
- /* Pin Mode configuration */
- LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
-
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
{
/* Check Speed mode parameters */
@@ -230,6 +227,12 @@
/* Speed mode configuration */
LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
+
+ /* Check Output mode parameters */
+ assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
+
+ /* Output mode configuration*/
+ LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
}
/* Pull-up Pull down resistor configuration*/
@@ -250,19 +253,11 @@
LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
}
}
+ /* Pin Mode configuration */
+ LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
}
pinpos++;
}
-
- if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
- {
- /* Check Output mode parameters */
- assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
-
- /* Output mode configuration*/
- LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
-
- }
return (SUCCESS);
}
diff --git a/Src/stm32f7xx_ll_lptim.c b/Src/stm32f7xx_ll_lptim.c
index c4076e0..63c8a55 100644
--- a/Src/stm32f7xx_ll_lptim.c
+++ b/Src/stm32f7xx_ll_lptim.c
@@ -21,18 +21,20 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_ll_lptim.h"
#include "stm32f7xx_ll_bus.h"
+#include "stm32f7xx_ll_rcc.h"
+
#ifdef USE_FULL_ASSERT
- #include "stm32_assert.h"
+#include "stm32_assert.h"
#else
- #define assert_param(expr) ((void)0U)
+#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F7xx_LL_Driver
* @{
*/
-#if defined (LPTIM1) || defined (LPTIM2)
+#if defined (LPTIM1)
/** @addtogroup LPTIM_LL
* @{
@@ -46,28 +48,35 @@
* @{
*/
#define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
- || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
+ || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
#define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
#define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
- || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
+ || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
#define IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \
- || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))
+ || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
+ * @{
+ */
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
/** @addtogroup LPTIM_LL_Exported_Functions
* @{
@@ -84,30 +93,23 @@
* - SUCCESS: LPTIMx registers are de-initialized
* - ERROR: invalid LPTIMx instance
*/
-ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef* LPTIMx)
+ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx)
{
ErrorStatus result = SUCCESS;
/* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(LPTIMx));
-
+ assert_param(IS_LPTIM_INSTANCE(LPTIMx));
+
if (LPTIMx == LPTIM1)
{
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1);
- }
-#if defined(LPTIM2)
- else if (LPTIMx == LPTIM2)
- {
- LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2);
- LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1);
}
-#endif
else
{
result = ERROR;
}
-
+
return result;
}
@@ -117,7 +119,7 @@
* @param LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
* @retval None
*/
-void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef* LPTIM_InitStruct)
+void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
{
/* Set the default configuration */
LPTIM_InitStruct->ClockSource = LL_LPTIM_CLK_SOURCE_INTERNAL;
@@ -136,42 +138,144 @@
* - SUCCESS: LPTIMx instance has been initialized
* - ERROR: LPTIMx instance hasn't been initialized
*/
-ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef * LPTIMx, LL_LPTIM_InitTypeDef* LPTIM_InitStruct)
+ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
{
ErrorStatus result = SUCCESS;
-
- /* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(LPTIMx));
+ assert_param(IS_LL_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource));
+ assert_param(IS_LL_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler));
+ assert_param(IS_LL_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform));
+ assert_param(IS_LL_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity));
+
+ /* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled
(ENABLE bit is reset to 0).
*/
- if (LL_LPTIM_IsEnabled(LPTIMx))
+ if (LL_LPTIM_IsEnabled(LPTIMx) == 1UL)
{
result = ERROR;
}
else
{
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(LPTIMx));
- assert_param(IS_LL_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource));
- assert_param(IS_LL_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler));
- assert_param(IS_LL_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform));
- assert_param(IS_LL_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity));
-
- /* Set CKSEL bitfield according to ClockSource value */
- /* Set PRESC bitfield according to Prescaler value */
- /* Set WAVE bitfield according to Waveform value */
- /* Set WAVEPOL bitfield according to Polarity value */
- MODIFY_REG(LPTIMx->CFGR,
- (LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE| LPTIM_CFGR_WAVPOL),
- LPTIM_InitStruct->ClockSource | \
- LPTIM_InitStruct->Prescaler | \
- LPTIM_InitStruct->Waveform | \
- LPTIM_InitStruct->Polarity);
+ /* Set CKSEL bitfield according to ClockSource value */
+ /* Set PRESC bitfield according to Prescaler value */
+ /* Set WAVE bitfield according to Waveform value */
+ /* Set WAVEPOL bitfield according to Polarity value */
+ MODIFY_REG(LPTIMx->CFGR,
+ (LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL),
+ LPTIM_InitStruct->ClockSource | \
+ LPTIM_InitStruct->Prescaler | \
+ LPTIM_InitStruct->Waveform | \
+ LPTIM_InitStruct->Polarity);
}
return result;
}
/**
+ * @brief Disable the LPTIM instance
+ * @rmtoll CR ENABLE LL_LPTIM_Disable
+ * @param LPTIMx Low-Power Timer instance
+ * @note The following sequence is required to solve LPTIM disable HW limitation.
+ * Please check Errata Sheet ES0335 for more details under "MCU may remain
+ * stuck in LPTIM interrupt when entering Stop mode" section.
+ * @retval None
+ */
+void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
+{
+ LL_RCC_ClocksTypeDef rcc_clock;
+ uint32_t tmpclksource = 0;
+ uint32_t tmpIER;
+ uint32_t tmpCFGR;
+ uint32_t tmpCMP;
+ uint32_t tmpARR;
+
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(LPTIMx));
+
+ __disable_irq();
+
+ /********** Save LPTIM Config *********/
+ /* Save LPTIM source clock */
+ switch ((uint32_t)LPTIMx)
+ {
+ case LPTIM1_BASE:
+ tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
+ break;
+ default:
+ break;
+ }
+
+ /* Save LPTIM configuration registers */
+ tmpIER = LPTIMx->IER;
+ tmpCFGR = LPTIMx->CFGR;
+ tmpCMP = LPTIMx->CMP;
+ tmpARR = LPTIMx->ARR;
+
+ /************* Reset LPTIM ************/
+ (void)LL_LPTIM_DeInit(LPTIMx);
+
+ /********* Restore LPTIM Config *******/
+ LL_RCC_GetSystemClocksFreq(&rcc_clock);
+
+ if ((tmpCMP != 0UL) || (tmpARR != 0UL))
+ {
+ /* Force LPTIM source kernel clock from APB */
+ switch ((uint32_t)LPTIMx)
+ {
+ case LPTIM1_BASE:
+ LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1);
+ break;
+ default:
+ break;
+ }
+
+ if (tmpCMP != 0UL)
+ {
+ /* Restore CMP and ARR registers (LPTIM should be enabled first) */
+ LPTIMx->CR |= LPTIM_CR_ENABLE;
+ LPTIMx->CMP = tmpCMP;
+
+ /* Polling on CMP write ok status after above restore operation */
+ do
+ {
+ rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
+ }
+ while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
+
+ LL_LPTIM_ClearFlag_CMPOK(LPTIMx);
+ }
+
+ if (tmpARR != 0UL)
+ {
+ LPTIMx->CR |= LPTIM_CR_ENABLE;
+ LPTIMx->ARR = tmpARR;
+
+ LL_RCC_GetSystemClocksFreq(&rcc_clock);
+ /* Polling on ARR write ok status after above restore operation */
+ do
+ {
+ rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
+ }
+ while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
+
+ LL_LPTIM_ClearFlag_ARROK(LPTIMx);
+ }
+
+
+ /* Restore LPTIM source kernel clock */
+ LL_RCC_SetLPTIMClockSource(tmpclksource);
+ }
+
+ /* Restore configuration registers (LPTIM should be disabled first) */
+ LPTIMx->CR &= ~(LPTIM_CR_ENABLE);
+ LPTIMx->IER = tmpIER;
+ LPTIMx->CFGR = tmpCFGR;
+
+ __enable_irq();
+}
+
+/**
* @}
*/
@@ -183,12 +287,12 @@
* @}
*/
-#endif /* defined (LPTIM1) || defined (LPTIM2) */
+#endif /* LPTIM1 */
/**
* @}
*/
-
+
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f7xx_ll_rcc.c b/Src/stm32f7xx_ll_rcc.c
index 9c03d56..083659b 100644
--- a/Src/stm32f7xx_ll_rcc.c
+++ b/Src/stm32f7xx_ll_rcc.c
@@ -163,7 +163,7 @@
*/
ErrorStatus LL_RCC_DeInit(void)
{
- uint32_t vl_mask = 0xFFFFFFFFU;
+ __IO uint32_t vl_mask;
/* Set HSION bit */
LL_RCC_HSI_Enable();
@@ -175,10 +175,13 @@
/* Reset CFGR register */
LL_RCC_WriteReg(CFGR, 0x00000000U);
+ /* Read CR register */
+ vl_mask = LL_RCC_ReadReg(CR);
+
/* Reset HSEON, HSEBYP, PLLON, CSSON, PLLI2SON and PLLSAION bits */
CLEAR_BIT(vl_mask, (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_PLLSAION | RCC_CR_PLLI2SON));
- /* Write new mask in CR register */
+ /* Write new value in CR register */
LL_RCC_WriteReg(CR, vl_mask);
/* Set HSITRIM bits to the reset value*/
diff --git a/Src/stm32f7xx_ll_sdmmc.c b/Src/stm32f7xx_ll_sdmmc.c
index ccb8057..3cd5b1f 100644
--- a/Src/stm32f7xx_ll_sdmmc.c
+++ b/Src/stm32f7xx_ll_sdmmc.c
@@ -15,7 +15,7 @@
==============================================================================
##### SDMMC peripheral features #####
==============================================================================
- [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the APB2
+ [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the AHB
peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA
devices.
@@ -29,8 +29,7 @@
(+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol
Rev1.1)
(+) Data transfer up to 48 MHz for the 8 bit mode
- (+) Data and command output enable signals to control external bidirectional drivers.
-
+ (+) Data and command output enable signals to control external bidirectional drivers
##### How to use this driver #####
==============================================================================
@@ -44,8 +43,8 @@
functionalities of the external device.
[..]
- (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output of PLL
- (PLL48CLK). Before start working with SDMMC peripheral make sure that the
+ (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output (MSI, PLLUSB1CLK,
+ PLLUSB2CLK). Before start working with SDMMC peripheral make sure that the
PLL is well configured.
The SDMMC peripheral uses two clock signals:
(++) SDMMC adapter clock (SDMMCCLK = 48 MHz)
@@ -57,13 +56,13 @@
(+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC
peripheral.
- (+) Enable the Power ON State using the SDMMC_PowerState_ON(SDMMCx)
- function and disable it using the function SDMMC_PowerState_OFF(SDMMCx).
+ (+) Enable the Power ON State using the SDMMC_PowerState_ON()
+ function and disable it using the function SDMMC_PowerState_OFF().
(+) Enable/Disable the clock using the __SDMMC_ENABLE()/__SDMMC_DISABLE() macros.
- (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT(hSDMMC, IT)
- and __SDMMC_DISABLE_IT(hSDMMC, IT) if you need to use interrupt mode.
+ (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT()
+ and __SDMMC_DISABLE_IT() if you need to use interrupt mode.
(+) When using the DMA mode
(++) Configure the DMA in the MSP layer of the external device
@@ -72,7 +71,7 @@
__SDMMC_DMA_DISABLE().
(+) To control the CPSM (Command Path State Machine) and send
- commands to the card use the SDMMC_SendCommand(SDMMCx),
+ commands to the card use the SDMMC_SendCommand(),
SDMMC_GetCommandResponse() and SDMMC_GetResponse() functions. First, user has
to fill the command structure (pointer to SDMMC_CmdInitTypeDef) according
to the selected command to be sent.
@@ -135,7 +134,7 @@
*** Command management operations ***
=====================================
[..]
- (#) The commands used for Read/Write//Erase operations are managed in
+ (#) The commands used for Read/Write/Erase operations are managed in
separate functions.
Each function allows to send the needed command with the related argument,
then check the response.
@@ -151,7 +150,7 @@
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -159,6 +158,8 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
+#if defined(SDMMC1)
+
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
@@ -168,7 +169,7 @@
* @{
*/
-#if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)
+#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -204,8 +205,8 @@
/**
* @brief Initializes the SDMMC according to the specified
* parameters in the SDMMC_InitTypeDef and create the associated handle.
- * @param SDMMCx Pointer to SDMMC register base
- * @param Init SDMMC initialization structure
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param Init: SDMMC initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init)
@@ -258,7 +259,7 @@
/**
* @brief Read data (word) from Rx FIFO in blocking mode (polling)
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx)
@@ -269,8 +270,8 @@
/**
* @brief Write data (word) to Tx FIFO in blocking mode (polling)
- * @param SDMMCx Pointer to SDMMC register base
- * @param pWriteData pointer to data to write
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param pWriteData: pointer to data to write
* @retval HAL status
*/
HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData)
@@ -302,20 +303,24 @@
/**
* @brief Set SDMMC Power state to ON.
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx)
{
/* Set power state to ON */
SDMMCx->POWER = SDMMC_POWER_PWRCTRL;
+
+ /* 1ms: required power up waiting time before starting the SD initialization
+ sequence */
+ HAL_Delay(2);
- return HAL_OK;
+ return HAL_OK;
}
/**
* @brief Set SDMMC Power state to OFF.
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx)
@@ -328,7 +333,7 @@
/**
* @brief Get SDMMC Power state.
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval Power status of the controller. The returned value can be one of the
* following values:
* - 0x00: Power OFF
@@ -343,8 +348,8 @@
/**
* @brief Configure the SDMMC command path according to the specified parameters in
* SDMMC_CmdInitTypeDef structure and send the command
- * @param SDMMCx Pointer to SDMMC register base
- * @param Command pointer to a SDMMC_CmdInitTypeDef structure that contains
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param Command: pointer to a SDMMC_CmdInitTypeDef structure that contains
* the configuration information for the SDMMC command
* @retval HAL status
*/
@@ -375,7 +380,7 @@
/**
* @brief Return the command index of last command for which response received
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval Command index of the last command response received
*/
uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx)
@@ -386,8 +391,8 @@
/**
* @brief Return the response received from the card for the last command
- * @param SDMMCx Pointer to SDMMC register base
- * @param Response Specifies the SDMMC response register.
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param Response: Specifies the SDMMC response register.
* This parameter can be one of the following values:
* @arg SDMMC_RESP1: Response Register 1
* @arg SDMMC_RESP2: Response Register 2
@@ -397,13 +402,13 @@
*/
uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response)
{
- __IO uint32_t tmp = 0;
+ uint32_t tmp;
/* Check the parameters */
assert_param(IS_SDMMC_RESP(Response));
/* Get the response */
- tmp = (uint32_t)&(SDMMCx->RESP1) + Response;
+ tmp = (uint32_t)(&(SDMMCx->RESP1)) + Response;
return (*(__IO uint32_t *) tmp);
}
@@ -411,8 +416,8 @@
/**
* @brief Configure the SDMMC data path according to the specified
* parameters in the SDMMC_DataInitTypeDef.
- * @param SDMMCx Pointer to SDMMC register base
- * @param Data pointer to a SDMMC_DataInitTypeDef structure
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param Data : pointer to a SDMMC_DataInitTypeDef structure
* that contains the configuration information for the SDMMC data.
* @retval HAL status
*/
@@ -448,7 +453,7 @@
/**
* @brief Returns number of remaining data bytes to be transferred.
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval Number of remaining data bytes to be transferred
*/
uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx)
@@ -458,7 +463,7 @@
/**
* @brief Get the FIFO data
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval Data received
*/
uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx)
@@ -468,8 +473,8 @@
/**
* @brief Sets one of the two options of inserting read wait interval.
- * @param SDMMCx Pointer to SDMMC register base
- * @param SDMMC_ReadWaitMode SDMMC Read Wait operation mode.
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMC_ReadWaitMode: SDMMC Read Wait operation mode.
* This parameter can be:
* @arg SDMMC_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK
* @arg SDMMC_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2
@@ -507,13 +512,13 @@
/**
* @brief Send the Data Block Lenght command and check the response
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)BlockSize;
@@ -521,7 +526,7 @@
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCKLEN, SDMMC_CMDTIMEOUT);
@@ -531,13 +536,13 @@
/**
* @brief Send the Read Single Block command and check the response
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)ReadAdd;
@@ -545,7 +550,7 @@
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_SINGLE_BLOCK, SDMMC_CMDTIMEOUT);
@@ -555,13 +560,13 @@
/**
* @brief Send the Read Multi Block command and check the response
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)ReadAdd;
@@ -569,7 +574,7 @@
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_MULT_BLOCK, SDMMC_CMDTIMEOUT);
@@ -579,13 +584,13 @@
/**
* @brief Send the Write Single Block command and check the response
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)WriteAdd;
@@ -593,7 +598,7 @@
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDMMC_CMDTIMEOUT);
@@ -603,13 +608,13 @@
/**
* @brief Send the Write Multi Block command and check the response
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)WriteAdd;
@@ -617,7 +622,7 @@
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_MULT_BLOCK, SDMMC_CMDTIMEOUT);
@@ -627,13 +632,13 @@
/**
* @brief Send the Start Address Erase command for SD and check the response
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)StartAdd;
@@ -641,7 +646,7 @@
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_START, SDMMC_CMDTIMEOUT);
@@ -651,13 +656,13 @@
/**
* @brief Send the End Address Erase command for SD and check the response
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)EndAdd;
@@ -665,7 +670,7 @@
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_END, SDMMC_CMDTIMEOUT);
@@ -675,13 +680,13 @@
/**
* @brief Send the Start Address Erase command and check the response
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)StartAdd;
@@ -689,7 +694,7 @@
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_START, SDMMC_CMDTIMEOUT);
@@ -699,13 +704,13 @@
/**
* @brief Send the End Address Erase command and check the response
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)EndAdd;
@@ -713,7 +718,7 @@
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_END, SDMMC_CMDTIMEOUT);
@@ -723,21 +728,21 @@
/**
* @brief Send the Erase command and check the response
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Set Block Size for Card */
- sdmmc_cmdinit.Argument = 0;
+ sdmmc_cmdinit.Argument = 0U;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE, SDMMC_MAXERASETIMEOUT);
@@ -747,38 +752,38 @@
/**
* @brief Send the Stop Transfer command and check the response.
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Send CMD12 STOP_TRANSMISSION */
- sdmmc_cmdinit.Argument = 0;
+ sdmmc_cmdinit.Argument = 0U;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
/* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_STOP_TRANSMISSION, 100000000/*SDMMC_CMDTIMEOUT*/);
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_STOP_TRANSMISSION, SDMMC_STOPTRANSFERTIMEOUT);
return errorstate;
}
/**
* @brief Send the Select Deselect command and check the response.
- * @param SDMMCx Pointer to SDMMC register base
- * @param addr Address of the card to be selected
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param addr: Address of the card to be selected
* @retval HAL status
*/
uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Send CMD7 SDMMC_SEL_DESEL_CARD */
sdmmc_cmdinit.Argument = (uint32_t)Addr;
@@ -786,7 +791,7 @@
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEL_DESEL_CARD, SDMMC_CMDTIMEOUT);
@@ -796,20 +801,20 @@
/**
* @brief Send the Go Idle State command and check the response.
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
- sdmmc_cmdinit.Argument = 0;
+ sdmmc_cmdinit.Argument = 0U;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_NO;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdError(SDMMCx);
@@ -819,13 +824,13 @@
/**
* @brief Send the Operating Condition command and check the response.
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Send CMD8 to verify SD card interface operating condition */
/* Argument: - [31:12]: Reserved (shall be set to '0')
@@ -837,7 +842,7 @@
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp7(SDMMCx);
@@ -849,20 +854,21 @@
* @brief Send the Application command to verify that that the next command
* is an application specific com-mand rather than a standard command
* and check the response.
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param Argument: Command Argument
* @retval HAL status
*/
uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
sdmmc_cmdinit.Argument = (uint32_t)Argument;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
/* Check for error conditions */
/* If there is a HAL_ERROR, it is a MMC card, else
@@ -876,20 +882,21 @@
/**
* @brief Send the command asking the accessed card to send its operating
* condition register (OCR)
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param Argument: Command Argument
* @retval HAL status
*/
-uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t SdType)
+uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
- sdmmc_cmdinit.Argument = SDMMC_VOLTAGE_WINDOW_SD | SdType;
+ sdmmc_cmdinit.Argument = SDMMC_VOLTAGE_WINDOW_SD | Argument;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp3(SDMMCx);
@@ -899,20 +906,21 @@
/**
* @brief Send the Bus Width command and check the response.
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param BusWidth: BusWidth
* @retval HAL status
*/
uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
sdmmc_cmdinit.Argument = (uint32_t)BusWidth;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDMMC_CMDTIMEOUT);
@@ -922,21 +930,21 @@
/**
* @brief Send the Send SCR command and check the response.
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Send CMD51 SD_APP_SEND_SCR */
- sdmmc_cmdinit.Argument = 0;
+ sdmmc_cmdinit.Argument = 0U;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_SEND_SCR, SDMMC_CMDTIMEOUT);
@@ -946,21 +954,21 @@
/**
* @brief Send the Send CID command and check the response.
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Send CMD2 ALL_SEND_CID */
- sdmmc_cmdinit.Argument = 0;
+ sdmmc_cmdinit.Argument = 0U;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp2(SDMMCx);
@@ -970,21 +978,22 @@
/**
* @brief Send the Send CSD command and check the response.
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param Argument: Command Argument
* @retval HAL status
*/
uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Send CMD9 SEND_CSD */
- sdmmc_cmdinit.Argument = (uint32_t)Argument;
+ sdmmc_cmdinit.Argument = Argument;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_CSD;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp2(SDMMCx);
@@ -994,21 +1003,22 @@
/**
* @brief Send the Send CSD command and check the response.
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param pRCA: Card RCA
* @retval HAL status
*/
uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Send CMD3 SD_CMD_SET_REL_ADDR */
- sdmmc_cmdinit.Argument = 0;
+ sdmmc_cmdinit.Argument = 0U;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp6(SDMMCx, SDMMC_CMD_SET_REL_ADDR, pRCA);
@@ -1018,20 +1028,21 @@
/**
* @brief Send the Status command and check the response.
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param Argument: Command Argument
* @retval HAL status
*/
uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
- sdmmc_cmdinit.Argument = (uint32_t)Argument;
+ sdmmc_cmdinit.Argument = Argument;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEND_STATUS, SDMMC_CMDTIMEOUT);
@@ -1041,20 +1052,20 @@
/**
* @brief Send the Status register command and check the response.
- * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
- sdmmc_cmdinit.Argument = 0;
+ sdmmc_cmdinit.Argument = 0U;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_STATUS;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_STATUS, SDMMC_CMDTIMEOUT);
@@ -1065,21 +1076,21 @@
/**
* @brief Sends host capacity support information and activates the card's
* initialization process. Send SDMMC_CMD_SEND_OP_COND command
- * @param SDIOx Pointer to SDIO register base
- * @parame Argument Argument used for the command
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @parame Argument: Argument used for the command
* @retval HAL status
*/
uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
sdmmc_cmdinit.Argument = Argument;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_OP_COND;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp3(SDMMCx);
@@ -1089,21 +1100,23 @@
/**
* @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand
- * @param SDIOx Pointer to SDIO register base
- * @parame Argument Argument used for the command
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @parame Argument: Argument used for the command
* @retval HAL status
*/
uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
- sdmmc_cmdinit.Argument = Argument;
+ /* Send CMD6 to activate SDR50 Mode and Power Limit 1.44W */
+ /* CMD Response: R1 */
+ sdmmc_cmdinit.Argument = Argument; /* SDMMC_SDR25_SWITCH_PATTERN */
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SWITCH;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SWITCH, SDMMC_CMDTIMEOUT);
@@ -1122,18 +1135,18 @@
/**
* @brief Checks for error conditions for CMD0.
- * @param hsd SD handle
+ * @param hsd: SD handle
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx)
{
/* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */
- register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000);
+ register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
do
{
- if (count-- == 0)
+ if (count-- == 0U)
{
return SDMMC_ERROR_TIMEOUT;
}
@@ -1141,34 +1154,36 @@
}while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT));
/* Clear all the static flags */
- __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS);
+ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
return SDMMC_ERROR_NONE;
}
/**
* @brief Checks for error conditions for R1 response.
- * @param hsd SD handle
- * @param SD_CMD The sent command index
+ * @param hsd: SD handle
+ * @param SD_CMD: The sent command index
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout)
{
uint32_t response_r1;
+ uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
The Timeout is expressed in ms */
- register uint32_t count = Timeout * (SystemCoreClock / 8 /1000);
+ register uint32_t count = Timeout * (SystemCoreClock / 8U /1000U);
do
{
- if (count-- == 0)
+ if (count-- == 0U)
{
return SDMMC_ERROR_TIMEOUT;
}
+ sta_reg = SDMMCx->STA;
+ }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
- }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT));
-
if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
{
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
@@ -1181,6 +1196,13 @@
return SDMMC_ERROR_CMD_CRC_FAIL;
}
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Clear all the static flags */
+ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
/* Check response received is of desired command */
if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)
@@ -1188,9 +1210,6 @@
return SDMMC_ERROR_CMD_CRC_FAIL;
}
- /* Clear all the static flags */
- __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS);
-
/* We have received response, retrieve it for analysis */
response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
@@ -1278,23 +1297,25 @@
/**
* @brief Checks for error conditions for R2 (CID or CSD) response.
- * @param hsd SD handle
+ * @param hsd: SD handle
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx)
{
+ uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */
- register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000);
+ register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
do
{
- if (count-- == 0)
+ if (count-- == 0U)
{
return SDMMC_ERROR_TIMEOUT;
}
-
- }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT));
+ sta_reg = SDMMCx->STA;
+ }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
{
@@ -1312,7 +1333,7 @@
{
/* No error flag set */
/* Clear all the static flags */
- __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS);
+ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
}
return SDMMC_ERROR_NONE;
@@ -1320,24 +1341,26 @@
/**
* @brief Checks for error conditions for R3 (OCR) response.
- * @param hsd SD handle
+ * @param hsd: SD handle
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx)
{
+ uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */
- register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000);
+ register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
do
{
- if (count-- == 0)
+ if (count-- == 0U)
{
return SDMMC_ERROR_TIMEOUT;
}
+ sta_reg = SDMMCx->STA;
+ }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
- }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT));
-
if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
{
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
@@ -1345,10 +1368,9 @@
return SDMMC_ERROR_CMD_RSP_TIMEOUT;
}
else
-
{
/* Clear all the static flags */
- __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS);
+ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
}
return SDMMC_ERROR_NONE;
@@ -1356,29 +1378,31 @@
/**
* @brief Checks for error conditions for R6 (RCA) response.
- * @param hsd SD handle
- * @param SD_CMD The sent command index
- * @param pRCA Pointer to the variable that will contain the SD card relative
+ * @param hsd: SD handle
+ * @param SD_CMD: The sent command index
+ * @param pRCA: Pointer to the variable that will contain the SD card relative
* address RCA
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA)
{
uint32_t response_r1;
+ uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */
- register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000);
+ register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
do
{
- if (count-- == 0)
+ if (count-- == 0U)
{
return SDMMC_ERROR_TIMEOUT;
}
+ sta_reg = SDMMCx->STA;
+ }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
- }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT));
-
if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
{
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
@@ -1391,6 +1415,10 @@
return SDMMC_ERROR_CMD_CRC_FAIL;
}
+ else
+ {
+ /* Nothing to do */
+ }
/* Check response received is of desired command */
if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)
@@ -1399,7 +1427,7 @@
}
/* Clear all the static flags */
- __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS);
+ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
/* We have received response, retrieve it. */
response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
@@ -1426,31 +1454,44 @@
/**
* @brief Checks for error conditions for R7 response.
- * @param hsd SD handle
+ * @param hsd: SD handle
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx)
{
+ uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */
- register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000);
+ register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
do
{
- if (count-- == 0)
+ if (count-- == 0U)
{
return SDMMC_ERROR_TIMEOUT;
}
+ sta_reg = SDMMCx->STA;
+ }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
- }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT));
-
if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
{
/* Card is SD V2.0 compliant */
- __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND);
+ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
return SDMMC_ERROR_CMD_RSP_TIMEOUT;
}
+ else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+ {
+ /* Card is SD V2.0 compliant */
+ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+
+ return SDMMC_ERROR_CMD_CRC_FAIL;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND))
{
@@ -1466,11 +1507,7 @@
* @}
*/
-/**
- * @}
- */
-
-#endif /* (HAL_SD_MODULE_ENABLED) */
+#endif /* HAL_SD_MODULE_ENABLED || HAL_MMC_MODULE_ENABLED */
/**
* @}
*/
@@ -1479,4 +1516,6 @@
* @}
*/
+#endif /* SDMMC1 */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f7xx_ll_tim.c b/Src/stm32f7xx_ll_tim.c
index 8bd622a..d3a992d 100644
--- a/Src/stm32f7xx_ll_tim.c
+++ b/Src/stm32f7xx_ll_tim.c
@@ -26,7 +26,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32F7xx_LL_Driver
* @{
@@ -46,135 +46,135 @@
* @{
*/
#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
- || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
- || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
- || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
- || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
- || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
- || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
+ || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
+ || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
- || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
- || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
- || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
- || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
- || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
- || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
- || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
- || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
- || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
+ || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
+ || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
+ || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
+ || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
- || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
+ || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
- || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
+ || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
- || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
+ || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
- || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
- || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
+ || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
+ || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
- || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
- || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
- || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
- || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
- || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
- || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
- || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
+ || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
+ || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
- || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
- || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
+ || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
- || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
+ || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
- || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
- || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
- || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
- || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
+ || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
- || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
+ || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
#define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
#define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
- || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
+ || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
#define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
- || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
+ || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
#define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
- || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
+ || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
/**
* @}
*/
@@ -336,7 +336,7 @@
TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
- TIM_InitStruct->RepetitionCounter = (uint8_t)0x00;
+ TIM_InitStruct->RepetitionCounter = 0x00000000U;
}
/**
@@ -728,9 +728,9 @@
* and DTG[7:0] can be write-locked depending on the LOCK configuration, it
* can be necessary to configure all of them during the first write access to
* the TIMx_BDTR register.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
- * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a second break input.
* @param TIMx Timer Instance
* @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
@@ -795,7 +795,7 @@
*/
/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
- * @brief Private functions
+ * @brief Private functions
* @{
*/
/**
diff --git a/Src/stm32f7xx_ll_usart.c b/Src/stm32f7xx_ll_usart.c
index 028c704..d7f3675 100644
--- a/Src/stm32f7xx_ll_usart.c
+++ b/Src/stm32f7xx_ll_usart.c
@@ -22,11 +22,11 @@
#include "stm32f7xx_ll_usart.h"
#include "stm32f7xx_ll_rcc.h"
#include "stm32f7xx_ll_bus.h"
-#ifdef USE_FULL_ASSERT
+#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32F7xx_LL_Driver
* @{
@@ -41,14 +41,6 @@
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
-/** @addtogroup USART_LL_Private_Constants
- * @{
- */
-
-/**
- * @}
- */
-
/* Private macros ------------------------------------------------------------*/
/** @addtogroup USART_LL_Private_Macros
* @{
@@ -65,42 +57,42 @@
#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
- || ((__VALUE__) == LL_USART_DIRECTION_RX) \
- || ((__VALUE__) == LL_USART_DIRECTION_TX) \
- || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
+ || ((__VALUE__) == LL_USART_DIRECTION_RX) \
+ || ((__VALUE__) == LL_USART_DIRECTION_TX) \
+ || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
- || ((__VALUE__) == LL_USART_PARITY_EVEN) \
- || ((__VALUE__) == LL_USART_PARITY_ODD))
+ || ((__VALUE__) == LL_USART_PARITY_EVEN) \
+ || ((__VALUE__) == LL_USART_PARITY_ODD))
#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
- || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
- || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
+ || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
+ || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
- || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
+ || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
- || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
+ || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
- || ((__VALUE__) == LL_USART_PHASE_2EDGE))
+ || ((__VALUE__) == LL_USART_PHASE_2EDGE))
#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
- || ((__VALUE__) == LL_USART_POLARITY_HIGH))
+ || ((__VALUE__) == LL_USART_POLARITY_HIGH))
#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
- || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
+ || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
- || ((__VALUE__) == LL_USART_STOPBITS_1) \
- || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
- || ((__VALUE__) == LL_USART_STOPBITS_2))
+ || ((__VALUE__) == LL_USART_STOPBITS_1) \
+ || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
+ || ((__VALUE__) == LL_USART_STOPBITS_2))
#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
- || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
- || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
- || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
+ || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
+ || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
+ || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
/**
* @}
diff --git a/Src/stm32f7xx_ll_usb.c b/Src/stm32f7xx_ll_usb.c
index b6659ae..cb59bad 100644
--- a/Src/stm32f7xx_ll_usb.c
+++ b/Src/stm32f7xx_ll_usb.c
@@ -94,6 +94,11 @@
/* Init The ULPI Interface */
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
+#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F732xx) || defined(STM32F733xx)
+ /* Select ULPI Interface */
+ USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPI_UTMI_SEL;
+#endif /* defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F732xx) || defined(STM32F733xx) */
+
/* Select vbus source */
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
if (cfg.use_external_vbus == 1U)
@@ -115,7 +120,7 @@
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
/* Select UTMI Interace */
- USBx->GUSBCFG &= ~ USB_OTG_GUSBCFG_ULPI_UTMI_SEL;
+ USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_ULPI_UTMI_SEL;
USBx->GCCFG |= USB_OTG_GCCFG_PHYHSEN;
/* Enables control of a High Speed USB PHY */
@@ -169,7 +174,7 @@
used by application. In the low AHB frequency range it is used to stretch enough the USB response
time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
latency to the Data FIFO */
- if (speed == USB_OTG_SPEED_FULL)
+ if (speed == USBD_FS_SPEED)
{
if ((hclk >= 14200000U) && (hclk < 15000000U))
{
@@ -222,7 +227,7 @@
UsbTrd = 0x6U;
}
}
- else if (speed == USB_OTG_SPEED_HIGH)
+ else if (speed == USBD_HS_SPEED)
{
UsbTrd = USBD_HS_TRDT_VALUE;
}
@@ -314,6 +319,8 @@
/* VBUS Sensing setup */
if (cfg.vbus_sensing_enable == 0U)
{
+ USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
+
/* Deactivate VBUS Sensing B */
USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
@@ -335,33 +342,33 @@
if (cfg.phy_itface == USB_OTG_ULPI_PHY)
{
- if (cfg.speed == USB_OTG_SPEED_HIGH)
+ if (cfg.speed == USBD_HS_SPEED)
{
- /* Set High speed phy */
+ /* Set Core speed to High speed mode */
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH);
}
else
{
- /* set High speed phy in Full speed mode */
+ /* Set Core speed to Full speed mode */
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL);
}
}
else if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY)
{
- if (cfg.speed == USB_OTG_SPEED_HIGH)
+ if (cfg.speed == USBD_HS_SPEED)
{
- /* Set High speed phy */
+ /* Set Core speed to High speed mode */
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH);
}
else
{
- /* set High speed phy in Full speed mode */
+ /* Set Core speed to Full speed mode */
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL);
}
}
else
{
- /* Set Full speed phy */
+ /* Set Core speed to Full speed mode */
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
}
@@ -427,17 +434,6 @@
USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
- if (cfg.dma_enable == 1U)
- {
- /*Set threshold parameters */
- USBx_DEVICE->DTHRCTL = USB_OTG_DTHRCTL_TXTHRLEN_6 |
- USB_OTG_DTHRCTL_RXTHRLEN_6;
-
- USBx_DEVICE->DTHRCTL |= USB_OTG_DTHRCTL_RXTHREN |
- USB_OTG_DTHRCTL_ISOTHREN |
- USB_OTG_DTHRCTL_NONISOTHREN;
- }
-
/* Disable all interrupts. */
USBx->GINTMSK = 0U;
@@ -542,8 +538,8 @@
* @param USBx Selected device
* @retval speed device speed
* This parameter can be one of these values:
- * @arg USB_OTG_SPEED_HIGH: High speed mode
- * @arg USB_OTG_SPEED_FULL: Full speed mode
+ * @arg PCD_SPEED_HIGH: High speed mode
+ * @arg PCD_SPEED_FULL: Full speed mode
*/
uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
{
@@ -553,16 +549,16 @@
if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
{
- speed = USB_OTG_SPEED_HIGH;
+ speed = USBD_HS_SPEED;
}
else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) ||
(DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))
{
- speed = USB_OTG_SPEED_FULL;
+ speed = USBD_FS_SPEED;
}
else
{
- speed = 0U;
+ speed = 0xFU;
}
return speed;
@@ -659,6 +655,12 @@
/* Read DEPCTLn register */
if (ep->is_in == 1U)
{
+ if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
+ {
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;
+ }
+
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |
@@ -669,6 +671,12 @@
}
else
{
+ if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+ {
+ USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
+ USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;
+ }
+
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |
@@ -694,11 +702,23 @@
/* Read DEPCTLn register */
if (ep->is_in == 1U)
{
+ if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
+ {
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;
+ }
+
USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
}
else
{
+ if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+ {
+ USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
+ USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;
+ }
+
USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
}
@@ -757,9 +777,27 @@
{
USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
}
+
+ if (ep->type == EP_TYPE_ISOC)
+ {
+ if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
+ {
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
+ }
+ else
+ {
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
+ }
+ }
+
+ /* EP enable, IN data in FIFO */
+ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
}
else
{
+ /* EP enable, IN data in FIFO */
+ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+
if (ep->type != EP_TYPE_ISOC)
{
/* Enable the Tx FIFO Empty Interrupt for this EP */
@@ -768,27 +806,20 @@
USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
}
}
- }
-
- if (ep->type == EP_TYPE_ISOC)
- {
- if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
- {
- USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
- }
else
{
- USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
+ if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
+ {
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
+ }
+ else
+ {
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
+ }
+
+ (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma);
}
}
-
- /* EP enable, IN data in FIFO */
- USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
-
- if (ep->type == EP_TYPE_ISOC)
- {
- (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma);
- }
}
else /* OUT endpoint */
{
@@ -886,18 +917,21 @@
{
USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
}
+
+ /* EP enable, IN data in FIFO */
+ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
}
else
{
+ /* EP enable, IN data in FIFO */
+ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+
/* Enable the Tx FIFO Empty Interrupt for this EP */
if (ep->xfer_len > 0U)
{
USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
}
}
-
- /* EP enable, IN data in FIFO */
- USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
}
else /* OUT endpoint */
{
@@ -955,7 +989,7 @@
count32b = ((uint32_t)len + 3U) / 4U;
for (i = 0U; i < count32b; i++)
{
- USBx_DFIFO((uint32_t)ch_ep_num) = *((__packed uint32_t *)pSrc);
+ USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);
pSrc++;
}
}
@@ -964,15 +998,10 @@
}
/**
- * @brief USB_ReadPacket : read a packet from the Tx FIFO associated
- * with the EP/channel
+ * @brief USB_ReadPacket : read a packet from the RX FIFO
* @param USBx Selected device
* @param dest source pointer
* @param len Number of bytes to read
- * @param dma USB dma enabled or disabled
- * This parameter can be one of these values:
- * 0 : DMA feature not used
- * 1 : DMA feature used
* @retval pointer to destination buffer
*/
void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
@@ -984,7 +1013,7 @@
for (i = 0U; i < count32b; i++)
{
- *(__packed uint32_t *)pDest = USBx_DFIFO(0U);
+ __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));
pDest++;
}
@@ -1256,13 +1285,9 @@
{
uint32_t USBx_BASE = (uint32_t)USBx;
- /* Set the MPS of the IN EP based on the enumeration speed */
+ /* Set the MPS of the IN EP0 to 64 bytes */
USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
- if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
- {
- USBx_INEP(0U)->DIEPCTL |= 3U;
- }
USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
return HAL_OK;
@@ -1429,7 +1454,7 @@
if ((USBx->CID & (0x1U << 8)) != 0U)
{
- if (cfg.speed == USB_OTG_SPEED_FULL)
+ if (cfg.speed == USBH_FSLS_SPEED)
{
/* Force Device Enumeration to FS/LS mode only */
USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
@@ -1590,9 +1615,9 @@
* @param USBx Selected device
* @retval speed : Host speed
* This parameter can be one of these values:
- * @arg USB_OTG_SPEED_HIGH: High speed mode
- * @arg USB_OTG_SPEED_FULL: Full speed mode
- * @arg USB_OTG_SPEED_LOW: Low speed mode
+ * @arg HCD_SPEED_HIGH: High speed mode
+ * @arg HCD_SPEED_FULL: Full speed mode
+ * @arg HCD_SPEED_LOW: Low speed mode
*/
uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx)
{
@@ -1770,7 +1795,7 @@
uint16_t num_packets;
uint16_t max_hc_pkt_count = 256U;
- if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USB_OTG_SPEED_HIGH))
+ if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USBH_HS_SPEED))
{
if ((dma == 0U) && (hc->do_ping == 1U))
{
@@ -1998,7 +2023,6 @@
uint32_t value;
uint32_t i;
-
(void)USB_DisableGlobalInt(USBx);
/* Flush FIFO */
@@ -2037,6 +2061,7 @@
/* Clear any pending Host interrupts */
USBx_HOST->HAINT = 0xFFFFFFFFU;
USBx->GINTSTS = 0xFFFFFFFFU;
+
(void)USB_EnableGlobalInt(USBx);
return HAL_OK;
