Release v1.4.1
diff --git a/Inc/stm32g0xx_hal_flash.h b/Inc/stm32g0xx_hal_flash.h
index 8474e8c..456bb4e 100644
--- a/Inc/stm32g0xx_hal_flash.h
+++ b/Inc/stm32g0xx_hal_flash.h
@@ -369,7 +369,7 @@
OB_USER_BANK_SWAP | OB_USER_DUAL_BANK | \
OB_USER_RAM_PARITY_CHECK | OB_USER_nBOOT_SEL | OB_USER_nBOOT1 | \
OB_USER_nBOOT0 | OB_USER_NRST_MODE | OB_USER_INPUT_RESET_HOLDER) /*!< all option bits */
-#else
+#else
#define OB_USER_ALL ( OB_USER_nRST_STOP | \
OB_USER_nRST_STDBY | OB_USER_IWDG_SW | \
OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | \
@@ -743,7 +743,7 @@
* @arg @ref FLASH_FLAG_BSY2 FLASH bank 2 write/erase operations in progress flag(*)
* @arg @ref FLASH_FLAG_BSY FLASH write/erase operations in progress flag - legacy name for single bank
* @arg @ref FLASH_FLAG_CFGBSY FLASH configuration is busy : program or erase setting are used.
- * @arg @ref FLASH_FLAG_ECCC1 FLASH one ECC error has been detected and corrected
+ * @arg @ref FLASH_FLAG_ECCC1 FLASH one ECC error has been detected and corrected
* @arg @ref FLASH_FLAG_ECCD1 FLASH two ECC errors have been detected on bank 1
* @arg @ref FLASH_FLAG_ECCC2 FLASH one ECC error has been detected and corrected on bank 2(*)
* @arg @ref FLASH_FLAG_ECCD2 FLASH two ECC errors have been detected on bank 2(*)
@@ -779,7 +779,7 @@
* @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag
* @arg @ref FLASH_FLAG_RDERR FLASH PCROP read error flag
* @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag
- * @arg @ref FLASH_FLAG_ECCC1 FLASH one ECC error has been detected and corrected
+ * @arg @ref FLASH_FLAG_ECCC1 FLASH one ECC error has been detected and corrected
* @arg @ref FLASH_FLAG_ECCD1 FLASH two ECC errors have been detected on bank 1
* @arg @ref FLASH_FLAG_ECCC2 FLASH one ECC error has been detected and corrected on bank 2(*)
* @arg @ref FLASH_FLAG_ECCD2 FLASH two ECC errors have been detected on bank 2(*)
@@ -876,24 +876,22 @@
#define FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE
#if defined(FLASH_DBANK_SUPPORT)
-#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /*!< FLASH Bank Size is Flash size divided by 2 */
-#else
-#define FLASH_BANK_SIZE (FLASH_SIZE) /*!< FLASH Bank Size */
-#endif
+#define OB_DUAL_BANK_BASE (FLASH_R_BASE + 0x20U) /*!< Not use cmsis FLASH alias to avoid iar warning about volatile reading sequence */
+#define FLASH_SALES_TYPE_Pos (24U)
+#define FLASH_SALES_TYPE (0x3UL << FLASH_SALES_TYPE_Pos) /*!< 0x000001E0 */
+#define FLASH_SALES_TYPE_0 (0x1UL << FLASH_SALES_TYPE_Pos) /*!< 0x01000000 */
+#define FLASH_SALES_TYPE_1 (0x2UL << FLASH_SALES_TYPE_Pos) /*!< 0x02000000 */
+#define FLASH_SALES_VALUE ((*((uint32_t *)PACKAGE_BASE)) & (FLASH_SALES_TYPE))
+#define OB_DUAL_BANK_VALUE ((*((uint32_t *)OB_DUAL_BANK_BASE)) & (FLASH_OPTR_DUAL_BANK))
+#define FLASH_BANK_NB (((FLASH_SALES_VALUE == 0U) || ((FLASH_SALES_VALUE == FLASH_SALES_TYPE_0) && (OB_DUAL_BANK_VALUE == 0U)))?1U:2U)
+#define FLASH_BANK_SIZE ((FLASH_BANK_NB==1U)?(FLASH_SIZE):(FLASH_SIZE >> 1U)) /*!< FLASH Bank Size. Divided by 2 if 2 Banks */
+#else /* FLASH_DBANK_SUPPORT */
+#define FLASH_BANK_SIZE (FLASH_SIZE) /*!< FLASH Bank Size */
+#endif /* FLASH_DBANK_SUPPORT */
#define FLASH_PAGE_SIZE 0x00000800U /*!< FLASH Page Size, 2 KBytes */
-
-#if defined(STM32G081xx)||defined(STM32G071xx)||defined(STM32G070xx)
-#define FLASH_PAGE_NB 64U
-#elif defined(STM32G0C1xx)||defined(STM32G0B1xx)||defined(STM32G0B0xx)
-/* warning : on those product, constant represents number of page per bank */
-#define FLASH_PAGE_NB 128U
-#else
-#define FLASH_PAGE_NB 32U
-#endif
-
+#define FLASH_PAGE_NB (FLASH_BANK_SIZE/FLASH_PAGE_SIZE) /* Number of pages per bank */
#define FLASH_TIMEOUT_VALUE 1000U /*!< FLASH Execution Timeout, 1 s */
-
#define FLASH_TYPENONE 0x00000000U /*!< No programming Procedure On Going */
#if defined(FLASH_PCROP_SUPPORT)
@@ -947,9 +945,12 @@
#define IS_FLASH_PAGE(__PAGE__) ((__PAGE__) < FLASH_PAGE_NB)
#if defined(FLASH_DBANK_SUPPORT)
-#define IS_FLASH_BANK(__BANK__) (((__BANK__) == FLASH_BANK_1) || \
- ((__BANK__) == FLASH_BANK_2) || \
- ((__BANK__) == (FLASH_BANK_2 | FLASH_BANK_1)))
+#define IS_FLASH_BANK(__BANK__) \
+ ((FLASH_BANK_NB == 2U) ? \
+ (((__BANK__) == FLASH_BANK_1) || \
+ ((__BANK__) == FLASH_BANK_2) || \
+ ((__BANK__) == (FLASH_BANK_2 | FLASH_BANK_1))): \
+ ((__BANK__) == FLASH_BANK_1))
#else
#define IS_FLASH_BANK(__BANK__) ((__BANK__) == FLASH_BANK_1)
#endif
@@ -964,8 +965,11 @@
(((__VALUE__) & ~OPTIONBYTE_ALL) == 0x00U))
#if defined(FLASH_DBANK_SUPPORT)
-#define IS_OB_WRPAREA(__VALUE__) (((__VALUE__) == OB_WRPAREA_ZONE_A) || ((__VALUE__) == OB_WRPAREA_ZONE_B) || \
- ((__VALUE__) == OB_WRPAREA_ZONE2_A) || ((__VALUE__) == OB_WRPAREA_ZONE2_B))
+#define IS_OB_WRPAREA(__VALUE__) \
+ ((FLASH_BANK_NB == 2U) ? \
+ (((__VALUE__) == OB_WRPAREA_ZONE_A) || ((__VALUE__) == OB_WRPAREA_ZONE_B) || \
+ ((__VALUE__) == OB_WRPAREA_ZONE2_A) || ((__VALUE__) == OB_WRPAREA_ZONE2_B)) : \
+ (((__VALUE__) == OB_WRPAREA_ZONE_A) || ((__VALUE__) == OB_WRPAREA_ZONE_B)))
#else
#define IS_OB_WRPAREA(__VALUE__) (((__VALUE__) == OB_WRPAREA_ZONE_A) || ((__VALUE__) == OB_WRPAREA_ZONE_B))
#endif
@@ -981,8 +985,11 @@
#if defined(FLASH_PCROP_SUPPORT)
#if defined(FLASH_DBANK_SUPPORT)
-#define IS_OB_PCROP_CONFIG(__CONFIG__) (((__CONFIG__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | \
- OB_PCROP_ZONE2_A | OB_PCROP_ZONE2_B | OB_PCROP_RDP_ERASE)) == 0x00U)
+#define IS_OB_PCROP_CONFIG(__CONFIG__) \
+ ((FLASH_BANK_NB == 2U) ? \
+ (((__CONFIG__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | \
+ OB_PCROP_ZONE2_A | OB_PCROP_ZONE2_B | OB_PCROP_RDP_ERASE)) == 0x00U): \
+ (((__CONFIG__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0x00U))
#else
#define IS_OB_PCROP_CONFIG(__CONFIG__) (((__CONFIG__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0x00U)
#endif
diff --git a/README.md b/README.md
index dcd4f1a..ed9334e 100644
--- a/README.md
+++ b/README.md
@@ -41,6 +41,7 @@
Tag v1.2.0 | Tag v1.2.0 | Tag v4.5_cm0 | Tag v1.2.0 (and following, if any, till next new tag)
Tag v1.3.0 | Tag v1.3.0 | Tag v5.4.0_cm0 | Tag v1.3.0 (and following, if any, till next new tag)
Tag v1.4.0 | Tag v1.4.0 | Tag v5.6.0_cm0 | Tag v1.4.0 (and following, if any, till next new tag)
+Tag v1.4.1 | Tag v1.4.0 | Tag v5.6.0_cm0 | Tag v1.4.1 (and following, if any, till next new tag)
The full **STM32CubeG0** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeG0).
diff --git a/Release_Notes.html b/Release_Notes.html
index a2c6a1d..7e99de4 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -42,9 +42,53 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section5" checked aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">V1.4.0 / 29-October-2020</label>
+<input type="checkbox" id="collapse-section6" checked aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">V1.4.1 / 25-February-2021</label>
<div>
<h2 id="main-changes">Main Changes</h2>
+<h3 id="patch-release">Patch release</h3>
+<p>Patch release of <strong>HAL and Low Layer</strong> drivers</p>
+<p><strong>Additional features</strong></p>
+<table>
+<thead>
+<tr class="header">
+<th style="text-align: left;">Headline</th>
+</tr>
+</thead>
+<tbody>
+<tr class="odd">
+<td style="text-align: left;"><strong>HAL FLASH</strong> driver update to support all STM32G0C1xx devices (with 128K dual bank and mono bank)</td>
+</tr>
+</tbody>
+</table>
+<h2 id="known-limitations">Known limitations</h2>
+<ul>
+<li>USB HAL limitation: Double buffer mode is not functional with isochronous data transfers in host mode.</li>
+</ul>
+<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2>
+<ul>
+<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.30.1</li>
+<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.29</li>
+<li>STM32CubeIDE toolchain v1.5.0</li>
+</ul>
+<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
+<p>Supported Devices:</p>
+<ul>
+<li>STM32G0C1xx, STM32G0B1xx, STM32G0B0xx</li>
+<li>STM32G061xx, STM32G051xx, STM32G050xx</li>
+<li>STM32G081xx, STM32G071xx, STM32G070xx</li>
+<li>STM32G041xx, STM32G031xx, STM32G030xx</li>
+</ul>
+<h2 id="backward-compatibility">Backward Compatibility</h2>
+<p>This release is compatible with the previous versions.</p>
+<h2 id="dependencies">Dependencies</h2>
+<p><br />
+</p>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">V1.4.0 / 29-October-2020</label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
<h3 id="maintenance-release-and-product-update">Maintenance release and Product Update</h3>
<p><strong>Official release</strong> of HAL and Low layers drivers introducing <strong>STM32G0C1xx/STM32G0B1xx/STM32G0B0xx</strong> devices and <strong>STM32G061xx/STM32G051xx/STM32G050xx</strong> devices.</p>
<p>Maintenance release of HAL and Low layers drivers supporting STM32G041xx/STM32G031xx/STM32G030xx and STM32G081xx/STM32G071xx/STM32G070xx devices.</p>
@@ -511,17 +555,17 @@
</tr>
</tbody>
</table>
-<h2 id="known-limitations">Known limitations</h2>
+<h2 id="known-limitations-1">Known limitations</h2>
<ul>
<li>USB HAL limitation: Double buffer mode is not functional with isochronous data transfers in host mode.</li>
</ul>
-<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2>
+<h2 id="development-toolchains-and-compilers-1">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.30.1</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.29</li>
<li>STM32CubeIDE toolchain v1.5.0</li>
</ul>
-<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-1">Supported Devices and boards</h2>
<p>Supported Devices:</p>
<ul>
<li><strong>STM32G0C1xx, STM32G0B1xx, STM32G0B0xx</strong></li>
@@ -529,15 +573,17 @@
<li>STM32G081xx, STM32G071xx, STM32G070xx</li>
<li>STM32G041xx, STM32G031xx, STM32G030xx</li>
</ul>
-<h2 id="backward-compatibility">Backward Compatibility</h2>
+<h2 id="backward-compatibility-1">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
-<h2 id="dependencies">Dependencies</h2>
+<h2 id="dependencies-1">Dependencies</h2>
+<p><br />
+</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">V1.3.0 / 25-June-2019</label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
<h3 id="maintenance-release">Maintenance release</h3>
<p>Maintenance release of HAL and Low layers drivers supporting STM32G041xx/STM32G031xx/STM32G030xx and STM32G081xx/STM32G071xx/STM32G070xx devices.</p>
<p><strong>Fixed bugs list</strong></p>
@@ -607,27 +653,27 @@
</tr>
</tbody>
</table>
-<h2 id="development-toolchains-and-compilers-1">Development Toolchains and Compilers</h2>
+<h2 id="development-toolchains-and-compilers-2">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
<li>System Workbench STM32 (SW4STM32) toolchain V2.7.2</li>
</ul>
-<h2 id="supported-devices-and-boards-1">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-2">Supported Devices and boards</h2>
<p>Supported Devices:</p>
<ul>
<li>STM32G081xx, STM32G071xx, STM32G070xx</li>
<li>STM32G041xx, STM32G031xx, STM32G030xx</li>
</ul>
-<h2 id="backward-compatibility-1">Backward Compatibility</h2>
+<h2 id="backward-compatibility-2">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
-<h2 id="dependencies-1">Dependencies</h2>
+<h2 id="dependencies-2">Dependencies</h2>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.2.0 / 05-April-2019</label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
<h3 id="maintenance-release-and-product-update-1">Maintenance release and product update</h3>
<p>First release of HAL and Low layers drivers to introduce support of <strong>STM32G041xx/STM32G031xx/STM32G030xx devices</strong>.</p>
<p>Maintenance release of HAL and Low layers drivers supporting STM32G081xx/STM32G071xx/STM32G070xx devices.</p>
@@ -714,27 +760,27 @@
</tr>
</tbody>
</table>
-<h2 id="development-toolchains-and-compilers-2">Development Toolchains and Compilers</h2>
+<h2 id="development-toolchains-and-compilers-3">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
<li>System Workbench STM32 (SW4STM32) toolchain V2.7.2</li>
</ul>
-<h2 id="supported-devices-and-boards-2">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-3">Supported Devices and boards</h2>
<p>Supported Devices:</p>
<ul>
<li>STM32G081xx, STM32G071xx, STM32G070xx</li>
<li><strong>STM32G041xx, STM32G031xx, STM32G030xx</strong></li>
</ul>
-<h2 id="backward-compatibility-2">Backward Compatibility</h2>
+<h2 id="backward-compatibility-3">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
-<h2 id="dependencies-2">Dependencies</h2>
+<h2 id="dependencies-3">Dependencies</h2>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 06-February-2019</label>
<div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
<h3 id="maintenance-release-and-product-update-2">Maintenance release and product update</h3>
<p>Maintenance release of HAL and Low layers drivers to support STM32G071xx/STM32G081xx/STM32G070xx devices.</p>
<p><strong>Additional features</strong></p>
@@ -823,24 +869,6 @@
</tr>
</tbody>
</table>
-<h2 id="supported-devices-and-boards-3">Supported Devices and boards</h2>
-<p>Supported Devices:</p>
-<ul>
-<li>STM32G0<strong>81</strong>xx</li>
-<li>STM32G0<strong>71</strong>xx</li>
-<li>STM32G0<strong>70</strong>xx</li>
-</ul>
-<h2 id="backward-compatibility-3">Backward Compatibility</h2>
-<p>This release is compatible with the previous versions.</p>
-<h2 id="dependencies-3">Dependencies</h2>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 26-October-2018</label>
-<div>
-<h2 id="main-changes-4">Main Changes</h2>
-<h3 id="first-release">First release</h3>
-<p>First official release of HAL and Low layers drivers to support STM32G071xx/STM32G081xx/STM32G070xx</p>
<h2 id="supported-devices-and-boards-4">Supported Devices and boards</h2>
<p>Supported Devices:</p>
<ul>
@@ -848,9 +876,27 @@
<li>STM32G0<strong>71</strong>xx</li>
<li>STM32G0<strong>70</strong>xx</li>
</ul>
+<h2 id="backward-compatibility-4">Backward Compatibility</h2>
+<p>This release is compatible with the previous versions.</p>
<h2 id="dependencies-4">Dependencies</h2>
</div>
</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 26-October-2018</label>
+<div>
+<h2 id="main-changes-5">Main Changes</h2>
+<h3 id="first-release">First release</h3>
+<p>First official release of HAL and Low layers drivers to support STM32G071xx/STM32G081xx/STM32G070xx</p>
+<h2 id="supported-devices-and-boards-5">Supported Devices and boards</h2>
+<p>Supported Devices:</p>
+<ul>
+<li>STM32G0<strong>81</strong>xx</li>
+<li>STM32G0<strong>71</strong>xx</li>
+<li>STM32G0<strong>70</strong>xx</li>
+</ul>
+<h2 id="dependencies-5">Dependencies</h2>
+</div>
+</div>
</div>
</div>
<footer class="sticky">
diff --git a/Src/stm32g0xx_hal.c b/Src/stm32g0xx_hal.c
index 8c5afa3..eb3ab8f 100644
--- a/Src/stm32g0xx_hal.c
+++ b/Src/stm32g0xx_hal.c
@@ -57,7 +57,7 @@
*/
#define __STM32G0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32G0xx_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */
-#define __STM32G0xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
+#define __STM32G0xx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32G0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32G0xx_HAL_VERSION ((__STM32G0xx_HAL_VERSION_MAIN << 24U)\
|(__STM32G0xx_HAL_VERSION_SUB1 << 16U)\
diff --git a/Src/stm32g0xx_hal_flash_ex.c b/Src/stm32g0xx_hal_flash_ex.c
index e3282b5..e7c31dc 100644
--- a/Src/stm32g0xx_hal_flash_ex.c
+++ b/Src/stm32g0xx_hal_flash_ex.c
@@ -512,7 +512,7 @@
#if defined(FLASH_SECURABLE_MEMORY_SUPPORT)
/**
* @brief Securable memory area protection enable
- * @param Banks Select Bank to be secured.
+ * @param Banks Select Bank to be secured.
* This parameter can be a value of @ref FLASH_Banks
* @note On some devices, there is only 1 bank so parameter has to be set FLASH_BANK_1.
* @note This API locks Securable memory area which is defined in SEC_SIZE option byte
@@ -539,7 +539,7 @@
UNUSED(Banks);
#endif
{
- FLASH->CR |= FLASH_CR_SEC_PROT;
+ FLASH->CR |= FLASH_CR_SEC_PROT;
}
}
#endif
@@ -851,8 +851,8 @@
assert_param(IS_OB_PCROP_CONFIG(PCROPConfig));
#if defined(FLASH_DBANK_SUPPORT)
- /* Check if banks are swapped */
- if ((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != FLASH_OPTR_nSWAP_BANK)
+ /* Check if banks are swapped (valid if only one bank) */
+ if (((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != FLASH_OPTR_nSWAP_BANK) && (FLASH_BANK_NB == 2U))
{
/* Check the parameters */
assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP1AStartAddr));
@@ -920,8 +920,8 @@
uint32_t ropbase;
#if defined(FLASH_DBANK_SUPPORT)
- /* Check if banks are swapped */
- if ((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != FLASH_OPTR_nSWAP_BANK)
+ /* Check if banks are swapped (valid if only one bank) */
+ if (((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != FLASH_OPTR_nSWAP_BANK) && (FLASH_BANK_NB == 2U))
{
/* Check the parameters */
assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP1BStartAddr));
@@ -966,8 +966,8 @@
uint32_t ropbase;
#if defined(FLASH_DBANK_SUPPORT)
- /* Check if banks are swapped */
- if ((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != FLASH_OPTR_nSWAP_BANK)
+ /* Check if banks are swapped (valid if only one bank) */
+ if (((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != FLASH_OPTR_nSWAP_BANK) && (FLASH_BANK_NB == 2U))
{
/* Bank swap, bank 1 read only protection is on second half of Flash */
ropbase = (FLASH_BASE + FLASH_BANK_SIZE);
@@ -1005,8 +1005,8 @@
uint32_t ropbase;
#if defined(FLASH_DBANK_SUPPORT)
- /* Check if banks are swapped */
- if ((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != FLASH_OPTR_nSWAP_BANK)
+ /* Check if banks are swapped (valid if only one bank) */
+ if (((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != FLASH_OPTR_nSWAP_BANK) && (FLASH_BANK_NB == 2U))
{
/* Bank swap, bank 1 read only protection is on second half of Flash */
ropbase = (FLASH_BASE + FLASH_BANK_SIZE);
@@ -1217,7 +1217,11 @@
/* Check the parameters */
assert_param(IS_OB_SEC_BOOT_LOCK(BootEntry));
assert_param(IS_OB_SEC_SIZE(SecSize));
- assert_param(IS_OB_SEC_SIZE(SecSize2));
+
+ if ((FLASH_BANK_NB == 2U))
+ {
+ assert_param(IS_OB_SEC_SIZE(SecSize2));
+ }
/* Set securable memory area configuration */
secmem = (FLASH->SECR & ~(FLASH_SECR_BOOT_LOCK | FLASH_SECR_SEC_SIZE | FLASH_SECR_SEC_SIZE2));
