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<h1 id="release-notes-for-stm32g4xx-hal-drivers"><small>Release Notes for</small> STM32G4xx HAL Drivers</h1>
<p>Copyright © 2019 STMicroelectronics<br />
</p>
<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo.png" alt="ST logo" /></a>
</center>
</div>
</div>
<h1 id="license">License</h1>
<p>This software component is licensed by ST under BSD 3-Clause license, the “License”; You may not use this component except in compliance with the License. You may obtain a copy of the License at:</p>
<p><a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a></p>
<h1 id="purpose">Purpose</h1>
<p>The STM32Cube HAL and LL, an STM32 abstraction layer embedded software, ensure maximized portability across STM32 portfolio.</p>
<p>The Portable APIs layer provides a generic, multi instanced and simple set of APIs to interact with the upper layer (application, libraries and stacks). It is composed of native and extended APIs set. It is directly built around a generic architecture and allows the build-upon layers, like the middleware layer, to implement its functions without knowing in-depth the used STM32 device. This improves the library code reusability and guarantees an easy portability on other devices and STM32 families.</p>
<p>The Low Layer (LL) drivers are part of the STM32Cube firmware HAL that provide basic set of optimized and one shot services. The Low layer drivers, contrary to the HAL ones are not Fully Portable across the STM32 families; the availability of some functions depend on the physical availability of the relative features on the product. The Low Layer (LL) drivers are designed to offer the following features:</p>
<ul>
<li>New set of inline function for direct and atomic register access</li>
<li>One-shot operations that can be used by the HAL drivers or from application level.</li>
<li>Fully Independent from HAL and can be used in standalone usage (without HAL drivers)</li>
<li>Full features coverage of the all the supported peripherals.</li>
</ul>
</div>
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
<input type="checkbox" id="collapse-section4" checked aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">V1.2.0 / 26-June-2020</label>
<div>
<h2 id="main-changes">Main Changes</h2>
<h3 id="maintenance-release">Maintenance Release</h3>
<ul>
<li>Add support for STM32G491xx and STM32G4A1 part numbers</li>
<li><p>General updates to fix known defects and enhancements implementation</p></li>
<li><strong>HAL/LL GPIO</strong> update
<ul>
<li>Enhancement GPIO_TogglePin API to allow the toggling of many pins</li>
<li>Update GPIO initialization sequence to avoid unwanted pulse on GPIO Pin’s</li>
</ul></li>
<li><strong>HAL/LL HRTIM</strong> update
<ul>
<li>Constants renaming:
<ul>
<li>Rename HAL constants HRTIM_TIMEEVENT_… and HRTIM_TIMEEVENTRESETMODE_… respectively HRTIM_EVENT<strong>COUNTER</strong>_… and HRTIM_EVENT<strong>COUNTER</strong>_RSTMODE_… to reflect their relation to external event <strong>counters</strong>.</li>
<li>Rename LL constants LL_HRTIM_OUTPUTSET_TIM… and LL_HRTIM_OUTPUTRESET_TIM… to make them compliant to the CMSIS bits definitions they correspond to.</li>
<li><strong>Warning:</strong> Possible <strong>compatibility break</strong> with CubeMX 5.6.0 and previous versions!</li>
</ul></li>
<li>Constants removal:
<ul>
<li>Remove unused HAL constants HRTIM_RSYNCUPDATE_… and HRTIM_TIMEEVENTCOUNTER_….</li>
<li>Remove unused LL constant LL_HRTIM_RESETTRIG_OTHER5_CMP4 as the definition it corresponds to (HRTIM_RSTR_TIMFCMP4) exists neither in the CMSIS nor in the reference manual.</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL I2S</strong> update
<ul>
<li>Update HAL_I2S_DMAStop() API to be more safe
<ul>
<li>Add a check on BSY, TXE and RXNE flags before disabling the I2S</li>
</ul></li>
<li>Update HAL_I2S_DMAStop() API to fix multi-call transfer issue(to avoid re-initializing the I2S for the next transfer).
<ul>
<li>Add __HAL_I2SEXT_FLUSH_RX_DR() and __HAL_I2S_FLUSH_RX_DR() macros to flush the remaining data inside DR registers.</li>
<li>Add new ErrorCode define: HAL_I2S_ERROR_BUSY_LINE_RX</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL SPI</strong> update
<ul>
<li>Update HAL_SPI_Init() API
<ul>
<li>To avoid setting the BaudRatePrescaler in case of Slave Motorola Mode</li>
<li>Use the bit-mask for SPI configuration</li>
</ul></li>
<li>Update Transmit/Receive processes in half-duplex mode
<ul>
<li>Disable the SPI instance before setting BDIOE bit</li>
</ul></li>
<li>Update SPI_DMAReceiveCplt() API to handle efficiently the repeated transfers.
<ul>
<li>Disable TX DMA request only in bidirectional receive mode.</li>
</ul></li>
<li>Fix wrong timeout management
<ul>
<li>Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled</li>
</ul></li>
</ul></li>
<li><strong>HAL SAI</strong> update
<ul>
<li>Update HAL_SAI_Init() API to correct the formula in case of SPDIF is wrong</li>
</ul></li>
<li><strong>HAL/LL ADC</strong> update
<ul>
<li>Update Channel &amp; external trigger to support <strong>STM32G491/STM32G4A1</strong> embedded with 3 ADC:
<ul>
<li>IS_ADC_EXTRIG, IS_ADC_CHANNEL, IS_ADC_EXTRIGINJ, ADC_IS_INDEPENDENT.</li>
<li>IS_LL_ADC_REG_TRIG_SOURCE, IS_LL_ADC_INJ_TRIG_SOURCE, __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE.</li>
</ul></li>
<li>Update note in ll_adc.h &amp; hal_adc.h to highlight that the ADC with transfers DMA and ADC mode auto delay can work simultaneously.</li>
</ul></li>
<li><strong>HAL COMP</strong> update
<ul>
<li>Update Blanking sources to support <strong>STM32G491/STM32G4A1</strong> embedded with 4 COMP:
<ul>
<li>IS_COMP_BLANKINGSRC_INSTANCE</li>
</ul></li>
</ul></li>
<li><strong>HAL OPAMP</strong> update
<ul>
<li>Update hal_opamp_ex.c to support <strong>STM32G491/STM32G4A1</strong> embedded with 4 OPAMP (OPAMP1/OPAMP2/OPAMP3/OPAMP6):</li>
</ul></li>
<li><strong>HAL FLASH</strong> update
<ul>
<li>Update FLASH Latency comment param to list all supported flash latency values.</li>
<li>Update FLASH_PAGE_NB to return the right page number(256 pages for devices embedded with 512KB flash size and 64 for devices embedded with 128KB flash size)</li>
</ul></li>
<li><strong>HAL/LL RCC</strong> update
<ul>
<li>Update Table 1. HCLK clock frequency for STM32G4xx devices to be aligned with referance manual RM0440</li>
<li>Update peripheral clock to support <strong>STM32G491/STM32G4A1</strong> devices:
<ul>
<li>HAL_RCCEx_GetPeriphCLKConfig</li>
<li>IS_RCC_PERIPHCLOCK</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL TIM</strong> driver
<ul>
<li>Align HAL/LL TIM driver with latest updates and enhancements</li>
<li>Add new macros to enable and disable the fast mode when using the one pulse mode to output a waveform with a minimum delay
<ul>
<li>__HAL_TIM_ENABLE_OCxFAST() and __HAL_TIM_DISABLE_OCxFAST().</li>
</ul></li>
<li>Update HAL_TIMEx_MasterConfigSynchronization() API to avoid functional errors and assert fails when using some TIM instances as input trigger.
<ul>
<li>Replace IS_TIM_SYNCHRO_INSTANCE() macro by IS_TIM_MASTER_INSTANCE() macro.</li>
<li>Add IS_TIM_SLAVE_INSTANCE() macro to check on TIM_SMCR_MSM bit.</li>
</ul></li>
<li>Remove ‘register’ storage class specifier from LL TIM driver.</li>
<li>Add new API HAL_TIM_DMABurst_MultiWriteStart() allowing to configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral</li>
<li>Add new API HAL_TIM_DMABurst_MultiReadStart() allowing to configure the DMA Burst to transfer Data from the TIM peripheral to the memory</li>
</ul></li>
<li><strong>HAL/LL UART</strong> driver
<ul>
<li>Update UART polling processes to handle efficiently the Lock mechanism
<ul>
<li>Move the process unlock at the top of the HAL_UART_Receive() and HAL_UART_Transmit() API.</li>
</ul></li>
<li>Update UART BRR calculation for ROM size gain</li>
<li>Remove ‘register’ storage class specifier from LL UART driver.</li>
</ul></li>
<li><strong>HAL/LL USART</strong> driver
<ul>
<li>Remove ‘register’ storage class specifier from LL USART driver.</li>
</ul></li>
<li><strong>HAL/LL USB</strong> driver
<ul>
<li>Fix USB Bulk transfer double buffer mode</li>
<li>Remove register keyword from USB defined macros as no more supported by c++ compiler</li>
<li>minor rework USBD_Start and USBD_Stop API, stop device to be handled by HAL_PCD_DeInit()</li>
<li>Correct some word spelling issues</li>
</ul></li>
</ul>
<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.40.1</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain <strong>V5.29</strong></li>
<li>STM32CubeIDE toolchain <strong>V1.4.0</strong></li>
</ul>
<h2 id="supported-devices">Supported Devices</h2>
<ul>
<li>STM32G431/41xx</li>
<li>STM32G471xx</li>
<li>STM32G473/83xx</li>
<li>STM32G474/84xx</li>
<li>STM32G4<strong>91</strong>/<strong>A1</strong>xx</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.1.1 / 14-February-2020</label>
<div>
<h2 id="main-changes-1">Main Changes</h2>
<h3 id="maintenance-release-1">Maintenance Release</h3>
<ul>
<li><p>General updates to fix known defects and enhancements implementation</p></li>
<li><strong>HAL/LL CRYP</strong> update
<ul>
<li>Correct MISRA C:2012 warnings reported by rules 2.2_c, 10.1_R6, 10.3, 10.4_a, 10.6, 12.1, 13.5 15.7</li>
<li>Perform a new check mechanism on the cryp buffer size in Encryption et Decryption API
<ul>
<li>Add IS_CRYP_BUFFERSIZE() macro</li>
</ul></li>
<li>Clean up the HAL_CRYP_Resume() API to avoid infinite loop due to an early interruption during resumption process
<ul>
<li>Remove __HAL_CRYP_ENABLE_IT() and __HAL_CRYP_ENABLE() API .</li>
</ul></li>
<li>Add new parameter in the CRYP_HandleTypeDef structure
<ul>
<li>Add SizesSum_saved to save the SizesSum when processing is suspended</li>
<li>Update the HAL_CRYP_Suspend() and HAL_CRYP_Resume() API by adding this new parameter</li>
</ul></li>
<li>Add missing interruptions re-enabling operations following an all flags clear-up in the CRYP_PhaseProcessingResume() API</li>
<li>Support AAD with all possible byte sizes, not only multiple of 4 bytes
<ul>
<li>Update CRYP_GCMCCM_SetHeaderPhase() API</li>
<li>Add new parameter HeaderWidthUnit in the CRYP_ConfigTypeDef structure which contains the Cryp Header Width Unit</li>
<li>Add new definition of the CRYP Header size Unit
<ul>
<li>CRYP_HEADERWIDTHUNIT_WORD</li>
<li>CRYP_HEADERWIDTHUNIT_BYTE</li>
</ul></li>
</ul></li>
<li>Support data encryption and decryption with length not only multiple of 16 bytes
<ul>
<li>Update IS_CRYP_BUFFERSIZE() macro</li>
<li>Update AES functions : CRYP_AES_ProcessData() / CRYP_AES_IT() / CRYP_AESCCM_Process() / CRYP_AESGCM_Process_DMA()</li>
<li>Update CRYP_GCMCCM_SetPayloadPhase_IT() API</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL FMAC</strong> update
<ul>
<li>General updates to comply to internal coding rules.</li>
</ul></li>
<li><strong>HAL GPIO</strong> update
<ul>
<li>Update the GPIO initialization sequence in HAL_GPIO_Init() API to avoid unwanted glitches on GPIO pins.</li>
<li>Add missing GPIO Alternate Function definitions:
<ul>
<li>GPIO_AF2_TIM16, GPIO_AF9_TIM8, GPIO_AF11_TIM8, GPIO_AF12_TIM1.</li>
</ul></li>
</ul></li>
<li><strong>HAL HRTIM</strong> update
<ul>
<li>Update HAL_HRTIM_WaveformCompareConfig() to clear HRTIM_TIMxCR.DELCMP bitfield when the auto-delayed protection mode is disabled.</li>
<li>Correct some “HRTIM_OUTPUTSET_TIMxx” constant names which are not compliant with Timer Events Mapping specified in the reference manual
<ul>
<li>Remove HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1, HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 , HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 and HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2</li>
<li>Add HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2 and HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3 , HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3 and HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2</li>
<li>Update HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 and HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 definitions</li>
</ul></li>
<li>Update HAL_HRTIM_DLLCalibrationStart() and HAL_HRTIM_DLLCalibrationStart_IT() API by setting HRTIM state ready to avoid some unstable behavior of the TIMER E.</li>
<li>Add new check field in the IS_HRTIM_EVENTSRC() macro to check also on EVENT</li>
<li>Add a new check in the HAL_HRTIM_EventConfig() API on event and event source through the IS_HRTIM_EVENTSRC() macro</li>
<li>Remove UPDGAT bits reset from the HRTIM_TimingUnitWaveform_Control() API</li>
<li>Add a lock and unlock handle process in the HAL_HRTIM_SimpleOCChannelConfig() API</li>
</ul></li>
<li><strong>HAL I2C</strong> update
<ul>
<li>Update I2C_DMAAbort() APIs to fix hardfault issue when hdmatx and hdmarx parameters in i2c handle aren’t initialized (NULL pointer).
<ul>
<li>Add additional check on hi2c-&gt;hdmtx and hi2c-&gt;hdmarx before resetting DMA Tx/Rx complete callbacks</li>
</ul></li>
<li>Fix HAL I2C slave interrupt handling issue with I2C sequential transfers.
<ul>
<li>Update I2C_Slave_ISR_IT() and I2C_Slave_ISR_DMA() APIs to check on STOP condition and handle it before clearing the ADDR flag</li>
</ul></li>
</ul></li>
<li><strong>HAL LPTIM</strong> update
<ul>
<li>Add a polling mechanism to check on LPTIM_FLAG_XXOK flags in different API
<ul>
<li>Add LPTIM_WaitForFlag() API to wait for flag set.</li>
<li>Perform new checks on HAL_LPTIM_STATE_TIMEOUT.</li>
</ul></li>
<li>Apply digital filter for external clock for all LPTIM clock source.
<ul>
<li>Update HAL_LPTIM_Init() API</li>
</ul></li>
<li>Correct the input1source and input2source selection
<ul>
<li>Update LL_LPTIM_SetInput1Src and LL_LPTIM_SetInput2Src
<ul>
<li>Remove WRITE_REG and replace it by MODIFY_REG</li>
</ul></li>
</ul></li>
</ul></li>
<li><strong>HAL/LL RTC</strong> update
<ul>
<li>Update API HAL_RTC_SetAlarm_IT() to allow changing alarm time “on the fly” simply by calling the API again.</li>
<li>Update API LL_RTC_BKP_SetRegister() and API LL_RTC_BKP_GetRegister() to comply to rules 2.2 and 13.2 of MISRAC-2012.</li>
</ul></li>
<li><strong>HAL SPI</strong> update
<ul>
<li>Update the “Rx DMA transfer complete callback” to disable the Tx DMA request only in case of full-duplex mode and not it in half-duplex mode.</li>
</ul></li>
<li><strong>HAL TIM</strong> update
<ul>
<li>Update Encoder interface mode to keep TIM_CCER_CCxNP bits low
<ul>
<li>Add TIM_ENCODERINPUTPOLARITY_RISING and TIM_ENCODERINPUTPOLARITY_FALLING definitions to determine encoder input polarity.</li>
<li>Add IS_TIM_ENCODERINPUT_POLARITY() macro to check the encoder input polarity.</li>
<li>Update HAL_TIM_Encoder_Init() API
<ul>
<li>Replace IS_TIM_IC_POLARITY() macro by IS_TIM_ENCODERINPUT_POLARITY() macro.</li>
</ul></li>
</ul></li>
<li>Provide new API to set and clear UIFREMAP
<ul>
<li>Add new definition for TIM Update Interrupt Flag Remap
<ul>
<li>TIM_UIFREMAP_DISABLE</li>
<li>TIM_UIFREMAP_ENABLE</li>
</ul></li>
<li>Add new macro in HAL driver to enable and desable the Update Interrupt Flag Remap
<ul>
<li>__HAL_TIM_UIFREMAP_ENABLE()</li>
<li>__HAL_TIM_UIFREMAP_DISABLE()/__HAL_TIM_GET_UIFCPY macro</li>
</ul></li>
<li>Add new mechanism to check whether the update interrupt flag (UIF) copy is set or not
<ul>
<li>Add the __HAL_TIM_GET_UIFCPY() macro in the HAL driver</li>
<li>Add LL_TIM_IsActiveUIFCPY() API in the LL driver</li>
</ul></li>
<li>Add new macro to check on the Update Interrupt Flag Remap mode
<ul>
<li>IS_TIM_UIFREMAP_MODE()</li>
</ul></li>
</ul></li>
<li>Remove useless TIM trigger selector</li>
<li>Fix bug when using multiple DMA request to different channels of same timer
<ul>
<li>Introduce DMA burst state management mechanism
<ul>
<li>Add a new structure for DMA Burst States definition : HAL_TIM_DMABurstStateTypeDef</li>
<li>Update __HAL_TIM_RESET_HANDLE_STATE to support DMABurstState</li>
<li>Add a new API HAL_TIM_DMABurstState() to get the actual state of a DMA burst operation</li>
<li>Add DMABurstState, the DMA burst operation state, in the TIM_HandleTypeDef structure</li>
<li>Add new API TIM_DMAErrorCCxN() for TIM DMA error callback (complementary channel)</li>
<li>Add new API TIM_DMADelayPulseNCplt() for TIM DMA Delay Pulse complete callback (complementary channel)</li>
</ul></li>
</ul></li>
<li>Implement TIM channel state management mechanism
<ul>
<li>Add new macro
<ul>
<li>TIM_CHANNEL_STATE_SET_ALL and TIM_CHANNEL_N_STATE_SET_ALL</li>
<li>TIM_CHANNEL_STATE_SET and TIM_CHANNEL_N_STATE_SET</li>
<li>TIM_CHANNEL_STATE_GET and TIM_CHANNEL_N_STATE_GET</li>
</ul></li>
<li>Add new API HAL_TIM_GetActiveChannel()</li>
<li>Add new API HAL_TIM_GetChannelState() to get actual state of the TIM channel</li>
<li>Add a new structure for TIM channel States definition : HAL_TIM_ChannelStateTypeDef</li>
<li>Update __HAL_TIM_RESET_HANDLE_STATE to support ChannelState and ChannelNState</li>
<li>Add a new element in the TIM_HandleTypeDef structure : ChannelState to manage TIM channel operation stat.</li>
<li>Add a new element in the TIM_HandleTypeDef structure : ChannelNState to manage TIM complementary channel operation state</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL USART</strong> update
<ul>
<li>Add support to the Receiver Timeout Interrupt in the HAL_USART_IRQHandler</li>
<li>Fix wrong value for SlaveMode field in USART handle after HAL_USARTEx_DisableSlaveMode() call
<ul>
<li>Set USART_SLAVEMODE_DISABLE instead of USART_SLAVEMODE_ENABLE</li>
</ul></li>
</ul></li>
<li><strong>HAL USB</strong> update
<ul>
<li>Improve USB endpoint out re-enabling with double-buffer mode.</li>
</ul></li>
<li><strong>LL UTILS</strong> update
<ul>
<li>API UTILS_SetFlashLatency() renamed LL_SetFlashLatency() and set exportable.</li>
<li>API LL_PLL_ConfigSystemClock_HSI() and API LL_PLL_ConfigSystemClock_HSE() updated to set back the AHB prescaler to 1 after it has been temporarily set to 2 to avoid undershoot when configuring PLL at high frequencies.</li>
</ul></li>
</ul>
<h2 id="development-toolchains-and-compilers-1">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1</li>
<li>STM32CubeIDE toolchain v1.3.0</li>
</ul>
<h2 id="supported-devices-1">Supported Devices</h2>
<ul>
<li>STM32G431/41xx</li>
<li>STM32G471xx</li>
<li>STM32G473/<strong>83xx</strong></li>
<li>STM32G474/84xx</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 28-June-2019</label>
<div>
<h2 id="main-changes-2">Main Changes</h2>
<h3 id="maintenance-release-2">Maintenance Release</h3>
<p>Maintenance release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32G431/41xx, STM32G471xx, STM32G473/83xx and STM32G474/84xx.</p>
<h2 id="contents">Contents</h2>
<table>
<caption>Additional features and changes :</caption>
<thead>
<tr class="header">
<th style="text-align: left;">Headline</th>
</tr>
</thead>
<tbody>
<tr class="odd">
<td style="text-align: left;">General: Support of device STM32G483xx in HAL and LL drivers</td>
</tr>
<tr class="even">
<td style="text-align: left;">COMP: Suppress Deglitcher mode - Not supported on STM32G4 series</td>
</tr>
<tr class="odd">
<td style="text-align: left;">HAL: Change naming of the IRQn 2 to RTC_TAMP_LSECSS_IRQn</td>
</tr>
<tr class="even">
<td style="text-align: left;">HRTIM: HRTIM_OUTPUTRESET_TIMAEVx renamed to HRTIM_OUTPUTRESET_TIMEVx</td>
</tr>
<tr class="odd">
<td style="text-align: left;">TIM: Add new macro to configure fast mode</td>
</tr>
<tr class="even">
<td style="text-align: left;">TIM: Master Slave Mode (MSM) is now configurable</td>
</tr>
</tbody>
</table>
<table>
<caption>Bugs fix :</caption>
<thead>
<tr class="header">
<th style="text-align: left;">Headline</th>
</tr>
</thead>
<tbody>
<tr class="odd">
<td style="text-align: left;">General : redefinition of registers with adjusted address MUST be volatile</td>
</tr>
<tr class="even">
<td style="text-align: left;">DMA : DMA2 instance cannot be configured in LL drivers</td>
</tr>
<tr class="odd">
<td style="text-align: left;">GPIO: HAL_GPIO_DeInit() bug on EXTI management</td>
</tr>
<tr class="even">
<td style="text-align: left;">GPIO: Compilation warning with IAR v8.30</td>
</tr>
<tr class="odd">
<td style="text-align: left;">HAL: Correct potential issue within HAL_SetTickFreq() function</td>
</tr>
<tr class="even">
<td style="text-align: left;">HRTIM: HRTIM_TIMxCR.DELCMP isn’t systematically programmed</td>
</tr>
<tr class="odd">
<td style="text-align: left;">HRTIM: Fault source programming isn’t wrong in HAL_HRTIM_FaultConfig</td>
</tr>
<tr class="even">
<td style="text-align: left;">HRTIM : Useless Assignment at function HAL_HRTIM_SimpleOCChannelConfig</td>
</tr>
<tr class="odd">
<td style="text-align: left;">RCC: Should not overwrite Tick priority</td>
</tr>
<tr class="even">
<td style="text-align: left;">RTC: HAL_RTCEx_SetWakeUpTimer WUTWF management reworked to be aligned with Reference Manual</td>
</tr>
<tr class="odd">
<td style="text-align: left;">RTC: INITF can rise too early when entering init mode just after exiting</td>
</tr>
<tr class="even">
<td style="text-align: left;">RTC : fix issue in define with STM32L4 LL RTC month macros</td>
</tr>
<tr class="odd">
<td style="text-align: left;">RTC : Remove ALRBWF and ALRAWF bits</td>
</tr>
<tr class="even">
<td style="text-align: left;">TIM: CodeSonar warnings about useless assignment in HAL_TIMEx_ConfigBreakInput()</td>
</tr>
</tbody>
</table>
<h2 id="development-toolchains-and-compilers-2">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
<li>System Workbench STM32 (SW4STM32) toolchain V2.7.2</li>
</ul>
<h2 id="supported-devices-2">Supported Devices</h2>
<ul>
<li>STM32G431/41xx</li>
<li>STM32G471xx</li>
<li>STM32G473/<strong>83xx</strong></li>
<li>STM32G474/84xx</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 12-April-2019</label>
<div>
<h2 id="main-changes-3">Main Changes</h2>
<h3 id="first-release">First release</h3>
<p>First official release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32G431/41xx, STM32G471xx, STM32G473/83xx and STM32G474/84xx.</p>
<h2 id="development-toolchains-and-compilers-3">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
<li>System Workbench STM32 (SW4STM32) toolchain V2.7.2</li>
</ul>
<h2 id="supported-devices-3">Supported Devices</h2>
<ul>
<li>STM32G431/41xx</li>
<li>STM32G471xx</li>
<li>STM32G473xx</li>
<li>STM32G474/84xx</li>
</ul>
</div>
</div>
</div>
</div>
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