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/**
******************************************************************************
* @file stm32g4xx_ll_hrtim.h
* @author MCD Application Team
* @brief Header file of HRTIM LL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_HRTIM_H
#define STM32G4xx_LL_HRTIM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
#if defined (HRTIM1)
/** @defgroup HRTIM_LL HRTIM
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup HRTIM_LL_Private_Variables HRTIM Private Variables
* @{
*/
static const uint16_t REG_OFFSET_TAB_TIMER[] =
{
0x00U, /* 0: MASTER */
0x80U, /* 1: TIMER A */
0x100U, /* 2: TIMER B */
0x180U, /* 3: TIMER C */
0x200U, /* 4: TIMER D */
0x280U, /* 5: TIMER E */
0x300U, /* 6: TIMER F */
};
static const uint8_t REG_OFFSET_TAB_ADCER[] =
{
0x00U, /* LL_HRTIM_ADCTRIG_1: HRTIM_ADC1R */
0x04U, /* LL_HRTIM_ADCTRIG_2: HRTIM_ADC2R */
0x08U, /* LL_HRTIM_ADCTRIG_3: HRTIM_ADC3R */
0x0CU, /* LL_HRTIM_ADCTRIG_4: HRTIM_ADC4R */
0x3CU, /* LL_HRTIM_ADCTRIG_5: HRTIM_ADCER */
0x3CU, /* LL_HRTIM_ADCTRIG_6: HRTIM_ADCER */
0x3CU, /* LL_HRTIM_ADCTRIG_7: HRTIM_ADCER */
0x3CU, /* LL_HRTIM_ADCTRIG_8: HRTIM_ADCER */
0x3CU, /* LL_HRTIM_ADCTRIG_9: HRTIM_ADCER */
0x3CU, /* LL_HRTIM_ADCTRIG_10: HRTIM_ADCER */
};
static const uint8_t REG_OFFSET_TAB_ADCUR[] =
{
0x00U, /* LL_HRTIM_ADCTRIG_1: HRTIM_CR1 */
0x00U, /* LL_HRTIM_ADCTRIG_2: HRTIM_CR1 */
0x00U, /* LL_HRTIM_ADCTRIG_3: HRTIM_CR1 */
0x00U, /* LL_HRTIM_ADCTRIG_4: HRTIM_CR1 */
0x7CU, /* LL_HRTIM_ADCTRIG_5: HRTIM_ADCUR */
0x7CU, /* LL_HRTIM_ADCTRIG_6: HRTIM_ADCUR */
0x7CU, /* LL_HRTIM_ADCTRIG_7: HRTIM_ADCUR */
0x7CU, /* LL_HRTIM_ADCTRIG_8: HRTIM_ADCUR */
0x7CU, /* LL_HRTIM_ADCTRIG_9: HRTIM_ADCUR */
0x7CU, /* LL_HRTIM_ADCTRIG_10: HRTIM_ADCUR */
};
static const uint8_t REG_SHIFT_TAB_ADCER[] =
{
0, /* LL_HRTIM_ADCTRIG_1 */
0, /* LL_HRTIM_ADCTRIG_2 */
0, /* LL_HRTIM_ADCTRIG_3 */
0, /* LL_HRTIM_ADCTRIG_4 */
0, /* LL_HRTIM_ADCTRIG_5 */
5, /* LL_HRTIM_ADCTRIG_6 */
10, /* LL_HRTIM_ADCTRIG_7 */
16, /* LL_HRTIM_ADCTRIG_8 */
21, /* LL_HRTIM_ADCTRIG_9 */
26 /* LL_HRTIM_ADCTRIG_10 */
};
static const uint8_t REG_SHIFT_TAB_ADCUR[] =
{
16, /* LL_HRTIM_ADCTRIG_1 */
19, /* LL_HRTIM_ADCTRIG_2 */
22, /* LL_HRTIM_ADCTRIG_3 */
25, /* LL_HRTIM_ADCTRIG_4 */
0, /* LL_HRTIM_ADCTRIG_5 */
4, /* LL_HRTIM_ADCTRIG_6 */
8, /* LL_HRTIM_ADCTRIG_7 */
12, /* LL_HRTIM_ADCTRIG_8 */
16, /* LL_HRTIM_ADCTRIG_9 */
20 /* LL_HRTIM_ADCTRIG_10 */
};
static const uint32_t REG_MASK_TAB_ADCER[] =
{
0xFFFFFFFFU, /* LL_HRTIM_ADCTRIG_1 */
0xFFFFFFFFU, /* LL_HRTIM_ADCTRIG_2 */
0xFFFFFFFFU, /* LL_HRTIM_ADCTRIG_3 */
0xFFFFFFFFU, /* LL_HRTIM_ADCTRIG_4 */
0x0000001FU, /* LL_HRTIM_ADCTRIG_5 */
0x000003E0U, /* LL_HRTIM_ADCTRIG_6 */
0x00007C00U, /* LL_HRTIM_ADCTRIG_7 */
0x001F0000U, /* LL_HRTIM_ADCTRIG_8 */
0x03E00000U, /* LL_HRTIM_ADCTRIG_9 */
0x7C000000U /* LL_HRTIM_ADCTRIG_10 */
};
static const uint32_t REG_MASK_TAB_ADCUR[] =
{
0x00070000U, /* LL_HRTIM_ADCTRIG_1 */
0x00380000U, /* LL_HRTIM_ADCTRIG_2 */
0x01C00000U, /* LL_HRTIM_ADCTRIG_3 */
0x0E000000U, /* LL_HRTIM_ADCTRIG_4 */
0x00000007U, /* LL_HRTIM_ADCTRIG_5 */
0x00000070U, /* LL_HRTIM_ADCTRIG_6 */
0x00000700U, /* LL_HRTIM_ADCTRIG_7 */
0x00007000U, /* LL_HRTIM_ADCTRIG_8 */
0x00070000U, /* LL_HRTIM_ADCTRIG_9 */
0x00700000U /* LL_HRTIM_ADCTRIG_10 */
};
static const uint8_t REG_OFFSET_TAB_ADCPSx[] =
{
0U, /* 0: HRTIM_ADC1R */
6U, /* 1: HRTIM_ADC2R */
12U, /* 2: HRTIM_ADC3R */
18U, /* 3: HRTIM_ADC4R */
24U, /* 4: HRTIM_ADC5R */
32U, /* 5: HRTIM_ADC6R */
38U, /* 6: HRTIM_ADC7R */
44U, /* 7: HRTIM_ADC8R */
50U, /* 8: HRTIM_ADC9R */
56U /* 9: HRTIM_ADC10R */
};
static const uint16_t REG_OFFSET_TAB_SETxR[] =
{
0x00U, /* 0: TA1 */
0x08U, /* 1: TA2 */
0x80U, /* 2: TB1 */
0x88U, /* 3: TB2 */
0x100U, /* 4: TC1 */
0x108U, /* 5: TC2 */
0x180U, /* 6: TD1 */
0x188U, /* 7: TD2 */
0x200U, /* 8: TE1 */
0x208U, /* 9: TE2 */
0x280U, /* 10: TF1 */
0x288U /* 11: TF2 */
};
static const uint16_t REG_OFFSET_TAB_OUTxR[] =
{
0x00U, /* 0: TA1 */
0x00U, /* 1: TA2 */
0x80U, /* 2: TB1 */
0x80U, /* 3: TB2 */
0x100U, /* 4: TC1 */
0x100U, /* 5: TC2 */
0x180U, /* 6: TD1 */
0x180U, /* 7: TD2 */
0x200U, /* 8: TE1 */
0x200U, /* 9: TE2 */
0x280U, /* 10: TF1 */
0x280U /* 11: TF2 */
};
static const uint8_t REG_OFFSET_TAB_EECR[] =
{
0x00U, /* LL_HRTIM_EVENT_1 */
0x00U, /* LL_HRTIM_EVENT_2 */
0x00U, /* LL_HRTIM_EVENT_3 */
0x00U, /* LL_HRTIM_EVENT_4 */
0x00U, /* LL_HRTIM_EVENT_5 */
0x04U, /* LL_HRTIM_EVENT_6 */
0x04U, /* LL_HRTIM_EVENT_7 */
0x04U, /* LL_HRTIM_EVENT_8 */
0x04U, /* LL_HRTIM_EVENT_9 */
0x04U /* LL_HRTIM_EVENT_10 */
};
static const uint8_t REG_OFFSET_TAB_FLTINR[] =
{
0x00U, /* LL_HRTIM_FAULT_1 */
0x00U, /* LL_HRTIM_FAULT_2 */
0x00U, /* LL_HRTIM_FAULT_3 */
0x00U, /* LL_HRTIM_FAULT_4 */
0x04U, /* LL_HRTIM_FAULT_5 */
0x04U /* LL_HRTIM_FAULT_6 */
};
static const uint32_t REG_MASK_TAB_UPDATETRIG[] =
{
0x20000000U, /* 0: MASTER */
0x01FF0000U, /* 1: TIMER A */
0x01FF0000U, /* 2: TIMER B */
0x01FF0000U, /* 3: TIMER C */
0x01FF0000U, /* 4: TIMER D */
0x01FF0000U, /* 5: TIMER E */
0x01FF0000U, /* 5: TIMER E */
0x01FF0000U /* 6: TIMER F */
};
static const uint8_t REG_SHIFT_TAB_UPDATETRIG[] =
{
12U, /* 0: MASTER */
0U, /* 1: TIMER A */
0U, /* 2: TIMER B */
0U, /* 3: TIMER C */
0U, /* 4: TIMER D */
0U, /* 5: TIMER E */
0U /* 6: TIMER F */
};
static const uint8_t REG_SHIFT_TAB_EExSRC[] =
{
0U, /* LL_HRTIM_EVENT_1 */
6U, /* LL_HRTIM_EVENT_2 */
12U, /* LL_HRTIM_EVENT_3 */
18U, /* LL_HRTIM_EVENT_4 */
24U, /* LL_HRTIM_EVENT_5 */
0U, /* LL_HRTIM_EVENT_6 */
6U, /* LL_HRTIM_EVENT_7 */
12U, /* LL_HRTIM_EVENT_8 */
18U, /* LL_HRTIM_EVENT_9 */
24U /* LL_HRTIM_EVENT_10 */
};
static const uint32_t REG_MASK_TAB_UPDATEGATING[] =
{
HRTIM_MCR_BRSTDMA, /* 0: MASTER */
HRTIM_TIMCR_UPDGAT, /* 1: TIMER A */
HRTIM_TIMCR_UPDGAT, /* 2: TIMER B */
HRTIM_TIMCR_UPDGAT, /* 3: TIMER C */
HRTIM_TIMCR_UPDGAT, /* 4: TIMER D */
HRTIM_TIMCR_UPDGAT, /* 5: TIMER E */
HRTIM_TIMCR_UPDGAT /* 6: TIMER F */
};
static const uint8_t REG_SHIFT_TAB_UPDATEGATING[] =
{
2U, /* 0: MASTER */
0U, /* 1: TIMER A */
0U, /* 2: TIMER B */
0U, /* 3: TIMER C */
0U, /* 4: TIMER D */
0U, /* 5: TIMER E */
0U /* 6: TIMER F */
};
static const uint8_t REG_SHIFT_TAB_OUTxR[] =
{
0U, /* 0: TA1 */
16U, /* 1: TA2 */
0U, /* 2: TB1 */
16U, /* 3: TB2 */
0U, /* 4: TC1 */
16U, /* 5: TC2 */
0U, /* 6: TD1 */
16U, /* 7: TD2 */
0U, /* 8: TE1 */
16U, /* 9: TE2 */
0U, /* 10: TF1 */
16U /* 11: TF2 */
};
static const uint8_t REG_SHIFT_TAB_OxSTAT[] =
{
0U, /* 0: TA1 */
1U, /* 1: TA2 */
0U, /* 2: TB1 */
1U, /* 3: TB2 */
0U, /* 4: TC1 */
1U, /* 5: TC2 */
0U, /* 6: TD1 */
1U, /* 7: TD2 */
0U, /* 8: TE1 */
1U, /* 9: TE2 */
0U, /* 10: TF1 */
1U /* 11: TF2 */
};
static const uint8_t REG_SHIFT_TAB_FLTxE[] =
{
0U, /* LL_HRTIM_FAULT_1 */
8U, /* LL_HRTIM_FAULT_2 */
16U, /* LL_HRTIM_FAULT_3 */
24U, /* LL_HRTIM_FAULT_4 */
0U, /* LL_HRTIM_FAULT_5 */
8U /* LL_HRTIM_FAULT_6 */
};
static const uint8_t REG_SHIFT_TAB_FLTxF[] =
{
0U, /* LL_HRTIM_FAULT_1 */
8U, /* LL_HRTIM_FAULT_2 */
16U, /* LL_HRTIM_FAULT_3 */
24U, /* LL_HRTIM_FAULT_4 */
32U, /* LL_HRTIM_FAULT_5 */
40U /* LL_HRTIM_FAULT_6 */
};
static const uint8_t REG_SHIFT_TAB_FLTx[] =
{
0, /* LL_HRTIM_FAULT_1 */
1, /* LL_HRTIM_FAULT_2 */
2, /* LL_HRTIM_FAULT_3 */
3, /* LL_HRTIM_FAULT_4 */
4, /* LL_HRTIM_FAULT_5 */
5 /* LL_HRTIM_FAULT_6 */
};
static const uint8_t REG_SHIFT_TAB_INTLVD[] =
{
0U, /* 0: MASTER */
1U, /* 1: TIMER A */
1U, /* 2: TIMER B */
1U, /* 3: TIMER C */
1U, /* 4: TIMER D */
1U, /* 5: TIMER E */
1U, /* 6: TIMER F */
};
static const uint32_t REG_MASK_TAB_INTLVD[] =
{
0x000000E0U, /* 0: MASTER */
0x000001A0U, /* 1: TIMER A */
0x000001A0U, /* 2: TIMER B */
0x000001A0U, /* 3: TIMER C */
0x000001A0U, /* 4: TIMER D */
0x000001A0U, /* 5: TIMER E */
0x000001A0U, /* 6: TIMER F */
};
static const uint8_t REG_SHIFT_TAB_CPT[] =
{
12U, /* 1: TIMER A */
16U, /* 2: TIMER B */
20U, /* 3: TIMER C */
24U, /* 4: TIMER D */
28U, /* 5: TIMER E */
32U, /* 6: TIMER F */
};
static const uint32_t REG_MASK_TAB_CPT[] =
{
0xFFFF0000U, /* 1: TIMER A */
0xFFF0F000U, /* 2: TIMER B */
0xFF0FF000U, /* 3: TIMER C */
0xF0FFF000U, /* 4: TIMER D */
0x0FFFF000U, /* 5: TIMER E */
0xFFFFF000U, /* 6: TIMER F */
};
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup HRTIM_LL_Private_Constants HRTIM Private Constants
* @{
*/
#define HRTIM_CR1_UDIS_MASK ((uint32_t)(HRTIM_CR1_MUDIS |\
HRTIM_CR1_TAUDIS |\
HRTIM_CR1_TBUDIS |\
HRTIM_CR1_TCUDIS |\
HRTIM_CR1_TDUDIS |\
HRTIM_CR1_TEUDIS |\
HRTIM_CR1_TFUDIS))
#define HRTIM_CR2_SWUPD_MASK ((uint32_t)(HRTIM_CR2_MSWU |\
HRTIM_CR2_TASWU |\
HRTIM_CR2_TBSWU |\
HRTIM_CR2_TCSWU |\
HRTIM_CR2_TDSWU |\
HRTIM_CR2_TESWU |\
HRTIM_CR2_TFSWU))
#define HRTIM_CR2_SWAP_MASK ((uint32_t)(HRTIM_CR2_SWPA |\
HRTIM_CR2_SWPB |\
HRTIM_CR2_SWPC |\
HRTIM_CR2_SWPD |\
HRTIM_CR2_SWPE |\
HRTIM_CR2_SWPF))
#define HRTIM_CR2_SWRST_MASK ((uint32_t)(HRTIM_CR2_MRST |\
HRTIM_CR2_TARST |\
HRTIM_CR2_TBRST |\
HRTIM_CR2_TCRST |\
HRTIM_CR2_TDRST |\
HRTIM_CR2_TERST |\
HRTIM_CR2_TFRST))
#define HRTIM_OENR_OEN_MASK ((uint32_t)(HRTIM_OENR_TA1OEN |\
HRTIM_OENR_TA2OEN |\
HRTIM_OENR_TB1OEN |\
HRTIM_OENR_TB2OEN |\
HRTIM_OENR_TC1OEN |\
HRTIM_OENR_TC2OEN |\
HRTIM_OENR_TD1OEN |\
HRTIM_OENR_TD2OEN |\
HRTIM_OENR_TE1OEN |\
HRTIM_OENR_TE2OEN |\
HRTIM_OENR_TF1OEN |\
HRTIM_OENR_TF2OEN))
#define HRTIM_OENR_ODIS_MASK ((uint32_t)(HRTIM_ODISR_TA1ODIS |\
HRTIM_ODISR_TA2ODIS |\
HRTIM_ODISR_TB1ODIS |\
HRTIM_ODISR_TB2ODIS |\
HRTIM_ODISR_TC1ODIS |\
HRTIM_ODISR_TC2ODIS |\
HRTIM_ODISR_TD1ODIS |\
HRTIM_ODISR_TD2ODIS |\
HRTIM_ODISR_TE1ODIS |\
HRTIM_ODISR_TE2ODIS |\
HRTIM_ODISR_TF1ODIS |\
HRTIM_ODISR_TF2ODIS))
#define HRTIM_OUT_CONFIG_MASK ((uint32_t)(HRTIM_OUTR_POL1 |\
HRTIM_OUTR_IDLM1 |\
HRTIM_OUTR_IDLES1 |\
HRTIM_OUTR_FAULT1 |\
HRTIM_OUTR_CHP1 |\
HRTIM_OUTR_DIDL1))
#define HRTIM_EE_CONFIG_MASK ((uint32_t)(HRTIM_EECR1_EE1SRC |\
HRTIM_EECR1_EE1POL |\
HRTIM_EECR1_EE1SNS |\
HRTIM_EECR1_EE1FAST))
#define HRTIM_FLT_CONFIG_MASK ((uint32_t)(HRTIM_FLTINR1_FLT1P |\
HRTIM_FLTINR1_FLT1SRC_0 ))
#define HRTIM_FLT_SRC_1_MASK ((uint32_t)(HRTIM_FLTINR2_FLT6SRC_1 |\
HRTIM_FLTINR2_FLT5SRC_1 |\
HRTIM_FLTINR2_FLT4SRC_1 |\
HRTIM_FLTINR2_FLT3SRC_1 |\
HRTIM_FLTINR2_FLT2SRC_1 |\
HRTIM_FLTINR2_FLT1SRC_1))
#define HRTIM_BM_CONFIG_MASK ((uint32_t)( HRTIM_BMCR_BMPRSC |\
HRTIM_BMCR_BMCLK |\
HRTIM_BMCR_BMOM))
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup HRTIM_LL_Exported_Constants HRTIM Exported Constants
* @{
*/
/** @defgroup HRTIM_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_HRTIM_ReadReg function
* @{
*/
#define LL_HRTIM_ISR_FLT1 HRTIM_ISR_FLT1
#define LL_HRTIM_ISR_FLT2 HRTIM_ISR_FLT2
#define LL_HRTIM_ISR_FLT3 HRTIM_ISR_FLT3
#define LL_HRTIM_ISR_FLT4 HRTIM_ISR_FLT4
#define LL_HRTIM_ISR_FLT5 HRTIM_ISR_FLT5
#define LL_HRTIM_ISR_FLT6 HRTIM_ISR_FLT6
#define LL_HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT
#define LL_HRTIM_ISR_DLLRDY HRTIM_ISR_DLLRDY
#define LL_HRTIM_ISR_BMPER HRTIM_ISR_BMPER
#define LL_HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1
#define LL_HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2
#define LL_HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3
#define LL_HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4
#define LL_HRTIM_MISR_MREP HRTIM_MISR_MREP
#define LL_HRTIM_MISR_SYNC HRTIM_MISR_SYNC
#define LL_HRTIM_MISR_MUPD HRTIM_MISR_MUPD
#define LL_HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1
#define LL_HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2
#define LL_HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3
#define LL_HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4
#define LL_HRTIM_TIMISR_REP HRTIM_TIMISR_REP
#define LL_HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD
#define LL_HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1
#define LL_HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2
#define LL_HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1
#define LL_HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1
#define LL_HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2
#define LL_HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2
#define LL_HRTIM_TIMISR_RST HRTIM_TIMISR_RST
#define LL_HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_HRTIM_ReadReg and LL_HRTIM_WriteReg functions
* @{
*/
#define LL_HRTIM_IER_FLT1IE HRTIM_IER_FLT1IE
#define LL_HRTIM_IER_FLT2IE HRTIM_IER_FLT2IE
#define LL_HRTIM_IER_FLT3IE HRTIM_IER_FLT3IE
#define LL_HRTIM_IER_FLT4IE HRTIM_IER_FLT4IE
#define LL_HRTIM_IER_FLT5IE HRTIM_IER_FLT5IE
#define LL_HRTIM_IER_FLT6IE HRTIM_IER_FLT6IE
#define LL_HRTIM_IER_SYSFLTIE HRTIM_IER_SYSFLTIE
#define LL_HRTIM_IER_DLLRDYIE HRTIM_IER_DLLRDYIE
#define LL_HRTIM_IER_BMPERIE HRTIM_IER_BMPERIE
#define LL_HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE
#define LL_HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE
#define LL_HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE
#define LL_HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE
#define LL_HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE
#define LL_HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE
#define LL_HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE
#define LL_HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE
#define LL_HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE
#define LL_HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE
#define LL_HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE
#define LL_HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE
#define LL_HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE
#define LL_HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE
#define LL_HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE
#define LL_HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE
#define LL_HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE
#define LL_HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE
#define LL_HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE
#define LL_HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE
#define LL_HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_SYNCIN_SRC SYNCHRONIZATION INPUT SOURCE
* @{
* @brief Constants defining defining the synchronization input source.
*/
#define LL_HRTIM_SYNCIN_SRC_NONE 0x00000000U /*!< HRTIM is not synchronized and runs in standalone mode */
#define LL_HRTIM_SYNCIN_SRC_TIM_EVENT (HRTIM_MCR_SYNC_IN_1) /*!< The HRTIM is synchronized with the on-chip timer */
#define LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_SYNCOUT_SRC SYNCHRONIZATION OUTPUT SOURCE
* @{
* @brief Constants defining the source and event to be sent on the synchronization output.
*/
#define LL_HRTIM_SYNCOUT_SRC_MASTER_START 0x00000000U /*!< A pulse is sent on the SYNCOUT output upon master timer start event */
#define LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/
#define LL_HRTIM_SYNCOUT_SRC_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */
#define LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_SYNCOUT_POLARITY SYNCHRONIZATION OUTPUT POLARITY
* @{
* @brief Constants defining the routing and conditioning of the synchronization output event.
*/
#define LL_HRTIM_SYNCOUT_DISABLED 0x00000000U /*!< Synchronization output event is disabled */
#define LL_HRTIM_SYNCOUT_POSITIVE_PULSE (HRTIM_MCR_SYNC_OUT_1) /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */
#define LL_HRTIM_SYNCOUT_NEGATIVE_PULSE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_TIMER TIMER ID
* @{
* @brief Constants identifying a timing unit.
*/
#define LL_HRTIM_TIMER_NONE 0U /*!< Master timer identifier */
#define LL_HRTIM_TIMER_MASTER HRTIM_MCR_MCEN /*!< Master timer identifier */
#define LL_HRTIM_TIMER_A HRTIM_MCR_TACEN /*!< Timer A identifier */
#define LL_HRTIM_TIMER_B HRTIM_MCR_TBCEN /*!< Timer B identifier */
#define LL_HRTIM_TIMER_C HRTIM_MCR_TCCEN /*!< Timer C identifier */
#define LL_HRTIM_TIMER_D HRTIM_MCR_TDCEN /*!< Timer D identifier */
#define LL_HRTIM_TIMER_E HRTIM_MCR_TECEN /*!< Timer E identifier */
#define LL_HRTIM_TIMER_F HRTIM_MCR_TFCEN /*!< Timer F identifier */
#define LL_HRTIM_TIMER_X (HRTIM_MCR_TFCEN | HRTIM_MCR_TACEN |\
HRTIM_MCR_TBCEN | HRTIM_MCR_TCCEN |\
HRTIM_MCR_TDCEN | HRTIM_MCR_TECEN )
#define LL_HRTIM_TIMER_ALL (LL_HRTIM_TIMER_MASTER | LL_HRTIM_TIMER_X)
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_OUTPUT OUTPUT ID
* @{
* @brief Constants identifying an HRTIM output.
*/
#define LL_HRTIM_OUTPUT_TA1 HRTIM_OENR_TA1OEN /*!< Timer A - Output 1 identifier */
#define LL_HRTIM_OUTPUT_TA2 HRTIM_OENR_TA2OEN /*!< Timer A - Output 2 identifier */
#define LL_HRTIM_OUTPUT_TB1 HRTIM_OENR_TB1OEN /*!< Timer B - Output 1 identifier */
#define LL_HRTIM_OUTPUT_TB2 HRTIM_OENR_TB2OEN /*!< Timer B - Output 2 identifier */
#define LL_HRTIM_OUTPUT_TC1 HRTIM_OENR_TC1OEN /*!< Timer C - Output 1 identifier */
#define LL_HRTIM_OUTPUT_TC2 HRTIM_OENR_TC2OEN /*!< Timer C - Output 2 identifier */
#define LL_HRTIM_OUTPUT_TD1 HRTIM_OENR_TD1OEN /*!< Timer D - Output 1 identifier */
#define LL_HRTIM_OUTPUT_TD2 HRTIM_OENR_TD2OEN /*!< Timer D - Output 2 identifier */
#define LL_HRTIM_OUTPUT_TE1 HRTIM_OENR_TE1OEN /*!< Timer E - Output 1 identifier */
#define LL_HRTIM_OUTPUT_TE2 HRTIM_OENR_TE2OEN /*!< Timer E - Output 2 identifier */
#define LL_HRTIM_OUTPUT_TF1 HRTIM_OENR_TF1OEN /*!< Timer F - Output 1 identifier */
#define LL_HRTIM_OUTPUT_TF2 HRTIM_OENR_TF2OEN /*!< Timer F - Output 2 identifier */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_COMPAREUNIT COMPARE UNIT ID
* @{
* @brief Constants identifying a compare unit.
*/
#define LL_HRTIM_COMPAREUNIT_2 HRTIM_TIMCR_DELCMP2 /*!< Compare unit 2 identifier */
#define LL_HRTIM_COMPAREUNIT_4 HRTIM_TIMCR_DELCMP4 /*!< Compare unit 4 identifier */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_CAPTUREUNIT CAPTURE UNIT ID
* @{
* @brief Constants identifying a capture unit.
*/
#define LL_HRTIM_CAPTUREUNIT_1 0 /*!< Capture unit 1 identifier */
#define LL_HRTIM_CAPTUREUNIT_2 1 /*!< Capture unit 2 identifier */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_FAULT FAULT ID
* @{
* @brief Constants identifying a fault channel.
*/
#define LL_HRTIM_FAULT_1 HRTIM_FLTR_FLT1EN /*!< Fault channel 1 identifier */
#define LL_HRTIM_FAULT_2 HRTIM_FLTR_FLT2EN /*!< Fault channel 2 identifier */
#define LL_HRTIM_FAULT_3 HRTIM_FLTR_FLT3EN /*!< Fault channel 3 identifier */
#define LL_HRTIM_FAULT_4 HRTIM_FLTR_FLT4EN /*!< Fault channel 4 identifier */
#define LL_HRTIM_FAULT_5 HRTIM_FLTR_FLT5EN /*!< Fault channel 5 identifier */
#define LL_HRTIM_FAULT_6 HRTIM_FLTR_FLT6EN /*!< Fault channel 6 identifier */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_EVENT EXTERNAL EVENT ID
* @{
* @brief Constants identifying an external event channel.
*/
#define LL_HRTIM_EVENT_1 ((uint32_t)0x00000001U) /*!< External event channel 1 identifier */
#define LL_HRTIM_EVENT_2 ((uint32_t)0x00000002U) /*!< External event channel 2 identifier */
#define LL_HRTIM_EVENT_3 ((uint32_t)0x00000004U) /*!< External event channel 3 identifier */
#define LL_HRTIM_EVENT_4 ((uint32_t)0x00000008U) /*!< External event channel 4 identifier */
#define LL_HRTIM_EVENT_5 ((uint32_t)0x00000010U) /*!< External event channel 5 identifier */
#define LL_HRTIM_EVENT_6 ((uint32_t)0x00000020U) /*!< External event channel 6 identifier */
#define LL_HRTIM_EVENT_7 ((uint32_t)0x00000040U) /*!< External event channel 7 identifier */
#define LL_HRTIM_EVENT_8 ((uint32_t)0x00000080U) /*!< External event channel 8 identifier */
#define LL_HRTIM_EVENT_9 ((uint32_t)0x00000100U) /*!< External event channel 9 identifier */
#define LL_HRTIM_EVENT_10 ((uint32_t)0x00000200U) /*!< External event channel 10 identifier */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_OUTPUTSTATE OUTPUT STATE
* @{
* @brief Constants defining the state of an HRTIM output.
*/
#define LL_HRTIM_OUTPUTSTATE_IDLE ((uint32_t)0x00000001U) /*!< Main operating mode, where the output can take the active or inactive level as programmed in the crossbar unit */
#define LL_HRTIM_OUTPUTSTATE_RUN ((uint32_t)0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the outputs are disabled by software or during a burst mode operation) */
#define LL_HRTIM_OUTPUTSTATE_FAULT ((uint32_t)0x00000003U) /*!< Safety state, entered in case of a shut-down request on FAULTx inputs */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_ADCTRIG ADC TRIGGER
* @{
* @brief Constants identifying an ADC trigger.
*/
#define LL_HRTIM_ADCTRIG_1 ((uint32_t)0x00000000U) /*!< ADC trigger 1 identifier */
#define LL_HRTIM_ADCTRIG_2 ((uint32_t)0x00000001U) /*!< ADC trigger 2 identifier */
#define LL_HRTIM_ADCTRIG_3 ((uint32_t)0x00000002U) /*!< ADC trigger 3 identifier */
#define LL_HRTIM_ADCTRIG_4 ((uint32_t)0x00000003U) /*!< ADC trigger 4 identifier */
#define LL_HRTIM_ADCTRIG_5 ((uint32_t)0x00000004U) /*!< ADC trigger 5 identifier */
#define LL_HRTIM_ADCTRIG_6 ((uint32_t)0x00000005U) /*!< ADC trigger 6 identifier */
#define LL_HRTIM_ADCTRIG_7 ((uint32_t)0x00000006U) /*!< ADC trigger 7 identifier */
#define LL_HRTIM_ADCTRIG_8 ((uint32_t)0x00000007U) /*!< ADC trigger 8 identifier */
#define LL_HRTIM_ADCTRIG_9 ((uint32_t)0x00000008U) /*!< ADC trigger 9 identifier */
#define LL_HRTIM_ADCTRIG_10 ((uint32_t)0x00000009U) /*!< ADC trigger 10 identifier */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_ADCTRIG_UPDATE ADC TRIGGER UPDATE
* @{
* @brief constants defining the source triggering the update of the HRTIM_ADCxR register (transfer from preload to active register).
*/
#define LL_HRTIM_ADCTRIG_UPDATE_MASTER 0x00000000U /*!< HRTIM_ADCxR register update is triggered by the Master timer */
#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_A 0x00000001U /*!< HRTIM_ADCxR register update is triggered by the Timer A */
#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_B 0x00000002U /*!< HRTIM_ADCxR register update is triggered by the Timer B */
#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_C 0x00000003U /*!< HRTIM_ADCxR register update is triggered by the Timer C */
#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_D 0x00000004U /*!< HRTIM_ADCxR register update is triggered by the Timer D */
#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_E 0x00000005U /*!< HRTIM_ADCxR register update is triggered by the Timer E */
#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_F 0x00000006U /*!< HRTIM_ADCxR register update is triggered by the Timer F */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_ADCTRIG_SRC13 ADC TRIGGER 1/3 SOURCE
* @{
* @brief constants defining the events triggering ADC conversion for ADC Triggers 1 and 3.
*/
#define LL_HRTIM_ADCTRIG_SRC13_NONE 0x00000000U /*!< No ADC trigger event */
#define LL_HRTIM_ADCTRIG_SRC13_MCMP1 HRTIM_ADC1R_AD1MC1 /*!< ADC Trigger on master compare 1 */
#define LL_HRTIM_ADCTRIG_SRC13_MCMP2 HRTIM_ADC1R_AD1MC2 /*!< ADC Trigger on master compare 2 */
#define LL_HRTIM_ADCTRIG_SRC13_MCMP3 HRTIM_ADC1R_AD1MC3 /*!< ADC Trigger on master compare 3 */
#define LL_HRTIM_ADCTRIG_SRC13_MCMP4 HRTIM_ADC1R_AD1MC4 /*!< ADC Trigger on master compare 4 */
#define LL_HRTIM_ADCTRIG_SRC13_MPER HRTIM_ADC1R_AD1MPER /*!< ADC Trigger on master period */
#define LL_HRTIM_ADCTRIG_SRC13_EEV1 HRTIM_ADC1R_AD1EEV1 /*!< ADC Trigger on external event 1 */
#define LL_HRTIM_ADCTRIG_SRC13_EEV2 HRTIM_ADC1R_AD1EEV2 /*!< ADC Trigger on external event 2 */
#define LL_HRTIM_ADCTRIG_SRC13_EEV3 HRTIM_ADC1R_AD1EEV3 /*!< ADC Trigger on external event 3 */
#define LL_HRTIM_ADCTRIG_SRC13_EEV4 HRTIM_ADC1R_AD1EEV4 /*!< ADC Trigger on external event 4 */
#define LL_HRTIM_ADCTRIG_SRC13_EEV5 HRTIM_ADC1R_AD1EEV5 /*!< ADC Trigger on external event 5 */
#define LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2 HRTIM_ADC1R_AD1TFC2 /*!< ADC Trigger on Timer F compare 2 */
#define LL_HRTIM_ADCTRIG_SRC13_TIMACMP3 HRTIM_ADC1R_AD1TAC3 /*!< ADC Trigger on Timer A compare 3 */
#define LL_HRTIM_ADCTRIG_SRC13_TIMACMP4 HRTIM_ADC1R_AD1TAC4 /*!< ADC Trigger on Timer A compare 4 */
#define LL_HRTIM_ADCTRIG_SRC13_TIMAPER HRTIM_ADC1R_AD1TAPER /*!< ADC Trigger on Timer A period */
#define LL_HRTIM_ADCTRIG_SRC13_TIMARST HRTIM_ADC1R_AD1TARST /*!< ADC Trigger on Timer A reset */
#define LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3 HRTIM_ADC1R_AD1TFC3 /*!< ADC Trigger on Timer F compare 3 */
#define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3 HRTIM_ADC1R_AD1TBC3 /*!< ADC Trigger on Timer B compare 3 */
#define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4 HRTIM_ADC1R_AD1TBC4 /*!< ADC Trigger on Timer B compare 4 */
#define LL_HRTIM_ADCTRIG_SRC13_TIMBPER HRTIM_ADC1R_AD1TBPER /*!< ADC Trigger on Timer B period */
#define LL_HRTIM_ADCTRIG_SRC13_TIMBRST HRTIM_ADC1R_AD1TBRST /*!< ADC Trigger on Timer B reset */
#define LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4 HRTIM_ADC1R_AD1TFC4 /*!< ADC Trigger on Timer F compare 4 */
#define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3 HRTIM_ADC1R_AD1TCC3 /*!< ADC Trigger on Timer C compare 3 */
#define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4 HRTIM_ADC1R_AD1TCC4 /*!< ADC Trigger on Timer C compare 4 */
#define LL_HRTIM_ADCTRIG_SRC13_TIMCPER HRTIM_ADC1R_AD1TCPER /*!< ADC Trigger on Timer C period */
#define LL_HRTIM_ADCTRIG_SRC13_TIMFPER HRTIM_ADC1R_AD1TFPER /*!< ADC Trigger on Timer F period */
#define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3 HRTIM_ADC1R_AD1TDC3 /*!< ADC Trigger on Timer D compare 3 */
#define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4 HRTIM_ADC1R_AD1TDC4 /*!< ADC Trigger on Timer D compare 4 */
#define LL_HRTIM_ADCTRIG_SRC13_TIMDPER HRTIM_ADC1R_AD1TDPER /*!< ADC Trigger on Timer D period */
#define LL_HRTIM_ADCTRIG_SRC13_TIMFRST HRTIM_ADC1R_AD1TFRST /*!< ADC Trigger on Timer F reset */
#define LL_HRTIM_ADCTRIG_SRC13_TIMECMP3 HRTIM_ADC1R_AD1TEC3 /*!< ADC Trigger on Timer E compare 3 */
#define LL_HRTIM_ADCTRIG_SRC13_TIMECMP4 HRTIM_ADC1R_AD1TEC4 /*!< ADC Trigger on Timer E compare 4 */
#define LL_HRTIM_ADCTRIG_SRC13_TIMEPER HRTIM_ADC1R_AD1TEPER /*!< ADC Trigger on Timer E period */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_ADCTRIG_SRC24 ADC TRIGGER 2/4 SOURCE
* @{
* @brief constants defining the events triggering ADC conversion for ADC Triggers 2 and 4.
*/
#define LL_HRTIM_ADCTRIG_SRC24_NONE 0x00000000U /*!< No ADC trigger event */
#define LL_HRTIM_ADCTRIG_SRC24_MCMP1 HRTIM_ADC2R_AD2MC1 /*!< ADC Trigger on master compare 1 */
#define LL_HRTIM_ADCTRIG_SRC24_MCMP2 HRTIM_ADC2R_AD2MC2 /*!< ADC Trigger on master compare 2 */
#define LL_HRTIM_ADCTRIG_SRC24_MCMP3 HRTIM_ADC2R_AD2MC3 /*!< ADC Trigger on master compare 3 */
#define LL_HRTIM_ADCTRIG_SRC24_MCMP4 HRTIM_ADC2R_AD2MC4 /*!< ADC Trigger on master compare 4 */
#define LL_HRTIM_ADCTRIG_SRC24_MPER HRTIM_ADC2R_AD2MPER /*!< ADC Trigger on master period */
#define LL_HRTIM_ADCTRIG_SRC24_EEV6 HRTIM_ADC2R_AD2EEV6 /*!< ADC Trigger on external event 6 */
#define LL_HRTIM_ADCTRIG_SRC24_EEV7 HRTIM_ADC2R_AD2EEV7 /*!< ADC Trigger on external event 7 */
#define LL_HRTIM_ADCTRIG_SRC24_EEV8 HRTIM_ADC2R_AD2EEV8 /*!< ADC Trigger on external event 8 */
#define LL_HRTIM_ADCTRIG_SRC24_EEV9 HRTIM_ADC2R_AD2EEV9 /*!< ADC Trigger on external event 9 */
#define LL_HRTIM_ADCTRIG_SRC24_EEV10 HRTIM_ADC2R_AD2EEV10 /*!< ADC Trigger on external event 10 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMACMP2 HRTIM_ADC2R_AD2TAC2 /*!< ADC Trigger on Timer A compare 2 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2 HRTIM_ADC2R_AD2TFC2 /*!< ADC Trigger on Timer F compare 2 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMACMP4 HRTIM_ADC2R_AD2TAC4 /*!< ADC Trigger on Timer A compare 4 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMAPER HRTIM_ADC2R_AD2TAPER /*!< ADC Trigger on Timer A period */
#define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2 HRTIM_ADC2R_AD2TBC2 /*!< ADC Trigger on Timer B compare 2 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3 HRTIM_ADC2R_AD2TFC3 /*!< ADC Trigger on Timer F compare 3 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4 HRTIM_ADC2R_AD2TBC4 /*!< ADC Trigger on Timer B compare 4 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMBPER HRTIM_ADC2R_AD2TBPER /*!< ADC Trigger on Timer B period */
#define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2 HRTIM_ADC2R_AD2TCC2 /*!< ADC Trigger on Timer C compare 2 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4 HRTIM_ADC2R_AD2TFC4 /*!< ADC Trigger on Timer F compare 4 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4 HRTIM_ADC2R_AD2TCC4 /*!< ADC Trigger on Timer C compare 4 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMCPER HRTIM_ADC2R_AD2TCPER /*!< ADC Trigger on Timer C period */
#define LL_HRTIM_ADCTRIG_SRC24_TIMCRST HRTIM_ADC2R_AD2TCRST /*!< ADC Trigger on Timer C reset */
#define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2 HRTIM_ADC2R_AD2TDC2 /*!< ADC Trigger on Timer D compare 2 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMFPER HRTIM_ADC2R_AD2TFPER /*!< ADC Trigger on Timer F period */
#define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4 HRTIM_ADC2R_AD2TDC4 /*!< ADC Trigger on Timer D compare 4 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMDPER HRTIM_ADC2R_AD2TDPER /*!< ADC Trigger on Timer D period */
#define LL_HRTIM_ADCTRIG_SRC24_TIMDRST HRTIM_ADC2R_AD2TDRST /*!< ADC Trigger on Timer D reset */
#define LL_HRTIM_ADCTRIG_SRC24_TIMECMP2 HRTIM_ADC2R_AD2TEC2 /*!< ADC Trigger on Timer E compare 2 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMECMP3 HRTIM_ADC2R_AD2TEC3 /*!< ADC Trigger on Timer E compare 3 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMECMP4 HRTIM_ADC2R_AD2TEC4 /*!< ADC Trigger on Timer E compare 4 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMERST HRTIM_ADC2R_AD2TERST /*!< ADC Trigger on Timer E reset */
/**
* @}
*/
/** @defgroup HRTIM_ADC_TRIG HRTIM ADC TRIGGER SELECTION
* @{
* @brief Constants defining the selection that can be used as ADC trigger source for extended ADC 6, 8 ,10.
*/
#define LL_HRTIM_ADCTRIG_SRC6810_MCMP1 (uint32_t)0x00 /*!< ADC extended Trigger on Master Compare 1 */
#define LL_HRTIM_ADCTRIG_SRC6810_MCMP2 (uint32_t)0x01 /*!< ADC extended Trigger on Master Compare 2 */
#define LL_HRTIM_ADCTRIG_SRC6810_MCMP3 (uint32_t)0x02 /*!< ADC extended Trigger on Master Compare 3 */
#define LL_HRTIM_ADCTRIG_SRC6810_MCMP4 (uint32_t)0x03 /*!< ADC extended Trigger on Master Compare 4 */
#define LL_HRTIM_ADCTRIG_SRC6810_MPER (uint32_t)0x04 /*!< ADC extended Trigger on Master Period */
#define LL_HRTIM_ADCTRIG_SRC6810_EEV6 (uint32_t)0x05 /*!< ADC extended Trigger on External Event 6 */
#define LL_HRTIM_ADCTRIG_SRC6810_EEV7 (uint32_t)0x06 /*!< ADC extended Trigger on External Event 7 */
#define LL_HRTIM_ADCTRIG_SRC6810_EEV8 (uint32_t)0x07 /*!< ADC extended Trigger on External Event 8 */
#define LL_HRTIM_ADCTRIG_SRC6810_EEV9 (uint32_t)0x08 /*!< ADC extended Trigger on External Event 9 */
#define LL_HRTIM_ADCTRIG_SRC6810_EEV10 (uint32_t)0x09 /*!< ADC extended Trigger on External Event 10 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2 (uint32_t)0x0A /*!< ADC extended Trigger on Timer A Compare 2 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4 (uint32_t)0x0B /*!< ADC extended Trigger on Timer A Compare 4 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER (uint32_t)0x0C /*!< ADC extended Trigger on Timer A Period */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2 (uint32_t)0x0D /*!< ADC extended Trigger on Timer B Compare 2 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4 (uint32_t)0x0E /*!< ADC extended Trigger on Timer B Compare 4 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER (uint32_t)0x0F /*!< ADC extended Trigger on Timer B Period */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2 (uint32_t)0x10 /*!< ADC extended Trigger on Timer C Compare 2 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4 (uint32_t)0x11 /*!< ADC extended Trigger on Timer C Compare 4 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER (uint32_t)0x12 /*!< ADC extended Trigger on Timer C Period */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST (uint32_t)0x13 /*!< ADC extended Trigger on Timer C Reset and counter roll-over */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2 (uint32_t)0x14 /*!< ADC extended Trigger on Timer D Compare 2 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4 (uint32_t)0x15 /*!< ADC extended Trigger on Timer D Compare 4 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER (uint32_t)0x16 /*!< ADC extended Trigger on Timer D Period */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST (uint32_t)0x17 /*!< ADC extended Trigger on Timer D Reset and counter roll-over */
#define LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2 (uint32_t)0x18 /*!< ADC extended Trigger on Timer E Compare 2 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3 (uint32_t)0x19 /*!< ADC extended Trigger on Timer E Compare 3 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4 (uint32_t)0x1A /*!< ADC extended Trigger on Timer E Compare 4 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIME_RST (uint32_t)0x1B /*!< ADC extended Trigger on Timer E Reset and counter roll-over */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2 (uint32_t)0x1C /*!< ADC extended Trigger on Timer F Compare 2 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3 (uint32_t)0x1D /*!< ADC extended Trigger on Timer F Compare 3 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4 (uint32_t)0x1E /*!< ADC extended Trigger on Timer F Compare 4 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER (uint32_t)0x1F /*!< ADC extended Trigger on Timer F Period */
/**
* @}
*/
/** @defgroup HRTIM_ADC_TRIG HRTIM ADC TRIGGER SELECTION
* @{
* @brief Constants defining the selection that can be used as ADC trigger source for extended ADC 5, 7 ,9.
*/
#define LL_HRTIM_ADCTRIG_SRC579_MCMP1 (uint32_t)0x00 /*!< ADC extended Trigger on Master Compare 1 */
#define LL_HRTIM_ADCTRIG_SRC579_MCMP2 (uint32_t)0x01 /*!< ADC extended Trigger on Master Compare 2 */
#define LL_HRTIM_ADCTRIG_SRC579_MCMP3 (uint32_t)0x02 /*!< ADC extended Trigger on Master Compare 3 */
#define LL_HRTIM_ADCTRIG_SRC579_MCMP4 (uint32_t)0x03 /*!< ADC extended Trigger on Master Compare 4 */
#define LL_HRTIM_ADCTRIG_SRC579_MPER (uint32_t)0x04 /*!< ADC extended Trigger on Master Period */
#define LL_HRTIM_ADCTRIG_SRC579_EEV1 (uint32_t)0x05 /*!< ADC extended Trigger on External Event 1 */
#define LL_HRTIM_ADCTRIG_SRC579_EEV2 (uint32_t)0x06 /*!< ADC extended Trigger on External Event 2 */
#define LL_HRTIM_ADCTRIG_SRC579_EEV3 (uint32_t)0x07 /*!< ADC extended Trigger on External Event 3 */
#define LL_HRTIM_ADCTRIG_SRC579_EEV4 (uint32_t)0x08 /*!< ADC extended Trigger on External Event 4 */
#define LL_HRTIM_ADCTRIG_SRC579_EEV5 (uint32_t)0x09 /*!< ADC extended Trigger on External Event 5 */
#define LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3 (uint32_t)0x0A /*!< ADC extended Trigger on Timer A Compare 3 */
#define LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4 (uint32_t)0x0B /*!< ADC extended Trigger on Timer A Compare 4 */
#define LL_HRTIM_ADCTRIG_SRC579_TIMA_PER (uint32_t)0x0C /*!< ADC extended Trigger on Timer A Period */
#define LL_HRTIM_ADCTRIG_SRC579_TIMA_RST (uint32_t)0x0D /*!< ADC extended Trigger on Timer A Period */
#define LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3 (uint32_t)0x0E /*!< ADC extended Trigger on Timer B Compare 3 */
#define LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4 (uint32_t)0x0F /*!< ADC extended Trigger on Timer B Compare 4 */
#define LL_HRTIM_ADCTRIG_SRC579_TIMB_PER (uint32_t)0x10 /*!< ADC extended Trigger on Timer B Period */
#define LL_HRTIM_ADCTRIG_SRC579_TIMB_RST (uint32_t)0x11 /*!< ADC extended Trigger on Timer B Reset and counter roll-over */
#define LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3 (uint32_t)0x12 /*!< ADC extended Trigger on Timer C Compare 3 */
#define LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4 (uint32_t)0x13 /*!< ADC extended Trigger on Timer C Compare 4 */
#define LL_HRTIM_ADCTRIG_SRC579_TIMC_PER (uint32_t)0x14 /*!< ADC extended Trigger on Timer C Period */
#define LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3 (uint32_t)0x15 /*!< ADC extended Trigger on Timer D Compare 3 */
#define LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4 (uint32_t)0x16 /*!< ADC extended Trigger on Timer D Compare 4 */
#define LL_HRTIM_ADCTRIG_SRC579_TIMD_PER (uint32_t)0x17 /*!< ADC extended Trigger on Timer D Period */
#define LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3 (uint32_t)0x18 /*!< ADC extended Trigger on Timer E Compare 3 */
#define LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4 (uint32_t)0x19 /*!< ADC extended Trigger on Timer E Compare 4 */
#define LL_HRTIM_ADCTRIG_SRC579_TIME_PER (uint32_t)0x1A /*!< ADC extended Trigger on Timer E Period */
#define LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2 (uint32_t)0x1B /*!< ADC extended Trigger on Timer F Compare 2 */
#define LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3 (uint32_t)0x1C /*!< ADC extended Trigger on Timer F Compare 3 */
#define LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4 (uint32_t)0x1D /*!< ADC extended Trigger on Timer F Compare 4 */
#define LL_HRTIM_ADCTRIG_SRC579_TIMF_PER (uint32_t)0x1E /*!< ADC extended Trigger on Timer F Period */
#define LL_HRTIM_ADCTRIG_SRC579_TIMF_RST (uint32_t)0x1F /*!< ADC extended Trigger on Timer F Reset and counter roll-over */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_DLLCALIBRATION_MODE DLL CALIBRATION MODE
* @{
* @brief Constants defining the DLL calibration mode.
*/
#define LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT 0x00000000U /*!<Calibration is perfomed only once */
#define LL_HRTIM_DLLCALIBRATION_MODE_CONTINUOUS HRTIM_DLLCR_CALEN /*!<Calibration is performed periodically */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_CALIBRATIONRATE DLL CALIBRATION RATE
* @{
* @brief Constants defining the DLL calibration periods (in micro seconds).
*/
#define LL_HRTIM_DLLCALIBRATION_RATE_0 0x00000000U /*!< Periodic DLL calibration: T = 1048576U * tHRTIM (6.168 ms) */
#define LL_HRTIM_DLLCALIBRATION_RATE_1 (HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 131072U * tHRTIM (0.771 ms) */
#define LL_HRTIM_DLLCALIBRATION_RATE_2 (HRTIM_DLLCR_CALRTE_1) /*!< Periodic DLL calibration: T = 16384U * tHRTIM (0.096 ms) */
#define LL_HRTIM_DLLCALIBRATION_RATE_3 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 2048U * tHRTIM (0.012 ms) */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_PRESCALERRATIO PRESCALER RATIO
* @{
* @brief Constants defining timer high-resolution clock prescaler ratio.
*/
#define LL_HRTIM_PRESCALERRATIO_MUL32 0x00000000U /*!< fHRCK: fHRTIM x 32 = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
#define LL_HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001U) /*!< fHRCK: fHRTIM x 16 = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
#define LL_HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002U) /*!< fHRCK: fHRTIM x 8 = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
#define LL_HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003U) /*!< fHRCK: fHRTIM x 4 = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
#define LL_HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004U) /*!< fHRCK: fHRTIM x 2 = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
#define LL_HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
#define LL_HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006U) /*!< fHRCK: fHRTIM / 2 = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
#define LL_HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007U) /*!< fHRCK: fHRTIM / 4 = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_MODE COUNTER MODE
* @{
* @brief Constants defining timer counter operating mode.
*/
#define LL_HRTIM_MODE_CONTINUOUS ((uint32_t)0x00000008U) /*!< The timer operates in continuous (free-running) mode */
#define LL_HRTIM_MODE_SINGLESHOT 0x00000000U /*!< The timer operates in non retriggerable single-shot mode */
#define LL_HRTIM_MODE_RETRIGGERABLE ((uint32_t)0x00000010U) /*!< The timer operates in retriggerable single-shot mode */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_DACTRIG DAC TRIGGER
* @{
* @brief Constants defining on which output the DAC synchronization event is sent.
*/
#define LL_HRTIM_DACTRIG_NONE 0x00000000U /*!< No DAC synchronization event generated */
#define LL_HRTIM_DACTRIG_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
#define LL_HRTIM_DACTRIG_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
#define LL_HRTIM_DACTRIG_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut3 output upon timer update */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_UPDATETRIG UPDATE TRIGGER
* @{
* @brief Constants defining whether the registers update is done synchronously with any other timer or master update.
*/
#define LL_HRTIM_UPDATETRIG_NONE 0x00000000U /*!< Register update is disabled */
#define LL_HRTIM_UPDATETRIG_MASTER HRTIM_TIMCR_MSTU /*!< Register update is triggered by the master timer update */
#define LL_HRTIM_UPDATETRIG_TIMER_A HRTIM_TIMCR_TAU /*!< Register update is triggered by the timer A update */
#define LL_HRTIM_UPDATETRIG_TIMER_B HRTIM_TIMCR_TBU /*!< Register update is triggered by the timer B update */
#define LL_HRTIM_UPDATETRIG_TIMER_C HRTIM_TIMCR_TCU /*!< Register update is triggered by the timer C update*/
#define LL_HRTIM_UPDATETRIG_TIMER_D HRTIM_TIMCR_TDU /*!< Register update is triggered by the timer D update */
#define LL_HRTIM_UPDATETRIG_TIMER_E HRTIM_TIMCR_TEU /*!< Register update is triggered by the timer E update */
#define LL_HRTIM_UPDATETRIG_TIMER_F HRTIM_TIMCR_TFU /*!< Register update is triggered by the timer F update */
#define LL_HRTIM_UPDATETRIG_REPETITION HRTIM_TIMCR_TREPU /*!< Register update is triggered when the counter rolls over and HRTIM_REPx = 0*/
#define LL_HRTIM_UPDATETRIG_RESET HRTIM_TIMCR_TRSTU /*!< Register update is triggered by counter reset or roll-over to 0 after reaching the period value in continuous mode */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_UPDATEGATING UPDATE GATING
* @{
* @brief Constants defining how the update occurs relatively to the burst DMA transaction and the external update request on update enable inputs 1 to 3.
*/
#define LL_HRTIM_UPDATEGATING_INDEPENDENT 0x00000000U /*!< Update done independently from the DMA burst transfer completion */
#define LL_HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */
#define LL_HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/
#define LL_HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 */
#define LL_HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 */
#define LL_HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 */
#define LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1 */
#define LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 */
#define LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_COMPAREMODE COMPARE MODE
* @{
* @brief Constants defining whether the compare register is behaving in regular mode (compare match issued as soon as counter equal compare) or in auto-delayed mode.
*/
#define LL_HRTIM_COMPAREMODE_REGULAR 0x00000000U /*!< standard compare mode */
#define LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occurred */
#define LL_HRTIM_COMPAREMODE_DELAY_CMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
#define LL_HRTIM_COMPAREMODE_DELAY_CMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_RESETTRIG RESET TRIGGER
* @{
* @brief Constants defining the events that can be selected to trigger the reset of the timer counter.
*/
#define LL_HRTIM_RESETTRIG_NONE 0x00000000U /*!< No counter reset trigger */
#define LL_HRTIM_RESETTRIG_UPDATE HRTIM_RSTR_UPDATE /*!< The timer counter is reset upon update event */
#define LL_HRTIM_RESETTRIG_CMP2 HRTIM_RSTR_CMP2 /*!< The timer counter is reset upon Timer Compare 2 event */
#define LL_HRTIM_RESETTRIG_CMP4 HRTIM_RSTR_CMP4 /*!< The timer counter is reset upon Timer Compare 4 event */
#define LL_HRTIM_RESETTRIG_MASTER_PER HRTIM_RSTR_MSTPER /*!< The timer counter is reset upon master timer period event */
#define LL_HRTIM_RESETTRIG_MASTER_CMP1 HRTIM_RSTR_MSTCMP1 /*!< The timer counter is reset upon master timer Compare 1 event */
#define LL_HRTIM_RESETTRIG_MASTER_CMP2 HRTIM_RSTR_MSTCMP2 /*!< The timer counter is reset upon master timer Compare 2 event */
#define LL_HRTIM_RESETTRIG_MASTER_CMP3 HRTIM_RSTR_MSTCMP3 /*!< The timer counter is reset upon master timer Compare 3 event */
#define LL_HRTIM_RESETTRIG_MASTER_CMP4 HRTIM_RSTR_MSTCMP4 /*!< The timer counter is reset upon master timer Compare 4 event */
#define LL_HRTIM_RESETTRIG_EEV_1 HRTIM_RSTR_EXTEVNT1 /*!< The timer counter is reset upon external event 1 */
#define LL_HRTIM_RESETTRIG_EEV_2 HRTIM_RSTR_EXTEVNT2 /*!< The timer counter is reset upon external event 2 */
#define LL_HRTIM_RESETTRIG_EEV_3 HRTIM_RSTR_EXTEVNT3 /*!< The timer counter is reset upon external event 3 */
#define LL_HRTIM_RESETTRIG_EEV_4 HRTIM_RSTR_EXTEVNT4 /*!< The timer counter is reset upon external event 4 */
#define LL_HRTIM_RESETTRIG_EEV_5 HRTIM_RSTR_EXTEVNT5 /*!< The timer counter is reset upon external event 5 */
#define LL_HRTIM_RESETTRIG_EEV_6 HRTIM_RSTR_EXTEVNT6 /*!< The timer counter is reset upon external event 6 */
#define LL_HRTIM_RESETTRIG_EEV_7 HRTIM_RSTR_EXTEVNT7 /*!< The timer counter is reset upon external event 7 */
#define LL_HRTIM_RESETTRIG_EEV_8 HRTIM_RSTR_EXTEVNT8 /*!< The timer counter is reset upon external event 8 */
#define LL_HRTIM_RESETTRIG_EEV_9 HRTIM_RSTR_EXTEVNT9 /*!< The timer counter is reset upon external event 9 */
#define LL_HRTIM_RESETTRIG_EEV_10 HRTIM_RSTR_EXTEVNT10 /*!< The timer counter is reset upon external event 10 */
#define LL_HRTIM_RESETTRIG_OTHER1_CMP1 HRTIM_RSTR_TIMBCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
#define LL_HRTIM_RESETTRIG_OTHER1_CMP2 HRTIM_RSTR_TIMBCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
#define LL_HRTIM_RESETTRIG_OTHER1_CMP4 HRTIM_RSTR_TIMBCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
#define LL_HRTIM_RESETTRIG_OTHER2_CMP1 HRTIM_RSTR_TIMCCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
#define LL_HRTIM_RESETTRIG_OTHER2_CMP2 HRTIM_RSTR_TIMCCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
#define LL_HRTIM_RESETTRIG_OTHER2_CMP4 HRTIM_RSTR_TIMCCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
#define LL_HRTIM_RESETTRIG_OTHER3_CMP1 HRTIM_RSTR_TIMDCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
#define LL_HRTIM_RESETTRIG_OTHER3_CMP2 HRTIM_RSTR_TIMDCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
#define LL_HRTIM_RESETTRIG_OTHER3_CMP4 HRTIM_RSTR_TIMDCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
#define LL_HRTIM_RESETTRIG_OTHER4_CMP1 HRTIM_RSTR_TIMECMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
#define LL_HRTIM_RESETTRIG_OTHER4_CMP2 HRTIM_RSTR_TIMECMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
#define LL_HRTIM_RESETTRIG_OTHER4_CMP4 HRTIM_RSTR_TIMECMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
#define LL_HRTIM_RESETTRIG_OTHER5_CMP1 HRTIM_RSTR_TIMFCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
#define LL_HRTIM_RESETTRIG_OTHER5_CMP2 HRTIM_RSTR_TIMFCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
#define LL_HRTIM_RESETTRIG_OTHER5_CMP4 HRTIM_RSTR_TIMFCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_CAPTURETRIG CAPTURE TRIGGER
* @{
* @brief Constants defining the events that can be selected to trigger the capture of the timing unit counter.
*/
#define LL_HRTIM_CAPTURETRIG_NONE (uint64_t)0 /*!< Capture trigger is disabled */
#define LL_HRTIM_CAPTURETRIG_SW (uint64_t)HRTIM_CPT1CR_SWCPT /*!< The sw event triggers the Capture */
#define LL_HRTIM_CAPTURETRIG_UPDATE (uint64_t)HRTIM_CPT1CR_UPDCPT /*!< The update event triggers the Capture */
#define LL_HRTIM_CAPTURETRIG_EEV_1 (uint64_t)HRTIM_CPT1CR_EXEV1CPT /*!< The External event 1 triggers the Capture */
#define LL_HRTIM_CAPTURETRIG_EEV_2 (uint64_t)HRTIM_CPT1CR_EXEV2CPT /*!< The External event 2 triggers the Capture */
#define LL_HRTIM_CAPTURETRIG_EEV_3 (uint64_t)HRTIM_CPT1CR_EXEV3CPT /*!< The External event 3 triggers the Capture */
#define LL_HRTIM_CAPTURETRIG_EEV_4 (uint64_t)HRTIM_CPT1CR_EXEV4CPT /*!< The External event 4 triggers the Capture */
#define LL_HRTIM_CAPTURETRIG_EEV_5 (uint64_t)HRTIM_CPT1CR_EXEV5CPT /*!< The External event 5 triggers the Capture */
#define LL_HRTIM_CAPTURETRIG_EEV_6 (uint64_t)HRTIM_CPT1CR_EXEV6CPT /*!< The External event 6 triggers the Capture */
#define LL_HRTIM_CAPTURETRIG_EEV_7 (uint64_t)HRTIM_CPT1CR_EXEV7CPT /*!< The External event 7 triggers the Capture */
#define LL_HRTIM_CAPTURETRIG_EEV_8 (uint64_t)HRTIM_CPT1CR_EXEV8CPT /*!< The External event 8 triggers the Capture */
#define LL_HRTIM_CAPTURETRIG_EEV_9 (uint64_t)HRTIM_CPT1CR_EXEV9CPT /*!< The External event 9 triggers the Capture */
#define LL_HRTIM_CAPTURETRIG_EEV_10 (uint64_t)HRTIM_CPT1CR_EXEV10CPT /*!< The External event 10 triggers the Capture */
#define LL_HRTIM_CAPTURETRIG_TA1_SET (uint64_t)(HRTIM_CPT1CR_TA1SET ) <<32 /*!< Capture is triggered by TA1 output inactive to active transition */
#define LL_HRTIM_CAPTURETRIG_TA1_RESET (uint64_t)(HRTIM_CPT1CR_TA1RST ) <<32 /*!< Capture is triggered by TA1 output active to inactive transition */
#define LL_HRTIM_CAPTURETRIG_TIMA_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMACMP1 ) <<32 /*!< Timer A Compare 1 triggers Capture */
#define LL_HRTIM_CAPTURETRIG_TIMA_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMACMP2 ) <<32 /*!< Timer A Compare 2 triggers Capture */
#define LL_HRTIM_CAPTURETRIG_TB1_SET (uint64_t)(HRTIM_CPT1CR_TB1SET ) <<32 /*!< Capture is triggered by TB1 output inactive to active transition */
#define LL_HRTIM_CAPTURETRIG_TB1_RESET (uint64_t)(HRTIM_CPT1CR_TB1RST ) <<32 /*!< Capture is triggered by TB1 output active to inactive transition */
#define LL_HRTIM_CAPTURETRIG_TIMB_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMBCMP1 ) <<32 /*!< Timer B Compare 1 triggers Capture */
#define LL_HRTIM_CAPTURETRIG_TIMB_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMBCMP2 ) <<32 /*!< Timer B Compare 2 triggers Capture */
#define LL_HRTIM_CAPTURETRIG_TC1_SET (uint64_t)(HRTIM_CPT1CR_TC1SET ) <<32 /*!< Capture is triggered by TC1 output inactive to active transition */
#define LL_HRTIM_CAPTURETRIG_TC1_RESET (uint64_t)(HRTIM_CPT1CR_TC1RST ) <<32 /*!< Capture is triggered by TC1 output active to inactive transition */
#define LL_HRTIM_CAPTURETRIG_TIMC_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMCCMP1 ) <<32 /*!< Timer C Compare 1 triggers Capture */
#define LL_HRTIM_CAPTURETRIG_TIMC_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMCCMP2 ) <<32 /*!< Timer C Compare 2 triggers Capture */
#define LL_HRTIM_CAPTURETRIG_TD1_SET (uint64_t)(HRTIM_CPT1CR_TD1SET ) <<32 /*!< Capture is triggered by TD1 output inactive to active transition */
#define LL_HRTIM_CAPTURETRIG_TD1_RESET (uint64_t)(HRTIM_CPT1CR_TD1RST ) <<32 /*!< Capture is triggered by TD1 output active to inactive transition */
#define LL_HRTIM_CAPTURETRIG_TIMD_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMDCMP1 ) <<32 /*!< Timer D Compare 1 triggers Capture */
#define LL_HRTIM_CAPTURETRIG_TIMD_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMDCMP2 ) <<32 /*!< Timer D Compare 2 triggers Capture */
#define LL_HRTIM_CAPTURETRIG_TE1_SET (uint64_t)(HRTIM_CPT1CR_TE1SET ) <<32 /*!< Capture is triggered by TE1 output inactive to active transition */
#define LL_HRTIM_CAPTURETRIG_TE1_RESET (uint64_t)(HRTIM_CPT1CR_TE1RST ) <<32 /*!< Capture is triggered by TE1 output active to inactive transition */
#define LL_HRTIM_CAPTURETRIG_TIME_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMECMP1 ) <<32 /*!< Timer E Compare 1 triggers Capture */
#define LL_HRTIM_CAPTURETRIG_TIME_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMECMP2 ) <<32 /*!< Timer E Compare 2 triggers Capture */
#define LL_HRTIM_CAPTURETRIG_TF1_SET (uint64_t)(HRTIM_CPT1CR_TF1SET ) <<32 /*!< Capture is triggered by TF1 output inactive to active transition */
#define LL_HRTIM_CAPTURETRIG_TF1_RESET (uint64_t)(HRTIM_CPT1CR_TF1RST ) <<32 /*!< Capture is triggered by TF1 output active to inactive transition */
#define LL_HRTIM_CAPTURETRIG_TIMF_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMFCMP1 ) <<32 /*!< Timer F Compare 1 triggers Capture */
#define LL_HRTIM_CAPTURETRIG_TIMF_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMFCMP2 ) <<32 /*!< Timer F Compare 2 triggers Capture */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_DLYPRT DELAYED PROTECTION (DLYPRT) MODE
* @{
* @brief Constants defining all possible delayed protection modes for a timer (also define the source and outputs on which the delayed protection schemes are applied).
*/
#define LL_HRTIM_DLYPRT_DELAYOUT1_EEV6 0x00000000U /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6 */
#define LL_HRTIM_DLYPRT_DELAYOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6 */
#define LL_HRTIM_DLYPRT_DELAYBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1) /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6 */
#define LL_HRTIM_DLYPRT_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 6 */
#define LL_HRTIM_DLYPRT_DELAYOUT1_EEV7 (HRTIM_OUTR_DLYPRT_2) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7 */
#define LL_HRTIM_DLYPRT_DELAYOUT2_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7 */
#define LL_HRTIM_DLYPRT_DELAYBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1) /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7 */
#define LL_HRTIM_DLYPRT_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 7 */
#define LL_HRTIM_DLYPRT_DELAYOUT1_EEV8 0x00000000U /*!< Timers D, E: Output 1 delayed Idle on external Event 8 */
#define LL_HRTIM_DLYPRT_DELAYOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Output 2 delayed Idle on external Event 8 */
#define LL_HRTIM_DLYPRT_DELAYBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1) /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 8 */
#define LL_HRTIM_DLYPRT_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Balanced Idle on external Event 8 */
#define LL_HRTIM_DLYPRT_DELAYOUT1_EEV9 (HRTIM_OUTR_DLYPRT_2) /*!< Timers D, E: Output 1 delayed Idle on external Event 9 */
#define LL_HRTIM_DLYPRT_DELAYOUT2_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Output 2 delayed Idle on external Event 9 */
#define LL_HRTIM_DLYPRT_DELAYBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1) /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 9 */
#define LL_HRTIM_DLYPRT_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Balanced Idle on external Event 9 */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_BURSTMODE BURST MODE
* @{
* @brief Constants defining how the timer behaves during a burst mode operation.
*/
#define LL_HRTIM_BURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /*!< Timer counter clock is maintained and the timer operates normally */
#define LL_HRTIM_BURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_BURSTDMA BURST DMA
* @{
* @brief Constants defining the registers that can be written during a burst DMA operation.
*/
#define LL_HRTIM_BURSTDMA_NONE 0x00000000U /*!< No register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_MCR (HRTIM_BDMUPR_MCR) /*!< MCR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_MICR (HRTIM_BDMUPR_MICR) /*!< MICR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_MDIER (HRTIM_BDMUPR_MDIER) /*!< MDIER register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_MCNT (HRTIM_BDMUPR_MCNT) /*!< MCNTR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_MPER (HRTIM_BDMUPR_MPER) /*!< MPER register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_MREP (HRTIM_BDMUPR_MREP) /*!< MREPR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_MCMP1 (HRTIM_BDMUPR_MCMP1) /*!< MCMP1R register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_MCMP2 (HRTIM_BDMUPR_MCMP2) /*!< MCMP2R register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_MCMP3 (HRTIM_BDMUPR_MCMP3) /*!< MCMP3R register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_MCMP4 (HRTIM_BDMUPR_MCMP4) /*!< MCMP4R register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMMCR (HRTIM_BDTUPR_TIMCR) /*!< TIMxCR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMICR (HRTIM_BDTUPR_TIMICR) /*!< TIMxICR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMDIER (HRTIM_BDTUPR_TIMDIER) /*!< TIMxDIER register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMCNT (HRTIM_BDTUPR_TIMCNT) /*!< CNTxCR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMPER (HRTIM_BDTUPR_TIMPER) /*!< PERxR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMREP (HRTIM_BDTUPR_TIMREP) /*!< REPxR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMCMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< CMP1xR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMCMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< CMP2xR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMCMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< CMP3xR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMCMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< CMP4xR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMDTR (HRTIM_BDTUPR_TIMDTR) /*!< DTxR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMSET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMRST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMSET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMRST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMEEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMEEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMRSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMCHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMOUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMFLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_CR2 (HRTIM_BDTUPR_TIMCR2) /*!< TIMxCR2 register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_EEFR3 (HRTIM_BDTUPR_TIMEEFR3) /*!< EEFxR3 register is updated by Burst DMA accesses */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_CPPSTAT CURRENT PUSH-PULL STATUS
* @{
* @brief Constants defining on which output the signal is currently applied in push-pull mode.
*/
#define LL_HRTIM_CPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /*!< Signal applied on output 1 and output 2 forced inactive */
#define LL_HRTIM_CPPSTAT_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_IPPSTAT IDLE PUSH-PULL STATUS
* @{
* @brief Constants defining on which output the signal was applied, in push-pull mode balanced fault mode or delayed idle mode, when the protection was triggered.
*/
#define LL_HRTIM_IPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
#define LL_HRTIM_IPPSTAT_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_TIM_EEFLTR TIMER EXTERNAL EVENT FILTER
* @{
* @brief Constants defining the event filtering applied to external events by a timer.
*/
#define LL_HRTIM_EEFLTR_NONE (0x00000000U)
#define LL_HRTIM_EEFLTR_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1U */
#define LL_HRTIM_EEFLTR_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2U */
#define LL_HRTIM_EEFLTR_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3U */
#define LL_HRTIM_EEFLTR_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4U */
/* Blanking Filter for TIMER A */
#define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF1_TIMBCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF2_TIMBCMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF3_TIMBOUT2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF4_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF5_TIMCCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF6_TIMFCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF7_TIMDCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF8_TIMECMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
/* Blanking Filter for TIMER B */
#define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF1_TIMACMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF2_TIMACMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF3_TIMAOUT2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF4_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF5_TIMCCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF6_TIMFCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF7_TIMDCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF8_TIMECMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
/* Blanking Filter for TIMER C */
#define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF1_TIMACMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF2_TIMBCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF3_TIMBCMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF4_TIMFCMP1 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF5_TIMDCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF6_TIMDCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF7_TIMDOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF8_TIMECMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
/* Blanking Filter for TIMER D */
#define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF1_TIMACMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF2_TIMBCMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF3_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF4_TIMCCMP2 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF5_TIMCOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF6_TIMECMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF7_TIMECMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF8_TIMFCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
/* Blanking Filter for TIMER E */
#define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF1_TIMACMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF2_TIMBCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF3_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF4_TIMFCMP4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF5_TIMFOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF6_TIMDCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF7_TIMDCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF8_TIMDOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
/* Blanking Filter for TIMER F */
#define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF1_TIMACMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF2_TIMBCMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF3_TIMCCMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF4_TIMDCMP2 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF5_TIMDCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF6_TIMECMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF7_TIMECMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF8_TIMEOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
#define LL_HRTIM_EEFLTR_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */
#define LL_HRTIM_EEFLTR_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */
#define LL_HRTIM_EEFLTR_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1\
| HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_TIM_LATCHSTATUS TIMER EXTERNAL EVENT LATCH STATUS
* @{
* @brief Constants defining whether or not the external event is memorized (latched) and generated as soon as the blanking period is completed or the window ends.
*/
#define LL_HRTIM_EELATCH_DISABLED 0x00000000U /*!< Event is ignored if it happens during a blank, or passed through during a window */
#define LL_HRTIM_EELATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event is latched and delayed till the end of the blanking or windowing period */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_DT_PRESCALER DEADTIME PRESCALER
* @{
* @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the deadtime generator clock (fDTG).
*/
#define LL_HRTIM_DT_PRESCALER_MUL8 0x00000000U /*!< fDTG = fHRTIM * 8 */
#define LL_HRTIM_DT_PRESCALER_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM * 4 */
#define LL_HRTIM_DT_PRESCALER_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM * 2 */
#define LL_HRTIM_DT_PRESCALER_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */
#define LL_HRTIM_DT_PRESCALER_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< fDTG = fHRTIM / 2 */
#define LL_HRTIM_DT_PRESCALER_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4 */
#define LL_HRTIM_DT_PRESCALER_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8 */
#define LL_HRTIM_DT_PRESCALER_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16 */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_DT_RISING_SIGN DEADTIME RISING SIGN
* @{
* @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on rising edge.
*/
#define LL_HRTIM_DT_RISING_POSITIVE 0x00000000U /*!< Positive deadtime on rising edge */
#define LL_HRTIM_DT_RISING_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative deadtime on rising edge */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_DT_FALLING_SIGN DEADTIME FALLING SIGN
* @{
* @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on falling edge.
*/
#define LL_HRTIM_DT_FALLING_POSITIVE 0x00000000U /*!< Positive deadtime on falling edge */
#define LL_HRTIM_DT_FALLING_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative deadtime on falling edge */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_CHP_PRESCALER CHOPPER MODE PRESCALER
* @{
* @brief Constants defining the frequency of the generated high frequency carrier (fCHPFRQ).
*/
#define LL_HRTIM_CHP_PRESCALER_DIV16 0x00000000U /*!< fCHPFRQ = fHRTIM / 16 */
#define LL_HRTIM_CHP_PRESCALER_DIV32 (HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 32 */
#define LL_HRTIM_CHP_PRESCALER_DIV48 (HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 48 */
#define LL_HRTIM_CHP_PRESCALER_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 64 */
#define LL_HRTIM_CHP_PRESCALER_DIV80 (HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 80 */
#define LL_HRTIM_CHP_PRESCALER_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 96 */
#define LL_HRTIM_CHP_PRESCALER_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 112 */
#define LL_HRTIM_CHP_PRESCALER_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 128 */
#define LL_HRTIM_CHP_PRESCALER_DIV144 (HRTIM_CHPR_CARFRQ_3) /*!< fCHPFRQ = fHRTIM / 144 */
#define LL_HRTIM_CHP_PRESCALER_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 160 */
#define LL_HRTIM_CHP_PRESCALER_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 176 */
#define LL_HRTIM_CHP_PRESCALER_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 192 */
#define LL_HRTIM_CHP_PRESCALER_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 208 */
#define LL_HRTIM_CHP_PRESCALER_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */
#define LL_HRTIM_CHP_PRESCALER_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */
#define LL_HRTIM_CHP_PRESCALER_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_CHP_DUTYCYCLE CHOPPER MODE DUTY CYCLE
* @{
* @brief Constants defining the duty cycle of the generated high frequency carrier. Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8).
*/
#define LL_HRTIM_CHP_DUTYCYCLE_0 0x00000000U /*!< Only 1st pulse is present */
#define LL_HRTIM_CHP_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 12.5 % */
#define LL_HRTIM_CHP_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 25 % */
#define LL_HRTIM_CHP_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 37.5 % */
#define LL_HRTIM_CHP_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /*!< Duty cycle of the carrier signal is 50 % */
#define LL_HRTIM_CHP_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 62.5 % */
#define LL_HRTIM_CHP_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 75 % */
#define LL_HRTIM_CHP_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5 % */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_CHP_PULSEWIDTH CHOPPER MODE PULSE WIDTH
* @{
* @brief Constants defining the pulse width of the first pulse of the generated high frequency carrier.
*/
#define LL_HRTIM_CHP_PULSEWIDTH_16 0x00000000U /*!< tSTPW = tHRTIM x 16 */
#define LL_HRTIM_CHP_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 32 */
#define LL_HRTIM_CHP_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 48 */
#define LL_HRTIM_CHP_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 64 */
#define LL_HRTIM_CHP_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 80 */
#define LL_HRTIM_CHP_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 96 */
#define LL_HRTIM_CHP_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 112 */
#define LL_HRTIM_CHP_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 128 */
#define LL_HRTIM_CHP_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3) /*!< tSTPW = tHRTIM x 144 */
#define LL_HRTIM_CHP_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 160 */
#define LL_HRTIM_CHP_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 176 */
#define LL_HRTIM_CHP_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 192 */
#define LL_HRTIM_CHP_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 208 */
#define LL_HRTIM_CHP_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 224 */
#define LL_HRTIM_CHP_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 240 */
#define LL_HRTIM_CHP_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 256 */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_OUTPUTSET_INPUT OUTPUTSET INPUT
* @{
* @brief Constants defining the events that can be selected to configure the set/reset crossbar of a timer output.
*/
#define LL_HRTIM_OUTPUTSET_NONE 0x00000000U /*!< Reset the output set crossbar */
#define LL_HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces an output level transision */
#define LL_HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces an output level transision */
#define LL_HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces an output level transision */
#define LL_HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces an output level transision */
#define LL_HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces an output level transision */
#define LL_HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces an output level transision */
#define LL_HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces an output level transision */
#define LL_HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces an output level transision */
#define LL_HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces an output level transision */
#define LL_HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces an output level transision */
#define LL_HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces an output level transision */
/* Timer Events mapping for Timer A */
#define LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its ictive state */
#define LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMAEV3_TIMFCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP2 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMAEV5_TIMCCMP3 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP1 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMAEV7_TIMDCMP2 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP3 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMAEV9_TIMECMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
/* Timer Events mapping for Timer B */
#define LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMBEV3_TIMFCMP3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMBEV5_TIMCCMP4 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP3 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMBEV7_TIMDCMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP1 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMBEV9_TIMECMP2 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
/* Timer Events mapping for Timer C */
#define LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMCEV7_TIMFCMP2 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP3 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMCEV9_TIMECMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
/* Timer Events mapping for Timer D */
#define LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMDEV5_TIMFCMP1 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMDEV6_TIMFCMP3 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMDEV7_TIMCCMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMDEV8_TIMECMP1 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMDEV9_TIMECMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
/* Timer Events mapping for Timer E */
#define LL_HRTIM_OUTPUTSET_TIMEEV1_TIMFCMP3 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMEEV2_TIMACMP4 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMEEV4_TIMBCMP4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP1 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMEEV6_TIMCCMP2 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP1 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMEEV8_TIMDCMP2 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
/* Timer Events mapping for Timer F */
#define LL_HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces an output level transision */
#define LL_HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces an output level transision */
#define LL_HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces an output level transision */
#define LL_HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces an output level transision */
#define LL_HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces an output level transision */
#define LL_HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces an output level transision */
#define LL_HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces an output level transision */
#define LL_HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces an output level transision */
#define LL_HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces an output level transision */
#define LL_HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces an output level transision */
#define LL_HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces an output level transision */
/**
* @}
*/
/** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source
* @{
* @brief Constants defining the events that can be selected to configure the
* set crossbar of a timer output
*/
#define LL_HRTIM_OUTPUTRESET_NONE 0x00000000U /*!< Reset the output reset crossbar */
#define LL_HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */
/* Timer Events mapping for Timer A */
#define LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMFCMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP2 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMCCMP3 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP1 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMDCMP2 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP3 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMECMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
/* Timer Events mapping for Timer B */
#define LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMFCMP3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMCCMP4 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP3 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMDCMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP1 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMECMP2 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
/* Timer Events mapping for Timer C */
#define LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMFCMP2 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP3 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMECMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
/* Timer Events mapping for Timer D */
#define LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMFCMP1 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMFCMP3 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMCCMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMECMP1 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMECMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
/* Timer Events mapping for Timer E */
#define LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMFCMP3 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMACMP4 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMBCMP4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP1 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMCCMP2 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP1 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMDCMP2 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
/* Timer Events mapping for Timer F */
#define LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_OUT_POLARITY OUPUT_POLARITY
* @{
* @brief Constants defining the polarity of a timer output.
*/
#define LL_HRTIM_OUT_POSITIVE_POLARITY 0x00000000U /*!< Output is acitve HIGH */
#define LL_HRTIM_OUT_NEGATIVE_POLARITY (HRTIM_OUTR_POL1) /*!< Output is active LOW */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_OUT_IDLEMODE OUTPUT IDLE MODE
* @{
* @brief Constants defining whether or not the timer output transition to its IDLE state when burst mode is entered.
*/
#define LL_HRTIM_OUT_NO_IDLE 0x00000000U /*!< The output is not affected by the burst mode operation */
#define LL_HRTIM_OUT_IDLE_WHEN_BURST (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_INTLVD_MODE INTLVD MODE
* @{
* @brief Constants defining the interleaved mode of an HRTIM Timer instance.
*/
#define LL_HRTIM_INTERLEAVED_MODE_DISABLED 0x000U /*!< HRTIM interleaved Mode is disabled */
#define LL_HRTIM_INTERLEAVED_MODE_DUAL HRTIM_MCR_HALF /*!< HRTIM interleaved Mode is Dual */
#define LL_HRTIM_INTERLEAVED_MODE_TRIPLE HRTIM_MCR_INTLVD_0 /*!< HRTIM interleaved Mode is Triple */
#define LL_HRTIM_INTERLEAVED_MODE_QUAD HRTIM_MCR_INTLVD_1 /*!< HRTIM interleaved Mode is Quad */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_HALF_MODE HALF MODE
* @{
* @brief Constants defining the half mode of an HRTIM Timer instance.
*/
#define LL_HRTIM_HALF_MODE_DISABLED 0x000U /*!< HRTIM Half Mode is disabled */
#define LL_HRTIM_HALF_MODE_ENABLE HRTIM_MCR_HALF /*!< HRTIM Half Mode is Half */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_OUT_IDLELEVEL OUTPUT IDLE LEVEL
* @{
* @brief Constants defining the output level when output is in IDLE state
*/
#define LL_HRTIM_OUT_IDLELEVEL_INACTIVE 0x00000000U /*!< Output at inactive level when in IDLE state */
#define LL_HRTIM_OUT_IDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_OUT_FAULTSTATE OUTPUT FAULT STATE
* @{
* @brief Constants defining the output level when output is in FAULT state.
*/
#define LL_HRTIM_OUT_FAULTSTATE_NO_ACTION 0x00000000U /*!< The output is not affected by the fault input */
#define LL_HRTIM_OUT_FAULTSTATE_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */
#define LL_HRTIM_OUT_FAULTSTATE_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */
#define LL_HRTIM_OUT_FAULTSTATE_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_OUT_CHOPPERMODE OUTPUT CHOPPER MODE
* @{
* @brief Constants defining whether or not chopper mode is enabled for a timer output.
*/
#define LL_HRTIM_OUT_CHOPPERMODE_DISABLED 0x00000000U /*!< Output signal is not altered */
#define LL_HRTIM_OUT_CHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output signal is chopped by a carrier signal */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_OUT_BM_ENTRYMODE OUTPUT BURST MODE ENTRY MODE
* @{
* @brief Constants defining the idle state entry mode during a burst mode operation. It is possible to delay the burst mode entry and force the output to an inactive state
during a programmable period before the output takes its idle state.
*/
#define LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR 0x00000000U /*!< The programmed Idle state is applied immediately to the Output */
#define LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED (HRTIM_OUTR_DIDL1) /*!< Deadtime is inserted on output before entering the idle mode */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_OUT_LEVEL OUTPUT LEVEL
* @{
* @brief Constants defining the level of a timer output.
*/
#define LL_HRTIM_OUT_LEVEL_INACTIVE 0x00000000U /*!< Corresponds to a logic level 0 for a positive polarity (High) and to a logic level 1 for a negative polarity (Low) */
#define LL_HRTIM_OUT_LEVEL_ACTIVE ((uint32_t)0x00000001) /*!< Corresponds to a logic level 1 for a positive polarity (High) and to a logic level 0 for a negative polarity (Low) */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_EE_SRC EXTERNAL EVENT SOURCE
* @{
* @brief Constants defining available sources associated to external events.
*/
#define LL_HRTIM_EEV1SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 1 */
#define LL_HRTIM_EEV2SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 2 */
#define LL_HRTIM_EEV3SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 3 */
#define LL_HRTIM_EEV4SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 4 */
#define LL_HRTIM_EEV5SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 5 */
#define LL_HRTIM_EEV6SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 6 */
#define LL_HRTIM_EEV7SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 7 */
#define LL_HRTIM_EEV8SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 8 */
#define LL_HRTIM_EEV9SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 9 */
#define LL_HRTIM_EEV10SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 10 */
#define LL_HRTIM_EEV1SRC_COMP2_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 1 */
#define LL_HRTIM_EEV2SRC_COMP4_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 2 */
#define LL_HRTIM_EEV3SRC_COMP6_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 3 */
#define LL_HRTIM_EEV4SRC_COMP1_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 4 */
#define LL_HRTIM_EEV5SRC_COMP3_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 5 */
#define LL_HRTIM_EEV6SRC_COMP2_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 6 */
#define LL_HRTIM_EEV7SRC_COMP4_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 7 */
#define LL_HRTIM_EEV8SRC_COMP6_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 8 */
#define LL_HRTIM_EEV9SRC_COMP5_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 9 */
#define LL_HRTIM_EEV10SRC_COMP7_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 10 */
#define LL_HRTIM_EEV1SRC_TIM1_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 1 */
#define LL_HRTIM_EEV2SRC_TIM2_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 2 */
#define LL_HRTIM_EEV3SRC_TIM3_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 3 */
#define LL_HRTIM_EEV4SRC_COMP5_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 4 */
#define LL_HRTIM_EEV5SRC_COMP7_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 5 */
#define LL_HRTIM_EEV6SRC_COMP1_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 6 */
#define LL_HRTIM_EEV7SRC_TIM7_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 7 */
#define LL_HRTIM_EEV8SRC_COMP3_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 8 */
#define LL_HRTIM_EEV9SRC_TIM15_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 9 */
#define LL_HRTIM_EEV10SRC_TIM6_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 10 */
#define LL_HRTIM_EEV1SRC_ADC1_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 1 */
#define LL_HRTIM_EEV2SRC_ADC1_AWD2 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 2 */
#define LL_HRTIM_EEV3SRC_ADC1_AWD3 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 3 */
#define LL_HRTIM_EEV4SRC_ADC2_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 4 */
#define LL_HRTIM_EEV5SRC_ADC2_AWD2 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 5 */
#define LL_HRTIM_EEV6SRC_ADC2_AWD3 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 6 */
#define LL_HRTIM_EEV7SRC_ADC3_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 7 */
#define LL_HRTIM_EEV8SRC_ADC4_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 8 */
#define LL_HRTIM_EEV9SRC_COMP4_OUT (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 9 */
#define LL_HRTIM_EEV10SRC_ADC5_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 10 */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_EE_POLARITY EXTERNAL EVENT POLARITY
* @{
* @brief Constants defining the polarity of an external event.
*/
#define LL_HRTIM_EE_POLARITY_HIGH 0x00000000U /*!< External event is active high */
#define LL_HRTIM_EE_POLARITY_LOW (HRTIM_EECR1_EE1POL) /*!< External event is active low */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_EE_SENSITIVITY EXTERNAL EVENT SENSITIVITY
* @{
* @brief Constants defining the sensitivity (level-sensitive or edge-sensitive) of an external event.
*/
#define LL_HRTIM_EE_SENSITIVITY_LEVEL 0x00000000U /*!< External event is active on level */
#define LL_HRTIM_EE_SENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */
#define LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */
#define LL_HRTIM_EE_SENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_EE_FASTMODE EXTERNAL EVENT FAST MODE
* @{
* @brief Constants defining whether or not an external event is programmed in fast mode.
*/
#define LL_HRTIM_EE_FASTMODE_DISABLE 0x00000000U /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
#define LL_HRTIM_EE_FASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is acting asynchronously on outputs (low latency mode) */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_EE_FILTER EXTERNAL EVENT DIGITAL FILTER
* @{
* @brief Constants defining the frequency used to sample an external event input (fSAMPLING) and the length (N) of the digital filter applied.
*/
#define LL_HRTIM_EE_FILTER_NONE 0x00000000U /*!< Filter disabled */
#define LL_HRTIM_EE_FILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fHRTIM, N=2 */
#define LL_HRTIM_EE_FILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fHRTIM, N=4 */
#define LL_HRTIM_EE_FILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fHRTIM, N=8 */
#define LL_HRTIM_EE_FILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING = fEEVS/2, N=6 */
#define LL_HRTIM_EE_FILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/2, N=8 */
#define LL_HRTIM_EE_FILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/4, N=6 */
#define LL_HRTIM_EE_FILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/4, N=8 */
#define LL_HRTIM_EE_FILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING = fEEVS/8, N=6 */
#define LL_HRTIM_EE_FILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/8, N=8 */
#define LL_HRTIM_EE_FILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/16, N=5 */
#define LL_HRTIM_EE_FILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/16, N=6 */
#define LL_HRTIM_EE_FILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING = fEEVS/16, N=8 */
#define LL_HRTIM_EE_FILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/32, N=5 */
#define LL_HRTIM_EE_FILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/32, N=6 */
#define LL_HRTIM_EE_FILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/32, N=8 */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_EE_PRESCALER EXTERNAL EVENT PRESCALER
* @{
* @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the external event signal sampling clock (fEEVS) used by the digital filters.
*/
#define LL_HRTIM_EE_PRESCALER_DIV1 0x00000000U /*!< fEEVS = fHRTIM */
#define LL_HRTIM_EE_PRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 2 */
#define LL_HRTIM_EE_PRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS = fHRTIM / 4 */
#define LL_HRTIM_EE_PRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 8 */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_EE_COUNTER EXTERNAL EVENT A or B COUNTER
* @{
* @brief Constants defining the external event counter.
*/
#define LL_HRTIM_EVENT_COUNTER_A ((uint32_t)0U) /*!< External Event A Counter */
#define LL_HRTIM_EVENT_COUNTER_B ((uint32_t)16U) /*!< External Event B Counter */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_EE_COUNTERRSTMODE EXTERNAL EVENT A or B RESET MODE
* @{
* @brief Constants defining the external event reset mode.
*/
#define LL_HRTIM_EVENT_COUNTERRSTMODE_UNCONDITIONAL ((uint32_t)0U) /*!< External Event counter is reset on each reset / roll-over event */
#define LL_HRTIM_EVENT_COUNTERRSTMODE_CONDITIONAL ((uint32_t)HRTIM_EEFR3_EEVARSTM) /*!< External Event counter is reset on each reset / roll-over event only if no event occurs during last counting period */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_FLT_SRC FAULT SOURCE
* @{
* @brief Constants defining whether a faults is be triggered by any external or internal fault source.
*/
#define LL_HRTIM_FLT_SRC_DIGITALINPUT 0x00000000U /*!< Fault input is FLT input pin */
#define LL_HRTIM_FLT_SRC_INTERNAL HRTIM_FLTINR1_FLT1SRC_0 /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
#define LL_HRTIM_FLT_SRC_EEVINPUT HRTIM_FLTINR2_FLT1SRC_1 /*!< Fault input is external event pin */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_FLT_POLARITY FAULT POLARITY
* @{
* @brief Constants defining the polarity of a fault event.
*/
#define LL_HRTIM_FLT_POLARITY_LOW 0x00000000U /*!< Fault input is active low */
#define LL_HRTIM_FLT_POLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_FLT_FILTER FAULT DIGITAL FILTER
* @{
* @brief Constants defining the frequency used to sample the fault input (fSAMPLING) and the length (N) of the digital filter applied.
*/
#define LL_HRTIM_FLT_FILTER_NONE 0x00000000U /*!< Filter disabled */
#define LL_HRTIM_FLT_FILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2 */
#define LL_HRTIM_FLT_FILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4 */
#define LL_HRTIM_FLT_FILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8 */
#define LL_HRTIM_FLT_FILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2, N=6 */
#define LL_HRTIM_FLT_FILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2, N=8 */
#define LL_HRTIM_FLT_FILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4, N=6 */
#define LL_HRTIM_FLT_FILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4, N=8 */
#define LL_HRTIM_FLT_FILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8, N=6 */
#define LL_HRTIM_FLT_FILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8, N=8 */
#define LL_HRTIM_FLT_FILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16, N=5 */
#define LL_HRTIM_FLT_FILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16, N=6 */
#define LL_HRTIM_FLT_FILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16, N=8 */
#define LL_HRTIM_FLT_FILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=5 */
#define LL_HRTIM_FLT_FILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32, N=6 */
#define LL_HRTIM_FLT_FILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=8 */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_FLT_PRESCALER BURST FAULT PRESCALER
* @{
* @brief Constants defining the division ratio between the timer clock frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used by the digital filters.
*/
#define LL_HRTIM_FLT_PRESCALER_DIV1 0x00000000U /*!< fFLTS = fHRTIM */
#define LL_HRTIM_FLT_PRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 2 */
#define LL_HRTIM_FLT_PRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS = fHRTIM / 4 */
#define LL_HRTIM_FLT_PRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 8 */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_FLT_BLKS FAULT BLANKING Source
* @{
* @brief Constants defining the Blanking Source of a fault event.
*/
#define LL_HRTIM_FLT_BLANKING_RSTALIGNED 0x00000000U /*!< Fault blanking source is Reset-aligned */
#define LL_HRTIM_FLT_BLANKING_MOVING (HRTIM_FLTINR3_FLT1BLKS) /*!< Fault blanking source is Moving window */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_FLT_RSTM FAULT Counter RESET Mode
* @{
* @brief Constants defining the Counter RESet Mode of a fault event.
*/
#define LL_HRTIM_FLT_COUNTERRST_UNCONDITIONAL 0x00000000U /*!< Fault counter is reset on each reset / roll-over event */
#define LL_HRTIM_FLT_COUNTERRST_CONDITIONAL (HRTIM_FLTINR3_FLT1RSTM) /*!< Fault counter is reset on each reset / roll-over event only if no fault occurred during last counting
period. */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_BM_MODE BURST MODE OPERATING MODE
* @{
* @brief Constants defining if the burst mode is entered once or if it is continuously operating.
*/
#define LL_HRTIM_BM_MODE_SINGLESHOT 0x00000000U /*!< Burst mode operates in single shot mode */
#define LL_HRTIM_BM_MODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_BM_CLKSRC BURST MODE CLOCK SOURCE
* @{
* @brief Constants defining the clock source for the burst mode counter.
*/
#define LL_HRTIM_BM_CLKSRC_MASTER 0x00000000U /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
#define LL_HRTIM_BM_CLKSRC_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
#define LL_HRTIM_BM_CLKSRC_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
#define LL_HRTIM_BM_CLKSRC_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
#define LL_HRTIM_BM_CLKSRC_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
#define LL_HRTIM_BM_CLKSRC_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
#define LL_HRTIM_BM_CLKSRC_TIMER_F (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer F counter reset/roll-over is used as clock source for the burst mode counter */
#define LL_HRTIM_BM_CLKSRC_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
#define LL_HRTIM_BM_CLKSRC_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
#define LL_HRTIM_BM_CLKSRC_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
#define LL_HRTIM_BM_CLKSRC_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_BM_PRESCALER BURST MODE PRESCALER
* @{
* @brief Constants defining the prescaling ratio of the fHRTIM clock for the burst mode controller (fBRST).
*/
#define LL_HRTIM_BM_PRESCALER_DIV1 0x00000000U /*!< fBRST = fHRTIM */
#define LL_HRTIM_BM_PRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2 */
#define LL_HRTIM_BM_PRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/4 */
#define LL_HRTIM_BM_PRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8 */
#define LL_HRTIM_BM_PRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/16 */
#define LL_HRTIM_BM_PRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32 */
#define LL_HRTIM_BM_PRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/64 */
#define LL_HRTIM_BM_PRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/128 */
#define LL_HRTIM_BM_PRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /*!< fBRST = fHRTIM/256 */
#define LL_HRTIM_BM_PRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/512 */
#define LL_HRTIM_BM_PRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/1024 */
#define LL_HRTIM_BM_PRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2048*/
#define LL_HRTIM_BM_PRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/4096 */
#define LL_HRTIM_BM_PRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8192 */
#define LL_HRTIM_BM_PRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/16384 */
#define LL_HRTIM_BM_PRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768 */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_BM_TRIG HRTIM BURST MODE TRIGGER
* @{
* @brief Constants defining the events that can be used to trig the burst mode operation.
*/
#define LL_HRTIM_BM_TRIG_NONE 0x00000000U /*!< No trigger */
#define LL_HRTIM_BM_TRIG_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master timer reset event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master timer repetition event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master timer compare 1 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master timer compare 2 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master timer compare 3 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master timer compare 4 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C resetevent is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMC_CMP2 (HRTIM_BMTRGR_TCCMP2) /*!< Timer C compare 2 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMD_CMP1 (HRTIM_BMTRGR_TDCMP1) /*!< Timer D compare 1 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIME_RESET (HRTIM_BMTRGR_TERST) /*!< Timer E reset event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIME_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIME_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIME_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMF_RESET (HRTIM_BMTRGR_TFRST) /*!< Timer F reset event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMF_REPETITION (HRTIM_BMTRGR_TFREP) /*!< Timer F repetition event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMF_CMP1 (HRTIM_BMTRGR_TFCMP1) /*!< Timer F compare 1 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMF_CMP2 (HRTIM_BMTRGR_TFCMP2) /*!< Timer F compare 2 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following an external event 7 (conditioned by TIMA filters) is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following an external event 8 (conditioned by TIMD filters) is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External event 7 conditioned by TIMA filters is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External event 8 conditioned by TIMD filters is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< A rising edge on an on-chip Event (for instance from GP timer or comparator) triggers the burst mode operation */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_BM_STATUS HRTIM BURST MODE STATUS
* @{
* @brief Constants defining the operating state of the burst mode controller.
*/
#define LL_HRTIM_BM_STATUS_NORMAL 0x00000000U /*!< Normal operation */
#define LL_HRTIM_BM_STATUS_BURST_ONGOING HRTIM_BMCR_BMSTAT /*!< Burst operation on-going */
/**
* @}
*/
/** @defgroup HRTIM_LL_COUNTER_MODE Counter Mode
* @{
* @brief Constants defining the Counter Up Down Mode.
*/
#define LL_HRTIM_COUNTING_MODE_UP 0x00000000U /*!< counter is operating in up-counting mode */
#define LL_HRTIM_COUNTING_MODE_UP_DOWN HRTIM_TIMCR2_UDM /*!< counter is operating in up-down counting mode */
/**
* @}
*/
/** @defgroup HRTIM_LL_COUNTER_Roll-Over counter Mode
* @{
* @brief Constants defining the Roll-Over counter Mode.
*/
#define LL_HRTIM_ROLLOVER_MODE_PER 2U /*!< Event generated when counter reaches period value ('crest' mode) */
#define LL_HRTIM_ROLLOVER_MODE_RST 1U /*!< Event generated when counter equals 0 ('valley' mode) */
#define LL_HRTIM_ROLLOVER_MODE_BOTH 0U /*!< Event generated when counter reach both conditions (0 or HRTIM_PERxR value) */
/**
* @}
*/
/** @defgroup HRTIM_Timer_TrigHalf_Mode HRTIM Timer Triggered-Half Mode
* @{
* @brief Constants defining how the timer counter operates.
*/
#define LL_HRTIM_TRIGHALF_DISABLED 0x00000000U /*!< Timer Compare 2 register is behaving in standard mode */
#define LL_HRTIM_TRIGHALF_ENABLED HRTIM_TIMCR2_TRGHLF /*!< Timer Compare 2 register is behaving in triggered-half mode */
/**
* @}
*/
/** @defgroup HRTIM_LL_COUNTER_Compare Greater than compare PWM Mode
* @{
* @brief Constants defining the greater than compare 1 or 3 PWM Mode.
*/
#define LL_HRTIM_GTCMP1_EQUAL 0x00000000U /*!< event is generated when counter is equal to compare value */
#define LL_HRTIM_GTCMP1_GREATER HRTIM_TIMCR2_GTCMP1 /*!< event is generated when counter is greater than compare value */
#define LL_HRTIM_GTCMP3_EQUAL 0x00000000U /*!< event is generated when counter is equal to compare value */
#define LL_HRTIM_GTCMP3_GREATER HRTIM_TIMCR2_GTCMP3 /*!< event is generated when counter is greater than compare value */
/**
* @}
*/
/** @defgroup HRTIM_LL_COUNTER_DCDE Enabling the Dual Channel DAC Triggering
* @{
* @brief Constants enabling the Dual Channel DAC Reset trigger mechanism.
*/
#define LL_HRTIM_DCDE_DISABLED 0x00000000U /*!< Dual Channel DAC trigger is generated on counter reset or roll-over event */
#define LL_HRTIM_DCDE_ENABLED HRTIM_TIMCR2_DCDE /*!< Dual Channel DAC trigger is generated on output 1 set event */
/**
* @}
*/
/** @defgroup HRTIM_LL_COUNTER_DCDR Dual Channel DAC Reset Trigger
* @{
* @brief Constants defining the Dual Channel DAC Reset trigger.
*/
#define LL_HRTIM_DCDR_COUNTER 0x00000000U /*!< Dual Channel DAC trigger is generated on counter reset or roll-over event */
#define LL_HRTIM_DCDR_OUT1SET HRTIM_TIMCR2_DCDR /*!< Dual Channel DAC trigger is generated on output 1 set event */
/**
* @}
*/
/** @defgroup HRTIM_LL_COUNTER_DCDS Dual Channel DAC Step trigger
* @{
* @brief Constants defining the Dual Channel DAC Step trigger.
*/
#define LL_HRTIM_DCDS_CMP2 0x00000000U /*!< trigger is generated on compare 2 event */
#define LL_HRTIM_DCDS_OUT1RST HRTIM_TIMCR2_DCDS /*!< trigger is generated on output 1 reset event */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup HRTIM_LL_Exported_Macros HRTIM Exported Macros
* @{
*/
/** @defgroup HRTIM_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in HRTIM register
* @param __INSTANCE__ HRTIM Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_HRTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in HRTIM register
* @param __INSTANCE__ HRTIM Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_HRTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/** @defgroup HRTIM_LL_EM_Exported_Macros Exported_Macros
* @{
*/
/**
* @brief HELPER macro returning the output state from output enable/disable status
* @param __OUTPUT_STATUS_EN__ output enable status
* @param __OUTPUT_STATUS_DIS__ output Disable status
* @retval Returned value can be one of the following values:
* @arg @ref LL_HRTIM_OUTPUTSTATE_IDLE
* @arg @ref LL_HRTIM_OUTPUTSTATE_RUN
* @arg @ref LL_HRTIM_OUTPUTSTATE_FAULT
*/
#define __LL_HRTIM_GET_OUTPUT_STATE(__OUTPUT_STATUS_EN__, __OUTPUT_STATUS_DIS__)\
(((__OUTPUT_STATUS_EN__) == 1) ? LL_HRTIM_OUTPUTSTATE_RUN :\
((__OUTPUT_STATUS_DIS__) == 0) ? LL_HRTIM_OUTPUTSTATE_IDLE : LL_HRTIM_OUTPUTSTATE_FAULT)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup HRTIM_LL_Exported_Functions HRTIM Exported Functions
* @{
*/
/** @defgroup HRTIM_LL_EF_HRTIM_Control HRTIM_Control
* @{
*/
/**
* @brief Select the HRTIM synchronization input source.
* @note This function must not be called when the concerned timer(s) is (are) enabled .
* @rmtoll MCR SYNCIN LL_HRTIM_SetSyncInSrc
* @param HRTIMx High Resolution Timer instance
* @param SyncInSrc This parameter can be one of the following values:
* @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
* @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
* @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_SetSyncInSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncInSrc)
{
MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN, SyncInSrc);
}
/**
* @brief Get actual HRTIM synchronization input source.
* @rmtoll MCR SYNCIN LL_HRTIM_SetSyncInSrc
* @param HRTIMx High Resolution Timer instance
* @retval SyncInSrc Returned value can be one of the following values:
* @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
* @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
* @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
*/
__STATIC_INLINE uint32_t LL_HRTIM_GetSyncInSrc(HRTIM_TypeDef *HRTIMx)
{
return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN));
}
/**
* @brief Configure the HRTIM synchronization output.
* @rmtoll MCR SYNCSRC LL_HRTIM_ConfigSyncOut\n
* MCR SYNCOUT LL_HRTIM_ConfigSyncOut
* @param HRTIMx High Resolution Timer instance
* @param Config This parameter can be one of the following values:
* @arg @ref LL_HRTIM_SYNCOUT_DISABLED
* @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
* @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
* @param Src This parameter can be one of the following values:
* @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
* @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
* @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
* @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ConfigSyncOut(HRTIM_TypeDef *HRTIMx, uint32_t Config, uint32_t Src)
{
MODIFY_REG(HRTIMx->sMasterRegs.MCR, (HRTIM_MCR_SYNC_OUT | HRTIM_MCR_SYNC_SRC), (Config | Src));
}
/**
* @brief Set the routing and conditioning of the synchronization output event.
* @rmtoll MCR SYNCOUT LL_HRTIM_SetSyncOutConfig
* @note This function can be called only when the master timer is enabled.
* @param HRTIMx High Resolution Timer instance
* @param SyncOutConfig This parameter can be one of the following values:
* @arg @ref LL_HRTIM_SYNCOUT_DISABLED
* @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
* @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_SetSyncOutConfig(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutConfig)
{
MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT, SyncOutConfig);
}
/**
* @brief Get actual routing and conditioning of the synchronization output event.
* @rmtoll MCR SYNCOUT LL_HRTIM_GetSyncOutConfig
* @param HRTIMx High Resolution Timer instance
* @retval SyncOutConfig Returned value can be one of the following values:
* @arg @ref LL_HRTIM_SYNCOUT_DISABLED
* @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
* @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
*/
__STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutConfig(HRTIM_TypeDef *HRTIMx)
{
return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT));
}
/**
* @brief Set the source and event to be sent on the HRTIM synchronization output.
* @rmtoll MCR SYNCSRC LL_HRTIM_SetSyncOutSrc
* @param HRTIMx High Resolution Timer instance
* @param SyncOutSrc This parameter can be one of the following values:
* @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
* @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
* @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
* @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_SetSyncOutSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutSrc)
{
MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC, SyncOutSrc);
}
/**
* @brief Get actual source and event sent on the HRTIM synchronization output.
* @rmtoll MCR SYNCSRC LL_HRTIM_GetSyncOutSrc
* @param HRTIMx High Resolution Timer instance
* @retval SyncOutSrc Returned value can be one of the following values:
* @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
* @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
* @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
* @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
*/
__STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutSrc(HRTIM_TypeDef *HRTIMx)
{
return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC));
}
/**
* @brief Disable (temporarily) update event generation.
* @rmtoll CR1 MUDIS LL_HRTIM_SuspendUpdate\n
* CR1 TAUDIS LL_HRTIM_SuspendUpdate\n
* CR1 TBUDIS LL_HRTIM_SuspendUpdate\n
* CR1 TCUDIS LL_HRTIM_SuspendUpdate\n
* CR1 TDUDIS LL_HRTIM_SuspendUpdate\n
* CR1 TEUDIS LL_HRTIM_SuspendUpdate\n
* CR1 TFUDIS LL_HRTIM_SuspendUpdate
* @note Allow to temporarily disable the transfer from preload to active
* registers, whatever the selected update event. This allows to modify
* several registers in multiple timers.
* @param HRTIMx High Resolution Timer instance
* @param Timers This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_SuspendUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
{
/* clear register before applying the new value */
CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((LL_HRTIM_TIMER_ALL >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
SET_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
}
/**
* @brief Enable update event generation.
* @rmtoll CR1 MUDIS LL_HRTIM_ResumeUpdate\n
* CR1 TAUDIS LL_HRTIM_ResumeUpdate\n
* CR1 TBUDIS LL_HRTIM_ResumeUpdate\n
* CR1 TCUDIS LL_HRTIM_ResumeUpdate\n
* CR1 TDUDIS LL_HRTIM_ResumeUpdate\n
* CR1 TEUDIS LL_HRTIM_ResumeUpdate\n
* CR1 TFUDIS LL_HRTIM_ResumeUpdate
* @note The regular update event takes place.
* @param HRTIMx High Resolution Timer instance
* @param Timers This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ResumeUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
{
CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
}
/**
* @brief Force an immediate transfer from the preload to the active register .
* @rmtoll CR2 MSWU LL_HRTIM_ForceUpdate\n
* CR2 TASWU LL_HRTIM_ForceUpdate\n
* CR2 TBSWU LL_HRTIM_ForceUpdate\n
* CR2 TCSWU LL_HRTIM_ForceUpdate\n
* CR2 TDSWU LL_HRTIM_ForceUpdate\n
* CR2 TESWU LL_HRTIM_ForceUpdate\n
* CR2 TFSWU LL_HRTIM_ForceUpdate
* @note Any pending update request is cancelled.
* @param HRTIMx High Resolution Timer instance
* @param Timers This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ForceUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
{
SET_BIT(HRTIMx->sCommonRegs.CR2, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR2_SWUPD_MASK));
}
/**
* @brief Reset the HRTIM timer(s) counter.
* @rmtoll CR2 MRST LL_HRTIM_CounterReset\n
* CR2 TARST LL_HRTIM_CounterReset\n
* CR2 TBRST LL_HRTIM_CounterReset\n
* CR2 TCRST LL_HRTIM_CounterReset\n
* CR2 TDRST LL_HRTIM_CounterReset\n
* CR2 TERST LL_HRTIM_CounterReset\n
* CR2 TFRST LL_HRTIM_CounterReset
* @param HRTIMx High Resolution Timer instance
* @param Timers This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_CounterReset(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
{
SET_BIT(HRTIMx->sCommonRegs.CR2, (((Timers >> HRTIM_MCR_MCEN_Pos) << HRTIM_CR2_MRST_Pos) & HRTIM_CR2_SWRST_MASK));
}
/**
* @brief enable the swap of the Timer Output.
* @note the HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A2,
* and the HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A1
* @note This bit is not significant when the Push-pull mode is enabled (PSHPLL = 1)
* @rmtoll CR2 SWPA LL_HRTIM_EnableSwapOutputs\n
* CR2 SWPB LL_HRTIM_EnableSwapOutputs\n
* CR2 SWPC LL_HRTIM_EnableSwapOutputs\n
* CR2 SWPD LL_HRTIM_EnableSwapOutputs\n
* CR2 SWPE LL_HRTIM_EnableSwapOutputs\n
* CR2 SWPF LL_HRTIM_EnableSwapOutputs
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableSwapOutputs(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
SET_BIT(HRTIMx->sCommonRegs.CR2, (uint32_t)(HRTIM_CR2_SWPA) << iTimer);
}
/**
* @brief disable the swap of the Timer Output.
* @note the HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A1,
* and the HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A2
* @note This bit is not significant when the Push-pull mode is enabled (PSHPLL = 1)
* @rmtoll CR2 SWPA LL_HRTIM_DisableSwapOutputs\n
* CR2 SWPB LL_HRTIM_DisableSwapOutputs\n
* CR2 SWPC LL_HRTIM_DisableSwapOutputs\n
* CR2 SWPD LL_HRTIM_DisableSwapOutputs\n
* CR2 SWPE LL_HRTIM_DisableSwapOutputs\n
* CR2 SWPF LL_HRTIM_DisableSwapOutputs
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableSwapOutputs(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
CLEAR_BIT(HRTIMx->sCommonRegs.CR2, (HRTIM_CR2_SWPA << iTimer));
}
/**
* @brief reports the Timer Outputs swap position.
* @note This bit is not significant when the Push-pull mode is enabled (PSHPLL = 1)
* @rmtoll CR2 SWPA LL_HRTIM_IsEnabledSwapOutputs\n
* CR2 SWPB LL_HRTIM_IsEnabledSwapOutputs\n
* CR2 SWPC LL_HRTIM_IsEnabledSwapOutputs\n
* CR2 SWPD LL_HRTIM_IsEnabledSwapOutputs\n
* CR2 SWPE LL_HRTIM_IsEnabledSwapOutputs\n
* CR2 SWPF LL_HRTIM_IsEnabledSwapOutputs
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval
* 1: HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A2,
* HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A1
* 0: HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A1,
* HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A2
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledSwapOutputs(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
register uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos) & 0x1FU);
return (READ_BIT(HRTIMx->sCommonRegs.CR2, (uint32_t)(HRTIM_CR2_SWPA) << iTimer) >> ((HRTIM_CR2_SWPA_Pos + iTimer)));
}
/**
* @brief Enable the HRTIM timer(s) output(s) .
* @rmtoll OENR TA1OEN LL_HRTIM_EnableOutput\n
* OENR TA2OEN LL_HRTIM_EnableOutput\n
* OENR TB1OEN LL_HRTIM_EnableOutput\n
* OENR TB2OEN LL_HRTIM_EnableOutput\n
* OENR TC1OEN LL_HRTIM_EnableOutput\n
* OENR TC2OEN LL_HRTIM_EnableOutput\n
* OENR TD1OEN LL_HRTIM_EnableOutput\n
* OENR TD2OEN LL_HRTIM_EnableOutput\n
* OENR TE1OEN LL_HRTIM_EnableOutput\n
* OENR TE2OEN LL_HRTIM_EnableOutput\n
* OENR TF1OEN LL_HRTIM_EnableOutput\n
* OENR TF2OEN LL_HRTIM_EnableOutput
* @param HRTIMx High Resolution Timer instance
* @param Outputs This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_OUTPUT_TA1
* @arg @ref LL_HRTIM_OUTPUT_TA2
* @arg @ref LL_HRTIM_OUTPUT_TB1
* @arg @ref LL_HRTIM_OUTPUT_TB2
* @arg @ref LL_HRTIM_OUTPUT_TC1
* @arg @ref LL_HRTIM_OUTPUT_TC2
* @arg @ref LL_HRTIM_OUTPUT_TD1
* @arg @ref LL_HRTIM_OUTPUT_TD2
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @arg @ref LL_HRTIM_OUTPUT_TF1
* @arg @ref LL_HRTIM_OUTPUT_TF2
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)
{
SET_BIT(HRTIMx->sCommonRegs.OENR, (Outputs & HRTIM_OENR_OEN_MASK));
}
/**
* @brief Disable the HRTIM timer(s) output(s) .
* @rmtoll OENR TA1OEN LL_HRTIM_DisableOutput\n
* OENR TA2OEN LL_HRTIM_DisableOutput\n
* OENR TB1OEN LL_HRTIM_DisableOutput\n
* OENR TB2OEN LL_HRTIM_DisableOutput\n
* OENR TC1OEN LL_HRTIM_DisableOutput\n
* OENR TC2OEN LL_HRTIM_DisableOutput\n
* OENR TD1OEN LL_HRTIM_DisableOutput\n
* OENR TD2OEN LL_HRTIM_DisableOutput\n
* OENR TE1OEN LL_HRTIM_DisableOutput\n
* OENR TE2OEN LL_HRTIM_DisableOutput\n
* OENR TF1OEN LL_HRTIM_DisableOutput\n
* OENR TF2OEN LL_HRTIM_DisableOutput
* @param HRTIMx High Resolution Timer instance
* @param Outputs This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_OUTPUT_TA1
* @arg @ref LL_HRTIM_OUTPUT_TA2
* @arg @ref LL_HRTIM_OUTPUT_TB1
* @arg @ref LL_HRTIM_OUTPUT_TB2
* @arg @ref LL_HRTIM_OUTPUT_TC1
* @arg @ref LL_HRTIM_OUTPUT_TC2
* @arg @ref LL_HRTIM_OUTPUT_TD1
* @arg @ref LL_HRTIM_OUTPUT_TD2
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @arg @ref LL_HRTIM_OUTPUT_TF1
* @arg @ref LL_HRTIM_OUTPUT_TF2
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)
{
SET_BIT(HRTIMx->sCommonRegs.ODISR, (Outputs & HRTIM_OENR_ODIS_MASK));
}
/**
* @brief Indicates whether the HRTIM timer output is enabled.
* @rmtoll OENR TA1OEN LL_HRTIM_IsEnabledOutput\n
* OENR TA2OEN LL_HRTIM_IsEnabledOutput\n
* OENR TB1OEN LL_HRTIM_IsEnabledOutput\n
* OENR TB2OEN LL_HRTIM_IsEnabledOutput\n
* OENR TC1OEN LL_HRTIM_IsEnabledOutput\n
* OENR TC2OEN LL_HRTIM_IsEnabledOutput\n
* OENR TD1OEN LL_HRTIM_IsEnabledOutput\n
* OENR TD2OEN LL_HRTIM_IsEnabledOutput\n
* OENR TE1OEN LL_HRTIM_IsEnabledOutput\n
* OENR TE2OEN LL_HRTIM_IsEnabledOutput\n
* OENR TF1OEN LL_HRTIM_IsEnabledOutput\n
* OENR TF2OEN LL_HRTIM_IsEnabledOutput
* @param HRTIMx High Resolution Timer instance
* @param Output This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUTPUT_TA1
* @arg @ref LL_HRTIM_OUTPUT_TA2
* @arg @ref LL_HRTIM_OUTPUT_TB1
* @arg @ref LL_HRTIM_OUTPUT_TB2
* @arg @ref LL_HRTIM_OUTPUT_TC1
* @arg @ref LL_HRTIM_OUTPUT_TC2
* @arg @ref LL_HRTIM_OUTPUT_TD1
* @arg @ref LL_HRTIM_OUTPUT_TD2
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @arg @ref LL_HRTIM_OUTPUT_TF1
* @arg @ref LL_HRTIM_OUTPUT_TF2
* @retval State of TxyOEN bit in HRTIM_OENR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledOutput(HRTIM_TypeDef *HRTIMx, uint32_t Output)
{
return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == Output) ? 1UL : 0UL);
}
/**
* @brief Indicates whether the HRTIM timer output is disabled.
* @rmtoll ODISR TA1ODIS LL_HRTIM_IsDisabledOutput\n
* ODISR TA2ODIS LL_HRTIM_IsDisabledOutput\n
* ODISR TB1ODIS LL_HRTIM_IsDisabledOutput\n
* ODISR TB2ODIS LL_HRTIM_IsDisabledOutput\n
* ODISR TC1ODIS LL_HRTIM_IsDisabledOutput\n
* ODISR TC2ODIS LL_HRTIM_IsDisabledOutput\n
* ODISR TD1ODIS LL_HRTIM_IsDisabledOutput\n
* ODISR TD2ODIS LL_HRTIM_IsDisabledOutput\n
* ODISR TE1ODIS LL_HRTIM_IsDisabledOutput\n
* ODISR TE2ODIS LL_HRTIM_IsDisabledOutput\n
* ODISR TF1ODIS LL_HRTIM_IsDisabledOutput\n
* ODISR TF2ODIS LL_HRTIM_IsDisabledOutput
* @param HRTIMx High Resolution Timer instance
* @param Output This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUTPUT_TA1
* @arg @ref LL_HRTIM_OUTPUT_TA2
* @arg @ref LL_HRTIM_OUTPUT_TB1
* @arg @ref LL_HRTIM_OUTPUT_TB2
* @arg @ref LL_HRTIM_OUTPUT_TC1
* @arg @ref LL_HRTIM_OUTPUT_TC2
* @arg @ref LL_HRTIM_OUTPUT_TD1
* @arg @ref LL_HRTIM_OUTPUT_TD2
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @arg @ref LL_HRTIM_OUTPUT_TF1
* @arg @ref LL_HRTIM_OUTPUT_TF2
* @retval State of TxyODS bit in HRTIM_OENR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(HRTIM_TypeDef *HRTIMx, uint32_t Output)
{
return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == 0U) ? 1UL : 0UL);
}
/**
* @brief Configure an ADC trigger.
* @rmtoll CR1 ADC1USRC LL_HRTIM_ConfigADCTrig\n
* CR1 ADC2USRC LL_HRTIM_ConfigADCTrig\n
* CR1 ADC3USRC LL_HRTIM_ConfigADCTrig\n
* CR1 ADC4USRC LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1MC1 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1MC2 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1MC3 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1MC4 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1MPER LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1EEV1 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1EEV2 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1EEV3 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1EEV4 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1EEV5 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TFC2 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TAC3 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TAC4 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TAPER LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TARST LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TFC3 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TBC3 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TBC4 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TBPER LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TBRST LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TFC4 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TCC3 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TCC4 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TCPER LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TFPER LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TDC3 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TDC4 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TDPER LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TFRST LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TEC3 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TEC4 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TEPER LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2MC1 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2MC2 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2MC3 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2MC4 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2MPER LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2EEV6 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2EEV7 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2EEV8 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2EEV9 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2EEV10 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TAC2 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TFC2 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TAC4 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TAPER LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TBC2 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TFC3 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TBC4 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TBPER LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TCC2 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TFC4 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TCC4 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TCPER LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TCRST LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TDC2 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TFPER LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TDC4 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TDPER LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TDRST LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TEC2 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TEC3 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TEC4 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TERST LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3MC1 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3MC2 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3MC3 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3MC4 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3MPER LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3EEV1 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3EEV2 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3EEV3 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3EEV4 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3EEV5 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TFC2 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TAC3 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TAC4 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TAPER LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TARST LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TFC3 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TBC3 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TBC4 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TBPER LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TBRST LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TFC4 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TCC3 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TCC4 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TCPER LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TFPER LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TDC3 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TDC4 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TDPER LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TFRST LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TEC3 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TEC4 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TEPER LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4MC1 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4MC2 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4MC3 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4MC4 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4MPER LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4EEV6 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4EEV7 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4EEV8 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4EEV9 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4EEV10 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TAC2 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TFC2 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TAC4 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TAPER LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TBC2 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TFC3 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TBC4 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TBPER LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TCC2 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TFC4 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TCC4 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TCPER LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TCRST LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TDC2 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TFPER LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TDC4 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TDPER LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TDRST LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TEC2 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TEC3 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TEC4 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TERST LL_HRTIM_ConfigADCTrig
* @param HRTIMx High Resolution Timer instance
* @param ADCTrig This parameter can be one of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_1
* @arg @ref LL_HRTIM_ADCTRIG_2
* @arg @ref LL_HRTIM_ADCTRIG_3
* @arg @ref LL_HRTIM_ADCTRIG_4
* @param Update This parameter can be one of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_F
* @param Src This parameter can be a combination of the following values:
*
* For ADC trigger 1 and ADC trigger 3:
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFRST
*
* For ADC trigger 2 and ADC trigger 4:
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFPER
*
* For ADC trigger 5, ADC trigger 7 and ADC trigger 9 this parameter
* can be one of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP1
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_MPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV1
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV2
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV5
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_RST
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_RST
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_RST
*
* For ADC trigger 6, ADC trigger 8 and ADC trigger 10 this parameter
* can be one of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP1
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV6
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV7
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV8
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV9
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV10
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_RST
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update, uint32_t Src)
{
register __IO uint32_t *padcur = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) +
REG_OFFSET_TAB_ADCUR[ADCTrig]));
register __IO uint32_t *padcer = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
REG_OFFSET_TAB_ADCER[ADCTrig]));
MODIFY_REG(*padcur, REG_MASK_TAB_ADCUR[ADCTrig], (Update << REG_SHIFT_TAB_ADCUR[ADCTrig]));
MODIFY_REG(*padcer, REG_MASK_TAB_ADCER[ADCTrig], (Src << REG_SHIFT_TAB_ADCER[ADCTrig]));
}
/**
* @brief Associate the ADCx trigger to a timer triggering the update of the HRTIM_ADCxR register.
* @rmtoll CR1 ADC1USRC LL_HRTIM_SetADCTrigUpdate\n
* CR1 ADC2USRC LL_HRTIM_SetADCTrigUpdate\n
* CR1 ADC3USRC LL_HRTIM_SetADCTrigUpdate\n
* CR1 ADC4USRC LL_HRTIM_SetADCTrigUpdate\n
* ADCUR ADC5USRC LL_HRTIM_SetADCTrigUpdate\n
* ADCUR ADC6USRC LL_HRTIM_SetADCTrigUpdate\n
* ADCUR ADC7USRC LL_HRTIM_SetADCTrigUpdate\n
* ADCUR ADC8USRC LL_HRTIM_SetADCTrigUpdate\n
* ADCUR ADC9USRC LL_HRTIM_SetADCTrigUpdate\n
* ADCUR ADC10USRC LL_HRTIM_SetADCTrigUpdate
* @note When the preload is disabled in the source timer, the HRTIM_ADCxR
* registers are not preloaded either: a write access will result in an
* immediate update of the trigger source.
* @param HRTIMx High Resolution Timer instance
* @param ADCTrig This parameter can be one of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_1
* @arg @ref LL_HRTIM_ADCTRIG_2
* @arg @ref LL_HRTIM_ADCTRIG_3
* @arg @ref LL_HRTIM_ADCTRIG_4
* @arg @ref LL_HRTIM_ADCTRIG_5
* @arg @ref LL_HRTIM_ADCTRIG_6
* @arg @ref LL_HRTIM_ADCTRIG_7
* @arg @ref LL_HRTIM_ADCTRIG_8
* @arg @ref LL_HRTIM_ADCTRIG_9
* @arg @ref LL_HRTIM_ADCTRIG_10
* @param Update This parameter can be one of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update)
{
register __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) +
REG_OFFSET_TAB_ADCUR[ADCTrig]));
MODIFY_REG(*preg, REG_MASK_TAB_ADCUR[ADCTrig], (Update << REG_SHIFT_TAB_ADCUR[ADCTrig]));
}
/**
* @brief Get the source timer triggering the update of the HRTIM_ADCxR register.
* @rmtoll CR1 ADC1USRC LL_HRTIM_GetADCTrigUpdate\n
* CR1 ADC2USRC LL_HRTIM_GetADCTrigUpdate\n
* CR1 ADC3USRC LL_HRTIM_GetADCTrigUpdate\n
* CR1 ADC4USRC LL_HRTIM_GetADCTrigUpdate\n
* ADCUR ADC5USRC LL_HRTIM_GetADCTrigUpdate\n
* ADCUR ADC6USRC LL_HRTIM_GetADCTrigUpdate\n
* ADCUR ADC7USRC LL_HRTIM_GetADCTrigUpdate\n
* ADCUR ADC8USRC LL_HRTIM_GetADCTrigUpdate\n
* ADCUR ADC9USRC LL_HRTIM_GetADCTrigUpdate\n
* ADCUR ADC10USRC LL_HRTIM_GetADCTrigUpdate
* @param HRTIMx High Resolution Timer instance
* @param ADCTrig This parameter can be one of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_1
* @arg @ref LL_HRTIM_ADCTRIG_2
* @arg @ref LL_HRTIM_ADCTRIG_3
* @arg @ref LL_HRTIM_ADCTRIG_4
* @arg @ref LL_HRTIM_ADCTRIG_5
* @arg @ref LL_HRTIM_ADCTRIG_6
* @arg @ref LL_HRTIM_ADCTRIG_7
* @arg @ref LL_HRTIM_ADCTRIG_8
* @arg @ref LL_HRTIM_ADCTRIG_9
* @arg @ref LL_HRTIM_ADCTRIG_10
* @retval Update Returned value can be one of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_F
*/
__STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
{
register const __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) +
REG_OFFSET_TAB_ADCUR[ADCTrig]));
return (READ_BIT(*preg, (REG_MASK_TAB_ADCUR[ADCTrig])) >> REG_SHIFT_TAB_ADCUR[ADCTrig]);
}
/**
* @brief Specify which events (timer events and/or external events) are used as triggers for ADC conversion.
* @rmtoll ADC1R ADC1MC1 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1MC2 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1MC3 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1MC4 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1MPER LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1EEV1 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1EEV2 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1EEV3 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1EEV4 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1EEV5 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TFC2 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TAC3 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TAC4 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TAPER LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TARST LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TFC3 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TBC3 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TBC4 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TBPER LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TBRST LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TFC4 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TCC3 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TCC4 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TCPER LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TFPER LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TDC3 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TDC4 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TDPER LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TFRST LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TEC3 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TEC4 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TEPER LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2MC1 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2MC2 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2MC3 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2MC4 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2MPER LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2EEV6 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2EEV7 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2EEV8 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2EEV9 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2EEV10 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TAC2 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TFC2 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TAC4 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TAPER LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TBC2 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TFC3 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TBC4 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TBPER LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TCC2 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TFC4 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TCC4 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TCPER LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TCRST LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TDC2 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TFPER LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TDC4 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TDPER LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TDRST LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TEC2 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TEC3 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TEC4 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TERST LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3MC1 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3MC2 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3MC3 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3MC4 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3MPER LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3EEV1 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3EEV2 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3EEV3 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3EEV4 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3EEV5 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TFC2 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TAC3 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TAC4 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TAPER LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TARST LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TFC3 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TBC3 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TBC4 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TBPER LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TBRST LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TFC4 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TCC3 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TCC4 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TCPER LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TFPER LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TDC3 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TDC4 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TDPER LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TFRST LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TEC3 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TEC4 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TEPER LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4MC1 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4MC2 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4MC3 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4MC4 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4MPER LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4EEV6 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4EEV7 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4EEV8 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4EEV9 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4EEV10 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TAC2 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TFC2 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TAC4 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TAPER LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TBC2 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TFC3 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TBC4 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TBPER LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TCC2 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TFC4 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TCC4 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TCPER LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TCRST LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TDC2 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TFPER LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TDC4 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TDPER LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TDRST LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TEC2 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TEC3 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TEC4 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TERST LL_HRTIM_SetADCTrigSrc\n
* ADCER ADC5TRG LL_HRTIM_SetADCTrigSrc\n
* ADCER ADC6TRG LL_HRTIM_SetADCTrigSrc\n
* ADCER ADC7TRG LL_HRTIM_SetADCTrigSrc\n
* ADCER ADC8TRG LL_HRTIM_SetADCTrigSrc\n
* ADCER ADC9TRG LL_HRTIM_SetADCTrigSrc\n
* ADCER ADC10TRG LL_HRTIM_SetADCTrigSrc
* @param HRTIMx High Resolution Timer instance
* @param ADCTrig This parameter can be one of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_1
* @arg @ref LL_HRTIM_ADCTRIG_2
* @arg @ref LL_HRTIM_ADCTRIG_3
* @arg @ref LL_HRTIM_ADCTRIG_4
* @arg @ref LL_HRTIM_ADCTRIG_5
* @arg @ref LL_HRTIM_ADCTRIG_6
* @arg @ref LL_HRTIM_ADCTRIG_7
* @arg @ref LL_HRTIM_ADCTRIG_8
* @arg @ref LL_HRTIM_ADCTRIG_9
* @arg @ref LL_HRTIM_ADCTRIG_10
* @param Src
* For ADC trigger 1 and ADC trigger 3 this parameter can be a
* combination of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFRST