Release v1.8.0
diff --git a/.github/PULL_REQUEST_TEMPLATE.md b/.github/PULL_REQUEST_TEMPLATE.md
index 5392390..0c54e55 100644
--- a/.github/PULL_REQUEST_TEMPLATE.md
+++ b/.github/PULL_REQUEST_TEMPLATE.md
@@ -2,4 +2,4 @@
### Contributor License Agreement (CLA)
* The Pull Request feature will be considered by STMicroelectronics after the signature of a **Contributor License Agreement (CLA)** by the submitter.
-* If you did not sign such agreement, please follow the steps mentioned in the CONTRIBUTING.md file.
+* If you did not sign such agreement, please follow the steps mentioned in the [CONTRIBUTING.md](https://github.com/STMicroelectronics/stm32h7xx_hal_driver/blob/master/CONTRIBUTING.md) file.
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index 78c8d9c..805a9a5 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -241,7 +241,7 @@
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4)
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
#endif
@@ -313,8 +313,8 @@
#endif /* STM32L4 */
#if defined(STM32G0)
-#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
-#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
+#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
#endif
#if defined(STM32H7)
@@ -955,7 +955,7 @@
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7)
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
@@ -1014,7 +1014,7 @@
/**
* @}
*/
-
+
/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
* @{
*/
@@ -1450,7 +1450,7 @@
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
-#if defined(STM32L4) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
@@ -1472,7 +1472,7 @@
#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
-#endif /* STM32L4 || STM32F4 || STM32F7 || STM32H7 */
+#endif /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */
/**
* @}
*/
@@ -1563,10 +1563,10 @@
*/
#if defined(STM32G0)
-#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
-#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
-#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
-#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
+#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
+#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
+#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
+#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
#endif
#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
@@ -3243,9 +3243,8 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-#if defined(STM32L4)
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
-#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif
@@ -3373,7 +3372,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3481,9 +3480,9 @@
#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
-#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
-#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
-#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
+#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
+#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
+#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
/* alias CMSIS for compatibilities */
#define SDIO_IRQn SDMMC1_IRQn
#define SDIO_IRQHandler SDMMC1_IRQHandler
@@ -3751,9 +3750,9 @@
/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32L4)
+#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
-#endif
+#endif /* STM32L4 || STM32F4 || STM32F7 */
/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal_gpio.h b/Inc/stm32h7xx_hal_gpio.h
index cdc9722..52f8ecd 100644
--- a/Inc/stm32h7xx_hal_gpio.h
+++ b/Inc/stm32h7xx_hal_gpio.h
@@ -296,8 +296,8 @@
* @{
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
-#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
- (((__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
+#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
+ (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
((MODE) == GPIO_MODE_OUTPUT_PP) ||\
((MODE) == GPIO_MODE_OUTPUT_OD) ||\
diff --git a/Inc/stm32h7xx_hal_gpio_ex.h b/Inc/stm32h7xx_hal_gpio_ex.h
index 1e70a71..933a4c5 100644
--- a/Inc/stm32h7xx_hal_gpio_ex.h
+++ b/Inc/stm32h7xx_hal_gpio_ex.h
@@ -303,7 +303,6 @@
#define GPIO_AF13_PSSI ((uint8_t)0x0D) /* PSSI Alternate Function mapping */
#endif /* PSSI */
#define GPIO_AF13_TIM1 ((uint8_t)0x0D) /* TIM1 Alternate Function mapping */
-#define GPIO_AF13_TIM8 ((uint8_t)0x0D) /* TIM8 Alternate Function mapping : available on STM32H74xxx/STM32H75xxx */
/**
* @brief AF 14 selection
@@ -364,7 +363,7 @@
#define GPIOI_PIN_AVAILABLE GPIO_PIN_All
#define GPIOJ_PIN_AVAILABLE GPIO_PIN_All
#define GPIOH_PIN_AVAILABLE GPIO_PIN_All
-#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | \
+#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \
GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)
/**
diff --git a/Inc/stm32h7xx_hal_hrtim.h b/Inc/stm32h7xx_hal_hrtim.h
index e727bc5..c2be7a5 100644
--- a/Inc/stm32h7xx_hal_hrtim.h
+++ b/Inc/stm32h7xx_hal_hrtim.h
@@ -654,11 +654,6 @@
* @{
* @brief Constants defining timer high-resolution clock prescaler ratio.
*/
-#define HRTIM_PRESCALERRATIO_MUL32 (0x00000000U) /*!< fHRCK: fHRTIM x 32U = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
-#define HRTIM_PRESCALERRATIO_MUL16 (0x00000001U) /*!< fHRCK: fHRTIM x 16U = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
-#define HRTIM_PRESCALERRATIO_MUL8 (0x00000002U) /*!< fHRCK: fHRTIM x 8U = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
-#define HRTIM_PRESCALERRATIO_MUL4 (0x00000003U) /*!< fHRCK: fHRTIM x 4U = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
-#define HRTIM_PRESCALERRATIO_MUL2 (0x00000004U) /*!< fHRCK: fHRTIM x 2U = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
#define HRTIM_PRESCALERRATIO_DIV1 (0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
#define HRTIM_PRESCALERRATIO_DIV2 (0x00000006U) /*!< fHRCK: fHRTIM / 2U = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
#define HRTIM_PRESCALERRATIO_DIV4 (0x00000007U) /*!< fHRCK: fHRTIM / 4U = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
@@ -2083,12 +2078,7 @@
((FAULT) == HRTIM_FAULT_5))
#define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\
- (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \
- ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \
- ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) || \
- ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) || \
- ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) || \
- ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \
+ (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4))
@@ -3117,11 +3107,6 @@
* @arg 0x0 to 0x4 for timers A to E
* @param __PRESCALER__ specifies the clock prescaler new value.
* This parameter can be one of the following values:
- * @arg HRTIM_PRESCALERRATIO_MUL32: fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz)
- * @arg HRTIM_PRESCALERRATIO_MUL16: fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz)
- * @arg HRTIM_PRESCALERRATIO_MUL8: fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)
- * @arg HRTIM_PRESCALERRATIO_MUL4: fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)
- * @arg HRTIM_PRESCALERRATIO_MUL2: fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)
* @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)
* @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)
* @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)
diff --git a/Inc/stm32h7xx_hal_nand.h b/Inc/stm32h7xx_hal_nand.h
index ce956fb..ccf984c 100644
--- a/Inc/stm32h7xx_hal_nand.h
+++ b/Inc/stm32h7xx_hal_nand.h
@@ -271,33 +271,33 @@
/** @defgroup NAND_Private_Constants NAND Private Constants
* @{
*/
-#define NAND_DEVICE ((uint32_t)0x80000000U)
-#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U)
+#define NAND_DEVICE 0x80000000UL
+#define NAND_WRITE_TIMEOUT 0x01000000UL
-#define CMD_AREA ((uint32_t)(1UL<<16U)) /* A16 = CLE high */
-#define ADDR_AREA ((uint32_t)(1UL<<17U)) /* A17 = ALE high */
+#define CMD_AREA (1UL<<16U) /* A16 = CLE high */
+#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */
-#define NAND_CMD_AREA_A ((uint8_t)0x00U)
-#define NAND_CMD_AREA_B ((uint8_t)0x01U)
-#define NAND_CMD_AREA_C ((uint8_t)0x50U)
-#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U)
+#define NAND_CMD_AREA_A 0x00U
+#define NAND_CMD_AREA_B 0x01U
+#define NAND_CMD_AREA_C 0x50U
+#define NAND_CMD_AREA_TRUE1 0x30U
-#define NAND_CMD_WRITE0 ((uint8_t)0x80U)
-#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U)
-#define NAND_CMD_ERASE0 ((uint8_t)0x60U)
-#define NAND_CMD_ERASE1 ((uint8_t)0xD0U)
-#define NAND_CMD_READID ((uint8_t)0x90U)
-#define NAND_CMD_STATUS ((uint8_t)0x70U)
-#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU)
-#define NAND_CMD_RESET ((uint8_t)0xFFU)
+#define NAND_CMD_WRITE0 0x80U
+#define NAND_CMD_WRITE_TRUE1 0x10U
+#define NAND_CMD_ERASE0 0x60U
+#define NAND_CMD_ERASE1 0xD0U
+#define NAND_CMD_READID 0x90U
+#define NAND_CMD_STATUS 0x70U
+#define NAND_CMD_LOCK_STATUS 0x7AU
+#define NAND_CMD_RESET 0xFFU
/* NAND memory status */
-#define NAND_VALID_ADDRESS ((uint32_t)0x00000100U)
-#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U)
-#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U)
-#define NAND_BUSY ((uint32_t)0x00000000U)
-#define NAND_ERROR ((uint32_t)0x00000001U)
-#define NAND_READY ((uint32_t)0x00000040U)
+#define NAND_VALID_ADDRESS 0x00000100UL
+#define NAND_INVALID_ADDRESS 0x00000200UL
+#define NAND_TIMEOUT_ERROR 0x00000400UL
+#define NAND_BUSY 0x00000000UL
+#define NAND_ERROR 0x00000001UL
+#define NAND_READY 0x00000040UL
/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal_nor.h b/Inc/stm32h7xx_hal_nor.h
index d767cf5..04a3800 100644
--- a/Inc/stm32h7xx_hal_nor.h
+++ b/Inc/stm32h7xx_hal_nor.h
@@ -245,29 +245,29 @@
* @{
*/
/* NOR device IDs addresses */
-#define MC_ADDRESS ((uint16_t)0x0000U)
-#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U)
-#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU)
-#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU)
+#define MC_ADDRESS ((uint16_t)0x0000)
+#define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
+#define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
+#define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
/* NOR CFI IDs addresses */
-#define CFI1_ADDRESS ((uint16_t)0x61U)
-#define CFI2_ADDRESS ((uint16_t)0x62U)
-#define CFI3_ADDRESS ((uint16_t)0x63U)
-#define CFI4_ADDRESS ((uint16_t)0x64U)
+#define CFI1_ADDRESS ((uint16_t)0x61)
+#define CFI2_ADDRESS ((uint16_t)0x62)
+#define CFI3_ADDRESS ((uint16_t)0x63)
+#define CFI4_ADDRESS ((uint16_t)0x64)
/* NOR operation wait timeout */
-#define NOR_TMEOUT ((uint16_t)0xFFFFU)
+#define NOR_TMEOUT ((uint16_t)0xFFFF)
/* NOR memory data width */
-#define NOR_MEMORY_8B ((uint8_t)0x0U)
-#define NOR_MEMORY_16B ((uint8_t)0x1U)
+#define NOR_MEMORY_8B ((uint8_t)0x0)
+#define NOR_MEMORY_16B ((uint8_t)0x1)
/* NOR memory device read/write start address */
-#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U)
-#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U)
-#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U)
-#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U)
+#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000)
+#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000)
+#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000)
+#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000)
/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal_ospi.h b/Inc/stm32h7xx_hal_ospi.h
index d2ee43c..35da484 100644
--- a/Inc/stm32h7xx_hal_ospi.h
+++ b/Inc/stm32h7xx_hal_ospi.h
@@ -259,6 +259,9 @@
This parameter can be a value of @ref OSPIM_IOPort */
uint32_t IOHighPort; /* It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins.
This parameter can be a value of @ref OSPIM_IOPort */
+ uint32_t Req2AckTime; /* It indicates the minimum switching duration (in number of clock cycles) expected
+ if some signals are multiplexed in the OSPI IO Manager with the other OSPI.
+ This parameter can be a value between 1 and 256 */
}OSPIM_CfgTypeDef;
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
@@ -683,7 +686,7 @@
* @{
*/
/** @brief Reset OSPI handle state.
- * @param __HANDLE__: OSPI handle.
+ * @param __HANDLE__ specifies the OSPI Handle.
* @retval None
*/
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
@@ -697,20 +700,20 @@
#endif
/** @brief Enable the OSPI peripheral.
- * @param __HANDLE__: specifies the OSPI Handle.
+ * @param __HANDLE__ specifies the OSPI Handle.
* @retval None
*/
#define __HAL_OSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN)
/** @brief Disable the OSPI peripheral.
- * @param __HANDLE__: specifies the OSPI Handle.
+ * @param __HANDLE__ specifies the OSPI Handle.
* @retval None
*/
#define __HAL_OSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN)
/** @brief Enable the specified OSPI interrupt.
- * @param __HANDLE__: specifies the OSPI Handle.
- * @param __INTERRUPT__: specifies the OSPI interrupt source to enable.
+ * @param __HANDLE__ specifies the OSPI Handle.
+ * @param __INTERRUPT__ specifies the OSPI interrupt source to enable.
* This parameter can be one of the following values:
* @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt
* @arg HAL_OSPI_IT_SM: OSPI Status match interrupt
@@ -723,8 +726,8 @@
/** @brief Disable the specified OSPI interrupt.
- * @param __HANDLE__: specifies the OSPI Handle.
- * @param __INTERRUPT__: specifies the OSPI interrupt source to disable.
+ * @param __HANDLE__ specifies the OSPI Handle.
+ * @param __INTERRUPT__ specifies the OSPI interrupt source to disable.
* This parameter can be one of the following values:
* @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt
* @arg HAL_OSPI_IT_SM: OSPI Status match interrupt
@@ -736,8 +739,8 @@
#define __HAL_OSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
/** @brief Check whether the specified OSPI interrupt source is enabled or not.
- * @param __HANDLE__: specifies the OSPI Handle.
- * @param __INTERRUPT__: specifies the OSPI interrupt source to check.
+ * @param __HANDLE__ specifies the OSPI Handle.
+ * @param __INTERRUPT__ specifies the OSPI interrupt source to check.
* This parameter can be one of the following values:
* @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt
* @arg HAL_OSPI_IT_SM: OSPI Status match interrupt
@@ -750,8 +753,8 @@
/**
* @brief Check whether the selected OSPI flag is set or not.
- * @param __HANDLE__: specifies the OSPI Handle.
- * @param __FLAG__: specifies the OSPI flag to check.
+ * @param __HANDLE__ specifies the OSPI Handle.
+ * @param __FLAG__ specifies the OSPI flag to check.
* This parameter can be one of the following values:
* @arg HAL_OSPI_FLAG_BUSY: OSPI Busy flag
* @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag
@@ -764,8 +767,8 @@
#define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
/** @brief Clears the specified OSPI's flag status.
- * @param __HANDLE__: specifies the OSPI Handle.
- * @param __FLAG__: specifies the OSPI clear register flag that needs to be set
+ * @param __HANDLE__ specifies the OSPI Handle.
+ * @param __FLAG__ specifies the OSPI clear register flag that needs to be set
* This parameter can be one of the following values:
* @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag
* @arg HAL_OSPI_FLAG_SM: OSPI Status match flag
@@ -1046,6 +1049,8 @@
((PORT) == HAL_OSPIM_IOPORT_7_HIGH) || \
((PORT) == HAL_OSPIM_IOPORT_8_LOW) || \
((PORT) == HAL_OSPIM_IOPORT_8_HIGH))
+
+#define IS_OSPIM_REQ2ACKTIME(TIME) (((TIME) >= 1U) && ((TIME) <= 256U))
/**
@endcond
*/
diff --git a/Inc/stm32h7xx_hal_pssi.h b/Inc/stm32h7xx_hal_pssi.h
index 8b33335..922fafa 100644
--- a/Inc/stm32h7xx_hal_pssi.h
+++ b/Inc/stm32h7xx_hal_pssi.h
@@ -239,6 +239,9 @@
#define PSSI_FLAG_RTT1B PSSI_SR_RTT1B /*!< 1 Byte Fifo Flag*/
#define PSSI_FLAG_RTT4B PSSI_SR_RTT4B /*!< 4 Bytes Fifo Flag*/
+
+
+
/**
* @}
*/
@@ -253,6 +256,9 @@
/**
* @}
*/
+
+
+
/**
* @}
*/
@@ -403,6 +409,7 @@
* @}
*/
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PSSI_Exported_Functions
* @{
@@ -411,6 +418,7 @@
/** @addtogroup PSSI_Exported_Functions_Group1
* @{
*/
+
/* Initialization and de-initialization functions *******************************/
HAL_StatusTypeDef HAL_PSSI_Init(PSSI_HandleTypeDef *hpssi);
HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi);
@@ -420,6 +428,8 @@
HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID, pPSSI_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID);
+
+
/**
* @}
*/
@@ -427,6 +437,7 @@
/** @addtogroup PSSI_Exported_Functions_Group2
* @{
*/
+
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout);
@@ -434,6 +445,7 @@
HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size);
HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi);
void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi);
+
/**
* @}
*/
@@ -441,10 +453,13 @@
/** @addtogroup PSSI_Exported_Functions_Group3
* @{
*/
+
void HAL_PSSI_TxCpltCallback(PSSI_HandleTypeDef *hpssi);
void HAL_PSSI_RxCpltCallback(PSSI_HandleTypeDef *hpssi);
void HAL_PSSI_ErrorCallback(PSSI_HandleTypeDef *hpssi);
void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi);
+
+
/**
* @}
*/
@@ -452,9 +467,11 @@
/** @addtogroup PSSI_Exported_Functions_Group4
* @{
*/
+
/* Peripheral State functions ***************************************************/
HAL_PSSI_StateTypeDef HAL_PSSI_GetState(PSSI_HandleTypeDef *hpssi);
-uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi);
+uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi);
+
/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal_qspi.h b/Inc/stm32h7xx_hal_qspi.h
index b67222d..4379cbe 100644
--- a/Inc/stm32h7xx_hal_qspi.h
+++ b/Inc/stm32h7xx_hal_qspi.h
@@ -12,7 +12,7 @@
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -25,11 +25,11 @@
extern "C" {
#endif
-#if defined(QUADSPI)
-
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
+#if defined(QUADSPI)
+
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
@@ -46,35 +46,27 @@
/**
* @brief QSPI Init structure definition
*/
-
typedef struct
{
uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
This parameter can be a number between 0 and 255 */
-
uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
This parameter can be a value between 1 and 32 */
-
uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
This parameter can be a value of @ref QSPI_SampleShifting */
-
uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
required to address the flash memory. The flash capacity can be up to 4GB
(addressed using 32 bits) in indirect mode, but the addressable space in
memory-mapped mode is limited to 256MB
This parameter can be a number between 0 and 31 */
-
uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
of clock cycles which the chip select must remain high between commands.
This parameter can be a value of @ref QSPI_ChipSelectHighTime */
-
uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
This parameter can be a value of @ref QSPI_ClockMode */
-
uint32_t FlashID; /* Specifies the Flash which will be used,
This parameter can be a value of @ref QSPI_Flash_Select */
-
uint32_t DualFlash; /* Specifies the Dual Flash Mode State
This parameter can be a value of @ref QSPI_DualFlash_Mode */
}QSPI_InitTypeDef;
@@ -102,7 +94,7 @@
typedef struct __QSPI_HandleTypeDef
#else
typedef struct
-#endif/* USE_HAL_QSPI_REGISTER_CALLBACKS */
+#endif
{
QUADSPI_TypeDef *Instance; /* QSPI registers base address */
QSPI_InitTypeDef Init; /* QSPI communication parameters */
@@ -112,7 +104,7 @@
uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
__IO uint32_t RxXferSize; /* QSPI Rx Transfer size */
__IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */
- MDMA_HandleTypeDef *hmdma; /* QSPI Rx/Tx MDMA Handle parameters */
+ MDMA_HandleTypeDef *hmdma; /* QSPI Rx/Tx MDMA Handle parameters */
__IO HAL_LockTypeDef Lock; /* Locking object */
__IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
__IO uint32_t ErrorCode; /* QSPI Error code */
@@ -157,13 +149,13 @@
This parameter can be a value of @ref QSPI_AlternateBytesMode */
uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
This parameter can be a value of @ref QSPI_DataMode */
- uint32_t NbData; /* Specifies the number of data to transfer.
+ uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes)
This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
until end of memory)*/
uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
This parameter can be a value of @ref QSPI_DdrMode */
- uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
- system clock in DDR mode.
+ uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data
+ output by one half of system clock in DDR mode.
This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
uint32_t SIOOMode; /* Specifies the send instruction only once mode
This parameter can be a value of @ref QSPI_SIOOMode */
@@ -195,7 +187,7 @@
{
uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
This parameter can be any value between 0 and 0xFFFF */
- uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select.
+ uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select.
This parameter can be a value of @ref QSPI_TimeOutActivation */
}QSPI_MemoryMappedTypeDef;
@@ -235,11 +227,11 @@
/** @defgroup QSPI_ErrorCode QSPI Error Code
* @{
*/
-#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
-#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */
-#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */
-#define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */
+#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */
+#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */
+#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */
+#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */
#endif
@@ -250,7 +242,7 @@
/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
* @{
*/
-#define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!<No clock cycle shift to sample data*/
+#define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/
#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
/**
* @}
@@ -259,7 +251,7 @@
/** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
* @{
*/
-#define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000U) /*!<nCS stay high for at least 1 clock cycle between commands*/
+#define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/
#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
@@ -274,7 +266,7 @@
/** @defgroup QSPI_ClockMode QSPI Clock Mode
* @{
*/
-#define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000) /*!<Clk stays low while nCS is released*/
+#define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/
#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
/**
* @}
@@ -283,7 +275,7 @@
/** @defgroup QSPI_Flash_Select QSPI Flash Select
* @{
*/
-#define QSPI_FLASH_ID_1 ((uint32_t)0x00000000) /*!<FLASH 1 selected*/
+#define QSPI_FLASH_ID_1 0x00000000U /*!<FLASH 1 selected*/
#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/
/**
* @}
@@ -293,7 +285,7 @@
* @{
*/
#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/
-#define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000) /*!<Dual-flash mode disabled*/
+#define QSPI_DUALFLASH_DISABLE 0x00000000U /*!<Dual-flash mode disabled*/
/**
* @}
*/
@@ -301,7 +293,7 @@
/** @defgroup QSPI_AddressSize QSPI Address Size
* @{
*/
-#define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000) /*!<8-bit address*/
+#define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/
#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/
@@ -312,7 +304,7 @@
/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
* @{
*/
-#define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000) /*!<8-bit alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/
@@ -323,7 +315,7 @@
/** @defgroup QSPI_InstructionMode QSPI Instruction Mode
* @{
*/
-#define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000) /*!<No instruction*/
+#define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/
#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/
@@ -334,7 +326,7 @@
/** @defgroup QSPI_AddressMode QSPI Address Mode
* @{
*/
-#define QSPI_ADDRESS_NONE ((uint32_t)0x00000000) /*!<No address*/
+#define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/
#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/
@@ -345,7 +337,7 @@
/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
* @{
*/
-#define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000) /*!<No alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/
#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/
@@ -356,7 +348,7 @@
/** @defgroup QSPI_DataMode QSPI Data Mode
* @{
*/
-#define QSPI_DATA_NONE ((uint32_t)0X00000000) /*!<No data*/
+#define QSPI_DATA_NONE 0x00000000U /*!<No data*/
#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/
@@ -367,7 +359,7 @@
/** @defgroup QSPI_DdrMode QSPI DDR Mode
* @{
*/
-#define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000) /*!<Double data rate mode disabled*/
+#define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/
#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
/**
* @}
@@ -376,8 +368,8 @@
/** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay
* @{
*/
-#define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000) /*!<Delay the data output using analog delay in DDR mode*/
-#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
+#define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/
+#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by one half of system clock in DDR mode*/
/**
* @}
*/
@@ -385,7 +377,7 @@
/** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
* @{
*/
-#define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000) /*!<Send instruction on every transaction*/
+#define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/
#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
/**
* @}
@@ -394,7 +386,7 @@
/** @defgroup QSPI_MatchMode QSPI Match Mode
* @{
*/
-#define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000) /*!<AND match mode between unmasked bits*/
+#define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/
#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
/**
* @}
@@ -403,7 +395,7 @@
/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
* @{
*/
-#define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000) /*!<AutoPolling stops only with abort or QSPI disabling*/
+#define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/
#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
/**
* @}
@@ -412,7 +404,7 @@
/** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
* @{
*/
-#define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000) /*!<Timeout counter disabled, nCS remains active*/
+#define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/
#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
/**
* @}
@@ -447,7 +439,7 @@
* @brief QSPI Timeout definition
* @{
*/
-#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
+#define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */
/**
* @}
*/
@@ -461,7 +453,7 @@
* @{
*/
/** @brief Reset QSPI handle state.
- * @param __HANDLE__: QSPI handle.
+ * @param __HANDLE__ : QSPI handle.
* @retval None
*/
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
@@ -475,20 +467,20 @@
#endif
/** @brief Enable the QSPI peripheral.
- * @param __HANDLE__: specifies the QSPI Handle.
+ * @param __HANDLE__ : specifies the QSPI Handle.
* @retval None
*/
#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
/** @brief Disable the QSPI peripheral.
- * @param __HANDLE__: specifies the QSPI Handle.
+ * @param __HANDLE__ : specifies the QSPI Handle.
* @retval None
*/
#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
/** @brief Enable the specified QSPI interrupt.
- * @param __HANDLE__: specifies the QSPI Handle.
- * @param __INTERRUPT__: specifies the QSPI interrupt source to enable.
+ * @param __HANDLE__ : specifies the QSPI Handle.
+ * @param __INTERRUPT__ : specifies the QSPI interrupt source to enable.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
@@ -501,8 +493,8 @@
/** @brief Disable the specified QSPI interrupt.
- * @param __HANDLE__: specifies the QSPI Handle.
- * @param __INTERRUPT__: specifies the QSPI interrupt source to disable.
+ * @param __HANDLE__ : specifies the QSPI Handle.
+ * @param __INTERRUPT__ : specifies the QSPI interrupt source to disable.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
@@ -514,8 +506,8 @@
#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
/** @brief Check whether the specified QSPI interrupt source is enabled or not.
- * @param __HANDLE__: specifies the QSPI Handle.
- * @param __INTERRUPT__: specifies the QSPI interrupt source to check.
+ * @param __HANDLE__ : specifies the QSPI Handle.
+ * @param __INTERRUPT__ : specifies the QSPI interrupt source to check.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
@@ -528,8 +520,8 @@
/**
* @brief Check whether the selected QSPI flag is set or not.
- * @param __HANDLE__: specifies the QSPI Handle.
- * @param __FLAG__: specifies the QSPI flag to check.
+ * @param __HANDLE__ : specifies the QSPI Handle.
+ * @param __FLAG__ : specifies the QSPI flag to check.
* This parameter can be one of the following values:
* @arg QSPI_FLAG_BUSY: QSPI Busy flag
* @arg QSPI_FLAG_TO: QSPI Timeout flag
@@ -542,8 +534,8 @@
#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
/** @brief Clears the specified QSPI's flag status.
- * @param __HANDLE__: specifies the QSPI Handle.
- * @param __FLAG__: specifies the QSPI clear register flag that needs to be set
+ * @param __HANDLE__ : specifies the QSPI Handle.
+ * @param __FLAG__ : specifies the QSPI clear register flag that needs to be set
* This parameter can be one of the following values:
* @arg QSPI_FLAG_TO: QSPI Timeout flag
* @arg QSPI_FLAG_SM: QSPI Status match flag
@@ -560,12 +552,22 @@
/** @addtogroup QSPI_Exported_Functions
* @{
*/
+
+/** @addtogroup QSPI_Exported_Functions_Group1
+ * @{
+ */
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
+/**
+ * @}
+ */
+/** @addtogroup QSPI_Exported_Functions_Group2
+ * @{
+ */
/* IO operation functions *****************************************************/
/* QSPI IRQ handler method */
void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
@@ -628,12 +630,15 @@
* @}
*/
+/**
+ * @}
+ */
/* End of exported functions -------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup QSPI_Private_Macros QSPI Private Macros
-* @{
-*/
+ * @{
+ */
#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U))
@@ -655,7 +660,6 @@
#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
((CLKMODE) == QSPI_CLOCK_MODE_3))
-
#define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \
((FLASH_ID) == QSPI_FLASH_ID_2))
@@ -732,11 +736,7 @@
* @}
*/
-/**
- * @}
- */
-
-#endif /* QUADSPI */
+#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */
#ifdef __cplusplus
}
diff --git a/Inc/stm32h7xx_hal_rcc.h b/Inc/stm32h7xx_hal_rcc.h
index fcad6dd..dc360b0 100644
--- a/Inc/stm32h7xx_hal_rcc.h
+++ b/Inc/stm32h7xx_hal_rcc.h
@@ -294,10 +294,10 @@
/** @defgroup RCC_PLL1_VCI_Range RCC PLL1 VCI Range
* @{
*/
-#define RCC_PLL1VCIRANGE_0 RCC_PLLCFGR_PLL1RGE_0
-#define RCC_PLL1VCIRANGE_1 RCC_PLLCFGR_PLL1RGE_1
-#define RCC_PLL1VCIRANGE_2 RCC_PLLCFGR_PLL1RGE_2
-#define RCC_PLL1VCIRANGE_3 RCC_PLLCFGR_PLL1RGE_3
+#define RCC_PLL1VCIRANGE_0 RCC_PLLCFGR_PLL1RGE_0 /*!< Clock range frequency between 1 and 2 MHz */
+#define RCC_PLL1VCIRANGE_1 RCC_PLLCFGR_PLL1RGE_1 /*!< Clock range frequency between 2 and 4 MHz */
+#define RCC_PLL1VCIRANGE_2 RCC_PLLCFGR_PLL1RGE_2 /*!< Clock range frequency between 4 and 8 MHz */
+#define RCC_PLL1VCIRANGE_3 RCC_PLLCFGR_PLL1RGE_3 /*!< Clock range frequency between 8 and 16 MHz */
/**
@@ -1176,6 +1176,7 @@
} while(0)
#endif /* DCMI && PSSI */
+#if defined(CRYP)
#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
@@ -1183,7 +1184,9 @@
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
UNUSED(tmpreg); \
} while(0)
+#endif /* CRYP */
+#if defined(HASH)
#define __HAL_RCC_HASH_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
@@ -1191,6 +1194,7 @@
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
UNUSED(tmpreg); \
} while(0)
+#endif /* HASH */
#define __HAL_RCC_RNG_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -1280,8 +1284,12 @@
#else
#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
#endif /* DCMI && PSSI */
+#if defined(CRYP)
#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
+#endif /* CRYP */
+#if defined(HASH)
#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
+#endif /* HASH */
#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
#if defined(RCC_AHB2ENR_D2SRAM1EN)
@@ -1316,8 +1324,12 @@
#else
#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) != 0U)
#endif /* DCMI && PSSI */
+#if defined(CRYP)
#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) != 0U)
+#endif /* CRYP */
+#if defined(HASH)
#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) != 0U)
+#endif /* HASH */
#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) != 0U)
#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) != 0U)
#if defined(RCC_AHB2ENR_D2SRAM1EN)
@@ -1346,8 +1358,12 @@
#else
#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) == 0U)
#endif /* DCMI && PSSI */
+#if defined(CRYP)
#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) == 0U)
+#endif /* CRYP */
+#if defined(HASH)
#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) == 0U)
+#endif /* HASH */
#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) == 0U)
#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) == 0U)
#if defined(RCC_AHB2ENR_D2SRAM1EN)
@@ -2711,7 +2727,7 @@
tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
UNUSED(tmpreg); \
} while(0)
-
+#if defined(CRYP)
#define __HAL_RCC_C1_CRYP_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
@@ -2719,7 +2735,9 @@
tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
UNUSED(tmpreg); \
} while(0)
+#endif /* CRYP */
+#if defined(HASH)
#define __HAL_RCC_C1_HASH_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\
@@ -2727,6 +2745,7 @@
tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\
UNUSED(tmpreg); \
} while(0)
+#endif /* HASH */
#define __HAL_RCC_C1_RNG_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -2769,8 +2788,12 @@
} while(0)
#define __HAL_RCC_C1_DCMI_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
+#if defined(CRYP)
#define __HAL_RCC_C1_CRYP_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
+#endif /* CRYP */
+#if defined(HASH)
#define __HAL_RCC_C1_HASH_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
+#endif /* HASH */
#define __HAL_RCC_C1_RNG_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
#define __HAL_RCC_C1_SDMMC2_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
#define __HAL_RCC_C1_D2SRAM1_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
@@ -3734,6 +3757,7 @@
UNUSED(tmpreg); \
} while(0)
+#if defined(CRYP)
#define __HAL_RCC_C2_CRYP_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
@@ -3741,7 +3765,9 @@
tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
UNUSED(tmpreg); \
} while(0)
+#endif /* CRYP */
+#if defined(HASH)
#define __HAL_RCC_C2_HASH_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\
@@ -3749,6 +3775,7 @@
tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\
UNUSED(tmpreg); \
} while(0)
+#endif /* HASH */
#define __HAL_RCC_C2_RNG_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -3791,8 +3818,12 @@
} while(0)
#define __HAL_RCC_C2_DCMI_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
+#if defined(CRYP)
#define __HAL_RCC_C2_CRYP_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
+#endif /* CRYP */
+#if defined(HASH)
#define __HAL_RCC_C2_HASH_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
+#endif /* HASH */
#define __HAL_RCC_C2_RNG_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
#define __HAL_RCC_C2_SDMMC2_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
#define __HAL_RCC_C2_D2SRAM1_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
@@ -4528,7 +4559,7 @@
/** @brief Enable or disable the AHB3 peripheral reset.
*/
-#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x7FFFFFFFU)
#define __HAL_RCC_MDMA_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST))
#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST))
#if defined(JPEG)
@@ -4637,8 +4668,12 @@
#else
#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
#endif /* DCMI && PSSI */
+#if defined(CRYP)
#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
+#endif /* CRYP */
+#if defined(HASH)
#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
+#endif /* HASH */
#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
#define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST))
#if defined(RCC_AHB2RSTR_HSEMRST)
@@ -4655,8 +4690,12 @@
#else
#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST))
#endif /* DCMI && PSSI */
+#if defined(CRYP)
#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST))
+#endif /* CRYP */
+#if defined(HASH)
#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST))
+#endif /* HASH */
#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST))
#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST))
#if defined(RCC_AHB2RSTR_HSEMRST)
@@ -5240,8 +5279,12 @@
#else
#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
#endif /* DCMI && PSSI */
+#if defined(CRYP)
#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
@@ -5267,8 +5310,12 @@
#else
#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
#endif /* DCMI && PSSI */
+#if defined(CRYP)
#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
@@ -5301,8 +5348,12 @@
#else
#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != 0U)
#endif /* DCMI && PSSI */
+#if defined(CRYP)
#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != 0U)
+#endif /* CRYP */
+#if defined(HASH)
#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != 0U)
+#endif /* HASH */
#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != 0U)
#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) != 0U)
#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
@@ -5328,8 +5379,12 @@
#else
#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == 0U)
#endif /* DCMI && PSSI */
+#if defined(CRYP)
#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == 0U)
+#endif /* CRYP */
+#if defined(HASH)
#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == 0U)
+#endif /* HASH */
#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == 0U)
#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
#define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) == 0U)
@@ -6010,8 +6065,12 @@
*/
#define __HAL_RCC_C1_DCMI_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#if defined(CRYP)
#define __HAL_RCC_C1_CRYP_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
#define __HAL_RCC_C1_HASH_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
#define __HAL_RCC_C1_RNG_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
#define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
#define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
@@ -6019,8 +6078,12 @@
#define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
#define __HAL_RCC_C1_DCMI_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
+#if defined(CRYP)
#define __HAL_RCC_C1_CRYP_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
#define __HAL_RCC_C1_HASH_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
#define __HAL_RCC_C1_RNG_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
#define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
#define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
@@ -6298,8 +6361,12 @@
*/
#define __HAL_RCC_C2_DCMI_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#if defined(CRYP)
#define __HAL_RCC_C2_CRYP_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
#define __HAL_RCC_C2_HASH_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
#define __HAL_RCC_C2_RNG_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
#define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
#define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
@@ -6307,8 +6374,12 @@
#define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
#define __HAL_RCC_C2_DCMI_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
+#if defined(CRYP)
#define __HAL_RCC_C2_CRYP_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
#define __HAL_RCC_C2_HASH_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
#define __HAL_RCC_C2_RNG_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
#define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
#define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
diff --git a/Inc/stm32h7xx_hal_rcc_ex.h b/Inc/stm32h7xx_hal_rcc_ex.h
index 1b6ee38..9d62e9e 100644
--- a/Inc/stm32h7xx_hal_rcc_ex.h
+++ b/Inc/stm32h7xx_hal_rcc_ex.h
@@ -461,10 +461,10 @@
/** @defgroup RCC_PLL2_VCI_Range RCC PLL2 VCI Range
* @{
*/
-#define RCC_PLL2VCIRANGE_0 RCC_PLLCFGR_PLL2RGE_0
-#define RCC_PLL2VCIRANGE_1 RCC_PLLCFGR_PLL2RGE_1
-#define RCC_PLL2VCIRANGE_2 RCC_PLLCFGR_PLL2RGE_2
-#define RCC_PLL2VCIRANGE_3 RCC_PLLCFGR_PLL2RGE_3
+#define RCC_PLL2VCIRANGE_0 RCC_PLLCFGR_PLL2RGE_0 /*!< Clock range frequency between 1 and 2 MHz */
+#define RCC_PLL2VCIRANGE_1 RCC_PLLCFGR_PLL2RGE_1 /*!< Clock range frequency between 2 and 4 MHz */
+#define RCC_PLL2VCIRANGE_2 RCC_PLLCFGR_PLL2RGE_2 /*!< Clock range frequency between 4 and 8 MHz */
+#define RCC_PLL2VCIRANGE_3 RCC_PLLCFGR_PLL2RGE_3 /*!< Clock range frequency between 8 and 16 MHz */
/**
* @}
@@ -484,10 +484,10 @@
/** @defgroup RCC_PLL3_VCI_Range RCC PLL3 VCI Range
* @{
*/
-#define RCC_PLL3VCIRANGE_0 RCC_PLLCFGR_PLL3RGE_0
-#define RCC_PLL3VCIRANGE_1 RCC_PLLCFGR_PLL3RGE_1
-#define RCC_PLL3VCIRANGE_2 RCC_PLLCFGR_PLL3RGE_2
-#define RCC_PLL3VCIRANGE_3 RCC_PLLCFGR_PLL3RGE_3
+#define RCC_PLL3VCIRANGE_0 RCC_PLLCFGR_PLL3RGE_0 /*!< Clock range frequency between 1 and 2 MHz */
+#define RCC_PLL3VCIRANGE_1 RCC_PLLCFGR_PLL3RGE_1 /*!< Clock range frequency between 2 and 4 MHz */
+#define RCC_PLL3VCIRANGE_2 RCC_PLLCFGR_PLL3RGE_2 /*!< Clock range frequency between 4 and 8 MHz */
+#define RCC_PLL3VCIRANGE_3 RCC_PLLCFGR_PLL3RGE_3 /*!< Clock range frequency between 8 and 16 MHz */
/**
* @}
@@ -1511,6 +1511,14 @@
#endif /*DUAL_CORE*/
+/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
+ * @{
+ */
+#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM18 /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
+/**
+ * @}
+ */
+
/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
* @{
*/
@@ -3403,6 +3411,134 @@
/**
* @}
*/
+
+/**
+ * @brief Enable the RCC LSE CSS Extended Interrupt Line.
+ * @retval None
+ */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+ * @brief Disable the RCC LSE CSS Extended Interrupt Line.
+ * @retval None
+ */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+ * @brief Enable the RCC LSE CSS Event Line.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+ * @brief Disable the RCC LSE CSS Event Line.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
+
+#if defined(DUAL_CORE)
+/**
+ * @brief Enable the RCC LSE CSS Extended Interrupt Line for CM4.
+ * @retval None
+ */
+#define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+ * @brief Disable the RCC LSE CSS Extended Interrupt Line for CM4.
+ * @retval None
+ */
+#define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+ * @brief Enable the RCC LSE CSS Event Line for CM4.
+ * @retval None.
+ */
+#define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+ * @brief Disable the RCC LSE CSS Event Line for CM4.
+ * @retval None.
+ */
+#define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS)
+#endif /* DUAL_CORE */
+
+/**
+ * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
+
+
+/**
+ * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
+
+
+/**
+ * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+ * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+ * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \
+ do { \
+ __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \
+ do { \
+ __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
+ * @retval EXTI RCC LSE CSS Line Status.
+ */
+#define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
+
+/**
+ * @brief Clear the RCC LSE CSS EXTI flag.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
+
+#if defined(DUAL_CORE)
+/**
+ * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not for CM4.
+ * @retval EXTI RCC LSE CSS Line Status.
+ */
+#define __HAL_RCC_C2_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
+
+/**
+ * @brief Clear the RCC LSE CSS EXTI flag or not for CM4.
+ * @retval None.
+ */
+#define __HAL_RCC_C2_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS)
+#endif /* DUAL_CORE */
+/**
+ * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
+
/**
* @brief Enable the specified CRS interrupts.
* @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
@@ -3583,6 +3719,9 @@
void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk);
void HAL_RCCEx_EnableLSECSS(void);
void HAL_RCCEx_DisableLSECSS(void);
+void HAL_RCCEx_EnableLSECSS_IT(void);
+void HAL_RCCEx_LSECSS_IRQHandler(void);
+void HAL_RCCEx_LSECSS_Callback(void);
#if defined(DUAL_CORE)
void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx);
#endif /*DUAL_CORE*/
diff --git a/Inc/stm32h7xx_hal_usart.h b/Inc/stm32h7xx_hal_usart.h
index c794031..15b610e 100644
--- a/Inc/stm32h7xx_hal_usart.h
+++ b/Inc/stm32h7xx_hal_usart.h
@@ -228,6 +228,7 @@
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
#define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+#define HAL_USART_ERROR_RTO ((uint32_t)0x00000080U) /*!< Receiver Timeout error */
/**
* @}
*/
@@ -352,6 +353,7 @@
#define USART_FLAG_UDR USART_ISR_UDR /*!< SPI slave underrun error flag */
#define USART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< USART transmit data register empty */
#define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< USART TXFIFO not full */
+#define USART_FLAG_RTOF USART_ISR_RTOF /*!< USART receiver timeout flag */
#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */
#define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< USART read data register not empty */
#define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< USART RXFIFO not empty */
@@ -406,6 +408,7 @@
#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
#define USART_CLEAR_UDRF USART_ICR_UDRCF /*!< SPI slave underrun error Clear Flag */
#define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO Empty Clear Flag */
+#define USART_CLEAR_RTOF USART_ICR_RTOCF /*!< USART receiver timeout clear flag */
/**
* @}
*/
@@ -462,6 +465,7 @@
* @arg @ref USART_FLAG_TC Transmission Complete flag
* @arg @ref USART_FLAG_RXNE Receive data register not empty flag
* @arg @ref USART_FLAG_RXFNE RXFIFO not empty flag
+ * @arg @ref USART_FLAG_RTOF Receiver Timeout flag
* @arg @ref USART_FLAG_IDLE Idle Line detection flag
* @arg @ref USART_FLAG_ORE OverRun Error flag
* @arg @ref USART_FLAG_NE Noise Error flag
@@ -482,6 +486,7 @@
* @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
* @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag
* @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
+ * @arg @ref USART_CLEAR_RTOF Receiver Timeout clear flag
* @arg @ref USART_CLEAR_UDRF SPI slave underrun error Clear Flag
* @retval None
*/
@@ -632,6 +637,7 @@
* @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
* @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag
* @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
+ * @arg @ref USART_CLEAR_RTOF Receiver timeout clear flag
* @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag
* @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
* @retval None
diff --git a/Inc/stm32h7xx_hal_usart_ex.h b/Inc/stm32h7xx_hal_usart_ex.h
index 8b6fe98..b698726 100644
--- a/Inc/stm32h7xx_hal_usart_ex.h
+++ b/Inc/stm32h7xx_hal_usart_ex.h
@@ -46,7 +46,7 @@
* @{
*/
#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */
-#define USART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long USART frame */
+#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */
/**
* @}
@@ -169,7 +169,6 @@
} \
} while(0U)
-
/**
* @brief Ensure that USART frame length is valid.
* @param __LENGTH__ USART frame length.
diff --git a/Inc/stm32h7xx_ll_dma.h b/Inc/stm32h7xx_ll_dma.h
index 639565b..095202d 100644
--- a/Inc/stm32h7xx_ll_dma.h
+++ b/Inc/stm32h7xx_ll_dma.h
@@ -970,6 +970,50 @@
}
/**
+ * @brief Enable DMA stream bufferable transfer.
+ * @rmtoll CR TRBUFF LL_DMA_EnableBufferableTransfer
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+ SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF);
+}
+
+/**
+ * @brief Disable DMA stream bufferable transfer.
+ * @rmtoll CR TRBUFF LL_DMA_DisableBufferableTransfer
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+ CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF);
+}
+
+/**
* @brief Set Number of data to transfer.
* @rmtoll NDTR NDT LL_DMA_SetDataLength
* @note This action has no effect if
diff --git a/Inc/stm32h7xx_ll_fmc.h b/Inc/stm32h7xx_ll_fmc.h
index 915a677..124f5cd 100644
--- a/Inc/stm32h7xx_ll_fmc.h
+++ b/Inc/stm32h7xx_ll_fmc.h
@@ -457,10 +457,10 @@
/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
* @{
*/
-#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U)
-#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U)
-#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U)
-#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U)
+#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
+#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
+#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
+#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
/**
* @}
*/
@@ -468,8 +468,8 @@
/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
* @{
*/
-#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U)
-#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U)
+#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
+#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
/**
* @}
*/
@@ -477,9 +477,9 @@
/** @defgroup FMC_Memory_Type FMC Memory Type
* @{
*/
-#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U)
-#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U)
-#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U)
+#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
+#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
+#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
/**
* @}
*/
@@ -487,9 +487,9 @@
/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
* @{
*/
-#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
-#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
-#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
/**
* @}
*/
@@ -497,8 +497,8 @@
/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
* @{
*/
-#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U)
-#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U)
+#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
+#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
/**
* @}
*/
@@ -506,8 +506,8 @@
/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
* @{
*/
-#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U)
-#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U)
+#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
+#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
/**
* @}
*/
@@ -515,8 +515,8 @@
/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
* @{
*/
-#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U)
-#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U)
+#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
+#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
/**
* @}
*/
@@ -524,8 +524,8 @@
/** @defgroup FMC_Wait_Timing FMC Wait Timing
* @{
*/
-#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U)
-#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U)
+#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
+#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
/**
* @}
*/
@@ -533,8 +533,8 @@
/** @defgroup FMC_Write_Operation FMC Write Operation
* @{
*/
-#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U)
-#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U)
+#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
+#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
/**
* @}
*/
@@ -542,8 +542,8 @@
/** @defgroup FMC_Wait_Signal FMC Wait Signal
* @{
*/
-#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U)
-#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U)
+#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
+#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
/**
* @}
*/
@@ -551,8 +551,8 @@
/** @defgroup FMC_Extended_Mode FMC Extended Mode
* @{
*/
-#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U)
-#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U)
+#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
+#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
/**
* @}
*/
@@ -560,8 +560,8 @@
/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
* @{
*/
-#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U)
-#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U)
+#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
+#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
/**
* @}
*/
@@ -569,7 +569,7 @@
/** @defgroup FMC_Page_Size FMC Page Size
* @{
*/
-#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U)
+#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000)
#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCRx_CPSIZE_0)
#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCRx_CPSIZE_1)
#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCRx_CPSIZE_0 | FMC_BCRx_CPSIZE_1))
@@ -581,8 +581,8 @@
/** @defgroup FMC_Write_Burst FMC Write Burst
* @{
*/
-#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U)
-#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U)
+#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
+#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
/**
* @}
*/
@@ -590,8 +590,8 @@
/** @defgroup FMC_Continous_Clock FMC Continuous Clock
* @{
*/
-#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U)
-#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U)
+#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
+#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
/**
* @}
*/
@@ -600,7 +600,7 @@
* @{
*/
#define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
-#define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U)
+#define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000)
/**
* @}
*/
@@ -608,10 +608,10 @@
/** @defgroup FMC_Access_Mode FMC Access Mode
* @{
*/
-#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U)
-#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000U)
-#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000U)
-#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000U)
+#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
+#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
+#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
+#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
/**
* @}
*/
@@ -627,7 +627,7 @@
/** @defgroup FMC_NAND_Bank FMC NAND Bank
* @{
*/
-#define FMC_NAND_BANK3 ((uint32_t)0x00000100U)
+#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
/**
* @}
*/
@@ -635,8 +635,8 @@
/** @defgroup FMC_Wait_feature FMC Wait feature
* @{
*/
-#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U)
-#define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U)
+#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
+#define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
/**
* @}
*/
@@ -644,7 +644,7 @@
/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
* @{
*/
-#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U)
+#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
/**
* @}
*/
@@ -652,8 +652,8 @@
/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
* @{
*/
-#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
-#define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
+#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
+#define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
/**
* @}
*/
@@ -661,8 +661,8 @@
/** @defgroup FMC_ECC FMC ECC
* @{
*/
-#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U)
-#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U)
+#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
+#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
/**
* @}
*/
@@ -670,12 +670,12 @@
/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
* @{
*/
-#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U)
-#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U)
-#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U)
-#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U)
-#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U)
-#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U)
+#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
+#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
+#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
+#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
+#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
+#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
/**
* @}
*/
@@ -690,8 +690,8 @@
/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
* @{
*/
-#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000U)
-#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001U)
+#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
+#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
/**
* @}
*/
@@ -699,10 +699,10 @@
/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
* @{
*/
-#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000U)
-#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001U)
-#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002U)
-#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003U)
+#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
+#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
+#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
+#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
/**
* @}
*/
@@ -710,9 +710,9 @@
/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
* @{
*/
-#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000U)
-#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004U)
-#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008U)
+#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
+#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
+#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
/**
* @}
*/
@@ -720,9 +720,9 @@
/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
* @{
*/
-#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
-#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
-#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
+#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
+#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
+#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
/**
* @}
*/
@@ -730,8 +730,8 @@
/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
* @{
*/
-#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000U)
-#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040U)
+#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
+#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
/**
* @}
*/
@@ -739,9 +739,9 @@
/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
* @{
*/
-#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080U)
-#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100U)
-#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180U)
+#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
+#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
+#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
/**
* @}
*/
@@ -749,8 +749,8 @@
/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
* @{
*/
-#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000U)
-#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200U)
+#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
+#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
/**
* @}
*/
@@ -758,9 +758,9 @@
/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
* @{
*/
-#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000U)
-#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800U)
-#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00U)
+#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
+#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
+#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
/**
* @}
*/
@@ -768,8 +768,8 @@
/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
* @{
*/
-#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000U)
-#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000U)
+#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
+#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
/**
* @}
*/
@@ -777,9 +777,9 @@
/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
* @{
*/
-#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000U)
-#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000U)
-#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000U)
+#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
+#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
+#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
/**
* @}
*/
@@ -787,13 +787,13 @@
/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
* @{
*/
-#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000U)
-#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001U)
-#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002U)
-#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003U)
-#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004U)
-#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005U)
-#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006U)
+#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
+#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
+#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
+#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
+#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
+#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
+#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
/**
* @}
*/
@@ -803,7 +803,7 @@
*/
#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
-#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018U)
+#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
/**
* @}
*/
@@ -811,7 +811,7 @@
/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
* @{
*/
-#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000U)
+#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
/**
@@ -826,10 +826,10 @@
/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition
* @{
*/
-#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008U)
-#define FMC_IT_LEVEL ((uint32_t)0x00000010U)
-#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020U)
-#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000U)
+#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
+#define FMC_IT_LEVEL ((uint32_t)0x00000010)
+#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
+#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
/**
* @}
*/
@@ -837,10 +837,10 @@
/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition
* @{
*/
-#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U)
-#define FMC_FLAG_LEVEL ((uint32_t)0x00000002U)
-#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U)
-#define FMC_FLAG_FEMPT ((uint32_t)0x00000040U)
+#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
+#define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
+#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
+#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
diff --git a/Inc/stm32h7xx_ll_hrtim.h b/Inc/stm32h7xx_ll_hrtim.h
index c24b53c..a16dd28 100644
--- a/Inc/stm32h7xx_ll_hrtim.h
+++ b/Inc/stm32h7xx_ll_hrtim.h
@@ -608,11 +608,6 @@
* @{
* @brief Constants defining timer high-resolution clock prescaler ratio.
*/
-#define LL_HRTIM_PRESCALERRATIO_MUL32 0x00000000U /*!< fHRCK: fHRTIM x 32 = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
-#define LL_HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001U) /*!< fHRCK: fHRTIM x 16 = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
-#define LL_HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002U) /*!< fHRCK: fHRTIM x 8 = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
-#define LL_HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003U) /*!< fHRCK: fHRTIM x 4 = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
-#define LL_HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004U) /*!< fHRCK: fHRTIM x 2 = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
#define LL_HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
#define LL_HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006U) /*!< fHRCK: fHRTIM / 2 = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
#define LL_HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007U) /*!< fHRCK: fHRTIM / 4 = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
@@ -2568,11 +2563,6 @@
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @param Prescaler This parameter can be one of the following values:
- * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
- * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
- * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
- * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
- * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
* @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
* @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
* @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
@@ -2598,11 +2588,6 @@
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @retval Prescaler Returned value can be one of the following values:
- * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
- * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
- * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
- * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
- * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
* @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
* @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
* @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
diff --git a/Inc/stm32h7xx_ll_lptim.h b/Inc/stm32h7xx_ll_lptim.h
index d5a4fc9..2529003 100644
--- a/Inc/stm32h7xx_ll_lptim.h
+++ b/Inc/stm32h7xx_ll_lptim.h
@@ -375,7 +375,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
}
/**
@@ -428,7 +428,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
}
/**
@@ -772,7 +772,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
}
/**
@@ -1063,7 +1063,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
}
/**
@@ -1093,7 +1093,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL));
}
/**
@@ -1115,7 +1115,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
}
/**
@@ -1137,7 +1137,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
}
/**
@@ -1159,7 +1159,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL));
}
/**
@@ -1181,7 +1181,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
}
/**
@@ -1203,7 +1203,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
}
/**
@@ -1225,7 +1225,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
}
/**
@@ -1266,7 +1266,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL));
}
/**
@@ -1299,7 +1299,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL));
}
/**
@@ -1332,7 +1332,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL));
}
/**
@@ -1365,7 +1365,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL));
}
/**
@@ -1394,11 +1394,11 @@
* @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
* @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
* @param LPTIMx Low-Power Timer instance
- * @retval State of bit (1 or 0).
+ * @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL));
}
/**
@@ -1427,11 +1427,11 @@
* @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
* @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
* @param LPTIMx Low-Power Timer instance
- * @retval State of bit (1 or 0).
+ * @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL));
}
/**
@@ -1460,11 +1460,11 @@
* @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
* @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
* @param LPTIMx Low-Power Timer instance
- * @retval State of bit (1 or 0).
+ * @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
{
- return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE)? 1UL : 0UL);
+ return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL);
}
/**
diff --git a/Inc/stm32h7xx_ll_rcc.h b/Inc/stm32h7xx_ll_rcc.h
index 65c28f7..3ec127c 100644
--- a/Inc/stm32h7xx_ll_rcc.h
+++ b/Inc/stm32h7xx_ll_rcc.h
@@ -1419,9 +1419,9 @@
* @retval SYSCLK clock frequency (in Hz)
*/
#if defined(RCC_D1CFGR_D1CPRE)
-#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos])
+#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU))
#else
-#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos])
+#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU))
#endif /* RCC_D1CFGR_D1CPRE */
/**
@@ -1440,9 +1440,9 @@
* @retval HCLK clock frequency (in Hz)
*/
#if defined(RCC_D1CFGR_HPRE)
-#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> LL_RCC_PrescTable[((__HPRESCALER__) & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos])
+#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU))
#else
-#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> LL_RCC_PrescTable[((__HPRESCALER__) & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos])
+#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU))
#endif /* RCC_D1CFGR_HPRE */
/**
@@ -1457,9 +1457,9 @@
* @retval PCLK1 clock frequency (in Hz)
*/
#if defined(RCC_D2CFGR_D2PPRE1)
-#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos])
+#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU))
#else
-#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos])
+#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU))
#endif /* RCC_D2CFGR_D2PPRE1 */
/**
@@ -1474,9 +1474,9 @@
* @retval PCLK2 clock frequency (in Hz)
*/
#if defined(RCC_D2CFGR_D2PPRE2)
-#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos])
+#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU))
#else
-#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos])
+#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU))
#endif /* RCC_D2CFGR_D2PPRE2 */
/**
@@ -1491,9 +1491,9 @@
* @retval PCLK1 clock frequency (in Hz)
*/
#if defined(RCC_D1CFGR_D1PPRE)
-#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_D1CFGR_D1PPRE) >> RCC_D1CFGR_D1PPRE_Pos])
+#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_D1CFGR_D1PPRE) >> RCC_D1CFGR_D1PPRE_Pos]) & 0x1FU))
#else
-#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos])
+#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos]) & 0x1FU))
#endif /* RCC_D1CFGR_D1PPRE */
/**
@@ -1508,9 +1508,9 @@
* @retval PCLK1 clock frequency (in Hz)
*/
#if defined(RCC_D3CFGR_D3PPRE)
-#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos])
+#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos]) & 0x1FU))
#else
-#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos])
+#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos]) & 0x1FU))
#endif /* RCC_D3CFGR_D3PPRE */
/**
diff --git a/Inc/stm32h7xx_ll_tim.h b/Inc/stm32h7xx_ll_tim.h
index 0953b66..728c423 100644
--- a/Inc/stm32h7xx_ll_tim.h
+++ b/Inc/stm32h7xx_ll_tim.h
@@ -220,13 +220,14 @@
This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
- uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
+ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
reaches zero, an update event is generated and counting restarts
from the RCR value (N).
This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
- This parameter must be a number between 0x00 and 0xFF.
+ GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+ Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
} LL_TIM_InitTypeDef;
@@ -1734,7 +1735,7 @@
* whether or not a timer instance supports a repetition counter.
* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
* @param TIMx Timer instance
- * @param RepetitionCounter between Min_Data=0 and Max_Data=255
+ * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
diff --git a/Inc/stm32h7xx_ll_usart.h b/Inc/stm32h7xx_ll_usart.h
index 8e2e154..e090a1e 100644
--- a/Inc/stm32h7xx_ll_usart.h
+++ b/Inc/stm32h7xx_ll_usart.h
@@ -2651,7 +2651,8 @@
{
/* In Asynchronous mode, the following bits must be kept cleared:
- LINEN, CLKEN bits in the USART_CR2 register,
- - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
+ - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
}
@@ -2687,7 +2688,8 @@
{
/* In Synchronous mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register,
- - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
+ - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
/* set the UART/USART in Synchronous mode */
@@ -2727,7 +2729,8 @@
{
/* In LIN mode, the following bits must be kept cleared:
- STOP and CLKEN bits in the USART_CR2 register,
- - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
+ - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
/* Set the UART/USART in LIN mode */
@@ -2765,7 +2768,8 @@
{
/* In Half Duplex mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN and IREN bits in the USART_CR3 register.*/
+ - SCEN and IREN bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
/* set the UART/USART in Half Duplex mode */
@@ -2805,7 +2809,8 @@
{
/* In Smartcard mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register,
- - IREN and HDSEL bits in the USART_CR3 register.*/
+ - IREN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
/* Configure Stop bits to 1.5 bits */
@@ -2848,7 +2853,8 @@
{
/* In IRDA mode, the following bits must be kept cleared:
- LINEN, STOP and CLKEN bits in the USART_CR2 register,
- - SCEN and HDSEL bits in the USART_CR3 register.*/
+ - SCEN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
/* set the UART/USART in IRDA mode */
@@ -2886,7 +2892,8 @@
{
/* In Multi Processor mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
+ - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
}
diff --git a/Inc/stm32h7xx_ll_utils.h b/Inc/stm32h7xx_ll_utils.h
index 6391264..3dc60e7 100644
--- a/Inc/stm32h7xx_ll_utils.h
+++ b/Inc/stm32h7xx_ll_utils.h
@@ -121,13 +121,13 @@
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL1_SetFRACN(). */
- uint32_t VCO_Input; /*!< Fractional part of the multiplication factor for PLL VCO.
+ uint32_t VCO_Input; /*!< PLL clock Input range.
This parameter can be a value of @ref RCC_LL_EC_PLLINPUTRANGE
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL1_SetVCOInputRange(). */
- uint32_t VCO_Output; /*!< Fractional part of the multiplication factor for PLL VCO.
+ uint32_t VCO_Output; /*!< PLL clock Output range.
This parameter can be a value of @ref RCC_LL_EC_PLLVCORANGE
This feature can be modified afterwards using unitary function
@@ -213,11 +213,11 @@
#define LL_UTILS_PACKAGETYPE_LQFP144 0x00000005UL /*!< LQFP144 package type */
#define LL_UTILS_PACKAGETYPE_LQFP144_SMPS 0x00000006UL /*!< LQFP144 with SMPS package type */
#define LL_UTILS_PACKAGETYPE_UFBGA169 0x00000007UL /*!< UFBGA169 package type */
-#define LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176 0x00000010UL /*!< UFBGA176 or LQFP176 package type */
-#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS 0x00000011UL /*!< LQFP176 with SMPS package type */
-#define LL_UTILS_PACKAGETYPE_UFBGA176_SMPS 0x00000012UL /*!< UFBGA176 with SMPS package type */
-#define LL_UTILS_PACKAGETYPE_TFBGA216 0x00000014UL /*!< TFBGA216 package type */
-#define LL_UTILS_PACKAGETYPE_TFBGA225 0x00000016UL /*!< TFBGA225 package type */
+#define LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176 0x00000008UL /*!< UFBGA176 or LQFP176 package type */
+#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS 0x00000009UL /*!< LQFP176 with SMPS package type */
+#define LL_UTILS_PACKAGETYPE_UFBGA176_SMPS 0x0000000AUL /*!< UFBGA176 with SMPS package type */
+#define LL_UTILS_PACKAGETYPE_TFBGA216 0x0000000CUL /*!< TFBGA216 package type */
+#define LL_UTILS_PACKAGETYPE_TFBGA225 0x0000000EUL /*!< TFBGA225 package type */
#endif /* SYSCFG_PKGR_PKG */
/**
* @}
@@ -355,6 +355,7 @@
uint32_t HSEBypass,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
/**
* @}
diff --git a/README.md b/README.md
index 07ef571..1003ec6 100644
--- a/README.md
+++ b/README.md
@@ -23,9 +23,13 @@
Copyright (c) 2017 STMicroelectronics.
-This software component is licensed by STMicroelectronics under BSD 3-Clause license. You may not use this file except in compliance with the License.
+This software component is licensed by STMicroelectronics under BSD-3-Clause license. You may not use this file except in compliance with the License.
You may obtain a copy of the License [here](https://opensource.org/licenses/BSD-3-Clause).
+## Release note
+
+Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/stm32h7xx_hal_driver/blob/master/Release_Notes.html).
+
## Compatibility information
In this table, you can find the successive versions of this HAL-LL Driver component, in line with the corresponding versions of the full MCU package:
@@ -34,8 +38,9 @@
HAL Driver H7 | CMSIS Device H7 | CMSIS Core | Was delivered in the full MCU package
------------- | --------------- | ---------- | -------------------------------------
-Tag v1.6.0 | Tag v1.6.0 | Tag v5.4.0 | Tag v1.5.0 (and following, if any, till next new tag)
-Tag v1.7.0 | Tag v1.7.0 | Tag v5.4.0 | Tag v1.6.0 (and following, if any, till next new tag)
+Tag v1.6.0 | Tag v1.6.0 | Tag v5.4.0 | Tag v1.5.0 (and following, if any, till next HAL tag)
+Tag v1.7.0 | Tag v1.7.0 | Tag v5.4.0 | Tag v1.6.0 (and following, if any, till next HAL tag)
+Tag v1.8.0 | Tag v1.8.0 | Tag v5.4.0 | Tag v1.7.0 (and following, if any, till next HAL tag)
The full **STM32CubeH7** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeH7).
diff --git a/Release_Notes.html b/Release_Notes.html
index bc59796..37472cb 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -38,10 +38,249 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history"><strong>Update History</strong></h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section8" checked aria-hidden="true"> <label for="collapse-section8" aria-hidden="true"><strong>V1.7.0 / 06-December-2019</strong></label>
+<input type="checkbox" id="collapse-section9" checked aria-hidden="true"> <label for="collapse-section9" aria-hidden="true"><strong>V1.8.0 / 14-February-2020</strong></label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
+<li>General updates to fix known defects and implementation enhancements</li>
+<li><strong>HAL</strong>: generic
+<ul>
+<li>stm32h7xx_hal.c:
+<ul>
+<li>Update HAL_Init implementation to reflect the current core clock in SystemCoreClock global variable (Corex-M7 or Corext-M4 clock depending of the current context in case of Dual Core)</li>
+<li>Update HAL_InitTick implementation to use SystemCoreClock global variable as it reflect now the current core clock (simplifying the implementation)</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL DAC</strong>:
+<ul>
+<li>stm32h7xx_hal_dac.c:
+<ul>
+<li>Update HAL_DAC_ConfigChannel function implemenation to fix the “DAC_ConnectOnChipPeripheral” check and settings</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL GPIO</strong>:
+<ul>
+<li>stm32h7xx_hal_gpio.h
+<ul>
+<li>Update IS_GPIO_PIN macro implementation with an explicit cast to avoid compilation warning on EWARM 8.30</li>
+</ul></li>
+<li>stm32h7xx_hal_gpio_ex.h
+<ul>
+<li>Remove useless GPIO_AF13_TIM8 define</li>
+<li>Update GPIOK_PIN_AVAILABLE define to consider missed GPIO Pin 2</li>
+</ul></li>
+<li>stm32h7xx_hal_gpio.c:
+<ul>
+<li>Update HAL_GPIO_Init and HAL_GPIO_DeInit functions implementation to avoid a glitch during GPIO initialization/de-initialization</li>
+</ul></li>
+<li>stm32h7xx_ll_gpio.c:
+<ul>
+<li>Update LL_GPIO_Init function implementation to avoid a glitch during GPIO initialization</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL HRTIM</strong>:
+<ul>
+<li>stm32h7xx_hal_hrtim.h
+<ul>
+<li>Remove HRTIM_PRESCALERRATIO_MUL2 to HRTIM_PRESCALERRATIO_MUL32 definition that are not supported on STM32H7 devices</li>
+</ul></li>
+<li>stm32h7xx_ll_hrtim.h
+<ul>
+<li>Remove LL_HRTIM_PRESCALERRATIO_MUL2 to LL_HRTIM_PRESCALERRATIO_MUL32 definition that are not supported on STM32H7 devices</li>
+</ul></li>
+<li>Note: Only Prescaler ratios 1/2/4 are supported for HRTIM on STM32H7 devices</li>
+</ul></li>
+<li><strong>HAL I2C</strong>:
+<ul>
+<li>stm32h7xx_hal_i2c.h
+<ul>
+<li>Updates to fix incorrectly enable interrupts in I2C_Enable_IRQ routine when InterruptRequest = I2C_XFER_CPLT_IT</li>
+<li>Updates to avoid HardFault in I2C_DMAAbort when DMA is not used for Tx or/and Rx</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL JPEG</strong>:
+<ul>
+<li>stm32h7xx_hal_jpeg.h: Minor update for STM32 coding rules compliance (one line per variable declaration, local variables naming …)</li>
+</ul></li>
+<li><strong>HAL/LL LPTIM</strong>:
+<ul>
+<li>stm32h7xx_hal_lptim.c:
+<ul>
+<li>Update HAL_LPTIM_Init implementation to configure digital filter for external clock when LPTIM is clocked by an internal clock source</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL MMC</strong>:
+<ul>
+<li>stm32h7xx_hal_mmc.c:
+<ul>
+<li>Update implementation to avoid setting the block size during every MMC card transaction (block size is set once in HAL_MMC_InitCard )</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL NAND</strong>:
+<ul>
+<li>stm32h7xx_hal_nand.h: Minor update to use UL/U suffix respectively instead of uint32_t/uint8_t cast</li>
+</ul></li>
+<li><strong>HAL NOR</strong>:
+<ul>
+<li>stm32h7xx_hal_nor.h: Minor update to remove useless U suffix following uint32_t/uint16_t/uint8_t cast</li>
+</ul></li>
+<li><strong>HAL OSPI</strong>: <strong>Add support of multiplexed mode feature</strong>
+<ul>
+<li>stm32h7xx_hal_ospi.h:
+<ul>
+<li>Update “OSPIM_CfgTypeDef” structure definition to add “Req2AckTime” allowing to set the “minimum switching duration” clock cycles when OSPI signals are multiplexed in the OSPI IO Manager</li>
+<li>Add IS_OSPIM_REQ2ACKTIME macro useful when the HAL assert is enabled and allowing to check the “Req2AckTime” value validity<br />
+</li>
+</ul></li>
+<li>stm32h7xx_hal_ospi.c:
+<ul>
+<li>Update “HAL_OSPIM_Config” implementation to support OSPI signals Mux using the OSPI IO Manager</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL PSSI</strong>:
+<ul>
+<li>stm32h7xx_hal_pssi.c:
+<ul>
+<li>Update HAL_PSSI_Transmit/HAL_PSSI_Receive implementation to fix warning on GCC compiler</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL QSPI</strong>:
+<ul>
+<li>stm32h7xx_hal_qspi.h:
+<ul>
+<li>Rename HAL_QPSI_TIMEOUT_DEFAULT_VALUE define to HAL_QSPI_TIMEOUT_DEFAULT_VALUE (typo fix). backward compatibility ensured through stm32_hal_legacy.h header file<br />
+</li>
+</ul></li>
+<li>stm32h7xx_hal_qspi.c:
+<ul>
+<li>Update HAL_QSPI_Init/HAL_QSPI_DeInit implementation to remove useless lock/unlock</li>
+<li>Update HAL_QSPI_IRQHandler implementation to optimize flags check</li>
+<li>Update HAL_QSPI_Transmit_DMA to:
+<ul>
+<li>Fix performance issue at high frequency by fixing wrong activation of TC interrupt</li>
+<li>Enabling QUADSPI_CR_DMAEN bit field: used only by the HAL_QSPI_IRQHandler to check if current Transmit is using DMA when IT occurs</li>
+</ul></li>
+<li>Update HAL_QSPI_Receive_DMA to enable QUADSPI_CR_DMAEN bit field: used only by the HAL_QSPI_IRQHandler to check if current Receive is using DMA when IT occurs</li>
+<li>Update HAL_QSPI_Abort to reset functional mode configuration to indirect write mode by default<br />
+</li>
+<li>Update HAL_QSPI_Abort_IT to call Abort Complete callback</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL RCC</strong>:
+<ul>
+<li>stm32h7xx_hal_rcc.h:
+<ul>
+<li>Delimit CRYP and HASH Clock enable/disable/reset/sleep macros with conditional define on respectively CRYP/HASH availability (through CMSIS device header files)</li>
+<li>Update __HAL_RCC_AHB3_FORCE_RESET macro implementation to avoid altering reserved bit 31.</li>
+</ul></li>
+<li>stm32h7xx_hal_rcc_ex.h:
+<ul>
+<li>Add definition of RCC_EXTI_LINE_LSECSS (EXTI IMR1 EXTI line 18)</li>
+<li>Add macros __HAL_RCC_LSECSS_EXTI_ENABLE_IT, __HAL_RCC_LSECSS_EXTI_DISABLE_IT, __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT and __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT</li>
+<li>Add macros __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT, __HAL_RCC_C2_LSECSS_EXTI_DISABLE_IT, __HAL_RCC_C2_LSECSS_EXTI_ENABLE_EVENT, __HAL_RCC_C2_LSECSS_EXTI_DISABLE_EVENT: for Dual Core lines allowing to control LSECSS EXTI Line for Coretx-M4.</li>
+<li>Add macros __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE, __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE, __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE, __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE, __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE, __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE, __HAL_RCC_LSECSS_EXTI_GET_FLAG and __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG.</li>
+<li>Add macros __HAL_RCC_C2_LSECSS_EXTI_GET_FLAG and __HAL_RCC_C2_LSECSS_EXTI_CLEAR_FLAG for Dual Core lines allowing to get/clear LSECSS EXTI line on Coretx-M4.</li>
+<li>Add macro __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT</li>
+<li>Add prototypes for new APIs HAL_RCCEx_EnableLSECSS_IT, HAL_RCCEx_LSECSS_IRQHandler and HAL_RCCEx_LSECSS_Callback.</li>
+</ul></li>
+<li>stm32h7xx_ll_rcc.h:
+<ul>
+<li>Update LL_RCC_CALC_SYSCLK_FREQ, LL_RCC_CALC_HCLK_FREQ, LL_RCC_CALC_PCLK1_FREQ, LL_RCC_CALC_PCLK2_FREQ, LL_RCC_CALC_PCLK3_FREQ and LL_RCC_CALC_PCLK4_FREQ macros implementation to avoid overflow (MISRA-C 2012 compliant)<br />
+</li>
+</ul></li>
+<li>stm32h7xx_hal_rcc.c:
+<ul>
+<li>Update HAL_RCC_DeInit, HAL_RCC_ClockConfig, HAL_RCC_GetHCLKFreq and HAL_RCC_GetPCLK1Freq to reflect the current core clock in SystemCoreClock global variable (Corex-M7 or Corext-M4 clock depending of the current context in case of Dual Core)</li>
+</ul></li>
+<li>stm32h7xx_hal_rcc_ex.c:
+<ul>
+<li>Update HAL_RCCEx_GetD1SysClockFreq to reflect the current core clock in SystemCoreClock global variable (Corex-M7 or Corext-M4 clock depending of the current context in case of Dual Core).</li>
+<li>Add HAL_RCCEx_EnableLSECSS_IT, HAL_RCCEx_LSECSS_IRQHandler and HAL_RCCEx_LSECSS_Callback APIs: allowing to handle LSECSS interrupt.</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL SD</strong>:
+<ul>
+<li>stm32h7xx_hal_sd.c:
+<ul>
+<li>Update HAL_SD_InitCard implementation to fix compilation issue when USE_SD_TRANSCEIVER is disabled and USE_SD_DIRPOL enabled</li>
+<li>Update implementation to avoid setting the block size during every SD card transaction (block size is set once in HAL_SD_InitCard, HAL_SD_GetCardStatus, HAL_SD_ConfigWideBusOperation)</li>
+</ul></li>
+<li>stm32h7xx_hal_sd_ex.c:
+<ul>
+<li>Update HAL_SDEx_ReadBlocksDMAMultiBuffer and HAL_SDEx_WriteBlocksDMAMultiBuffer to avoid setting the block size during every SD card transaction</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL TIM</strong>:
+<ul>
+<li>stm32h7xx_hal_tim.c: Minor fixes with the assert parameters checks</li>
+</ul></li>
+<li><strong>HAL/LL USART</strong>: Add RTO (Receive Time Out) flag support
+<ul>
+<li>stm32h7xx_hal_usart.h
+<ul>
+<li>Add HAL_USART_ERROR_RTO define to USART Error Definition section</li>
+<li>Add USART_FLAG_RTOF define to USART Flags section</li>
+<li>Add USART_CLEAR_RTOF define to USART Interruption Clear Flags section</li>
+</ul></li>
+<li>stm32h7xx_hal_usart.c: Update HAL_USART_IRQHandler to handle USART_ISR_RTOF flag and IT</li>
+<li>stm32h7xx_hal_usart_ex.c: Update HAL_USARTEx_DisableSlaveMode to fix typo in disabling salve mode</li>
+</ul></li>
+<li><strong>HAL/LL DMA</strong>: Add support for DMA_SxCR_TRBUFF
+<ul>
+<li>stm32h7xx_ll_dma.h
+<ul>
+<li>Add API “LL_DMA_EnableBufferableTransfer” allowing to enable bufferable transfer<br />
+</li>
+<li>Add API “LL_DMA_DisableBufferableTransfer” allowing to disable bufferable transfer</li>
+</ul></li>
+<li>stm32h7xx_hal_dma.c:
+<ul>
+<li>Add workaround to fix Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be lock when transferring data to/from USART/UART
+<ul>
+<li>Enabling the DMA bufferable transfer when the request is from a UART/USART(DMA_SxCR_TRBUFF bit field)</li>
+</ul></li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL TIM</strong>:
+<ul>
+<li>stm32h7xx_ll_tim.h
+<ul>
+<li>Parameter “RepetitionCounter” of “LL_TIM_InitTypeDef” is now of type “uint32_t” with possible values from 0 to 0xFFFF for advanced timers</li>
+</ul></li>
+</ul></li>
+<li><strong>LL FMC</strong>: (Core LL driver for HAL NAND, NOR, SDRAM, SRAM, not user LL driver)
+<ul>
+<li>stm32h7xx_ll_fmc.h: Minor update to remove useless U suffix following uint32_t cast</li>
+<li>stm32h7xx_ll_fmc.c:
+<ul>
+<li>Update FMC_NORSRAM_Init implemenation to fix compilation issue with MS Visual 2017</li>
+<li>Update FMC_NAND_CommonSpace_Timing_Init, FMC_NAND_AttributeSpace_Timing_Init, FMC_NAND_ECC_Enable, FMC_NAND_ECC_Disable and FMC_NAND_GetECC to fix GCC compiler warning due to unused parameter</li>
+</ul></li>
+</ul></li>
+<li><strong>LL UTIL</strong>:
+<ul>
+<li>stm32h7xx_ll_utils.h
+<ul>
+<li>Update numerical value of LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176 to LL_UTILS_PACKAGETYPE_TFBGA225 definition to align with the Reference Manual</li>
+<li>Add LL_SetFlashLatency API.</li>
+</ul></li>
+<li>stm32h7xx_ll_utils.c
+<ul>
+<li>Add implementation of LL_SetFlashLatency API (static functions UTILS_CalculateFlashLatency and UTILS_SetFlashLatency removed and repalced by the user API LL_SetFlashLatency)</li>
+<li>Update LL_SetSystemCoreClock to keep only setting SystemCoreClock according to the current Core frequency (Corex-M7 or Coretx-M4 in case of Dual Core line).
+<ul>
+<li>SystemD2Clock reflecting the D2 domain frequency is now set within UTILS_EnablePLLAndSwitchSystem</li>
+</ul></li>
+</ul></li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true"><strong>V1.7.0 / 06-December-2019</strong></label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
<li>Official release with support of STM32H7A3/B3xx/B0xx new devices<br />
</li>
<li>General updates to fix known defects and implementation enhancements</li>
@@ -633,7 +872,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true"><strong>V1.6.0 / 28-June-2019</strong></label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements</li>
<li><strong>HAL</strong>: generic
@@ -930,7 +1169,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true"><strong>V1.5.0 / 05-April-2019</strong></label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements</li>
<li>Add support for VOS0 power regulator voltage scaling with 480MHz over clock</li>
@@ -1466,7 +1705,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true"><strong>V1.4.0 / 30-November-2018</strong></label>
<div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements</li>
<li>Add LL drivers : LL_ADC, LL_BDMA, LL_BUS, LL_COMP, LL_CORTEX, LL_CRC, LL_DAC, LL_DMA, LL_DMA2D, LL_DMAMUX, LL_EXTI, LL_GPIO, LL_HRTIM, LL_HSEM, LL_I2C, LL_IWDG, LL_LPTIM, LL_LPUART, LL_MDMA, LL_OPAMP,LL_PWR, LL_RCC, LL_RNG, LL_RTC, LL_SPI, LL_SWPMI, LL_SYSTEM, LL_TIM, LL_USART, LL_UTILS, LL_WWDG</li>
@@ -1783,7 +2022,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.3.0 / 29-June-2018</strong></label>
<div>
-<h2 id="main-changes-4">Main Changes</h2>
+<h2 id="main-changes-5">Main Changes</h2>
<ul>
<li>Updates to fix known defects on HAL Cortex, HAL RCC and HAL SDMMC drivers</li>
<li><strong>HAL Cortex</strong>: Driver update to support 16 MPU regions instead of 8. User can now select an MPU regions from MPU_REGION_NUMBER0 to MPU_REGION_NUMBER15</li>
@@ -1795,7 +2034,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 / 29-December-2017</strong></label>
<div>
-<h2 id="main-changes-5">Main Changes</h2>
+<h2 id="main-changes-6">Main Changes</h2>
<ul>
<li>General updates to fix known defects and enhancements implementation</li>
<li><strong>HAL SPI</strong>: Driver reworked to fix critical issues</li>
@@ -1806,7 +2045,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 31-August-2017</strong></label>
<div>
-<h2 id="main-changes-6">Main Changes</h2>
+<h2 id="main-changes-7">Main Changes</h2>
<ul>
<li>General updates to fix known defects and enhancements implementation</li>
<li><strong>HAL FLASH</strong>: Add Mass Erase for both banks</li>
@@ -1821,7 +2060,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 21-April-2017</strong></label>
<div>
-<h2 id="main-changes-7">Main Changes</h2>
+<h2 id="main-changes-8">Main Changes</h2>
<ul>
<li>First official release for STM32H743xx/753xx devices</li>
</ul>
diff --git a/Src/stm32h7xx_hal.c b/Src/stm32h7xx_hal.c
index c52df22..861bf40 100644
--- a/Src/stm32h7xx_hal.c
+++ b/Src/stm32h7xx_hal.c
@@ -47,10 +47,10 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/**
- * @brief STM32H7xx HAL Driver version number V1.7.0
+ * @brief STM32H7xx HAL Driver version number V1.8.0
*/
#define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */
-#define __STM32H7xx_HAL_VERSION_SUB1 (0x07UL) /*!< [23:16] sub1 version */
+#define __STM32H7xx_HAL_VERSION_SUB1 (0x08UL) /*!< [23:16] sub1 version */
#define __STM32H7xx_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */
#define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */
#define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\
@@ -134,6 +134,8 @@
HAL_StatusTypeDef HAL_Init(void)
{
+uint32_t common_system_clock;
+
#if defined(DUAL_CORE) && defined(CORE_CM4)
/* Configure Cortex-M4 Instruction cache through ART accelerator */
__HAL_RCC_ART_CLK_ENABLE(); /* Enable the Cortex-M4 ART Clock */
@@ -146,18 +148,24 @@
/* Update the SystemCoreClock global variable */
#if defined(RCC_D1CFGR_D1CPRE)
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
+ common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
#else
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
+ common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
#endif
/* Update the SystemD2Clock global variable */
#if defined(RCC_D1CFGR_HPRE)
- SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
#else
- SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
#endif
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+ SystemCoreClock = SystemD2Clock;
+#else
+ SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
{
@@ -259,32 +267,11 @@
return HAL_ERROR;
}
-#if defined(DUAL_CORE)
- if (HAL_GetCurrentCPUID() == CM7_CPUID)
- {
- /* Cortex-M7 detected */
- /* Configure the SysTick to have interrupt in 1ms time basis*/
- if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
- {
- return HAL_ERROR;
- }
- }
- else
- {
- /* Cortex-M4 detected */
- /* Configure the SysTick to have interrupt in 1ms time basis*/
- if (HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / (1000UL / (uint32_t)uwTickFreq)) > 0U)
- {
- return HAL_ERROR;
- }
- }
-#else
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
{
return HAL_ERROR;
}
-#endif
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
diff --git a/Src/stm32h7xx_hal_dac.c b/Src/stm32h7xx_hal_dac.c
index a9437eb..89fbd80 100644
--- a/Src/stm32h7xx_hal_dac.c
+++ b/Src/stm32h7xx_hal_dac.c
@@ -1112,15 +1112,15 @@
/* Clear DAC_MCR_MODEx bits */
tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL));
/* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
- if ((sConfig->DAC_ConnectOnChipPeripheral & DAC_CHIPCONNECT_EXTERNAL) == DAC_CHIPCONNECT_EXTERNAL)
+ if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL)
{
connectOnChip = 0x00000000UL;
}
- else if ((sConfig->DAC_ConnectOnChipPeripheral & DAC_CHIPCONNECT_INTERNAL) == DAC_CHIPCONNECT_INTERNAL)
+ else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL)
{
connectOnChip = DAC_MCR_MODE1_0;
}
- else /* (sConfig->DAC_ConnectOnChipPeripheral & DAC_CHIPCONNECT_BOTH) == DAC_CHIPCONNECT_BOTH */
+ else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */
{
if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE)
{
diff --git a/Src/stm32h7xx_hal_dma.c b/Src/stm32h7xx_hal_dma.c
index 399ae0e..aeabc95 100644
--- a/Src/stm32h7xx_hal_dma.c
+++ b/Src/stm32h7xx_hal_dma.c
@@ -146,6 +146,19 @@
#define DMA_TO_BDMA_PRIORITY(__DMA_PRIORITY__) ((__DMA_PRIORITY__) >> 4U)
+#if defined(UART9)
+#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX) && ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \
+ (((__REQUEST__) >= DMA_REQUEST_UART4_RX) && ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \
+ (((__REQUEST__) >= DMA_REQUEST_USART6_RX) && ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \
+ (((__REQUEST__) >= DMA_REQUEST_UART7_RX) && ((__REQUEST__) <= DMA_REQUEST_UART8_TX )) || \
+ (((__REQUEST__) >= DMA_REQUEST_UART9_RX) && ((__REQUEST__) <= DMA_REQUEST_USART10_TX )))
+#else
+#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX) && ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \
+ (((__REQUEST__) >= DMA_REQUEST_UART4_RX) && ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \
+ (((__REQUEST__) >= DMA_REQUEST_USART6_RX) && ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \
+ (((__REQUEST__) >= DMA_REQUEST_UART7_RX) && ((__REQUEST__) <= DMA_REQUEST_UART8_TX )))
+
+#endif
/**
* @}
*/
@@ -278,6 +291,20 @@
registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
}
+ /* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be
+ lock when transfering data to/from USART/UART */
+#if (STM32H7_DEV_ID == 0x450UL)
+ if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U)
+ {
+#endif /* STM32H7_DEV_ID == 0x450UL */
+ if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U)
+ {
+ registerValue |= DMA_SxCR_TRBUFF;
+ }
+#if (STM32H7_DEV_ID == 0x450UL)
+ }
+#endif /* STM32H7_DEV_ID == 0x450UL */
+
/* Write to DMA Stream CR register */
((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue;
diff --git a/Src/stm32h7xx_hal_gpio.c b/Src/stm32h7xx_hal_gpio.c
index 641c7e9..25a19de 100644
--- a/Src/stm32h7xx_hal_gpio.c
+++ b/Src/stm32h7xx_hal_gpio.c
@@ -198,26 +198,6 @@
if (iocurrent != 0x00U)
{
/*--------------------- GPIO Mode Configuration ------------------------*/
- /* In case of Alternate function mode selection */
- if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- {
- /* Check the Alternate function parameters */
- assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
- assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
-
- /* Configure Alternate function mapped with the current IO */
- temp = GPIOx->AFR[position >> 3U];
- temp &= ~(0xFU << ((position & 0x07U) * 4U));
- temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
- GPIOx->AFR[position >> 3U] = temp;
- }
-
- /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
- temp = GPIOx->MODER;
- temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
- temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
- GPIOx->MODER = temp;
-
/* In case of Output or Alternate function mode selection */
if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
@@ -243,6 +223,26 @@
temp |= ((GPIO_Init->Pull) << (position * 2U));
GPIOx->PUPDR = temp;
+ /* In case of Alternate function mode selection */
+ if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ {
+ /* Check the Alternate function parameters */
+ assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
+ /* Configure Alternate function mapped with the current IO */
+ temp = GPIOx->AFR[position >> 3U];
+ temp &= ~(0xFU << ((position & 0x07U) * 4U));
+ temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
+ GPIOx->AFR[position >> 3U] = temp;
+ }
+
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+ temp = GPIOx->MODER;
+ temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
+ temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ GPIOx->MODER = temp;
+
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
@@ -333,9 +333,6 @@
tmp &= (0x0FUL << (4U * (position & 0x03U)));
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
{
- tmp = 0x0FUL << (4U * (position & 0x03U));
- SYSCFG->EXTICR[position >> 2U] &= ~tmp;
-
/* Clear EXTI line configuration for Current CPU */
EXTI_CurrentCPU->IMR1 &= ~(iocurrent);
EXTI_CurrentCPU->EMR1 &= ~(iocurrent);
@@ -343,6 +340,9 @@
/* Clear Rising Falling edge configuration */
EXTI->RTSR1 &= ~(iocurrent);
EXTI->FTSR1 &= ~(iocurrent);
+
+ tmp = 0x0FUL << (4U * (position & 0x03U));
+ SYSCFG->EXTICR[position >> 2U] &= ~tmp;
}
/*------------------------- GPIO Mode Configuration --------------------*/
@@ -352,14 +352,14 @@
/* Configure the default Alternate Function in current IO */
GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * 4U)) ;
- /* Configure the default value for IO Speed */
- GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
+ /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
/* Configure the default value IO Output Type */
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ;
- /* Deactivate the Pull-up and Pull-down resistor for the current IO */
- GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
+ /* Configure the default value for IO Speed */
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
}
position++;
diff --git a/Src/stm32h7xx_hal_i2c.c b/Src/stm32h7xx_hal_i2c.c
index 1b8c179..a9e7408 100644
--- a/Src/stm32h7xx_hal_i2c.c
+++ b/Src/stm32h7xx_hal_i2c.c
@@ -351,13 +351,13 @@
/* Private define to centralize the enable/disable of Interrupts */
-#define I2C_XFER_TX_IT (0x00000001U)
-#define I2C_XFER_RX_IT (0x00000002U)
-#define I2C_XFER_LISTEN_IT (0x00000004U)
+#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */
-#define I2C_XFER_ERROR_IT (0x00000011U)
-#define I2C_XFER_CPLT_IT (0x00000012U)
-#define I2C_XFER_RELOAD_IT (0x00000012U)
+#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error and NACK treatment */
+#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */
+#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */
/* Private define Sequential Transfer Options default/reset value */
#define I2C_NO_OPTION_FRAME (0xFFFF0000U)
@@ -410,6 +410,9 @@
static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+/* Private function to treat different error callback */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
+
/* Private function to flush TXDR register */
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
@@ -4251,9 +4254,21 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Disable Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
- I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+ /* Disable Interrupts and Store Previous state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ }
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
/* Set State at HAL_I2C_STATE_ABORT */
hi2c->State = HAL_I2C_STATE_ABORT;
@@ -5001,6 +5016,7 @@
{
uint32_t tmpoptions = hi2c->XferOptions;
uint32_t treatdmanack = 0U;
+ HAL_I2C_StateTypeDef tmpstate;
/* Process locked */
__HAL_LOCK(hi2c);
@@ -5079,8 +5095,24 @@
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
+ tmpstate = hi2c->State;
+
if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
{
+ if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+ {
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+ }
+ else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ {
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
}
@@ -5369,9 +5401,27 @@
*/
static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
{
+ uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+
/* Reset I2C handle mode */
hi2c->Mode = HAL_I2C_MODE_NONE;
+ /* If a DMA is ongoing, Update handle size context */
+ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+ {
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+ }
+ else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+ {
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
{
/* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
@@ -5426,19 +5476,36 @@
static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
uint32_t tmperror;
+ uint32_t tmpITFlags = ITFlags;
+ uint32_t tmp;
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ /* Disable Interrupts and Store Previous state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ }
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
/* Reset handle parameters */
- hi2c->PreviousState = I2C_STATE_NONE;
hi2c->XferISR = NULL;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET)
+ if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -5447,12 +5514,18 @@
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
+ /* Fetch Last receive data if any */
+ if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
+ {
+ /* Read data from RXDR */
+ tmp = (uint8_t)hi2c->Instance->RXDR;
+
+ UNUSED(tmp);
+ }
+
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
- /* Disable Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT);
-
/* Store current volatile hi2c->ErrorCode, misra rule */
tmperror = hi2c->ErrorCode;
@@ -5466,6 +5539,7 @@
else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
{
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
@@ -5500,6 +5574,7 @@
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
@@ -5546,12 +5621,26 @@
{
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
uint32_t tmpITFlags = ITFlags;
+ HAL_I2C_StateTypeDef tmpstate = hi2c->State;
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- /* Disable all interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
+ /* Disable Interrupts and Store Previous state */
+ if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+ }
+ else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -5565,6 +5654,9 @@
/* If a DMA is ongoing, Update handle size context */
if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
{
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
if (hi2c->hdmatx != NULL)
{
hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx);
@@ -5572,6 +5664,9 @@
}
else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
{
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
if (hi2c->hdmarx != NULL)
{
hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx);
@@ -5608,7 +5703,6 @@
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
- hi2c->PreviousState = I2C_STATE_NONE;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->XferISR = NULL;
@@ -5631,6 +5725,7 @@
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -5646,6 +5741,7 @@
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -5660,6 +5756,7 @@
else
{
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -5733,6 +5830,7 @@
static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
{
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+ uint32_t tmppreviousstate;
/* Reset handle parameters */
hi2c->Mode = HAL_I2C_MODE_NONE;
@@ -5752,7 +5850,6 @@
/* keep HAL_I2C_STATE_LISTEN if set */
hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->PreviousState = I2C_STATE_NONE;
hi2c->XferISR = I2C_Slave_ISR_IT;
}
else
@@ -5767,16 +5864,19 @@
/* Set HAL_I2C_STATE_READY */
hi2c->State = HAL_I2C_STATE_READY;
}
- hi2c->PreviousState = I2C_STATE_NONE;
hi2c->XferISR = NULL;
}
/* Abort DMA TX transfer if any */
- if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ tmppreviousstate = hi2c->PreviousState;
+ if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
{
- hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+ if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+ }
- if (hi2c->hdmatx != NULL)
+ if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
{
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
@@ -5792,13 +5892,20 @@
hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
}
}
+ else
+ {
+ I2C_TreatErrorCallback(hi2c);
+ }
}
/* Abort DMA RX transfer if any */
- else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+ else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
{
- hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+ if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+ }
- if (hi2c->hdmarx != NULL)
+ if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
{
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
@@ -5814,10 +5921,28 @@
hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
}
}
+ else
+ {
+ I2C_TreatErrorCallback(hi2c);
+ }
}
- else if (hi2c->State == HAL_I2C_STATE_ABORT)
+ else
+ {
+ I2C_TreatErrorCallback(hi2c);
+ }
+}
+
+/**
+ * @brief I2C Error callback treatment.
+ * @param hi2c I2C handle.
+ * @retval None
+ */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+ if (hi2c->State == HAL_I2C_STATE_ABORT)
{
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -5831,6 +5956,8 @@
}
else
{
+ hi2c->PreviousState = I2C_STATE_NONE;
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -6062,30 +6189,16 @@
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
/* Reset AbortCpltCallback */
- hi2c->hdmatx->XferAbortCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
-
- /* Check if come from abort from user */
- if (hi2c->State == HAL_I2C_STATE_ABORT)
+ if (hi2c->hdmatx != NULL)
{
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- hi2c->AbortCpltCallback(hi2c);
-#else
- HAL_I2C_AbortCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ hi2c->hdmatx->XferAbortCallback = NULL;
}
- else
+ if (hi2c->hdmarx != NULL)
{
- /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- hi2c->ErrorCallback(hi2c);
-#else
- HAL_I2C_ErrorCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ hi2c->hdmarx->XferAbortCallback = NULL;
}
+
+ I2C_TreatErrorCallback(hi2c);
}
/**
@@ -6362,19 +6475,19 @@
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
- if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
+ if (InterruptRequest == I2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
}
- if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+ if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
- tmpisr |= I2C_IT_STOPI;
+ tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
}
- if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
+ if (InterruptRequest == I2C_XFER_RELOAD_IT)
{
/* Enable TC interrupts */
tmpisr |= I2C_IT_TCI;
@@ -6400,7 +6513,7 @@
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
}
- if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+ if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
@@ -6454,19 +6567,19 @@
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
- if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
+ if (InterruptRequest == I2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
}
- if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+ if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
}
- if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
+ if (InterruptRequest == I2C_XFER_RELOAD_IT)
{
/* Enable TC interrupts */
tmpisr |= I2C_IT_TCI;
diff --git a/Src/stm32h7xx_hal_jpeg.c b/Src/stm32h7xx_hal_jpeg.c
index d60bdd0..223574f 100644
--- a/Src/stm32h7xx_hal_jpeg.c
+++ b/Src/stm32h7xx_hal_jpeg.c
@@ -1100,7 +1100,11 @@
HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf)
{
uint32_t error;
- uint32_t numberMCU, hfactor, vfactor, hMCU, vMCU;
+ uint32_t numberMCU;
+ uint32_t hfactor;
+ uint32_t vfactor;
+ uint32_t hMCU;
+ uint32_t vMCU;
/* Check the JPEG handle allocation */
if ((hjpeg == NULL) || (pConf == NULL))
@@ -1285,7 +1289,9 @@
*/
HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
{
- uint32_t yblockNb, cBblockNb, cRblockNb;
+ uint32_t yblockNb;
+ uint32_t cBblockNb;
+ uint32_t cRblockNb;
/* Check the JPEG handle allocation */
if ((hjpeg == NULL) || (pInfo == NULL))
@@ -2192,7 +2198,8 @@
*/
HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg)
{
- uint32_t tickstart, tmpContext;
+ uint32_t tickstart;
+ uint32_t tmpContext;
tmpContext = hjpeg->Context;
/*Reset the Context operation and method*/
@@ -2522,7 +2529,11 @@
*/
static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK)
{
- uint32_t i, p, l, code, si;
+ uint32_t i;
+ uint32_t p;
+ uint32_t l;
+ uint32_t code;
+ uint32_t si;
/* Figure C.1: Generation of table of Huffman code sizes */
p = 0;
@@ -2688,7 +2699,9 @@
{
HAL_StatusTypeDef error;
JPEG_DC_HuffCodeTableTypeDef dcSizeCodesTable;
- uint32_t i, lsb, msb;
+ uint32_t i;
+ uint32_t lsb;
+ uint32_t msb;
__IO uint32_t *address, *addressDef;
if (DCTableAddress == (hjpeg->Instance->HUFFENC_DC0))
@@ -3053,7 +3066,11 @@
static uint32_t JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable,
__IO uint32_t *QTableAddress)
{
- uint32_t i, j, quantRow, quantVal, ScaleFactor;
+ uint32_t i;
+ uint32_t j;
+ uint32_t quantRow;
+ uint32_t quantVal;
+ uint32_t ScaleFactor;
__IO uint32_t *tableAddress;
tableAddress = QTableAddress;
@@ -3455,7 +3472,10 @@
*/
static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords)
{
- uint32_t index, nBwords, nbBytes, dataword;
+ uint32_t index;
+ uint32_t nb_words;
+ uint32_t nb_bytes;
+ uint32_t dataword;
if (hjpeg->OutDataLength >= (hjpeg->JpegOutCount + (nbOutputWords * 4UL)))
{
@@ -3482,8 +3502,8 @@
}
else if (hjpeg->OutDataLength > hjpeg->JpegOutCount)
{
- nBwords = (hjpeg->OutDataLength - hjpeg->JpegOutCount) / 4UL;
- for (index = 0; index < nBwords; index++)
+ nb_words = (hjpeg->OutDataLength - hjpeg->JpegOutCount) / 4UL;
+ for (index = 0; index < nb_words; index++)
{
/*Transfer 32 bits from the JPEG output FIFO*/
dataword = hjpeg->Instance->DOR;
@@ -3505,9 +3525,9 @@
}
else
{
- nbBytes = hjpeg->OutDataLength - hjpeg->JpegOutCount;
+ nb_bytes = hjpeg->OutDataLength - hjpeg->JpegOutCount;
dataword = hjpeg->Instance->DOR;
- for (index = 0; index < nbBytes; index++)
+ for (index = 0; index < nb_bytes; index++)
{
hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)((dataword >> (8UL * (index & 0x3UL))) & 0xFFUL);
hjpeg->JpegOutCount++;
@@ -3521,8 +3541,8 @@
hjpeg->JpegOutCount = 0;
- nbBytes = 4UL - nbBytes;
- for (index = nbBytes; index < 4UL; index++)
+ nb_bytes = 4UL - nb_bytes;
+ for (index = nb_bytes; index < 4UL; index++)
{
hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)((dataword >> (8UL * index)) & 0xFFUL);
hjpeg->JpegOutCount++;
@@ -3546,7 +3566,11 @@
*/
static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords)
{
- uint32_t nbBytes = 0, nBwords, index, Dataword, inputCount;
+ uint32_t nb_bytes = 0;
+ uint32_t nb_words;
+ uint32_t index;
+ uint32_t dataword;
+ uint32_t input_count;
if ((hjpeg->InDataLength == 0UL) || (nbRequestWords == 0UL))
{
@@ -3555,7 +3579,7 @@
}
else if (hjpeg->InDataLength > hjpeg->JpegInCount)
{
- nbBytes = hjpeg->InDataLength - hjpeg->JpegInCount;
+ nb_bytes = hjpeg->InDataLength - hjpeg->JpegInCount;
}
else if (hjpeg->InDataLength == hjpeg->JpegInCount)
{
@@ -3571,39 +3595,39 @@
hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4UL);
}
hjpeg->JpegInCount = 0;
- nbBytes = hjpeg->InDataLength;
+ nb_bytes = hjpeg->InDataLength;
}
else
{
/* Nothing to do */
}
- if (((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0UL) && (nbBytes > 0UL))
+ if (((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0UL) && (nb_bytes > 0UL))
{
- nBwords = nbBytes / 4UL;
- if (nBwords >= nbRequestWords)
+ nb_words = nb_bytes / 4UL;
+ if (nb_words >= nbRequestWords)
{
for (index = 0; index < nbRequestWords; index++)
{
- inputCount = hjpeg->JpegInCount;
- hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount])) | \
- (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 1UL])) << 8) | \
- (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 2UL])) << 16) | \
- (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 3UL])) << 24));
+ input_count = hjpeg->JpegInCount;
+ hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count])) | \
+ (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 1UL])) << 8) | \
+ (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 2UL])) << 16) | \
+ (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 3UL])) << 24));
hjpeg->JpegInCount += 4UL;
}
}
- else /*nBwords < nbRequestWords*/
+ else /*nb_words < nbRequestWords*/
{
- if (nBwords > 0UL)
+ if (nb_words > 0UL)
{
- for (index = 0; index < nBwords; index++)
+ for (index = 0; index < nb_words; index++)
{
- inputCount = hjpeg->JpegInCount;
- hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount])) | \
- (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 1UL])) << 8) | \
- (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 2UL])) << 16) | \
- (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 3UL])) << 24));
+ input_count = hjpeg->JpegInCount;
+ hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count])) | \
+ (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 1UL])) << 8) | \
+ (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 2UL])) << 16) | \
+ (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 3UL])) << 24));
hjpeg->JpegInCount += 4UL;
}
@@ -3611,13 +3635,13 @@
else
{
/* end of file*/
- Dataword = 0;
- for (index = 0; index < nbBytes; index++)
+ dataword = 0;
+ for (index = 0; index < nb_bytes; index++)
{
- Dataword |= (uint32_t)hjpeg->pJpegInBuffPtr[hjpeg->JpegInCount] << (8UL * (index & 0x03UL));
+ dataword |= (uint32_t)hjpeg->pJpegInBuffPtr[hjpeg->JpegInCount] << (8UL * (index & 0x03UL));
hjpeg->JpegInCount++;
}
- hjpeg->Instance->DIR = Dataword;
+ hjpeg->Instance->DIR = dataword;
}
}
}
@@ -3850,7 +3874,9 @@
*/
static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg)
{
- uint32_t tmpContext, count, dataOut;
+ uint32_t tmpContext;
+ uint32_t count;
+ uint32_t dataOut;
for (count = JPEG_FIFO_SIZE; count > 0UL; count--)
{
diff --git a/Src/stm32h7xx_hal_lptim.c b/Src/stm32h7xx_hal_lptim.c
index b11c521..0a579dc 100644
--- a/Src/stm32h7xx_hal_lptim.c
+++ b/Src/stm32h7xx_hal_lptim.c
@@ -174,7 +174,6 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
/** @addtogroup LPTIM_Private_Constants
* @{
*/
@@ -183,6 +182,7 @@
* @}
*/
+/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
@@ -235,16 +235,19 @@
assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
- if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
{
assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
- assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
}
assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
+ }
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
{
assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
- assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
+ assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
}
assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
@@ -278,13 +281,17 @@
/* Get the LPTIMx CFGR value */
tmpcfgr = hlptim->Instance->CFGR;
- if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL))
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
{
- tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL));
}
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
{
- tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRIGSEL));
+ }
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
+ {
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_CKFLT));
}
/* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
@@ -298,25 +305,35 @@
hlptim->Init.UpdateMode |
hlptim->Init.CounterSource);
- if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL))
+ /* Glitch filters for internal triggers and external inputs are configured
+ * only if an internal clock source is provided to the LPTIM
+ */
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
{
- tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
+ tmpcfgr |= (hlptim->Init.Trigger.SampleTime |
hlptim->Init.UltraLowPowerClock.SampleTime);
}
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ /* Configure the active edge or edges used by the counter only if LPTIM is
+ * clocked by an external clock source
+ */
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ {
+ tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity);
+ }
+
+ if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Enable External trigger and set the trigger source */
- tmpcfgr |= (hlptim->Init.Trigger.Source |
- hlptim->Init.Trigger.ActiveEdge |
- hlptim->Init.Trigger.SampleTime);
+ tmpcfgr |= (hlptim->Init.Trigger.Source |
+ hlptim->Init.Trigger.ActiveEdge);
}
/* Write to LPTIMx CFGR */
hlptim->Instance->CFGR = tmpcfgr;
/* Configure LPTIM input sources */
- if ((hlptim->Instance == LPTIM1)||(hlptim->Instance == LPTIM2))
+ if ((hlptim->Instance == LPTIM1) || (hlptim->Instance == LPTIM2))
{
/* Check LPTIM Input1 and Input2 sources */
assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
@@ -327,7 +344,7 @@
}
else
{
- if(hlptim->Instance == LPTIM3)
+ if (hlptim->Instance == LPTIM3)
{
/* Check LPTIM3 Input1 source */
assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
@@ -2307,17 +2324,17 @@
{
HAL_StatusTypeDef result = HAL_OK;
uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);
- do
+ do
+ {
+ count--;
+ if (count == 0UL)
{
- count--;
- if (count == 0UL)
- {
- result = HAL_TIMEOUT;
- }
+ result = HAL_TIMEOUT;
}
- while((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
+ }
+ while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
- return result;
+ return result;
}
/**
@@ -2344,29 +2361,29 @@
/* Save LPTIM source clock */
switch ((uint32_t)hlptim->Instance)
{
- case LPTIM1_BASE:
- tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE();
- break;
- case LPTIM2_BASE:
- tmpclksource = __HAL_RCC_GET_LPTIM2_SOURCE();
- break;
+ case LPTIM1_BASE:
+ tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE();
+ break;
+ case LPTIM2_BASE:
+ tmpclksource = __HAL_RCC_GET_LPTIM2_SOURCE();
+ break;
#if defined(LPTIM3)
- case LPTIM3_BASE:
- tmpclksource = __HAL_RCC_GET_LPTIM3_SOURCE();
- break;
+ case LPTIM3_BASE:
+ tmpclksource = __HAL_RCC_GET_LPTIM3_SOURCE();
+ break;
#endif /* LPTIM3 */
#if defined(LPTIM4)
- case LPTIM4_BASE:
- tmpclksource = __HAL_RCC_GET_LPTIM4_SOURCE();
- break;
+ case LPTIM4_BASE:
+ tmpclksource = __HAL_RCC_GET_LPTIM4_SOURCE();
+ break;
#endif /* LPTIM4 */
#if defined(LPTIM5)
- case LPTIM5_BASE:
- tmpclksource = __HAL_RCC_GET_LPTIM5_SOURCE();
- break;
+ case LPTIM5_BASE:
+ tmpclksource = __HAL_RCC_GET_LPTIM5_SOURCE();
+ break;
#endif /* LPTIM5 */
- default:
- break;
+ default:
+ break;
}
/* Save LPTIM configuration registers */
@@ -2379,34 +2396,34 @@
/*********** Reset LPTIM ***********/
switch ((uint32_t)hlptim->Instance)
{
- case LPTIM1_BASE:
- __HAL_RCC_LPTIM1_FORCE_RESET();
- __HAL_RCC_LPTIM1_RELEASE_RESET();
- break;
- case LPTIM2_BASE:
- __HAL_RCC_LPTIM2_FORCE_RESET();
- __HAL_RCC_LPTIM2_RELEASE_RESET();
- break;
+ case LPTIM1_BASE:
+ __HAL_RCC_LPTIM1_FORCE_RESET();
+ __HAL_RCC_LPTIM1_RELEASE_RESET();
+ break;
+ case LPTIM2_BASE:
+ __HAL_RCC_LPTIM2_FORCE_RESET();
+ __HAL_RCC_LPTIM2_RELEASE_RESET();
+ break;
#if defined(LPTIM3)
- case LPTIM3_BASE:
- __HAL_RCC_LPTIM3_FORCE_RESET();
- __HAL_RCC_LPTIM3_RELEASE_RESET();
- break;
+ case LPTIM3_BASE:
+ __HAL_RCC_LPTIM3_FORCE_RESET();
+ __HAL_RCC_LPTIM3_RELEASE_RESET();
+ break;
#endif /* LPTIM3 */
#if defined(LPTIM4)
- case LPTIM4_BASE:
- __HAL_RCC_LPTIM4_FORCE_RESET();
- __HAL_RCC_LPTIM4_RELEASE_RESET();
- break;
+ case LPTIM4_BASE:
+ __HAL_RCC_LPTIM4_FORCE_RESET();
+ __HAL_RCC_LPTIM4_RELEASE_RESET();
+ break;
#endif /* LPTIM4 */
#if defined(LPTIM5)
- case LPTIM5_BASE:
- __HAL_RCC_LPTIM5_FORCE_RESET();
- __HAL_RCC_LPTIM5_RELEASE_RESET();
- break;
+ case LPTIM5_BASE:
+ __HAL_RCC_LPTIM5_FORCE_RESET();
+ __HAL_RCC_LPTIM5_RELEASE_RESET();
+ break;
#endif /* LPTIM5 */
- default:
- break;
+ default:
+ break;
}
/*********** Restore LPTIM Config ***********/
@@ -2415,29 +2432,29 @@
/* Force LPTIM source kernel clock from APB */
switch ((uint32_t)hlptim->Instance)
{
- case LPTIM1_BASE:
- __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_D2PCLK1);
- break;
- case LPTIM2_BASE:
- __HAL_RCC_LPTIM2_CONFIG(RCC_LPTIM2CLKSOURCE_D3PCLK1);
- break;
+ case LPTIM1_BASE:
+ __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_D2PCLK1);
+ break;
+ case LPTIM2_BASE:
+ __HAL_RCC_LPTIM2_CONFIG(RCC_LPTIM2CLKSOURCE_D3PCLK1);
+ break;
#if defined(LPTIM3)
- case LPTIM3_BASE:
- __HAL_RCC_LPTIM3_CONFIG(RCC_LPTIM3CLKSOURCE_D3PCLK1);
- break;
+ case LPTIM3_BASE:
+ __HAL_RCC_LPTIM3_CONFIG(RCC_LPTIM3CLKSOURCE_D3PCLK1);
+ break;
#endif /* LPTIM3 */
#if defined(LPTIM4)
- case LPTIM4_BASE:
- __HAL_RCC_LPTIM4_CONFIG(RCC_LPTIM4CLKSOURCE_D3PCLK1);
- break;
+ case LPTIM4_BASE:
+ __HAL_RCC_LPTIM4_CONFIG(RCC_LPTIM4CLKSOURCE_D3PCLK1);
+ break;
#endif /* LPTIM4 */
#if defined(LPTIM5)
- case LPTIM5_BASE:
- __HAL_RCC_LPTIM5_CONFIG(RCC_LPTIM5CLKSOURCE_D3PCLK1);
- break;
+ case LPTIM5_BASE:
+ __HAL_RCC_LPTIM5_CONFIG(RCC_LPTIM5CLKSOURCE_D3PCLK1);
+ break;
#endif /* LPTIM5 */
- default:
- break;
+ default:
+ break;
}
if (tmpCMP != 0UL)
@@ -2472,29 +2489,29 @@
/* Restore LPTIM source kernel clock */
switch ((uint32_t)hlptim->Instance)
{
- case LPTIM1_BASE:
- __HAL_RCC_LPTIM1_CONFIG(tmpclksource);
- break;
- case LPTIM2_BASE:
- __HAL_RCC_LPTIM2_CONFIG(tmpclksource);
- break;
+ case LPTIM1_BASE:
+ __HAL_RCC_LPTIM1_CONFIG(tmpclksource);
+ break;
+ case LPTIM2_BASE:
+ __HAL_RCC_LPTIM2_CONFIG(tmpclksource);
+ break;
#if defined(LPTIM3)
- case LPTIM3_BASE:
- __HAL_RCC_LPTIM3_CONFIG(tmpclksource);
- break;
+ case LPTIM3_BASE:
+ __HAL_RCC_LPTIM3_CONFIG(tmpclksource);
+ break;
#endif /* LPTIM3 */
#if defined(LPTIM4)
- case LPTIM4_BASE:
- __HAL_RCC_LPTIM4_CONFIG(tmpclksource);
- break;
+ case LPTIM4_BASE:
+ __HAL_RCC_LPTIM4_CONFIG(tmpclksource);
+ break;
#endif /* LPTIM4 */
#if defined(LPTIM5)
- case LPTIM5_BASE:
- __HAL_RCC_LPTIM5_CONFIG(tmpclksource);
- break;
+ case LPTIM5_BASE:
+ __HAL_RCC_LPTIM5_CONFIG(tmpclksource);
+ break;
#endif /* LPTIM5 */
- default:
- break;
+ default:
+ break;
}
}
diff --git a/Src/stm32h7xx_hal_mmc.c b/Src/stm32h7xx_hal_mmc.c
index 9774f14..227a1a4 100644
--- a/Src/stm32h7xx_hal_mmc.c
+++ b/Src/stm32h7xx_hal_mmc.c
@@ -387,7 +387,6 @@
{
uint32_t errorstate;
MMC_InitTypeDef Init;
- HAL_StatusTypeDef status;
/* Default SDMMC peripheral configuration for MMC card initialization */
Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
@@ -397,18 +396,10 @@
Init.ClockDiv = SDMMC_INIT_CLK_DIV;
/* Initialize SDMMC peripheral interface with default configuration */
- status = SDMMC_Init(hmmc->Instance, Init);
- if(status == HAL_ERROR)
- {
- return HAL_ERROR;
- }
+ (void)SDMMC_Init(hmmc->Instance, Init);
/* Set Power State to ON */
- status = SDMMC_PowerState_ON(hmmc->Instance);
- if(status == HAL_ERROR)
- {
- return HAL_ERROR;
- }
+ (void)SDMMC_PowerState_ON(hmmc->Instance);
/* Identify card operating voltage */
errorstate = MMC_PowerON(hmmc);
@@ -428,6 +419,17 @@
return HAL_ERROR;
}
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
return HAL_OK;
}
@@ -568,20 +570,6 @@
add *= 512U;
}
- if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U)
- {
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- }
-
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE;
@@ -755,20 +743,6 @@
add *= 512U;
}
- if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U)
- {
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- }
-
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE;
@@ -943,20 +917,6 @@
add *= 512U;
}
- if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U)
- {
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- }
-
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
@@ -1050,20 +1010,6 @@
add *= 512U;
}
- if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U)
- {
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- }
-
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
@@ -1158,20 +1104,6 @@
add *= 512U;
}
- if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U)
- {
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode = errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- }
-
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
@@ -1268,20 +1200,6 @@
add *= 512U;
}
- if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U)
- {
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- }
-
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
@@ -2757,29 +2675,6 @@
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = 0;
- config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B;
- config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
- config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- config.DPSM = SDMMC_DPSM_DISABLE;
- (void)SDMMC_ConfigData(hmmc->Instance, &config);
-
- if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U)
- {
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- }
-
- /* Configure the MMC DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = 512;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
diff --git a/Src/stm32h7xx_hal_ospi.c b/Src/stm32h7xx_hal_ospi.c
index 0a8e480..b76f805 100644
--- a/Src/stm32h7xx_hal_ospi.c
+++ b/Src/stm32h7xx_hal_ospi.c
@@ -377,11 +377,8 @@
#endif
/* Configure the default timeout for the OSPI memory access */
- status = HAL_OSPI_SetTimeout(hospi, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
- }
+ (void)HAL_OSPI_SetTimeout(hospi, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
- if (status == HAL_OK)
- {
/* Configure memory type, device size, chip select high time, clocked chip select high time, delay block bypass, free running clock, clock mode */
MODIFY_REG(hospi->Instance->DCR1,
(OCTOSPI_DCR1_MTYP | OCTOSPI_DCR1_DEVSIZE | OCTOSPI_DCR1_CSHT | OCTOSPI_DCR1_CKCSHT |
@@ -408,33 +405,33 @@
if (status == HAL_OK)
{
- /* Configure clock prescaler */
- MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER, ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos));
+ /* Configure clock prescaler */
+ MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER, ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos));
- /* Configure Dual Quad mode */
- MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DQM, hospi->Init.DualQuad);
+ /* Configure Dual Quad mode */
+ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DQM, hospi->Init.DualQuad);
- /* Configure sample shifting and delay hold quarter cycle */
- MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC), (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle));
+ /* Configure sample shifting and delay hold quarter cycle */
+ MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC), (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle));
- /* Enable OctoSPI */
- __HAL_OSPI_ENABLE(hospi);
-
- /* Enable free running clock if needed : must be done after OSPI enable */
- if (hospi->Init.FreeRunningClock == HAL_OSPI_FREERUNCLK_ENABLE)
- {
- SET_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
- }
+ /* Enable OctoSPI */
+ __HAL_OSPI_ENABLE(hospi);
- /* Initialize the OSPI state */
- if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
- {
- hospi->State = HAL_OSPI_STATE_HYPERBUS_INIT;
- }
- else
- {
- hospi->State = HAL_OSPI_STATE_READY;
- }
+ /* Enable free running clock if needed : must be done after OSPI enable */
+ if (hospi->Init.FreeRunningClock == HAL_OSPI_FREERUNCLK_ENABLE)
+ {
+ SET_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
+ }
+
+ /* Initialize the OSPI state */
+ if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
+ {
+ hospi->State = HAL_OSPI_STATE_HYPERBUS_INIT;
+ }
+ else
+ {
+ hospi->State = HAL_OSPI_STATE_READY;
+ }
}
}
}
@@ -2457,6 +2454,7 @@
assert_param(IS_OSPIM_PORT(cfg->NCSPort));
assert_param(IS_OSPIM_IO_PORT(cfg->IOLowPort));
assert_param(IS_OSPIM_IO_PORT(cfg->IOHighPort));
+ assert_param(IS_OSPIM_REQ2ACKTIME(cfg->Req2AckTime));
if (hospi->Instance == OCTOSPI1)
{
@@ -2494,13 +2492,29 @@
}
/***************** Deactivation of previous configuration *****************/
- if (IOM_cfg[instance].ClkPort != 0U)
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN);
+ if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) != 0U)
{
- CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN);
- CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN);
- CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN);
- CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN);
- CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN);
+ /* De-multiplexing should be performed */
+ CLEAR_BIT(OCTOSPIM->CR, OCTOSPIM_CR_MUXEN);
+
+ if (other_instance == 1U)
+ {
+ SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKSRC);
+ SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSSRC);
+ SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLSRC_1);
+ SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHSRC_1);
+ }
+ }
+ else
+ {
+ if (IOM_cfg[instance].ClkPort != 0U)
+ {
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN);
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN);
+ CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN);
+ CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN);
+ }
}
/********************* Deactivation of other instance *********************/
@@ -2508,38 +2522,79 @@
(cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) ||
(cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort))
{
- CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN);
- CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN);
- CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN);
- CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN);
- CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN);
+ if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) && (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) &&
+ (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) && (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort))
+ {
+ /* Multiplexing should be performed */
+ SET_BIT(OCTOSPIM->CR, OCTOSPIM_CR_MUXEN);
+ }
+ else
+ {
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN);
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN);
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN);
+ CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN);
+ CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN);
+ }
}
/******************** Activation of new configuration *********************/
- MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos)));
- MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos)));
MODIFY_REG(OCTOSPIM->PCR[(cfg->NCSPort-1U)], (OCTOSPIM_PCR_NCSEN | OCTOSPIM_PCR_NCSSRC), (OCTOSPIM_PCR_NCSEN | (instance << OCTOSPIM_PCR_NCSSRC_Pos)));
- if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U)
+ if ((cfg->Req2AckTime - 1U) > ((OCTOSPIM->CR & OCTOSPIM_CR_REQ2ACK_TIME) >> OCTOSPIM_CR_REQ2ACK_TIME_Pos))
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
- (OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
- }
- else
- {
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
- (OCTOSPIM_PCR_IOHEN | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
+ MODIFY_REG(OCTOSPIM->CR, OCTOSPIM_CR_REQ2ACK_TIME, ((cfg->Req2AckTime - 1U) << OCTOSPIM_CR_REQ2ACK_TIME_Pos));
}
- if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U)
+ if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) != 0U)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
- (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
+ MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), OCTOSPIM_PCR_CLKEN);
+ MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), OCTOSPIM_PCR_DQSEN);
+
+ if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U)
+ {
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), OCTOSPIM_PCR_IOLEN);
+ }
+ else
+ {
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), OCTOSPIM_PCR_IOHEN);
+ }
+
+ if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U)
+ {
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0));
+ }
+ else
+ {
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0));
+ }
}
else
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
- (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
+ MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos)));
+ MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos)));
+
+ if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U)
+ {
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
+ (OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
+ }
+ else
+ {
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
+ (OCTOSPIM_PCR_IOHEN | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
+ }
+
+ if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U)
+ {
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
+ (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
+ }
+ else
+ {
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
+ (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
+ }
}
/******* Re-enable both OctoSPI after configure OctoSPI IO Manager ********/
@@ -2905,7 +2960,14 @@
if (instance_nb == 2U)
{
- value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1);
+ if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) == 0U)
+ {
+ value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1);
+ }
+ else
+ {
+ value = OCTOSPIM_PCR_NCSSRC;
+ }
}
/* Get the information about the instance */
diff --git a/Src/stm32h7xx_hal_pssi.c b/Src/stm32h7xx_hal_pssi.c
index 11ab361..19f0a69 100644
--- a/Src/stm32h7xx_hal_pssi.c
+++ b/Src/stm32h7xx_hal_pssi.c
@@ -185,6 +185,7 @@
void PSSI_DMAError(DMA_HandleTypeDef *hdma);
void PSSI_DMAAbort(DMA_HandleTypeDef *hdma);
+
/* Private functions to handle IT transfer */
static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode);
@@ -613,6 +614,10 @@
uint32_t tickstart;
uint32_t transfer_size = Size;
+#if defined (__GNUC__)
+ __IO uint16_t *pdr_16bits = (__IO uint16_t *)(&(hpssi->Instance->DR));
+#endif /* __GNUC__ */
+
if (((hpssi->Init.DataWidth == HAL_PSSI_8BITS) && (hpssi->Init.BusWidth != HAL_PSSI_8LINES)) ||
((hpssi->Init.DataWidth == HAL_PSSI_16BITS) && ((Size%2U) != 0U)) ||
((hpssi->Init.DataWidth == HAL_PSSI_32BITS) && ((Size%4U) != 0U)))
@@ -682,7 +687,11 @@
return HAL_ERROR;
}
/* Write data to DR */
+#if defined (__GNUC__)
+ *pdr_16bits = *pbuffer;
+#else
*(__IO uint16_t *)((uint32_t)(&hpssi->Instance->DR)) = *pbuffer;
+#endif /* __GNUC__ */
/* Increment Buffer pointer */
pbuffer++;
@@ -763,6 +772,9 @@
{
uint32_t tickstart;
uint32_t transfer_size = Size;
+#if defined (__GNUC__)
+ __IO uint16_t *pdr_16bits = (__IO uint16_t *)(&(hpssi->Instance->DR));
+#endif /* __GNUC__ */
if (((hpssi->Init.DataWidth == HAL_PSSI_8BITS) && (hpssi->Init.BusWidth != HAL_PSSI_8LINES)) ||
((hpssi->Init.DataWidth == HAL_PSSI_16BITS) && ((Size%2U) != 0U)) ||
@@ -784,8 +796,8 @@
HAL_PSSI_DISABLE(hpssi);
/* Configure transfer parameters */
hpssi->Instance->CR |= PSSI_CR_OUTEN_INPUT |((hpssi->Init.ClockPolarity == HAL_PSSI_FALLING_EDGE)?0U:PSSI_CR_CKPOL);
-
-
+
+
/* DMA Disable */
hpssi->Instance->CR &= PSSI_CR_DMA_DISABLE;
@@ -833,7 +845,12 @@
}
/* Read data from DR */
+#if defined (__GNUC__)
+ *pbuffer = *pdr_16bits;
+#else
*pbuffer = *(__IO uint16_t *)((uint32_t)&hpssi->Instance->DR);
+#endif /* __GNUC__ */
+
pbuffer++;
transfer_size -= 2U;
@@ -942,12 +959,12 @@
if( hpssi->hdmatx->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
{
MODIFY_REG(hpssi->Instance->CR,PSSI_CR_DMAEN|PSSI_CR_OUTEN|PSSI_CR_CKPOL,PSSI_CR_DMA_ENABLE | PSSI_CR_OUTEN_OUTPUT |
- ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE)?0U:PSSI_CR_CKPOL));
+ ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE)?0U:PSSI_CR_CKPOL));
}
else
{
MODIFY_REG(hpssi->Instance->CR,PSSI_CR_DMAEN|PSSI_CR_OUTEN|PSSI_CR_CKPOL,PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth | PSSI_CR_OUTEN_OUTPUT |
- ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE)?0U:PSSI_CR_CKPOL));
+ ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE)?0U:PSSI_CR_CKPOL));
}
/* Set the PSSI DMA transfer complete callback */
@@ -1075,17 +1092,17 @@
{
if (hpssi->hdmarx != NULL)
{
-
+
/* Configure BusWidth */
if( hpssi->hdmatx->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
{
MODIFY_REG(hpssi->Instance->CR,PSSI_CR_DMAEN|PSSI_CR_OUTEN|PSSI_CR_CKPOL,PSSI_CR_DMA_ENABLE |
- ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE)?PSSI_CR_CKPOL:0U));
+ ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE)?PSSI_CR_CKPOL:0U));
}
else
{
MODIFY_REG(hpssi->Instance->CR,PSSI_CR_DMAEN|PSSI_CR_OUTEN|PSSI_CR_CKPOL,PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth |
- ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE)?PSSI_CR_CKPOL:0U));
+ ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE)?PSSI_CR_CKPOL:0U));
}
/* Set the PSSI DMA transfer complete callback */
diff --git a/Src/stm32h7xx_hal_qspi.c b/Src/stm32h7xx_hal_qspi.c
index 4e3132e..0587b0b 100644
--- a/Src/stm32h7xx_hal_qspi.c
+++ b/Src/stm32h7xx_hal_qspi.c
@@ -24,7 +24,7 @@
[..]
(#) As prerequisite, fill in the HAL_QSPI_MspInit() :
(++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
- (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
+ (++) Reset QuadSPI Peripheral with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
(++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
(++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
(++) If interrupt mode is used, enable and configure QuadSPI global
@@ -64,7 +64,7 @@
(++) In polling mode, the output of the function is done when the transfer is complete.
(++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
- (++) In DMA mode,HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
+ (++) In DMA mode,HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
*** Auto-polling functional mode ***
====================================
@@ -91,23 +91,23 @@
====================================
[..]
(#) Configure the SourceInc and DestinationInc of MDMA paramters in the HAL_QSPI_MspInit() function :
- (++) MDMA settings for write operation :
- (+) The DestinationInc should be MDMA_DEST_INC_DISABLE
+ (++) MDMA settings for write operation :
+ (+) The DestinationInc should be MDMA_DEST_INC_DISABLE
(+) The SourceInc must be a value of @ref MDMA_Source_increment_mode (Except the MDMA_SRC_INC_DOUBLEWORD).
- (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD)
+ (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD)
aligned with @ref MDMA_Source_increment_mode .
- (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
- (++) MDMA settings for read operation :
- (+) The SourceInc should be MDMA_SRC_INC_DISABLE
+ (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
+ (++) MDMA settings for read operation :
+ (+) The SourceInc should be MDMA_SRC_INC_DISABLE
(+) The DestinationInc must be a value of @ref MDMA_Destination_increment_mode (Except the MDMA_DEST_INC_DOUBLEWORD).
(+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) .
(+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
aligned with @ref MDMA_Destination_increment_mode.
(++)The buffer Transfer Length (BufferTransferLength) = number of bytes in the FIFO (FifoThreshold) of the Quadspi.
- (#)In case of wrong MDMA setting
- (++) For write operation :
+ (#)In case of wrong MDMA setting
+ (++) For write operation :
(+) If the DestinationInc is different to MDMA_DEST_INC_DISABLE , it will be disabled by the HAL_QSPI_Transmit_DMA().
- (++) For read operation :
+ (++) For read operation :
(+) If the SourceInc is not set to MDMA_SRC_INC_DISABLE , it will be disabled by the HAL_QSPI_Receive_DMA().
*** Memory-mapped functional mode ***
@@ -137,7 +137,7 @@
(++) In polling mode, the output of the function is done when the transfer
complete bit is set and the busy bit cleared.
(++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
- the transfer complete bi is set.
+ the transfer complete bit is set.
*** Control functions ***
=========================
@@ -146,6 +146,7 @@
(#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
(#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
(#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
+ (#) HAL_QSPI_SetFlashID() function configures the index of the flash memory to be accessed.
*** Callback registration ***
=============================================
@@ -218,7 +219,7 @@
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -226,18 +227,17 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
+#if defined(QUADSPI)
+
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
-#ifdef HAL_QSPI_MODULE_ENABLED
-
-#if defined(QUADSPI)
-
/** @defgroup QSPI QSPI
* @brief QSPI HAL module driver
* @{
*/
+#ifdef HAL_QSPI_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
@@ -245,7 +245,7 @@
/** @defgroup QSPI_Private_Constants QSPI Private Constants
* @{
*/
-#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /*!<Indirect write mode*/
+#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE 0x00000000U /*!<Indirect write mode*/
#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE) /*!<Memory-mapped mode*/
@@ -300,7 +300,7 @@
/**
* @brief Initialize the QSPI mode according to the specified parameters
* in the QSPI_InitTypeDef and initialize the associated handle.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
@@ -329,13 +329,8 @@
assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
}
- /* Process locked */
- __HAL_LOCK(hqspi);
-
if(hqspi->State == HAL_QSPI_STATE_RESET)
{
- /* Allocate lock resource and initialize it */
- hqspi->Lock = HAL_UNLOCKED;
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
/* Reset Callback pointers in HAL_QSPI_STATE_RESET only */
@@ -359,8 +354,9 @@
/* Init the low level hardware : GPIO, CLOCK */
HAL_QSPI_MspInit(hqspi);
#endif
+
/* Configure the default timeout for the QSPI memory access */
- HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
+ HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE);
}
/* Configure QSPI FIFO Threshold */
@@ -392,16 +388,13 @@
hqspi->State = HAL_QSPI_STATE_READY;
}
- /* Release Lock */
- __HAL_UNLOCK(hqspi);
-
/* Return function status */
return status;
}
/**
* @brief De-Initialize the QSPI peripheral.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
@@ -412,9 +405,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hqspi);
-
/* Disable the QSPI Peripheral Clock */
__HAL_QSPI_DISABLE(hqspi);
@@ -437,15 +427,12 @@
/* Initialize the QSPI state */
hqspi->State = HAL_QSPI_STATE_RESET;
- /* Release Lock */
- __HAL_UNLOCK(hqspi);
-
return HAL_OK;
}
/**
* @brief Initialize the QSPI MSP.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
@@ -460,7 +447,7 @@
/**
* @brief DeInitialize the QSPI MSP.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
@@ -499,7 +486,7 @@
/**
* @brief Handle QSPI interrupt request.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @retval None
*/
void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
@@ -509,7 +496,7 @@
uint32_t itsource = READ_REG(hqspi->Instance->CR);
/* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
- if(((flag & QSPI_FLAG_FT) == QSPI_FLAG_FT) && ((itsource & QSPI_IT_FT) == QSPI_IT_FT))
+ if(((flag & QSPI_FLAG_FT) != 0U) && ((itsource & QSPI_IT_FT) != 0U))
{
data_reg = &hqspi->Instance->DR;
@@ -521,7 +508,7 @@
if (hqspi->TxXferCount > 0U)
{
/* Fill the FIFO until the threshold is reached */
- *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr;
+ *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;
hqspi->pTxBuffPtr++;
hqspi->TxXferCount--;
}
@@ -542,7 +529,7 @@
if (hqspi->RxXferCount > 0U)
{
/* Read the FIFO until the threshold is reached */
- *hqspi->pRxBuffPtr = *(__IO uint8_t *)data_reg;
+ *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
hqspi->pRxBuffPtr++;
hqspi->RxXferCount--;
}
@@ -559,6 +546,7 @@
{
/* Nothing to do */
}
+
/* FIFO Threshold callback */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
hqspi->FifoThresholdCallback(hqspi);
@@ -568,7 +556,7 @@
}
/* QSPI Transfer Complete interrupt occurred -------------------------------*/
- else if(((flag & QSPI_FLAG_TC) == QSPI_FLAG_TC) && ((itsource & QSPI_IT_TC) == QSPI_IT_TC))
+ else if(((flag & QSPI_FLAG_TC) != 0U) && ((itsource & QSPI_IT_TC) != 0U))
{
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
@@ -579,7 +567,7 @@
/* Transfer complete callback */
if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
{
- if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
@@ -588,6 +576,7 @@
__HAL_MDMA_DISABLE(hqspi->hmdma);
}
+
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
@@ -600,7 +589,7 @@
}
else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
{
- if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
@@ -616,7 +605,7 @@
if (hqspi->RxXferCount > 0U)
{
/* Read the last data received in the FIFO until it is empty */
- *hqspi->pRxBuffPtr = *(__IO uint8_t *)data_reg;
+ *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
hqspi->pRxBuffPtr++;
hqspi->RxXferCount--;
}
@@ -628,6 +617,7 @@
}
}
+
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
@@ -688,7 +678,7 @@
}
/* QSPI Status Match interrupt occurred ------------------------------------*/
- else if(((flag & QSPI_FLAG_SM)== QSPI_FLAG_SM) && ((itsource & QSPI_IT_SM) == QSPI_IT_SM))
+ else if(((flag & QSPI_FLAG_SM) != 0U) && ((itsource & QSPI_IT_SM) != 0U))
{
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
@@ -712,7 +702,7 @@
}
/* QSPI Transfer Error interrupt occurred ----------------------------------*/
- else if(((flag & QSPI_FLAG_TE) == QSPI_FLAG_TE) && ((itsource & QSPI_IT_TE) == QSPI_IT_TE))
+ else if(((flag & QSPI_FLAG_TE) != 0U) && ((itsource & QSPI_IT_TE) != 0U))
{
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
@@ -723,7 +713,7 @@
/* Set error code */
hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
- if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
@@ -761,7 +751,7 @@
}
/* QSPI Timeout interrupt occurred -----------------------------------------*/
- else if(((flag & QSPI_FLAG_TO) == QSPI_FLAG_TO) && ((itsource & QSPI_IT_TO) == QSPI_IT_TO))
+ else if(((flag & QSPI_FLAG_TO) != 0U) && ((itsource & QSPI_IT_TO) != 0U))
{
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
@@ -773,6 +763,7 @@
HAL_QSPI_TimeOutCallback(hqspi);
#endif
}
+
else
{
/* Nothing to do */
@@ -781,7 +772,7 @@
/**
* @brief Set the command configuration.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @param cmd : structure that contains the command configuration information
* @param Timeout : Timeout duration
* @note This function is used only in Indirect Read or Write Modes
@@ -849,7 +840,6 @@
/* Update QSPI state */
hqspi->State = HAL_QSPI_STATE_READY;
}
-
}
else
{
@@ -872,7 +862,7 @@
/**
* @brief Set the command configuration in interrupt mode.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @param cmd : structure that contains the command configuration information
* @note This function is used only in Indirect Read or Write Modes
* @retval HAL status
@@ -971,10 +961,11 @@
/**
* @brief Transmit an amount of data in blocking mode.
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer
+ * @param hqspi : QSPI handle
+ * @param pData : pointer to data buffer
* @param Timeout : Timeout duration
* @note This function is used only in Indirect Write Mode
+
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
@@ -1013,7 +1004,7 @@
break;
}
- *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr;
+ *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;
hqspi->pTxBuffPtr++;
hqspi->TxXferCount--;
}
@@ -1054,8 +1045,8 @@
/**
* @brief Receive an amount of data in blocking mode.
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer
+ * @param hqspi : QSPI handle
+ * @param pData : pointer to data buffer
* @param Timeout : Timeout duration
* @note This function is used only in Indirect Read Mode
* @retval HAL status
@@ -1100,7 +1091,7 @@
break;
}
- *hqspi->pRxBuffPtr = *(__IO uint8_t *)data_reg;
+ *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
hqspi->pRxBuffPtr++;
hqspi->RxXferCount--;
}
@@ -1114,6 +1105,7 @@
{
/* Clear Transfer Complete bit */
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
}
}
@@ -1139,8 +1131,8 @@
/**
* @brief Send an amount of data in non-blocking mode with interrupt.
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer
+ * @param hqspi : QSPI handle
+ * @param pData : pointer to data buffer
* @note This function is used only in Indirect Write Mode
* @retval HAL status
*/
@@ -1199,8 +1191,8 @@
/**
* @brief Receive an amount of data in non-blocking mode with interrupt.
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer
+ * @param hqspi : QSPI handle
+ * @param pData : pointer to data buffer
* @note This function is used only in Indirect Read Mode
* @retval HAL status
*/
@@ -1263,18 +1255,15 @@
/**
* @brief Send an amount of data in non-blocking mode with DMA.
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer
+ * @param hqspi : QSPI handle
+ * @param pData : pointer to data buffer
* @note This function is used only in Indirect Write Mode
- * @note If MDMA peripheral access is configured as halfword, the number
- * of data and the fifo threshold should be aligned on halfword
- * @note If MDMA peripheral access is configured as word, the number
- * of data and the fifo threshold should be aligned on word
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
{
HAL_StatusTypeDef status = HAL_OK;
+ uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
/* Process locked */
__HAL_LOCK(hqspi);
@@ -1286,64 +1275,75 @@
if(pData != NULL )
{
+ /* Configure counters of the handle */
+ hqspi->TxXferCount = data_size;
- /* Update state */
- hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
- /* Clear interrupt */
- __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
+ /* Clear interrupt */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
- /* Configure counters and size of the handle */
- hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
- hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
- hqspi->pTxBuffPtr = pData;
+ /* Configure size and pointer of the handle */
+ hqspi->TxXferSize = hqspi->TxXferCount;
+ hqspi->pTxBuffPtr = pData;
- /* Configure QSPI: CCR register with functional mode as indirect write */
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+ /* Configure QSPI: CCR register with functional mode as indirect write */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
- /* Set the QSPI MDMA transfer complete callback */
- hqspi->hmdma->XferCpltCallback = QSPI_DMATxCplt;
+ /* Set the QSPI MDMA transfer complete callback */
+ hqspi->hmdma->XferCpltCallback = QSPI_DMATxCplt;
- /* Set the MDMA error callback */
- hqspi->hmdma->XferErrorCallback = QSPI_DMAError;
+ /* Set the MDMA error callback */
+ hqspi->hmdma->XferErrorCallback = QSPI_DMAError;
- /* Clear the MDMA abort callback */
- hqspi->hmdma->XferAbortCallback = NULL;
-
- /* In Transmit mode , the MDMA destination is the QSPI DR register : Force the MDMA Destination Increment to disable */
- MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) ,MDMA_DEST_INC_DISABLE);
-
- /* Update MDMA configuration with the correct SourceInc field for Write operation */
- if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_BYTE)
- {
- MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_BYTE);
- }
- else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_HALFWORD)
- {
- MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_HALFWORD);
- }
- else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_WORD)
- {
- MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_WORD);
- }
- else
- {
- /* in case of incorrect source data size */
- hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
- status = HAL_ERROR;
- }
+ /* Clear the MDMA abort callback */
+ hqspi->hmdma->XferAbortCallback = NULL;
- /* Enable the QSPI transfer error and complete Interrupts : Workaround for QSPI low kernel clock frequency */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE |QSPI_IT_TC);
-
- /* Enable the QSPI transmit MDMA */
- if(HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize, 1) == HAL_OK)
- {
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
+ /* In Transmit mode , the MDMA destination is the QSPI DR register : Force the MDMA Destination Increment to disable */
+ MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) ,MDMA_DEST_INC_DISABLE);
- /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
- }
+ /* Update MDMA configuration with the correct SourceInc field for Write operation */
+ if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_BYTE)
+ {
+ MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_BYTE);
+ }
+ else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_HALFWORD)
+ {
+ MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_HALFWORD);
+ }
+ else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_WORD)
+ {
+ MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_WORD);
+ }
+ else
+ {
+ /* in case of incorrect source data size */
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+ status = HAL_ERROR;
+ }
+
+ /* Enable the QSPI transmit MDMA */
+ if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize, 1) == HAL_OK)
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Enable the QSPI transfer error Interrupt */
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
+
+ /* Enable the MDMA transfer by setting the DMAEN bit in the QSPI CR register */
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+ hqspi->State = HAL_QSPI_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+ }
}
else
{
@@ -1367,8 +1367,8 @@
/**
* @brief Receive an amount of data in non-blocking mode with DMA.
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer.
+ * @param hqspi : QSPI handle
+ * @param pData : pointer to data buffer.
* @note This function is used only in Indirect Read Mode
* @retval HAL status
*/
@@ -1376,6 +1376,7 @@
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
+ uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
/* Process locked */
__HAL_LOCK(hqspi);
@@ -1387,39 +1388,30 @@
if(pData != NULL )
{
+ /* Configure counters of the handle */
+ hqspi->RxXferCount = data_size;
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
- /* Update state */
- hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
+ /* Clear interrupt */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
- /* Clear interrupt */
- __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
+ /* Configure size and pointer of the handle */
+ hqspi->RxXferSize = hqspi->RxXferCount;
+ hqspi->pRxBuffPtr = pData;
- /* Configure counters and size of the handle */
- hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
- hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
- hqspi->pRxBuffPtr = pData;
+ /* Set the QSPI MDMA transfer complete callback */
+ hqspi->hmdma->XferCpltCallback = QSPI_DMARxCplt;
- /* Set the QSPI DMA transfer complete callback */
- hqspi->hmdma->XferCpltCallback = QSPI_DMARxCplt;
+ /* Set the MDMA error callback */
+ hqspi->hmdma->XferErrorCallback = QSPI_DMAError;
- /* Set the MDMA error callback */
- hqspi->hmdma->XferErrorCallback = QSPI_DMAError;
+ /* Clear the MDMA abort callback */
+ hqspi->hmdma->XferAbortCallback = NULL;
- /* Clear the MDMA abort callback */
- hqspi->hmdma->XferAbortCallback = NULL;
-
-
- /* QSPI need to be configured to indirect mode before starting
- the MDMA to avoid primatury triggering for the MDMA transfert */
- /* Configure QSPI: CCR register with functional as indirect read */
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
-
- /* Start the transfer by re-writing the address in AR register */
- WRITE_REG(hqspi->Instance->AR, addr_reg);
-
/* In Receive mode , the MDMA source is the QSPI DR register : Force the MDMA Source Increment to disable */
MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_DISABLE);
-
+
/* Update MDMA configuration with the correct DestinationInc field for read operation */
if (hqspi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_BYTE)
{
@@ -1433,27 +1425,43 @@
{
MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_WORD);
}
- else
+ else
{
/* in case of incorrect destination data size */
hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
status = HAL_ERROR;
- }
-
- /* Enable the MDMA */
- if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize, 1) == HAL_OK)
- {
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Enable the QSPI transfer error Interrupt */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
-
- /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
}
+ /* Configure QSPI: CCR register with functional as indirect read */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+
+ /* Start the transfer by re-writing the address in AR register */
+ WRITE_REG(hqspi->Instance->AR, addr_reg);
+
+ /* Enable the MDMA */
+ if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize, 1) == HAL_OK)
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Enable the QSPI transfer error Interrupt */
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
+
+ /* Enable the MDMA transfer by setting the DMAEN bit in the QSPI CR register */
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+ hqspi->State = HAL_QSPI_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+ }
}
else
{
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
status = HAL_ERROR;
/* Process unlocked */
@@ -1473,9 +1481,9 @@
/**
* @brief Configure the QSPI Automatic Polling Mode in blocking mode.
- * @param hqspi: QSPI handle
- * @param cmd: structure that contains the command configuration information.
- * @param cfg: structure that contains the polling configuration information.
+ * @param hqspi : QSPI handle
+ * @param cmd : structure that contains the command configuration information.
+ * @param cfg : structure that contains the polling configuration information.
* @param Timeout : Timeout duration
* @note This function is used only in Automatic Polling Mode
* @retval HAL status
@@ -1574,9 +1582,9 @@
/**
* @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
- * @param hqspi: QSPI handle
- * @param cmd: structure that contains the command configuration information.
- * @param cfg: structure that contains the polling configuration information.
+ * @param hqspi : QSPI handle
+ * @param cmd : structure that contains the command configuration information.
+ * @param cfg : structure that contains the polling configuration information.
* @note This function is used only in Automatic Polling Mode
* @retval HAL status
*/
@@ -1678,9 +1686,9 @@
/**
* @brief Configure the Memory Mapped mode.
- * @param hqspi: QSPI handle
- * @param cmd: structure that contains the command configuration information.
- * @param cfg: structure that contains the memory mapped configuration information.
+ * @param hqspi : QSPI handle
+ * @param cmd : structure that contains the command configuration information.
+ * @param cfg : structure that contains the memory mapped configuration information.
* @note This function is used only in Memory mapped Mode
* @retval HAL status
*/
@@ -1733,9 +1741,9 @@
if (status == HAL_OK)
{
/* Configure QSPI: CR register with timeout counter enable */
- MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
+ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
- if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
+ if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
{
assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
@@ -1767,7 +1775,7 @@
/**
* @brief Transfer Error callback.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
@@ -1782,7 +1790,7 @@
/**
* @brief Abort completed callback.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1797,7 +1805,7 @@
/**
* @brief Command completed callback.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1812,7 +1820,7 @@
/**
* @brief Rx Transfer completed callback.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1827,10 +1835,10 @@
/**
* @brief Tx Transfer completed callback.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @retval None
*/
- __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
+__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
@@ -1843,7 +1851,7 @@
/**
* @brief FIFO Threshold callback.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
@@ -1858,7 +1866,7 @@
/**
* @brief Status Match callback.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
@@ -1873,7 +1881,7 @@
/**
* @brief Timeout callback.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
@@ -2115,7 +2123,7 @@
/**
* @brief Return the QSPI handle state.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @retval HAL state
*/
HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
@@ -2126,7 +2134,7 @@
/**
* @brief Return the QSPI error code.
-* @param hqspi: QSPI handle
+* @param hqspi : QSPI handle
* @retval QSPI Error Code
*/
uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
@@ -2136,7 +2144,7 @@
/**
* @brief Abort the current transmission.
-* @param hqspi: QSPI handle
+* @param hqspi : QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
@@ -2150,7 +2158,7 @@
/* Process unlocked */
__HAL_UNLOCK(hqspi);
- if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
@@ -2169,7 +2177,7 @@
/* Wait until TC flag is set to go back in idle state */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
- if(status == HAL_OK)
+ if (status == HAL_OK)
{
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
@@ -2179,6 +2187,9 @@
if (status == HAL_OK)
{
+ /* Reset functional mode configuration to indirect write mode by default */
+ CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
+
/* Update state */
hqspi->State = HAL_QSPI_STATE_READY;
}
@@ -2189,7 +2200,7 @@
/**
* @brief Abort the current transmission (non-blocking function)
-* @param hqspi: QSPI handle
+* @param hqspi : QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
@@ -2208,7 +2219,7 @@
/* Disable all interrupts */
__HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));
- if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
@@ -2217,10 +2228,15 @@
hqspi->hmdma->XferAbortCallback = QSPI_DMAAbortCplt;
if (HAL_MDMA_Abort_IT(hqspi->hmdma) != HAL_OK)
{
- /* Set error code to DMA */
- hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+ /* Change state of QSPI */
+ hqspi->State = HAL_QSPI_STATE_READY;
- status = HAL_ERROR;
+ /* Abort Complete callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->AbortCpltCallback(hqspi);
+#else
+ HAL_QSPI_AbortCpltCallback(hqspi);
+#endif
}
}
else
@@ -2239,8 +2255,8 @@
}
/** @brief Set QSPI timeout.
- * @param hqspi: QSPI handle.
- * @param Timeout: Timeout for the QSPI memory access.
+ * @param hqspi : QSPI handle.
+ * @param Timeout : Timeout for the QSPI memory access.
* @retval None
*/
void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
@@ -2249,8 +2265,8 @@
}
/** @brief Set QSPI Fifo threshold.
- * @param hqspi: QSPI handle.
- * @param Threshold: Threshold of the Fifo (value between 1 and 16).
+ * @param hqspi : QSPI handle.
+ * @param Threshold : Threshold of the Fifo (value between 1 and 16).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
@@ -2282,7 +2298,7 @@
}
/** @brief Get QSPI Fifo threshold.
- * @param hqspi: QSPI handle.
+ * @param hqspi : QSPI handle.
* @retval Fifo threshold (value between 1 and 16)
*/
uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
@@ -2332,13 +2348,21 @@
*/
/**
+ * @}
+ */
+
+/** @defgroup QSPI_Private_Functions QSPI Private Functions
+ * @{
+ */
+
+/**
* @brief DMA QSPI receive process complete callback.
- * @param hmdma: MDMA handle
+ * @param hmdma : MDMA handle
* @retval None
*/
static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma)
{
- QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
+ QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hmdma->Parent);
hqspi->RxXferCount = 0U;
/* Enable the QSPI transfer complete Interrupt */
@@ -2347,12 +2371,12 @@
/**
* @brief DMA QSPI transmit process complete callback.
- * @param hmdma: MDMA handle
+ * @param hmdma : MDMA handle
* @retval None
*/
static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma)
{
- QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
+ QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hmdma->Parent);
hqspi->TxXferCount = 0U;
/* Enable the QSPI transfer complete Interrupt */
@@ -2361,12 +2385,12 @@
/**
* @brief DMA QSPI communication error callback.
- * @param hmdma: MDMA handle
+ * @param hmdma : MDMA handle
* @retval None
*/
static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma)
{
- QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
+ QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hmdma->Parent);
hqspi->RxXferCount = 0U;
hqspi->TxXferCount = 0U;
@@ -2382,12 +2406,12 @@
/**
* @brief MDMA QSPI abort complete callback.
- * @param hmdma: MDMA handle
+ * @param hmdma : MDMA handle
* @retval None
*/
static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma)
{
- QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
+ QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hmdma->Parent);
hqspi->RxXferCount = 0U;
hqspi->TxXferCount = 0U;
@@ -2418,13 +2442,14 @@
#endif
}
}
+
/**
* @brief Wait for a flag state until timeout.
- * @param hqspi: QSPI handle
- * @param Flag: Flag checked
- * @param State: Value of the flag expected
- * @param Tickstart: Tick start value
- * @param Timeout: Duration of the timeout
+ * @param hqspi : QSPI handle
+ * @param Flag : Flag checked
+ * @param State : Value of the flag expected
+ * @param Tickstart : Tick start value
+ * @param Timeout : Duration of the timeout
* @retval HAL status
*/
static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
@@ -2450,9 +2475,9 @@
/**
* @brief Configure the communication registers.
- * @param hqspi: QSPI handle
- * @param cmd: structure that contains the command configuration information
- * @param FunctionalMode: functional mode to configured
+ * @param hqspi : QSPI handle
+ * @param cmd : structure that contains the command configuration information
+ * @param FunctionalMode : functional mode to configured
* This parameter can be one of the following values:
* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
@@ -2606,16 +2631,15 @@
* @}
*/
-/**
- * @}
- */
-
-#endif /* QUADSPI */
-
#endif /* HAL_QSPI_MODULE_ENABLED */
+/**
+ * @}
+ */
/**
* @}
*/
+#endif /* defined(QUADSPI) */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_rcc.c b/Src/stm32h7xx_hal_rcc.c
index 5be9eb1..17c241b 100644
--- a/Src/stm32h7xx_hal_rcc.c
+++ b/Src/stm32h7xx_hal_rcc.c
@@ -228,8 +228,9 @@
/* Reset CFGR register */
CLEAR_REG(RCC->CFGR);
- /* Update the SystemCoreClock global variable */
+ /* Update the SystemCoreClock and SystemD2Clock global variables */
SystemCoreClock = HSI_VALUE;
+ SystemD2Clock = HSI_VALUE;
/* Adapt Systick interrupt period */
if(HAL_InitTick(uwTickPrio) != HAL_OK)
@@ -859,7 +860,7 @@
* contains the configuration information for the RCC peripheral.
* @param FLatency: FLASH Latency, this parameter depend on device selected
*
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+ * @note The SystemCoreClock CMSIS variable is used to store System Core Clock Frequency
* and updated by HAL_InitTick() function called within this function
*
* @note The HSI is used (enabled by hardware) as system clock source after
@@ -882,6 +883,7 @@
{
HAL_StatusTypeDef halstatus;
uint32_t tickstart;
+ uint32_t common_system_clock;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
@@ -1174,10 +1176,23 @@
/* Update the SystemCoreClock global variable */
#if defined(RCC_D1CFGR_D1CPRE)
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
+ common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
#else
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
+ common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
#endif
+
+#if defined(RCC_D1CFGR_HPRE)
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+#else
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+ SystemCoreClock = SystemD2Clock;
+#else
+ SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+
/* Configure the source of time base considering new system clocks settings*/
halstatus = HAL_InitTick (uwTickPrio);
@@ -1429,11 +1444,26 @@
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
-#if defined(RCC_D1CFGR_HPRE)
- SystemD2Clock = (HAL_RCCEx_GetD1SysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+uint32_t common_system_clock;
+
+#if defined(RCC_D1CFGR_D1CPRE)
+ common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
#else
- SystemD2Clock = (HAL_RCCEx_GetD1SysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+ common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
#endif
+
+#if defined(RCC_D1CFGR_HPRE)
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+#else
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+ SystemCoreClock = SystemD2Clock;
+#else
+ SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+
return SystemD2Clock;
}
@@ -1451,7 +1481,7 @@
return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)>> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU));
#else
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq() >> D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)>> POSITION_VAL(RCC_CDCFGR2_CDPPRE1_0)]);
+ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)>> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU));
#endif
}
diff --git a/Src/stm32h7xx_hal_rcc_ex.c b/Src/stm32h7xx_hal_rcc_ex.c
index e8cfbf2..22c9e94 100644
--- a/Src/stm32h7xx_hal_rcc_ex.c
+++ b/Src/stm32h7xx_hal_rcc_ex.c
@@ -2635,21 +2635,37 @@
}
/**
- * @brief Returns the main Core frequency
- * @note Each time core clock changes, this function must be called to update the
- * right system core clock value. Otherwise, any configuration based on this function will be incorrect.
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+ * @brief Returns the main System frequency
+ * @note Each time System clock changes, this function must be called to update the
+ * right core clock value. Otherwise, any configuration based on this function will be incorrect.
+ * @note The SystemCoreClock CMSIS variable is used to store System current Core Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCCEx_GetD1SysClockFreq(void)
{
+uint32_t common_system_clock;
+
#if defined(RCC_D1CFGR_D1CPRE)
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
+ common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
#else
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
+ common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
#endif
- return SystemCoreClock;
+
+ /* Update the SystemD2Clock global variable */
+#if defined(RCC_D1CFGR_HPRE)
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+#else
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+ SystemCoreClock = SystemD2Clock;
+#else
+ SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+
+ return common_system_clock;
}
/**
* @}
@@ -2684,6 +2700,28 @@
}
/**
+ * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
+ * @note LSE Clock Security System Interrupt is mapped on EXTI line 18
+ * @retval None
+ */
+void HAL_RCCEx_EnableLSECSS_IT(void)
+{
+ /* Enable LSE CSS */
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+
+ /* Enable LSE CSS IT */
+ __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
+
+ /* Enable IT on EXTI Line 18 */
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+ __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT();
+#else
+ __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
+#endif /* DUAL_CORE && CORE_CM4 */
+ __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
+}
+
+/**
* @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock
* @param WakeUpClk: Wakeup clock
* This parameter can be one of the following values:
@@ -3352,6 +3390,38 @@
}
/**
+ * @brief Handle the RCC LSE Clock Security System interrupt request.
+ * @retval None
+ */
+void HAL_RCCEx_LSECSS_IRQHandler(void)
+{
+ /* Check RCC LSE CSSF flag */
+ if(__HAL_RCC_GET_IT(RCC_IT_LSECSS))
+ {
+
+ /* Clear RCC LSE CSS pending bit */
+ __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
+
+ /* RCC LSE Clock Security System interrupt user callback */
+ HAL_RCCEx_LSECSS_Callback();
+
+ }
+}
+
+/**
+ * @brief RCCEx LSE Clock Security System interrupt callback.
+ * @retval none
+ */
+__weak void HAL_RCCEx_LSECSS_Callback(void)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
+ */
+}
+
+
+
+/**
* @}
*/
diff --git a/Src/stm32h7xx_hal_sd.c b/Src/stm32h7xx_hal_sd.c
index 4ba47ad..700660d 100644
--- a/Src/stm32h7xx_hal_sd.c
+++ b/Src/stm32h7xx_hal_sd.c
@@ -464,7 +464,6 @@
HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
{
uint32_t errorstate;
- HAL_StatusTypeDef status;
SD_InitTypeDef Init;
uint32_t sdmmc_clk;
@@ -475,27 +474,22 @@
Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
Init.ClockDiv = SDMMC_INIT_CLK_DIV;
-#if (USE_SD_TRANSCEIVER != 0U) || defined (USE_SD_DIRPOL)
+#if (USE_SD_TRANSCEIVER != 0U)
if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
{
/* Set Transceiver polarity */
hsd->Instance->POWER |= SDMMC_POWER_DIRPOL;
}
+#elif defined (USE_SD_DIRPOL)
+ /* Set Transceiver polarity */
+ hsd->Instance->POWER |= SDMMC_POWER_DIRPOL;
#endif /* USE_SD_TRANSCEIVER */
/* Initialize SDMMC peripheral interface with default configuration */
- status = SDMMC_Init(hsd->Instance, Init);
- if(status != HAL_OK)
- {
- return HAL_ERROR;
- }
+ (void)SDMMC_Init(hsd->Instance, Init);
/* Set Power State to ON */
- status = SDMMC_PowerState_ON(hsd->Instance);
- if(status != HAL_OK)
- {
- return HAL_ERROR;
- }
+ (void)SDMMC_PowerState_ON(hsd->Instance);
/* wait 74 Cycles: required power up waiting time before starting
the SD initialization sequence */
@@ -528,6 +522,17 @@
return HAL_ERROR;
}
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
return HAL_OK;
}
@@ -684,17 +689,6 @@
add *= 512U;
}
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = NumberOfBlocks * BLOCKSIZE;
@@ -877,17 +871,6 @@
add *= 512U;
}
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = NumberOfBlocks * BLOCKSIZE;
@@ -1071,17 +1054,6 @@
add *= 512U;
}
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
@@ -1175,17 +1147,6 @@
add *= 512U;
}
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
@@ -1281,17 +1242,6 @@
add *= 512U;
}
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
@@ -1390,16 +1340,6 @@
add *= 512U;
}
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
@@ -2342,6 +2282,7 @@
{
uint32_t sd_status[16];
uint32_t errorstate;
+ HAL_StatusTypeDef status = HAL_OK;
errorstate = SD_SendSDStatus(hsd, sd_status);
if(errorstate != HAL_SD_ERROR_NONE)
@@ -2350,7 +2291,7 @@
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
+ status = HAL_ERROR;
}
else
{
@@ -2380,7 +2321,18 @@
pStatus->VideoSpeedClass = (uint8_t)((sd_status[4] & 0xFF000000U) >> 24U);
}
- return HAL_OK;
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode = errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ status = HAL_ERROR;
+ }
+
+ return status;
}
/**
@@ -2419,6 +2371,7 @@
{
SDMMC_InitTypeDef Init;
uint32_t errorstate;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_SDMMC_BUS_WIDE(WideMode));
@@ -2460,8 +2413,7 @@
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
+ status = HAL_ERROR;
}
else
{
@@ -2495,10 +2447,20 @@
(void)SDMMC_Init(hsd->Instance, Init);
}
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ status = HAL_ERROR;
+ }
+
/* Change State */
hsd->State = HAL_SD_STATE_READY;
- return HAL_OK;
+ return status;
}
/**
@@ -2516,6 +2478,7 @@
HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t SpeedMode)
{
uint32_t tickstart;
+ uint32_t errorstate;
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
@@ -2743,6 +2706,16 @@
}
}
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ status = HAL_ERROR;
+ }
+
/* Change State */
hsd->State = HAL_SD_STATE_READY;
return status;
@@ -3548,7 +3521,7 @@
{
/* Initialize the Data control register */
hsd->Instance->DCTRL = 0;
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64);
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
if (errorstate != HAL_SD_ERROR_NONE)
{
@@ -3557,16 +3530,13 @@
/* Configure the SD DPSM (Data Path State Machine) */
sdmmc_datainitstructure.DataTimeOut = SDMMC_DATATIMEOUT;
- sdmmc_datainitstructure.DataLength = 64;
+ sdmmc_datainitstructure.DataLength = 64U;
sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;
- if ( SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK)
- {
- return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
- }
+ (void)SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure);
errorstate = SDMMC_CmdSwitch(hsd->Instance,SDMMC_SDR25_SWITCH_PATTERN);
@@ -3662,7 +3632,7 @@
{
/* Initialize the Data control register */
hsd->Instance->DCTRL = 0;
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64);
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
if (errorstate != HAL_SD_ERROR_NONE)
{
@@ -3671,7 +3641,7 @@
/* Configure the SD DPSM (Data Path State Machine) */
sdmmc_datainitstructure.DataTimeOut = SDMMC_DATATIMEOUT;
- sdmmc_datainitstructure.DataLength = 64;
+ sdmmc_datainitstructure.DataLength = 64U;
sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
@@ -3790,7 +3760,7 @@
{
/* Initialize the Data control register */
hsd->Instance->DCTRL = 0;
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64);
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
if (errorstate != HAL_SD_ERROR_NONE)
{
@@ -3799,7 +3769,7 @@
/* Configure the SD DPSM (Data Path State Machine) */
sdmmc_datainitstructure.DataTimeOut = SDMMC_DATATIMEOUT;
- sdmmc_datainitstructure.DataLength = 64;
+ sdmmc_datainitstructure.DataLength = 64U;
sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
diff --git a/Src/stm32h7xx_hal_sd_ex.c b/Src/stm32h7xx_hal_sd_ex.c
index cc78447..7c4da99 100644
--- a/Src/stm32h7xx_hal_sd_ex.c
+++ b/Src/stm32h7xx_hal_sd_ex.c
@@ -139,17 +139,6 @@
add *= 512U;
}
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
@@ -231,17 +220,6 @@
add *= 512U;
}
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
diff --git a/Src/stm32h7xx_hal_tim.c b/Src/stm32h7xx_hal_tim.c
index 4e45001..f1165b4 100644
--- a/Src/stm32h7xx_hal_tim.c
+++ b/Src/stm32h7xx_hal_tim.c
@@ -2617,10 +2617,10 @@
}
/* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
@@ -2783,7 +2783,7 @@
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Enable the encoder interface channels */
switch (Channel)
@@ -2827,7 +2827,7 @@
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
@@ -2873,7 +2873,7 @@
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Enable the encoder interface channels */
/* Enable the capture compare Interrupts 1 and/or 2 */
@@ -2923,7 +2923,7 @@
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
@@ -2978,7 +2978,7 @@
uint32_t *pData2, uint16_t Length)
{
/* Check the parameters */
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
if (htim->State == HAL_TIM_STATE_BUSY)
{
@@ -3112,7 +3112,7 @@
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
diff --git a/Src/stm32h7xx_hal_usart.c b/Src/stm32h7xx_hal_usart.c
index 0458da4..8f9d2b6 100644
--- a/Src/stm32h7xx_hal_usart.c
+++ b/Src/stm32h7xx_hal_usart.c
@@ -317,7 +317,8 @@
/* In Synchronous mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register
- - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
+ - HDSEL, SCEN and IREN bits in the USART_CR3 register.
+ */
husart->Instance->CR2 &= ~USART_CR2_LINEN;
husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
@@ -2091,7 +2092,7 @@
uint32_t errorcode;
/* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_UDR));
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF | USART_ISR_UDR));
if (errorflags == 0U)
{
/* USART in mode Receiver ---------------------------------------------------*/
@@ -2146,6 +2147,14 @@
husart->ErrorCode |= HAL_USART_ERROR_ORE;
}
+ /* USART Receiver Timeout interrupt occurred ---------------------------------*/
+ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(husart, UART_CLEAR_RTOF);
+
+ husart->ErrorCode |= HAL_USART_ERROR_RTO;
+ }
+
/* USART SPI slave underrun error interrupt occurred -------------------------*/
if (((isrflags & USART_ISR_UDR) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
{
diff --git a/Src/stm32h7xx_hal_usart_ex.c b/Src/stm32h7xx_hal_usart_ex.c
index 5a2f54e..f38b03d 100644
--- a/Src/stm32h7xx_hal_usart_ex.c
+++ b/Src/stm32h7xx_hal_usart_ex.c
@@ -57,10 +57,10 @@
/** @defgroup USARTEx_Private_Constants USARTEx Private Constants
* @{
*/
-/* UART RX FIFO depth */
+/* USART RX FIFO depth */
#define RX_FIFO_DEPTH 8U
-/* UART TX FIFO depth */
+/* USART TX FIFO depth */
#define TX_FIFO_DEPTH 8U
/**
* @}
@@ -243,7 +243,7 @@
/* Restore USART configuration */
WRITE_REG(husart->Instance->CR1, tmpcr1);
- husart->SlaveMode = USART_SLAVEMODE_ENABLE;
+ husart->SlaveMode = USART_SLAVEMODE_DISABLE;
husart->State = HAL_USART_STATE_READY;
diff --git a/Src/stm32h7xx_ll_fmc.c b/Src/stm32h7xx_ll_fmc.c
index 9271b02..320fcf0 100644
--- a/Src/stm32h7xx_ll_fmc.c
+++ b/Src/stm32h7xx_ll_fmc.c
@@ -194,6 +194,8 @@
HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init)
{
uint32_t flashaccess;
+ uint32_t btcr_reg;
+ uint32_t mask;
/* Check the parameters */
assert_param(IS_FMC_NORSRAM_DEVICE(Device));
@@ -226,38 +228,42 @@
flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE;
}
- MODIFY_REG(Device->BTCR[Init->NSBank],
- (FMC_BCRx_MBKEN |
- FMC_BCRx_MUXEN |
- FMC_BCRx_MTYP |
- FMC_BCRx_MWID |
- FMC_BCRx_FACCEN |
- FMC_BCRx_BURSTEN |
- FMC_BCRx_WAITPOL |
- FMC_BCRx_WAITCFG |
- FMC_BCRx_WREN |
- FMC_BCRx_WAITEN |
- FMC_BCRx_EXTMOD |
- FMC_BCRx_ASYNCWAIT |
- FMC_BCRx_CBURSTRW |
- FMC_BCR1_CCLKEN |
- FMC_BCR1_WFDIS |
- FMC_BCRx_CPSIZE),
- (flashaccess |
- Init->DataAddressMux |
- Init->MemoryType |
- Init->MemoryDataWidth |
- Init->BurstAccessMode |
- Init->WaitSignalPolarity |
- Init->WaitSignalActive |
- Init->WriteOperation |
- Init->WaitSignal |
- Init->ExtendedMode |
- Init->AsynchronousWait |
- Init->WriteBurst |
- Init->ContinuousClock |
- Init->WriteFifo |
- Init->PageSize));
+ btcr_reg = (flashaccess | \
+ Init->DataAddressMux | \
+ Init->MemoryType | \
+ Init->MemoryDataWidth | \
+ Init->BurstAccessMode | \
+ Init->WaitSignalPolarity | \
+ Init->WaitSignalActive | \
+ Init->WriteOperation | \
+ Init->WaitSignal | \
+ Init->ExtendedMode | \
+ Init->AsynchronousWait | \
+ Init->WriteBurst);
+
+ btcr_reg |= Init->ContinuousClock;
+ btcr_reg |= Init->WriteFifo;
+ btcr_reg |= Init->PageSize;
+
+ mask = (FMC_BCRx_MBKEN |
+ FMC_BCRx_MUXEN |
+ FMC_BCRx_MTYP |
+ FMC_BCRx_MWID |
+ FMC_BCRx_FACCEN |
+ FMC_BCRx_BURSTEN |
+ FMC_BCRx_WAITPOL |
+ FMC_BCRx_WAITCFG |
+ FMC_BCRx_WREN |
+ FMC_BCRx_WAITEN |
+ FMC_BCRx_EXTMOD |
+ FMC_BCRx_ASYNCWAIT |
+ FMC_BCRx_CBURSTRW);
+
+ mask |= FMC_BCR1_CCLKEN;
+ mask |= FMC_BCR1_WFDIS;
+ mask |= FMC_BCRx_CPSIZE;
+
+ MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
/* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
@@ -556,6 +562,9 @@
assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
assert_param(IS_FMC_NAND_BANK(Bank));
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ UNUSED(Bank);
+
/* NAND bank 3 registers configuration */
MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime |
((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) |
@@ -583,6 +592,9 @@
assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
assert_param(IS_FMC_NAND_BANK(Bank));
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ UNUSED(Bank);
+
/* NAND bank 3 registers configuration */
MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime |
((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) |
@@ -608,6 +620,9 @@
__FMC_NAND_DISABLE(Device, Bank);
/* De-initialize the NAND Bank */
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ UNUSED(Bank);
+
/* Set the FMC_NAND_BANK3 registers to their reset values */
WRITE_REG(Device->PCR, 0x00000018U);
WRITE_REG(Device->SR, 0x00000040U);
@@ -650,6 +665,9 @@
assert_param(IS_FMC_NAND_BANK(Bank));
/* Enable ECC feature */
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ UNUSED(Bank);
+
SET_BIT(Device->PCR, FMC_PCR_ECCEN);
return HAL_OK;
@@ -669,6 +687,9 @@
assert_param(IS_FMC_NAND_BANK(Bank));
/* Disable ECC feature */
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ UNUSED(Bank);
+
CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);
return HAL_OK;
@@ -706,6 +727,9 @@
}
}
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ UNUSED(Bank);
+
/* Get the ECCR register value */
*ECCval = (uint32_t)Device->ECCR;
diff --git a/Src/stm32h7xx_ll_gpio.c b/Src/stm32h7xx_ll_gpio.c
index 6a7b9c8..5a809db 100644
--- a/Src/stm32h7xx_ll_gpio.c
+++ b/Src/stm32h7xx_ll_gpio.c
@@ -220,8 +220,6 @@
if (currentpin != 0x00000000U)
{
- /* Pin Mode configuration */
- LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
{
@@ -230,6 +228,13 @@
/* Speed mode configuration */
LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
+
+ /* Check Output mode parameters */
+ assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
+
+ /* Output mode configuration*/
+ LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
+
}
/* Pull-up Pull down resistor configuration*/
@@ -240,7 +245,7 @@
/* Check Alternate parameter */
assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
- /* Speed mode configuration */
+ /* Alternate function configuration */
if (currentpin < LL_GPIO_PIN_8)
{
LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
@@ -250,19 +255,13 @@
LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
}
}
+
+ /* Pin Mode configuration */
+ LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
}
pinpos++;
}
- if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
- {
- /* Check Output mode parameters */
- assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
-
- /* Output mode configuration*/
- LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
-
- }
return (SUCCESS);
}
diff --git a/Src/stm32h7xx_ll_lptim.c b/Src/stm32h7xx_ll_lptim.c
index 139764c..ff1ee65 100644
--- a/Src/stm32h7xx_ll_lptim.c
+++ b/Src/stm32h7xx_ll_lptim.c
@@ -226,25 +226,25 @@
/* Save LPTIM source clock */
switch ((uint32_t)LPTIMx)
{
- case LPTIM1_BASE:
- tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
- break;
- case LPTIM2_BASE:
- tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE);
- break;
+ case LPTIM1_BASE:
+ tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
+ break;
+ case LPTIM2_BASE:
+ tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE);
+ break;
#if defined(LPTIM3)&&defined(LPTIM4)&&defined(LPTIM5)
- case LPTIM3_BASE:
- case LPTIM4_BASE:
- case LPTIM5_BASE:
- tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM345_CLKSOURCE);
- break;
+ case LPTIM3_BASE:
+ case LPTIM4_BASE:
+ case LPTIM5_BASE:
+ tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM345_CLKSOURCE);
+ break;
#elif defined(LPTIM3)
- case LPTIM3_BASE:
- tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE);
- break;
+ case LPTIM3_BASE:
+ tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE);
+ break;
#endif /* LPTIM3 && LPTIM4 && LPTIM5 */
- default:
- break;
+ default:
+ break;
}
/* Save LPTIM configuration registers */
@@ -265,25 +265,25 @@
/* Force LPTIM source kernel clock from APB */
switch ((uint32_t)LPTIMx)
{
- case LPTIM1_BASE:
- LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1);
- break;
- case LPTIM2_BASE:
- LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE_PCLK4);
- break;
+ case LPTIM1_BASE:
+ LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1);
+ break;
+ case LPTIM2_BASE:
+ LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE_PCLK4);
+ break;
#if defined(LPTIM3)&&defined(LPTIM4)&&defined(LPTIM5)
- case LPTIM3_BASE:
- case LPTIM4_BASE:
- case LPTIM5_BASE:
- LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM345_CLKSOURCE_PCLK4);
- break;
+ case LPTIM3_BASE:
+ case LPTIM4_BASE:
+ case LPTIM5_BASE:
+ LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM345_CLKSOURCE_PCLK4);
+ break;
#elif defined(LPTIM3)
- case LPTIM3_BASE:
- LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE_PCLK4);
- break;
+ case LPTIM3_BASE:
+ LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE_PCLK4);
+ break;
#endif /* LPTIM3 && LPTIM4 && LPTIM5*/
- default:
- break;
+ default:
+ break;
}
if (tmpCMP != 0UL)
@@ -296,7 +296,8 @@
do
{
rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
- } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
+ }
+ while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
LL_LPTIM_ClearFlag_CMPOK(LPTIMx);
}
@@ -311,7 +312,8 @@
do
{
rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
- } while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
+ }
+ while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
LL_LPTIM_ClearFlag_ARROK(LPTIMx);
}
diff --git a/Src/stm32h7xx_ll_tim.c b/Src/stm32h7xx_ll_tim.c
index 30e3be7..a11ca83 100644
--- a/Src/stm32h7xx_ll_tim.c
+++ b/Src/stm32h7xx_ll_tim.c
@@ -338,7 +338,7 @@
TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
- TIM_InitStruct->RepetitionCounter = (uint8_t)0x00;
+ TIM_InitStruct->RepetitionCounter = 0x00000000U;
}
/**
diff --git a/Src/stm32h7xx_ll_utils.c b/Src/stm32h7xx_ll_utils.c
index a4836fd..a039e79 100644
--- a/Src/stm32h7xx_ll_utils.c
+++ b/Src/stm32h7xx_ll_utils.c
@@ -224,8 +224,6 @@
* @{
*/
static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
-static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t *latency);
-static ErrorStatus UTILS_SetFlashLatency(uint32_t latency);
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
static ErrorStatus UTILS_IsPLLsReady(void);
/**
@@ -341,7 +339,7 @@
(++) +----------------------------------------------------------------------------+
#else
- (+) The maximum frequency of the SYSCLK is 280 MHz and HCLK is 140 MHz.
+ (+) The maximum frequency of the SYSCLK is 280 MHz and HCLK is 280 MHz.
(+) The maximum frequency of the PCLK1, PCLK2, PCLK3 and PCLK4 is 140 MHz.
@endverbatim
@internal
@@ -399,14 +397,6 @@
{
/* HCLK clock frequency */
SystemCoreClock = CPU_Frequency;
-
- /* Update the SystemD2Clock global variable */
-#if defined(RCC_D1CFGR_HPRE)
- SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
-#else
- SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
-#endif
-
}
/**
@@ -505,7 +495,7 @@
* @note Function is based on the following formula:
* - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP)
* - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSE frequency / PLLM)
- * - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz (PLLVCO_output = PLLVCO_input * PLLN)
+ * - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz or 128 to 560 MHz(*) (PLLVCO_output = PLLVCO_input * PLLN)
* - PLLP: ensure that max frequency at 400000000 Hz or 280000000 Hz(*) is reached (PLLVCO_output / PLLP)
* @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000
* @param HSEBypass This parameter can be one of the following values:
@@ -609,36 +599,24 @@
*/
/**
- * @}
- */
-
-/** @addtogroup UTILS_LL_Private_Functions
- * @{
- */
-
-/**
- * @brief Calculate and check the Flash wait states number according to the
- new HCLK frequency and current voltage range.
+ * @brief Update number of Flash wait states in line with new frequency and current
+ voltage range.
* @param HCLK_Frequency HCLK frequency
- * @param latency This parameter can be one of the following values:
- * @arg @ref LL_FLASH_LATENCY_0
- * @arg @ref LL_FLASH_LATENCY_1
- * @arg @ref LL_FLASH_LATENCY_2
- * @arg @ref LL_FLASH_LATENCY_3
- * @arg @ref LL_FLASH_LATENCY_4
- * @arg @ref LL_FLASH_LATENCY_5
- * @arg @ref LL_FLASH_LATENCY_6
- * @arg @ref LL_FLASH_LATENCY_7
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Latency has been modified
* - ERROR: Latency cannot be modified
*/
-static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t *latency)
+ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency)
{
ErrorStatus status = SUCCESS;
+ uint32_t timeout;
+ uint32_t getlatency;
+ uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
+
+
/* Frequency cannot be equal to 0 */
- if(HCLK_Frequency == 0U)
+ if (HCLK_Frequency == 0U)
{
status = ERROR;
}
@@ -650,37 +628,36 @@
if((HCLK_Frequency > UTILS_SCALE0_LATENCY5_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY6_FREQ))
{
/* 264 < HCLK <= 280 => 6WS (7 CPU cycles) */
- *latency = LL_FLASH_LATENCY_6;
+ latency = LL_FLASH_LATENCY_6;
}
else if((HCLK_Frequency > UTILS_SCALE0_LATENCY4_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY5_FREQ))
{
/* 220 < HCLK <= 264 => 5WS (6 CPU cycles) */
- *latency = LL_FLASH_LATENCY_5;
+ latency = LL_FLASH_LATENCY_5;
}
else if((HCLK_Frequency > UTILS_SCALE0_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY4_FREQ))
{
/* 176 < HCLK <= 220 => 4WS (5 CPU cycles) */
- *latency = LL_FLASH_LATENCY_4;
+ latency = LL_FLASH_LATENCY_4;
}
else if((HCLK_Frequency > UTILS_SCALE0_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY3_FREQ))
{
/* 132 < HCLK <= 176 => 3WS (4 CPU cycles) */
- *latency = LL_FLASH_LATENCY_3;
+ latency = LL_FLASH_LATENCY_3;
}
else if((HCLK_Frequency > UTILS_SCALE0_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY2_FREQ))
{
/* 88 < HCLK <= 132 => 2WS (3 CPU cycles) */
- *latency = LL_FLASH_LATENCY_2;
+ latency = LL_FLASH_LATENCY_2;
}
else if((HCLK_Frequency > UTILS_SCALE0_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY1_FREQ))
{
/* 44 < HCLK <= 88 => 1WS (2 CPU cycles) */
- *latency = LL_FLASH_LATENCY_1;
+ latency = LL_FLASH_LATENCY_1;
}
else if(HCLK_Frequency <= UTILS_SCALE0_LATENCY0_FREQ)
{
- /* HCLK <= 44 => 0WS (1 CPU cycles) */
- *latency = LL_FLASH_LATENCY_0;
+ /* HCLK <= 44 => 0WS (1 CPU cycles) : Do nothing keep latency to default LL_FLASH_LATENCY_0 */
}
else
{
@@ -692,17 +669,17 @@
if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY5_FREQ))
{
/* 210 < HCLK <= 225 => 5WS (6 CPU cycles) */
- *latency = LL_FLASH_LATENCY_5;
+ latency = LL_FLASH_LATENCY_5;
}
else if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY4_FREQ))
{
/* 168 < HCLK <= 210 => 4WS (5 CPU cycles) */
- *latency = LL_FLASH_LATENCY_4;
+ latency = LL_FLASH_LATENCY_4;
}
else if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY3_FREQ))
{
/* 126 < HCLK <= 168 => 3WS (4 CPU cycles) */
- *latency = LL_FLASH_LATENCY_3;
+ latency = LL_FLASH_LATENCY_3;
}
else if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ))
#else
@@ -712,17 +689,16 @@
#endif /*POWER_DOMAINS_NUMBER == 2U*/
{
/* 140 < HCLK <= 210 => 2WS (3 CPU cycles) */
- *latency = LL_FLASH_LATENCY_2;
+ latency = LL_FLASH_LATENCY_2;
}
else if((HCLK_Frequency > UTILS_SCALE1_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY1_FREQ))
{
/* 70 < HCLK <= 140 => 1WS (2 CPU cycles) */
- *latency = LL_FLASH_LATENCY_1;
+ latency = LL_FLASH_LATENCY_1;
}
else if(HCLK_Frequency <= UTILS_SCALE1_LATENCY0_FREQ)
{
- /* HCLK <= 70 => 0WS (1 CPU cycles) */
- *latency = LL_FLASH_LATENCY_0;
+ /* HCLK <= 70 => 0WS (1 CPU cycles) : Do nothing keep latency to default LL_FLASH_LATENCY_0 */
}
else
{
@@ -735,7 +711,7 @@
if((HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY4_FREQ))
{
/* 136 < HCLK <= 160 => 4WS (5 CPU cycles) */
- *latency = LL_FLASH_LATENCY_4;
+ latency = LL_FLASH_LATENCY_4;
}
else if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY3_FREQ))
#else
@@ -743,22 +719,21 @@
#endif /*POWER_DOMAINS_NUMBER == 2U*/
{
/* 165 < HCLK <= 220 => 3WS (4 CPU cycles) */
- *latency = LL_FLASH_LATENCY_3;
+ latency = LL_FLASH_LATENCY_3;
}
else if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY2_FREQ))
{
/* 110 < HCLK <= 165 => 2WS (3 CPU cycles) */
- *latency = LL_FLASH_LATENCY_2;
+ latency = LL_FLASH_LATENCY_2;
}
else if((HCLK_Frequency > UTILS_SCALE2_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY1_FREQ))
{
/* 55 < HCLK <= 110 => 1WS (2 CPU cycles) */
- *latency = LL_FLASH_LATENCY_1;
+ latency = LL_FLASH_LATENCY_1;
}
else if(HCLK_Frequency <= UTILS_SCALE2_LATENCY0_FREQ)
{
- /* HCLK <= 55 => 0WS (1 CPU cycles) */
- *latency = LL_FLASH_LATENCY_0;
+ /* HCLK <= 55 => 0WS (1 CPU cycles) : Do nothing keep latency to default LL_FLASH_LATENCY_0 */
}
else
{
@@ -771,7 +746,7 @@
if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY4_FREQ))
{
/* 180 < HCLK <= 225 => 4WS (5 CPU cycles) */
- *latency = LL_FLASH_LATENCY_4;
+ latency = LL_FLASH_LATENCY_4;
}
else if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY3_FREQ))
#else
@@ -779,55 +754,62 @@
#endif /*POWER_DOMAINS_NUMBER == 3U*/
{
/* 135 < HCLK <= 180 => 3WS (4 CPU cycles) */
- *latency = LL_FLASH_LATENCY_3;
+ latency = LL_FLASH_LATENCY_3;
}
else if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY2_FREQ))
{
/* 90 < HCLK <= 135 => 2WS (3 CPU cycles) */
- *latency = LL_FLASH_LATENCY_2;
+ latency = LL_FLASH_LATENCY_2;
}
else if((HCLK_Frequency > UTILS_SCALE3_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY1_FREQ))
{
/* 45 < HCLK <= 90 => 1WS (2 CPU cycles) */
- *latency = LL_FLASH_LATENCY_1;
+ latency = LL_FLASH_LATENCY_1;
}
else if(HCLK_Frequency <= UTILS_SCALE3_LATENCY0_FREQ)
{
- /* HCLK <= 45 => 0WS (1 CPU cycles) */
- *latency = LL_FLASH_LATENCY_0;
+ /* HCLK <= 45 => 0WS (1 CPU cycles) : Do nothing keep latency to default LL_FLASH_LATENCY_0 */
}
else
{
status = ERROR;
}
}
+
+ if(status == SUCCESS)
+ {
+ LL_FLASH_SetLatency(latency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ timeout = 2;
+ do
+ {
+ /* Wait for Flash latency to be updated */
+ getlatency = LL_FLASH_GetLatency();
+ timeout--;
+ } while ((getlatency != latency) && (timeout > 0U));
+
+ if(getlatency != latency)
+ {
+ status = ERROR;
+ }
+ }
+
}
return status;
}
+
/**
- * @brief Update number of Flash wait states
- * @param latency Flash Latency
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Latency has been modified
- * - ERROR: Latency cannot be modified
+ * @}
*/
-static ErrorStatus UTILS_SetFlashLatency(uint32_t latency)
-{
- ErrorStatus status = SUCCESS;
- LL_FLASH_SetLatency(latency);
+/** @addtogroup UTILS_LL_Private_Functions
+ * @{
+ */
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if(LL_FLASH_GetLatency() != latency)
- {
- status = ERROR;
- }
-
- return status;
-}
/**
* @brief Function to check that PLL can be modified
@@ -896,8 +878,8 @@
*/
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
- ErrorStatus status;
- uint32_t new_hclk_frequency, new_latency;
+ ErrorStatus status = SUCCESS;
+ uint32_t new_hclk_frequency;
assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->SYSCLKDivider));
assert_param(IS_LL_UTILS_AHB_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
@@ -909,63 +891,72 @@
/* Calculate the new HCLK frequency */
new_hclk_frequency = LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
- /* Calculate the new FLASH latency according to the new HCLK frequency */
- status = UTILS_CalculateFlashLatency(new_hclk_frequency, &new_latency);
+ /* Increasing the number of wait states because of higher CPU frequency */
+ if (SystemD2Clock < new_hclk_frequency)
+ {
+ /* Set FLASH latency to highest latency */
+ status = LL_SetFlashLatency(new_hclk_frequency);
+ }
+ /* Update system clock configuration */
if(status == SUCCESS)
{
- /* Increasing the number of wait states because of higher CPU frequency */
- if(LL_FLASH_GetLatency() < new_latency)
+ /* Enable PLL */
+ LL_RCC_PLL1_Enable();
+ while (LL_RCC_PLL1_IsReady() != 1U)
{
- status = UTILS_SetFlashLatency(new_latency);
+ /* Wait for PLL ready */
}
- /* Update system clock configuration */
- if(status == SUCCESS)
+ /* Set All APBxPrescaler to the Highest Divider */
+ LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_16);
+ LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_16);
+ LL_RCC_SetAPB3Prescaler(LL_RCC_APB3_DIV_16);
+ LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_16);
+
+ /* Set SYS prescaler*/
+ LL_RCC_SetSysPrescaler(UTILS_ClkInitStruct->SYSCLKDivider);
+
+ /* Set AHB prescaler*/
+ LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+
+ /* Sysclk activation on the main PLL */
+ LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
+ while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1)
{
- /* Enable PLL */
- LL_RCC_PLL1_Enable();
- while (LL_RCC_PLL1_IsReady() != 1U)
- {
- /* Wait for PLL ready */
- }
-
- /* Set All APBxPrescaler to the Highest Divider */
- LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_16);
- LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_16);
- LL_RCC_SetAPB3Prescaler(LL_RCC_APB3_DIV_16);
- LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_16);
-
- /* Set SYS prescaler*/
- LL_RCC_SetSysPrescaler(UTILS_ClkInitStruct->SYSCLKDivider);
-
- /* Set AHB prescaler*/
- LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
-
- /* Sysclk activation on the main PLL */
- LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
- while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1)
- {
- /* Wait for system clock switch to PLL */
- }
-
- /* Set APBn prescaler*/
- LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
- LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
- LL_RCC_SetAPB3Prescaler(UTILS_ClkInitStruct->APB3CLKDivider);
- LL_RCC_SetAPB4Prescaler(UTILS_ClkInitStruct->APB4CLKDivider);
-
- /* Update SystemCoreClock variable */
- LL_SetSystemCoreClock(SYSCLK_Frequency);
+ /* Wait for system clock switch to PLL */
}
+ /* Set APBn prescaler*/
+ LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
+ LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
+ LL_RCC_SetAPB3Prescaler(UTILS_ClkInitStruct->APB3CLKDivider);
+ LL_RCC_SetAPB4Prescaler(UTILS_ClkInitStruct->APB4CLKDivider);
+
/* Decreasing the number of wait states because of lower CPU frequency */
- if(LL_FLASH_GetLatency() > new_latency)
+ if (SystemD2Clock > new_hclk_frequency)
{
- status = UTILS_SetFlashLatency(new_latency);
+ /* Set FLASH latency to lowest latency */
+ status = LL_SetFlashLatency(new_hclk_frequency);
}
+
+ /* Update the SystemD2Clock global variable */
+#if defined(RCC_D1CFGR_HPRE)
+ SystemD2Clock = (SYSCLK_Frequency >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+#else
+ SystemD2Clock = (SYSCLK_Frequency >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+#endif
+
+ /* Update SystemCoreClock variable */
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+ LL_SetSystemCoreClock(SystemD2Clock);
+#else
+ LL_SetSystemCoreClock(SYSCLK_Frequency);
+#endif /* DUAL_CORE && CORE_CM4 */
+
}
+
return status;
}
