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<h1 id="release-notes-for-stm32h7xx-hal-drivers"><strong>Release Notes for STM32H7xx HAL Drivers</strong></h1>
<p>Copyright © 2017 STMicroelectronics<br />
</p>
<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo.png" alt="ST logo" /></a>
</center>
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<h1 id="license"><strong>License</strong></h1>
This software component is licensed by ST under BSD 3-Clause license, the “License”; You may not use this component except in compliance with the License. You may obtain a copy of the License at:
<center>
<a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a>
</center>
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<h1 id="update-history"><strong>Update History</strong></h1>
<div class="collapse">
<input type="checkbox" id="collapse-section12" checked aria-hidden="true"> <label for="collapse-section12" aria-hidden="true"><strong>V1.9.0 / 29-May-2020</strong></label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
<li>First official release of the STM32CubeH7 Firmware Package supporting <strong>STM32H72x/3x</strong> new devices</li>
<li>General updates to fix known defects and implementation enhancements</li>
<li><strong>HAL</strong>: generic, Update to support <strong>STM32H72x/3x</strong> new devices
<ul>
<li>stm32h7xx_hal.h:
<ul>
<li>Add SYSCGF defines for Adc2 Alternate Connection on Vinp[16] and Vinp[17]</li>
<li>Add HAL_SYSCFG_ADC2ALT_Rout0Config and HAL_SYSCFG_ADC2ALT_Rout1Config APIs allowing to configure Adc2 Alternate Connection on Vinp[16] or Vinp[17]<br />
</li>
<li>Update EXTI lines definitions for <strong>STM32H72x/3x</strong> devices</li>
<li>Add __HAL_DBGMCU_FREEZE_I2C5/__HAL_DBGMCU_UnFreeze_I2C5, __HAL_DBGMCU_FREEZE_TIM23/__HAL_DBGMCU_UnFreeze_TIM23 and __HAL_DBGMCU_FREEZE_TIM24/__HAL_DBGMCU_UnFreeze_TIM24 macros</li>
</ul></li>
<li>stm32h7xx_hal_conf_template.h:
<ul>
<li>Add CORDIC and FMAC modules enabling (new peripherals in STM32H723xx/33xx/25xx/35xx/30xx devices)</li>
<li>Add CORDIC and FMAC register callback enabling</li>
</ul></li>
<li>stm32h7xx_hal.c:
<ul>
<li>Add implementation of HAL_SYSCFG_ADC2ALT_Rout0Config and HAL_SYSCFG_ADC2ALT_Rout1Config APIs implementation allowing to configure Adc2 Alternate Connection on Vinp[16] or Vinp[17]</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL ADC</strong>: Updated to support <strong>STM32H72x/3x</strong> devices: ADC1/2 (16 bits ADCs in D2 domain) and ADC3 (12 Bits ADC in D3 domain)
<ul>
<li>3 compilations defines are used:
<ul>
<li>ADC_VER_V5_V90 : for <strong>STM32H72x/3x</strong> ADCs : ADC1/2 (16 bits ADCs in D2 domain) and ADC3 (12 Bits ADC in D3 domain)</li>
<li>ADC_VER_V5_3: For STM32H7Ax/Bx : ADC1/2 (16 bits ADCs in D2/CDC domain)</li>
<li>ADC_VER_V5_X: For STM32H74x/5x : ADC1/2 (16 bits ADCs in D2/CDC domain) and ADC3 (16 Bits ADC in D3 domain)
<ul>
<li>supporting rev.Y and rev.V devices</li>
</ul></li>
<li>These defines are available on each CMSIS device header file stm32h723xx.h/stm32h733xx.h …/STM32H7a3xx.h/STM32H7b3xx.h/…/stm32h743xx/stm32h773xx…</li>
</ul></li>
</ul></li>
<li><strong>HAL DFSDM</strong>:
<ul>
<li>stm32h7xx_hal_dfsdm.h:
<ul>
<li>Use conditional define on STM32H7_DEV_ID for external triggers definition instead of device RPN definitions (STM32H7_DEV_ID define available on CMSIS device header files for each STM32H7 line : <strong>STM32H72x/3x</strong>/4x/5x/Ax/Bx)</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL DMA</strong>:
<ul>
<li>stm32h7xx_ll_bdma.h, stm32h7xx_ll_dma.h and stm32h7xx_ll_dmamux.h:
<ul>
<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
<li>Add requests definitions for FMAC, CORDIC, I2C5, TIM23 and TIM24 new peripherals available on <strong>STM32H72x/3x</strong> devices</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL CORDIC</strong>:
<ul>
<li>New HAL and LL drivers to support CORDIC peripheral available on new <strong>STM32H72x/3x</strong> new devices</li>
</ul></li>
<li><strong>HAL CRYP</strong>:
<ul>
<li>stm32h7xx_hal_cryp.c/.h and stm32h7xx_hal_cryp_ex.c: Update doxygen documentation</li>
</ul></li>
<li><strong>HAL DCMI</strong>:
<ul>
<li>stm32h7xx_hal_dcmi.c:
<ul>
<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
</ul></li>
</ul></li>
<li><strong>HAL ETH</strong>:
<ul>
<li>stm32h7xx_hal_eth.h:
<ul>
<li><p>Update ETH_DMADescTypeDef definition: remove useless volatile of the BackupAddr0 and BackupAddr1 fields since they are not used by ETH DMA.</p></li>
<li>stm32h7xx_hal_eth.c:
<ul>
<li>HAL_ETH_Start_IT:
<ul>
<li>Move the update of the ETH gState and RxState after ETH IT Start.</li>
<li>Remove useless INCR_RX_DESC_INDEX(descindex, 1U) when enabling Interrupt on Completion fields</li>
</ul></li>
<li>HAL_ETH_Stop_IT:
<ul>
<li>Clear Fatal bus interrupt and Abnormal Interrupt Summary Enable</li>
<li>Clear interrupt Enabled on Completion for all used descriptors</li>
</ul></li>
<li>HAL_ETH_Transmit:
<ul>
<li>Set ETH gState to HAL_ETH_STATE_ERROR when timeout error occurred</li>
<li>Remove unnecessary set of ETH HAL State to Ready</li>
</ul></li>
<li>HAL_ETH_Transmit_IT:
<ul>
<li>Set ETH ErrorCode to HAL_ETH_ERROR_PARAM when parameter is not valid and use logical OR when updating the ErrorCode</li>
</ul></li>
<li>HAL_ETH_IsRxDataAvailable
<ul>
<li>Updating the CurRxDesc and FirstAppDesc values when building descriptor of an invalid/incomplete</li>
</ul></li>
</ul></li>
</ul></li>
</ul></li>
<li><strong>HAL/LL EXTI</strong>: Updated to support <strong>STM32H72x/3x</strong> devices
<ul>
<li>stm32h7xx_hal_exti.h and stm32h7xx_ll_exti.h:
<ul>
<li>Update EXTI lines definition with according to its availability on STM32H74x/5x STM32Ax/Bx or <strong>STM32H72x/3x</strong> devices</li>
</ul></li>
</ul></li>
<li><strong>HAL FDCAN</strong>:
<ul>
<li>stm32h7xx_hal_fdcan.h:
<ul>
<li>Add guard on FDCAN1 peripheral availability on top of the header file</li>
</ul></li>
<li>stm32h7xx_hal_fdcan.c:
<ul>
<li>Add guard on FDCAN1 peripheral availability on top of the source file</li>
<li>Add FDCAN_TIMEOUT_COUNT private define to be used when a timeout based on number of trials is needed</li>
<li>Fix HAL_FDCAN_GetRxMessage function implementation to discard first message in FIFO when overwrite status is on</li>
</ul></li>
</ul></li>
<li><strong>HAL FLASH</strong>:
<ul>
<li>stm32h7xx_hal_flash.h:
<ul>
<li>Update to use DUAL_BANK define in macros __HAL_FLASH_ENABLE_IT, __HAL_FLASH_DISABLE_IT, __HAL_FLASH_GET_FLAG and __HAL_FLASH_CLEAR_FLAG:
<ul>
<li>Two different implementations depending of dual bank device (STM32H74x/5x/Ax/Bx) of single bank device (<strong>STM32H72x/3x</strong>/50/B0)</li>
</ul></li>
<li>Delimit Bank2 private macros with DUAL_BANK define<br />
</li>
<li>Add IS_FLASH_PROGRAM_ADDRESS_OTP and IS_FLASH_PROGRAM_ADDRESS private macros used within the Flash HAL driver for STM32H7Ax/Bx devices</li>
</ul></li>
<li>stm32h7xx_hal_flash_ex.h:
<ul>
<li>Update to support option bytes TCM_AXI_SHARED and CPUFREQ_BOOST available on <strong>STM32H72x/3x</strong> new devices</li>
</ul></li>
<li>stm32h7xx_hal_flash.c:
<ul>
<li>Update implementation to consider dual bank devices (STM32H74x/5x and STM32H7Ax/Bx) and single bank devices (<strong>STM32H72x/3x</strong>)</li>
</ul></li>
<li>stm32h7xx_hal_flash_ex.c:
<ul>
<li>Update implementation to consider dual bank devices (STM32H74x/5x and STM32H7Ax/Bx) and single bank devices (<strong>STM32H72x/3x</strong>)</li>
<li>Update implementation to to support option bytes TCM_AXI_SHARED and CPUFREQ_BOOST available on <strong>STM32H72x/3x</strong> new devices</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL FMAC</strong>:
<ul>
<li>New HAL and LL drivers to support FMAC peripheral available on new <strong>STM32H72x/3x</strong> new devices</li>
</ul></li>
<li><strong>HAL/LL GPIO</strong>:
<ul>
<li>stm32h7xx_hal_gpio_ex.h:
<ul>
<li>Update Alternate functions definition for new <strong>STM32H72x/3x</strong> devices</li>
</ul></li>
<li>stm32h7xx_hal_gpio.c:
<ul>
<li>Update HAL_GPIO_DeInit implementation to re-order register sequence and avoid inconsistent ISR behavior</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL USB</strong>:
<ul>
<li>stm32h7xx_hal_hcd.h:
<ul>
<li>Update HCD_SPEED_FULL HCD_SPEED_LOW defines values with respect to new defines in stm32h7xx_ll_usb.h (USBH_FSLS_SPEED)</li>
</ul></li>
<li>stm32h7xx_hal_hcd.c:
<ul>
<li>Update HCD_HC_IN_IRQHandler to handle USB_OTG_HCINT_BBERR IT</li>
</ul></li>
<li>stm32h7xx_ll_usb.h:
<ul>
<li>USBH_FS_SPEED define renamed to USBH_FSLS_SPEED (no impact as used by the stm32h7xx_hal_hcd.h that has been updated)</li>
</ul></li>
<li>stm32h7xx_ll_usb.c:
<ul>
<li>Update USB_DeactivateDedicatedEndpoint implementation to ensure to disable EP during deactivation</li>
<li>Update USB_HostInit implementation to fix compilation error when host core is low speed</li>
</ul></li>
</ul></li>
<li>__HAL/LL HRTIM:
<ul>
<li>stm32h7xx_hal_hrtim.c:
<ul>
<li>Update Doxygen documentation</li>
</ul></li>
<li>stm32h7xx_ll_hrtim.h:
<ul>
<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL I2C</strong>:
<ul>
<li>stm32h7xx_hal_i2c_ex.h:
<ul>
<li>Update I2CEx_FastModePlus definition to add I2C_FASTMODEPLUS_I2C5 define allowing to support for I2C5 instance available on <strong>STM32H72x/3x</strong> devices</li>
</ul></li>
<li>stm32h7xx_hal_i2c.c:
<ul>
<li>Fix implementation of HAL_I2C_Master_Seq_Transmit_IT, HAL_I2C_Master_Seq_Transmit_DMA, HAL_I2C_Master_Seq_Receive_IT and HAL_I2C_Master_Seq_Receive_DMA
<ul>
<li>Update xfermode upon MAX_NBYTE_SIZE reached</li>
</ul></li>
<li>Improve implementation of I2C_ITMasterCplt function<br />
</li>
</ul></li>
<li>stm32h7xx_hal_i2c_ex.c:
<ul>
<li>Update doxygen documentation with references to I2C5 instance available on <strong>STM32H72x/3x</strong> devices</li>
</ul></li>
<li>stm32h7xx_ll_i2c.h
<ul>
<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
<li>Fix doxygen documentation</li>
</ul></li>
<li>stm32h7xx_ll_i2c.c
<ul>
<li>Update LL_I2C_DeInit implementation to add support of I2C5 instance available on <strong>STM32H72x/3x</strong> devices</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL I2S</strong>: Update to support <strong>I2S Full Duplex</strong> mode (no backward compatibility break):
<ul>
<li>stm32h7xx_hal_i2s.h:
<ul>
<li>Add HAL_I2S_STATE_BUSY_TX_RX state</li>
<li>Add I2S_IT_DXP IT and I2S_FLAG_DXP flag definitions</li>
<li>Update value of I2S_FLAG_MASK define</li>
<li>Add extension <strong>Full Duplex</strong> APIs Transmit/Receive APIs (Polling, IT and DMA)
<ul>
<li>HAL_I2SEx_TransmitReceive,HAL_I2SEx_TransmitReceive_IT and HAL_I2SEx_TransmitReceive_DMA</li>
</ul></li>
<li>Add extension <strong>Full Duplex</strong> callbacks: HAL_I2SEx_TxRxHalfCpltCallback and HAL_I2SEx_TxRxCpltCallback</li>
<li>Update register callback defines to support <strong>Full Duplex</strong> TxRx complete callbacks</li>
<li>Add IS_I2S_FULLDUPLEX private macro use in the HAL I2S driver</li>
</ul></li>
<li>stm32h7xx_hal_i2s.c:
<ul>
<li>Update HAL_I2S_Init, HAL_I2S_RegisterCallback and HAL_I2S_UnRegisterCallback implementation to consider TxRxCpltCallback and TxRxHalfCpltCallback callbacks</li>
<li>Add HAL_I2SEx_TransmitReceive, HAL_I2SEx_TransmitReceive_IT and HAL_I2SEx_TransmitReceive_DMA APIs implementation</li>
<li>Update HAL_I2S_IRQHandler implementation to consider full duplex mode</li>
<li>Add HAL_I2SEx_TxRxHalfCpltCallback and HAL_I2SEx_TxRxCpltCallback weak callbacks<br />
</li>
<li>Add I2SEx_DMATxRxCplt and I2SEx_DMATxRxHalfCplt private functions</li>
<li>Update implementation of I2S_Transmit_16Bit_IT and I2S_Transmit_32Bit_IT functions</li>
<li>Update implementation of I2S_Receive_16Bit_IT and I2S_Receive_32Bit_IT functions</li>
<li>Update doxygen documentation</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL IWDG</strong>:
<ul>
<li>stm32h7xx_hal_iwdg.c:
<ul>
<li>Update HAL_IWDG_DEFAULT_TIMEOUT define value to consider LSI value instead of hardcoded value</li>
<li>Update doxygen documentation</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL MDMA</strong>:
<ul>
<li>stm32h7xx_hal_mdma.h:
<ul>
<li>Add __HAL_MDMA_SET_COUNTER and __HAL_MDMA_GET_COUNTER macros (same macros as the HAL DMA)</li>
</ul></li>
<li>stm32h7xx_ll_mdma.h
<ul>
<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL SD/MMC</strong>: Add support for Sanitize and Discard functions:
<ul>
<li>stm32h7xx_hal_mmc.h:
<ul>
<li>Added APIs: HAL_MMC_EraseSequence, HAL_MMC_Sanitize, HAL_MMC_ConfigSecRemovalType and HAL_MMC_GetSupportedSecRemovalType</li>
<li>added defines:
<ul>
<li>defines used for HAL_MMC_EraseSequence API:
<ul>
<li>HAL_MMC_ERASE, HAL_MMC_TRIM, HAL_MMC_DISCARD, HAL_MMC_SECURE_ERASE, HAL_MMC_SECURE_TRIM_STEP1 and HAL_MMC_SECURE_TRIM_STEP2</li>
</ul></li>
<li>defines used for HAL_MMC_ConfigSecRemovalType/HAL_MMC_GetSupportedSecRemovalType API:
<ul>
<li>HAL_MMC_SRT_ERASE, HAL_MMC_SRT_WRITE_CHAR_ERASE, HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM and HAL_MMC_SRT_VENDOR_DEFINED</li>
</ul></li>
</ul></li>
</ul></li>
<li>stm32h7xx_hal_mmc.c:
<ul>
<li>Add implementation of APIs HAL_MMC_EraseSequence, HAL_MMC_Sanitize, HAL_MMC_ConfigSecRemovalType and HAL_MMC_GetSupportedSecRemovalType</li>
<li>Update implementation of MMC_HighSpeed, MMC_DDR_Mode private functions</li>
<li>Update HAL_MMC_InitCard to allow upper to 200MHz SDMM Clock<br />
</li>
</ul></li>
<li>stm32h7xx_hal_sd.c:
<ul>
<li>Update HAL_SD_Erase implementation to consider private SDMMC_CmdErase function update</li>
<li>Update HAL_SD_InitCard to allow upper to 200MHz SDMM Clock<br />
</li>
</ul></li>
<li>stm32h7xx_ll_sdmmc.h (HAL core driver, not a user driver)
<ul>
<li>Update SDMMC_CmdErase function to add EraseType parameter</li>
</ul></li>
<li>stm32h7xx_ll_sdmmc.c:
<ul>
<li>Update implementation of SDMMC_CmdErase to add EraseType parameter</li>
<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL OPAMP</strong>:
<ul>
<li>stm32h7xx_ll_opamp.h:
<ul>
<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL OTFDEC</strong>:
<ul>
<li>stm32h7xx_hal_otfdec.h
<ul>
<li>Add implementation of macros __HAL_OTFDEC_GET_FLAG and __HAL_OTFDEC_CLEAR_FLAG</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL PWR</strong>:
<ul>
<li>stm32h7xx_hal_pwr.h:
<ul>
<li>Update __HAL_PWR_VOLTAGESCALING_CONFIG, __HAL_PWR_GET_FLAG, __HAL_PWR_GET_WAKEUPFLAG and __HAL_PWR_CLEAR_WAKEUPFLAG macros implementation to support <strong>STM32H72x/3x</strong> devices</li>
</ul></li>
<li>stm32h7xx_hal_pwr_ex.h:
<ul>
<li>Update to delimit wakeup pins 3 and 5 definitions according to their availability (not available on <strong>STM32H72x/3x</strong> devices)<br />
</li>
</ul></li>
<li>stm32h7xx_hal_pwr.c:
<ul>
<li>Update Doxygen documentation to consider <strong>STM32H72x/3x</strong> devices</li>
</ul></li>
<li>stm32h7xx_hal_pwr_ex.c:
<ul>
<li>Update HAL_PWREx_ControlVoltageScaling implemenation for <strong>STM32H72x/3x</strong> devices<br />
</li>
<li>Update HAL_PWREx_EnterSTOPMode implementation to domain Deep sleep entry foe each Core (CM7/CM4)</li>
<li>Update HAL_PWREx_WAKEUP_PIN_IRQHandler implemenation to delimit wakeup pins 3 and 5 usage according to their availability (not available on <strong>STM32H72x/3x</strong> devices)</li>
</ul></li>
<li>stm32h7xx_ll_pwr.h
<ul>
<li>Update to delimit wakeup pins 3 and 5 definitions according to their availability (not available on <strong>STM32H72x/3x</strong> devices)</li>
<li>Update LL_PWR_REGU_VOLTAGE_SCALE0 value to support <strong>STM32H72x/3x</strong> devices</li>
<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
</ul></li>
<li>stm32h7xx_ll_pwr.c
<ul>
<li>Update LL_PWR_DeInit implemenation to delimit wakeup pins 3 and 5 usage according to their availability (not available on <strong>STM32H72x/3x</strong> devices)</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL RCC</strong>:
<ul>
<li>stm32h7xx_hal_rcc.h:
<ul>
<li>Fix RCC_HSICALIBRATION_DEFAULT and RCC_CSICALIBRATION_DEFAULT values for STM32H74x/5x rev.V and update __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST and __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST macros implementation to consider STM32H74x/7x rev.Y**</li>
<li>Add FMAC anc CORDIC peripherals Clock enable/disable macros</li>
<li>GPIOI not available on <strong>STM32H72x/3x</strong>, corresponding RCC macro are delimited with GPIOI availability check</li>
<li>Add I2C5, TIM23,TIM24 clock enable/disable macros</li>
<li>SAI2 not available on <strong>STM32H72x/3x</strong>, corresponding RCC macro are delimited with SAI2 availability check</li>
<li>Update __HAL_RCC_AHB3_FORCE_RESET implementation to consider STM32H72x/3x (DEV ID 483), STM32H7Ax/Bx (DEV ID 480) and STM32H74x/5x (DEV ID 450)<br />
</li>
<li>Update __HAL_RCC_AHB1_FORCE_RESET implementation to consider STM32H72x/3x (DEV ID 483), STM32H7Ax/Bx (DEV ID 480) and STM32H74x/5x (DEV ID 450)<br />
</li>
<li>Update __HAL_RCC_AHB2_FORCE_RESET implementation to consider STM32H72x/3x (DEV ID 483), STM32H7Ax/Bx (DEV ID 480) and STM32H74x/5x (DEV ID 450)</li>
<li>Update __HAL_RCC_AHB4_FORCE_RESET implementation to consider STM32H72x/3x (DEV ID 483), STM32H7Ax/Bx (DEV ID 480) and STM32H74x/5x (DEV ID 450)</li>
<li>Update __HAL_RCC_APB3_FORCE_RESET implementation to consider STM32H72x/3x (DEV ID 483), STM32H7Ax/Bx (DEV ID 480) and STM32H74x/5x (DEV ID 450)</li>
<li>Update __HAL_RCC_APB1L_FORCE_RESET and __HAL_RCC_APB1H_FORCE_RESET implementation to consider <strong>STM32H72x/3x</strong> (DEV ID 483), STM32H7Ax/Bx (DEV ID 480) and STM32H74x/5x (DEV ID 450)</li>
<li>Update __HAL_RCC_APB2_FORCE_RESET implementation to consider STM32H72x/3x (DEV ID 483), STM32H7Ax/Bx (DEV ID 480) and STM32H74x/5x (DEV ID 450)</li>
<li>Update __HAL_RCC_APB4_FORCE_RESET implementation to consider STM32H72x/3x (DEV ID 483), STM32H7Ax/Bx (DEV ID 480) and STM32H74x/5x (DEV ID 450)</li>
<li>Update __HAL_RCC_APB4_FORCE_RESET implementation to consider STM32H72x/3x (DEV ID 483), STM32H7Ax/Bx (DEV ID 480) and STM32H74x/5x (DEV ID 450)</li>
<li>Add __HAL_RCC_DTS_CLKAM_ENABLE and __HAL_RCC_DTS_CLKAM_DISABLE macro</li>
</ul></li>
<li>stm32h7xx_hal_rcc_ex.h:
<ul>
<li>Update to support I2C5, TIM23,TIM24 clock setting</li>
<li>Update to USART 9/10 clock setting macros to support <strong>STM32H72x/3x</strong> devices<br />
</li>
<li>Update to OSPI clock setting macros to support <strong>STM32H72x/3x</strong> devices</li>
</ul></li>
<li>stm32h7xx_hal_rcc_ex.c:
<ul>
<li>Fix HAL_RCCEx_PeriphCLKConfig implementation
<ul>
<li>Use HRTIM1 con define instead of HRTIM</li>
<li>Support I2C5 available on <strong>STM32H72x/3x</strong> devices</li>
</ul></li>
</ul></li>
<li>stm32h7xx_ll_rcc.h
<ul>
<li>Update to support I2C5, TIM23,TIM24 clock setting</li>
<li>Update to USART 9/10 clock setting macros to support <strong>STM32H72x/3x</strong> devices<br />
</li>
<li>Update to OSPI clock setting macros to support <strong>STM32H72x/3x</strong> devices</li>
<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
</ul></li>
<li>stm32h7xx_ll_rcc.c:
<ul>
<li>Update LL_RCC_DeInit implementation to add Flash latency setting versus the clock when de-initializing</li>
<li>SAI2 not available on <strong>STM32H72x/3x</strong>, corresponding RCC macro are delimited with SAI2 availability check</li>
<li>SAI4 not available on STM32H7Ax/Bx, corresponding RCC macro are delimited with SAI4 availability check</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL RTC</strong>:
<ul>
<li>stm32h7xx_hal_rtc.h:
<ul>
<li>Add prototype of RTC_ExitInitMode private function</li>
</ul></li>
<li>stm32h7xx_hal_rtc_ex.h:
<ul>
<li>Add RTC_MONOTONIC_COUNTER_1 define</li>
<li>Update HAL_RTCEx_MonotonicCounterIncrement and HAL_RTCEx_MonotonicCounterGet APIs prototypes with new parameters Instance</li>
</ul></li>
<li>stm32h7xx_ll_rtc.h:
<ul>
<li>Fix Doxygen documentation</li>
<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
</ul></li>
<li>stm32h7xx_hal_rtc.c:
<ul>
<li>Update HAL_RTC_Init, HAL_RTC_DeInit, HAL_RTC_SetTime, HAL_RTC_SetDate, implementation with enter/exit initialization sequence</li>
<li>Update RTC_EnterInitMode implementation to set state to HAL_RTC_STATE_TIMEOUT upon timeout</li>
<li>Add RTC_ExitInitMode private functions implementation</li>
</ul></li>
<li>stm32h7xx_hal_rtc_ex.c:
<ul>
<li>Update HAL_RTCEx_SetActiveTampers implementation to disable all active tampers with HAL_RTCEx_DeactivateActiveTampers in case of error</li>
<li>Update HAL_RTCEx_SetRefClock and HAL_RTCEx_DeactivateRefClock implementation with enter/exit initialization sequence</li>
<li>Update HAL_RTCEx_MonotonicCounterIncrement and HAL_RTCEx_MonotonicCounterGet APIs with new parameters Instance</li>
<li>Update HAL_RTCEx_SetWakeUpTimer to fix WUTWF flag management</li>
</ul></li>
<li>stm32h7xx_ll_rtc.h
<ul>
<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
</ul></li>
</ul></li>
<li><strong>HAL SAI</strong>:
<ul>
<li>stm32h7xx_hal_sai.h:
<ul>
<li>Update doxygen documentation</li>
</ul></li>
<li>stm32h7xx_hal_sai.c:
<ul>
<li>Update HAL_SAI_Init to add a check on master clock divider parameter and to fix SAI frequency calculation in case of SPDIF output</li>
<li>Update SAI_Disable implementation to remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
</ul></li>
</ul></li>
<li><strong>HAL SMARTCARD</strong>:
<ul>
<li>stm32h7xx_hal_smartcard.c:
<ul>
<li>Update HAL_SMARTCARD_Transmit, HAL_SMARTCARD_Transmit_IT, HAL_SMARTCARD_Transmit_DMA and SMARTCARD_EndTransmit_IT implementation to fix an issue when No repetition after NACK is received in smartcard T=0</li>
</ul></li>
<li>stm32h7xx_hal_smartcard_ex.c:
<ul>
<li>Update RX_FIFO_DEPTH and TX_FIFO_DEPTH private defines values to fix FIFO threshold level (16 instead of 8)</li>
</ul></li>
<li>Update doxygen documentation</li>
</ul></li>
<li><strong>HAL SMBUS</strong>:
<ul>
<li>stm32h7xx_hal_smbus.h:
<ul>
<li>Add SMBUS_FIRST_FRAME_WITH_PEC define used within Master/Slave Transmit/Receive API
<ul>
<li>This fix allows to properly differentiate short read or write transfers with PEC and react adequately</li>
</ul></li>
</ul></li>
<li>stm32h7xx_hal_smbus.c:
<ul>
<li>Update private functions implementation to use “SMBUS_HandleTypeDef type” instead of "struct __SMBUS_HandleTypeDef"</li>
</ul></li>
</ul></li>
<li><strong>HAL SPDIFRX</strong>:
<ul>
<li>stm32h7xx_hal_spdifrx.c:
<ul>
<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL SPI</strong>:
<ul>
<li>stm32h7xx_hal_spi.c
<ul>
<li>Update HAL_SPI_TransmitReceive implementation to avoid a a risk going to infinite loop in 32 bit data mode (when timeout occurs)</li>
</ul></li>
<li>stm32h7xx_ll_spi.h
<ul>
<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL TIM</strong>:
<ul>
<li>stm32h7xx_hal_tim.h:
<ul>
<li>Update to handle channel state and DMA burst state independently allowing to use multiple DMA request with different channels of same timer:
<ul>
<li>Add HAL_TIM_ChannelStateTypeDef and HAL_TIM_DMABurstStateTypeDef enumerations</li>
<li>Add ChannelState, ChannelNState and DMABurstState private parameters to the TIM_HandleTypeDef structure</li>
<li>Update __HAL_TIM_RESET_HANDLE_STATE to consider ChannelState, ChannelNState and DMABurstState.</li>
<li>Add private macros: TIM_CHANNEL_STATE_GET, TIM_CHANNEL_STATE_SET, TIM_CHANNEL_STATE_SET_ALL, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET and TIM_CHANNEL_N_STATE_SET_ALL</li>
<li>Add APIs: HAL_TIM_GetActiveChannel, HAL_TIM_GetChannelState and HAL_TIM_DMABurstState and remove TIM_DMADelayPulseCplt callback</li>
</ul></li>
</ul></li>
<li>stm32h7xx_hal_tim_ex.h:
<ul>
<li>Add HAL_TIMEx_GetChannelNState API allowing to retrieve a channel state</li>
</ul></li>
<li>stm32h7xx_hal_tim.c and stm32h7xx_hal_tim_ex.c:
<ul>
<li>Remove private function “TIM_DMADelayPulseCplt”</li>
<li>Update to handle channel state and DMA burst state independently allowing to use multiple DMA request with different channels of same timer<br />
</li>
</ul></li>
<li>stm32h7xx_ll_tim.h
<ul>
<li>Fix values of defines LL_TIM_COUNTERMODE_CENTER_UP and LL_TIM_COUNTERMODE_CENTER_DOWN (values was inverted)</li>
<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL UART</strong>:
<ul>
<li>stm32h7xx_hal_uart.h:
<ul>
<li>Update implementation of UART_DIV_LPUART, UART_DIV_SAMPLING8 and UART_DIV_SAMPLING16 macros using “UARTPrescTable” table</li>
</ul></li>
<li>stm32h7xx_hal_uart.c:
<ul>
<li>Update implementation of HAL_UART_Transmit and HAL_UART_Receive to add lock that avoid deadlock scenario while mixing polling Transmit and IT Receive requests</li>
<li>Rework BRR register value computation in HAL_UART_Init() for code footprint size optimization
<ul>
<li>Add UARTPrescTable private table</li>
<li>Update UART_SetConfig function to use UARTPrescTable instead of run time calculation<br />
</li>
</ul></li>
</ul></li>
<li>stm32h7xx_hal_uart_ex.c:
<ul>
<li>Update RX_FIFO_DEPTH and TX_FIFO_DEPTH private defines values to fix FIFO threshold level (16 instead of 8)</li>
</ul></li>
<li>stm32h7xx_ll_lpuart.h
<ul>
<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL USART</strong>:
<ul>
<li>stm32h7xx_hal_usart.c
<ul>
<li>Update HAL_USART_IRQHandler implementation to fix typo when clearing USART_CLEAR_RTOF flag</li>
</ul></li>
<li>stm32h7xx_hal_usart_ex.c:
<ul>
<li>Update RX_FIFO_DEPTH and TX_FIFO_DEPTH private defines values to fix FIFO threshold level (16 instead of 8)<br />
</li>
</ul></li>
<li>stm32h7xx_ll_usart.h
<ul>
<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
<li>Fix doxygen documentation</li>
</ul></li>
</ul></li>
<li><strong>LL SYSTEM</strong>:
<ul>
<li>stm32h7xx_ll_system.h: Update to support <strong>STM32H72x/3x</strong> devices
<ul>
<li>New I2C5 instance with Fast Mode plus capability</li>
<li>GPIOI not available</li>
<li>AXI to ITCM RAM sharing</li>
<li>TIM23/TIM24 new instances</li>
<li>Device ID: 0x483</li>
</ul></li>
</ul></li>
<li><strong>LL UTIL</strong>:
<ul>
<li>stm32h7xx_ll_utils.h:
<ul>
<li>Update LL_UTILS_PACKAGETYPE_xx defines to support <strong>STM32H72x/3x</strong> devices (device ID 0x483)</li>
</ul></li>
<li>stm32h7xx_ll_utils.c:
<ul>
<li>Update UTILS_MAX_FREQUENCY_SCALEx values according the STM32H74x/5x devices (device ID 0x450): 480MHz max frequency</li>
<li>Update UTILS_MAX_FREQUENCY_SCALEx values according the <strong>STM32H72x/3x</strong> devices (device ID 0x483) : 550MHz max frequency</li>
<li>Update LL_SetFlashLatency to support <strong>STM32H72x/3x</strong> devices (device ID 0x483)</li>
<li>Update doxygen documentation</li>
</ul></li>
</ul></li>
</ul>
<h2 id="known-limitations">Known Limitations</h2>
<ul>
<li>None</li>
</ul>
<h2 id="backward-compatibility">Backward compatibility</h2>
<ul>
<li>Extension RTC APIs HAL_RTCEx_MonotonicCounterIncrement and HAL_RTCEx_MonotonicCounterGet APIs prototypes updated with new parameters Instance (alignment with other STM32 familes)</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true"><strong>V1.8.0 / 14-February-2020</strong></label>
<div>
<h2 id="main-changes-1">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements</li>
<li><strong>HAL</strong>: generic
<ul>
<li>stm32h7xx_hal.c:
<ul>
<li>Update HAL_Init implementation to reflect the current core clock in SystemCoreClock global variable (Corex-M7 or Corext-M4 clock depending of the current context in case of Dual Core)</li>
<li>Update HAL_InitTick implementation to use SystemCoreClock global variable as it reflect now the current core clock (simplifying the implementation)</li>
</ul></li>
</ul></li>
<li><strong>HAL DAC</strong>:
<ul>
<li>stm32h7xx_hal_dac.c:
<ul>
<li>Update HAL_DAC_ConfigChannel function implemenation to fix the “DAC_ConnectOnChipPeripheral” check and settings</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL GPIO</strong>:
<ul>
<li>stm32h7xx_hal_gpio.h
<ul>
<li>Update IS_GPIO_PIN macro implementation with an explicit cast to avoid compilation warning on EWARM 8.30</li>
</ul></li>
<li>stm32h7xx_hal_gpio_ex.h
<ul>
<li>Remove useless GPIO_AF13_TIM8 define</li>
<li>Update GPIOK_PIN_AVAILABLE define to consider missed GPIO Pin 2</li>
</ul></li>
<li>stm32h7xx_hal_gpio.c:
<ul>
<li>Update HAL_GPIO_Init and HAL_GPIO_DeInit functions implementation to avoid a glitch during GPIO initialization/de-initialization</li>
</ul></li>
<li>stm32h7xx_ll_gpio.c:
<ul>
<li>Update LL_GPIO_Init function implementation to avoid a glitch during GPIO initialization</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL HRTIM</strong>:
<ul>
<li>stm32h7xx_hal_hrtim.h
<ul>
<li>Remove HRTIM_PRESCALERRATIO_MUL2 to HRTIM_PRESCALERRATIO_MUL32 definition that are not supported on STM32H7 devices</li>
</ul></li>
<li>stm32h7xx_ll_hrtim.h
<ul>
<li>Remove LL_HRTIM_PRESCALERRATIO_MUL2 to LL_HRTIM_PRESCALERRATIO_MUL32 definition that are not supported on STM32H7 devices</li>
</ul></li>
<li>Note: Only Prescaler ratios 1/2/4 are supported for HRTIM on STM32H7 devices</li>
</ul></li>
<li><strong>HAL I2C</strong>:
<ul>
<li>stm32h7xx_hal_i2c.h
<ul>
<li>Updates to fix incorrectly enable interrupts in I2C_Enable_IRQ routine when InterruptRequest = I2C_XFER_CPLT_IT</li>
<li>Updates to avoid HardFault in I2C_DMAAbort when DMA is not used for Tx or/and Rx</li>
</ul></li>
</ul></li>
<li><strong>HAL JPEG</strong>:
<ul>
<li>stm32h7xx_hal_jpeg.h: Minor update for STM32 coding rules compliance (one line per variable declaration, local variables naming …)</li>
</ul></li>
<li><strong>HAL/LL LPTIM</strong>:
<ul>
<li>stm32h7xx_hal_lptim.c:
<ul>
<li>Update HAL_LPTIM_Init implementation to configure digital filter for external clock when LPTIM is clocked by an internal clock source</li>
</ul></li>
</ul></li>
<li><strong>HAL MMC</strong>:
<ul>
<li>stm32h7xx_hal_mmc.c:
<ul>
<li>Update implementation to avoid setting the block size during every MMC card transaction (block size is set once in HAL_MMC_InitCard )</li>
</ul></li>
</ul></li>
<li><strong>HAL NAND</strong>:
<ul>
<li>stm32h7xx_hal_nand.h: Minor update to use UL/U suffix respectively instead of uint32_t/uint8_t cast</li>
</ul></li>
<li><strong>HAL NOR</strong>:
<ul>
<li>stm32h7xx_hal_nor.h: Minor update to remove useless U suffix following uint32_t/uint16_t/uint8_t cast</li>
</ul></li>
<li><strong>HAL OSPI</strong>: <strong>Add support of multiplexed mode feature</strong>
<ul>
<li>stm32h7xx_hal_ospi.h:
<ul>
<li>Update “OSPIM_CfgTypeDef” structure definition to add “Req2AckTime” allowing to set the “minimum switching duration” clock cycles when OSPI signals are multiplexed in the OSPI IO Manager</li>
<li>Add IS_OSPIM_REQ2ACKTIME macro useful when the HAL assert is enabled and allowing to check the “Req2AckTime” value validity<br />
</li>
</ul></li>
<li>stm32h7xx_hal_ospi.c:
<ul>
<li>Update “HAL_OSPIM_Config” implementation to support OSPI signals Mux using the OSPI IO Manager</li>
</ul></li>
</ul></li>
<li><strong>HAL PSSI</strong>:
<ul>
<li>stm32h7xx_hal_pssi.c:
<ul>
<li>Update HAL_PSSI_Transmit/HAL_PSSI_Receive implementation to fix warning on GCC compiler</li>
</ul></li>
</ul></li>
<li><strong>HAL QSPI</strong>:
<ul>
<li>stm32h7xx_hal_qspi.h:
<ul>
<li>Rename HAL_QPSI_TIMEOUT_DEFAULT_VALUE define to HAL_QSPI_TIMEOUT_DEFAULT_VALUE (typo fix). backward compatibility ensured through stm32_hal_legacy.h header file<br />
</li>
</ul></li>
<li>stm32h7xx_hal_qspi.c:
<ul>
<li>Update HAL_QSPI_Init/HAL_QSPI_DeInit implementation to remove useless lock/unlock</li>
<li>Update HAL_QSPI_IRQHandler implementation to optimize flags check</li>
<li>Update HAL_QSPI_Transmit_DMA to:
<ul>
<li>Fix performance issue at high frequency by fixing wrong activation of TC interrupt</li>
<li>Enabling QUADSPI_CR_DMAEN bit field: used only by the HAL_QSPI_IRQHandler to check if current Transmit is using DMA when IT occurs</li>
</ul></li>
<li>Update HAL_QSPI_Receive_DMA to enable QUADSPI_CR_DMAEN bit field: used only by the HAL_QSPI_IRQHandler to check if current Receive is using DMA when IT occurs</li>
<li>Update HAL_QSPI_Abort to reset functional mode configuration to indirect write mode by default<br />
</li>
<li>Update HAL_QSPI_Abort_IT to call Abort Complete callback</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL RCC</strong>:
<ul>
<li>stm32h7xx_hal_rcc.h:
<ul>
<li>Delimit CRYP and HASH Clock enable/disable/reset/sleep macros with conditional define on respectively CRYP/HASH availability (through CMSIS device header files)</li>
<li>Update __HAL_RCC_AHB3_FORCE_RESET macro implementation to avoid altering reserved bit 31.</li>
</ul></li>
<li>stm32h7xx_hal_rcc_ex.h:
<ul>
<li>Add definition of RCC_EXTI_LINE_LSECSS (EXTI IMR1 EXTI line 18)</li>
<li>Add macros __HAL_RCC_LSECSS_EXTI_ENABLE_IT, __HAL_RCC_LSECSS_EXTI_DISABLE_IT, __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT and __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT</li>
<li>Add macros __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT, __HAL_RCC_C2_LSECSS_EXTI_DISABLE_IT, __HAL_RCC_C2_LSECSS_EXTI_ENABLE_EVENT, __HAL_RCC_C2_LSECSS_EXTI_DISABLE_EVENT: for Dual Core lines allowing to control LSECSS EXTI Line for Coretx-M4.</li>
<li>Add macros __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE, __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE, __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE, __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE, __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE, __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE, __HAL_RCC_LSECSS_EXTI_GET_FLAG and __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG.</li>
<li>Add macros __HAL_RCC_C2_LSECSS_EXTI_GET_FLAG and __HAL_RCC_C2_LSECSS_EXTI_CLEAR_FLAG for Dual Core lines allowing to get/clear LSECSS EXTI line on Coretx-M4.</li>
<li>Add macro __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT</li>
<li>Add prototypes for new APIs HAL_RCCEx_EnableLSECSS_IT, HAL_RCCEx_LSECSS_IRQHandler and HAL_RCCEx_LSECSS_Callback.</li>
</ul></li>
<li>stm32h7xx_ll_rcc.h:
<ul>
<li>Update LL_RCC_CALC_SYSCLK_FREQ, LL_RCC_CALC_HCLK_FREQ, LL_RCC_CALC_PCLK1_FREQ, LL_RCC_CALC_PCLK2_FREQ, LL_RCC_CALC_PCLK3_FREQ and LL_RCC_CALC_PCLK4_FREQ macros implementation to avoid overflow (MISRA-C 2012 compliant)<br />
</li>
</ul></li>
<li>stm32h7xx_hal_rcc.c:
<ul>
<li>Update HAL_RCC_DeInit, HAL_RCC_ClockConfig, HAL_RCC_GetHCLKFreq and HAL_RCC_GetPCLK1Freq to reflect the current core clock in SystemCoreClock global variable (Corex-M7 or Corext-M4 clock depending of the current context in case of Dual Core)</li>
</ul></li>
<li>stm32h7xx_hal_rcc_ex.c:
<ul>
<li>Update HAL_RCCEx_GetD1SysClockFreq to reflect the current core clock in SystemCoreClock global variable (Corex-M7 or Corext-M4 clock depending of the current context in case of Dual Core).</li>
<li>Add HAL_RCCEx_EnableLSECSS_IT, HAL_RCCEx_LSECSS_IRQHandler and HAL_RCCEx_LSECSS_Callback APIs: allowing to handle LSECSS interrupt.</li>
</ul></li>
</ul></li>
<li><strong>HAL SD</strong>:
<ul>
<li>stm32h7xx_hal_sd.c:
<ul>
<li>Update HAL_SD_InitCard implementation to fix compilation issue when USE_SD_TRANSCEIVER is disabled and USE_SD_DIRPOL enabled</li>
<li>Update implementation to avoid setting the block size during every SD card transaction (block size is set once in HAL_SD_InitCard, HAL_SD_GetCardStatus, HAL_SD_ConfigWideBusOperation)</li>
</ul></li>
<li>stm32h7xx_hal_sd_ex.c:
<ul>
<li>Update HAL_SDEx_ReadBlocksDMAMultiBuffer and HAL_SDEx_WriteBlocksDMAMultiBuffer to avoid setting the block size during every SD card transaction</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL TIM</strong>:
<ul>
<li>stm32h7xx_hal_tim.c: Minor fixes with the assert parameters checks</li>
</ul></li>
<li><strong>HAL/LL USART</strong>: Add RTO (Receive Time Out) flag support
<ul>
<li>stm32h7xx_hal_usart.h
<ul>
<li>Add HAL_USART_ERROR_RTO define to USART Error Definition section</li>
<li>Add USART_FLAG_RTOF define to USART Flags section</li>
<li>Add USART_CLEAR_RTOF define to USART Interruption Clear Flags section</li>
</ul></li>
<li>stm32h7xx_hal_usart.c: Update HAL_USART_IRQHandler to handle USART_ISR_RTOF flag and IT</li>
<li>stm32h7xx_hal_usart_ex.c: Update HAL_USARTEx_DisableSlaveMode to fix typo in disabling salve mode</li>
</ul></li>
<li><strong>HAL/LL DMA</strong>: Add support for DMA_SxCR_TRBUFF
<ul>
<li>stm32h7xx_ll_dma.h
<ul>
<li>Add API “LL_DMA_EnableBufferableTransfer” allowing to enable bufferable transfer<br />
</li>
<li>Add API “LL_DMA_DisableBufferableTransfer” allowing to disable bufferable transfer</li>
</ul></li>
<li>stm32h7xx_hal_dma.c:
<ul>
<li>Add workaround to fix Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be lock when transferring data to/from USART/UART
<ul>
<li>Enabling the DMA bufferable transfer when the request is from a UART/USART(DMA_SxCR_TRBUFF bit field)</li>
</ul></li>
</ul></li>
</ul></li>
<li><strong>HAL/LL TIM</strong>:
<ul>
<li>stm32h7xx_ll_tim.h
<ul>
<li>Parameter “RepetitionCounter” of “LL_TIM_InitTypeDef” is now of type “uint32_t” with possible values from 0 to 0xFFFF for advanced timers</li>
</ul></li>
</ul></li>
<li><strong>LL FMC</strong>: (Core LL driver for HAL NAND, NOR, SDRAM, SRAM, not user LL driver)
<ul>
<li>stm32h7xx_ll_fmc.h: Minor update to remove useless U suffix following uint32_t cast</li>
<li>stm32h7xx_ll_fmc.c:
<ul>
<li>Update FMC_NORSRAM_Init implemenation to fix compilation issue with MS Visual 2017</li>
<li>Update FMC_NAND_CommonSpace_Timing_Init, FMC_NAND_AttributeSpace_Timing_Init, FMC_NAND_ECC_Enable, FMC_NAND_ECC_Disable and FMC_NAND_GetECC to fix GCC compiler warning due to unused parameter</li>
</ul></li>
</ul></li>
<li><strong>LL UTIL</strong>:
<ul>
<li>stm32h7xx_ll_utils.h
<ul>
<li>Update numerical value of LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176 to LL_UTILS_PACKAGETYPE_TFBGA225 definition to align with the Reference Manual</li>
<li>Add LL_SetFlashLatency API.</li>
</ul></li>
<li>stm32h7xx_ll_utils.c
<ul>
<li>Add implementation of LL_SetFlashLatency API (static functions UTILS_CalculateFlashLatency and UTILS_SetFlashLatency removed and repalced by the user API LL_SetFlashLatency)</li>
<li>Update LL_SetSystemCoreClock to keep only setting SystemCoreClock according to the current Core frequency (Corex-M7 or Coretx-M4 in case of Dual Core line).
<ul>
<li>SystemD2Clock reflecting the D2 domain frequency is now set within UTILS_EnablePLLAndSwitchSystem</li>
</ul></li>
</ul></li>
</ul></li>
</ul>
<h2 id="known-limitations-1">Known Limitations</h2>
<ul>
<li><strong>HAL I2S</strong>:
<ul>
<li>Full duplex Transmit/receive feature not available
<ul>
<li>stm32h7xx_hal_i2s_ex.h/stm32h7xx_hal_i2s_ex.c: These files are empty as full duplex feature is not available in this release</li>
</ul></li>
</ul></li>
</ul>
<h2 id="backward-compatibility-1">Backward compatibility</h2>
<ul>
<li>None</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true"><strong>V1.7.0 / 06-December-2019</strong></label>
<div>
<h2 id="main-changes-2">Main Changes</h2>
<ul>
<li>Official release with support of STM32H7A3/B3xx/B0xx new devices<br />
</li>
<li>General updates to fix known defects and implementation enhancements</li>
<li><strong>HAL</strong>: generic
<ul>
<li>stm32h7xx_hal.h:
<ul>
<li>Add __HAL_SYSCFG_FASTMODEPLUS_ENABLE and __HAL_SYSCFG_FASTMODEPLUS_DISABLE macros allowing to enable/disable the I2C Fast-mode Plus driving capability
<ul>
<li>This feature is available on STM32H7A3/B3xx/B0xx devices only</li>
</ul></li>
<li>Add HAL_SYSCFG_VDDMMC_CompensationCodeConfig API allowing to configure the VDDMMC compensation<br />
</li>
</ul></li>
<li>stm32h7xx_hal_conf_template.h:
<ul>
<li>Add support for HAL DTS, GFXMMU, OSPI, PSSI (HAL modules enabling, header files inclusion and register callback activation)</li>
</ul></li>
<li>stm32h7xx_hal.c:
<ul>
<li>Update HAL_SetTickFreq API to restore current tick frequency when call to HAL_InitTick fails</li>
<li>Add HAL_SYSCFG_VDDMMC_CompensationCodeConfig API implementation</li>
<li>Fix HAL_EXTI_D1_ClearFlag and HAL_EXTI_D2_ClearFlag APIs implementation: using direct write operation (instead of read/modify/write)</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL ADC</strong>:
<ul>
<li>stm32h7xx_hal_adc.h:
<ul>
<li>Add ADC_CHANNEL_DAC2CH1_ADC2 definition for DAC2 to ADC connection (DAC2 available on STM32H7A3/B3xx/B0xx devices only)</li>
<li>Update ADC_IS_SYNCHRONOUS_CLOCK_MODE macro implementation (ADC3 not available on STM32H7A3/B3xx/B0xx devices)</li>
</ul></li>
<li>stm32h7xx_hal_adc_ex.h:
<ul>
<li>ADC_IS_INDEPENDENT macro available only when device supports ADC3</li>
<li>Update ADC_OFFSET_SHIFT_RESOLUTION , ADC_AWD1THRESHOLD_SHIFT_RESOLUTION and ADC_AWD23THRESHOLD_SHIFT_RESOLUTION macros implemenation to support STM32H7A3/B3xx/B0xx new devices<br />
</li>
<li>ADC3_COMMON_REGISTER macro available only when device supports ADC3</li>
<li>Update ADC_MASTER_REGISTER macro to consider ADC3 when it is available only</li>
<li>ADC3_NONMULTIMODE_OR_MULTIMODEMASTER macro available only when device supports ADC3</li>
<li>Update ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE and ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE macro to consider ADC3 when it is available only</li>
<li>Update ADC_TEMPERATURE_SENSOR_INSTANCE, ADC_BATTERY_VOLTAGE_INSTANCE and ADC_VREFINT_INSTANCE to consider ADC3 when it is available and if not ADC2 (case of STM32H7A3/B3xx/B0xx devices)</li>
</ul></li>
<li>stm32h7xx_ll_adc.h:
<ul>
<li>Adapt definition of LL_ADC_RESOLUTION_8B for STM32H7A3/B3xx/B0xx devices</li>
<li>ADC3 definitions are conditionned by the ADC3 instance availability (according to CMSIS device mapping, ADC3 is not available on STM32H7A3/B3xx/B0xx devices)</li>
<li>Add DAC2 LL_ADC_CHANNEL_DAC2CH1_ADC2 definition</li>
</ul></li>
<li>stm32h7xx_hal_adc.c:
<ul>
<li>Update HAL_ADC_Init implementation to consider STM32H7A3/B3xx/B0xx devices (ADC_VER_V5_3)</li>
<li>Update HAL_ADC_Start_DMA to add configuration of Data transfer mode</li>
<li>Update HAL_ADC_ConfigChannel implemenation to consider ADC3 when it is available only</li>
<li>Update ADC_ConfigureBoostMode implemenation to consider frequency ranges for STM32H7A3/B3xx/B0xx devices (ADC_VER_V5_3)</li>
</ul></li>
<li>stm32h7xx_hal_adc_ex.c:
<ul>
<li>Update HAL_ADCEx_LinearCalibration_GetValue and HAL_ADCEx_LinearCalibration_SetValue APIs implementation to stop the Ongoing conversion, if any, before the calibration. In this case the convertion is retsored after the calibration</li>
<li>Update HAL_ADCEx_LinearCalibration_FactorLoad API implementation to consider ADC2 and ADC3 in addition to ADC1</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL COMP</strong>:
<ul>
<li>stm32h7xx_hal_comp.h:
<ul>
<li>Add definition of COMP_INPUT_PLUS_DAC2_CH1 (DAC2 available on STM32H7A3/B3xx/B0xx devices only)</li>
<li>Add definition of COMP_INPUT_MINUS_TPSENS_DAC2CH1 and COMP_INPUT_MINUS_VBAT_VDDAP (available on STM32H7A3/B3xx/B0xx devices only)</li>
<li>Update IS_COMP_INPUT_PLUS and IS_COMP_INPUT_MINUS macros according to the new above defines</li>
</ul></li>
<li>stm32h7xx_hal_comp.c:
<ul>
<li>Update HAL_COMP_Init API implementation to
<ul>
<li>Support new inputs available on STM32H7A3/B3xx/B0xx devices</li>
<li>Add EXTI configuration for Coretx-M7 and Coretx-M4 (in case of Dual Core device)</li>
</ul></li>
</ul></li>
<li>stm32h7xx_ll_comp.h:
<ul>
<li>Add definition of LL_COMP_INPUT_MINUS_TPSENS_DAC2CH1 (DAC2 available on STM32H7A3/B3xx/B0xx devices only)<br />
</li>
<li>Add definition of LL_COMP_INPUT_MINUS_VBAT_VDDAP (DAC2 available on STM32H7A3/B3xx/B0xx devices only)</li>
<li>Add definition of LL_COMP_AF_PA6 to LL_COMP_AF_PK2 Comparator output definitions</li>
<li>Update LL_COMP_ConfigInputs, LL_COMP_SetInputPlus and LL_COMP_GetInputPlus APIs implementation with support of STM32H7A3/B3xx/B0xx devices</li>
<li>Add LL_COMP_SetOutputAlternateFunction and LL_COMP_GetOutputAlternateFunction allowing to Set/Get the output alternate function in the Option register</li>
</ul></li>
</ul></li>
<li><strong>HAL CRYP</strong>:
<ul>
<li>stm32h7xx_hal_cryp.h:
<ul>
<li>Add KeyIVConfigSkip parameter to CRYP_ConfigTypeDef structure: allowing user to skip IV and key setting when processing large buffers by chunks</li>
<li>Add definition of CRYP_KEYIVCONFIG_ALWAYS and CRYP_KEYIVCONFIG_ONCE used to fill KeyIVConfigSkip configuration parameter<br />
</li>
</ul></li>
<li>stm32h7xx_hal_cryp.c:
<ul>
<li>Update HAL_CRYP_Encrypt/HAL_CRYP_Decrypt HAL_CRYP_Encrypt_IT/HAL_CRYP_Decrypt_IT and HAL_CRYP_Encrypt_DMA/HAL_CRYP_Decrypt_DMA APIs to support large buffers encryption/decryption by chunks without reconfiguring the Key or the Initialization Vector between each API call</li>
<li>Update to support user input/output buffers size that is not multiple of 4 words (size of the CRYP peripheral FIFO)</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL DAC</strong>:
<ul>
<li>stm32h7xx_hal_dac.h:
<ul>
<li>Add support for DAC2 instance (available on STM32H7A3/B3xx/B0xx devices only)</li>
<li>HAL_DAC_MSP_INIT_CB_ID and HAL_DAC_MSP_DEINIT_CB_ID callaback IDs respectively changed to HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID:
<ul>
<li>Backward compatibility ensured by the stm32_hal_legacy header file</li>
</ul></li>
<li>HRTIM tiggers definitions (DAC_TRIGGER_HR1_TRGO1 and DAC_TRIGGER_HR1_TRGO2) are available only for devices where the HRTIM peripheral is present
<ul>
<li>HRTIM peripheral not present on STM32H7A3/B3xx/B0xx devices</li>
</ul></li>
<li>DAC_TRIGGER_LP1_OUT and DAC_TRIGGER_LP2_OUT triggers defines renamed respectively to DAC_TRIGGER_LPTIM1_OUT and DAC_TRIGGER_LPTIM2_OUT
<ul>
<li>Backward compatibility ensured by the stm32_hal_legacy header file</li>
</ul></li>
<li>Add DAC_TRIGGER_LPTIM3_OUT trigger definition: available for DAC2 instance that is present on STM32H7A3/B3xx/B0xx devices only</li>
<li>DAC_CHIPCONNECT_DISABLE and DAC_CHIPCONNECT_ENABLE definitions respectively changed to DAC_CHIPCONNECT_EXTERNAL and DAC_CHIPCONNECT_INTERNAL
<ul>
<li>Backward compatibility ensured by the stm32_hal_legacy header file</li>
</ul></li>
</ul></li>
<li>stm32h7xx_hal_dac_ex.h:
<ul>
<li>Add support for DAC2 instance (available on STM32H7A3/B3xx/B0xx devices only)</li>
<li>Update IS_DAC_TRIGGER macro implementation to consider HRTIM and DAC2 triggers when it is available</li>
<li>Update IS_DAC_CHIP_CONNECTION macro implementation to consider new DAC_CHIPCONNECT_EXTERNAL and DAC_CHIPCONNECT_INTERNAL defines</li>
<li>Add HAL_DACEx_DualStart, HAL_DACEx_DualStop, HAL_DACEx_DualStart_DMA, HAL_DACEx_DualStop_DMA, HAL_DACEx_DualSetValue and HAL_DACEx_DualGetValue APIs</li>
</ul></li>
<li>stm32h7xx_hal_dac.c:
<ul>
<li>Update HAL_DAC_ConfigChannel implementation to consider DAC_CHIPCONNECT_EXTERNAL and DAC_CHIPCONNECT_INTERNAL defines</li>
</ul></li>
<li>stm32h7xx_hal_dac_ex.c:
<ul>
<li>Add implemenation of HAL_DACEx_DualStart, HAL_DACEx_DualStop, HAL_DACEx_DualStart_DMA, HAL_DACEx_DualStop_DMA, HAL_DACEx_DualSetValue and HAL_DACEx_DualGetValue APIs</li>
</ul></li>
<li>stm32h7xx_ll_dac.h: Update to support STM32H7A3/B3xx/B0xx devices New DAC triggers</li>
</ul></li>
<li><strong>HAL DCMI</strong>:
<ul>
<li>stm32h7xx_hal_dcmi.h:
<ul>
<li>Add definition of DCMI_SyncUnmaskTypeDef structure used with new HAL_DCMI_ConfigSyncUnmask API</li>
<li>Add HAL_DCMI_ConfigSyncUnmask API</li>
</ul></li>
<li>stm32h7xx_hal_dcmi.c:
<ul>
<li>Add implemenation HAL_DCMI_ConfigSyncUnmask API</li>
</ul></li>
</ul></li>
<li><strong>HAL DFSDM</strong>:
<ul>
<li>stm32h7xx_hal_dfsdm.h:
<ul>
<li>Add inclusion of stm32h7xx_hal_dfsdm_ex.h new file</li>
</ul></li>
<li>stm32h7xx_hal_dfsdm_ex.h:
<ul>
<li>New extension file with HAL_DFDSMEx_ChannelSetPulsesSkipping and HAL_DFDSMEx_ChannelGetPulsesSkipping APIs</li>
</ul></li>
<li>stm32h7xx_hal_dfsdm.c:
<ul>
<li>Add support of DFSDM2_Channel0 available on STM32H7A3/B3xx/B0xx devices</li>
</ul></li>
<li>stm32h7xx_hal_dfsdm_ex.c:
<ul>
<li>New extension file with HAL_DFDSMEx_ChannelSetPulsesSkipping and HAL_DFDSMEx_ChannelGetPulsesSkipping APIs implementation</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL DMA</strong>:
<ul>
<li>stm32h7xx_hal_dma.h:
<ul>
<li>Add PSSI, DAC2, UART9 and USART10 requests (PSSI and DAC2 peripherals available on STM32H7A3/B3xx/B0xx devices only)</li>
<li>HRTIM, SAI3, SAI4, ADC3 requests are available only when these peripherals are present on the given device (through CMSIS device mapping)</li>
<li>Update to support BDMA1 and BDMA2 available on STM32H7A3/B3xx/B0xx devices</li>
</ul></li>
<li>stm32h7xx_hal_dma_ex.h:
<ul>
<li>DMAMUX request generator defines HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP, HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP and ADC3 are available when LPTIM4, LPTIM5 and ADC3 are respectively available</li>
</ul></li>
<li>stm32h7xx_hal_dma.c/stm32h7xx_hal_dma_ex.c:
<ul>
<li>Update to support BDMA1 and BDMA2 available on STM32H7A3/B3xx/B0xx devices</li>
</ul></li>
<li>stm32h7xx_ll_bdma.h:
<ul>
<li>Add support for BDMA1 and BDMA2 available on STM32H7A3/B3xx/B0xx devices</li>
</ul></li>
<li>stm32h7xx_ll_dmamux.h:
<ul>
<li>Add Add PSSI, DAC2, UART9 and USART10 requests (PSSI and DAC2 peripherals available on STM32H7A3/B3xx/B0xx devices only)</li>
<li>HRTIM, SAI3, SAI4, ADC3 requests are available only when these peripherals are present on the given device (through CMSIS device mapping)</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL DMA2D</strong>:
<ul>
<li>stm32h7xx_hal_dma2d.h:
<ul>
<li>Update DMA2D_InitTypeDef initialization structure with BytesSwap and LineOffsetMode allowing respectively to support byte swap and line offset modes</li>
<li>Add DMA2D_M2M_BLEND_FG and DMA2D_M2M_BLEND_BG definitions allowing to support blending with fixed foreground/background colors</li>
<li>Add DMA2D_LOM_PIXELS and DMA2D_LOM_BYTES definitions allowing to support Line Offset mode feature</li>
<li>Add DMA2D_BYTES_REGULAR and DMA2D_BYTES_SWAP definitions allowing to support Byte Swap feature</li>
<li>Add HAL_DMA2D_CLUTStartLoad and HAL_DMA2D_CLUTStartLoad_IT APIs: same as HAL_DMA2D_CLUTStartLoad/HAL_DMA2D_CLUTStartLoad_IT APIs but with the parameter CLUTCfg passed by address instead of variable</li>
</ul></li>
<li>stm32h7xx_hal_dma2d.c:
<ul>
<li>Update HAL_DMA2D_Init implementation to support byte swap and line offset modes</li>
<li>Update HAL_DMA2D_BlendingStart and HAL_DMA2D_BlendingStart_IT to support blending with fixed foreground/background colors</li>
<li>Add implementation of HAL_DMA2D_CLUTStartLoad and HAL_DMA2D_CLUTStartLoad_IT APIs</li>
</ul></li>
<li>stm32h7xx_ll_dma2d.h:
<ul>
<li>Update LL_DMA2D_InitTypeDef initialization structure with OutputSwapMode and LineOffsetMode allowing respectively to support byte swap and line offset modes<br />
</li>
<li>Add LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG and LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG definitions allowing to support blending with fixed foreground/background colors</li>
<li>Add LL_DMA2D_SWAP_MODE_REGULAR and LL_DMA2D_SWAP_MODE_TWO_BY_TWO definitions allowing to support Byte Swap feature</li>
<li>Add LL_DMA2D_LINE_OFFSET_PIXELS and LL_DMA2D_LINE_OFFSET_BYTES definitions allowing to support Line Offset mode feature</li>
<li>Add LL_DMA2D_SetOutputSwapMode and LL_DMA2D_GetOutputSwapMode APIs</li>
<li>Add LL_DMA2D_SetLineOffsetMode and LL_DMA2D_GetLineOffsetMode APIs</li>
</ul></li>
<li>stm32h7xx_ll_dma2d.c:
<ul>
<li>Update LL_DMA2D_StructInit API implementation to support byte swap and line offset modes</li>
</ul></li>
</ul></li>
<li><strong>HAL DTS</strong>:
<ul>
<li>Add New HAL DTS driver stm32h7xx_hal_dts.h/stm32h7xx_hal_dts.c (Digital Temperature Sensor). This peripheral is available on STM32H7A3/B3xx/B0xx devices only</li>
</ul></li>
<li><strong>HAL/LL EXTI</strong>:
<ul>
<li>Update to consider STM32H7A3/B3xx/B0xx devices EXTI lines</li>
<li>Update EXTI Pend Clear Sources considering STM32H7A3/B3xx/B0xx devices: LPTIM2 and LPTIM3 used as SRD domain wakeup pend clear source versus LPTIM4/LPTIM5 in the legacy devices</li>
</ul></li>
<li><strong>HAL FLASH</strong>:
<ul>
<li>Update to consider Flash operations on STM32H7A3/B3xx/B0xx devices</li>
</ul></li>
<li><strong>HAL GFXMMU</strong>:
<ul>
<li>Add GFXMMU HAL driver stm32h7xx_hal_gfxmmu.h/stm32h7xx_hal_gfxmmu.c. This peripheral is available on STM32H7A3/B3xx/B0xx devices only</li>
</ul></li>
<li><strong>HAL GPIO</strong>:
<ul>
<li>Update GPIO Alternate functions definitions (in stm32h7xx_hal_gpio_ex.h file) for STM32H7A3/B3xx/B0xx devices</li>
</ul></li>
<li><strong>HAL HASH</strong>:
<ul>
<li>stm32h7xx_hal_hash.h:
<ul>
<li>Add IS_HASH_POLLING_MULTIBUFFER_SIZE macro to check that input data buffer size is valid for multi-buffer HASH</li>
<li>Add HAL_HASH_SHA1_Accmlt_IT/HAL_HASH_SHA1_Accmlt_End_IT and HAL_HASH_MD5_Accmlt_IT/HAL_HASH_MD5_Accmlt_End_IT APIs</li>
</ul></li>
<li>stm32h7xx_hal_hash_ex.h:
<ul>
<li>Add HAL_HASHEx_SHA224_Accmlt/HAL_HASHEx_SHA224_Accmlt_End, HAL_HASHEx_SHA256_Accmlt/HAL_HASHEx_SHA256_Accmlt_End APIs</li>
<li>Add HAL_HASHEx_SHA224_Accmlt_IT/HAL_HASHEx_SHA224_Accmlt_End_IT, HAL_HASHEx_SHA256_Accmlt_IT/HAL_HASHEx_SHA256_Accmlt_End_IT APIs</li>
</ul></li>
<li>stm32h7xx_hal_hash.c:
<ul>
<li>Add implementation of HAL_HASH_SHA1_Accmlt_IT/HAL_HASH_SHA1_Accmlt_End_IT and HAL_HASH_MD5_Accmlt_IT/HAL_HASH_MD5_Accmlt_End_IT APIs</li>
</ul></li>
<li>stm32h7xx_hal_hash_ex.c:
<ul>
<li>Add implementation of HAL_HASHEx_SHA224_Accmlt/HAL_HASHEx_SHA224_Accmlt_End, HAL_HASHEx_SHA256_Accmlt/HAL_HASHEx_SHA256_Accmlt_End APIs</li>
<li>Add implementation of HAL_HASHEx_SHA224_Accmlt_IT/HAL_HASHEx_SHA224_Accmlt_End_IT, HAL_HASHEx_SHA256_Accmlt_IT/HAL_HASHEx_SHA256_Accmlt_End_IT APIs</li>
</ul></li>
</ul></li>
<li><strong>HAL I2S</strong>:
<ul>
<li>stm32h7xx_hal_i2s.h:
<ul>
<li>Add definition of HAL_I2S_ERROR_NO_OGT and HAL_I2S_ERROR_NOT_SUPPORTED errors<br />
</li>
</ul></li>
<li>stm32h7xx_hal_i2s.c:
<ul>
<li>Add support of I2S mode on SPI6 peripheral (available on STM32H7A3/B3xx/B0xx devices only)</li>
<li>Fix GCC compilation warning on HAL_I2S_Transmit/HAL_I2S_Receive due to 16 bits access on TXDR/RXDR 32 bits registers</li>
<li>Update and fix HAL_I2S_DMAPause/HAL_I2S_DMAResume APIs</li>
<li>Update HAL_I2S_IRQHandler APIs to handle I2S_FLAG_OVR, I2S_FLAG_UDR and I2S_FLAG_FRE error flags</li>
</ul></li>
<li>stm32h7xx_hal_i2s_ex.h/stm32h7xx_hal_i2s_ex.c : These files are empty as full duplex feature is not available in this release</li>
</ul></li>
<li><strong>HAL/LL LPTIM</strong>:
<ul>
<li>stm32h7xx_hal_lptim.h:
<ul>
<li>LPTIM_INPUT1SOURCE_SAI1_FSA and LPTIM_INPUT1SOURCE_SAI1_FSB replaced respectively by LPTIM_INPUT1SOURCE_SAI4_FSA and LPTIM_INPUT1SOURCE_SAI4_FSB to be aligned with the Reference Manual (<strong>Compatibility break</strong>)</li>
</ul></li>
<li>stm32h7xx_ll_lptim.h:
<ul>
<li>Add definition of LL_LPTIM_TRIG_SOURCE_LPTIM2 to LL_LPTIM_TRIG_SOURCE_DFSDM2_BRK trigger sources</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL MDMA</strong>:
<ul>
<li>stm32h7xx_hal_mdma.h:
<ul>
<li>Add definitions of OctoSPI peripheral requests when available (OctoSPI available on STM32H7A3/B3xx/B0xx devices only)</li>
<li>Add definitions of DSI peripheral requests when available (DSI available on STM32H747/757 devices only)</li>
<li>Add definitions of MDMA_REQUEST_SDMMC1_DMA_ENDBUFFER and MDMA_REQUEST_SDMMC1_COMMAND_END requests</li>
<li>Delimit definition of LTDC, QUADSPI and JPEG requests by the peripherals availability</li>
</ul></li>
<li>stm32h7xx_hal_mdma.c:
<ul>
<li>Update HAL_MDMA_DeInit APIs implementation to avoid returning error when the MDMA state is busy: the MDMA will be deinitialized in any case when calling HAL_MDMA_DeInit</li>
</ul></li>
<li>stm32h7xx_ll_mdma.h:
<ul>
<li>Add definitions of OctoSPI peripheral requests when available (OctoSPI available on STM32H7A3/B3xx/B0xx devices only)</li>
<li>Add definitions of DSI peripheral requests when available (DSI available on STM32H747/757 devices only)</li>
<li>Add definitions of MDMA_REQUEST_SDMMC1_DMA_ENDBUFFER and MDMA_REQUEST_SDMMC1_COMMAND_END requests</li>
<li>Delimit definition of LTDC, QUADSPI and JPEG requests by the peripherals availability</li>
</ul></li>
</ul></li>
<li><strong>HAL MMC</strong>:
<ul>
<li>stm32h7xx_hal_mmc_ex.h:
<ul>
<li>APIs HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback, HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback, HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback and HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback respectevely renamed to HAL_MMCEx_Read_DMADoubleBuf0CpltCallback, HAL_MMCEx_Read_DMADoubleBuf1CpltCallback, HAL_MMCEx_Write_DMADoubleBuf0CpltCallback and HAL_MMCEx_Write_DMADoubleBuf1CpltCallback:</li>
<li>Backward compatibility ensured by the stm32_hal_legacy header file</li>
</ul></li>
<li>stm32h7xx_hal_mmc.c:
<ul>
<li>Fix HAL_MMC_ReadBlocks/HAL_MMC_WriteBlocks, HAL_MMC_ReadBlocks_IT/HAL_MMC_WriteBlocks_IT and HAL_MMC_ReadBlocks_DMA/HAL_MMC_WriteBlocks_DMA APIs implementation for DDR mode</li>
</ul></li>
<li>stm32h7xx_hal_mmc_ex.c:
<ul>
<li>Fix HAL_MMCEx_ConfigDMAMultiBuffer API implementation regarding DMA block size</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL OPAMP</strong>:
<ul>
<li>stm32h7xx_hal_opamp.h:
<ul>
<li>APIs HAL_OPAMP_MSP_INIT_CB_ID/HAL_OPAMP_MSP_DEINIT_CB_ID enumeration respectively renamed to HAL_OPAMP_MSPINIT_CB_ID/HAL_OPAMP_MSPDEINIT_CB_ID
<ul>
<li>Backward compatibility ensured by the stm32_hal_legacy header file</li>
</ul></li>
<li>Add definition of OPAMP_NONINVERTINGINPUT_DAC2_CH input trigger conditioned by the DAC2 peripheral availability (DAC2 peripheral available on STM32H7A3/B3xx/B0xx devices only)</li>
</ul></li>
<li>stm32h7xx_hal_opamp.c:
<ul>
<li>Update HAL_OPAMP_DeInit to disabled first the OPAMP before resetting the configuration</li>
</ul></li>
<li>stm32h7xx_ll_opamp.h:
<ul>
<li>Add definition of LL_OPAMP_INPUT_NONINVERT_DAC2 input trigger conditioned by the DAC2 peripheral availability (DAC2 peripheral available on STM32H7A3/B3xx/B0xx devices</li>
</ul></li>
</ul></li>
<li><p><strong>HAL OSPI</strong>: New HAL driver stm32h7xx_hal_ospi.h/stm32h7xx_hal_ospi.c to handle OctoSPI peripheral (available on STM32H7A3/B3xx/B0xx devices only)</p></li>
<li><p><strong>HAL OTFDEC</strong>: New HAL driver stm32h7xx_hal_otfdec.h/stm32h7xx_hal_otfdec.c to handle OTFDEC peripheral (available on STM32H7A3/B3xx/B0xx devices only)</p></li>
<li><p><strong>HAL PSSI</strong>: New HAL driver stm32h7xx_hal_pssi.h/stm32h7xx_hal_pssi.c to handle PSSI peripheral (available on STM32H7A3/B3xx/B0xx devices only)</p></li>
<li><strong>HAL/LL PWR</strong>: Update to handle STM32H7A3/B3xx/B0xx devices
<ul>
<li>2 power domains only (versus 3 in legacy STM32H7 devices)</li>
<li>VOS0 voltage scalling management</li>
<li>Wake up flag management</li>
<li>STOP2 Low Power mode management</li>
</ul></li>
<li><strong>HAL RAMECC</strong>:
<ul>
<li>stm32h7xx_hal_ramecc.h:
<ul>
<li>Add definition of RAMECC Error Codes</li>
<li>Add __HAL_RAMECC_GET_GLOBAL_IT_SOURCE, __HAL_RAMECC_GET_MONITOR_IT_SOURCE and __HAL_RAMECC_GET_IT_SOURCE macros</li>
<li>Add HAL_RAMECC_IsECCSingleErrorDetected, HAL_RAMECC_IsECCDoubleErrorDetected APIs</li>
</ul></li>
<li>stm32h7xx_hal_ramecc.c:
<ul>
<li>Add error codes management</li>
<li>Add HAL_RAMECC_IsECCSingleErrorDetected, HAL_RAMECC_IsECCDoubleErrorDetected APIs implementation</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL RCC</strong>:
<ul>
<li>stm32h7xx_hal_rcc.h: Update to support STM32H7A3/B3xx/B0xx devices</li>
<li>Add OCTOSPI1/2, OCTOSPIM, OTFDEC1/2, GFXMMU peripherals clock enabling/disabling, force reset/release reset macros</li>
<li>Update other peripherals clock macros according to the number of instance on STM32H7A3/B3xx/B0xx devices and on the legacy STM32H7 devices</li>
<li>stm32h7xx_hal_rcc_ex.h: Update to support STM32H7A3/B3xx/B0xx devices
<ul>
<li>Update RCC_PeriphCLKInitTypeDef structure to handle OCTOSPI1/2, OCTOSPIM, OTFDEC1/2, GFXMMU peripherals clock settings</li>
</ul></li>
<li>Update other peripherals clock defines and macros according to the number of instance on STM32H7A3/B3xx/B0xx devices and on the legacy STM32H7 devices<br />
</li>
<li>stm32h7xx_hal_rcc.c:</li>
<li>General update to support STM32H7A3/B3xx/B0xx devices clock configurations<br />
</li>
<li>Update HAL_RCC_DeInit to handle flash latency configuration in both cases: when increasing and decreasing latency.</li>
<li>Update HAL_RCC_OscConfig to:
<ul>
<li>Allow only HSI calibration when HSI is used as system source clock (attempt to disable HSI will return error in this case)</li>
<li>Allow reconfiguring the system clock with the same current config without returning error (useful when reconfiguring the system clock after low power mode wakeup)<br />
</li>
</ul></li>
<li>stm32h7xx_hal_rcc_ex.c:</li>
<li>General update to support STM32H7A3/B3xx/B0xx devices peripherals clock configurations</li>
<li>Update HAL_RCCEx_GetPeriphCLKFreq to support SAI2/SAI3 and SPI6 peripherals</li>
<li>stm32h7xx_ll_rcc.h: Update to support STM32H7A3/B3xx/B0xx devices
<ul>
<li>Add OCTOSPI1/2, OCTOSPIM, OTFDEC1/2, GFXMMU peripherals clock source definitions</li>
</ul></li>
<li>Update other peripherals clock source definitions according to the number of instance on STM32H7A3/B3xx/B0xx devices and on the legacy STM32H7 devices</li>
</ul></li>
<li><strong>HAL/LL RNG</strong>:
<ul>
<li>stm32h7xx_hal_rng.h: Update to support STM32H7A3/B3xx/B0xx devices</li>
<li>Add definition of HAL_RNG_ERROR_BUSY, HAL_RNG_ERROR_SEED and HAL_RNG_ERROR_CLOCK error codes</li>
<li>Add inclusion of stm32h7xx_hal_rng_ex.h extended RNG HAL driver</li>
<li>stm32h7xx_hal_rng_ex.h:
<ul>
<li>New HAL extended HAL driver with support of support STM32H7A3/B3xx/B0xx devices RNG features</li>
</ul></li>
<li>stm32h7xx_hal_rng.c: Update to support STM32H7A3/B3xx/B0xx devices</li>
<li>Update HAL_RNG_Init and HAL_RNG_DeInit APIs implementation to support STM32H7A3/B3xx/B0xx devices RNG configuration</li>
<li>stm32h7xx_hal_rng_ex.c:
<ul>
<li>New HAL extended HAL RNG driver with support of support STM32H7A3/B3xx/B0xx devices RNG features</li>
</ul></li>
<li>stm32h7xx_ll_rng.h:
<ul>
<li>Add definition of LL_RNG_CLKDIV_BY_1 to LL_RNG_CLKDIV_BY_32768 RNG dividers</li>
<li>Add new APIs support features available on STM32H7A3/B3xx/B0xx devices:
<ul>
<li>LL_RNG_EnableCondReset, LL_RNG_DisableCondReset and LL_RNG_IsEnabledCondReset</li>
<li>LL_RNG_ConfigLock and LL_RNG_IsConfigLocked</li>
<li>LL_RNG_EnableNistCompliance, LL_RNG_DisableNistCompliance and LL_RNG_IsEnabledNistCompliance</li>
<li>LL_RNG_SetConfig1, LL_RNG_GetConfig1, LL_RNG_SetConfig2, LL_RNG_GetConfig2, LL_RNG_SetConfig3 and LL_RNG_GetConfig3</li>
<li>LL_RNG_SetClockDivider and LL_RNG_GetClockDivider</li>
<li>LL_RNG_SetHealthConfig and LL_RNG_GetHealthConfig</li>
</ul></li>
</ul></li>
</ul></li>
<li><p><strong>HAL/LL RTC</strong>: Update to support STM32H7A3/B3xx/B0xx devices new RTC features</p></li>
<li><strong>HAL SAI</strong>:
<ul>
<li>Update to support STM32H7A3/B3xx/B0xx devices SAI instances:
<ul>
<li>Only SAI2 and SAI3 instances are available on STM32H7A3/B3xx/B0xx devices</li>
<li>SAI1/2/3/4 are available for legacy STM32H7 devices</li>
<li>Usage of a giving SAI instance is conditioned with its presence on the given device (according to the CMSIS device memory mapping)</li>
</ul></li>
</ul></li>
<li><strong>HAL SAI</strong>:
<ul>
<li>Update to support STM32H7A3/B3xx/B0xx devices SAI instances:</li>
</ul></li>
<li><strong>HAL SD</strong>:
<ul>
<li>stm32h7xx_hal_sd_ex.h:
<ul>
<li>rename HAL_SDEx_Read_DMADoubleBuffer0CpltCallback, HAL_SDEx_Read_DMADoubleBuffer1CpltCallback, HAL_SDEx_Write_DMADoubleBuffer0CpltCallback and HAL_SDEx_Write_DMADoubleBuffer1CpltCallback respectevely to HAL_SDEx_Read_DMADoubleBuf0CpltCallback, HAL_SDEx_Read_DMADoubleBuf1CpltCallback, HAL_SDEx_Write_DMADoubleBuf0CpltCallback and HAL_SDEx_Write_DMADoubleBuf1CpltCallback</li>
<li>Backward compatibility ensured by the stm32_hal_legacy header file<br />
</li>
</ul></li>
<li>stm32h7xx_hal_sd.c:
<ul>
<li>Fix HAL_SD_ReadBlocks_IT/HAL_SD_WriteBlocks_IT HAL_SD_ReadBlocks_DMA/HAL_SD_WriteBlocks_DMA APIs implementation to avoid losing data in read and dead lock in write</li>
</ul></li>
<li>stm32h7xx_hal_sd_ex.c:
<ul>
<li>Fix HAL_SDEx_ReadBlocksDMAMultiBuffer/HAL_SDEx_WriteBlocksDMAMultiBuffer APIs implementation to avoid losing data in read and dead lock in write</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL SPI</strong>:
<ul>
<li>stm32h7xx_hal_spi.c:
<ul>
<li>Fix GCC compilation warning on HAL_SPI_Transmit/HAL_SPI_Receive, HAL_SPI_Transmit_IT/HAL_SPI_Receive_IT and HAL_SPI_TransmitReceive/HAL_SPI_TransmitReceive_IT APIs due to 16 bits access on TXDR/RXDR 32 bits registers</li>
<li>stm32h7xx_ll_spi.h:
<ul>
<li>Rename LL_SPI_SR_CRCERR define to LL_SPI_SR_CRCE to be aligned with the Reference Manual</li>
<li>Update LL_SPI_TransmitData16 to fix GCC compilation warning</li>
</ul></li>
</ul></li>
</ul></li>
<li><strong>HAL SPI</strong>:
<ul>
<li>stm32h7xx_hal_spi.c:
<ul>
<li>Fix GCC compilation war</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL TIM</strong>:
<ul>
<li>stm32h7xx_hal_tim.h:
<ul>
<li>Add definition of TIM_UIFREMAP_DISABLE and TIM_UIFREMAP_ENABLE Interrupt Flag Remap</li>
<li>Add definition of TIM_ENCODERINPUTPOLARITY_RISING and TIM_ENCODERINPUTPOLARITY_FALLING Encoder Input Polarity</li>
<li>Add definition of TIM_TS_ITR9 to TIM_TS_ITR13 Trigger Selection</li>
<li>Add __HAL_TIM_UIFREMAP_ENABLE, __HAL_TIM_UIFREMAP_DISABLE and __HAL_TIM_GET_UIFCPY macros</li>
</ul></li>
<li>stm32h7xx_hal_tim_ex.h:
<ul>
<li>Rename TIM_TIM1_ETR_ADC2_AWD1, TIM_TIM1_ETR_ADC2_AWD2 and TIM_TIM1_ETR_ADC2_AWD3 respectively to TIM_TIM1_ETR_ADC1_AWD1, TIM_TIM1_ETR_ADC1_AWD2 and TIM_TIM1_ETR_ADC1_AWD2 to be aligned with all STM32H7 devices Reference manuals (<strong>compatibility break</strong>)</li>
</ul></li>
<li>stm32h7xx_hal_tim.c:
<ul>
<li>Update TIM_SlaveTimer_SetConfig API implementation to handle TIM_TS_ITR9 to TIM_TS_ITR13 input triggers</li>
</ul></li>
</ul></li>
<li><strong>LL BUS</strong>:
<ul>
<li>stm32h7xx_ll_bus.h: Update to support STM32H7A3/B3xx/B0xx devices peripherals</li>
</ul></li>
<li><strong>LL CRS</strong>:
<ul>
<li>stm32h7xx_ll_crs.h/stm32h7xx_ll_crs.c: New LL driver allowing to handle CRS (Clock Recovery System) module</li>
</ul></li>
<li><strong>LL SDMMC</strong> (LL core driver for HAL SD/MMC):
<ul>
<li>stm32h7xx_ll_sdmmc.c: Fix SDMMC_CmdStopTransfer implementation to ignore address Out Of Range error that is not relevant at end of memory</li>
</ul></li>
<li><strong>LL SYSTEM</strong>:
<ul>
<li>stm32h7xx_ll_system.h:
<ul>
<li>Update LL_SYSCFG_SetTIMBreakInputs and LL_SYSCFG_GetTIMBreakInputs APIs to support STM32H7A3/B3xx/B0xx devices break inputs</li>
<li>Add LL_SYSCFG_EnableIOSpeedOptimization1/LL_SYSCFG_DisableIOSpeedOptimization1/LL_SYSCFG_IsEnabledIOSpeedOptimization1 APIs</li>
<li>Add LL_SYSCFG_EnableIOSpeedOptimization2/LL_SYSCFG_DisableIOSpeedOptimization2, LL_SYSCFG_IsEnabledIOSpeedOptimization1 APIs</li>
<li>Add LL_SYSCFG_EnableIOSpeedOptimization3/LL_SYSCFG_DisableIOSpeedOptimization3, LL_SYSCFG_IsEnabledIOSpeedOptimization3 APIs</li>
<li>Add LL_SYSCFG_MMCGetCellCompensationCode/LL_SYSCFG_MMCSetPMOSCompensationCode/LL_SYSCFG_MMCSetPMOSCompensationCode APIs</li>
<li>Add LL_SYSCFG_VDMMCSetNMOSCompensationCode/LL_SYSCFG_VDMMCGetNMOSCompensationCode APIs</li>
</ul></li>
</ul></li>
<li><strong>LL UTILS</strong>:
<ul>
<li>stm32h7xx_ll_utils.h:
<ul>
<li>Add definition of STM32H7A3/B3xx/B0xx devices package types: LL_UTILS_PACKAGETYPE_LQFP64 to LL_UTILS_PACKAGETYPE_TFBGA225</li>
<li>Update LL_GetPackageType API to support STM32H7A3/B3xx/B0xx devices package types</li>
</ul></li>
</ul></li>
<li><strong>LL DELAY BLOCK</strong> (LL core driver for HAL SD):
<ul>
<li>stm32h7xx_ll_delayblock.h:
<ul>
<li>Add DLYB_MAX_SELECT definition used for delay block tuning</li>
<li>Add DelayBlock_Configure use to configure the delay block</li>
</ul></li>
<li>stm32h7xx_ll_delayblock.c:
<ul>
<li>Add implemenation of DelayBlock_Configure function allowing to configure the delay block</li>
<li>Rework DelayBlock_Enable function (delay block calibration procedure)</li>
</ul></li>
</ul></li>
</ul>
<h2 id="known-limitations-2">Known Limitations</h2>
<ul>
<li><strong>HAL I2S</strong>:
<ul>
<li>Full duplex Transmit/receive feature not available
<ul>
<li>stm32h7xx_hal_i2s_ex.h/stm32h7xx_hal_i2s_ex.c: These files are empty as full duplex feature is not available in this release</li>
</ul></li>
</ul></li>
<li><strong>HAL PSSI</strong>:
<ul>
<li>New PSSI driver provided supporting both modes : DMA mode recommended/ polling mode has hardware limitation confirmed and mentioned in the STM32H7A3/B3xx/B0xx erratasheet.</li>
</ul></li>
</ul>
<h2 id="backward-compatibility-2">Backward compatibility</h2>
<ul>
<li><strong>HAL I2S</strong>:
<ul>
<li>stm32h7xx_hal_i2s_ex.h/stm32h7xx_hal_i2s_ex.c : These files are empty as full duplex feature is not available in this release</li>
</ul></li>
<li><strong>HAL LPTIM</strong>:
<ul>
<li>stm32h7xx_hal_lptim.h:
<ul>
<li>LPTIM_INPUT1SOURCE_SAI1_FSA and LPTIM_INPUT1SOURCE_SAI1_FSB replaced respectively by LPTIM_INPUT1SOURCE_SAI4_FSA and LPTIM_INPUT1SOURCE_SAI4_FSB to be aligned with the Reference manual</li>
</ul></li>
</ul></li>
<li><strong>HAL TIM</strong>:
<ul>
<li>stm32h7xx_hal_tim_ex.h:</li>
<li>TIM_TIM1_ETR_ADC2_AWD1, TIM_TIM1_ETR_ADC2_AWD2 and TIM_TIM1_ETR_ADC2_AWD3 respectively to TIM_TIM1_ETR_ADC1_AWD1, TIM_TIM1_ETR_ADC1_AWD2 and TIM_TIM1_ETR_ADC1_AWD2 to be aligned with all STM32H7 devices Reference manuals</li>
</ul></li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true"><strong>V1.6.0 / 28-June-2019</strong></label>
<div>
<h2 id="main-changes-3">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements</li>
<li><strong>HAL</strong>: generic
<ul>
<li>stm32h7xx_hal.h:
<ul>
<li>Add macros __HAL_ART_ENABLE, __HAL_ART_DISABLE and __HAL_ART_CONFIG_BASE_ADDRESS allowing to respectively enable/disable and configure the Cortex-M4 ART instruction cache</li>
<li>Add export of the variables uwTick, uwTickPrio and uwTickFreq</li>
<li>Add prototypes for utility APIs HAL_GetUIDw0, HAL_GetUIDw1 and HAL_GetUIDw2</li>
</ul></li>
<li>stm32h7xx_hal.c:
<ul>
<li>uwTick, uwTickPrio and uwTickFreq are no more static</li>
<li>Update HAL_Init API to configure and enable the Cortex-M4 ART instruction cache with default base address set to flash bank 2 (default boot address of the Cortex-M4). user can change this default configuration, if required, by calling macros __HAL_ART_ENABLE, __HAL_ART_DISABLE and __HAL_ART_CONFIG_BASE_ADDRESS after the HAL_Init</li>
<li>Add implementation of utility APIs HAL_GetUIDw0, HAL_GetUIDw1 and HAL_GetUIDw2<br />
</li>
</ul></li>
<li>stm32h7xx_hal_conf_template.h:
<ul>
<li>Add “USE_SPI_CRC” definition set to 1 by default and customizable by the HAL user</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL ADC</strong>:
<ul>
<li>stm32h7xx_hal_adc.h:
<ul>
<li>Remove useless defines ADC_OVERSAMPLING_RATIO_2 to ADC_OVERSAMPLING_RATIO_1024. the oversampling ratio is filled in parameter “Ratio” of the structure “Oversampling” of the “ADC_InitTypeDef” structure with a value between 1 and 1024</li>
</ul></li>
<li>stm32h7xx_hal_adc_ex.h:
<ul>
<li>Fix macro “IS_ADC_OVERSAMPLING_RATIO”, the allowed oversampling ratio is a value between 1 and 1024</li>
<li>Add prototype of “HAL_ADCEx_LinearCalibration_FactorLoad” API allowing to automatically load the linear calibration factors from ADC engineering bytes (programmed during device production, specific to each device)<br />
</li>
</ul></li>
<li>stm32h7xx_ll_adc.h:
<ul>
<li>Add definitions of ADC_LINEAR_CALIB_REG_1_ADDR to ADC_LINEAR_CALIB_REG_6_ADDR: these are the addresses with ADC linearity calibration content (programmed during device production, specific to each device) the content of these addresses is then automatically loaded by the API “HAL_ADCEx_LinearCalibration_FactorLoad”</li>
</ul></li>
<li>stm32h7xx_hal_adc.c:
<ul>
<li>Update “HAL_ADC_ConfigChannel” implementation to set the ADC selected offset right shift</li>
</ul></li>
<li>stm32h7xx_hal_adc_ex.c:
<ul>
<li>Update definition of “ADC_CALIBRATION_TIMEOUT” to 633600000 according to the data-sheet update</li>
<li>Update “HAL_ADCEx_LinearCalibration_SetValue” implementation to:
<ul>
<li>Enable the ADC before applying the calibration factors</li>
<li>Respect the user linear calibration buffer order from calibration factor 0 to 5</li>
</ul></li>
<li>Update “HAL_ADCEx_LinearCalibration_GetValue” implementation to:
<ul>
<li>Respect the user linear calibration buffer order from calibration factor 0 to 5</li>
</ul></li>
<li>Add “HAL_ADCEx_LinearCalibration_FactorLoad” API allowing to automatically load the linear calibration factors from ADC engineering bytes (programmed during device production, specific to each device)</li>
<li>Update “HAL_ADCEx_InjectedConfigChannel” implementation to set the ADC selected offset right shift</li>
</ul></li>
</ul></li>
<li><strong>HAL CRYP</strong>:
<ul>
<li>stm32h7xx_hal_cryp.c:
<ul>
<li>Update “CRYP_GCMCCM_SetPayloadPhase_IT” implementation to improve data management in interrupt mode</li>
<li>Update “CRYP_Workaround” to fix the implementation of the authentication tags computation phase during a GCM encryption when the size of the last payload block is inferior to 128 bits</li>
</ul></li>
</ul></li>
<li><strong>HAL GPIO</strong>:
<ul>
<li>stm32h7xx_hal_gpio.c:
<ul>
<li>Fix implementation of “HAL_GPIO_DeInit” API in order to clear the correct external interrupt/event in SYSCFG EXTICR register</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL HRTIM</strong>:
<ul>
<li>stm32h7xx_hal_hrtim.h:
<ul>
<li>Fix definitions of HRTIM Output Set Sources according the STM32H7 reference manual:
<ul>
<li>Remove definition HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 to HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3</li>
<li>Replaced by HRTIM_OUTPUTSET_TIMEV_1 to HRTIM_OUTPUTSET_TIMEV_9 definition</li>
<li>The stm32_hal_legacy.h file is also updated to avoid compatibility break versus the previous STM32H7 HAL version regarding the removed/replaced defines</li>
</ul></li>
</ul></li>
<li>stm32h7xx_hal_hrtim.c:
<ul>
<li>Update “HAL_HRTIM_WaveformCompareConfig” implementation to clear HRTIM_TIMCR_DELCMP2 bit field when required</li>
</ul></li>
<li>stm32h7xx_ll_hrtim.h:
<ul>
<li>Fix definitions of the output set sources (“LL_HRTIM_CROSSBAR_NONE” to “LL_HRTIM_CROSSBAR_UPDATE” replacing “LL_HRTIM_OUTPUTSET_NONE” to LL_HRTIM_OUTPUTSET_UPDATE) according to the reference manual (<strong>compatibility break</strong>)</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL HSEM</strong>:
<ul>
<li>stm32h7xx_hal_hsem.c:
<ul>
<li>Update “HAL_HSEM_Release” implementation to support dynamic CPU ID detection useful when code is intended to be shared between the Cortex-M4 and Cortex-M7 in a dual core device</li>
</ul></li>
</ul></li>
<li><strong>HAL IRDA</strong>:
<ul>
<li>stm32h7xx_hal_irda.c:
<ul>
<li>Update description of “HAL_IRDA_Transmit_XXX”, “HAL_IRDA_Receive_XXX” APIs with more details about the data size management</li>
</ul></li>
</ul></li>
<li><strong>HAL LPTIM</strong>:
<ul>
<li>stm32h7xx_hal_lptim.c:
<ul>
<li>Update “HAL_LPTIM_XXX_Start/HAL_LPTIM_XXX_Stop” and “HAL_LPTIM_XXX_Start_IT/HAL_LPTIM_XXX_Stop_IT” implementations to handle “ARROK” and “CMPOK” flags</li>
</ul></li>
<li>stm32h7xx_hal_lptim.h:
<ul>
<li>Update "__HAL_LPTIM_AUTORELOAD_SET" and "__HAL_LPTIM_COMPARE_SET" macros description to add details about macro usage:
<ul>
<li>can only be used when the LPTIM instance is enabled</li>
</ul></li>
<li>Update "__HAL_LPTIM_ENABLE_IT" and "__HAL_LPTIM_DISABLE_IT" macros description to add details about macro usage:
<ul>
<li>can only be used when the LPTIM instance is disabled</li>
</ul></li>
</ul></li>
</ul></li>
<li><strong>HAL MMC</strong>:
<ul>
<li>stm32h7xx_hal_mmc.h:
<ul>
<li>Comments clean-up and updates of the APIs signatures</li>
<li>Add prototypes for “HAL_MMC_ConfigSpeedBusOperation” API allowing to configure the Bus speed mode in
<ul>
<li>Auto mode: SDMMC_SPEED_MODE_AUTO (maximum supported by the detected MMC memory)</li>
<li>Default speed: SDMMC_SPEED_MODE_DEFAULT<br />
</li>
<li>High Speed: SDMMC_SPEED_MODE_HIGH</li>
<li>High Speed DDR: SDMMC_SPEED_MODE_DDR</li>
</ul></li>
</ul></li>
<li>stm32h7xx_hal_mmc.c:
<ul>
<li>Update of the “How to use this driver” documentation section</li>
<li>Update “HAL_MMC_ReadBlocks” and “HAL_MMC_WriteBlocks” implementations to avoid overflow during data reading/writing into/from user buffer</li>
<li>Update “HAL_MMC_IRQHandler” implementation to consider the interrupts and flag when required(context corresponds to the given flag/interrupt)</li>
<li>Add “HAL_MMC_ConfigSpeedBusOperation” API allowing to configure the Bus speed mode</li>
</ul></li>
</ul></li>
<li><p><strong>HAL SD</strong>:</p>
<ul>
<li>Updates to handle 2 SD instances with different settings regarding the transceiver presence as follow:
<ul>
<li>If the define “USE_SD_TRANSCEIVER” is set to 1 then user can select different transceiver settings through the parameter “TranceiverPresent” of the Init structure (SDMMC_TRANSCEIVER_PRESENT/SDMMC_TRANSCEIVER_NOT_PRESENT)</li>
<li>If “USE_SD_TRANSCEIVER” is set to 1 and the parameter “TranceiverPresent” of the Init structure is not set (it takes the numerical value 0 which corresponds to SDMMC_TRANSCEIVER_UNKNOWN) then “TranceiverPresent” is forced to SDMMC_TRANSCEIVER_PRESENT in the “HAL_SD_Init” API:
<ul>
<li>This allows legacy user code that sets “USE_SD_TRANSCEIVER” to 1 and doesn’t fill the parameter “TranceiverPresent” to continue working as the previous HAL SD version (using a transceiver)</li>
</ul></li>
<li>If the define “USE_SD_TRANSCEIVER” is set to 0 then the parameter “TranceiverPresent” is not available and the HAL SD driver assumes no transceivers for both SD instances
<ul>
<li>This allows also legacy user code that sets “USE_SD_TRANSCEIVER” to 0 to continue working as the previous HAL SD version</li>
</ul></li>
</ul></li>
<li>stm32h7xx_hal_sd.h:
<ul>
<li>Rename “HAL_SD_CardStateType<strong>d</strong>ef” to “HAL_SD_CardStateType<strong>D</strong>ef” as per the STM32Cube coding and naming rules<br />
</li>
<li>Rename “HAL_SD_CardCSDType<strong>d</strong>ef” to “HAL_SD_CardCSDType<strong>D</strong>ef” as per the STM32Cube coding and naming rules</li>
<li>Rename “HAL_SD_CardCIDType<strong>d</strong>ef” to “HAL_SD_CardCIDType<strong>D</strong>ef” as per the STM32Cube coding and naming rules</li>
<li>Rename “HAL_SD_CardStatusType<strong>d</strong>ef” to “HAL_SD_CardStatusType<strong>D</strong>ef” as per the STM32Cube coding and naming rules</li>
<li><strong>Notes: backward compatibility ensured through the stm32_hal_legacy.h file</strong></li>
</ul></li>
<li>stm32h7xx_hal_sd.c:
<ul>
<li>Update “HAL_SD_InitCard” implementation to add 74 SD card clock cycles delay required for power up before starting the SD initialization</li>
<li>Update “HAL_SD_ReadBlocks” and “HAL_SD_WriteBlocks” implementations to avoid overflow during data reading/writing into/from user buffer</li>
<li>Update “HAL_SD_IRQHandler” implementation to consider the interrupts and flag when required(context corresponds to the given flag/interrupt)</li>
<li>Updates following renaming of “HAL_SD_CardStateType<strong>D</strong>ef”, “HAL_SD_CardCSDType<strong>D</strong>ef”, “HAL_SD_CardCIDType<strong>D</strong>ef”, and “HAL_SD_CardStatusType<strong>D</strong>ef”</li>
<li>Update “HAL_SD_ConfigSpeedBusOperation” implementation to handle “SDMMC_SPEED_MODE_AUTO” and “SDMMC_SPEED_MODE_HIGH” SD card speed modes in case of no transceiver present</li>
</ul></li>
</ul></li>
<li><strong>LL SDMMC</strong>:
<ul>
<li>Update “SDMMC_InitTypeDef” structure to add “TranceiverPresent” field in case of the define “USE_SD_TRANSCEIVER” is not zero:
<ul>
<li>This parameter allows to handle 2 SD instances with different settings regarding the transceiver presence as described above</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL RCC</strong>:
<ul>
<li>stm32h7xx_ll_rcc.h:
<ul>
<li>Add suffix “LL_RCC” to private defines “REG_SHIFT”, “POS_SHIFT”, “CONFIG_SHIFT” and “MASK_SHIFT” according to the STM32Cube coding rules and to avoid clash with other modules defines if any</li>
</ul></li>
<li>stm32h7xx_hal_rcc.c:
<ul>
<li>Update “HAL_RCC_DeInit” API implementation to “uwTickPrio” variable when calling “HAL_InitTick” instead of the define “TICK_INT_PRIORITY” . The variable “uwTickPrio” maintains the last user Tick priority configuration where the “TICK_INT_PRIORITY” define is the initial Tick priority applied during the “HAL_Init”</li>
</ul></li>
<li>stm32h7xx_hal_rcc_ex.c:
<ul>
<li>Update “HAL_RCCEx_GetPeriphCLKFreq” API implementation to add support of the SDMMC peripheral clock frequency calculation</li>
</ul></li>
</ul></li>
<li><strong>HAL TIM</strong>:
<ul>
<li>stm32h7xx_hal_tim.h:
<ul>
<li>Add "__HAL_TIM_ENABLE_OCxFAST" and "__HAL_TIM_DISABLE_OCxFAST" macros allowing respectively to enable/disable the fast mode for a given channel</li>
</ul></li>
<li>stm32h7xx_hal_tim_ex.h:
<ul>
<li>Rename the timer remapping “TIM_TIM1_ETR_ADC1_AWD1” to “TIM_TIM1_ETR_ADC1_AWD3” defines respectively to “TIM_TIM1_ETR_ADC2_AWD1” to TIM_TIM1_ETR_ADC2_AWD3 according to the reference manual (<strong>compatibility break</strong>)<br />
</li>
<li>Rename the timer remapping “TIM_TIM8_ETR_ADC1_AWD1” to “TIM_TIM8_ETR_ADC1_AWD3” defines respectively to “TIM_TIM8_ETR_ADC2_AWD1” to “TIM_TIM8_ETR_ADC2_AWD3” according to the reference manual (<strong>compatibility break</strong>)</li>
</ul></li>
<li>stm32h7xx_hal_tim.c:
<ul>
<li>Update “HAL_TIM_OnePulse_ConfigChannel” description to add details about usage of "__HAL_TIM_ENABLE_OCxFAST" to output a waveform with a minimum delay</li>
</ul></li>
<li>stm32h7xx_hal_tim_ex.c:
<ul>
<li>Update “HAL_TIMEx_ConfigBreakDeadTime” description to add details about interrupts enabling and generation</li>
</ul></li>
</ul></li>
<li><strong>HAL UART</strong>:
<ul>
<li>Update to add UART Receiver timeout management (RTOF)</li>
<li>stm32h7xx_hal_uart.h:
<ul>
<li>Add definition of error code “HAL_UART_ERROR_RTO”</li>
<li>Add definition of “UART_FLAG_RTOF” flag</li>
<li>Add definition of “UART_IT_RTO” interrupt</li>
<li>Add definition of “UART_CLEAR_RTOF” clear flag</li>
<li>Add prototypes of APIs “HAL_UART_ReceiverTimeout_Config”, “HAL_UART_EnableReceiverTimeout” and “HAL_UART_DisableReceiverTimeout”</li>
</ul></li>
<li>stm32h7xx_hal_uart.c:
<ul>
<li>Update description of “HAL_UART_Transmit_XXX”, “HAL_UART_Receive_XXX” APIs with more details about the data size management</li>
<li>Update “HAL_UART_IRQHandler” to support RTOF flag</li>
<li>Add implementation of “HAL_UART_ReceiverTimeout_Config”, “HAL_UART_EnableReceiverTimeout” and “HAL_UART_DisableReceiverTimeout” APIs</li>
</ul></li>
</ul></li>
<li><strong>HAL USB</strong>:
<ul>
<li>stm32h7xx_hal_hcd.c
<ul>
<li>Update “HAL_HCD_HC_SubmitRequest” to avoid enabling do_ping during host setup</li>
<li>Update “HCD_Port_IRQHandler” implementation to fix fast host plug/inplug issue:
<ul>
<li>This update is to be used with rework done on the USB MW host process to fix process hangs during enumeration phase. The USB MW rework is part of the host USB library V3.3.3</li>
</ul></li>
</ul></li>
<li>stm32h7xx_hal_pcd.c
<ul>
<li>Update “HAL_PCD_IRQHandler” to remove useless initialization of epnum variable in HAL_PCD_IRQHandler() for OTG instance</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL USART</strong>:
<ul>
<li>stm32h7xx_hal_usart.c:
<ul>
<li>Update description of “HAL_USART_Transmit_XXX”, “HAL_USART_Receive_XXX” APIs with more details about the data size management</li>
</ul></li>
<li>stm32h7xx_ll_usart.h:
<ul>
<li>Update “LL_USART_SetBaudRate” implementation to avoid overflow in “USART_PRESCALER_TAB” table</li>
</ul></li>
</ul></li>
<li><strong>LL SYSTEM</strong>:
<ul>
<li>stm32h7xx_ll_system.h:
<ul>
<li>Add APIs “LL_ART_Enable”, “LL_ART_Disable”, “LL_ART_IsEnabled” and “LL_ART_SetBaseAddress” allowing to enable/disable and configure the Cortex-M4 “ART” instruction cache</li>
</ul></li>
</ul></li>
</ul>
<h2 id="known-limitations-3">Known Limitations</h2>
<ul>
<li>None</li>
</ul>
<h2 id="backward-compatibility-3">Backward compatibility</h2>
<ul>
<li><strong>HAL TIM</strong>:
<ul>
<li>Rename the timer remapping “TIM_TIM1_ETR_ADC1_AWD1” to “TIM_TIM1_ETR_ADC1_AWD3” defines respectively to “TIM_TIM1_ETR_ADC2_AWD1” to TIM_TIM1_ETR_ADC2_AWD3 according to the reference manual<br />
</li>
<li>Rename the timer remapping “TIM_TIM8_ETR_ADC1_AWD1” to “TIM_TIM8_ETR_ADC1_AWD3” defines respectively to “TIM_TIM8_ETR_ADC2_AWD1” to “TIM_TIM8_ETR_ADC2_AWD3” according to the reference manual</li>
</ul></li>
<li><strong>LL HRTIM</strong>:
<ul>
<li>Replace “LL_HRTIM_OUTPUTSET_NONE” to LL_HRTIM_OUTPUTSET_UPDATE defines by “LL_HRTIM_CROSSBAR_NONE” to “LL_HRTIM_CROSSBAR_UPDATE”</li>
</ul></li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true"><strong>V1.5.0 / 05-April-2019</strong></label>
<div>
<h2 id="main-changes-4">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements</li>
<li>Add support for VOS0 power regulator voltage scaling with 480MHz over clock</li>
<li>Add support of STM32H7 <strong>Rev.V</strong> (All HAL and LL drivers remains compatible with STM32H7 <strong>Rev.Y</strong>)</li>
<li>Update HAL/LL drivers to be <strong>MISRA-C 2012</strong> compliant</li>
<li>Add <strong>DUAL CORE</strong> support/APIs for system peripherals HAL and LL drivers(COMP, CORTEX, ETH, EXTI, FLASH, GPIO, HSEM, MDIOS, PWR, RCC, RTC)
<ul>
<li><strong>DUAL CORE</strong> features are delimited by the define <strong>“DUAL_CORE”</strong>, this define is automatically available when using a <strong>DUAL CORE</strong> device through the stm32h7XYxx CMSIS device include files</li>
</ul></li>
<li>Update HAL/LL PWR driver to support Step Down Convector regulator (SMPS) available on <strong>DUAL CORE</strong> lines</li>
<li><strong>HAL</strong>: generic
<ul>
<li>stm32h7xx_hal.h :
<ul>
<li>Add support STM32H7 <strong>Rev.V</strong></li>
<li>Add support of <strong>DUAL CORE</strong> lines</li>
<li>Add SYSCFG break macros allowing to break TIM1/8/15/16/17 and HRTIMER following a given RAM or a FLASH double ECC error, or Cortex-M7/M4 lockup.</li>
</ul></li>
<li>stm32h7xx_hal_conf_template.h:
<ul>
<li>Add support of DSI peripheral(available on STM32H747xx and STM32H757xx lines)</li>
<li>Add definition of LSI oscillator value(LSI_VALUE)</li>
</ul></li>
<li>stm32h7xx_hal.c :
<ul>
<li>Update HAL_Init APIs to get the SystemCoreClock(Cortex-M7 clock) and SystemD2Clock(D2 domain clock) values:
<ul>
<li>Useful to update these values when the system clock settings are done but the other Cortex on a <strong>DUAL CORE</strong> device</li>
</ul></li>
<li>Update HAL_InitTick to support both Cortex-M7 and Cortex-M4 SYSTICK configuration</li>
<li>Add <strong>DUAL CORE</strong> APIs:
<ul>
<li>Boot address and configuration APIs: HAL_SYSCFG_CM4BootAddConfig, HAL_SYSCFG_EnableCM7BOOT, HAL_SYSCFG_DisableCM7BOOT, HAL_SYSCFG_EnableCM4BOOT and HAL_SYSCFG_DisableCM4BOOT</li>
<li>Debug APIs: HAL_EnableDomain2DBGSleepMode, HAL_DisableDomain2DBGSleepMode, HAL_EnableDomain2DBGStopMode, HAL_DisableDomain2DBGStopMode HAL_EnableDomain2DBGStandbyMode and HAL_DisableDomain2DBGStandbyMode</li>
<li>EXTI APIs: HAL_EXTI_D2_ClearFlag and HAL_EXTI_D2_EventInputConfig</li>
</ul></li>
</ul></li>
<li>Add stm32h7xx_hal_msp_template.c file: MSP template source file</li>
<li>Add HAL time base template files: stm32h7xx_hal_timebase_rtc_alarm_template.c, stm32h7xx_hal_timebase_rtc_wakeup_template.c and stm32h7xx_hal_timebase_tim_template.c</li>
</ul></li>
<li><strong>HAL ADC</strong>:
<ul>
<li>Update to support STM32H7 <strong>Rev.V</strong> : 8bits resolution settings.</li>
<li>Remove inconsistent definition of flags ADC_FLAG_AWD and ADC_FLAG_ALL</li>
</ul></li>
<li><strong>HAL COMP</strong>:
<ul>
<li>Update to support <strong>DUAL CORE</strong> lines:
<ul>
<li>Add __HAL_COMP_COMP1_EXTID2_ENABLE_IT/EVENT macros to enable an COMP1 EXTI IT/Event for Cortex-M4</li>
<li>Add __HAL_COMP_COMP1_EXTID2_DISABLE_IT/EVENT macros to disable an COMP1 EXTI IT/Event for Cortex-M4</li>
<li>Add __HAL_COMP_COMP1_EXTID2_GET_FLAG and __HAL_COMP_COMP1_EXTID2_CLEAR_FLAG macros to get/clear COMP1 EXTI flag for Cortex-M4</li>
<li>Add __HAL_COMP_COMP2_EXTID2_ENABLE_IT/EVENT macros to enable an COMP2 EXTI IT/Event for Cortex-M4</li>
<li>Add __HAL_COMP_COMP2_EXTID2_DISABLE_IT/EVENT macros to disable an COMP2 EXTI IT/Event for Cortex-M4</li>
<li>Add __HAL_COMP_COMP2_EXTID2_GET_FLAG and __HAL_COMP_COMP2_EXTID2_CLEAR_FLAG macros to get/clear COMP2 EXTI flag for Cortex-M4</li>
<li>Update HAL_COMP_Init function : don’t enable the EXTI IT and event in case of <strong>DUAL CORE</strong>. User may the use either __HAL_COMP_COMP1_EXTI_ENABLE_IT/EVENT or __HAL_COMP_COMP1_EXTID2_ENABLE_IT/EVENT to enable the IT/event for either Cortex-M7 or Cortex-M4</li>
</ul></li>
</ul></li>
<li><strong>HAL CORTEX</strong>:
<ul>
<li>Update “CORTEX MPU Region Number” define for <strong>DUAL CORE</strong> lines:
<ul>
<li>Cortex-M4: 8 MPU regions available</li>
<li>Cortex-M7 (or single core): 16 MPU regions available</li>
</ul></li>
<li>Add definition of Cortex-M5 CPU ID (CM4_CPUID)</li>
<li>Update HAL_GetCurrentCPUID API to support Cortex-M7 and Cortex-M4</li>
</ul></li>
<li><strong>HAL DSI</strong>:
<ul>
<li>Introduce HAL DSI driver:stm32h7xx_hal_dsi.h and stm32h7xx_hal_dsi.c (DSI peripheral is available on STM32H747xx and STM32H757xx lines only)</li>
</ul></li>
<li><strong>HAL ETH</strong>:
<ul>
<li>stm32h7xx_hal_eth.h:
<ul>
<li>Update ETH_DMADescTypeDef definition: remove packing to avoid byte access(as all fields of this structure are UINT32)</li>
</ul></li>
<li>stm32h7xx_hal_eth.c:
<ul>
<li>Fix ETH_DMARxDescListInit function to support the case when Ethernet packet is split into more than one descriptor by:
<ul>
<li>Clearing the ETH_DMATXNDESCRF_LD bit of previous descriptor</li>
<li>Clearing the ETH_DMATXNDESCRF_FD bit of new descriptor to indicate that this descriptor is not the first segment of the packet</li>
</ul></li>
<li>Fix HAL_ETH_GetRxDataBuffer and HAL_ETH_IRQHandler functions for better robustness when mass receiving UDP/TCPIP packets:
<ul>
<li>HAL_ETH_IRQHandler : Remove call to HAL_ETH_IsRxDataAvailable when RX Interrupt occurs as it may update the RX DMA descriptors while the last received data is being proceeded by TCPIP stack/Application: in this case data will be lost or corrupted</li>
</ul></li>
<li>HAL_ETH_GetRxDataLength: Update descriptor informations (descidx and dmarxdesc) with the last values returned by HAL_ETH_IsRxDataAvailable() when new data is available</li>
</ul></li>
<li>Update to support <strong>DUAL CORE</strong> lines:
<ul>
<li>Add __HAL_ETH_WAKEUP_EXTID2_ENABLE_IT macro to enable ETH wakeup EXTI for Cortex-M4</li>
<li>Add __HAL_ETH_WAKEUP_EXTID2_GET_FLAG and __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG macros to get/clear ETH wakeup EXTI flag for Cortex-M4</li>
<li>Update HAL_ETH_IRQHandler function to get/clear ETH wakeup EXTI flag depending of the current CPU(Cortex-M4 or Cortex-M7)</li>
</ul></li>
</ul></li>
<li><strong>HAL EXTI</strong>:
<ul>
<li>Update to support <strong>DUAL CORE</strong> lines:
<ul>
<li>stm32h7xx_hal_exti.h:
<ul>
<li>Add <strong>DUAL CORE</strong> EXTI lines definition</li>
<li>Add EXTI_MODE_CORE1_INTERRUPT/EVENT, EXTI_MODE_CORE2_INTERRUPT/EVENT modes definition</li>
</ul></li>
<li>stm32h7xx_hal_exti.c:
<ul>
<li>Update to support EXTI lines on both Cortex-M7/Cortex-M4: APIs HAL_EXTI_SetConfigLine, HAL_EXTI_GetConfigLine, HAL_EXTI_ClearConfigLine, HAL_EXTI_IRQHandler, HAL_EXTI_GetPending and HAL_EXTI_ClearPending</li>
</ul></li>
</ul></li>
</ul></li>
<li><strong>HAL FLASH</strong>:
<ul>
<li>Update to support STM32H7 <strong>Rev.V</strong> devices</li>
<li>Add support of CRC calculation feature</li>
<li>Update to support <strong>DUAL CORE</strong> lines:
<ul>
<li>FLASH_OBProgramInitTypeDef structure: add CM4BootConfig, CM4BootAddr0 and CM4BootAddr1 for Cortex-M4 boot configuration</li>
<li>Add definitions for <strong>DUAL CORE</strong> lines option bytes:
<ul>
<li>OPTIONBYTE_CM7_BOOTADD, OPTIONBYTE_CM4_BOOTADD, OB_BCM7_DISABLE, OB_BCM7_ENABLE, OB_BCM4_DISABLE, OB_BCM4_ENABLE, OB_IWDG2_SW, OB_IWDG2_HW, OB_STOP_RST_D2, OB_STOP_NO_RST_D2, OB_STDBY_RST_D2, OB_STDBY_NO_RST_D2</li>
<li>Update HAL_FLASHEx_OBProgram, HAL_FLASHEx_OBGetConfig, FLASH_OB_UserConfig, FLASH_OB_BootAddConfig and FLASH_OB_GetBootAdd functions according to the new option bytes</li>
<li>Add FLASH_OB_CM4BootAddConfig and FLASH_OB_GetCM4BootAdd functions for Cortex-M4 boot address configuration</li>
</ul></li>
</ul></li>
<li>Enhance the HAL_FLASH_Program/HAL_FLASH_Program_IT implementation by adding Add ISB/DSB instructions:
<ul>
<li>Between programming enabling (Bit FLASH_CR_PG set to 1) and writing a flash word</li>
<li>Between the flash word writing and the wait for the programming operation to end</li>
</ul></li>
<li>Fix FLASH_OB_GetRDP APIs to return the correct value in case of RDP level 1</li>
</ul></li>
<li><strong>HAL GPIO</strong>:
<ul>
<li>Add definition of new AF available in STM32H7 <strong>Rev.V</strong> devices:
<ul>
<li>GPIO_AF0_C1DSLEEP, GPIO_AF0_C1DSLEEP, GPIO_AF0_C1SLEEP, GPIO_AF0_D1PWREN, GPIO_AF0_D2PWREN, GPIO_AF0_C2DSLEEP, GPIO_AF0_C2SLEEP, GPIO_AF13_CRS_SYNC and GPIO_AF13_DSI</li>
</ul></li>
<li>Update to support <strong>DUAL CORE</strong> lines:
<ul>
<li>Update to support EXTI lines on both Cortex-M7/Cortex-M4 when a GPIO is configured in IT:EVENT mode : APIs HAL_GPIO_Init, HAL_GPIO_DeInit and HAL_GPIO_EXTI_IRQHandler</li>
</ul></li>
</ul></li>
<li><strong>HAL HCD</strong>:
<ul>
<li>Fix HCD_HC_OUT_IRQHandler function to ensure setting the correct toggle for OUT interrupt during transfer complete</li>
</ul></li>
<li><strong>HAL I2S</strong>:
<ul>
<li>Fully reworked HAL I2S driver to fix issues and limitations and for MISRA-C 2012 compliance</li>
</ul></li>
<li><strong>HAL LPTIM</strong>:
<ul>
<li>Update LPTIM_Disable function to use RCC defines instead of hard coded zero values</li>
</ul></li>
<li><strong>HAL LTDC</strong>:
<ul>
<li>Add stm32h7xx_hal_ltdc_ex.c and stm32h7xx_hal_ltdc_ex.h files allowing to use the LTDC and DSI peripherals together</li>
</ul></li>
<li><strong>HAL MDIO</strong>:
<ul>
<li>Update to support <strong>DUAL CORE</strong> lines:
<ul>
<li>Add __HAL_MDIOS_WAKEUP_EXTID2_ENABLE_IT macro allowing to enable MDIO EXTI IT for Cortex-M4</li>
<li>Add __HAL_MDIOS_WAKEUP_EXTID2_GET_FLAG and __HAL_MDIOS_WAKEUP_EXTID2_CLEAR_FLAG macros allowing to get:clear MDIO EXTI flag for Cortex-M4</li>
<li>Update HAL_MDIOS_IRQHandler function to support MDIO EXTI flag clearing for Cortex-M7 or Cortex-M4 (depending of the current CPU)</li>
</ul></li>
</ul></li>
<li><strong>HAL MMC</strong>:
<ul>
<li>Implementation enhancement of APIs HAL_MMC_ReadBlocks/_IT/_DMA, HAL_MMC_WriteBlocks/_IT/_DMA, HAL_MMC_IRQHandler and HAL_MMC_Abort</li>
</ul></li>
<li><strong>HAL PCD</strong>:
<ul>
<li>Cleanup and fix USB PCD interrupt handler to handle EP0OUT transfers in USB DMA mode</li>
<li>Fix and enhancement of BCD (Battery Charging) feature</li>
<li>Fix and enhancement to power-up the internal FS transceiver when the BCD discovery is completed</li>
</ul></li>
<li><strong>HAL PWR</strong>:
<ul>
<li>Update to support VOS0 power regulator voltage scaling :
<ul>
<li>Add definition of PWR_REGULATOR_VOLTAGE_SCALE0</li>
<li>Update __HAL_PWR_VOLTAGESCALING_CONFIG macro for VOS0 support</li>
</ul></li>
<li>Update to support <strong>DUAL CORE</strong> lines:
<ul>
<li>File stm32h7xx_hal_pwr.h:
<ul>
<li>add definition of following flags:
<ul>
<li>PWR_FLAG_CPU_HOLD (Cortex-M7 hold boot flag), PWR_FLAG_CPU2_HOLD (Cortex-M4 hold boot flag), PWR_FLAG2_STOP (Cortex-M4 system stop flag), PWR_FLAG2_SB_D1 (Cortex-M4 D1 standby flag), PWR_FLAG2_SB_D2 (Cortex-M4 D2 standby flag), PWR_FLAG2_SB (Cortex-M4 system standby flag)</li>
</ul></li>
<li>Update __HAL_PWR_GET_FLAG and __HAL_PWR_CLEAR_FLAG macros implementation with new above flags</li>
<li>Update __HAL_PWR_PVD_XXX macros for D2 domain (Cortex-M4)</li>
</ul></li>
<li>File stm32h7xx_hal_pwr_ex.h
<ul>
<li>Add PWR_CORE_CPU1 and PWR_CORE_CPU2: PWR cores definitions respectively relative to Cortex-M7 and Cortex-M4</li>
<li>Add support for SMPS PWR supply regulator (note that SMPS regulator is available on <strong>DUAL CORE</strong> lines only)</li>
<li>Update __HAL_PWR_AVD_XXX macros for D2 domain (Cortex-M4)</li>
</ul></li>
<li>File stm32h7xx_hal_pwr.c
<ul>
<li>Update functions HAL_PWR_ConfigPVD, HAL_PWR_EnterSTOPMode, HAL_PWR_EnterSTANDBYMode and HAL_PWR_PVD_IRQHandler
<ul>
<li>Add CPU2(Cortex-M4) domains power configuration</li>
</ul></li>
</ul></li>
<li>File stm32h7xx_hal_pwr_ex.c
<ul>
<li>Update HAL_PWREx_EnterSTOPMode, HAL_PWREx_ClearPendingEvent, HAL_PWREx_EnterSTANDBYMode, HAL_PWREx_ConfigD3Domain, HAL_PWREx_EnableWakeUpPin, HAL_PWREx_ConfigAVD and HAL_PWREx_PVD_AVD_IRQHandler to consider <strong>DUAL CORE</strong> lines: Cortex-M4 versus power domains settings</li>
<li>Introduce HAL_PWREx_HoldCore API: allowing to hold a CPU (Cortex-M7 or Cortex-M4) when exiting from STOP mode</li>
<li>Introduce HAL_PWREx_ReleaseCore API: allowing to release a holden CPU(Cortex-M7 or Cortex-M4) after a wake-up from STOP</li>
<li>Update HAL_PWREx_ConfigSupply function implementation to support SMPS power regulator</li>
</ul></li>
</ul></li>
</ul></li>
<li><strong>HAL RAMECC</strong>:
<ul>
<li>Fix typo in HAL_RAMECC_EnableNotification and HAL_RAMECC_DisableNotification APIs naming</li>
</ul></li>
<li><strong>HAL RCC</strong>:
<ul>
<li>Update to support <strong>DUAL CORE</strong> lines:
<ul>
<li>stm32h7xx_hal_rcc.h:
<ul>
<li>Add <strong>DUAL CORE</strong> reset flags: RCC_FLAG_C1RST, RCC_FLAG_C2RST, RCC_FLAG_SFTR1ST, RCC_FLAG_SFTR2ST, RCC_FLAG_WWDG2RST and RCC_FLAG_IWDG2RST</li>
<li>Add Cortex-M4 ART clock enable/disable macros: __HAL_RCC_ART_CLK_ENABLE, __HAL_RCC_ART_CLK_DISABLE, and __HAL_RCC_ART_IS_CLK_ENABLED</li>
<li>Add Cortex-M4 ART force/release reset macros: __HAL_RCC_ART_FORCE_RESET and __HAL_RCC_ART_RELEASE_RESET</li>
<li>Add DSI clock enable/disable macros: __HAL_RCC_DSI_CLK_ENABLE, __HAL_RCC_DSI_CLK_DISABLE, __HAL_RCC_DSI_IS_CLK_ENABLED and __HAL_RCC_DSI_IS_CLK_DISABLED</li>
<li>Add DSI force/release reset macros: __HAL_RCC_DSI_FORCE_RESET and __HAL_RCC_DSI_RELEASE_RESET</li>
<li>Add DSI sleep clock enable/disable macros: __HAL_RCC_DSI_CLK_SLEEP_ENABLE, __HAL_RCC_DSI_CLK_SLEEP_DISABLE and __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED and __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED</li>
<li>Add WWDG2 enable/disable macros: __HAL_RCC_WWDG2_CLK_ENABLE, __HAL_RCC_WWDG2_CLK_DISABLE, __HAL_RCC_WWDG2_IS_CLK_ENABLED and __HAL_RCC_WWDG2_IS_CLK_DISABLED</li>
<li>Add WWDG2 sleep clock enable/disable macros : __HAL_RCC_WWDG2_CLK_SLEEP_ENABLE, __HAL_RCC_WWDG2_CLK_SLEEP_DISABLE, __HAL_RCC_WWDG2_IS_CLK_SLEEP_ENABLED and __HAL_RCC_WWDG2_IS_CLK_SLEEP_DISABLED</li>
<li>Add peripherals _HAL_RCC_C1_PPP_CLK_ENABLE macros: allowing to enable/allocate a peripheral clock for Cortex-M7</li>
<li>Add peripherals _HAL_RCC_C1_PPP_CLK_DISABLE macros: allowing to disable/deallocate a peripheral clock for Cortex-M7</li>
<li>Add peripherals _HAL_RCC_C2_PPP_CLK_ENABLE macros: allowing to enable/allocate a peripheral clock for Cortex-M4</li>
<li>Add peripherals _HAL_RCC_C2_PPP_CLK_DISABLE macros: allowing to disable/deallocate a peripheral clock for Cortex-M4</li>
<li>Add peripherals _HAL_RCC_C2_PPP_CLK_DISABLE macros: allowing to disable/deallocate a peripheral clock for Cortex-M4</li>
<li>Add peripherals __HAL_RCC_C1_PPP_CLK_SLEEP_ENABLE/DISABLE macros: allowing to enable/allocate or disable a peripheral sleep clock for Cortex-M7</li>
<li>Add peripherals __HAL_RCC_C2_PPP_CLK_SLEEP_ENABLE/DISABLE macros: allowing to enable/allocate or disable a peripheral sleep clock for Cortex-M4</li>
<li>Add __HAL_RCC_C1_CLEAR_RESET_FLAGS and __HAL_RCC_C1_GET_FLAG: allowing to get/reset an RCC flag for Cortex-M7</li>
<li>Add __HAL_RCC_C2_CLEAR_RESET_FLAGS and __HAL_RCC_C2_GET_FLAG: allowing to get/reset an RCC flag for Cortex-M4</li>
</ul></li>
<li>stm32h7xx_hal_rcc_ex.h:
<ul>
<li>Add __HAL_RCC_DSI_CONFIG and __HAL_RCC_GET_DSI_SOURCE macros allowing to configure and get the DSI source clock</li>
</ul></li>
<li>stm32h7xx_hal_rcc_ex.c:
<ul>
<li>Update HAL_RCCEx_PeriphCLKConfig and HAL_RCCEx_GetPeriphCLKConfig functions to add DSI peripheral clock configuration</li>
<li>Add HAL_RCCEx_EnableBootCore allowing to enable Cortex-M7 or Cortex-M4 boot independently from FLASH option bytes</li>
<li>Update HAL_RCCEx_WWDGxSysResetConfig to generate system reset using WWDG1 or WWDG2</li>
</ul></li>
</ul></li>
<li>Update __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST macro to support STM32H7 <strong>Rev.V</strong> and <strong>Rev.Y</strong></li>
<li>Update __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST macro to support STM32H7 <strong>Rev.V</strong> and <strong>Rev.Y</strong></li>
<li>Update __HAL_RCC_LSEDRIVE_CONFIG macro to support STM32H7 <strong>Rev.V</strong> and <strong>Rev.Y</strong></li>
<li>Update HAL_RCC_GetOscConfig function to support STM32H7 <strong>Rev.V</strong> and <strong>Rev.Y</strong></li>
<li>Fix HSITRIM value reset value in HAL_RCC_DeInit function</li>
<li>Update HAL_RCC_OscConfig to disable PLLFRACN before applying a new value</li>
<li>Update HAL_RCCEx_CRSConfig to support STM32H7 <strong>Rev.V</strong> and <strong>Rev.Y</strong></li>
<li>Add USB2 OTG FS ULPI macros: __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE, __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE, __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_ENABLED, __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_DISABLED __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE, __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE, __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_ENABLED and __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_DISABLED</li>
</ul></li>
<li><strong>HAL RTC</strong>:
<ul>
<li>Update to support <strong>DUAL CORE</strong> lines:
<ul>
<li>stm32h7xx_hal_rtc.h:
<ul>
<li>Add __HAL_RTC_ALARM_EXTID2_ENABLE_IT and __HAL_RTC_ALARM_EXTID2_DISABLE_IT macros : allowing to enable/disable generating EXTI IT for D2 Domain/Cortex-M4 upon an RTC ALARM</li>
<li>Add __HAL_RTC_ALARM_EXTID2_ENABLE_EVENT and __HAL_RTC_ALARM_EXTID2_DISABLE_EVENT macros: allowing to enable/disable generating EXTI EVENT for D2 Domain/Cortex-M4 upon an RTC ALARM</li>
<li>Add __HAL_RTC_ALARM_EXTID2_GET_FLAG and __HAL_RTC_ALARM_EXTID2_CLEAR_FLAG macros: allowing to get/clear EXTI RTC ALARM flag</li>
</ul></li>
<li>stm32h7xx_hal_rtc_ex.h:
<ul>
<li>Add __HAL_RTC_WAKEUPTIMER_EXTID2_ENABLE_IT and __HAL_RTC_WAKEUPTIMER_EXTID2_DISABLE_IT macros: allowing to enable/disable generating EXTI IT for D2 Domain/Cortex-M4 upon an RTC WakeUp</li>
<li>Add __HAL_RTC_WAKEUPTIMER_EXTID2_ENABLE_EVENT and __HAL_RTC_WAKEUPTIMER_EXTID2_DISABLE_EVENT macros: allowing to enable/disable generating EXTI EVENT for D2 Domain/Cortex-M4 upon an RTC WakeUp</li>
<li>Add __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_GET_FLAG and __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_CLEAR_FLAG macros: allowing to get/clear EXTI RTC TIMESTAMP flag</li>
</ul></li>
<li>stm32h7xx_hal_rtc.c:
<ul>
<li>Update HAL_RTC_AlarmIRQHandler function to support EXTI IT clearing for Cortex-M7 or Cortex-M4</li>
</ul></li>
<li>stm32h7xx_hal_rtc_ex.c:
<ul>
<li>Update HAL_RTCEx_SetTimeStamp_IT function : don’t enable the EXTI IT in case of <strong>DUAL CORE</strong>. User may the use either __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT or __HAL_RTC_ALARM_EXTID2_ENABLE_IT to enable the IT for either Cortex-M7 or Cortex-M4</li>
<li>Update HAL_RTCEx_TamperTimeStampIRQHandler function to support EXTI IT clearing for Cortex-M7 or Cortex-M4</li>
</ul></li>
</ul></li>
</ul></li>
<li><strong>HAL SAI</strong>:
<ul>
<li>Update to support STM32H7 <strong>Rev.V</strong>:
<ul>
<li>SAI_InitTypeDef structure: Add filed MckOutput field (specific for STM32H7 <strong>Rev.V</strong> devices) allowing to select whether master clock output will be generated or not</li>
<li>Update HAL_SAI_Init function in order to apply MckOutput field of the init structure for STM32H7 <strong>Rev.V</strong> devices (<strong>Rev.B</strong> and above)</li>
</ul></li>
<li>Fix register callback management for ErrorCallback in HAL_SAI_IRQHandler function</li>
</ul></li>
<li><strong>HAL SD</strong>:
<ul>
<li>Update to add support of DDR mode</li>
<li>Update to fix behavior of uSD cards v1.x</li>
</ul></li>
<li><strong>HAL TIM</strong>:
<ul>
<li>Align DMA Burst defines with the reference manual: Remove TIM_DMABASE_OR definition Add TIM_DMABASE_TISEL definition</li>
</ul></li>
<li><strong>LL ADC</strong>:
<ul>
<li>Update to support STM32H7 <strong>Rev.V</strong> :
<ul>
<li>Add definition for boost mode ranges supported by the STM32H7 <strong>Rev.V</strong>:
<ul>
<li>LL_ADC_BOOST_MODE_6MHZ25, LL_ADC_BOOST_MODE_12MHZ5, LL_ADC_BOOST_MODE_20MHZ, LL_ADC_BOOST_MODE_25MHZ and LL_ADC_BOOST_MODE_50MHZ</li>
</ul></li>
<li>Update LL_ADC_SetResolution and LL_ADC_GetResolution APIs to support STM32H7 <strong>Rev.V</strong> and STM32H7 <strong>Rev.Y</strong> (8bits resolution settings)</li>
<li>Update LL_ADC_SetBoostMode and LL_ADC_GetBoostMode APIs to support STM32H7 <strong>Rev.V</strong> and STM32H7 <strong>Rev.Y</strong></li>
</ul></li>
</ul></li>
<li><strong>LL EXTI</strong>:
<ul>
<li>Update to support <strong>DUAL CORE</strong> lines:
<ul>
<li>stm32h7xx_ll_exti.c:
<ul>
<li>Update LL_EXTI_Init and LL_EXTI_DeInit APIs to support configuration of EXTI lines for Cortex-M7 and Cortex-M4 (C2)</li>
</ul></li>
<li>stm32h7xx_ll_exti.h:
<ul>
<li>Introduce definitions of LL_EXTI_MODE_C1_IT/EVENT/IT_EVENT and LL_EXTI_MODE_C2_IT/EVENT/IT_EVENT allowing to select EXTI modes for Cortex-M7(C1) or Cortex-M4(C2) or a combination of both</li>
<li>Introduce APIs to handle EXTI events for Cortex-M4: LL_C2_EXTI_EnableEvent_x_y, LL_C2_EXTI_DisableEvent_x_y and LL_C2_EXTI_IsEnabledEvent_x_y</li>
<li>Introduce APIs to handle EXTI interrupts for Cortex-M4: LL_C2_EXTI_EnableIT_x_y, LL_C2_EXTI_DisableIT_x_y and LL_C2_EXTI_IsEnabledIT_x_y</li>
<li>Introduce APIs o handle EXTI flags for Cortex-M4: LL_C2_EXTI_IsActiveFlag_x_y, LL_C2_EXTI_ReadFlag_x_y and LL_C2_EXTI_ClearFlag_x_y</li>
</ul></li>
</ul></li>
</ul></li>
<li><strong>LL HSEM</strong>:
<ul>
<li>Update to support <strong>DUAL CORE</strong> lines:
<ul>
<li>stm32h7xx_ll_hsem.h:
<ul>
<li>Add definition of LL_HSEM_COREID_CPU2</li>
<li>Add APIs to handle IT management for Cortex-M4: LL_HSEM_EnableIT_C2IER, LL_HSEM_DisableIT_C2IER and LL_HSEM_IsEnabledIT_C2IER</li>
<li>Add APIs to handle flags management for Cortex-M4: LL_HSEM_ClearFlag_C2ICR, LL_HSEM_IsActiveFlag_C2ISR and LL_HSEM_IsActiveFlag_C2MISR</li>
</ul></li>
</ul></li>
</ul></li>
<li><strong>LL PWR</strong>:
<ul>
<li>Update to support <strong>DUAL CORE</strong> lines:
<ul>
<li>Add CPU1/2 low power flags:
<ul>
<li>Add LL_PWR_FLAG_CPU2_CSSF flag definition: for CPU2(Cortex-M4) STANDBY, STOP and HOLD flags</li>
<li>Add LL_PWR_FLAG_SMPSEXTRDY flag definition: SMPS External supply ready flag</li>
<li>Add LL_PWR_FLAG_CPU_HOLD2F flag definition: CPU1(Cortex-M7) in hold wakeup flag</li>
<li>Add LL_PWR_FLAG_CPU2_SBF_D2 and LL_PWR_FLAG_CPU2_SBF_D1: respectively for D1/D2 CPU2(Cortex-M4) standby flags</li>
<li>Add LL_PWR_FLAG_CPU2_SBF flag definition: CPU2(Cortex-M4) system standby flag</li>
<li>Add LL_PWR_FLAG_CPU2_STOPF flag definition: CPU2(Cortex-M4) system stop flag</li>
<li>Add LL_PWR_FLAG_CPU2_HOLD1F flag definition: CPU2(Cortex-M4) in hold wakeup flag</li>
</ul></li>
<li>Add CPU2 low power modes:
<ul>
<li>Add LL_PWR_CPU2_MODE_D1STOP definition: Enter D1 domain to Stop mode when the CPU2(Cortex-M4) enters deep sleep</li>
<li>Add LL_PWR_CPU2_MODE_D1STANDBY definition: Enter D1 domain to Standby mode when the CPU2(Cortex-M4) enters deep sleep</li>
<li>Add LL_PWR_CPU2_MODE_D2STOP definition: Enter D2 domain to Stop mode when the CPU2(Cortex-M4) enters deep sleep</li>
<li>Add LL_PWR_CPU2_MODE_D2STANDBY definition: Enter D2 domain to Standby mode when the CPU2(Cortex-M4) enters deep sleep</li>
<li>Add LL_PWR_CPU2_MODE_D3STOP definition: Enter D3 domain to Stop mode when the CPU2(Cortex-M4) enters deep sleep</li>
<li>Add LL_PWR_CPU2_MODE_D3STANDBY definition: Enter D3 domain to Standby mode when the CPU2(Cortex-M4) enters deep sleep</li>
<li>Add LL_PWR_CPU2_MODE_D3RUN definition: Keep system D3 domain in RUN mode when the CPU2 enter deep sleep</li>
</ul></li>
<li>Add definition for <strong>DUAL CORE</strong> lines new SMPS and LDO power supply source configuration:
<ul>
<li>LL_PWR_DIRECT_SMPS_SUPPLY: Core domains are supplied from the SMPS regulator</li>
<li>LL_PWR_SMPS_1V8_SUPPLIES_LDO: The SMPS 1.8V output supplies the LDO which supplies the Core domains</li>
<li>LL_PWR_SMPS_2V5_SUPPLIES_LDO: The SMPS 2.5V output supplies the LDO which supplies the Core domains</li>
<li>LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO: The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO</li>
<li>LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO: The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO</li>
<li>LL_PWR_SMPS_1V8_SUPPLIES_EXT : The SMPS 1.8V output supplies an external source which supplies the Core domains</li>
<li>LL_PWR_SMPS_2V5_SUPPLIES_EXT : The SMPS 2.5V output supplies an external source which supplies the Core domains</li>
</ul></li>
<li>Update LL_PWR_ConfigSupply and LL_PWR_GetSupply APIs implementation to support new power supply sources on <strong>DUAL CORE</strong> lines</li>
<li>Add LL_PWR_CPU2_SetD1PowerMode and LL_PWR_CPU2_GetD1PowerMode APIs: allowing to Set/Get D1 domain low power mode when CPU2(Cortex-M4) goes to deep sleep mode</li>
<li>Add LL_PWR_CPU2_SetD2PowerMode and LL_PWR_CPU2_GetD2PowerMode APIs: allowing to Set/Get D2 domain low power mode when CPU2(Cortex-M4) goes to deep sleep mode</li>
<li>Add LL_PWR_CPU2_SetD3PowerMode and LL_PWR_CPU2_GetD3PowerMode APIs: allowing to Set/Get D3 domain low power mode when CPU2(Cortex-M4) goes to deep sleep mode</li>
<li>Add LL_PWR_HoldCPU1 , LL_PWR_ReleaseCPU1 and LL_PWR_IsCPU1Held APIs : allowing to Hold/Release CPU1(CoretxM7) when exiting from STOP mode</li>
<li>Add LL_PWR_HoldCPU2 , LL_PWR_ReleaseCPU2 and LL_PWR_IsCPU2Held APIs : allowing to Hold/Release CPU2(CoretxM4) when exiting from STOP mode</li>
<li>Add LL_PWR_CPU2_EnableD3RunInLowPowerMode LL_PWR_CPU2_DisableD3RunInLowPowerMode and LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode APIs: allowing to Set/Get D3 domain low power mode when CPU2(Cortex-M4) goes to deep sleep mode</li>
<li>Add LL_PWR_IsActiveFlag_SMPSEXT API: allowing to check the external SMPS supply ready flag</li>
<li>Add LL_PWR_IsActiveFlag_HOLD2 and LL_PWR_IsActiveFlag_HOLD1: allowing to get CPU2(Cortex-M4) and CPU1(Cortex-M7) HOLD flags</li>
<li>Add LL_PWR_CPU2_IsActiveFlag_STOP and LL_PWR_CPU2_IsActiveFlag_SB: allowing to get CPU2(Cortex-M4) Stop and standby flags</li>
<li>Add LL_PWR_CPU2_IsActiveFlag_SB_D1 API: allowing to get CPU2(Cortex-M4) D1 domain standby flag</li>
<li>Add LL_PWR_CPU2_IsActiveFlag_SB_D2 API: allowing to get CPU2(Cortex-M4) D2 domain standby flag</li>
<li>Add LL_PWR_ClearFlag_CPU2 API: allowing to clear CPU2(Cortex-M4) low power flags</li>
</ul></li>
</ul></li>
<li><strong>LL LPTIM</strong>:
<ul>
<li>Update LL_LPTIM_Init function to configure the LPTIM only when it is disabled, return ERROR if not</li>
</ul></li>
<li><strong>LL RCC</strong>:
<ul>
<li>Fix RCC registers reset values in LL_RCC_DeInit API</li>
<li>Add LL_RCC_GetDSIClockFreq, LL_RCC_SetDSIClockSource and LL_RCC_GetDSIClockSource APIs and LL_RCC_DSI_CLKSOURCE_PHY/LL_RCC_DSI_CLKSOURCE_PLL2Q/LL_RCC_DSI_CLKSOURCE defines for DSI peripheral</li>
<li>Update LL_RCC_HSI_GetCalibration, LL_RCC_HSI_SetCalibTrimming and LL_RCC_HSI_GetCalibTrimming to support HSI trimming on STM32H7 <strong>Rev.V</strong> and STM32H7 <strong>Rev.Y</strong></li>
<li>Update LL_RCC_CSI_GetCalibration, LL_RCC_CSI_SetCalibTrimming and LL_RCC_CSI_GetCalibTrimming to support CSI trimming and calibration on STM32H7 <strong>Rev.V</strong> and STM32H7 <strong>Rev.Y</strong></li>
<li>Update to support <strong>DUAL CORE</strong> lines:
<ul>
<li>Add WWDG2 APIs: LL_RCC_WWDG2_EnableSystemReset and LL_RCC_WWDG2_IsSystemReset</li>
<li>Add LL_RCC_ForceCM4Boot and LL_RCC_IsCM4BootForced APIs: to enable/check Cortex-M4 boot if hold by FLASH option byte BCM4</li>
<li>Add LL_RCC_ForceCM7Boot and LL_RCC_IsCM7BootForced APIs: to enable/check Cortex-M7 boot if hold by FLASH option byte BCM7</li>
<li>Update implementation of LL_RCC_IsActiveFlag_LPWRRST for <strong>DUAL CORE</strong> lines</li>
<li>Add API LL_RCC_IsActiveFlag_LPWR2RST to check D2 domain low power reset flag</li>
<li>Add LL_RCC_IsActiveFlag_WWDG2RST and LL_RCC_IsActiveFlag_IWDG2RST allowing to check WWD2 and IWDG2 reset flag</li>
<li>Update LL_RCC_IsActiveFlag_SFTRST implementation for <strong>DUAL CORE</strong> lines</li>
<li>Add LL_RCC_IsActiveFlag_SFT2RST API allowing to check SW reset flag for Cortex-M4</li>
<li>Update LL_RCC_IsActiveFlag_CPURST implementation for <strong>DUAL CORE</strong> lines</li>
<li>Add LL_RCC_IsActiveFlag_CPU2RST API allowing to check CPU2(Cortex-M4) reset flag</li>
<li>Add LL_C1/2_RCC_IsActiveFlag_LPWRRST and LL_C1/2_RCC_IsActiveFlag_LPWR2RST APIs: allowing to check D1 and D2 domain low power reset respectively for CoretxM7/M4</li>
<li>Add LL_C1/2_RCC_IsActiveFlag_WWDG1RST and LL_C1/2_RCC_IsActiveFlag_WWDG2RST APIs: allowing to check WWDG1 and WWDG2 reset flag respectively for CoretxM7/M4</li>
<li>Add LL_C1/2_RCC_IsActiveFlag_IWDG1RST and LL_C1/2_RCC_IsActiveFlag_IWDG2RST APIs: allowing to check IWDG1 and IWDG2 reset flag respectively for CoretxM7/M4</li>
<li>Add LL_C1/C2_RCC_IsActiveFlag_SFTRST APIs: allowing to check SW reset flag for respectively for Cortex-M7/M4</li>
<li>Add LL_C1/C2_RCC_IsActiveFlag_SFT2RST APIs: allowing to check SW reset flag 2 for respectively for Cortex-M7/M4</li>
<li>Add LL_C1/C2_RCC_IsActiveFlag_PORRST APIs: allowing to check POR/PDR reset flag for respectively for Cortex-M7/M4</li>
<li>Add LL_C1/C2_RCC_IsActiveFlag_PINRST APIs: allowing to check Pin reset flag for respectively for Cortex-M7/M4</li>
<li>Add LL_C1/C2_RCC_IsActiveFlag_D1RST APIs: allowing to check D1 domain reset flag for respectively for Cortex-M7/M4</li>
<li>Add LL_C1/C2_RCC_IsActiveFlag_D2RST APIs: allowing to check D2 domain reset flag for respectively for Cortex-M7/M4</li>
<li>Add LL_C1/C2_RCC_IsActiveFlag_CPURST APIs: allowing to check Cortex-M7 reset</li>
<li>Add LL_C1/C2_RCC_IsActiveFlag_CPU2RST APIs: allowing to check Cortex-M4 reset</li>
<li>Add LL_C1/C2_RCC_ClearResetFlags APIs: allowing to clear respectively Cortex-M7/M4 reset flags</li>
</ul></li>
</ul></li>
<li><strong>LL SDMMC</strong>:
<ul>
<li>Update to support DDR mode</li>
</ul></li>
<li><strong>LL SYSTEM</strong>:
<ul>
<li>Add new APIs to allow timers break source selection (new feature of STM32H7 devices <strong>Rev.V</strong>)</li>
<li>Update to support <strong>DUAL CORE</strong> lines:
<ul>
<li>Add LL_SYSCFG_IWDG2_SW_CONTROL_MODE and LL_SYSCFG_IWDG2_HW_CONTROL_MODE definition: for IWDG2 control mode</li>
<li>Add LL_SYSCFG_GetIWDG2ControlMode API allowing to select IWDG2 control mode at SYSCFG level</li>
<li>Update LL_SYSCFG_SetCM7BootAddress0/1 and LL_SYSCFG_GetCM7BootAddress0/1 APIs implementation for <strong>DUAL CORE</strong> : register bit naming change</li>
<li>Add LL_SYSCFG_SetCM4BootAddress0/1 and LL_SYSCFG_GetCM4BootAddress0/1 APIs for Cortex-M4 SYSCFG boot address setting</li>
<li>Add LL_SYSCFG_IsD2StandbyGenerateReset and LL_SYSCFG_IsD2StopGenerateReset APIs: allowing to check D2 domain SYSCFG Stop/Standby reset flag</li>
<li>Add LL_DBGMCU_EnableD2DebugInSleepMode and LL_DBGMCU_DisableD2DebugInSleepMode APIs: allowing to enable/disable D2 domain debug in sleep mode</li>
<li>Add LL_DBGMCU_EnableD2DebugInStopMode and LL_DBGMCU_DisableD2DebugInStopMode APIs: allowing to enable/disable D2 domain debug in stop mode</li>
<li>Add LL_DBGMCU_EnableD2DebugInStandbyMode and LL_DBGMCU_DisableD2DebugInStandbyMode APIs: allowing to enable/disable D2 domain debug in standby mode</li>
</ul></li>
</ul></li>
<li><strong>LL USB</strong>:
<ul>
<li>Cleanup and fix USB PCD to handle EP0OUT transfers in USB DMA mode</li>
<li>Fix and enhancement of BCD (Battery Charging) feature</li>
<li>Fix and enhancement to power-up the internal FS transceiver when the BCD discovery is completed</li>
</ul></li>
<li><strong>LL UTILS</strong>:
<ul>
<li>Update LL_Init1msTick and LL_SetSystemCoreClock description for <strong>DUAL CORE</strong> lines</li>
</ul></li>
</ul>
<h2 id="known-limitations-4">Known Limitations</h2>
<ul>
<li><strong>HAL SD</strong>:
<ul>
<li>The STM32H7xx devices provide two instances of the SDMMC peripheral, each instance could be configured with or without an external 1.8V/3.3V transceiver:
<ul>
<li>The STM32H7 HAL SD driver doesn’t support Mix configuration: i.e one instance with transceiver and the other one without</li>
</ul></li>
</ul></li>
<li><strong>HAL I2S</strong>:
<ul>
<li>Full duplex Transmit/receive feature not available</li>
</ul></li>
</ul>
<h2 id="backward-compatibility-4">Backward compatibility</h2>
<ul>
<li><strong>HAL ADC</strong>:
<ul>
<li>Backward compatibility break introduced since <strong>v1.4.0</strong> versus <strong>v1.3.x</strong> versions: In ADC_InitTypeDef structure, filed BoostMode is removed.</li>
</ul></li>
<li><strong>HAL IRDA</strong>:
<ul>
<li>Backward compatibility break introduced since <strong>v1.4.0</strong> versus <strong>v1.3.x</strong> versions:
<ul>
<li>Alignment with STM32F7/L4/G0 (for inter STM32 families portability)</li>
<li>Add new field “ClockPrescaler” to “IRDA_InitTypeDef” structure"</li>
</ul></li>
</ul></li>
<li><strong>HAL SMARTCARD</strong>:
<ul>
<li>Backward compatibility break introduced since <strong>v1.4.0</strong> versus <strong>v1.3.x</strong> versions:
<ul>
<li>Alignment with STM32F7/L4/G0 (for inter STM32 families portability)</li>
<li>Remove fields “FIFOMode”, “TXFIFOThreshold” and “RXFIFOThreshold” from “SMARTCARD_InitTypeDef” structure</li>
<li>Add new field “ClockPrescaler” to “SMARTCARD_InitTypeDef” structure"</li>
<li>SMARTCARD RXFIFO and TXFIFO threshold level defines moved to “stm32h7xx_hal_smartcard_ex.h”</li>
</ul></li>
</ul></li>
<li><strong>HAL UART</strong>:
<ul>
<li>Backward compatibility break introduced since <strong>v1.4.0</strong> versus <strong>v1.3.x</strong> versions:
<ul>
<li>Alignment with STM32F7/L4/G0 (for inter STM32 families portability)</li>
<li>Field “Prescaler” of structure “UART_InitTypeDef” renamed to ClockPrescaler</li>
<li>remove fields “FIFOMode”, “TXFIFOThreshold” and “RXFIFOThreshold” from “UART_InitTypeDef” structure</li>
<li>UART RXFIFO and TXFIFO threshold level defines moved to “stm32h7xx_hal_uart_ex.h”</li>
</ul></li>
</ul></li>
<li><strong>HAL USART</strong>:
<ul>
<li>Backward compatibility break introduced since <strong>v1.4.0</strong> versus <strong>v1.3.x</strong> versions:
<ul>
<li>Alignment with STM32F7/L4/G0 (for inter STM32 families portability)</li>
<li>Introduce “stm32h7xx_hal_usart_ex.c” file with new Tx/Rx FIFO management APIs</li>
<li>Field “Prescaler” of structure “USART_InitTypeDef” renamed to ClockPrescaler</li>
<li>remove fields “NSS”, “SlaveMode”, “FIFOMode”, “TXFIFOThreshold” and “RXFIFOThreshold” from “USART_InitTypeDef” structure</li>
<li>USART RXFIFO and TXFIFO threshold level defines moved to “stm32h7xx_hal_usart_ex.h”</li>
<li>USART Salve Mode defines moved to “stm32h7xx_hal_usart_ex.h”</li>
</ul></li>
</ul></li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true"><strong>V1.4.0 / 30-November-2018</strong></label>
<div>
<h2 id="main-changes-5">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements</li>
<li>Add LL drivers : LL_ADC, LL_BDMA, LL_BUS, LL_COMP, LL_CORTEX, LL_CRC, LL_DAC, LL_DMA, LL_DMA2D, LL_DMAMUX, LL_EXTI, LL_GPIO, LL_HRTIM, LL_HSEM, LL_I2C, LL_IWDG, LL_LPTIM, LL_LPUART, LL_MDMA, LL_OPAMP,LL_PWR, LL_RCC, LL_RNG, LL_RTC, LL_SPI, LL_SWPMI, LL_SYSTEM, LL_TIM, LL_USART, LL_UTILS, LL_WWDG</li>
<li>Introduce the register callback mechanism. It permits the user to configure dynamically the interrupt callbacks:
<ul>
<li>hal_conf_template.h is updated to embed the required new define to activate the feature : one define per HAL driver, example: USE_HAL_I2C_REGISTER_CALLBACKS</li>
</ul></li>
<li>Add HAL <strong>EXTI</strong> driver</li>
<li>Add HAL <strong>RAMECC</strong> driver</li>
<li><strong>HAL</strong> : stm32h7xx_hal.c and stm32h7xx_hal.h and stm32h7xx_hal_conf_template.h files
<ul>
<li>Fix register bit field “SYSCFG_PMCR_EPIS_SEL” naming in function “HAL_SYSCFG_ETHInterfaceSelect” in stm32h7xx_hal.c:
<ul>
<li>Alignment with the cmsis device include files</li>
</ul></li>
<li>Rename internal private macro “IS_EXTI_CONFIG_LINE” to IS_HAL_EXTI_CONFIG_LINE in stm32h7xx_hal.h: to avoid conflict with HAL EXTI driver</li>
<li>Update stm32h7xx_hal_conf_template.h to add HAL EXTI and HAL RAMECC</li>
<li>Update stm32h7xx_hal_conf_template.h to to put the include of the MDMA HAL header file before the include of the JPEG and QSPI HAL header files (as JPEG and QSPI HAL drivers are using the MDMA)</li>
<li>File stm32h7xx_hal.c, update HAL_SetFMCMemorySwappingConfig and HAL_GetFMCMemorySwappingConfig to align with Reference Manual regarding registers and bit definition naming</li>
<li>Update stm32h7xx_hal.c with Driver version number set to V1.4.0</li>
</ul></li>
<li><strong>HAL ADC</strong>:
<ul>
<li>Remove BoostMode from Init structure, this settings is automatically handled by HAL_ADC_Init() function depending of the ADC Clock value
<ul>
<li><strong>Caution : compatibility break with previous version regarding ADC init parameters (ADC_InitTypeDef structure)</strong></li>
</ul></li>
</ul></li>
<li><strong>HAL_CRYP</strong>:
<ul>
<li>Improve error detection in function “CRYP_GCMCCM_SetPayloadPhase_IT”</li>
<li>Improve padding management in function “CRYP_GCMCCM_SetPayloadPhase_IT”</li>
<li>Fix data counter issue in function “CRYP_AESCCM_Process”</li>
</ul></li>
<li><strong>HAL DFSDM</strong>:
<ul>
<li>Rename DFSDM_FILTER_EXT_TRIG_LPTIMx with DFSDM_FILTER_EXT_TRIG_LPTIMx_OUT</li>
</ul></li>
<li><strong>HAL DMA</strong>:
<ul>
<li>Add double buffering feature support for BDMA</li>
<li>Fix DMA_FLAG_FEIF0_4 and DMA_FLAG_DMEIF0_4 numerical values (no impact on the functional behavior)</li>
<li>Add a Clean/Reset of callbacks in HAL_DMA_DeInit()</li>
<li>Remove FIFO error enabling in “HAL_DMA_Start_IT”. when FIFO error monitoring is requested in IT model, the macro __HAL_DMA_ENABLE_IT can be used to enable the FIFO error IT at the user Msp function</li>
<li>Remove check on busy state within “HAL_DMA_DeInit” function : to allow forcing a de-initialization even in busy state</li>
</ul></li>
<li><strong>HAL ETH</strong>:
<ul>
<li>Add check for input buffer against NULL in function HAL_ETH_GetRxDataBuffer</li>
</ul></li>
<li><strong>HAL FDCAN</strong>:
<ul>
<li>Fix counter increment in API HAL_FDCAN_ConfigFilter</li>
<li>Fix comment description of parameter “RxFDFflag” in “FDCAN_ProtocolStatusTypeDef” structure</li>
<li>Fix comment description of defines FDCAN_FRAME_FD_NO_BRS and FDCAN_FRAME_FD_BRS</li>
<li>Add a reset of FDCAN operation mode in the “HAL_FDCAN_Init” function</li>
<li>Add Error Status callback support:
<ul>
<li>Add parameter “ErrorStatusCallback” in FDCAN_HandleTypeDef structure in stm32h7xx_hal_fdcan.h</li>
<li>Add typedef “pFDCAN_ErrorStatusCallbackTypeDef” in stm32h7xx_hal_fdcan.h</li>
<li>Add APIs “HAL_FDCAN_RegisterErrorStatusCallback” and “HAL_FDCAN_UnRegisterErrorStatusCallback”</li>
<li>Add weak callback “HAL_FDCAN_ErrorStatusCallback”</li>
<li>Update “HAL_FDCAN_IRQHandler” function to call the ErrorStatusCallback in case of an error status interrupt</li>
</ul></li>
<li>Improve error management by adding error codes “HAL_FDCAN_ERROR_FIFO_EMPTY” and “HAL_FDCAN_ERROR_FIFO_FULL” used in case of FIFO full in “HAL_FDCAN_AddMessageToTxFifoQ” and FIFO empty in “HAL_FDCAN_GetRxMessage” functions</li>
<li>Fix implementation issue in “HAL_FDCAN_ResetTimeoutCounter” function</li>
<li>Improve behavior of “HAL_FDCAN_GetRxMessage” and “HAL_FDCAN_GetTxEvent” functions : operation not allowed in HAL_FDCAN_STATE_READY state</li>
</ul></li>
<li><strong>HAL FLASH</strong>:
<ul>
<li>Align driver with the Reference Manual regarding registers and bit definition naming</li>
</ul></li>
<li><strong>HAL GPIO</strong>:
<ul>
<li>Add assert check of parameter GPIO_Pin in function “HAL_GPIO_DeInit”</li>
<li>Add assert check against alternate function availability for parameter “GPIOx” in function “HAL_GPIO_Init”</li>
<li>Improve “HAL_GPIO_TogglePin” function against reentrancy</li>
<li>Move GPIO clearing to default values in “HAL_GPIO_DeInit” function after EXTI clearing to avoid unexpected pending interrupts issues</li>
</ul></li>
<li><strong>HAL HRTIM</strong>:
<ul>
<li>Fix “HAL_HRTIM_FaultConfig” function regarding FLTINR1 and FLTINR2 registers settings</li>
<li>Update “HAL_HRTIM_SimpleBaseStop_DMA”, “HAL_HRTIM_SimpleOCStop_DMA” and “HAL_HRTIM_SimplePWMStop_DMA” functions to add a check for the DMA handle against NULL pointer</li>
<li>Fix HAL_HRTIM_SimpleOCChannelConfig,, “HAL_HRTIM_SimpleCaptureChannelConfig”, HAL_HRTIM_SimplePWMChannelConfig and “HAL_HRTIM_SimpleOnePulseChannelConfig” functions : considering parameters “pSimpleOCChannelCfg-&gt;Polarity” , “pSimpleOCChannelCfg-&gt;IdleLevel” and “pSimpleCaptureChannelCfg-&gt;EventSensitivity”</li>
</ul></li>
<li><strong>HAL IRDA (compatibility break)</strong>: alignment with STM32L4 (for inter STM32 families portability)
<ul>
<li>Add new field “ClockPrescaler” to “IRDA_InitTypeDef” structure"</li>
</ul></li>
<li><strong>HAL I2C</strong>:
<ul>
<li>ErrorCode is set to HAL_I2C_ERROR_INVALID_PARAM in all APIs when I2C handle is NULL</li>
<li>Add and I2C restart condition for each call of HAL_I2C_Master_Sequential_xxxx_IT</li>
<li>Rename APIs “HAL_I2C_Master_Sequential_Transmit_IT” and “HAL_I2C_Master_Seq_Receive_IT” respectively to “HAL_I2C_Master_Seq_Transmit_IT” and “HAL_I2C_Master_Seq_Receive_IT” for MISRA-C 2012 compliance</li>
<li>Rename APIs “HAL_I2C_Slave_Sequential_Transmit_IT” and “HAL_I2C_Slave_Sequential_Receive_IT” respectively to “HAL_I2C_Slave_Seq_Transmit_IT” and “HAL_I2C_Slave_Seq_Receive_IT” for MISRA-C 2012 compliance</li>
<li>Rename APIs “HAL_I2C_Master_Sequential_Transmit_DMA” and “HAL_I2C_Master_Seq_Receive_DMA” respectively to “HAL_I2C_Master_Seq_Transmit_DMA” and “HAL_I2C_Master_Seq_Receive_DMA” for MISRA-C 2012 compliance</li>
<li>Rename APIs “HAL_I2C_Slave_Sequential_Transmit_DMA” and “HAL_I2C_Slave_Sequential_Receive_DMA” respectively to “HAL_I2C_Slave_Seq_Transmit_DMA” and “HAL_I2C_Slave_Seq_Receive_DMA” for MISRA-C 2012 compliance</li>
</ul></li>
<li><strong>HAL I2S</strong>:
<ul>
<li>Align driver with the Reference Manual regarding registers and bit definition naming</li>
<li>Fix HAL_I2S_DMAPause and HAL_I2S_DMAResume management</li>
<li>HAL_I2S_DMAStop is no more supported (return HAL_I2S_ERROR_NOT_SUPPORTED when called)</li>
<li>Fix FifoThreshold affectation into HAL_I2S_Init</li>
<li>Update several defines into stm32h7xx_hal_i2s.h</li>
<li>Add macro __HAL_I2S_CLEAR_SUSPFLAG</li>
<li>Fix compilation issue when SPI driver is not included in the project (Due to the use of some HAL SPI define, use appropriate I2S defines instead)</li>
<li>Fix Tx and RX buffers increment to avoid memory overflow (functions HAL_I2S_Transmit, HAL_I2S_Receive, I2S_RxISR_16BIT, I2S_RxISR_32BIT, I2S_TxISR_16BIT and I2S_TxISR_32BIT)</li>
<li><strong>Known limitations:</strong>
<ul>
<li><strong>Driver not fully tested, some features may not be working as expected</strong></li>
<li><strong>A new version of this driver will be available in next release with full features tested</strong></li>
</ul></li>
</ul></li>
<li><strong>HAL JPEG</strong>:
<ul>
<li>Remove include of MDMA HAL driver as it is already done through the stm32h7xx_hal_conf.h header file
<ul>
<li>Note : in the stm32h7xx_hal_conf.h the include of the MDMA HAL header file must be done before the include of the JPEG HAL header file (stm32h7xx_hal_conf_template.h updated accordingly)</li>
</ul></li>
</ul></li>
<li><strong>HAL LPTIM</strong>:
<ul>
<li>Update “HAL_LPTIM_Init” function to add a clock polarity reset</li>
<li>Update "__HAL_LPTIM_DISABLE" macro implementation</li>
<li>Replace usage of global variables “tmpclksource”, “tmpIER”, “tmpCFGR”, “tmpCMP”, “tmpARR” and “tmpCFGR2” by local ones</li>
</ul></li>
<li><strong>HAL MDMA</strong>:
<ul>
<li>Remove check on busy state within “HAL_MDMA_DeInit” function : to allow forcing a de-initialization even in busy state</li>
</ul></li>
<li><strong>HAL MMC</strong>:
<ul>
<li>Rename “BLOCKSIZE” define to “MMC_BLOCKSIZE” to avoid conflict with HAL SD definition</li>
</ul></li>
<li><strong>HAL PWR</strong>:
<ul>
<li>Update “HAL_PWR_DisableWakeUpPin” function to disable the Wakeup for the given wakeup pin only</li>
<li>Fix “HAL_PWR_EnterSLEEPMode” and “HAL_PWR_EnterSTOPMode” using one single __WFE instruction in case low power mode with wait for event</li>
<li>Fix “HAL_PWREx_EnterSTOPMode” using one single using one single __WFE instruction in case low power mode with wait for event</li>
<li>Add API “HAL_PWREx_ClearPendingEvent” to clear pending events if any</li>
</ul></li>
<li><strong>HAL QSPI</strong>:
<ul>
<li>Remove include of MDMA HAL driver as it is already done through the stm32h7xx_hal_conf.h header file
<ul>
<li>Note : in the stm32h7xx_hal_conf.h the include of the MDMA HAL header file must be done before the include of the QSPI HAL header file (stm32h7xx_hal_conf_template.h updated accordingly)</li>
</ul></li>
<li>Add description of MDMA required settings in the “How to use this driver” section</li>
<li>Fix the “HAL_QSPI_Transmit_DMA” function:
<ul>
<li>Add check for MDMA settings : Data size and increment mode
<ul>
<li>Support of BYTE, HALF WORD and WORD modes</li>
</ul></li>
<li>Enable the QSPI Transfer complete and errors interrupt before starting the MDMA transfer to avoid race condition</li>
</ul></li>
<li>Fix the “HAL_QSPI_Receive_DMA” function :
<ul>
<li>Add check for MDMA settings : Data size and increment mode
<ul>
<li>Support of BYTE, HALF WORD and WORD modes</li>
</ul></li>
</ul></li>
</ul></li>
<li><strong>HAL RCC</strong>:
<ul>
<li>Add management for “Frac” parameter in PLL2 and PLL3</li>
<li>Add macros __HAL_RCC_MCO1_CONFIG and __HAL_RCC_MCO2_CONFIG</li>
<li>Rework HAL_RCC_DeInit function to reset RCC registers</li>
<li>Rework HAL_RCC_ClockConfig function to use the correct divider settings order according to the Reference Manual</li>
<li>Fix PCLK1 Configuration in HAL_RCC_ClockConfig function : use correct register RCC-&gt;D2CFGR instead of RCC-&gt;D1CFGR.</li>
<li>Add definitions of “RCC_SYSCLKSOURCE_STATUS_CSI”, “RCC_SYSCLKSOURCE_STATUS_HSI”, “RCC_SYSCLKSOURCE_STATUS_HSE” and “RCC_SYSCLKSOURCE_STATUS_PLLCLK”</li>
<li>Fix “HAL_RCC_ClockConfig” implementation:
<ul>
<li>Null pointer check</li>
<li>use "__HAL_FLASH_GET_LATENCY" macro instead of direct register access</li>
<li>Optimize the wait for clock source switching</li>
</ul></li>
</ul></li>
<li><strong>HAL RTC</strong>:
<ul>
<li>Add new macro IS_RTC_TAMPER_FILTER_CONFIG_CORRECT() to check filter is enabled only in case of high or low level</li>
<li>Align driver with the Reference Manual regarding registers and bit definition naming</li>
</ul></li>
<li><strong>HAL SAI</strong>:
<ul>
<li>PDM feature is available on SAI1 and SAI4 only</li>
<li>Improve and fix HAL_SAI_DMAStop and HAL_SAI_Abort APIs</li>
<li>Expend external synchronization feature to SAI3 and SAI4</li>
</ul></li>
<li><strong>HAL SD</strong>:
<ul>
<li>Fix and improve High speed and ultra-high speed behavior</li>
<li>Add APIs “HAL_SD_ConfigSpeedBusOperation” to configure the SD card speed bus mode:
<ul>
<li>SDMMC_SPEED_MODE_AUTO: Max speed mode supported by the card</li>
<li>SDMMC_SPEED_MODE_DEFAULT: Default Speed/SDR12 mode</li>
<li>SDMMC_SPEED_MODE_HIGH: High Speed/SDR25 mode</li>
<li>SDMMC_SPEED_MODE_ULTRA: Ultra high speed mode</li>
</ul></li>
<li>Remove extra function prototype “HAL_SD_SendSDStatus” from stm32h7xx_hal_sd.h</li>
<li>Fix multi-buffering feature implementation</li>
</ul></li>
<li><strong>HAL SPI</strong>:
<ul>
<li>Update HAL_SPI_Transmit_DMA : checking hmdtx instead of hdmrx.</li>
<li>Update to add Reload Feature and Duplex Packet DXP
<ul>
<li>Add APIs : “HAL_SPI_Reload_Transmit_IT”, “HAL_SPI_Reload_Receive_IT” and “HAL_SPI_Reload_TransmitReceive_IT”</li>
</ul></li>
<li>Align driver with the Reference Manual regarding registers and bit definition naming</li>
</ul></li>
<li><strong>HAL SMARTCARD(compatibility break)</strong>: Alignment with STM32L4 (for inter STM32 families portability)
<ul>
<li>Remove fields “FIFOMode”, “TXFIFOThreshold” and “RXFIFOThreshold” from “SMARTCARD_InitTypeDef” structure</li>
<li>Add new field “ClockPrescaler” to “SMARTCARD_InitTypeDef” structure"</li>
<li>SMARTCARD RXFIFO and TXFIFO threshold level defines moved to “stm32h7xx_hal_smartcard_ex.h”</li>
<li>Introduce new APIs to manage the Tx and Rx FIFO:
<ul>
<li>HAL_SMARTCARDEx_EnableFifoMode, HAL_SMARTCARDEx_DisableFifoMode, HAL_SMARTCARDEx_SetTxFifoThreshold and HAL_SMARTCARDEx_SetRxFifoThreshold</li>
<li>Introduce “HAL_SMARTCARDEx_RxFifoFullCallback” and “HAL_SMARTCARDEx_TxFifoEmptyCallback”</li>
<li>Fix Linux compilation warning in function “HAL_SMARTCARD_Receive”</li>
</ul></li>
</ul></li>
<li><strong>HAL SRAM, HAL SDRAM , HAL NOR and HAL NAND</strong>:
<ul>
<li>Align driver with the Reference Manual regarding registers and bit definition naming</li>
<li>Fix and improve state and error management</li>
</ul></li>
<li><strong>HAL TIM</strong>:
<ul>
<li>Add a call to HAL_DMA_Abort_IT from HAL_TIM_XXX_Stop_DMA</li>
<li>Add APIs “HAL_TIM_DMABurst_MultiWriteStart” and “HAL_TIM_DMABurst_MultiReadStart”</li>
</ul></li>
<li><strong>HAL UART(compatibility break)</strong>: Alignment with STM32L4 (for inter STM32 families portability)
<ul>
<li>Field “Prescaler” of structure “UART_InitTypeDef” renamed to ClockPrescaler</li>
<li>remove fields “FIFOMode”, “TXFIFOThreshold” and “RXFIFOThreshold” from “UART_InitTypeDef” structure</li>
<li>UART RXFIFO and TXFIFO threshold level defines moved to “stm32h7xx_hal_uart_ex.h”</li>
<li>Introduce new APIs to manage the Tx and Rx FIFO:
<ul>
<li>HAL_UARTEx_EnableFifoMode, HAL_UARTEx_DisableFifoMode, HAL_UARTEx_SetTxFifoThreshold and HAL_UARTEx_SetRxFifoThreshold</li>
</ul></li>
<li>Introduce “HAL_UARTEx_RxFifoFullCallback” and “HAL_UARTEx_TxFifoEmptyCallback”</li>
</ul></li>
<li><strong>HAL USART(compatibility break)</strong>: Alignment with STM32L4 (for inter STM32 families portability)
<ul>
<li>Introduce “stm32h7xx_hal_usart_ex.c” file with new Tx/Rx FIFO management APIs</li>
<li>Field “Prescaler” of structure “USART_InitTypeDef” renamed to ClockPrescaler</li>
<li>remove fields “NSS”, “SlaveMode”, “FIFOMode”, “TXFIFOThreshold” and “RXFIFOThreshold” from “USART_InitTypeDef” structure</li>
<li>USART RXFIFO and TXFIFO threshold level defines moved to “stm32h7xx_hal_usart_ex.h”</li>
<li>USART Salve Mode defines moved to “stm32h7xx_hal_usart_ex.h”</li>
<li>Introduce new APIs to manage the Tx and Rx FIFO:
<ul>
<li>HAL_USARTEx_EnableFifoMode, HAL_USARTEx_DisableFifoMode, HAL_USARTEx_SetTxFifoThreshold and HAL_USARTEx_SetRxFifoThreshold</li>
</ul></li>
<li>Introduce new APIs to manage SPI slave mode:
<ul>
<li>HAL_USARTEx_EnableSlaveMode, HAL_USARTEx_DisableSlaveMode and HAL_USARTEx_ConfigNSS</li>
</ul></li>
</ul></li>
<li><strong>HAL USB</strong>:
<ul>
<li>Fix condition check for EmptyTX FIFO</li>
<li>Protect the hcd driver to be used only if the USB_OTG_FS, USB_OTG_HS are enabled</li>
</ul></li>
</ul>
<h2 id="known-limitations-5">Known Limitations</h2>
<ul>
<li><strong>HAL I2S</strong>:
<ul>
<li>Driver not fully tested, some features may not be working as expected</li>
<li>A new version of this driver will be available in next release with full features tested</li>
</ul></li>
</ul>
<h2 id="backward-compatibility-5">Backward compatibility</h2>
<ul>
<li><strong>HAL ADC</strong>:
<ul>
<li>ADC_InitTypeDef structure: remove filed BoostMode.</li>
</ul></li>
<li><strong>HAL IRDA</strong>:
<ul>
<li>Alignment with STM32F7/L4/G0 (for inter STM32 families portability)</li>
<li>Add new field “ClockPrescaler” to “IRDA_InitTypeDef” structure"</li>
</ul></li>
<li><strong>HAL SMARTCARD</strong>:
<ul>
<li>Alignment with STM32F7/L4/G0 (for inter STM32 families portability)</li>
<li>Remove fields “FIFOMode”, “TXFIFOThreshold” and “RXFIFOThreshold” from “SMARTCARD_InitTypeDef” structure</li>
<li>Add new field “ClockPrescaler” to “SMARTCARD_InitTypeDef” structure"</li>
<li>SMARTCARD RXFIFO and TXFIFO threshold level defines moved to “stm32h7xx_hal_smartcard_ex.h”</li>
</ul></li>
<li><strong>HAL UART</strong>:
<ul>
<li>Alignment with STM32F7/L4/G0 (for inter STM32 families portability)</li>
<li>Field “Prescaler” of structure “UART_InitTypeDef” renamed to ClockPrescaler</li>
<li>remove fields “FIFOMode”, “TXFIFOThreshold” and “RXFIFOThreshold” from “UART_InitTypeDef” structure</li>
<li>UART RXFIFO and TXFIFO threshold level defines moved to “stm32h7xx_hal_uart_ex.h”</li>
</ul></li>
<li><strong>HAL USART</strong>:
<ul>
<li>Alignment with STM32F7/L4/G0 (for inter STM32 families portability)</li>
<li>Introduce “stm32h7xx_hal_usart_ex.c” file with new Tx/Rx FIFO management APIs</li>
<li>Field “Prescaler” of structure “USART_InitTypeDef” renamed to ClockPrescaler</li>
<li>remove fields “NSS”, “SlaveMode”, “FIFOMode”, “TXFIFOThreshold” and “RXFIFOThreshold” from “USART_InitTypeDef” structure</li>
<li>USART RXFIFO and TXFIFO threshold level defines moved to “stm32h7xx_hal_usart_ex.h”</li>
<li>USART Salve Mode defines moved to “stm32h7xx_hal_usart_ex.h”</li>
</ul></li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.3.0 / 29-June-2018</strong></label>
<div>
<h2 id="main-changes-6">Main Changes</h2>
<ul>
<li>Updates to fix known defects on HAL Cortex, HAL RCC and HAL SDMMC drivers</li>
<li><strong>HAL Cortex</strong>: Driver update to support 16 MPU regions instead of 8. User can now select an MPU regions from MPU_REGION_NUMBER0 to MPU_REGION_NUMBER15</li>
<li><strong>HAL RCC</strong> : Update and rework HAL_RCC_PeriphCLKConfig function in order to support consecutive configurations for several peripherals using PLL2 and PLL3. To do so first the given PLL is stopped, then the given divider is updated, the given PLL clock output divider is enabled and finally the given PLL is enabled</li>
<li><strong>HAL SDMMC</strong>: Fix and enhancements to support high speed mode</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 / 29-December-2017</strong></label>
<div>
<h2 id="main-changes-7">Main Changes</h2>
<ul>
<li>General updates to fix known defects and enhancements implementation</li>
<li><strong>HAL SPI</strong>: Driver reworked to fix critical issues</li>
<li>HAL: Update HAL Tick implementation</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 31-August-2017</strong></label>
<div>
<h2 id="main-changes-8">Main Changes</h2>
<ul>
<li>General updates to fix known defects and enhancements implementation</li>
<li><strong>HAL FLASH</strong>: Add Mass Erase for both banks</li>
<li><strong>HAL RCC</strong>:
<ul>
<li>Update <strong>RCC_PeriphCLKInitTypeDef</strong> structure for more IP clock selection flexibility</li>
</ul></li>
<li><strong>HAL SPDIFRX</strong>: Add symbol clock generation</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 21-April-2017</strong></label>
<div>
<h2 id="main-changes-9">Main Changes</h2>
<ul>
<li>First official release for STM32H743xx/753xx devices</li>
</ul>
</div>
</div>
</div>
</div>
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