| /** |
| ****************************************************************************** |
| * @file stm32l1xx_ll_utils.c |
| * @author MCD Application Team |
| * @brief UTILS LL module driver. |
| ****************************************************************************** |
| * @attention |
| * |
| * Copyright (c) 2017 STMicroelectronics. |
| * All rights reserved. |
| * |
| * This software is licensed under terms that can be found in the LICENSE file |
| * in the root directory of this software component. |
| * If no LICENSE file comes with this software, it is provided AS-IS. |
| * |
| ****************************************************************************** |
| */ |
| /* Includes ------------------------------------------------------------------*/ |
| #include "stm32l1xx_ll_rcc.h" |
| #include "stm32l1xx_ll_utils.h" |
| #include "stm32l1xx_ll_system.h" |
| #include "stm32l1xx_ll_pwr.h" |
| #ifdef USE_FULL_ASSERT |
| #include "stm32_assert.h" |
| #else |
| #define assert_param(expr) ((void)0U) |
| #endif |
| |
| /** @addtogroup STM32L1xx_LL_Driver |
| * @{ |
| */ |
| |
| /** @addtogroup UTILS_LL |
| * @{ |
| */ |
| |
| /* Private types -------------------------------------------------------------*/ |
| /* Private variables ---------------------------------------------------------*/ |
| /* Private constants ---------------------------------------------------------*/ |
| /** @addtogroup UTILS_LL_Private_Constants |
| * @{ |
| */ |
| #define UTILS_MAX_FREQUENCY_SCALE1 32000000U /*!< Maximum frequency for system clock at power scale1, in Hz */ |
| #define UTILS_MAX_FREQUENCY_SCALE2 16000000U /*!< Maximum frequency for system clock at power scale2, in Hz */ |
| #define UTILS_MAX_FREQUENCY_SCALE3 4000000U /*!< Maximum frequency for system clock at power scale3, in Hz */ |
| |
| /* Defines used for PLL range */ |
| #define UTILS_PLLVCO_OUTPUT_SCALE1 96000000U /*!< Frequency max for PLLVCO output at power scale1, in Hz */ |
| #define UTILS_PLLVCO_OUTPUT_SCALE2 48000000U /*!< Frequency max for PLLVCO output at power scale2, in Hz */ |
| #define UTILS_PLLVCO_OUTPUT_SCALE3 24000000U /*!< Frequency max for PLLVCO output at power scale3, in Hz */ |
| |
| /* Defines used for HSE range */ |
| #define UTILS_HSE_FREQUENCY_MIN 1000000U /*!< Frequency min for HSE frequency, in Hz */ |
| #define UTILS_HSE_FREQUENCY_MAX 24000000U /*!< Frequency max for HSE frequency, in Hz */ |
| |
| /* Defines used for FLASH latency according to HCLK Frequency */ |
| #define UTILS_SCALE1_LATENCY1_FREQ 16000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ |
| #define UTILS_SCALE2_LATENCY1_FREQ 8000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */ |
| #define UTILS_SCALE3_LATENCY1_FREQ 2000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */ |
| /** |
| * @} |
| */ |
| /* Private macros ------------------------------------------------------------*/ |
| /** @addtogroup UTILS_LL_Private_Macros |
| * @{ |
| */ |
| #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \ |
| || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ |
| || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ |
| || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ |
| || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \ |
| || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \ |
| || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \ |
| || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \ |
| || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512)) |
| |
| #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \ |
| || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ |
| || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ |
| || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ |
| || ((__VALUE__) == LL_RCC_APB1_DIV_16)) |
| |
| #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \ |
| || ((__VALUE__) == LL_RCC_APB2_DIV_2) \ |
| || ((__VALUE__) == LL_RCC_APB2_DIV_4) \ |
| || ((__VALUE__) == LL_RCC_APB2_DIV_8) \ |
| || ((__VALUE__) == LL_RCC_APB2_DIV_16)) |
| |
| #define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_3) \ |
| || ((__VALUE__) == LL_RCC_PLL_MUL_4) \ |
| || ((__VALUE__) == LL_RCC_PLL_MUL_6) \ |
| || ((__VALUE__) == LL_RCC_PLL_MUL_8) \ |
| || ((__VALUE__) == LL_RCC_PLL_MUL_12) \ |
| || ((__VALUE__) == LL_RCC_PLL_MUL_16) \ |
| || ((__VALUE__) == LL_RCC_PLL_MUL_24) \ |
| || ((__VALUE__) == LL_RCC_PLL_MUL_32) \ |
| || ((__VALUE__) == LL_RCC_PLL_MUL_48)) |
| |
| #define IS_LL_UTILS_PLLDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_DIV_2) || ((__VALUE__) == LL_RCC_PLL_DIV_3) || \ |
| ((__VALUE__) == LL_RCC_PLL_DIV_4)) |
| |
| #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_SCALE1) : \ |
| ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_SCALE2) : \ |
| ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_SCALE3))) |
| |
| #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \ |
| ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \ |
| ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))) |
| |
| #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \ |
| || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) |
| |
| #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX)) |
| /** |
| * @} |
| */ |
| /* Private function prototypes -----------------------------------------------*/ |
| /** @defgroup UTILS_LL_Private_Functions UTILS Private functions |
| * @{ |
| */ |
| static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, |
| LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); |
| static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); |
| static ErrorStatus UTILS_PLL_IsBusy(void); |
| /** |
| * @} |
| */ |
| |
| /* Exported functions --------------------------------------------------------*/ |
| /** @addtogroup UTILS_LL_Exported_Functions |
| * @{ |
| */ |
| |
| /** @addtogroup UTILS_LL_EF_DELAY |
| * @{ |
| */ |
| |
| /** |
| * @brief This function configures the Cortex-M SysTick source to have 1ms time base. |
| * @note When a RTOS is used, it is recommended to avoid changing the Systick |
| * configuration by calling this function, for a delay use rather osDelay RTOS service. |
| * @param HCLKFrequency HCLK frequency in Hz |
| * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq |
| * @retval None |
| */ |
| void LL_Init1msTick(uint32_t HCLKFrequency) |
| { |
| /* Use frequency provided in argument */ |
| LL_InitTick(HCLKFrequency, 1000U); |
| } |
| |
| /** |
| * @brief This function provides accurate delay (in milliseconds) based |
| * on SysTick counter flag |
| * @note When a RTOS is used, it is recommended to avoid using blocking delay |
| * and use rather osDelay service. |
| * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which |
| * will configure Systick to 1ms |
| * @param Delay specifies the delay time length, in milliseconds. |
| * @retval None |
| */ |
| void LL_mDelay(uint32_t Delay) |
| { |
| __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ |
| uint32_t tmpDelay = Delay; |
| |
| /* Add this code to indicate that local variable is not used */ |
| ((void)tmp); |
| |
| /* Add a period to guaranty minimum wait */ |
| if(tmpDelay < LL_MAX_DELAY) |
| { |
| tmpDelay++; |
| } |
| |
| while (tmpDelay != 0U) |
| { |
| if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) |
| { |
| tmpDelay--; |
| } |
| } |
| } |
| |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup UTILS_EF_SYSTEM |
| * @brief System Configuration functions |
| * |
| @verbatim |
| =============================================================================== |
| ##### System Configuration functions ##### |
| =============================================================================== |
| [..] |
| System, AHB and APB buses clocks configuration |
| |
| (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 32000000 Hz. |
| @endverbatim |
| @internal |
| Depending on the device voltage range, the maximum frequency should be |
| adapted accordingly: |
| (++) +----------------------------------------------------------------+ |
| (++) | Wait states | HCLK clock frequency (MHz) | |
| (++) | |------------------------------------------------| |
| (++) | (Latency) | voltage range | voltage range | |
| (++) | | 1.65 V - 3.6 V | 2.0 V - 3.6 V | |
| (++) | |----------------|---------------|---------------| |
| (++) | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V | |
| (++) |-------------- |----------------|---------------|---------------| |
| (++) |0WS(1CPU cycle)|0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 | |
| (++) |---------------|----------------|---------------|---------------| |
| (++) |1WS(2CPU cycle)|2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32| |
| (++) +----------------------------------------------------------------+ |
| @endinternal |
| * @{ |
| */ |
| |
| /** |
| * @brief This function sets directly SystemCoreClock CMSIS variable. |
| * @note Variable can be calculated also through SystemCoreClockUpdate function. |
| * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) |
| * @retval None |
| */ |
| void LL_SetSystemCoreClock(uint32_t HCLKFrequency) |
| { |
| /* HCLK clock frequency */ |
| SystemCoreClock = HCLKFrequency; |
| } |
| |
| /** |
| * @brief Update number of Flash wait states in line with new frequency and current |
| voltage range. |
| * @param Frequency HCLK frequency |
| * @retval An ErrorStatus enumeration value: |
| * - SUCCESS: Latency has been modified |
| * - ERROR: Latency cannot be modified |
| */ |
| #if defined(FLASH_ACR_LATENCY) |
| ErrorStatus LL_SetFlashLatency(uint32_t Frequency) |
| { |
| ErrorStatus status = SUCCESS; |
| |
| uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ |
| |
| /* Frequency cannot be equal to 0 or greater than max clock */ |
| if ((Frequency == 0U) || (Frequency > UTILS_MAX_FREQUENCY_SCALE1)) |
| { |
| status = ERROR; |
| } |
| else |
| { |
| if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) |
| { |
| if (Frequency > UTILS_SCALE1_LATENCY1_FREQ) |
| { |
| /* 16 < HCLK <= 32 => 1WS (2 CPU cycles) */ |
| latency = LL_FLASH_LATENCY_1; |
| } |
| /* else HCLK < 16MHz default LL_FLASH_LATENCY_0 0WS */ |
| } |
| else if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) |
| { |
| if (Frequency > UTILS_SCALE2_LATENCY1_FREQ) |
| { |
| /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */ |
| latency = LL_FLASH_LATENCY_1; |
| } |
| /* else HCLK < 8MHz default LL_FLASH_LATENCY_0 0WS */ |
| } |
| else |
| { |
| if (Frequency > UTILS_SCALE3_LATENCY1_FREQ) |
| { |
| /* 2 < HCLK <= 4 => 1WS (2 CPU cycles) */ |
| latency = LL_FLASH_LATENCY_1; |
| } |
| /* else HCLK < 4MHz default LL_FLASH_LATENCY_0 0WS */ |
| } |
| |
| /* Latency cannot be set to 1WS only if 64-bit access bit is enabled */ |
| if (latency == LL_FLASH_LATENCY_1) |
| { |
| LL_FLASH_Enable64bitAccess(); |
| } |
| |
| LL_FLASH_SetLatency(latency); |
| |
| /* Check that the new number of wait states is taken into account to access the Flash |
| memory by reading the FLASH_ACR register */ |
| if (LL_FLASH_GetLatency() != latency) |
| { |
| status = ERROR; |
| } |
| } |
| return status; |
| } |
| #endif /* FLASH_ACR_LATENCY */ |
| |
| /** |
| * @brief This function configures system clock with HSI as clock source of the PLL |
| * @note The application need to ensure that PLL is disabled. |
| * @note Function is based on the following formula: |
| * - PLL output frequency = ((HSI frequency * PLLMul) / PLLDiv) |
| * - PLLMul: The application software must set correctly the PLL multiplication factor to avoid exceeding |
| * - 96 MHz as PLLVCO when the product is in range 1, |
| * - 48 MHz as PLLVCO when the product is in range 2, |
| * - 24 MHz when the product is in range 3 |
| * @note FLASH latency can be modified through this function. |
| * @note If this latency increases to 1WS, FLASH 64-bit access will be automatically enabled. |
| * A decrease of FLASH latency to 0WS will not disable 64-bit access. If needed, user should call |
| * the following function @ref LL_FLASH_Disable64bitAccess. |
| * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains |
| * the configuration information for the PLL. |
| * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains |
| * the configuration information for the BUS prescalers. |
| * @retval An ErrorStatus enumeration value: |
| * - SUCCESS: Max frequency configuration done |
| * - ERROR: Max frequency configuration not done |
| */ |
| ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, |
| LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) |
| { |
| ErrorStatus status; |
| uint32_t pllfreq; |
| |
| /* Check if one of the PLL is enabled */ |
| if (UTILS_PLL_IsBusy() == SUCCESS) |
| { |
| /* Calculate the new PLL output frequency */ |
| pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct); |
| |
| /* Enable HSI if not enabled */ |
| if (LL_RCC_HSI_IsReady() != 1U) |
| { |
| LL_RCC_HSI_Enable(); |
| while (LL_RCC_HSI_IsReady() != 1U) |
| { |
| /* Wait for HSI ready */ |
| } |
| } |
| |
| /* Configure PLL */ |
| LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); |
| |
| /* Enable PLL and switch system clock to PLL */ |
| status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); |
| } |
| else |
| { |
| /* Current PLL configuration cannot be modified */ |
| status = ERROR; |
| } |
| |
| return status; |
| } |
| |
| /** |
| * @brief This function configures system clock with HSE as clock source of the PLL |
| * @note The application need to ensure that PLL is disabled. |
| * @note Function is based on the following formula: |
| * - PLL output frequency = ((HSE frequency * PLLMul) / PLLDiv) |
| * - PLLMul: The application software must set correctly the PLL multiplication factor to avoid exceeding |
| * - 96 MHz as PLLVCO when the product is in range 1, |
| * - 48 MHz as PLLVCO when the product is in range 2, |
| * - 24 MHz when the product is in range 3 |
| * @note FLASH latency can be modified through this function. |
| * @note If this latency increases to 1WS, FLASH 64-bit access will be automatically enabled. |
| * A decrease of FLASH latency to 0WS will not disable 64-bit access. If needed, user should call |
| * the following function @ref LL_FLASH_Disable64bitAccess. |
| * @param HSEFrequency Value between Min_Data = 1000000 and Max_Data = 24000000 |
| * @param HSEBypass This parameter can be one of the following values: |
| * @arg @ref LL_UTILS_HSEBYPASS_ON |
| * @arg @ref LL_UTILS_HSEBYPASS_OFF |
| * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains |
| * the configuration information for the PLL. |
| * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains |
| * the configuration information for the BUS prescalers. |
| * @retval An ErrorStatus enumeration value: |
| * - SUCCESS: Max frequency configuration done |
| * - ERROR: Max frequency configuration not done |
| */ |
| ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, |
| LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) |
| { |
| ErrorStatus status; |
| uint32_t pllfreq; |
| |
| /* Check the parameters */ |
| assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); |
| assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass)); |
| |
| /* Check if one of the PLL is enabled */ |
| if (UTILS_PLL_IsBusy() == SUCCESS) |
| { |
| |
| /* Calculate the new PLL output frequency */ |
| pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct); |
| |
| /* Enable HSE if not enabled */ |
| if (LL_RCC_HSE_IsReady() != 1U) |
| { |
| /* Check if need to enable HSE bypass feature or not */ |
| if (HSEBypass == LL_UTILS_HSEBYPASS_ON) |
| { |
| LL_RCC_HSE_EnableBypass(); |
| } |
| else |
| { |
| LL_RCC_HSE_DisableBypass(); |
| } |
| |
| /* Enable HSE */ |
| LL_RCC_HSE_Enable(); |
| while (LL_RCC_HSE_IsReady() != 1U) |
| { |
| /* Wait for HSE ready */ |
| } |
| } |
| |
| /* Configure PLL */ |
| LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); |
| |
| /* Enable PLL and switch system clock to PLL */ |
| status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); |
| } |
| else |
| { |
| /* Current PLL configuration cannot be modified */ |
| status = ERROR; |
| } |
| |
| return status; |
| } |
| |
| /** |
| * @} |
| */ |
| |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup UTILS_LL_Private_Functions |
| * @{ |
| */ |
| |
| /** |
| * @brief Function to check that PLL can be modified |
| * @param PLL_InputFrequency PLL input frequency (in Hz) |
| * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains |
| * the configuration information for the PLL. |
| * @retval PLL output frequency (in Hz) |
| */ |
| static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) |
| { |
| uint32_t pllfreq; |
| |
| /* Check the parameters */ |
| assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul)); |
| assert_param(IS_LL_UTILS_PLLDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); |
| |
| /* Check different PLL parameters according to RM */ |
| /* The application software must set correctly the PLL multiplication factor to avoid exceeding |
| 96 MHz as PLLVCO when the product is in range 1, |
| 48 MHz as PLLVCO when the product is in range 2, |
| 24 MHz when the product is in range 3. */ |
| pllfreq = PLL_InputFrequency * (PLLMulTable[UTILS_PLLInitStruct->PLLMul >> RCC_CFGR_PLLMUL_Pos]); |
| assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq)); |
| |
| /* The application software must set correctly the PLL multiplication factor to avoid exceeding |
| maximum frequency 32000000 in range 1 */ |
| pllfreq = pllfreq / ((UTILS_PLLInitStruct->PLLDiv >> RCC_CFGR_PLLDIV_Pos)+1U); |
| assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); |
| |
| return pllfreq; |
| } |
| |
| /** |
| * @brief Function to check that PLL can be modified |
| * @retval An ErrorStatus enumeration value: |
| * - SUCCESS: PLL modification can be done |
| * - ERROR: PLL is busy |
| */ |
| static ErrorStatus UTILS_PLL_IsBusy(void) |
| { |
| ErrorStatus status = SUCCESS; |
| |
| /* Check if PLL is busy*/ |
| if (LL_RCC_PLL_IsReady() != 0U) |
| { |
| /* PLL configuration cannot be modified */ |
| status = ERROR; |
| } |
| |
| return status; |
| } |
| |
| /** |
| * @brief Function to enable PLL and switch system clock to PLL |
| * @param SYSCLK_Frequency SYSCLK frequency |
| * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains |
| * the configuration information for the BUS prescalers. |
| * @retval An ErrorStatus enumeration value: |
| * - SUCCESS: No problem to switch system to PLL |
| * - ERROR: Problem to switch system to PLL |
| */ |
| static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) |
| { |
| ErrorStatus status = SUCCESS; |
| uint32_t hclk_frequency; |
| |
| assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); |
| assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); |
| assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider)); |
| |
| /* Calculate HCLK frequency */ |
| hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider); |
| |
| /* Increasing the number of wait states because of higher CPU frequency */ |
| if (SystemCoreClock < hclk_frequency) |
| { |
| /* Set FLASH latency to highest latency */ |
| status = LL_SetFlashLatency(hclk_frequency); |
| } |
| |
| /* Update system clock configuration */ |
| if (status == SUCCESS) |
| { |
| /* Enable PLL */ |
| LL_RCC_PLL_Enable(); |
| while (LL_RCC_PLL_IsReady() != 1U) |
| { |
| /* Wait for PLL ready */ |
| } |
| |
| /* Sysclk activation on the main PLL */ |
| LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); |
| LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); |
| while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) |
| { |
| /* Wait for system clock switch to PLL */ |
| } |
| |
| /* Set APB1 & APB2 prescaler*/ |
| LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); |
| LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider); |
| } |
| |
| /* Decreasing the number of wait states because of lower CPU frequency */ |
| if (SystemCoreClock > hclk_frequency) |
| { |
| /* Set FLASH latency to lowest latency */ |
| status = LL_SetFlashLatency(hclk_frequency); |
| } |
| |
| /* Update SystemCoreClock variable */ |
| if (status == SUCCESS) |
| { |
| LL_SetSystemCoreClock(hclk_frequency); |
| } |
| |
| return status; |
| } |
| |
| /** |
| * @} |
| */ |
| |
| /** |
| * @} |
| */ |
| |
| /** |
| * @} |
| */ |
