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| <h1 id="release-notes-for">Release Notes for</h1> |
| <h1 id="stm32l4xx-hal-drivers"><mark>STM32L4xx HAL Drivers</mark></h1> |
| <p>Copyright © 2017 STMicroelectronics<br /> |
| </p> |
| <a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a> |
| </center> |
| <h1 id="purpose">Purpose</h1> |
| <p>The STM32Cube HAL and LL, an STM32 abstraction layer embedded software, ensure maximized portability across STM32 portfolio.</p> |
| <p>The portable APIs layer provides a generic, multi instanced and simple set of APIs to interact with the upper layer (application, libraries and stacks). It is composed of native and extended APIs set. It is directly built around a generic architecture and allows the build-upon layers, like the middleware layer, to implement its functions without knowing in-depth the used STM32 device. This improves the library code reusability and guarantees an easy portability on other devices and STM32 families.</p> |
| <p>The Low Layer (LL) drivers are part of the STM32Cube firmware HAL that provides a basic set of optimized and one shot services. The Low layer drivers, contrary to the HAL ones are not fully portable across the STM32 families; the availability of some functions depends on the physical availability of the relative features on the product. The Low Layer (LL) drivers are designed to offer the following features:</p> |
| <ul> |
| <li>New set of inline functions for direct and atomic register access</li> |
| <li>One-shot operations that can be used by the HAL drivers or from application level</li> |
| <li>Full independence from HAL and standalone usage (without HAL drivers)</li> |
| <li>Full features coverage of all the supported peripherals</li> |
| </ul> |
| </div> |
| <div class="col-sm-12 col-lg-8"> |
| <h1 id="update-history">Update History</h1> |
| <div class="collapse"> |
| <input type="checkbox" id="collapse-section31" checked aria-hidden="true"> <label for="collapse-section32" aria-hidden="true">V1.13.2 / 26-November-2021</label> |
| <div> |
| <h2 id="main-changes">Main Changes</h2> |
| <ul> |
| <li>Maintenance release of <strong>HAL and Low Layer</strong> drivers to include latest corrections</li> |
| </ul> |
| <h2 id="contents">Contents</h2> |
| <ul> |
| <li><strong>RCC_HAL</strong> |
| <ul> |
| <li>Update IS_RCC_PERIPHCLOCK() macro definition depending on targeted derivative.</li> |
| <li>Add new HAL_RCC_GetResetSource() API to get all reset sources and clear flags.</li> |
| <li>Update PLL clock source configuration to fix warnings with the GCC compiler.</li> |
| <li>Add check of PLL enable bit when a peripheral using PPL P or PLL Q.</li> |
| <li>Add new LL inline APIs to check specific PLL, PLLSAI1 and PLLSAI2 domains output: |
| <ul> |
| <li>LL_RCC_PLL_IsEnabledDomain_SAI()</li> |
| <li>LL_RCC_PLL_IsEnabledDomain_48M()</li> |
| <li>LL_RCC_PLL_IsEnabledDomain_SYS()</li> |
| <li>LL_RCC_PLLSAI1_IsEnabledDomain_SAI()</li> |
| <li>LL_RCC_PLLSAI1_IsEnabledDomain_48M()</li> |
| <li>LL_RCC_PLLSAI1_IsEnabledDomain_ADC()</li> |
| <li>LL_RCC_PLLSAI2_IsEnabledDomain_SAI()</li> |
| <li>LL_RCC_PLLSAI2_IsEnabledDomain_DSI()</li> |
| <li>LL_RCC_PLLSAI2_IsEnabledDomain_LTDC()</li> |
| <li>LL_RCC_PLLSAI2_IsEnabledDomain_ADC()</li> |
| </ul></li> |
| <li>Fix SAI clock source definition when RCC_CCIPR2_SAI1SEL and RCC_CCIPR2_SAI2SEL are present.</li> |
| <li>Update IS_RCC_PERIPHCLOCK() macro definition depending on targeted derivative.</li> |
| </ul></li> |
| <li><strong>EXTI_HAL</strong> |
| <ul> |
| <li>Update HAL_EXTI_GetConfigLine() API to set default configuration value of Trigger and GPIOSel before checking each corresponding registers.</li> |
| </ul></li> |
| <li><strong>FLASH_HAL</strong> |
| <ul> |
| <li>Disable ICache while Flash programming.</li> |
| <li>Update HAL_FLASHEx_Erase() to remove __HAL_FLASH_INSTRUCTION_CACHE_DISABLE().</li> |
| </ul></li> |
| <li><strong>GPIO_HAL</strong> |
| <ul> |
| <li>Update HAL_GPIO_Init() API to avoid the configuration of PUPDR register when Analog mode is selected.</li> |
| <li>Optimize assertion control for GPIO Pull mode in HAL_GPIO_Init() API.</li> |
| <li>Reorder EXTI configuration sequence in order to avoid unexpected level detection.</li> |
| </ul></li> |
| <li><strong>ADC_HAL/LL</strong> |
| <ul> |
| <li>Update of the TEMPSENSOR_CAL2_TEMP value in the ll_adc.h file.</li> |
| <li>Remove useless binary mask.</li> |
| <li>Update LL_ADC driver to prevent unused argument compilation warning.</li> |
| </ul></li> |
| <li><strong>OPAMP_HAL/LL</strong> |
| <ul> |
| <li>LL_OPAMP_SetTrimmingValue()/LL_OPAMP_GetTrimmingValue(): redefinition of registers address MUST be volatile (_IO)</li> |
| </ul></li> |
| <li><strong>RTC_BKP_HAL/LL</strong> |
| <ul> |
| <li>Update __HAL_RTC_…(<strong>HANDLE</strong>, …) macros to access registers through (<strong>HANDLE</strong>)->Instance pointer and avoid "unused variable" warnings.</li> |
| <li>Fix bad reference to RTC handle in LL_RTC_TIME_Init() & LL_RTC_DATE_Init() APIs</li> |
| </ul></li> |
| <li><strong>CAN_HAL</strong> |
| <ul> |
| <li>Update HAL_CAN_Init() API to be aligned with reference manual and to avoid timeout error: |
| <ul> |
| <li>Update CAN Initialization sequence to set "request initialization" bit before exit from sleep mode.</li> |
| </ul></li> |
| </ul></li> |
| <li><strong>SPI_HAL/LL</strong> |
| <ul> |
| <li>General update to fix MISRA-C 2012 Rule-13.2 issue.</li> |
| <li>Update LL_SPI_TransmitData8() API to avoid casting the result to 8 bits.</li> |
| </ul></li> |
| <li><strong>I2C_HAL</strong> |
| <ul> |
| <li>Fix written reserved bit 28 in I2C_CR2 register</li> |
| <li>Updated I2C_IsAcknowledgeFailed() API to avoid I2C in busy state if NACK received after transmitting register address.</li> |
| <li>Update to handle errors in polling mode. |
| <ul> |
| <li>Rename I2C_IsAcknowledgeFailed() to I2C_IsErrorOccurred() and correctly manage when error occurs.</li> |
| </ul></li> |
| <li>Update to fix issue detected due to low system frequency execution (HSI).</li> |
| <li>Declare an internal macro link to DMA macro to check remaining data: I2C_GET_DMA_REMAIN_DATA</li> |
| </ul></li> |
| <li><strong>SMBUS_HAL</strong> |
| <ul> |
| <li>Update to fix issue of mismatched data received by master in case of data size to be transmitted by the slave is greater than the data size to be received by the master. |
| <ul> |
| <li>Add flush on TX register.</li> |
| </ul></li> |
| <li>Add the support of wake up capability. |
| <ul> |
| <li>Add new APIs: |
| <ul> |
| <li>HAL_SMBUSEx_EnableWakeUp()</li> |
| <li>HAL_SMBUSEx_DisableWakeUp()</li> |
| </ul></li> |
| </ul></li> |
| </ul></li> |
| <li><strong>UART_HAL</strong> |
| <ul> |
| <li>Fix erroneous UART’s handle state in case of error returned after DMA reception start within UART_Start_Receive_DMA().</li> |
| <li>Correction on UART ReceptionType management in case of ReceptionToIdle API are called from RxEvent callback</li> |
| <li>Handling of UART concurrent register access in case of race condition between Tx and Rx transfers (HAL UART and LL LPUART)</li> |
| <li>Improve header description of UART_WaitOnFlagUntilTimeout() function</li> |
| <li>Add a check on the UART parity before enabling the parity error interruption.</li> |
| <li>Add const qualifier for read only pointers.</li> |
| <li>Fix wrong cast when computing the USARTDIV value in UART_SetConfig().</li> |
| </ul></li> |
| <li><strong>LPUART_LL</strong> |
| <ul> |
| <li>Remove TXFECF reference from LL LPUART driver</li> |
| </ul></li> |
| <li><strong>USART_HAL/LL</strong> |
| <ul> |
| <li>Handling of UART concurrent register access in case of race condition between Tx and Rx transfers (HAL UART and LL LPUART)</li> |
| <li>Fix compilation warnings generated with ARMV6 compiler</li> |
| <li>Improve header description of USART_WaitOnFlagUntilTimeout() function</li> |
| <li>Add a check on the USART parity before enabling the parity error interrupt.</li> |
| <li>Add const qualifier for read only pointers.</li> |
| </ul></li> |
| <li><strong>SMARTCARD_HAL</strong> |
| <ul> |
| <li>Improve header description of SMARTCARD_WaitOnFlagUntilTimeout() function</li> |
| <li>Add const qualifier for read only pointers.</li> |
| <li>Fix wrong cast when computing the USARTDIV value in SMARTCARD_SetConfig().</li> |
| </ul></li> |
| <li><strong>IRDA_HAL</strong> |
| <ul> |
| <li>Improve header description of IRDA_WaitOnFlagUntilTimeout() function</li> |
| <li>Add a check on the IRDA parity before enabling the parity error interrupt.</li> |
| <li>Add const qualifier for read only pointers.</li> |
| <li>Fix wrong cast when computing the USARTDIV value in IRDA_SetConfig().</li> |
| </ul></li> |
| <li><strong>DSI_HAL</strong> |
| <ul> |
| <li>Update HAL_DSI_Read() to avoid HAL_TIMEOUT when a DSI read command is issued to the panel and the read data is not captured by the DSI Host which returns Packet Size Error.</li> |
| <li>Update HAL_DSI_ExitULPM() to force DSI refresh</li> |
| </ul></li> |
| <li><strong>DCMI_HAL</strong> |
| <ul> |
| <li>Add const qualifier for read only pointers.</li> |
| </ul></li> |
| <li><strong>TIM_HAL</strong> |
| <ul> |
| <li>Fix compilation warnings with MDK-ARM</li> |
| <li>Update HAL_TIMEx_ConfigBreakInput to use CMSIS TIM1_OR2_BKDF1BK0E_Pos definition instead of its hard coded value.</li> |
| </ul></li> |
| <li><strong>LPTIM_HAL</strong>RNG |
| <ul> |
| <li>Add __HAL_LPTIM_RESET_COUNTER() and __HAL_LPTIM_RESET_COUNTER_AFTERREAD() macros managing the synchronous/asynchronous LPTIM counter reset.</li> |
| <li>Add check on PRIMASK register to prevent from enabling unwanted global interrupts within LPTIM_Disable() and LL_LPTIM_Disable()</li> |
| </ul></li> |
| <li><strong>NOR_HAL</strong> |
| <ul> |
| <li>Align HAL_NOR_Init() API with core of the function when write operation is disabled to avoid HardFault.</li> |
| </ul></li> |
| <li><strong>SDMMC_HAL</strong> |
| <ul> |
| <li>Fix Incorrect command sent in MMC_PowerOn |
| <ul> |
| <li>Update SEND_OP_COND (CMD1) to indicate as argument that the sector mode is supported by the host.</li> |
| </ul></li> |
| <li>Add new HAL_MMC_SleepDevice() API to Switch device from Standby State to Sleep State.</li> |
| <li>Fix MMC & SD chapters generation for PDF User Manual</li> |
| </ul></li> |
| <li><strong>PKA_HAL</strong> |
| <ul> |
| <li>Update to fix Montgomery multiplication in PKA.</li> |
| </ul></li> |
| <li><strong>USB_LL/HAL</strong> |
| <ul> |
| <li>Update in USB_SetCurrentMode() API to improve required wait timing to change core mode.</li> |
| <li>Remove non required 200ms delay during host initialization.</li> |
| <li>Update USB_FlushRxFifo() and USB_FlushTxFifo() APIs by adding check on AHB master IDLE state before flushing the USB FIFO.</li> |
| <li>Fix isochronous transfer in double buffer mode.</li> |
| <li>Update to avoid compiler optimization on count variable used for USB HAL timeout loop check.</li> |
| <li>Add missing registres callbacks check for HAL_HCD_HC_NotifyURBChange_Callback() API.</li> |
| <li>Add new HAL_PCD_SetTestMode() API to handle USB device high speed Test modes.</li> |
| <li>Update to set SNAK for EPs not required during device reset.</li> |
| <li>Add new API HAL_PCD_EP_Abort() to abort current USB endpoint transfer.</li> |
| <li>Footprint optimization in case USB double buffer mode not used, code protected with new define USE_USB_DOUBLE_BUFFER</li> |
| <li>Update to avoid multiple reads of USB ISR register</li> |
| </ul></li> |
| <li><strong>RNG_HAL</strong> |
| <ul> |
| <li>Fix Seed error due to a wrong HTCR value</li> |
| </ul></li> |
| <li><strong>IWDG_HAL</strong> |
| <ul> |
| <li>Update HAL_IWDG_Init() API in order to fix HAL_GetTick() timeout vulnerability issue.</li> |
| <li>Add LSI startup time in default IWDG timeout calculation (HAL_IWDG_DEFAULT_TIMEOUT).</li> |
| </ul></li> |
| </ul> |
| </div> |
| </div> |
| <div class="collapse"> |
| <input type="checkbox" id="collapse-section30" aria-hidden="true"> <label for="collapse-section30" aria-hidden="true">V1.13.1 / 24-September-2021</label> |
| <div> |
| <h2 id="main-changes-1">Main Changes</h2> |
| <ul> |
| <li>Patch release only of ** USB HAL and Low Layer** drivers to include latest corrections</li> |
| </ul> |
| <h2 id="contents-1">Contents</h2> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p> |
| <ul> |
| <li><strong>HAL USB PCD</strong> driver |
| <ul> |
| <li>Fix double buffer mode isochronous IN transfer</li> |
| <li>Optimize USB IRQ handler by removing multiple reads from USB interrupt registers</li> |
| </ul></li> |
| <li><strong>HAL USB HCD</strong> driver |
| <ul> |
| <li>Optimize USB IRQ handler by removing multiple reads on USB interrupt registers</li> |
| </ul></li> |
| </ul> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">LL drivers changes</span></span></strong></p> |
| <ul> |
| <li><strong>LL USB</strong> driver |
| <ul> |
| <li>Correction added on USB_ReadPacket() to ensure a byte by byte read from USB FiFO</li> |
| </ul></li> |
| </ul> |
| </div> |
| </div> |
| <div class="collapse"> |
| <input type="checkbox" id="collapse-section29" aria-hidden="true"> <label for="collapse-section29" aria-hidden="true">V1.13.0 / 11-February-2021</label> |
| <div> |
| <h2 id="main-changes-2">Main Changes</h2> |
| <ul> |
| <li>Maintenance release of <strong>HAL and Low Layer</strong> drivers to include latest corrections |
| <ul> |
| <li>Update of HAL SMBUS driver to introduce fast mode and fast mode plus |
| <ul> |
| <li>Add extension files stm32l4xx_hal_smbus_ex.h/.c for new APIs: |
| <ul> |
| <li><em>HAL_SMBUSEx_EnableFastModePlus()</em></li> |
| <li><em>HAL_SMBUSEx_DisableFastModePlus()</em></li> |
| </ul></li> |
| </ul></li> |
| <li>Update of HAL UART driver introducing enhanced reception services |
| <ul> |
| <li><em>HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle()</em></li> |
| <li><em>HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT()</em></li> |
| <li><em>HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA()</em></li> |
| </ul></li> |
| </ul></li> |
| </ul> |
| <h2 id="contents-2">Contents</h2> |
| <h3 id="halll-generic-updates"><strong>HAL/LL generic</strong> updates</h3> |
| <ul> |
| <li>stm32l4xx_hal_timebase_tim_template.c |
| <ul> |
| <li>Update Tick priority handling in <em>HAL_Init_Tick()</em></li> |
| </ul></li> |
| </ul> |
| <p><br /> |
| </p> |
| <h3 id="hal-drivers-updates"><strong>HAL Drivers</strong> updates</h3> |
| <ul> |
| <li><strong>HAL ADC</strong> driver |
| <ul> |
| <li>Fix delay computation of the local variable wait_loop_index at low system core clock frequency</li> |
| <li>Fix to avoid Error state returned by IRQ handler in case of injected conversion + IT mode + trigger timer</li> |
| <li>Update <em>HAL_ADC_DeInit()</em> description and behaviour to call <em>MspDeInit()</em> only when all ADC instances sharing the same common ADC instance are disabled</li> |
| <li>Update timeout mechanism to avoid false timeout detection in case of preemption</li> |
| <li>Extend internal regulator stabilization time from 10us to 20us</li> |
| </ul></li> |
| <li><strong>HAL COMP</strong> driver |
| <ul> |
| <li>Fix delay computation of the local variable wait_loop_index at low system core clock frequency</li> |
| </ul></li> |
| <li><strong>HAL EXTI</strong> driver |
| <ul> |
| <li>Replace macro parameter __LINE__ by __EXTI_LINE__ to avoid conflicts with standard C usage</li> |
| </ul></li> |
| <li><strong>HAL GPIO</strong> driver |
| <ul> |
| <li>Add AF6 missing definitions : GPIO_AF6_OCTOSPIM_P1 / GPIO_AF6_OCTOSPIM_P2</li> |
| </ul></li> |
| <li><strong>HAL IWDG</strong> driver |
| <ul> |
| <li>Update definition of HAL_IWDG_DEFAULT_TIMEOUT to avoid issue with the watchdog init procedure</li> |
| </ul></li> |
| <li><strong>HAL LPTIM</strong> driver |
| <ul> |
| <li>Update external clock configuration to cover all ClockSource/CounterSource combinations</li> |
| </ul></li> |
| <li><strong>HAL NAND</strong> driver |
| <ul> |
| <li>Update address calculation in <em>HAL_NAND_Read_SpareArea_16b()</em> and <em>HAL_NAND_Write_SpareArea_16b()</em></li> |
| <li>Fix issue in the access to NAND 8-bits memories with 16-bits APIs</li> |
| </ul></li> |
| <li><strong>HAL OPAMP</strong> driver |
| <ul> |
| <li>Align OPAMP PowerMode definitions with others series</li> |
| </ul></li> |
| <li><strong>HAL RCC</strong> driver |
| <ul> |
| <li>Update IS_RCC_CRS_HSI48CALIBRATION() definition to have specific maximum value for STM32L412xx/L422xx devices</li> |
| <li>Update RCC_HSICALIBRATION_DEFAULT definition depending on devices</li> |
| </ul></li> |
| <li><strong>HAL RTC</strong> driver |
| <ul> |
| <li>Update the description of <em>HAL_RTC_SetTime()</em> to mention that the DayLightSaving attribute of sTime should not be used</li> |
| <li>Add Daylight Saving Time service</li> |
| <li>Update <em>HAL_RTC_DeactivateAlarm()</em> to fix issue during Alarm Autoclear</li> |
| <li>Update <em>HAL_RTC_SetTime()</em> to add back assert_param() functions checking daylight saving parameters</li> |
| </ul></li> |
| <li><strong>HAL SDMMC</strong> driver |
| <ul> |
| <li>Update driver to enable interrupt after treating the single write command or multiple write command</li> |
| <li>Update eMMC High Speed Mode management</li> |
| </ul></li> |
| <li><strong>HAL SMSBUS</strong> driver |
| <ul> |
| <li>Implementation of fast mode and fast mode plus |
| <ul> |
| <li>Add extension files stm32l4xx_hal_smbus_ex.h/.c for new APIs: |
| <ul> |
| <li><em>HAL_SMBUSEx_EnableFastModePlus()</em></li> |
| <li><em>HAL_SMBUSEx_DisableFastModePlus()</em></li> |
| </ul></li> |
| </ul></li> |
| </ul></li> |
| <li><strong>HAL SPI</strong> driver |
| <ul> |
| <li>Fix <em>SPI_WaitFifoStateUntilTimeout()</em></li> |
| </ul></li> |
| <li><strong>HAL TIM</strong> driver |
| <ul> |
| <li>Update callback function invoked upon Half DMA transfer completion</li> |
| <li>Fix in <em>HAL_TIM_OnePulse_Start()</em> to handle OutputChannel parameter</li> |
| <li>Update <em>HAL_TIM_IC_Start_DMA()</em> to ensure correct behavior of counter value latch delay at high frequency</li> |
| </ul></li> |
| <li><strong>HAL TSC</strong> driver |
| <ul> |
| <li>Add assertion when fordidden configurations of bit value PGPSC versus bit value CTPL are requested by user</li> |
| </ul></li> |
| <li><strong>HAL UART</strong> driver |
| <ul> |
| <li>Remove FifoMode use in UART_SetConfig()</li> |
| <li>Add a HAL UART service to enable RTO interrupt</li> |
| <li>Implementation of HAL UART enhanced reception services (ReceptionToIdle) |
| <ul> |
| <li><em>HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle()</em></li> |
| <li><em>HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT()</em></li> |
| <li><em>HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA()</em></li> |
| </ul></li> |
| </ul></li> |
| <li><strong>HAL UART/USART/IRDA/SMARTCARD</strong> drivers |
| <ul> |
| <li>Fix typos in State definition description</li> |
| <li>Update parameter array to be always declared as static const</li> |
| </ul></li> |
| <li><strong>HAL SMARTCARD</strong> driver |
| <ul> |
| <li>Remove FifoMode use in SMARTCARD_SetConfig()</li> |
| </ul></li> |
| <li><strong>HAL USB </strong> driver |
| <ul> |
| <li>Fix regression in HAL USB double buffer mode</li> |
| </ul></li> |
| <li><strong>HAL WWDG</strong> driver |
| <ul> |
| <li>Update HAL WWDG driver description</li> |
| </ul></li> |
| </ul> |
| <p><br /> |
| </p> |
| <h3 id="ll-drivers-updates"><strong>LL Drivers</strong> updates</h3> |
| <ul> |
| <li><strong>LL DMA</strong> driver |
| <ul> |
| <li>Update LL_DMA_ClearFlag_GIx() to add text informing user not to clear GIx when channel is ON</li> |
| </ul></li> |
| <li><strong>LL FMC</strong> driver |
| <ul> |
| <li>Fix compilation warning with gcc -Wpedantic compiler option</li> |
| </ul></li> |
| <li><strong>LL GPIO</strong> driver |
| <ul> |
| <li>Update GPIO configuration order to avoid a glitch on the bus-lines when using CAN</li> |
| </ul></li> |
| <li><strong>LL OPAMP</strong> driver |
| <ul> |
| <li>Align OPAMP PowerMode definitions with others series</li> |
| </ul></li> |
| <li><strong>LL RCC</strong> driver |
| <ul> |
| <li>Update RCC private functions declaration to static</li> |
| </ul></li> |
| <li><strong>LL SPI</strong> driver |
| <ul> |
| <li>Update <em>LL_SPI_Init()</em> to et Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode</li> |
| </ul></li> |
| <li><strong>LL TIM</strong> driver |
| <ul> |
| <li>Update return value of <em>LL_TIM_GetCounterMode()</em></li> |
| <li>Update LL_TIM_ONEPULSEMODE_SINGLE and LL_TIM_ONEPULSEMODE_REPETITIVE defines description</li> |
| </ul></li> |
| <li><strong>LL USART</strong> driver |
| <ul> |
| <li>Update <em>LL_USART_ClockInit()</em> to allow the configuration of clock phase and polarity even if CR2_CLKEN is cleared</li> |
| <li>Remove useless IS_LL_USART_BRR_MAX() macro</li> |
| </ul></li> |
| </ul> |
| <p><br /> |
| </p> |
| </div> |
| </div> |
| <div class="collapse"> |
| <input type="checkbox" id="collapse-section28" aria-hidden="true"> <label for="collapse-section28" aria-hidden="true">V1.12.0 / 26-June-2020</label> |
| <div> |
| <h2 id="main-changes-3">Main Changes</h2> |
| <ul> |
| <li>Maintenance release of <strong>HAL and Low Layer</strong> drivers to include latest corrections</li> |
| <li>Update of <strong>HAL OSPI</strong> driver introducing <strong>compatibility break</strong> with previous versions</li> |
| </ul> |
| <h2 id="contents-3">Contents</h2> |
| <h3 id="halll-generic-updates-1"><strong>HAL/LL generic</strong> updates</h3> |
| <ul> |
| <li>Remove the use of keyword register in HAL/LL drivers</li> |
| </ul> |
| <h3 id="hal-drivers-updates-1"><strong>HAL Drivers</strong> updates</h3> |
| <ul> |
| <li><strong>HAL CAN</strong> driver |
| <ul> |
| <li>Update <em>HAL_CAN_GetRxMessage()</em> to remove shift on RTR field of the structure CAN_RxHeaderTypeDef</li> |
| </ul></li> |
| <li><strong>HAL DAC</strong> driver |
| <ul> |
| <li>Update <em>HAL_DAC_ConfigChannel()</em> to add correction on timout handling for sample and hold configuration on CHANNEL_2</li> |
| <li>Update <em>HAL_DAC_Stop_DMA()</em> to return HAL_OK value and avoid HAL_DAC_STATE_ERROR return value in case HAL_DMA_Abort return HAL_ERROR</li> |
| </ul></li> |
| <li><strong>HAL DCMI</strong> driver |
| <ul> |
| <li>Update <em>HAL_DCMI_Start_DMA()</em> to manage DMA transfers larger than 0xFFFF</li> |
| </ul></li> |
| <li><strong>HAL DMA</strong> driver |
| <ul> |
| <li>Update <em>HAL_DMA_PollForTransfer()</em> to move the UNLOCK process once the transfer is completed</li> |
| </ul></li> |
| <li><strong>HAL FLASH</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012-Rule-8.5 warning in HAL FLASH driver</li> |
| <li>Update __HAL_FLASH_GET_FLAG macro to correct the return value (when the flag ECCD is set to 1)</li> |
| </ul></li> |
| <li><strong>HAL GPIO</strong> driver |
| <ul> |
| <li>Add definition of GPIO_AF14_TIM2 missing for STM32L4R5xx products</li> |
| <li>Fix <em>HAL_GPIO_TogglePin()</em> to manage several pins</li> |
| </ul></li> |
| <li><strong>HAL</strong> driver |
| <ul> |
| <li>Add HAL_TickFreqTypeDef type definition for <em>HAL_SetTickFreq()</em> parameter and <em>HAL_GetTickFreq()</em> function</li> |
| </ul></li> |
| <li><strong>HAL I2C</strong> driver |
| <ul> |
| <li>Update of HAL I2C driver to correct some typo in comments</li> |
| </ul></li> |
| <li><strong>HAL LPTIM</strong> driver |
| <ul> |
| <li>Update <em>HAL_LPTIM_Init()</em> to allow digital filter configuration for external clock whatever the LPTIM clock source is</li> |
| </ul></li> |
| <li><strong>HAL NAND/NOR</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012-Rule-7.2 warning in HAL NAND/NOR drivers</li> |
| <li>Correct MISRA C:2012-Rule-10.4_a / 14.4_d / 18.4 warnings in HAL NOR drivers</li> |
| <li>Update address calculation in <em>HAL_NOR_ProgramBuffer()</em></li> |
| <li>Update <em>HAL_NOR_ProgramBuffer()</em> to fix CodeSonar warnings</li> |
| </ul></li> |
| <li><strong>HAL OPAMP</strong> driver |
| <ul> |
| <li>Update <em>HAL_OPAMP_Init()</em> to fix CodeSonar warnings</li> |
| </ul></li> |
| <li><strong>HAL OSPI</strong> driver |
| <ul> |
| <li>Update <em>HAL_OSPIM_Config()</em> to adapt the assert checks with OCTOSPI selected mode</li> |
| <li><strong>The following updates introduce compatibility break with previous version of HAL OSPI driver</strong> |
| <ul> |
| <li>The wrap functionality is no more supported by the STM32L4+ products : |
| <ul> |
| <li>Remove WrapSize field of the initialization structure OSPI_InitTypeDef</li> |
| <li>Remove HAL_OSPI_OPTYPE_WRAP_CFG value for OperationType field within regular command structure OSPI_RegularCmdTypeDef</li> |
| </ul></li> |
| <li>The delay block can be bypassed in the STM32L4+ products : |
| <ul> |
| <li>Add DelayBlockBypass field within the initialization structure OSPI_InitTypeDef</li> |
| </ul></li> |
| <li>The multiplex mode is allowed in the OSPI IO manager for the STM32L4+ 1M products : |
| <ul> |
| <li>Add MaxTran field within the initialization structure OSPI_InitTypeDef</li> |
| </ul></li> |
| </ul></li> |
| </ul></li> |
| <li><strong>HAL RCC</strong> driver |
| <ul> |
| <li>Update IS_RCC_PLLSAI1N_VALUE() and IS_RCC_PLLSAI2N_VALUE() macros with new RCC_PLLSAI1N_MUL_8_127_SUPPORT and RCC_PLLSAI2N_MUL_8_127_SUPPORT definitions</li> |
| <li>Update RCC_HSICALIBRATION_DEFAULT definition</li> |
| <li>Update __HAL_RCC_APB1_FORCE_RESET() and __HAL_RCC_APB1_RELEASE_RESET() macros to handle RCC_APB1RSTR1 and RCC_APB1RSTR2 updates</li> |
| </ul></li> |
| <li><strong>HAL SDMMC</strong> driver |
| <ul> |
| <li>Add support of Sanitize and FTRIM/discard functions for HAL eMMC functionality</li> |
| <li>Add new API function <em>HAL_MMC_GetCardExtCSD()</em> to allow the user application to get the Extended CSD register</li> |
| <li>Update <em>HAL_MMC_InitCard()</em> and <em>HAL_SD_InitCard()</em> to fix CodeSonar warnings</li> |
| <li>Update <em>MMC_ReadExtCSD()</em> and <em>MMC_PwrClassUpdate()</em> to fix STM32CubeIDE compilation warnings</li> |
| </ul></li> |
| <li><strong>HAL SMARTCARD</strong> driver |
| <ul> |
| <li>Update NACK management in <em>HAL_SMARTCARD_Transmit()</em>, <em>HAL_SMARTCARD_Transmit_IT()</em> and <em>HAL_SMARTCARD_Transmit_DMA()</em> functions</li> |
| </ul></li> |
| <li><strong>HAL SMBUS</strong> driver |
| <ul> |
| <li>Update of HAL SMBUS driver to correct some typo in comments</li> |
| </ul></li> |
| <li><strong>HAL SPI</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012-Rule-17.8 warning in HAL SPI driver</li> |
| <li>Update <em>HAL_SPI_Transmit()</em>, <em>HAL_SPI_Receive()</em> functions to fix in 3-wires communication (disable and enable SPI)</li> |
| <li>Update <em>SPI_DMAReceiveCplt()</em> to disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines)</li> |
| <li>Update HAL SPI driver to fix timeout management inside SPI DMA xfer complete handler</li> |
| <li>Update <em>HAL_SPI_Init()</em> to handle assert on BaudRatePrescaler in Slave Motorola mode</li> |
| </ul></li> |
| <li><strong>HAL TIM</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012-Rule-2.2 warning in HAL TIM driver</li> |
| <li>Update DMA management when DMA requests are used for several channels of the same timer</li> |
| <li>Update <em>HAL_TIM_IC_Stop_DMA()</em> to stop DMA prior to disabling the channel</li> |
| <li>Add new <em>HAL_TIM_DMABurst_MultiWriteStart()</em> and <em>HAL_TIM_DMABurst_MultiReadStart()</em> API in HAL TIM driver</li> |
| <li>Update all <em>HAL_TIM_xxx_Start()</em> functions to allow the check of the TIMx_SMCR.SMS bit if the timer instance is slave mode capable</li> |
| <li>Update references to TIM_DMABASE_AF1 and TIM_DMABASE_AF2</li> |
| <li>Update <em>HAL_TIM_DMABurst_WriteStop()</em> and <em>HAL_TIM_DMABurst_ReadStop()</em> to modify calls to HAL_DMA_Abort_IT().</li> |
| </ul></li> |
| <li><strong>HAL TSC</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012-Rule-2.4 warning in HAL TSC driver</li> |
| <li>Update IS_TSC_GROUP() macro definition to manage when field ChannelIOs or ShieldIOs or SamplingIOs are set to 0</li> |
| </ul></li> |
| <li><strong>HAL UART</strong> driver |
| <ul> |
| <li>Rework BRR register value computation in <em>HAL_UART_Init()</em> for ROM size gain</li> |
| <li>Update <em>HAL_UART_IRQHandler()</em> to handle UART Receive Timeout interruption in the ISR function</li> |
| </ul></li> |
| <li><strong>HAL USART</strong> driver |
| <ul> |
| <li>Update <em>HAL_USARTEx_DisableSlaveMode()</em> to correct SlaveMode field value</li> |
| </ul></li> |
| <li><strong>HAL WWDG</strong> driver |
| <ul> |
| <li>Update WWDG clock frequency, min, and max timeout values in header description</li> |
| </ul></li> |
| </ul> |
| <h3 id="ll-drivers-updates-1"><strong>LL Drivers</strong> updates</h3> |
| <ul> |
| <li><strong>LL FMC</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012-Rule-7.2 warning in LL FMC driver</li> |
| </ul></li> |
| <li><strong>LL GPIO</strong> driver |
| <ul> |
| <li>Fix <em>LL_GPIO_TogglePin()</em> to manage several pins</li> |
| <li>Update <em>LL_GPIO_TogglePin()</em> to use the BSRR register rather than reading / modifying the ODR.</li> |
| </ul></li> |
| <li><strong>LL I2C</strong> driver |
| <ul> |
| <li>Update of LL I2C driver to correct some typo in comments</li> |
| </ul></li> |
| <li><strong>LL RCC</strong> driver |
| <ul> |
| <li>Update LL_RCC_HSI_SetCalibTrimming definition</li> |
| </ul></li> |
| <li><strong>LL TIM</strong> driver |
| <ul> |
| <li>Update RepetitionCounter parameter in <em>LL_TIM_StructInit()</em></li> |
| <li>Invert LL_TIM_COUNTERMODE_CENTER_DOWN and LL_TIM_COUNTERMODE_CENTER_UP definitions</li> |
| </ul></li> |
| </ul> |
| </div> |
| </div> |
| <div class="collapse"> |
| <input type="checkbox" id="collapse-section27" aria-hidden="true"> <label for="collapse-section27" aria-hidden="true">V1.11.1 / 07-February-2020</label> |
| <div> |
| <h2 id="main-changes-4">Main Changes</h2> |
| <ul> |
| <li>Patch release of <strong>HAL and Low Layer</strong> drivers to include latest corrections</li> |
| </ul> |
| <h2 id="contents-4">Contents</h2> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p> |
| <ul> |
| <li><strong>HAL GPIO</strong> driver |
| <ul> |
| <li>Update <em>HAL_GPIO_Init()</em> initialization sequence to modify the order of GPIO registers update</li> |
| </ul></li> |
| <li><strong>HAL I2C</strong> driver |
| <ul> |
| <li>Update <em>I2C_Enable_IRQ()</em> function to remove incorrect interrupts enable when InterruptRequest = I2C_XFER_CPLT_IT</li> |
| <li>Update <em>I2C_DMAXferCplt()</em>, <em>I2C_DMAError()</em> and <em>I2C_DMAAbort()</em> functions to avoid null pointer exceptions</li> |
| <li>Update <em>HAL_I2C_Master_Seq_Transmit/Receive_IT/DMA()</em> functions to set correct condition range</li> |
| <li>Update <em>I2C_ITMasterCplt()</em> to remove C++ compilation warning due to unused variable</li> |
| </ul></li> |
| <li><strong>HAL RTC</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012-Rule-3.1 warning in RTC driver</li> |
| </ul></li> |
| <li><strong>HAL SDMMC</strong> driver |
| <ul> |
| <li>Update <em>MMC_InitCard()</em> function to add missing correction for eMMC card size computation issue</li> |
| <li>Update <em>SD_UltraHighSpeed()</em> and <em>SD_DDR_Mode()</em> functions to remove useless assignment</li> |
| <li>Correct MISRA C:2012 warnings in SDMMC driver (rules 10.4_a, 10.7, 13.5, 15.7, 2.2_c)</li> |
| </ul></li> |
| <li><strong>HAL SMBUS</strong> driver |
| <ul> |
| <li>Update IS_SMBUS_TRANSFER_OPTIONS_REQUEST macro definition to include transfers with PEC</li> |
| <li>Correct MISRA C:2012-Rule-2.4 warning in structure __SMBUS_HandleTypeDef definition</li> |
| </ul></li> |
| </ul> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">LL drivers changes</span></span></strong></p> |
| <ul> |
| <li><strong>LL UTILS</strong> driver |
| <ul> |
| <li>Change private <em>UTILS_SetFlashLatency()</em> function into <em>LL_SetFlashLatency()</em> public function</li> |
| <li>Update <em>LL_PLL_ConfigSystemClock_MSI/HSI/HSE()</em> functions to set expected AHB prescaler value</li> |
| </ul></li> |
| </ul> |
| </div> |
| </div> |
| <div class="collapse"> |
| <input type="checkbox" id="collapse-section26" aria-hidden="true"> <label for="collapse-section26" aria-hidden="true">V1.11.0 / 22-November-2019</label> |
| <div> |
| <h2 id="main-changes-5">Main Changes</h2> |
| <ul> |
| <li>Release of <strong>HAL and Low Layer</strong> drivers to add support of <strong>STM32L4P5xx/STM32L4Q5xx</strong> devices |
| <ul> |
| <li>New <strong>PKA</strong> and <strong>PSSI</strong> peripherals supported in <strong>new HAL/LL PKA</strong> and <strong>HAL PSSI</strong> drivers</li> |
| </ul></li> |
| <li>Superset features device STM32L4Q5xx API User Manual available (STM32L4Q5xx_User_Manual.chm)<br /> |
| </li> |
| <li>Correction of several issues applicable to other devices</li> |
| </ul> |
| <h2 id="contents-5">Contents</h2> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p> |
| <ul> |
| <li><strong>HAL</strong> driver |
| <ul> |
| <li>Add the following constants and macros definitions in stm32l4xx_hal.h for STM32L4P5xx/STM32L4Q5xx devices |
| <ul> |
| <li><span style="font-style: italic;">SYSCFG_BOOT_FMC</span></li> |
| <li><span style="font-style: italic;">SYSCFG_BOOT_OCTOPSPI1</span></li> |
| <li><span style="font-style: italic;">SYSCFG_BOOT_OCTOPSPI2</span></li> |
| <li><span style="font-style: italic;">__HAL_SYSCFG_REMAPMEMORY_FMC()</span></li> |
| <li><span style="font-style: italic;">__HAL_SYSCFG_REMAPMEMORY_OCTOSPI1()</span><br /> |
| </li> |
| <li><span style="font-style: italic;">__HAL_SYSCFG_REMAPMEMORY_OCTOSPI2()</span></li> |
| </ul></li> |
| </ul></li> |
| <li><strong>HAL ADC</strong> driver |
| <ul> |
| <li>Update <em>IS_ADC_CHANNEL()</em> macro in stm32l4xx_hal_adc_ex.h to encompass all ADC2 channels for STM32L4P5xx/STM32L4Q5xx devices</li> |
| <li>Correct channel status mask computation in <em>DMA_CalcDMAMUXChannelBaseAndMask()</em> function</li> |
| </ul></li> |
| <li><strong>HAL DAC</strong> driver |
| <ul> |
| <li>Correct <em>HAL_DAC_UnRegisterCallback()</em> API to fix compilation error when USE_HAL_DAC_REGISTER_CALLBACKS is equal to 1</li> |
| </ul></li> |
| <li><strong>HAL DFSDM</strong> driver |
| <ul> |
| <li>Update the return check of <em>HAL_DMA_Abort()</em> in <em>HAL_DFSDM_FilterRegularStop_DMA()</em> and <em>HAL_DFSDM_FilterInjectedStop_DMA()</em> APIs</li> |
| </ul></li> |
| <li><strong>HAL DMA</strong> driver |
| <ul> |
| <li>Define DMAMUX request constant <em>DMA_REQUEST_PSSI</em> in stm32l4xx_hal_dma.h to enable PSSI peripheral DMA transfers for STM32L4P5xx/STM32L4Q5xx devices<br /> |
| </li> |
| <li>Correct channel status mask computation in <em>DMA_CalcDMAMUXChannelBaseAndMask()</em> function</li> |
| </ul></li> |
| <li><strong>HAL DMA2D</strong> driver |
| <ul> |
| <li>Remove unused <em>DMA2D_ColorTypeDef</em> structure from stm32l4xx_hal_dma2d.h</li> |
| <li>Add new <em>HAL_DMA2D_CLUTStartLoad()</em> and <em>HAL_DMA2D_CLUTStartLoad_IT()</em> APIs to improve code compactness, code size and heap usage when loading CLUT</li> |
| <li>Add <span class="citation" data-cites="note">@note</span> to <em>HAL_DMA2D_CLUTLoad()</em>, <em>HAL_DMA2D_CLUTLoad_IT()</em> and <em>HAL_DMA2D_ConfigCLUT()</em> APIs to inform the user the latter are marked as obsolete and kept only to maintain compatibility with legacy</li> |
| </ul></li> |
| <li><strong>HAL FLASH</strong> driver |
| <ul> |
| <li>Correct <em>FLASH_FLAG_SR_ERRORS</em> and remove <em>FLASH_FLAG_PEMPTY</em> constants definitions in stm32l4xx_hal_flash.h for STM32L496xx/STM32L4A6xx since FLASH_SR PEMPTY bit is not defined for these devices</li> |
| <li>Update declaration of APIs <em>HAL_FLASHEx_EnableRunPowerDown()</em>, <em>HAL_FLASHEx_DisableRunPowerDown()</em> and <em>HAL_FLASHEx_OB_DBankConfig()</em> in stm32l4xx_flash_ramfunc.h and stm32l4xx_flash_ramfunc.c to implement new <span style="font-style: italic;">__RAM_FUNC</span> definition</li> |
| <li>Correct API <em>FLASH_PageErase()</em> in stm32l4xx_hal_flash_ex.c to make sure DBANK bit of FLASH_OPTR register is tested before a page erasure for STM32L4P5xx/STM32L4Q5xx devices</li> |
| </ul></li> |
| <li><strong>HAL FMC</strong> driver |
| <ul> |
| <li>Add PSRAM chip select counter management for STM32L4P5xx/STM32L4Q5xx devices in the following APIs |
| <ul> |
| <li><em>FMC_NORSRAM_Init()</em></li> |
| <li><em>FMC_NORSRAM_DeInit()</em></li> |
| </ul></li> |
| </ul></li> |
| <li><strong>HAL GENERIC</strong> driver |
| <ul> |
| <li>Correct <span style="font-style: italic;">__RAM_FUNC</span> define in stm32l4xx_hal_def.h in order not to impose function type</li> |
| </ul></li> |
| <li><strong>HAL GPIO</strong> driver |
| <ul> |
| <li>Add <em>GPIO_AF11_SDMMC2</em> and <em>GPIO_AF12_SDMMC2</em> alternate functions definitions in stm32l4xx_hal_gpio_ex.h for STM32L4P5xx/STM32L4Q5xx devices<br /> |
| </li> |
| <li>Define PSSI alternalte functions definitions <em>GPIO_AF4_PSSI</em>, <em>GPIO_AF5_PSSI</em> and <em>GPIO_AF10_PSSI</em> for STM32L4P5xx/STM32L4Q5xx devices</li> |
| </ul></li> |
| <li><strong>HAL HASH</strong> driver |
| <ul> |
| <li>Correct phase management issue when performing two successive hash operations on two different buffers</li> |
| <li>Enhance digest computation in polling mode in authorizing hashing of empty buffers</li> |
| <li>Fix Misra C:2012 Rule-5.1 warning on identifiers to be distinct in the first 31 characters in renaming all <em>HAL_HASH_xxx_Accumulate_yy()</em> and <em>HAL_HASHEx_xxx_Accumulate_yy()</em> APIs respectively into <em>HAL_HASH_xxx_Accmlt_yy()</em> and <em>HAL_HASHEx_xxx_Accmlt_yy()</em></li> |
| <li>Create new APIs to wrap-up multi-buffer hashing processing in polling and interrupt modes |
| <ul> |
| <li><em>HAL_HASH_MD5_Accmlt_End()</em></li> |
| <li><em>HAL_HASH_SHA1_Accmlt_End()</em></li> |
| <li><em>HAL_HASHEx_SHA224_Accmlt_End()</em></li> |
| <li><em>HAL_HASHEx_SHA256_Accmlt_End()</em></li> |
| <li><em>HAL_HASH_MD5_Accmlt_End_IT()</em><br /> |
| </li> |
| <li><em>HAL_HASH_SHA1_Accmlt_End_IT()</em></li> |
| <li><em>HAL_HASHEx_SHA224_Accmlt_End_IT()</em></li> |
| <li><em>HAL_HASHEx_SHA256_Accmlt_End_IT()</em></li> |
| </ul></li> |
| <li>Update example 32L4P5GDISCOVERY/Examples/HASH/HASH_HMAC_SHA224SHA256_MultiBuffer_DMA to illustrate how to use one of these APIs listed above</li> |
| <li>Ensure processing suspension flag is reset to HAL_HASH_SUSPEND_NONE value in <em>HAL_HASH_Init()</em> API</li> |
| </ul></li> |
| <li><strong>HAL I2C</strong> driver |
| <ul> |
| <li>Fix slave interrupt handling issue in checking STOPF bit at the beginning of the interrupt handling and no more at the end. Correction done in both <em>I2C_Slave_ISR_IT()</em> and <em>I2C_Slave_ISR_DMA()</em> static functions to consider interrupt and DMA cases.</li> |
| <li>Fix Misra C:2012 Rule-2.2_c warning on value assigned to a never used variable in <em>I2C_Slave_ISR_IT()</em> static function</li> |
| </ul></li> |
| <li><strong>HAL MMC</strong> driver |
| <ul> |
| <li>Implement DDR mode and High Speed feature for STM32L4P5xx/STM32L4Q5xx and STM32L4Rx/STM32L4Sx devices |
| <ul> |
| <li>Add new API <em>HAL_MMC_ConfigSpeedBusOperation()</em> to configure the speed bus<br /> |
| </li> |
| </ul></li> |
| <li>Correct <em>BLOCKSIZE</em> constant into <em>MMC_BLOCKSIZE</em> in <em>HAL_MMCEx_ConfigDMAMultiBuffer()</em> API</li> |
| <li>Implement DDR mode and high speed feature, applicable only to STM32L4P5xx/STM32L4Q5xx and STM32L4Rx/STM32L4Sx devices</li> |
| <li>eMMC card size computation issue correction<br /> |
| </li> |
| <li>Multi-block write issue correction</li> |
| </ul></li> |
| <li><strong>HAL OCTOSPI</strong> driver |
| <ul> |
| <li>Add OCTOSPI_DCR4_REFRESH register management for STM32L4P5xx/STM32L4Q5xx devices</li> |
| </ul></li> |
| <li><strong>HAL PCD</strong> driver |
| <ul> |
| <li>Update <em>PCD_EP_ISR_Handler()</em> API to re-enable EP OUT before copying data from IP buffer PMA to SRAM in order to improve data throughput</li> |
| </ul></li> |
| <li><strong>HAL PKA</strong> driver <strong>(NEW)</strong> |
| <ul> |
| <li>New stm32l4xx_hal_pka.h, stm32l4xx_hal_pka.c files (driver enabled with HAL_PKA_MODULE_ENABLED in stm32l4xx_hal_conf.h file)</li> |
| </ul></li> |
| <li><strong>HAL PSSI</strong> driver <strong>(NEW)</strong> |
| <ul> |
| <li>New stm32l4xx_hal_pssi.h, stm32l4xx_hal_pssi.c files (driver enabled with HAL_PSSI_MODULE_ENABLED in stm32l4xx_hal_conf.h file)</li> |
| </ul></li> |
| <li><strong>HAL PWR</strong> driver |
| <ul> |
| <li>Add new API <em>HAL_PWREx_SetSRAM2ContentRetention()</em> offering finer SRAM2 area retention in Standby mode for STM32L4P5xx/L4Q5xx devices (no retention, full retention or 4 Kbytes retention only) compared with other STM32L4 devices (no retention or full retention only)</li> |
| </ul></li> |
| <li><strong>HAL RCC</strong> driver |
| <ul> |
| <li>Add PSSI peripheral related macros |
| <ul> |
| <li><span style="font-style: italic;">__HAL_RCC_PSSI_CLK_ENABLE()</span><br /> |
| </li> |
| <li><span style="font-style: italic;">__HAL_RCC_PSSI_CLK_DISABLE()</span><br /> |
| </li> |
| <li><span style="font-style: italic;">__HAL_RCC_PSSI_IS_CLK_ENABLED()</span><br /> |
| </li> |
| <li><span style="font-style: italic;">__HAL_RCC_PSSI_IS_CLK_DISABLED()</span><br /> |
| </li> |
| <li><span style="font-style: italic;">__HAL_RCC_PSSI_FORCE_RESET()</span><br /> |
| </li> |
| <li><span style="font-style: italic;">__HAL_RCC_PSSI_RELEASE_RESET()</span><br /> |
| </li> |
| <li><span style="font-style: italic;">__HAL_RCC_PSSI_CLK_SLEEP_ENABLE()</span><br /> |
| </li> |
| <li><span style="font-style: italic;">__HAL_RCC_PSSI_CLK_SLEEP_DISABLE()</span><br /> |
| </li> |
| <li><span style="font-style: italic;">__HAL_RCC_PSSI_IS_CLK_SLEEP_ENABLED()</span><br /> |
| </li> |
| <li><span style="font-style: italic;">__HAL_RCC_PSSI_IS_CLK_SLEEP_DISABLED()</span><br /> |
| </li> |
| </ul></li> |
| <li>Add <em>HAL_RCCEx_OCTOSPIDelayConfig()</em> API to manage RCC_DLYCFGR register to configure OCTOSPI instances DQS delays. Applicable only to STM32L4P5xx/STM32L4Q5xx and STM32L4Rx/STM32L4Sx devices.</li> |
| <li>Correct <em>HAL_RCC_OscConfig()</em> API |
| <ul> |
| <li>to make sure Flash latency is decreased only when MSI is the system clock source</li> |
| <li>to ensure the PLL source is not updated when already used as PLLSAI(s) clock source</li> |
| </ul></li> |
| <li>Add the following macros to test whether or not OctoSPI clocks are enabled |
| <ul> |
| <li><span style="font-style: italic;">__HAL_RCC_OSPI1_IS_CLK_ENABLED()</span></li> |
| <li><span style="font-style: italic;">__HAL_RCC_OSPI2_IS_CLK_ENABLED()</span></li> |
| <li><span style="font-style: italic;">__HAL_RCC_OSPI1_IS_CLK_DISABLED()</span></li> |
| <li><span style="font-style: italic;">__HAL_RCC_OSPI2_IS_CLK_DISABLED()</span><br /> |
| </li> |
| </ul></li> |
| <li>Correct MISRA C:2012-Rule-21.1 warning in updating the defines created to prevent recursive inclusion in stm32l4xx_hal_rcc.h and stm32l4xx_hal_rcc_ex.h</li> |
| </ul></li> |
| <li><strong>HAL RNG</strong> driver |
| <ul> |
| <li>Deliver new APIs <em>HAL_RNGEx_SetConfig()</em>, <em>HAL_RNGEx_GetConfig()</em> and <em>HAL_RNGEx_LockConfig()</em> to open entropy configuration for new hardware peripheral version available on STM32L4P5xx/L4Q5xx APIs declared and defined in <strong>new files</strong> stm32l4xx_hal_rng_ex.h and stm32l4xx_hal_rng_ex.c</li> |
| <li>Update <em>HAL_RNG_GenerateRandomNumber()</em> and <em>HAL_RNG_ReadyDataCallback()</em> APIs comments to reflect the peripheral behavior when output random data are available in an output buffer</li> |
| <li>Correct seed or clock error setting in <em>HAL_RNG_IRQHandler()</em> API</li> |
| <li>Align all defines related to NISTN bit to new NISTC naming. Applicable only to STM32L4P5xx/STM32L4Q5xx devices.</li> |
| </ul></li> |
| <li><strong>HAL RTC</strong> driver |
| <ul> |
| <li>Correct tamper management in <em>HAL_RTCEx_SetTamper()</em> and <em>HAL_RTCEx_SetTamper_IT()</em> APIs to allow individual configuration of the fields Interrupt Enable IE, NOERASE and Mask Flag MF for each tamper channel</li> |
| <li>Correct <em>HAL_RTC_SetAlarm_IT()</em> API so that alarm can be set without having to be deactivated beforehand</li> |
| <li>Remove redundant condition from <em>HAL_RTC_Init()</em> to correct CodeSonar warning</li> |
| <li>Implement binary mode feature specific to STM32L4P5xx/STM32L4Q5xx devices |
| <ul> |
| <li>Add new field <em>BinaryAutoClr</em> in <em>RTC_AlarmTypeDef</em> structure</li> |
| <li>Add new fields <em>BinMode</em> and <em>BinMixBcdU</em> in <em>RTC_InitTypeDef</em> structure<br /> |
| </li> |
| </ul></li> |
| <li>Implement sub-second register underflow feature specific to STM32L4P5xx/STM32L4Q5xx devices |
| <ul> |
| <li>Create new APIs |
| <ul> |
| <li><em>HAL_RTCEx_SetSSRU_IT()</em></li> |
| <li><em>HAL_RTCEx_DeactivateSSRU()</em></li> |
| <li><em>HAL_RTCEx_SSRUIRQHandler()</em></li> |
| <li><em>HAL_RTCEx_SSRUEventCallback()</em></li> |
| </ul></li> |
| </ul></li> |
| </ul></li> |
| <li><strong>HAL SAI</strong> driver |
| <ul> |
| <li>Update code to remove tests on part numbers replaced on tests on SAI2 instance</li> |
| <li>Update the return check of <em>HAL_DMA_Abort()</em> in <em>HAL_SAI_DMAStop()</em> and <em>HAL_SAI_Abort()</em> APIs</li> |
| </ul></li> |
| <li><strong>HAL TIM</strong> driver |
| <ul> |
| <li>Add TIM update interrupt flag remap constants definitions |
| <ul> |
| <li>TIM_UIFREMAP_DISABLE</li> |
| <li>TIM_UIFREMAP_ENABLE</li> |
| </ul></li> |
| <li>Add TIM encoder input polarity constants definitions |
| <ul> |
| <li>TIM_INPUTCHANNELPOLARITY_RISING</li> |
| <li>TIM_INPUTCHANNELPOLARITY_FALLING</li> |
| </ul></li> |
| <li>Add macros to force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31) |
| <ul> |
| <li><span style="font-style: italic;">__HAL_TIM_UIFREMAP_ENABLE()</span></li> |
| <li><span style="font-style: italic;">__HAL_TIM_UIFREMAP_DISABLE()</span><br /> |
| </li> |
| </ul></li> |
| <li>Add <span style="font-style: italic;">__HAL_TIM_GET_UIFCPY()</span> macro to retrieve update interrupt flag (UIF) copy status</li> |
| <li>Add macros to manage fast mode for a given channel |
| <ul> |
| <li><span style="font-style: italic;">__HAL_TIM_ENABLE_OCxFAST()</span></li> |
| <li><span style="font-style: italic;">__HAL_TIM_DISABLE_OCxFAST()</span></li> |
| </ul></li> |
| </ul></li> |
| <li><strong>HAL UART</strong> driver |
| <ul> |
| <li>Add new APIs <em>HAL_UART_ReceiverTimeout_Config()</em>, <em>HAL_UART_EnableReceiverTimeout()</em> and <em>HAL_UART_DisableReceiverTimeout()</em> to update on the fly the receiver timeout value in RTOR register</li> |
| <li>Remove redundant condition on <em>UART_CLOCKSOURCE_UNDEFINED</em> in <em>UART_SetConfig()</em> API</li> |
| <li>Update HAL_UART_Transmit() and HAL_UART_Receive() functions to avoid deadlock problem while mixing polling Transmit and Receive requests</li> |
| <li>Update API description of HAL_UART_Transmit(), HAL_UART_Receive(), HAL_UART_Transmit_IT(), HAL_UART_Receive_IT(), HAL_UART_Transmit_DMA(), HAL_UART_Receive_DMA()</li> |
| <li>Correct MISRA C:2012-Rule-21.1 warning in updating the defines created to prevent recursive inclusion in stm32l4xx_hal_uart.h and stm32l4xx_hal_uart_ex.h</li> |
| <li>Correct MISRA C:2012-Rule-2.2_c warning in removing unnecessary initializations in stm32l4xx_hal_uart.c and stm32l4xx_hal_uart_ex.c</li> |
| <li>Correct MISRA C:2012-Rule-18.4 in <em>HAL_UART_Transmit()</em> and <em>HAL_UART_Receive()</em> APIs so that `+=’ operator is not applied to a pointer</li> |
| <li>Correct MISRA C:2012-Rule15.7 warning to remove all empty else clauses in stm32l4xx_hal_uart.c and stm32l4xx_hal_uart_ex.h</li> |
| <li>Correct MISRA C:2012-Rule-17.7 warning in all calls of <em>HAL_DMA_Abort()</em> API so that its return value is not discarded</li> |
| <li>Correct MISRA C:2012-Rule-13.5 for all tests with logical operators</li> |
| <li>Correct MISRA C:2012-Rule-18.1_x to ensure numerator[] and denominator[] arrays in static function <em>UARTEx_SetNbDataToProcess()</em> are not out of bounds</li> |
| <li>Correct MISRA C:2012-Rule-10.6 warning in suppressing implicit widening and unused value in <em>UART_SetConfig()</em> API in stm32l4xx_hal_uart.c</li> |
| <li>Correct MISRA C:2012-Rule-10.4_a warning in suppressing superfluous mask in <em>HAL_UART_Receive()</em> API in stm32l4xx_hal_uart.c</li> |
| </ul></li> |
| <li><strong>HAL USART</strong> driver |
| <ul> |
| <li>Update <em>USART_SetConfig()</em> to remove functions as argument out of macros</li> |
| </ul></li> |
| </ul> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">LL drivers changes</span></span></strong></p> |
| <ul> |
| <li><strong>LL ADC</strong> driver |
| <ul> |
| <li>Add new macros to respectively set and remove internal channels from the ADC peripheral configuration |
| <ul> |
| <li><em>LL_ADC_SetCommonPathInternalChAdd()</em></li> |
| <li><em>LL_ADC_SetCommonPathInternalChRem()</em></li> |
| </ul></li> |
| </ul></li> |
| <li><strong>LL DMA</strong> driver |
| <ul> |
| <li>Define DMAMUX request constant <em>LL_DMAMUX_REQ_PSSI</em> in stm32l4xx_ll_dmamux.h to enable PSSI peripheral DMA transfers for STM32L4P5xx/STM32L4Q5xx devices</li> |
| </ul></li> |
| <li><strong>LL FMC</strong> driver |
| <ul> |
| <li>Fix MS Visual 2017 compilation error in <em>FMC_NORSRAM_Init()</em> in removing the compilation switch from the macro definition</li> |
| </ul></li> |
| <li><strong>LL PKA</strong> driver <strong>(NEW)</strong> |
| <ul> |
| <li>New stm32l4xx_ll_pka.h, stm32l4xx_ll_pka.c files</li> |
| </ul></li> |
| <li><strong>LL PWR</strong> driver |
| <ul> |
| <li>Add new APIs <em>LL_PWR_SetSRAM2ContentRetention()</em> and <em>LL_PWR_GetSRAM2ContentRetention()</em> offering finer SRAM2 area retention in Standby mode for STM32L4P5xx/L4Q5xx devices (no retention, full retention or 4 Kbytes retention only) compared with other STM32L4 devices (no retention or full retention only)</li> |
| </ul></li> |
| <li><strong>LL RNG</strong> driver |
| <ul> |
| <li>Align all defines and macros related to NISTN bit to new NISTC naming. Applicable only to STM32L4P5xx/STM32L4Q5xx devices.</li> |
| </ul></li> |
| <li><strong>LL RCC</strong> driver |
| <ul> |
| <li>Add <em>LL_RCC_OCTOSPI1_DelayConfig()</em> and <em>LL_RCC_OCTOSPI2_DelayConfig()</em> API to manage RCC_DLYCFGR register to configure OCTOSPI instances DQS delays. Applicable only to STM32L4P5xx/STM32L4Q5xx and STM32L4Rx/STM32L4Sx devices.</li> |
| <li>Add <em>LL_AHB2_GRP1_PERIPH_PKA</em> constant definition in stm32l4xx_ll_bus.h for new PKA driver</li> |
| </ul></li> |
| <li><strong>LL RTC</strong> driver |
| <ul> |
| <li>Implement binary mode feature specific to STM32L4P5xx/STM32L4Q5xx devices |
| <ul> |
| <li>Create new APIs for binary mode management |
| <ul> |
| <li><em>LL_RTC_SetBinaryMode()</em></li> |
| <li><em>LL_RTC_GetBinaryMode()</em></li> |
| <li><em>LL_RTC_SetBinMixBCDU()</em></li> |
| <li><em>LL_RTC_GetBinMixBCDU()</em></li> |
| </ul></li> |
| <li>Create new APIS for binary mode autoclear |
| <ul> |
| <li><em>LL_RTC_ALMA_SetBinAutoClr()</em></li> |
| <li><em>LL_RTC_ALMA_GetBinAutoClr()</em></li> |
| <li><em>LL_RTC_ALMB_SetBinAutoClr()</em></li> |
| <li><em>LL_RTC_ALMB_GetBinAutoClr()</em></li> |
| </ul></li> |
| </ul></li> |
| <li>Implement sub-second register underflow feature specific to STM32L4P5xx/STM32L4Q5xx devices |
| <ul> |
| <li>Create new APIS |
| <ul> |
| <li><em>LL_RTC_IsActiveFlag_SSRU()</em></li> |
| <li><em>LL_RTC_ClearFlag_SSRU()</em></li> |
| <li><em>LL_RTC_IsActiveFlag_SSRUM()</em></li> |
| <li><em>LL_RTC_EnableIT_SSRU()</em></li> |
| <li><em>LL_RTC_DisableIT_SSRU()</em></li> |
| <li><em>LL_RTC_IsEnabledIT_SSRU()</em><br /> |
| </li> |
| </ul></li> |
| </ul></li> |
| <li>Correct <em>LL_RTC_SCR_ALRAF</em> constant misspelling</li> |
| </ul></li> |
| <li><strong>LL TIM</strong> driver |
| <ul> |
| <li>Add new macro <em>LL_TIM_IsActiveUIFCPY()</em> to indicate whether update interrupt flag (UIF) copy is set</li> |
| </ul></li> |
| <li><strong>LL UART</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012-Rule-21.1 warning in updating the defines created to prevent recursive inclusion in stm32l4xx_ll_uart.h</li> |
| <li>Correct MISRA C:2012-Rule-12.1 warning in adding parentheses around RXThreshold and TXThreshold in <em>LL_LPUART_ConfigFIFOsThreshold()</em> API</li> |
| <li>Correct comment on BBR check in stm32l4xx_ll_uart.c</li> |
| <li>Add mask in <em>LL_LPUART_ReceiveData8()</em> API in stm32l4xx_ll_uart.h to ensure proper cast operation</li> |
| <li>Ensure proper return value in <em>LL_LPUART_GetBaudRate()</em> API in stm32l4xx_ll_uart.h</li> |
| </ul></li> |
| <li><strong>LL USART</strong> driver |
| <ul> |
| <li>Add mask in <em>LL_USART_ReceiveData8()</em> API in stm32l4xx_ll_usart.h to ensure proper cast operation</li> |
| </ul></li> |
| <li><strong>LL USB</strong> driver |
| <ul> |
| <li>Correct <em>USB_DeactivateEndpoint()</em> and <em>USB_DeactivateDedicatedEndpoint()</em> APIs in stm32l4xx_ll_usb.c file to make sure the end point is disabled during deactivation</li> |
| <li>Correct local variable <em>wEpRegVal</em> type in <em>USB_ActivateEndpoint()</em> API</li> |
| </ul></li> |
| </ul> |
| </div> |
| </div> |
| <div class="collapse"> |
| <input type="checkbox" id="collapse-section22" aria-hidden="true"> <label for="collapse-section22" aria-hidden="true">V1.10.0 / 03-April-2019</label> |
| <div> |
| <h2 id="main-changes-6">Main Changes</h2> |
| <ul> |
| <li>Delivery of the new HAL MMC driver</li> |
| </ul> |
| <h2 id="contents-6">Contents</h2> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p> |
| <ul> |
| <li><strong>HAL ADC</strong> driver |
| <ul> |
| <li>Ensure channel number is properly cast in uint32_t in LL_ADC_SetChannelSamplingTime() macro calls</li> |
| <li>Ensure offset parameter is properly cast in uint32_t in ADC_OFFSET_SHIFT_RESOLUTION() macro calls</li> |
| <li>Correct ADC_EXTERNALTRIG_T4_TRGO constant definition in stm32l4xx_hal_adc.h</li> |
| <li>Correct MISRA C:2012-Rule-2.4 warning in structure __ADC_HandleTypeDef definition</li> |
| </ul></li> |
| <li><strong>HAL COMP</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012 Rule-2.4 warning in structure __COMP_HandleTypeDef definition</li> |
| </ul></li> |
| <li><strong>HAL CRC</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012 Rule-21.1 warning in removing underscores at the beginning of the defines set to prevent recursive inclusion</li> |
| </ul></li> |
| <li><strong>HAL CRYP</strong> driver |
| <ul> |
| <li>In HAL_CRYPEx_Read_SuspendRegisters() API, ensure that check of AES_SR_BUSY flag before processing suspension is done only in GCM mode</li> |
| </ul></li> |
| <li><strong>HAL DAC</strong> driver |
| <ul> |
| <li>Correct HAL_DAC_Start() in SW trigger mode for STM32L4Rx/STM32L4Sx products</li> |
| <li>Fix callback identifiers enum values</li> |
| </ul></li> |
| <li><strong>HAL DFSDM</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012 Rule-2.4 warning in structures __DFSDM_Channel_HandleTypeDef and __DFSDM_Filter_HandleTypeDef definitions</li> |
| </ul></li> |
| <li><strong>HAL DMA</strong> driver |
| <ul> |
| <li>Correct HAL_DMA_Abort() to add check of HAL_DMA_STATE_BUSY state</li> |
| </ul></li> |
| <li><strong>HAL DSI</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012 Rule-18.3 and Rule-2.4 warning in structure __DSI_HandleTypeDef definition</li> |
| <li>Correct HAL_DSI_ShortWrite() and HAL_DSI_Read to fix lock issue</li> |
| <li>Correct HAL_DSI_Read() to be able to read more than two parameters</li> |
| </ul></li> |
| <li><strong>HAL FLASH</strong> driver |
| <ul> |
| <li>Correct the address of PCROP area management in FLASH_OB_GetPCROP() API to include the last double-word</li> |
| <li>Correct IS_OB_USER_TYPE() macro to include nBoot0 and nSwBoot0 for STM32L496xx/L4A6xx devices</li> |
| <li>Correct FLASH_SIZE constant definition when 0x1FFF75E0 address content is undefined</li> |
| <li>Correct FLASH_Program_Fast() to ensure Interrupt mask is not lost during Fast Programming sequence</li> |
| <li>Update FLASH_Program_DoubleWord() to ensure programming is performed in 2 steps, in the right order, independently of compiler optimizations</li> |
| <li>Correct MISRA C:2012 Rule-8.5_b related to multiple declarations of externally-linked object</li> |
| </ul></li> |
| <li><strong>HAL GENERIC</strong> driver |
| <ul> |
| <li>Correct HAL_SYSCFG_EnableMemorySwappingBank() API for proper memory swapping</li> |
| <li>Update stm32l4xx_hal_conf_template.h to add HAL_EXTI_MODULE_ENABLED following HAL EXTI creation in V1.9.0</li> |
| <li>Update stm32l4xx_hal_conf_template.h to add HAL_MMC_MODULE_ENABLED following HAL MMC creation</li> |
| </ul></li> |
| <li><strong>HAL GFXMMU</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012 Rule-2.4 warning in structure __GFXMMU_HandleTypeDef definition</li> |
| </ul></li> |
| <li><strong>HAL GPIO</strong> driver |
| <ul> |
| <li>Enhance reentrancy robustness for HAL_GPIO_TogglePin() API</li> |
| <li>Update the external interrupt or event clear operation in HAL_GPIO_DeInit()API</li> |
| <li>Add comment in HAL_GPIO_LockPin() API to justify an unused read of a register</li> |
| <li>Correct IAR v8.30.1 warning in IS_GPIO_PIN_ACTION() macro</li> |
| </ul></li> |
| <li><strong>HAL HASH</strong> driver |
| <ul> |
| <li>Add HAL_HASH_SHA1_Accumulate_IT(), HAL_HASH_MD5_Accumulate_IT(), HAL_HASHEx_SHA224_Accumulate_IT() and HAL_HASHEx_SHA256_Accumulate_IT() manage multi-buffer messages in interrupt mode.</li> |
| <li>Correct HASH handle state management in DMA transfer mode</li> |
| <li>Add comments to describe case of messages made of several parts, not all with length multiple of 4 bytes</li> |
| <li>Fix comments in HAL_HASH_DMAFeed_ProcessSuspend()</li> |
| </ul></li> |
| <li><strong>HAL HCD</strong> driver |
| <ul> |
| <li>Rework usb modules define protection</li> |
| <li>Correct MISRA C:2012 Rule-21.1 warning in removing underscores at the beginning of the defines set to prevent recursive inclusion</li> |
| <li>Correct CodeSonar warning in HAL_HCD_Init()</li> |
| <li>Update HAL_HCD_HC_Init() in order to not expose HCD high speed in case hardware supports only FS mode</li> |
| </ul></li> |
| <li><strong>HAL IRDA</strong> driver |
| <ul> |
| <li>Correct IAR v8.30.1 warning in IRDA_GETCLOCKSOURCE() macro and IRDA_SetConfig() static function</li> |
| </ul></li> |
| <li><strong>HAL IWDG</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012 Rule-21.1 warning in removing underscores at the beginning of the defines set to prevent recursive inclusion</li> |
| <li>Correct __IWDG_HandleTypeDef structure definition in stm32l4xx_hal_iwdg.h</li> |
| </ul></li> |
| <li><strong>HAL LPTIM</strong> driver |
| <ul> |
| <li>Correct __HAL_LPTIM_REPETITIONCOUNTER_GET() macro parameter description</li> |
| <li>Correct LPTIM_Disable() so that __HAL_RCC_LPTIM1_CONFIG uses RCC constants instead of 0UL value</li> |
| </ul></li> |
| <li><strong>HAL LTDC</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012 Rule-2.4 issue</li> |
| </ul></li> |
| <li><strong>HAL MMC</strong> driver <strong>(NEW)</strong> |
| <ul> |
| <li>New stm32l4xx_hal_mmc.h, stm32l4xx_hal_mmc.c, stm32l4xx_hal_mmc_ex.h, stm32l4xx_hal_mmc_ex.c files (driver enabled with HAL_MMC_MODULE_ENABLED in stm32l4xx_hal_conf.h file)</li> |
| </ul></li> |
| <li><strong>HAL OCTOSPI</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012 Rule-5.4_c99 warning in stm32l4xx_hal_ospi.h</li> |
| </ul></li> |
| <li><strong>HAL OPAMP</strong> driver |
| <ul> |
| <li>Fix callback identifiers enum values</li> |
| </ul></li> |
| <li><strong>HAL PCD</strong> driver |
| <ul> |
| <li>Rework usb modules define protection</li> |
| <li>Correct mask to clear USB RX number of blocks</li> |
| <li>Correct cast used in HAL_PCD_EP_GetRxCount() API</li> |
| <li>Clear status phase received interrupt in HAL_PCD_IRQHandler() API</li> |
| <li>Correct MISRA C:2012 Rule-21.1 warning in removing underscores at the beginning of the defines set to prevent recursive inclusion</li> |
| <li>Correct MISRA C:2012 Rule-8.3_b, Rule-8.3_b and Rule-2.3 warnings</li> |
| <li>Update error handling management in HAL_PCD_Init() and HAL_PCD_Stop()</li> |
| <li>Correct PCD_WriteEmptyTxFifo() to handle transfer size equal to FIFO length</li> |
| <li>Correct maximum of EP number according to the allocated buffers on hpcd structure</li> |
| <li>Correct timing setting for BCD</li> |
| <li>Correct HCD_HC_OUT_IRQHandler() to ensure correct toggle for output interrupt during transfer complete</li> |
| <li>Correct USB interrupt handler to handle EP0 OUT transfers in USB DMA mode</li> |
| <li>Ensure proper management of the BCD feature for OTG instance</li> |
| <li>Remove PCD_GET_DB_DIR() macro</li> |
| <li>Prevent enabling USB DMA for OTG FS instance</li> |
| <li>Update PCD_EP_ISR_Handler() to prevent reading from PMA to NULL pointer addr</li> |
| <li>Correct ep table size for device only IP</li> |
| <li>Fix USB exti wakeup macros</li> |
| <li>Correct HAL_PCD_IRQHandler() to ensure correct OTG core speed usage</li> |
| <li>Correct CodeSonar warning in HAL_PCD_Init()</li> |
| </ul></li> |
| <li><strong>HAL PWR</strong> driver |
| <ul> |
| <li>Correct PWR_CR3 bit name EN_ULP into ENULP</li> |
| </ul></li> |
| <li><strong>HAL QSPI</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012 Rule-2.4 warning in structure __QSPI_HandleTypeDef definition</li> |
| <li>Remove the compilation switches related to QUADSPI1 and QUADSPI2 as all STM32 families have only one instance called QUADSPI</li> |
| <li>Fix HAL_QSPI_TIMEOUT_DEFAULT_VALUE misspelling</li> |
| </ul></li> |
| <li><strong>HAL RCC</strong> driver |
| <ul> |
| <li>Correct HAL_RCCEx_GetPeriphCLKFreq() to LSIPREDIV bit is taken into account when reporting LSI-clocked peripheral frequency</li> |
| <li>Update HAL_RCC_OscConfig() to not report an error if same PLL configuration is requested</li> |
| <li>Correct __HAL_RCC_PLLxx_CONFIG() macros to preserve output clock(s) enable state</li> |
| <li>Correct HAL_RCC_GetSysClockFreq() to prevent rounding errors</li> |
| </ul></li> |
| <li><strong>HAL RTC</strong> driver |
| <ul> |
| <li>Correct HAL_RTCEx_SetWakeUpTimer_IT() to ensure __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() is called upon an interruption</li> |
| <li>Remove use of ALRBWF and ALRAWF bits</li> |
| <li>Correct cast setting of BYPSHAD bit in HAL_RTCEx_EnableBypassShadow() API</li> |
| <li>Rename RTC_IT_MASK into RTC_FLAG_MASK</li> |
| <li>Add management of INITF flag rising occurrence too early when entering init mode</li> |
| <li>Correct WUTWF flag management in HAL_RTCEx_SetWakeUpTimer() API</li> |
| <li>ensure HAL RCC doesn’t overwrite Tick priority</li> |
| </ul></li> |
| <li><strong>HAL SAI</strong> driver |
| <ul> |
| <li>Add calls of registered callbacks in HAL_SAI_IRQHandler() API</li> |
| </ul></li> |
| <li><strong>HAL SD</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012 Rule-10.4a and Rule-10.5 warnings</li> |
| <li>Correct pointer deferencing in HAL_SD_ReadBlocks() and HAL_SD_WriteBlocks() APIs</li> |
| <li>Correct gcc warning in HAL_SD_Init() API</li> |
| </ul></li> |
| <li><strong>HAL SMARTCARD</strong> driver |
| <ul> |
| <li>Correct IAR v8.30.1 warnings related to GTPR register writing</li> |
| <li>Declare ErrorCode field of __SMARTCARD_HandleTypeDef structure as volatile</li> |
| <li>Correct MISRA C:2012 Rule-13.5 warnings in HAL_SMARTCARD_IRQHandler() API</li> |
| </ul></li> |
| <li><strong>HAL SPI</strong> driver |
| <ul> |
| <li>Correct SPI communication abort procedure in HAL_SPI_Abort() API</li> |
| <li>Correct comments in SPI_AbortRx_ISR()</li> |
| <li>Correct MISRA C:2012 Rule-10.3 warnings</li> |
| </ul></li> |
| <li><strong>HAL SWPMI</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012 Rule-2.4 warning in structure __SWPMI_HandleTypeDef definition</li> |
| </ul></li> |
| <li><strong>HAL TIM</strong> driver |
| <ul> |
| <li>Correct all MISRA C:2012 warnings</li> |
| <li>Add XferHalfCpltCallback interrupt callback</li> |
| <li>Update HAL_TIMEx_ConfigCommutationEvent() to disable IT and DMA</li> |
| <li>Update comments to stress ClearInputPrescaler value must be 0 when clearing the OCxREF signal on an external event</li> |
| <li>Ensure external clock mode 2 is not selected in encoder mode</li> |
| <li>Ensure gated mode is not used if TI1F_ED is selected as the trigger input</li> |
| <li>Update the list of DMABurst related constants to match the capabilities of the Timer instances supported by the devices of the family</li> |
| </ul></li> |
| <li><strong>HAL TSC</strong> driver |
| <ul> |
| <li>Correct all MISRA C:2012 warnings</li> |
| <li>Correct __HAL_TSC_GET_GROUP_STATUS() macro definition</li> |
| </ul></li> |
| <li><strong>HAL USART</strong> driver |
| <ul> |
| <li>Update USART_RxISR_8BIT(), USART_RxISR_16BIT(), USART_RxISR_8BIT_FIFOEN() and USART_RxISR_16BIT_FIFOEN() to ensure TXFT interrupt is handled in all cases</li> |
| </ul></li> |
| </ul> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">LL drivers changes</span></span></strong></p> |
| <ul> |
| <li><strong>LL ADC</strong> driver |
| <ul> |
| <li>Correct potential infinite wait in while loop of LL_ADC_DeInit()</li> |
| <li>Redefinition of memory-mapped peripheral registers address into volatile (_IO)</li> |
| <li>Correct LL_ADC_INJ_ConfigQueueContext() so that default edge is not included by default into trigger value</li> |
| </ul></li> |
| <li><strong>LL CRC</strong> driver |
| <ul> |
| <li>Add comment to report derogation to Misra C:2012 R.11.5 rule in API LL_CRC_FeedData16()</li> |
| </ul></li> |
| <li><strong>LL DMA2D</strong> driver |
| <ul> |
| <li>Correct all MISRA C:2012 warnings</li> |
| </ul></li> |
| <li><strong>LL GPIO</strong> driver |
| <ul> |
| <li>Enhance reentrancy robustness for HAL_GPIO_TogglePin() API</li> |
| <li>Update the external interrupt or event clear operation in HAL_GPIO_DeInit() API</li> |
| <li>Add comment in LL_GPIO_LockPin() API to justify an unused read of a register</li> |
| </ul></li> |
| <li><strong>LL LPTIM</strong> driver |
| <ul> |
| <li>Correct LL_LPTIM_Init() not returns an error status while LPTIM is disabled</li> |
| </ul></li> |
| <li><strong>LL OPAMP</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012 Rule-2.7 and Rule-8.13 warnings</li> |
| </ul></li> |
| <li><strong>LL PWR</strong> driver |
| <ul> |
| <li>Correct PWR_CR3 bit name EN_ULP into ENULP</li> |
| <li>Change compilation switch to trigger LL_PWR_EnableVddUSB(), LL_PWR_DisableVddUSB() and LL_PWR_IsEnabledVddUSB() APIs definition</li> |
| <li>Redefinition of memory-mapped peripheral registers address into volatile (_IO)</li> |
| </ul></li> |
| <li><strong>LL RCC</strong> driver |
| <ul> |
| <li>Correct LL_RCC_GetLPTIMClockFreq() to LSIPREDIV bit is taken into account when reporting LSI-clocked peripheral frequency</li> |
| <li>Update LL_RCC_DeInit() to be fully operational when compiled with gcc -O3</li> |
| </ul></li> |
| <li><strong>LL RTC</strong> driver |
| <ul> |
| <li>Remove use of ALRBWF and ALRAWF bits</li> |
| <li>Correct month management in LL_RTC_DATE_Init() API and IS_LL_RTC_MONTH() macro</li> |
| </ul></li> |
| <li><strong>LL SWPMI</strong> driver |
| <ul> |
| <li>Correct return value for LL_SWPMI_ClearFlag_RDY(), LL_SWPMI_EnableIT_RDY() and LL_SWPMI_DisableIT_RDY() APIs</li> |
| </ul></li> |
| <li><strong>LL TIM</strong> driver |
| <ul> |
| <li>Redefinition of memory-mapped peripheral registers address into volatile (_IO)</li> |
| <li>Correct LL_TIM_OC_(Get/Set)CompareCH5 and LL_TIM_SetCH5CombinedChannels</li> |
| </ul></li> |
| <li><strong>LL USART</strong> driver |
| <ul> |
| <li>Correct all MISRA C:2012 warnings</li> |
| <li>Correct LL_USART_ReceiveData8() to ensure proper cast value</li> |
| </ul></li> |
| <li><strong>LL USB</strong> driver |
| <ul> |
| <li>Rework usb modules define protection</li> |
| <li>Correct USB Vbus sensing</li> |
| <li>Correct MISRA C:2012 Rule-21.1 warning in removing underscores at the beginning of the defines set to prevent recursive inclusion</li> |
| <li>Correct MISRA C:2012 Rule-8.3_b, Rule-8.3_b and Rule-2.3 warnings</li> |
| <li>Update error handling management in LL APIs</li> |
| <li>Correct maximum of EP number according to the allocated buffers on hpcd structure</li> |
| <li>Improve USB_HostInit() to manage device low speed mode</li> |
| <li>Correct USB_CoreInit() to ensure proper management of the BCD feature for OTG instance</li> |
| <li>Correct USB_EPClearStall() to manage TX EP state during ep clear stall</li> |
| <li>Correct ep table size for device only IP</li> |
| <li>Correct USB_EP0StartXfer() and USB_EPStartXfer() to prevent enabling TX fifo IT before endpoint enable</li> |
| <li>Ensure correct OTG core speed usage</li> |
| </ul></li> |
| </ul> |
| </div> |
| </div> |
| <div class="collapse"> |
| <input type="checkbox" id="collapse-section21" aria-hidden="true"> <label for="collapse-section21" aria-hidden="true">V1.9.0 / 27-July-2018</label> |
| <div> |
| <h2 id="main-changes-7">Main Changes</h2> |
| <ul> |
| <li>Release of <strong>HAL and Low Layer drivers</strong> to add support of <strong>STM32L412xx/STM32L422xx</strong></li> |
| <li>Superset features device STM32L422xx API User Manual available (STM32L422xx_User_Manual.chm) </li> |
| <li>MISRA C:2012 corrections</li> |
| </ul> |
| <h2 id="contents-7">Contents</h2> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p> |
| <p>MISRA C:2012 corrections listed hereafter are applicable to LL driver as well.</p> |
| <ul> |
| <li><p><strong>HAL ADC</strong> driver </p> |
| <ul> |
| <li>Replace private macro using concurrent volatile access (generating MIRSA errors) by temporary variables or LL helper macro</li> |
| <li>Correct MISRA C:2012 warnings reported by rules 2.2_c, 8.13, 10.1_R2, 10.1_R3, 10.1_R6, 10.4_a, 10.4_b, 10.5, 14.4_c, 12.2, 15.7</li> |
| <li>stm32l4xx_hal_adc.c and stm32l4xx_hal_adc_ex.c |
| <ul> |
| <li>Change of time-out duration computation when expressed in microseconds to manage low system clock frequencies</li> |
| </ul></li> |
| <li>stm32l4xx_hal_adc.c |
| <ul> |
| <li>Remove useless stabilization delay in ADC_Enable() when enabling ADC</li> |
| <li>In HAL_ADC_Stop_DMA(), HAL_DMA_Abort() API is called only if DMA is busy </li> |
| </ul></li> |
| <li>stm32l4xx_hal_adc.h |
| <ul> |
| <li>Typo correction in ADC_AnalogWDGConfTypeDef FilteringConfig field description</li> |
| </ul></li> |
| <li>stm32l4xx_hal_adc.c, stm32l4xx_hal_adc.h |
| <ul> |
| <li>Clarify comments in HAL_ADC_AnalogWDGConfig for analog watchdog thresholds checks when oversampling is enabled</li> |
| </ul></li> |
| </ul></li> |
| <li><strong>HAL CAN</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012 warnings reported by rules 2.2_c, 10.3, 10.4_a, 10.6, 12.2, 13.3, 13.5, 15.7, 17.7, 18.1_b</li> |
| <li>stm32l4xx_hal_can.c, stm32l4xx_hal_can.h |
| <ul> |
| <li>Tx abort procedure correction</li> |
| </ul></li> |
| <li>stm32l4xx_hal_can.c |
| <ul> |
| <li>Correct implementation of test on pending message in HAL_CAN_IsTxMessagePending() </li> |
| <li>Update HAL_CAN_Stop() to reset any previous sleep mode request to avoid maintaining the sleep mode request active at next HAL_CAN_Start()</li> |
| </ul></li> |
| </ul></li> |
| <li><strong>HAL COMP</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012 warnings reported by rules 10.1, 10.3, 10.4, 13.5</li> |
| <li>stm32l4xx_hal_comp.c |
| <ul> |
| <li>Change of time-out duration computation when expressed in microseconds to manage low system clock frequencies</li> |
| </ul></li> |
| </ul></li> |
| <li><strong>HAL CRC</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012 warnings reported by rules 10.3, 12.1, 12.2</li> |
| </ul></li> |
| <li><strong>HAL CRYP</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012 warnings reported by rules 2.2_c, 8.13, 10.3, 10.4, 10.6, 10.7, 10.8, 12.1, 13.5, 15.7, 17.7, 18.4</li> |
| <li>stm32l4xx_hal_cryp_ex.c: CodeSonar warning correction</li> |
| </ul></li> |
| <li><strong>HAL DAC</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012warnings</li> |
| </ul></li> |
| <li><strong>HAL DCMI</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012 warnings reported by rules 2.2_c, 8.4, 10.4_a, 12.1, 17.7, 18.4</li> |
| </ul></li> |
| <li><strong>HAL DMA</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012 warnings</li> |
| </ul></li> |
| <li><strong>HAL DSI</strong> driver |
| <ul> |
| <li>stm32l4xx_hal_dsi.h: add __HAL_DSI_RESET_HANDLE_STATE() macro</li> |
| </ul></li> |
| <li><strong>HAL EXTI</strong> driver <strong>(NEW)</strong> |
| <ul> |
| <li>New stm32l4xx_hal_exti.h and stm32l4xx_hal_exti.c files (driver enabled with HAL_EXTI_MODULE_ENABLED in stm32l4xx_hal_conf.h file)</li> |
| </ul></li> |
| <li><strong>HAL FIREWALL</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012 warnings reported by rules 10.4</li> |
| </ul></li> |
| <li><strong>HAL GPIO</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012 warnings reported by rules 10.3, 21.1</li> |
| </ul></li> |
| <li><strong>HAL HASH</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012 warnings reported by rules 1.3_k, 2.2_c, 9.1_f, 10.3, 12.1, 13.4_b, 13.5, 15.7, 17.7, 21.1</li> |
| <li>stm32l4xx_hal_hash.c: |
| <ul> |
| <li>in HASH_Start_DMA(), test on HASH_CR_MDMAT bit before checking input buffer length in case of multi-buffer processing</li> |
| <li>Fill-up empty statement in HAL_HASH_DMAFeed_ProcessSuspend() to correct CodeSonar warning<br /> |
| </li> |
| </ul></li> |
| </ul></li> |
| <li><strong>HAL I2C</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012 warnings</li> |
| <li>stm32l4xx_hal_i2c.c: remove extra definition of I2C_GET_DMA_REMAIN_DATA() macro<br /> |
| </li> |
| </ul></li> |
| <li><strong>HAL IRDA</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012 warnings reported by rules 2.1, 2.2_c, 2.4, 2.3, 8.9_a, 10.3, 10.4_a, 10.5, 10.6, 10.7, 11.3, 13.3, 13.5, 15.7, 17.7, 17.8, 18.4, 21.1</li> |
| </ul></li> |
| <li><strong>HAL IWDG</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012 warnings reported by rules 2.7, 10.3, 10.4_a</li> |
| </ul></li> |
| <li><strong>HAL LPTIM</strong> driver |
| <ul> |
| <li>Add repetition counter management for STM32L412xx/L422xx devices</li> |
| <li>New field RepetitionCounter added in LPTIM_InitTypeDef structure</li> |
| </ul></li> |
| <li><strong>HAL OSPI</strong> driver |
| <ul> |
| <li>stm32l4xx_hal_ospi.h: update memory type definition to support new octal PSRAM from APMemory</li> |
| </ul></li> |
| <li><strong>HAL OPAMP</strong> driver |
| <ul> |
| <li>Correct MISRA C:2012 warnings</li> |
| </ul></li> |
| <li><p><strong>HAL PWR</strong> driver</p> |
| <ul> |
| <li>Update conversion mechanism from duration in us in number of cycles to manage low system frequencies</li> |
| <li>Correct MISRA C:2012 warnings reported by rules 2.2_c, 10.3, 10.4_a, 13.5, 16.3, 17.7</li> |
| </ul></li> |
| <li><p><strong>HAL RCC</strong> driver</p> |
| <ul> |
| <li>stm32l4xx_hal_rcc.c, stm32l4xx_hal_rcc.h: compilation switches update to ensure full STM32L412xx/L422xx devices support</li> |
| <li>Correct MISRA C:2012 warnings reported by rules 2.2_c, 8.13, 8.9_a, 10.1_R2, 10.4_a, 10.3, 10.7, 11.9, 12.1, 12.2, 13.5, 14.4_c, 15.7, 21.2</li> |
| </ul></li> |
| <li><p><strong>HAL RTC</strong> driver</p> |
| <ul> |
| <li>New HAL_RTCEx_SetLowPowerCalib() API for STM32L412xx/L422xx devices</li> |
| <li>HAL_RTC_AlarmIRQHandler() API optimization</li> |
| </ul></li> |
| <li><p><strong>HAL SAI</strong> driver</p> |
| <ul> |
| <li>stm32l4xx_hal_sai.c: remove empty if statements to fix CodeSonar warning</li> |
| <li>stm32l4xx_hal_sai.h, stm32l4xx_hal_sai.c: add check on master clock divider parameter, remove SAI_FIFO_SIZE definition</li> |
| </ul></li> |
| <li><p><strong>HAL SMARTCARD</strong> driver</p> |
| <ul> |
| <li>Correct MISRA C:2012 warnings reported by rules 2.2_c, 8.9_a, 10.3, 10.4_a, 10.5, 10.6, 10.7, 12.1, 12.2, 13.3, 13.5, 15.7, 17.7, 17.8, 18.1, 21.1</li> |
| </ul></li> |
| <li><p><strong>HAL SPI</strong> driver</p> |
| <ul> |
| <li>Correct MISRA C:2012 warnings</li> |
| </ul></li> |
| <li><p><strong>HAL SWPMI</strong> driver</p> |
| <ul> |
| <li>Correct MISRA C:2012 warnings reported by rules 2.2_c, 2.7, 10.3, 10.4_a, 13.3, 13.5, 15.7, 17.7, 17.8, 21.1</li> |
| </ul></li> |
| <li><p><strong>HAL TSC</strong> driver</p> |
| <ul> |
| <li>Correct MISRA C:2012 warnings reported by rule 21.1</li> |
| </ul></li> |
| <li><p><strong>HAL USART</strong> driver</p> |
| <ul> |
| <li>Correct MISRA C:2012 warnings reported by rule 10.4_a, 10.6, 12.2</li> |
| </ul></li> |
| </ul> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">LL Drivers changes</span></span></strong></p> |
| <ul> |
| <li><p><strong>LL ADC</strong> driver</p> |
| <ul> |
| <li>stm32l4xx_ll_dmamux.h: clarify comments when oversampling is enabled</li> |
| </ul></li> |
| <li><p><strong>LL DMA</strong> driver</p> |
| <ul> |
| <li>stm32l4xx_ll_dmamux.h: remove test on DMAMUX1</li> |
| </ul></li> |
| <li><p><strong>LL RCC</strong> driver</p> |
| <ul> |
| <li>stm32l4xx_ll_rcc.c,stm32l4xx_ll_rcc.h: compilation switches update to ensure full STM32L412xx/L422xx devices support</li> |
| </ul></li> |
| <li><p><strong>LL RTC</strong> driver</p> |
| <ul> |
| <li>stm32l4xx_ll_rtc.h: add new macros LL_RTC_WAKEUP_SetAutoClr(), LL_RTC_WAKEUP_GetAutoClr() applicable to STM32L412xx/L422xx devices only</li> |
| </ul></li> |
| </ul> |
| </div> |
| </div> |
| <div class="collapse"> |
| <input type="checkbox" id="collapse-section19" aria-hidden="true"> <label for="collapse-section19" aria-hidden="true">V1.8.3 / 22-May-2018</label> |
| <div> |
| <h2 id="main-changes-8">Main Changes</h2> |
| <p>Maintenance Release of <strong>HAL and Low Layer drivers</strong></p> |
| <p><strong>Add support of HAL callback registration feature</strong></p> |
| <ul> |
| <li><p>The feature <strong>disabled by default</strong> is available for the following HAL drivers:</p></li> |
| <li><p>ADC, CAN, COMP, CRYP, DAC, DCMI, DFSDM, DMA2D, DSI, GFXMMU, HASH, HCD, I2C, IRDA, LPTIM, LTDC, OPAMP, OSPI, PCD, QSPI, RNG, RTC, SAI, SD, SMARTCARD, SMBUS, SPI, SWPMI, TIM, TSC, UART, USART and WWDG</p></li> |
| <li><p>The feature may be enabled individually per HAL <em>PPP</em> driver by setting the corresponding definition USE_HAL_<span style="font-style: italic;">PPP</span>_REGISTER_CALLBACKS to 1U in stm32l4xx_hal_conf.h project configuration file (template file stm32l4xx_hal_conf_template.h available from Drivers/STM32L4xx_HAL_Driver/Inc)</p></li> |
| <li><p>Once enabled, the user application may resort to HAL_PPP_RegisterCallback() to register specific callback function(s) and unregister it(them) with HAL_PPP_UnRegisterCallback().</p></li> |
| </ul> |
| <p>MISRA C:2012 corrections</p> |
| <h2 id="contents-8">Contents</h2> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p> |
| <ul> |
| <li><p><strong>HAL generic</strong> driver</p> |
| <ul> |
| <li>stm32l4xx_hal_conf_template.h update to add callback registration feature support (disabled by default)</li> |
| <li>stm32l4xx_hal_def.h: UNUSED() macro update for g++ compilation<br /> |
| </li> |
| </ul></li> |
| <li><p><strong>HAL ADC</strong> driver</p> |
| <ul> |
| <li>Fix to enable ADC internal channels (VrefInt, temperature sensor and Vbat) without being too restrictive</li> |
| <li><p>Update internal ADC calibration timeout value</p></li> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_ADC_RegisterCallback() and HAL_ADC_UnRegisterCallback() APIs</li> |
| <li>Add callback identifiers in HAL_ADC_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL CAN</strong> driver</p> |
| <ul> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_CAN_RegisterCallback() and HAL_CAN_UnRegisterCallback() APIs</li> |
| <li>Add callback identifiers in HAL_CAN_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL COMP</strong> driver</p> |
| <ul> |
| <li>Add callback registration feature |
| <ul> |
| <li>Add HAL_COMP_RegisterCallback() and HAL_COMP_UnRegisterCallback APIs</li> |
| <li>Add callback identifiers in HAL_COMP_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL CRYP</strong> driver</p> |
| <ul> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_CRYP_RegisterCallback() and HAL_CRYP_UnRegisterCallback APIs</li> |
| <li>Add callback identifiers in HAL_CRYP_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL DAC</strong> driver</p> |
| <ul> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_DAC_RegisterCallback() and HAL_DAC_UnRegisterCallback APIs</li> |
| <li>Add callback identifiers in HAL_DAC_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL DCMI</strong> driver</p> |
| <ul> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_DCMI_RegisterCallback() and HAL_DCMI_UnRegisterCallback APIs</li> |
| <li>Add callback identifiers in HAL_DCMI_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL DFSDM</strong> driver</p> |
| <ul> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_DFSDM_Channel_RegisterCallback(), HAL_DFSDM_Channel_UnRegisterCallback(), HAL_DFSDM_Filter_RegisterCallback(), HAL_DFSDM_Filter_UnRegisterCallback(), HAL_DFSDM_Filter_RegisterAwdCallback() and HAL_DFSDM_Filter_UnRegisterAwdCallback APIs</li> |
| <li>Add callback identifiers in HAL_DFSDM_Channel_CallbackIDTypeDef and HAL_DFSDM_Filter_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL DM2D</strong> driver</p> |
| <ul> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_DMA2D_RegisterCallback() and HAL_DMA2D_UnRegisterCallback APIs</li> |
| <li>Add callback identifiers in HAL_DMA2D_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL DSI</strong> driver</p> |
| <ul> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_DSI_RegisterCallback() and HAL_DSI_UnRegisterCallback APIs</li> |
| <li>Add callback identifiers in HAL_DSI_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL GFXMMU</strong> driver</p> |
| <ul> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_GFXMMU_RegisterCallback() and HAL_GFXMMU_UnRegisterCallback APIs</li> |
| <li>Add callback identifiers in HAL_GFXMMU_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL HASH</strong> driver</p> |
| <ul> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_HASH_RegisterCallback() and HAL_HASH_UnRegisterCallback APIs</li> |
| <li>Add callback identifiers in HAL_HASH_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL HCD</strong> driver</p> |
| <ul> |
| <li><p>Add new user notification callbacks</p> |
| <ul> |
| <li>HAL_HCD_PortEnabled_Callback() and HAL_HCD_PortDisabled_Callback()</li> |
| </ul></li> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_HCD_RegisterCallback(), HAL_HCD_UnRegisterCallback(), HAL_HCD_RegisterHC_NotifyURBChangeCallback() and HAL_HCD_UnRegisterHC_NotifyURBChangeCallback APIs</li> |
| <li>Add callback identifiers in HAL_HCD_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL I2C</strong> driver</p> |
| <ul> |
| <li><p>I2C slave enhancement when master sends RESTART instead of STOP</p> |
| <ul> |
| <li>Add HAL_I2C_Master_Sequential_Transmit_DMA(), HAL_I2C_Master_Sequential_Receive_DMA(), HAL_I2C_Slave_Sequential_Transmit_DMA() and HAL_I2C_Slave_Sequential_Receive_DMA() APIs<br /> |
| </li> |
| </ul></li> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), HAL_I2C_RegisterAddrCallback() and HAL_I2C_UnRegisterAddrCallback APIs</li> |
| <li>Add callback identifiers in HAL_I2C_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL IRDA</strong> driver</p> |
| <ul> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_IRDA_RegisterCallback() and HAL_IRDA_UnRegisterCallback APIs</li> |
| <li>Add callback identifiers in HAL_IRDA_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL LPTIM</strong> driver</p> |
| <ul> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_LPTIM_RegisterCallback() and HAL_LPTIM_UnRegisterCallback APIs</li> |
| <li>Add callback identifiers in HAL_LPTIM_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL LTDC</strong> driver</p> |
| <ul> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_LTDC_RegisterCallback() and HAL_LTDC_UnRegisterCallback APIs</li> |
| <li>Add callback identifiers in HAL_LTDC_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL NAND</strong> driver</p> |
| <ul> |
| <li><p>Add new configuration API HAL_NAND_ConfigDevice()</p></li> |
| <li><p>Add new APIs for 8-bit and 16-bit accesses</p> |
| <ul> |
| <li><p>HAL_NAND_Read_Page_8b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Read_SpareArea_8b() and HAL_NAND_Write_SpareArea_8b()</p></li> |
| <li><p>HAL_NAND_Read_Page_16b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Read_SpareArea_16b() and HAL_NAND_Write_SpareArea_16b()</p></li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL OPAMP</strong> driver</p> |
| <ul> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_OPAMP_RegisterCallback() and HAL_OPAMP_UnRegisterCallback APIs</li> |
| <li>Add callback identifiers in HAL_OPAMP_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL OSPI</strong> driver</p> |
| <ul> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_OSPI_RegisterCallback() and HAL_OSPI_UnRegisterCallback APIs</li> |
| <li>Add callback identifiers in HAL_OSPI_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL PCD</strong> driver</p> |
| <ul> |
| <li><p>Fix USB double buffer issue in PCD_SET_EP_DBUF1_CNT() macro</p></li> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_PCD_RegisterCallback(),<br /> |
| HAL_PCD_UnRegisterCallback(), HAL_PCD_RegisterDataOutStageCallback(), HAL_PCD_UnRegisterDataOutStageCallback(), HAL_PCD_RegisterDataInStageCallback(), HAL_PCD_UnRegisterDataInStageCallback(), HAL_PCD_RegisterIsoOutIncpltCallback(), HAL_PCD_UnRegisterIsoOutIncpltCallback(), HAL_PCD_RegisterIsoInIncpltCallback(), HAL_PCD_UnRegisterIsoInIncpltCallback(), HAL_PCD_RegisterBcdCallback(), HAL_PCD_UnRegisterBcdCallback(), HAL_PCD_RegisterLpmCallback() and HAL_PCD_UnRegisterLpmCallback APIs</li> |
| <li>Add callback identifiers in HAL_PCD_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL QSPI</strong> driver</p> |
| <ul> |
| <li><p>Fix HAL_QSPI_Receive_IT() to avoid early clear of TE and TC flags</p></li> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_QSPI_RegisterCallback() and HAL_QSPI_UnRegisterCallback APIs</li> |
| <li>Add callback identifiers in HAL_QSPI_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL RCC</strong> driver</p> |
| <ul> |
| <li>Fix HAL_RCCEx_GetPeriphCLKFreq() for all peripheral clock frequency derivated from PLLSAI1 and PLLSAI2 when PLLSAI1M and PLLSAI2M dividers are present</li> |
| </ul></li> |
| <li><p><strong>HAL RNG</strong> driver</p> |
| <ul> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_RNG_RegisterCallback(), HAL_RNG_UnRegisterCallback(), HAL_RNG_RegisterReadyDataCallback() and HAL_RNG_UnRegisterReadyDataCallback APIs</li> |
| <li>Add callback identifiers in HAL_RNG_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL RTC</strong> driver</p> |
| <ul> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_RTC_RegisterCallback() and HAL_RTC_UnRegisterCallback APIs</li> |
| <li>Add callback identifiers in HAL_RTC_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL SAI</strong> driver</p> |
| <ul> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_SAI_RegisterCallback() and HAL_SAI_UnRegisterCallback APIs</li> |
| <li>Add callback identifiers in HAL_SAI_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL SMBUS</strong> driver</p> |
| <ul> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterCallback(), HAL_SMBUS_RegisterAddrCallback() and HAL_SMBUS_UnRegisterAddrCallback APIs</li> |
| <li>Add callback identifiers in HAL_SMBUS_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><strong>HAL SD</strong> driver |
| <ul> |
| <li>Fix DMA write issue</li> |
| <li>Fix to send the "Stop transfer" command only in case of multiple read or write operations<br /> |
| </li> |
| <li><p>Fix typo in FileFormatGroup field of HAL_SD_CardCSDTypedef</p></li> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_SD_RegisterCallback(), HAL_SD_UnRegisterCallback(), HAL_SD_RegisterTransceiverCallback() and HAL_SD_UnRegisterTransceiverCallback APIs</li> |
| <li>Add callback identifiers in HAL_SD_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL SMARTCARD</strong> driver</p> |
| <ul> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_SMARTCARD_RegisterCallback() and HAL_SMARTCARD_UnRegisterCallback APIs</li> |
| <li>Add callback identifiers in HAL_SMARTCARD_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL SPI</strong> driver</p> |
| <ul> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_SPI_RegisterCallback() and HAL_SPI_UnRegisterCallback APIs</li> |
| <li>Add callback identifiers in HAL_SPI_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL SWPMI</strong> driver</p> |
| <ul> |
| <li><p>Fix in HWL_SWPMI_EnableLoopback() to enable entering loopback mode after SWPMI initialization</p></li> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_SWPMI_RegisterCallback() and HAL_SWPMI_UnRegisterCallback APIs</li> |
| <li>Add callback identifiers in HAL_SWPMI_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL TIM</strong> driver</p> |
| <ul> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_TIM_RegisterCallback() and HAL_TIM_UnRegisterCallback APIs</li> |
| <li>Add callback identifiers in HAL_TIM_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL TSC</strong> driver</p> |
| <ul> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_TSC_RegisterCallback() and HAL_TSC_UnRegisterCallback APIs</li> |
| <li>Add callback identifiers in HAL_TSC_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL UART</strong> driver</p> |
| <ul> |
| <li><p>Add wakeup capability from Stop mode when clocked by LSE</p> |
| <ul> |
| <li>Add HAL_UARTEx_EnableClockStopMode() and HAL_UARTEx_DisableClockStopMode APIs</li> |
| </ul></li> |
| <li><p>Remove the following APIs since only applicable to HAL USART and not HAL UART</p></li> |
| <li><p>HAL_UARTEx_EnableSlaveMode(), HAL_UARTEx_DisableSlaveMode() and HAL_UARTEx_ConfigNSS()<br /> |
| </p></li> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_UART_RegisterCallback() and HAL_UART_UnRegisterCallback APIs</li> |
| <li>Add callback identifiers in HAL_UART_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL USART</strong> driver</p> |
| <ul> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_USART_RegisterCallback() and HAL_USART_UnRegisterCallback APIs</li> |
| <li>Add callback identifiers in HAL_USART_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL WWDG</strong> driver</p> |
| <ul> |
| <li><p>Add callback registration feature</p> |
| <ul> |
| <li>Add HAL_WWDG_RegisterCallback() and HAL_WWDG_UnRegisterCallback APIs</li> |
| <li>Add callback identifiers in HAL_WWDG_CallbackIDTypeDef enumerated typedef</li> |
| </ul></li> |
| </ul></li> |
| </ul> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">LL drivers changes</span></span></strong></p> |
| <ul> |
| <li><p><strong>LL ADC</strong> driver</p> |
| <ul> |
| <li>Fix temperature sensor calibration factor value for STM32L4 devices other than STM32L47x/L48x</li> |
| </ul></li> |
| <li><p><strong>LL LPUART</strong> driver</p> |
| <ul> |
| <li><p>Add wakeup capability from Stop mode when clocked by LSE</p> |
| <ul> |
| <li>Add LL_LPUART_EnableClockInStopMode(), LL_LPUART_DisableClockInStopMode() and LL_LPUART_IsClockEnabledInStopMode APIs</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>LL RTC</strong> driver</p> |
| <ul> |
| <li>Code optimization done in LL_RTC_TIME_GetHour(), LL_RTC_TIME_GetMinute(), LL_RTC_TIME_GetSecond(), LL_RTC_DATE_GetYear(), LL_RTC_DATE_GetMonth(), LL_RTC_DATE_GetDay(), LL_RTC_ALMA_GetDay(), LL_RTC_ALMA_GetHour(), LL_RTC_ALMA_GetMinute(), LL_RTC_ALMA_GetSecond(), LL_RTC_ALMB_GetDay(), LL_RTC_ALMB_GetHour(), LL_RTC_ALMB_GetMinute() and LL_RTC_ALMB_GetSecond APIs</li> |
| </ul></li> |
| <li><p><strong>LL SPI</strong> driver</p> |
| <ul> |
| <li>Fix GCC warnings in LL_SPI_TransmitData8() and LL_SPI_TransmitData16()</li> |
| </ul></li> |
| <li><p><strong>LL USART</strong> driver</p> |
| <ul> |
| <li>Rename LL_USART_ICR_NCF flag to LL_USART_ICR_NECF</li> |
| <li>Add wakeup capability from Stop mode when clocked by LSE |
| <ul> |
| <li>Add LL_USART_EnableClockInStopMode(), LL_USART_DisableClockInStopMode() and LL_USART_IsClockEnabledInStopMode APIs</li> |
| </ul></li> |
| </ul></li> |
| </ul> |
| </div> |
| </div> |
| <div class="collapse"> |
| <input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.8.2 / 22-December-2017</label> |
| <div> |
| <h2 id="main-changes-9">Main Changes</h2> |
| <ul> |
| <li>Maintenance Release of <strong>HAL and Low Layer drivers</strong></li> |
| </ul> |
| <h2 id="contents-9">Contents</h2> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p> |
| <ul> |
| <li><strong>HAL CAN</strong> driver</li> |
| </ul> |
| <p>Rework of HAL CAN driver (compatibility break)</p> |
| <p>A new HAL CAN driver has been redesigned with new APIs, to bypass limitations on CAN Tx/Rx FIFO management present with previous HAL CAN driver version.</p> |
| <p>The new HAL CAN driver is the recommended version. It is located as usual in Drivers/STM32L4xx_HAL_Driver/Src and drivers/STM32L4xx_HAL_Driver/Inc folders. It can be enabled through switch HAL_CAN_MODULE_ENABLED in stm32l4xx_hal_conf.h</p> |
| <p>The legacy HAL CAN driver is also present in the release in drivers/STM32L4xx_HAL_Driver/Src/Legacy and drivers/STM32L4xx_HAL_Driver/Inc/Legacy folders for software compatibility reasons. Its usage is not recommended as deprecated. It can however be enabled through switch HAL_CAN_LEGACY_MODULE_ENABLED in stm32l4xx_hal_conf.h</p> |
| <p>Short migration guide:</p> |
| <p>Fields of CAN_InitTypeDef structure are renamed </p> |
| <ul> |
| <li><p>SJW to SyncJumpWidth, BS1 to TimeSeg1, BS2 to TimeSeg2, TTCM to TimeTriggeredMode, ABOM to AutoBusOff, AWUM to AutoWakeUp, NART to AutoRetransmission (inversed), RFLM to ReceiveFifoLocked and TXFP to TransmitFifoPriority</p></li> |
| <li>HAL_CAN_Init() is split into both HAL_CAN_Init() and HAL_CAN_Start()</li> |
| <li>HAL_CAN_Transmit() is replaced by HAL_CAN_AddTxMessage() to place Tx request, then HAL_CAN_GetTxMailboxesFreeLevel() for polling until completion</li> |
| <li>HAL_CAN_Transmit_IT() is replaced by HAL_CAN_ActivateNotification() to enable transmission with interrupt mode, then HAL_CAN_AddTxMessage() to place Tx request</li> |
| <li>HAL_CAN_Receive() is replaced by HAL_CAN_GetRxFifoFillLevel() for polling until reception, then HAL_CAN_GetRxMessage() to get Rx message</li> |
| <li>HAL_CAN_Receive_IT() is replaced by HAL_CAN_ActivateNotification() to enable reception with interrupt mode, then HAL_CAN_GetRxMessage() in the receive callback to get Rx message</li> |
| <li>HAL_CAN_Sleep() is renamed to HAL_CAN_RequestSleep()</li> |
| <li>HAL_CAN_TxCpltCallback() is split into HAL_CAN_TxMailbox0CompleteCallback(), HAL_CAN_TxMailbox1CompleteCallback() and HAL_CAN_TxMailbox2CompleteCallback()</li> |
| <li><p>HAL_CAN_RxCpltCallback() is split into HAL_CAN_RxFifo0MsgPendingCallback() and HAL_CAN_RxFifo1MsgPendingCallback()</p></li> |
| </ul> |
| <p>More complete "how to use the new driver" is detailed in the driver header section itself.</p> |
| <ul> |
| <li><p><strong>HAL CORTEX</strong> driver</p> |
| <ul> |
| <li>HAL_MPU_Enable() and HAL_MPU_Disable() functions moved to stm32l4xx_hal_cortex.c</li> |
| </ul></li> |
| <li><p><strong>HAL CRC</strong> driver</p> |
| <ul> |
| <li>Fix GCC warning </li> |
| </ul></li> |
| <li><p><strong>HAL FLASH</strong> driver</p> |
| <ul> |
| <li>HAL_FLASH_Unlock() updated to not return HAL_ERROR if flash is already unlocked </li> |
| </ul></li> |
| <li><p><strong>HAL OSPI</strong> driver</p> |
| <ul> |
| <li>Cleanup IO Manager ports</li> |
| </ul></li> |
| <li><p><strong>HAL RCC</strong> driver</p> |
| <ul> |
| <li><p>RCC_RTCCLKSOURCE_NO_CLK enamed to RCC_RTCCLKSOURCE_NONE</p></li> |
| <li><p>HAL_RCC_DeInit() updates</p> |
| <ul> |
| <li>Clear of status flags</li> |
| <li>Wait for PLLs disable flags to clear PLLs configuration registers<br /> |
| </li> |
| </ul></li> |
| <li><p>Fix MISRA C-2004 rule 10.6 ('U' suffix)</p></li> |
| </ul></li> |
| <li><p><strong>HAL TIM</strong> driver</p> |
| <ul> |
| <li>Fix MISRA C-2004 rule 10.6 ('U' suffix)</li> |
| </ul></li> |
| </ul> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">LL drivers changes</span></span></strong></p> |
| <ul> |
| <li><p><strong>LL CRC</strong> driver</p> |
| <ul> |
| <li>Fix GCC warning</li> |
| </ul></li> |
| <li><p><strong>LL RCC</strong> driver</p> |
| <ul> |
| <li><p>Add LL_RCC_PLL_SetMainSource() and LL_RCC_HSI_IsEnabledInStopMode() APIs</p></li> |
| <li><p>LL_RCC_DeInit() update</p> |
| <ul> |
| <li>Clear of status flags</li> |
| <li>Wait for PLLs disable flags to clear PLLs configuration registers</li> |
| </ul></li> |
| <li><p>Fix IS_LL_RCC_I2C_CLKSOURCE() assert macro</p></li> |
| </ul></li> |
| </ul> |
| </div> |
| </div> |
| <div class="collapse"> |
| <input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">V1.8.1 / 13-October-2017</label> |
| <div> |
| <h2 id="main-changes-10">Main Changes</h2> |
| <ul> |
| <li>Maintenance Release of <strong>HAL and Low Layer drivers</strong></li> |
| </ul> |
| <h2 id="contents-10">Contents</h2> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p> |
| <ul> |
| <li><p><strong>HAL generic</strong> driver</p> |
| <ul> |
| <li>Fix compilation issue with ARMCC --gnu option on __packed declaration in stm32l4xx_hal_def.h<br /> |
| </li> |
| </ul></li> |
| <li><p><strong>HAL ADC</strong> driver</p> |
| <ul> |
| <li>Reuse LL ADC definitions</li> |
| <li>Fix MISRA C-2004 rule 19.10<br /> |
| </li> |
| </ul></li> |
| <li><p><strong>HAL DSI</strong> driver</p> |
| <ul> |
| <li>Fix timing issue at highest optimization level on IAR on DSI Host, DSI Wrapper, DSI PLL and DSI regulator enable/disable macros </li> |
| <li>Add macro __HAL_DSI_RESET_HANDLE_STATE()</li> |
| </ul></li> |
| <li><p><strong>HAL FLASH</strong> driver</p> |
| <ul> |
| <li>HAL_FLASH_Unlock() shall not return an error when Flash already unlocked</li> |
| </ul></li> |
| <li><p><strong>HAL I2C</strong> driver</p> |
| <ul> |
| <li>Fix race condition in HAL_I2C_Master_Receive() and HAL_I2C_Slave_Receive()</li> |
| </ul></li> |
| <li><p>Fix RD_WRN bit management in case of I2C_NO_STARTSTOP request<br /> |
| </p></li> |
| <li><p><strong>HAL OSPI</strong> driver</p> |
| <ul> |
| <li>Add note on limitation of HAL_OSPI_AutoPolling() and HAL_OSPI_AutoPolling_IT() usage in octal mode (cf. Errata Sheet)</li> |
| <li>Fix compilation warning in C++</li> |
| </ul></li> |
| <li><p><strong>HAL QSPI</strong> driver</p> |
| <ul> |
| <li>Fix MISRA C-2004 rules 10.3, 11.4 and 12.6</li> |
| </ul></li> |
| <li><p><strong>HAL RCC</strong> driver</p> |
| <ul> |
| <li>Update SDMMC1 clock source selection on STM32L4Rx/STM32L4Sx devices to select PLL divider "P" output instead of internal multiplexor on MSI, HSI48, PLLSAI1 or PLL "Q" outputs as SDMMC1 kernel clock source</li> |
| <li>Fix __HAL_RCC_GPIOB_IS_CLK_ENABLED() macro definition</li> |
| </ul></li> |
| <li><p><strong>HAL SDMMC</strong> driver</p> |
| <ul> |
| <li>Fix management of peripheral flags depending on command or data transfers.</li> |
| </ul></li> |
| <li><p><strong>HAL SMBUS</strong> driver</p> |
| <ul> |
| <li>Fix RD_WRN bit management in case of SMBUS_NO_STARTSTOP request</li> |
| </ul></li> |
| </ul> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">LL drivers changes</span></span></strong></p> |
| <ul> |
| <li><p>**LLDAC driver</p> |
| <ul> |
| <li>Add missing definition for external triggers from TIM and LPTIM instances</li> |
| </ul></li> |
| <li><p><strong>LL DMA2D</strong> driver</p> |
| <ul> |
| <li>Fix CodeSonar warning in LL_DMA2D_StructInit()</li> |
| </ul></li> |
| <li><p><strong>LL I2C</strong> driver</p> |
| <ul> |
| <li>Fix RD_WRN bit management in case of LL_I2C_GENERATE_NOSTARTSTOP request in LL_I2C_HandleTransfer()</li> |
| </ul></li> |
| <li><p><strong>LL RCC</strong> driver</p> |
| <ul> |
| <li><p>Update SDMMC1 clock source selection on STM32L4Rx/STM32L4Sx devices to select PLL divider "P" output instead of internal multiplexor on MSI, HSI48, PLLSAI1 or PLL "Q" outputs as SDMMC1 kernel clock source</p></li> |
| <li><p>Add LL_RCC_SetSDMMCKernelClockSource(), LL_RCC_GetSDMMCKernelClockSource() and LL_RCC_GetSDMMCKernelClockFreq() APIs<br /> |
| </p></li> |
| </ul></li> |
| </ul> |
| </div> |
| </div> |
| <div class="collapse"> |
| <input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">V1.8.0 / 25-August-2017</label> |
| <div> |
| <h2 id="main-changes-11">Main Changes</h2> |
| <ul> |
| <li><p>Release of <strong>HAL and Low Layer drivers</strong> to add support of <strong>STM32L4R5xx/STM32L4R7xx/STM32L4R9xx/STM32L4S5xx/STM32L4S7xx/STM32L4S9xx</strong> devices</p></li> |
| <li><p>New OctoSPI, DSI, LTDC, GFXMMU peripherals supported in <strong>new HAL OSPI, HAL DSI, HAL LTDC</strong> and <strong>HAL GFXMMU</strong> drivers</p></li> |
| <li><p>Superset features device STM32L4S9xx API User Manual available (STM32L4S9xx_User_Manual.chm) </p></li> |
| </ul> |
| <p> ## Contents</p> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p> |
| <ul> |
| <li><strong>HAL DSI</strong> driver <strong>(NEW)</strong>: stm32l4xx_hal_dsi.h/.c files</li> |
| <li><strong>HAL GFXMMU</strong> driver <strong>(NEW)</strong>:stm32l4xx_hal_gfxmmu.h/.c files</li> |
| <li><strong>HAL LTDC</strong> driver <strong>(NEW)</strong>:stm32l4xx_hal_ltdc.h/.c and extension stm32l4xx_hal_ltdc_ex.h/.c files</li> |
| <li><p><strong>HAL OSPI</strong> driver <strong>(NEW)</strong>:stm32l4xx_hal_ospi.h/.c files</p></li> |
| <li><p><strong>HAL generic</strong> driver</p> |
| <ul> |
| <li>Add HAL_GetUIDw0(), HAL_GetUIDw1() and HAL_GetUIDw2 APIs</li> |
| <li>Default HAL_Delay() implementation updated to insure minimum requested delay</li> |
| <li>Add __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE() and __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE() macros to set respectively SRAM2 page protection attribute for page 0 to 31 and page 32 to 63</li> |
| </ul></li> |
| <li><p><strong>HAL CAN</strong> driver</p> |
| <ul> |
| <li>Add FIFOs overrun error management (new error codes HAL_CAN_ERROR_FOV0 and HAL_CAN_ERROR_FOV1)</li> |
| </ul></li> |
| <li><p><strong>HAL CRYP</strong> driver</p> |
| <ul> |
| <li>Fix zero padding in case of Data type</li> |
| <li>Fix phase setting related to payload suspension</li> |
| <li>Fix to not be too restrictive on input parameters in HAL_CRYPEx_AES_Auth() and HAL_CRYPEx_AES_Auth_DMA()</li> |
| </ul></li> |
| <li><p><strong>HAL DAC</strong> driver </p> |
| <ul> |
| <li>Fix Sample & Hold configuration in case of multi-channel</li> |
| <li>Rename DAC_HIGH_FREQUENCY_INTERFACE_MODE_ENABLE to DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ</li> |
| </ul></li> |
| <li><p><strong>HAL DMA</strong> driver</p> |
| <ul> |
| <li><p>Fix DMAMUX synchronization signal configuration in HAL_DMAEx_ConfigMuxSync()</p></li> |
| <li><p>Support of DMAMUX1 peripheral via new DMA Extension APIs</p></li> |
| <li>HAL_DMAEx_ConfigMuxRequestGenerator()</li> |
| <li>HAL_DMAEx_EnableMuxRequestGenerator(), HAL_DMAEx_DisableMuxRequestGenerator()</li> |
| <li>HAL_DMAEx_ConfigMuxSync()</li> |
| <li><p>HAL_DMAEx_MUX_IRQHandler()</p></li> |
| </ul></li> |
| <li><p><strong>HAL DFSDM</strong> driver extension (new stm32l4xx_hal_dfsdm_ex.h/.c)</p> |
| <ul> |
| <li>New APIs HAL_DFSDMEx_ChannelSetPulsesSkipping() and HAL_DFSDMEx_ChannelGetPulsesSkipping()</li> |
| </ul></li> |
| <li><p><strong>HAL DFSDM</strong> driver</p> |
| <ul> |
| <li>Fix cast issue to return possible negative value in HAL_DFSDM_FilterGetRegularValue(), HAL_DFSDM_FilterGetInjectedValue(), HAL_DFSDM_FilterGetExdMaxValue() and HAL_DFSDM_FilterGetExdMinValue()</li> |
| </ul></li> |
| <li><p><strong>HAL FLASH</strong> driver </p> |
| <ul> |
| <li>Add new LVE pin management in HAL_FLASHEx_ConfigLVEPin()</li> |
| <li>Fix timeout issue in private FLASH_WaitForLastOperation() API</li> |
| <li>Fix error status of HAL_FLASHEx_OBProgram(</li> |
| </ul></li> |
| <li><p><strong>HAL FMC</strong> driver</p> |
| <ul> |
| <li>New field <em>NBLSetupTime</em> added in FMC_NORSRAM_InitTypeDef structure</li> |
| <li>New field <em>DataHoldTime</em> added in FMC_NORSRAM_TimingTypeDef structure</li> |
| </ul></li> |
| <li><p><strong>HAL HASH</strong> driver</p> |
| <ul> |
| <li>Update of context swap mechanism implemented in HAL_HASH_DMAFeed_ProcessSuspend() when input data are fed to the IP by DMA</li> |
| </ul></li> |
| <li><p><strong>HAL HCD/PCD</strong> driver</p> |
| <ul> |
| <li>Add support of STM32L4R5xx/STM32L4R7xx/STM32L4R9xx/ STM32L4S5xx/STM32L4S7xx/STM32L4S9xx devices</li> |
| </ul></li> |
| <li><p><strong>HAL IRDA</strong> driver</p> |
| <ul> |
| <li><p>Add Clock Prescaler management for STM32L4Rx/STM32L4Sx devices only</p></li> |
| <li><p>IRDA_InitTypeDef structure update to add ClockPrescaler parameter</p></li> |
| </ul></li> |
| <li><p><strong>HAL PCD</strong> driver </p> |
| <ul> |
| <li>Fix USB PCD lock/unlock and flush TX fifo during device reset</li> |
| </ul></li> |
| <li><p><strong>HAL PWR</strong> driver</p> |
| <ul> |
| <li><p>Add PWR_REGULATOR_VOLTAGE_SCALE1_BOOST new parameter value for HAL_PWREx_ControlVoltageScaling() to use higher supply voltage (1.28V) with main regulator voltage in range 1 above 80Mhz (maximum frequency equals to 120Mhz) for STM32L4Rx/STM32L4Sx devices </p></li> |
| <li><p>Add SRAM3 retention management APIs: HAL_PWREx_EnableSRAM3ContentRetention() and HAL_PWREx_DisableSRAM3ContentRetention()</p></li> |
| <li><p>Add DSI pins pull-down management</p></li> |
| <li><p>new HAL_PWREx_EnableDSIPinsPDActivation() and HAL_PWREx_DisableDSIPinsPDActivation APIs</p></li> |
| </ul></li> |
| <li><p><strong>HAL RCC</strong> driver </p> |
| <ul> |
| <li>Add clock management of new peripherals: DSI, GFXMMU, LTDC, OSPI1, OSPI2, OSPIM</li> |
| <li>Add OctoSPI peripherals clock source frequency computation in HAL_RCCEx_GetPeriphCLKFreq()</li> |
| <li>Fix issue with main PLL divider M value to allow 1 to 16 value range on STM32L4Rx/STM32L4Sx devices</li> |
| <li>Fix SDMMC1 clock source selection possibilities in HAL_RCCEx_PeriphCLKConfig(), __HAL_RCC_SDMMC1_CONFIG() and __HAL_RCC_GET_SDMMC1_SOURCE()</li> |
| <li><p>Fix HAL_RCCEx_GetPeriphCLKFreq() to take into account PLLSAI1 and PLLSAI2 divider M values (1 to 16 range) on STM32L4Rx/STM32L4Sx devices</p></li> |
| <li><p>Add undershoot/overshoot management in HAL_RCC_ClockConfig() when switching to/from system clock from main PLL above 80Mhz</p></li> |
| </ul></li> |
| <li><p><strong>HAL RNG</strong> driver </p> |
| <ul> |
| <li><p>Add support of Clock Error detection and Bypass mode management in new RNG_InitTypeDef and HAL_RNG_Init() API</p></li> |
| <li><p>parameters ClockErrorDetection and BypassMode added in new RNG_InitTypeDef</p></li> |
| </ul></li> |
| <li><p><strong>HAL RTC</strong> driver</p> |
| <ul> |
| <li>Fix HAL_RTC_Init() to wait for synchronization and avoid RTC registers access timing issues</li> |
| </ul></li> |
| <li><p><strong>HAL SAI</strong> driver</p> |
| <ul> |
| <li><p>Add FIFO flush in HAL_SAI_DMAStop()</p></li> |
| <li><p>Fix HAL_SAI_Transmit_DMA() to follow the slave TX mode sequence described in the Reference Manual</p></li> |
| </ul></li> |
| <li><p><strong>HAL SD</strong> driver</p> |
| <ul> |
| <li><p>Major rework of HAL SD driver aligned with STM32F7 series</p></li> |
| <li><p>BlockSize parameter removed in Read&Write block APIs since 512 byte size is always read&write.</p></li> |
| </ul></li> |
| <li><p><strong>HAL SMARTCARD</strong> driver</p> |
| <ul> |
| <li><p>Add Clock Prescaler management for STM32L4Rx/STM32L4Sx devices only</p></li> |
| <li><p>SMARTCARD_InitTypeDef structure update to add ClockPrescaler parameter</p></li> |
| <li><p>Add FIFO mode management for STM32L4Rx/STM32L4Sx devices only</p></li> |
| <li><p>new HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_SetTxFifoThreshold(), HAL_SMARTCARDEx_SetRxFifoThreshold(), HAL_SMARTCARDEx_RxFifoFullCallback() and HAL_SMARTCARDEx_TxFifoEmptyCallback APIs</p></li> |
| </ul></li> |
| <li><p><strong>HAL SMBUS</strong> driver</p> |
| <ul> |
| <li>Add Analog and digital filter configuration APIs: HAL_SMBUS_ConfigAnalogFilter() and HAL_SMBUS_ConfigDigitalFilter() </li> |
| <li>Add error management if occurring during STOP process</li> |
| </ul></li> |
| <li><p><strong>HAL SPI</strong> driver</p> |
| <ul> |
| <li>Add control of RXFIFO empty at end of transmissing in Master transmission 2 lines mode</li> |
| </ul></li> |
| <li><p><strong>HAL SWPMI</strong> driver</p> |
| <ul> |
| <li>Fix missing clock initialization before register update in HAL_SWPMI_Init()</li> |
| </ul></li> |
| <li><p><strong>HAL TIM</strong> driver</p> |
| <ul> |
| <li>Add TIM_TIM1_ETR_GPIO and TIM_TIM8_ETR_GPIO definitions</li> |
| <li>Add TIM_TIM16_TI1_MSI, TIM_TIM16_TI1_HSE_32 and TIM_TIM16_TI1_MCO definitions for STM32L4Rx/STM32L4Sx</li> |
| <li>Add new AutoReloadPreload parameter in TIM_Base_InitTypeDef (user code impacted)</li> |
| <li>Fix wrong MOE disable conditions with new macro __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY()</li> |
| </ul></li> |
| <li><p><strong>HAL UART</strong> driver</p> |
| <ul> |
| <li>Add Clock Prescaler management for STM32L4Rx/STM32L4Sx devices only</li> |
| <li>UART_InitTypeDef structure update to add ClockPrescaler parameter<br /> |
| </li> |
| <li><p>Add FIFO mode management for STM32L4Rx/STM32L4Sx devices only</p></li> |
| <li><p>new HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_SetTxFifoThreshold(), HAL_UARTEx_SetRxFifoThreshold(), HAL_UARTEx_RxFifoFullCallback() and HAL_UARTEx_TxFifoEmptyCallback APIs</p></li> |
| <li><p>Add SPI Slave mode management for STM32L4Rx/STM32L4Sx devices only</p></li> |
| <li><p>new HAL_UARTEx_EnableSlaveMode(), HAL_UARTEx_DisableSlaveMode() and HAL_UARTEx_ConfigNSS()</p></li> |
| </ul></li> |
| <li><p><strong>HAL USART</strong> driver (new stm32l4xx_hal_usart_ex.c)</p> |
| <ul> |
| <li><p>Add Clock Prescaler management for STM32L4Rx/STM32L4Sx devices only</p></li> |
| <li>USART_InitTypeDef structure update to add ClockPrescaler parameter<br /> |
| </li> |
| <li><p>Add FIFO mode management for STM32L4Rx/STM32L4Sx devices only</p></li> |
| <li><p>new HAL_USARTEx_EnableFifoMode(), HAL_USARTEx_DisableFifoMode(), HAL_USARTEx_SetTxFifoThreshold(), HAL_USARTEx_SetRxFifoThreshold(), HAL_USARTEx_RxFifoFullCallback() and HAL_USARTEx_TxFifoEmptyCallback APIs</p></li> |
| <li><p>Add SPI Slave mode management for STM32L4Rx/STM32L4Sx devices only</p></li> |
| <li><p>new HAL_USARTEx_EnableSlaveMode(), HAL_USARTEx_DisableSlaveMode() and HAL_USARTEx_ConfigNSS()</p></li> |
| </ul></li> |
| </ul> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">LL drivers changes</span></span></strong></p> |
| <p><strong>LL DMAMUX</strong> driver <strong>(NEW)</strong>: stm32l4xx_ll_dmamux.h</p> |
| <p><strong>All LL</strong> drivers update to remove usage of CMSIS POSITION_VAL() macro and resort to xx_Pos position bit definition</p> |
| <ul> |
| <li><p><strong>LL ADC</strong></p> |
| <ul> |
| <li>Fix legacy APIs LL_ADC_REG_SetTrigSource() and LL_ADC_INJ_SetTrigSource()</li> |
| </ul></li> |
| <li><p><strong>LL BUS</strong> </p> |
| <ul> |
| <li>Add management of new peripherals: DSI, GFXMMU, LTDC, OSPI1, OSPI2, OSPIM</li> |
| </ul></li> |
| <li><p><strong>LL DMA</strong></p> |
| <ul> |
| <li>Fix simple write register access to clear DMA flags in LL_DMA_ClearFlag_XXX APIs</li> |
| </ul></li> |
| <li><p><strong>LL DMA2D</strong></p> |
| <ul> |
| <li>Add management of output swapping mode (regular or bytes two by two) and line offset mode (pixel or byte)</li> |
| </ul></li> |
| <li><p><strong>LL EXTI</strong> </p> |
| <ul> |
| <li>Add management of EXTI line 40 (I2C4)</li> |
| </ul></li> |
| <li><p><strong>LL I2C</strong></p> |
| <ul> |
| <li>Fix LL_I2C_Init() to not set OAEN1 bit when Own Address 1 value is 0</li> |
| </ul></li> |
| <li><p><strong>LL LPUART / LL USART</strong></p> |
| <ul> |
| <li>Add management of Rx FIFO and Tx FIFO</li> |
| </ul></li> |
| <li><p><strong>LL PWR</strong></p> |
| <ul> |
| <li><p>Add SRAM3 retention management APIs </p></li> |
| <li><p>LL_PWR_EnableSRAM3Retention(), LL_PWR_DisableSRAM3Retention() and LL_PWR_IsEnabledSRAM3Retention()</p></li> |
| <li><p>Add voltage range 1 boost mode APIs</p></li> |
| <li><p>LL_PWR_EnableRange1BoostMode(), LL_PWR_DisableRange1BoostMode() and LL_PWR_IsEnabledRange1BoostMode()</p></li> |
| <li><p>For compatibility purpose across STM32 series, rename LL_PWR_IsActiveFlag_VOSF() to LL_PWR_IsActiveFlag_VOS()</p></li> |
| <li><p>Add DSI pins pull-down management</p></li> |
| <li><p>new LL_PWR_EnableDSIPinsPDActivation(), LL_PWR_DisableDSIPinsPDActivation() and LL_PWR_IsEnabledDSIPinsPDActivation APIs</p></li> |
| </ul></li> |
| <li><p><strong>LL RCC</strong></p> |
| <ul> |
| <li><p>Add management of new peripheral clock sources for DSI, LTDC, OSPI1, OSPI2 and SDMMC</p></li> |
| <li><p>Add new definitions for main PLL divider M values above LL_RCC_PLLM_DIV_8 and up to LL_RCC_PLLM_DIV_16 for STM32L4Rx/STM32L4Sx devices</p></li> |
| <li><p>Fix in __LL_RCC_CALC_PLLCLK_SAI_FREQ(), __LL_RCC_CALC_PLLSAI1_SAI_FREQ(), __LL_RCC_CALC_PLLSAI1_48M_FREQ(), __LL_RCC_CALC_PLLSAI1_ADC_FREQ(), __LL_RCC_CALC_PLLSAI2_SAI_FREQ()</p></li> |
| <li><p>Fix in LL_RCC_PLLSAI1_ConfigDomain_48M(), LL_RCC_PLLSAI1_ConfigDomain_SAI(), LL_RCC_PLLSAI1_ConfigDomain_ADC(), LL_RCC_PLLSAI1_GetP(), LL_RCC_PLLSAI2_ConfigDomain_SAI() and LL_RCC_PLLSAI2_GetP()</p></li> |
| <li><p>Fix LL_RCC_GetSDMMCClockFreq() to take into account all SDMMC1 possible clock sources</p></li> |
| <li><p>Add HSI48 oscillator clock source value for RNG and USB: </p> |
| <ul> |
| <li>LL_RCC_RNG_CLKSOURCE_HSI48 and update LL_RCC_GetRNGClockFreq()</li> |
| <li>LL_RCC_USB_CLKSOURCE_HSI48 and update LL_RCC_GetUSBClockFreq()</li> |
| </ul></li> |
| <li><p>General fixes<br /> |
| </p> |
| <ul> |
| <li>Renaming of RCC_DFSDM1CLKSOURCE_PCLK to RCC_DFSDM1CLKSOURCE_PCLK2</li> |
| <li>Renaming of RCC_SWPMI1CLKSOURCE_PCLK to RCC_SWPMI1CLKSOURCE_PCLK1</li> |
| <li>Renaming of RCC_LPTIMxCLKSOURCE_PCLK to RCC_LPTIMxCLKSOURCE_PCLK1</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>LL RNG</strong></p> |
| <ul> |
| <li><p>Add Clock Error detection and Bypass mode management in new LL_RNG_InitTypeDef and new LL_RNG_Init() API</p> |
| <ul> |
| <li>new LL_RNG_EnableClkErrorDetect(), LL_RNG_DisableClkErrorDetect() and LL_RNG_IsEnableClkErrorDetect()</li> |
| <li>new LL_RNG_EnableBypassMode(), LL_RNG_DisableBypassMode() and LL_RNG_IsEnabledBypassMode<br /> |
| </li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>LL RTC</strong></p> |
| <ul> |
| <li>LL_RTC_TIME_Get() and LL_RTC_DATE_Get() implementations optimization (single register read access)</li> |
| </ul></li> |
| <li><p><strong>LL SYSTEM</strong></p> |
| <ul> |
| <li>Add SRAM2 page write protection APIs: LL_SYSCFG_EnableSRAM2PageWRP_0_31() and LL_SYSCFG_EnableSRAM2PageWRP_32_63()</li> |
| </ul></li> |
| <li><p><strong>LL TIM</strong></p> |
| <ul> |
| <li>Fix definition of TIM break input polarity (inverse values LL_TIM_BKIN_POLARITY_LOW / LL_TIM_BKIN_POLARITY_HIGH)</li> |
| <li>Fix LL_TIM_EnableUpdateEvent(), LL_TIM_DisableUpdateEvent() and LL_TIM_IsEnabledUpdateEvent()</li> |
| </ul></li> |
| <li><p><strong>LL UTILS</strong></p> |
| <ul> |
| <li>Add management of new flash latency ranges in UTILS_SetFlashLatency()</li> |
| <li>Add undershoot management when switching to system clock from main PLL above 80Mhz in LL_PLL_ConfigSystemClock_MSI(), LL_PLL_ConfigSystemClock_HSI() and LL_PLL_ConfigSystemClock_HSE()</li> |
| </ul></li> |
| </ul> |
| </div> |
| </div> |
| <div class="collapse"> |
| <input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">V1.7.2 / 16-June-2017</label> |
| <div> |
| <h2 id="main-changes-12">Main Changes</h2> |
| <ul> |
| <li>Maintenance Release of <strong>HAL and Low Layer drivers</strong></li> |
| </ul> |
| <h2 id="contents-11">Contents</h2> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p> |
| <ul> |
| <li><p><strong>HAL CAN</strong> driver</p> |
| <ul> |
| <li>Add overrun error management by the error callback</li> |
| </ul></li> |
| <li><p><strong>HAL CRC</strong> driver</p> |
| <ul> |
| <li>Update of HAL_CRCEx_Polynomial_Set() to return an error when a non-supported polynomial length is passed as parameter</li> |
| </ul></li> |
| <li><strong>HAL CRYP</strong> driver |
| <ul> |
| <li>Update zero padding management with respect to data type</li> |
| <li>Phase setting and comments correction in case of payload phase suspension</li> |
| <li>Correct input parameters tests in HAL_CRYPEx_AES_Auth() and HAL_CRYPEx_AES_Auth_DMA APIs</li> |
| <li>Correct interruptions and IP enabling flags setting for key derivation in IT mode</li> |
| </ul></li> |
| <li><p><strong>HAL DCMI</strong> driver</p> |
| <ul> |
| <li>Comments correction to describe image size management when larger than maximum authorized DMA transfer size</li> |
| </ul></li> |
| <li><p><strong>HAL FLASH</strong> driver</p> |
| <ul> |
| <li>Add software work - around in HAL_FLASH_Unlock() to clear OPTVERR flag on STM32L45x/L46x parts when initially improperly raised</li> |
| <li>Correct timeout issue in FLASH_WaitForLastOperation()</li> |
| </ul></li> |
| <li><p><strong>HAL HASH</strong> driver</p> |
| <ul> |
| <li>Update of context swap mechanism implemented in HAL_HASH_DMAFeed_ProcessSuspend() when input data are fed to the IP by DMA</li> |
| </ul></li> |
| </ul> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">LL drivers changes</span></span></strong></p> |
| <ul> |
| <li><p><strong>LL RCC</strong></p> |
| <ul> |
| <li>Correct duplication of aRCC_APBAHBPrescTable</li> |
| </ul></li> |
| <li><p><strong>LL RTC</strong></p> |
| <ul> |
| <li>Simplication of implementation of function LL_RTC_DATE_Get()</li> |
| </ul></li> |
| <li><p><strong>LL TIM</strong></p> |
| <ul> |
| <li>Fix LL_TIM_EnableUpdateEvent(), LL_TIM_DisableUpdateEvent() and LL_TIM_IsEnabledUpdateEvent()</li> |
| </ul></li> |
| </ul> |
| </div> |
| </div> |
| <div class="collapse"> |
| <input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true">V1.7.1 / 21-April-2017</label> |
| <div> |
| <h2 id="main-changes-13">Main Changes</h2> |
| <ul> |
| <li>Maintenance Release of <strong>HAL and Low Layer drivers</strong></li> |
| </ul> |
| <h2 id="contents-12">Contents</h2> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p> |
| <ul> |
| <li><p><strong>HAL generic</strong> driver</p> |
| <ul> |
| <li>Add HAL_GetUIDw0(), HAL_GetUIDw1() and HAL_GetUIDw2 APIs</li> |
| </ul></li> |
| <li><p><strong>HAL DAC</strong> driver</p> |
| <ul> |
| <li>Fix Sample & Hold configuration in case of multi-channel</li> |
| </ul></li> |
| <li><p><strong>HAL HASH</strong> driver</p> |
| <ul> |
| <li>Fix to ensure proper DMA-based HASH processing suspension/resumption</li> |
| </ul></li> |
| <li><p><strong>HAL PCD</strong> driver</p> |
| <ul> |
| <li>Fix USB PCD lock/unlock and flush TX fifo during device reset</li> |
| </ul></li> |
| <li><p><strong>HAL RTC</strong> driver</p> |
| <ul> |
| <li>Add wait for synchronization in HAL_RTC_Init() to insure RTC time initialization </li> |
| </ul></li> |
| </ul> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">LL drivers changes</span></span></strong></p> |
| <ul> |
| <li><p><strong>LL ADC</strong></p> |
| <ul> |
| <li>Fix legacy APIs LL_ADC_REG_SetTrigSource() and LL_ADC_INJ_SetTrigSource()</li> |
| </ul></li> |
| <li><p><strong>LL DMA</strong> </p> |
| <ul> |
| <li>Write only operation on IFCR register</li> |
| </ul></li> |
| </ul> |
| </div> |
| </div> |
| <div class="collapse"> |
| <input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true">V1.7.0 / 17-February-2017</label> |
| <div> |
| <h2 id="main-changes-14">Main Changes</h2> |
| <ul> |
| <li>Release of <strong>HAL and Low Layer drivers</strong> to add support of <strong>STM32L496xx/STM32L4A6xx</strong> devices</li> |
| <li>New DCMI, DMA2D, HASH peripherals supported in <strong>new HAL DCMI, HAL & LL DMA2D and HAL HASH</strong> drivers</li> |
| <li>New CAN2 instance supported in HAL CAN <br /> |
| </li> |
| <li>Superset features device STM32L4A6xx API User Manual available (STM32L4A6xx_User_Manual.chm) <br /> |
| </li> |
| </ul> |
| <h2 id="contents-13">Contents</h2> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p> |
| <ul> |
| <li><strong>HAL DCMI</strong> driver <strong>(NEW)</strong>: stm32l4xx_hal_dcmi.h/.c files</li> |
| <li><strong>HAL DMA2D</strong> driver <strong>(NEW)</strong>: stm32l4xx_hal_dma2d.h/.c files</li> |
| <li><strong>HAL HASH</strong> driver <strong>(NEW)</strong>: stm32l4xx_hal_hash.h/.c and extension stm32l4xx_hal_hash_ex.h/.c files</li> |
| </ul> |
| <p><strong>The following changes done on the HAL drivers require an update on the application code based on older HAL versions</strong></p> |
| <ul> |
| <li><strong>HAL SD</strong> update</li> |
| </ul> |
| <p>Overall rework of the driver for a more efficient implementation</p> |
| <ul> |
| <li>Modify initialization API and structures</li> |
| <li>Modify Read / Write sequences: separate transfer process and SD Cards state management </li> |
| <li>Adding interrupt mode for Read / Write operations]</li> |
| <li>Update the HAL_SD_IRQHandler function by optimizing the management of interrupt errors</li> |
| </ul> |
| <p>Refer to the following examples in STM32CubeL4 firmware package V1.7.0 to identify the changes: BSP example and USB_Device/MSC_Standalone application</p> |
| <ul> |
| <li><p><strong>HAL generic</strong> update</p> |
| <ul> |
| <li><p>stm32l4xx_hal_conf_template.h updated for new HAL DCMI, HAL DMA2D and HAL HASH</p></li> |
| <li>#define HAL_DCMI_MODULE_ENABLED</li> |
| <li>#define HAL_DMA2D_MODULE_ENABLED</li> |
| <li><p>#define HAL_HASH_MODULE_ENABLED</p></li> |
| <li><p>HAL_Delay() updated to guarantee minimum delay</p></li> |
| </ul></li> |
| <li><p><strong>HAL CAN</strong> driver</p> |
| <ul> |
| <li>Add support of CAN2 instance</li> |
| </ul></li> |
| <li><p><strong>HAL GPIO</strong> driver</p> |
| <ul> |
| <li>Add support of GPIOI port and STM32L496xx/STM32L4A6xx alternate functions</li> |
| </ul></li> |
| <li><p><strong>HAL PWR</strong> driver</p> |
| <ul> |
| <li>Add support of GPIOI port pull-up/pull-down state in Standby and Shutdown modes</li> |
| </ul></li> |
| <li><p><strong>HAL QSPI</strong> driver</p> |
| <ul> |
| <li>Fix QSPI_HandleTypeDef structure to handle data size as uint32_t</li> |
| </ul></li> |
| <li><p><strong>HAL RCC</strong> driver</p> |
| <ul> |
| <li><p>Add new macros for new peripherals clock and reset for CAN2, DCMI, DMA2D, GPIOI and HASH</p></li> |
| <li><p>Fix HAL_RCCEx_GetPeriphCLKFreq() to compute peripheral frequencies from MSI frequency</p></li> |
| <li><p>Fix HAL_RCCEx_GetPeriphCLKFreq() to compute DFSDM1 frequency from PCLK2 frequency</p></li> |
| <li><p>Rename some peripheral clock sources to specify the corresponding APB clock:</p></li> |
| <li><p>RCC_DFSDM1CLKSOURCE_PCLK to RCC_DFSDM1CLKSOURCE_PCLK2</p></li> |
| <li><p>RCC_SWPMI1CLKSOURCE_PCLK to RCC_SWPMI1CLKSOURCE_PCLK1</p></li> |
| <li><p>RCC_LPTIMxCLKSOURCE_PCLK to RCC_LPTIMxCLKSOURCE_PCLK1</p></li> |
| </ul></li> |
| <li><p><strong>HAL RTC</strong> driver</p> |
| <ul> |
| <li>Fix wrong clear of time and date registers in HAL_RTCEx_TamperTimeStampIRQHandler()</li> |
| </ul></li> |
| <li><p><strong>HAL SPI</strong> driver</p> |
| <ul> |
| <li>Add internal timeout to exit HAL_SPI_Abort() and HAL_SPI_Abort_IT() </li> |
| </ul></li> |
| <li><p><strong>HAL TIM</strong> driver</p> |
| <ul> |
| <li>Fix wrong MOE disable conditions with new macro __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY()</li> |
| </ul></li> |
| <li><p><strong>HAL SWPMI</strong> driver</p> |
| <ul> |
| <li>Fix peripheral clock management sequence in HAL_SWPMI_Init()</li> |
| </ul></li> |
| </ul> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">LL drivers changes</span></span></strong></p> |
| <ul> |
| <li><p><strong>LL DMA2D</strong> driver <strong>(NEW)</strong></p></li> |
| <li><p><strong>LL BUS</strong></p> |
| <ul> |
| <li>Add management of new peripherals: CAN2, DCMI, DMA2D, GPIOI and HASH</li> |
| </ul></li> |
| <li><p><strong>LL PWR</strong></p> |
| <ul> |
| <li>For compatibility purpose across STM32 series, rename LL_PWR_IsActiveFlag_VOSF() to LL_PWR_IsActiveFlag_VOS()</li> |
| </ul></li> |
| <li><p><strong>LL RCC</strong></p> |
| <ul> |
| <li>Fix LL_RCC_GetDFSDMClockFreq() to compute frequency from PCLK2 frequency</li> |
| </ul></li> |
| <li><p><strong>LL SDMMC</strong></p> |
| <ul> |
| <li>Add new internal functions after HAL SD rework</li> |
| </ul></li> |
| <li><p><strong>LL TIM</strong></p> |
| <ul> |
| <li>Fix definition of TIM break input polarity (fix values LL_TIM_BKIN_POLARITY_LOW / LL_TIM_BKIN_POLARITY_HIGH)</li> |
| </ul></li> |
| </ul> |
| </div> |
| </div> |
| <div class="collapse"> |
| <input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true">V1.6.0 / 28-October-2016</label> |
| <div> |
| <h2 id="main-changes-15">Main Changes</h2> |
| <ul> |
| <li>Release of <strong>HAL and Low Layer drivers</strong> to add support of <strong>STM32L451xx/STM32L452xx/STM32L462xx</strong> devices</li> |
| <li>Superset features device STM32L462xx API User Manual available (STM32L462xx_User_Manual.chm)</li> |
| </ul> |
| <h2 id="contents-14">Contents</h2> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p> |
| <ul> |
| <li><p><strong>HAL CRYP</strong> driver</p> |
| <ul> |
| <li><p>HAL CRYP exported macros alignment with other STM32 series to use CRYP handle address as parameter in:</p></li> |
| <li><p>__HAL_CRYP_ENABLE(), __HAL_CRYP_DISABLE(), __HAL_CRYP_SET_OPERATINGMODE(), __HAL_CRYP_SET_CHAININGMODE(), __HAL_CRYP_GET_FLAG(), __HAL_CRYP_CLEAR_FLAG(), __HAL_CRYP_GET_IT_SOURCE(), __HAL_CRYP_GET_IT(), __HAL_CRYP_CLEAR_IT(), __HAL_CRYP_ENABLE_IT() and __HAL_CRYP_DISABLE_IT()</p></li> |
| </ul></li> |
| <li><p><strong>HAL FLASH</strong> driver</p> |
| <ul> |
| <li><p>Temporary data cache deactivation on </p> |
| <ul> |
| <li>Flash programming in HAL_FLASH_Program() and HAL_FLASH_Program_IT()</li> |
| <li>Flash erase in HAL_FLASHEx_Erase() and HAL_FLASHEx_Erase_IT()</li> |
| </ul></li> |
| <li><p>To insure LSB/MSB address order in C compiler assembly output, split 64-bit programming in 2 double-word write operations</p></li> |
| </ul></li> |
| <li><p><strong>HAL I2C</strong> driver</p> |
| <ul> |
| <li>Fix to reset HAL I2C handle LISTEN state option in transfer direction change with HAL_I2C_Slave_Sequential_Transmit_IT() and HAL_I2C_Slave_Sequential_Receive_IT()</li> |
| </ul></li> |
| <li><p><strong>HAL SMBUS</strong> driver</p> |
| <ul> |
| <li>Add support of Zone read/write feature thanks to new XferOptions parameter values SMBUS_OTHER_FRAME_NO_PEC, SMBUS_OTHER_FRAME_WITH_PEC, SMBUS_OTHER_AND_LAST_FRAME_NO_PEC and SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC that may be used in HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT() and HAL_SMBUS_Slave_Receive_IT()</li> |
| </ul></li> |
| <li><p><strong>HAL RTC</strong> driver</p> |
| <ul> |
| <li>Fix race conditions on EXTI flags clearing in HAL_RTC_AlarmIRQHandler(), HAL_RTCEx_TamperTimeStampIRQHandler() and HAL_RTCEx_WakeUpTimerIRQHandler()</li> |
| </ul></li> |
| <li><p>Fix CodeSonar warnings in </p> |
| <ul> |
| <li>HAL ADC, HAL CRC, HAL CRYP, HAL I2C, HAL IRDA, HAL SMARTCARD, HAL SMBUS, HAL OPAMP, HAL RTC, HAL UART, HAL USART</li> |
| </ul></li> |
| </ul> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">LL drivers changes</span></span></strong></p> |
| <ul> |
| <li><p><strong>LL I2C</strong> driver</p> |
| <ul> |
| <li>Add I2C4 management in LL_I2C_DeInit()</li> |
| </ul></li> |
| <li><p><strong>LL SYSTEM</strong> driver</p> |
| <ul> |
| <li>Application shall be responsible to write the correct key sequence in SYSCFG_SKR register prior to call LL_SYSCFG_EnableSRAM2Erase()</li> |
| </ul></li> |
| <li><p><strong>LL TIM</strong> driver</p> |
| <ul> |
| <li><p>New APIs to insure BDTR register initialization in a single write operation </p></li> |
| <li>LL_TIM_BDTR_StructInit()</li> |
| <li><p>LL_TIM_BDTR_Init()</p></li> |
| </ul></li> |
| <li><p><strong>LL UTILS</strong> driver</p> |
| <ul> |
| <li>Fix LL_RCC_PLLSOURCE_HSE in LL_PLL_ConfigSystemClock_HSE() </li> |
| </ul></li> |
| </ul> |
| </div> |
| </div> |
| <div class="collapse"> |
| <input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true">V1.5.2 / 12-September-2016</label> |
| <div> |
| <h2 id="contents-15">Contents</h2> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p> |
| <ul> |
| <li><p><strong>HAL ADC</strong> driver</p> |
| <ul> |
| <li>No need to configure number of discontinuous conversions if discontinuous mode is not enabled</li> |
| <li>HAL_ADCEx_MultiModeConfigChannel() returns HAL_ERROR if no Slave instance defined<br /> |
| </li> |
| </ul></li> |
| <li><p><strong>HAL DAC</strong> driver</p> |
| <ul> |
| <li>Fix calibration with correct handling of DAC_SR_CAL_FLAGx bits in HAL_DACEx_SelfCalibrate()</li> |
| </ul></li> |
| <li><p><strong>HAL FLASH</strong> driver</p> |
| <ul> |
| <li>Change in HAL_FLASHEx_OBGetConfig() to not return PCROP and/or WRP data if their respective areas are not defined</li> |
| <li>Fix error management in HAL_FLASH_IRQHandler() to simply call HAL_FLASH_OperationErrorCallback() instead of calling both HAL_FLASH_EndOfOperationCallback() and HAL_FLASH_OperationErrorCallback()</li> |
| </ul></li> |
| <li><p><strong>HAL I2C</strong> driver</p> |
| <ul> |
| <li>Fix wrong state check in HAL_I2C_Master_Sequential_Transmit_IT()</li> |
| <li>Add new option I2C_FIRST_AND_NEXT_FRAME to manage a sequencewith start condition, address and data to transfer without a final stop condition allowing successive calls to HAL_I2C_Master_Sequential_Transmit_IT()</li> |
| </ul></li> |
| <li><p><strong>HAL IRDA</strong> driver</p> |
| <ul> |
| <li><p>Add transfer abort functions and associated callbacks in interrupt mode</p> |
| <ul> |
| <li>HAL_IRDA_Abort(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortReceive()</li> |
| <li>HAL_IRDA_Abort_IT(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_AbortReceive_IT()</li> |
| <li>HAL_IRDA_AbortCpltCallback(), HAL_IRDA_AbortTransmitCpltCallback(), HAL_IRDA_AbortReceiveCpltCallback()</li> |
| <li>IRQ Handler + DMA model optimizations</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL RTC</strong> driver</p> |
| <ul> |
| <li>Fix missing wakeup flag clear in HAL_RTCEx_SetWakeUpTimer_IT()</li> |
| </ul></li> |
| <li><p><strong>HAL SMARTCARD</strong> driver</p> |
| <ul> |
| <li><p>Add transfer abort functions and associated callbacks in interrupt mode</p> |
| <ul> |
| <li>HAL_SMARTCARD_Abort(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortReceive()</li> |
| <li>HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_AbortReceive_IT()</li> |
| <li>HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_AbortTransmitCpltCallback(), HAL_SMARTCARD_AbortReceiveCpltCallback()</li> |
| </ul></li> |
| <li><p>IRQ Handler + DMA model optimizations</p></li> |
| </ul></li> |
| <li><p><strong>HAL SMBUS</strong> driver</p> |
| <ul> |
| <li>Fix issue on last data reception in host or device modes</li> |
| </ul></li> |
| <li><p><strong>HAL SPI</strong> driver</p> |
| <ul> |
| <li><p>USE_SPI_CRCcompilation define added to provide the mean to optimize the HAL SPI driver when CRC feature is not used (when CRC is used, application must be changed to set USE_SPI_CRC in stm32l4xx_hal_conf.h (see Inc\stm32l4xx_hal_conf_template.h))</p></li> |
| <li>Add transfer abort functions and associated callbacks in interrupt mode |
| <ul> |
| <li>HAL_SPI_Abort()</li> |
| <li>HAL_SPI_Abort_IT()</li> |
| <li>HAL_SPI_AbortCpltCallback()</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL SWPMI</strong> driver</p> |
| <ul> |
| <li>Fix SWPMI peripheral errors management in DMA (resort to HAL_DMA_Abort_IT() and DMA XferAbortCallback in HAL_SWPMI_IRQHandler())</li> |
| </ul></li> |
| <li><p><strong>HAL UART</strong> driver</p> |
| <ul> |
| <li>New APIs to abort UART transfer with associated callbacks added |
| <ul> |
| <li>HAL_UART_Abort(), HAL_UART_AbortTransmit(), HAL_UART_AbortReceive(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit_IT(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortCpltCallback(), HAL_UART_AbortTransmitCpltCallback() and HAL_UART_AbortReceiveCpltCallback()</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL USART</strong> driver</p> |
| <ul> |
| <li><p>New APIs to abort USART transfer with associated callbacks added</p> |
| <ul> |
| <li>HAL_USART_Abort(), HAL_USART_Abort_IT() and HAL_USART_AbortCpltCallback()</li> |
| </ul></li> |
| </ul></li> |
| </ul> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">LL drivers changes</span></span></strong></p> |
| <ul> |
| <li><p><strong>LL COMP</strong> driver</p> |
| <ul> |
| <li>Fis LL_COMP_INPUT_PLUS_IO3 definition</li> |
| </ul></li> |
| </ul> |
| </div> |
| </div> |
| <div class="collapse"> |
| <input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true">V1.5.1 / 31-May-2016</label> |
| <div> |
| <h2 id="contents-16">Contents</h2> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p> |
| <ul> |
| <li><p><strong>HAL ADC</strong> driver</p> |
| <ul> |
| <li>Bypass multimode assert_param macro calls depending on configuration</li> |
| </ul></li> |
| <li><p><strong>HAL CRC</strong> driver</p> |
| <ul> |
| <li>HAL_CRC_DeInit() resets CRC_IDR register to reset value</li> |
| </ul></li> |
| </ul> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">LL drivers changes</span></span></strong></p> |
| <ul> |
| <li><strong>LL BUS</strong> driver |
| <ul> |
| <li>LL_APB1_GRP1_PERIPH_USBFS renamed to LL_APB1_GRP1_PERIPH_USB</li> |
| </ul></li> |
| <li><strong>LL SYSTEM</strong>driver |
| <ul> |
| <li>Fix typo on LL_DBGMCU_APB1_xxx and LL_DBGMCU_APB2_xxx</li> |
| </ul></li> |
| </ul> |
| </div> |
| </div> |
| <div class="collapse"> |
| <input type="checkbox" id="collapse-section13" aria-hidden="true"> <label for="collapse-section13" aria-hidden="true">V1.5.0 / 29-April-2016</label> |
| <div> |
| <h2 id="main-changes-16">Main Changes</h2> |
| <ul> |
| <li>Maintenance Release of <strong>HAL and Low Layer drivers</strong></li> |
| </ul> |
| <h2 id="contents-17">Contents</h2> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p> |
| <p>Enhance HAL delay and timebase implementation</p> |
| <ul> |
| <li>Add new driver stm32l4xx_hal_timebase_tim_template.c which overrides the native HAL time base functions (defined as weak) to use the TIM peripheral as time base tick source. For more details about the usage of this driver, please refer to HAL\HAL_TimeBase example and FreeRTOS-based applications</li> |
| </ul> |
| <p>The following changes done on the HAL drivers require an update on the application code based on HAL V1.4.0.</p> |
| <ul> |
| <li><p><strong>HAL RCC</strong> driver</p> |
| <ul> |
| <li><p>To use PLLSAI1 and PLLSAI2 indidependently from main system PLL, PLLSAI1 & PLLSAI2 initialization enriched to add PLL entry clock source and divider M</p></li> |
| <li><p>RCC_PLLSAI1InitTypeDef includes PLLSAI1Source and PLLSAI1M new fields</p></li> |
| <li><p>RCC_PLLSAI2InitTypeDef includes PLLSAI2Source and PLLSAI2M new fields</p></li> |
| <li><p>Add missing RTC clock source definition RCC_RTCCLKSOURCE_NO_CLK</p></li> |
| <li>DFSDM renaming to DFSDM1 (previous definitions preserved for legacy compatibility) |
| <ul> |
| <li>All macros __HAL_RCC_DFSDM_xxx() renamed to __HAL_RCC_DFSDM1_xxx()</li> |
| <li>DfsdmClockSelection field of RCC_PeriphCLKInitTypeDef renamed to Dfsdm1ClockSelection</li> |
| <li>RCC_PERIPHCLK_DFSDM renamed to RCC_PERIPHCLK_DFSDM1</li> |
| <li>RCC_DFSDMCLKSOURCE_PCLK renamed to RCC_DFSDM1CLKSOURCE_PCLK</li> |
| <li>RCC_DFSDMCLKSOURCE_SYSCLK renamed to RCC_DFSDM1CLKSOURCE_SYSCLK</li> |
| <li>__HAL_RCC_DFSDM_CONFIG() renamed to __HAL_RCC_DFSDM1_CONFIG()</li> |
| <li>__HAL_RCC_GET_DFSDM_SOURCE() renamed to __HAL_RCC_GET_DFSDM1_SOURCE()<br /> |
| </li> |
| </ul></li> |
| <li><p>Add missing RTC clock source definition RCC_RTCCLKSOURCE_NO_CLK</p></li> |
| </ul></li> |
| <li><p><strong>HAL I2C</strong> driver</p> |
| <ul> |
| <li><p>Update to avoid waiting on STOPF/BTF/AF flag under DMA ISR by using the PPP end of transfer interrupt in the DMA transfer process. This requires the following updates on user application:</p></li> |
| <li>Configure and enable the I2Cx IRQ in HAL_I2C_MspInit() function</li> |
| <li><p>In stm32l4xx_it.c file, I2Cx_IRQHandler() function: add a call to HAL_I2C_IRQHandler() function</p></li> |
| </ul></li> |
| <li><p><strong>HAL UART/USART</strong> drivers</p> |
| <ul> |
| <li>IRQ Handler global optimization </li> |
| <li>Add error management in case of DMA transfer through HAL_DMA_Abort_IT() and DMA XferAbortCallback() |
| <ul> |
| <li>Polling management update</li> |
| <li>The user Timeout value must be estimated for the overall process duration</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL IRDA/SMARTCARD</strong> drivers</p> |
| <ul> |
| <li>Polling management update |
| <ul> |
| <li>The user Timeout value must be estimated for the overall process duration</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL SPI</strong> driver</p> |
| <ul> |
| <li>Add SPI error management during DMA process: this requires the following updates in the user application:</li> |
| <li>Configure and enable the SPIx IRQ in HAL_SPI_MspInit() function</li> |
| <li>In stm32l4xx_it.c file, SPIx_IRQHandler() function: add a call to HAL_SPI_IRQHandler() function</li> |
| <li>Add and customize the Error Callback API: HAL_SPI_ErrorCallback()]</li> |
| </ul></li> |
| <li><p><strong>HAL QSPI</strong> driver</p> |
| <ul> |
| <li>Add QSPI error management during DMA process</li> |
| <li>Improve the DMA transmit process by using QSPI TC interrupt instead of waiting on TC flag under DMA ISR</li> |
| <li>These two improvements require the following updates on user application: |
| <ul> |
| <li>Configure and enable the QSPI IRQ in HAL_QSPI_MspInit() function</li> |
| <li>In stm32l4xx_it.c file, QSPI_IRQHandler() function: add a call to HAL_QSPI_IRQHandler() function</li> |
| <li>Add and customize the Error Callback API: HAL_QSPI_ErrorCallback()</li> |
| </ul></li> |
| <li><p>Add the management of non-blocking transfer abort service: HAL_QSPI_Abort_IT(). In this case the user must:</p> |
| <ul> |
| <li>Add new callback HAL_QSPI_AbortCpltCallback() to inform user at the end of abort process</li> |
| <li>A new value of State in the HAL_QSPI_StateTypeDef provides the current state during the abort phase</li> |
| </ul></li> |
| <li>Polling management update: |
| <ul> |
| <li>The user Timeout value must be estimated for the overall process duration</li> |
| </ul></li> |
| <li>Fix wrong data size management in HAL_QSPI_Receive_DMA() |
| <ul> |
| <li>New API HAL_QSPI_SetFifoThreshold() and HAL_QSPI_GetFifoThreshold()</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>HAL IWDG</strong> driver</p> |
| <ul> |
| <li>New simplified HAL IWDG driver: |
| <ul> |
| <li>remove HAL_IWDG_Start(), HAL_IWDG_MspInit() and HAL_IWDG_GetState() APIs</li> |
| </ul></li> |
| <li>API functions are: |
| <ul> |
| <li>HAL_IWDG_Init(): this function insures the configuration and the start of the IWDG counter</li> |
| <li>HAL_IWDG_Refresh(): this function insures the reload of the IWDG counter</li> |
| </ul></li> |
| <li>Refer to the following example to identify the changes: IWDG_Example</li> |
| </ul></li> |
| <li><p><strong>HAL WWDG</strong> driver</p> |
| <ul> |
| <li>New simplified HAL WWDG driver: remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit() and HAL_WWDG_GetState() APIs |
| <ul> |
| <li>Update HAL_WWDG_Refresh() API to remove counter parameter</li> |
| <li>New field EWIMode in WWDG_InitTypeDef to specify need for Early Wakeup Interrupt</li> |
| </ul></li> |
| <li>API functions are: HAL_WWDG_Init(), HAL_WWDG_MspInit(), HAL_WWDG_Refresh(), HAL_WWDG_IRQHandler() and HAL_WWDG_EarlyWakeupCallback()</li> |
| </ul></li> |
| <li><p><strong>HAL DMA</strong> driver</p> |
| <ul> |
| <li><p>Global driver code optimization to reduce memory footprint </p></li> |
| <li>New APIs HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback() to register/unregister the different possible callbacks identified by enum typedef HAL_DMA_CallbackIDTypeDef</li> |
| <li>New API HAL_DMA_Abort_IT() to abort DMA transfer in non-blocking mode for interrupt context</li> |
| <li>The new registered Abort callback is called when DMA transfer abortion is completed</li> |
| <li>Add new Error Codes: HAL_DMA_ERROR_NO_XFER and HAL_DMA_ERROR_NOT_SUPPORTED</li> |
| <li><p>Add __HAL_DMA_GET_COUNTER() macro<br /> |
| </p></li> |
| </ul></li> |
| <li><strong>HAL COMP</strong> driver |
| <ul> |
| <li>EXTI configuration done in HAL_COMP_Init() based on TriggerMode field of COMP_InitTypeDef structure; HAL_COMP_Start()/HAL_COMP_Stop() APIs are sufficient to start and stop comparators (HAL_COMP_Start_IT() and HAL_COMP_Stop_IT() are preserved for legacy compatibility)</li> |
| <li>Add comparator startup time and scaler bridge stabilization time in HAL_COMP_Init()</li> |
| <li>Fix to call HAL_COMP_TriggerCallback() only once when the 2 comparators are configured in window mode</li> |
| <li>Inverting & Non-inverting inputs renaming (previous definitions preserved for legacy compatibility) |
| <ul> |
| <li>COMP_INVERTING_xxx definitions renamed to COMP_INPUT_MINUS_xxx</li> |
| <li>COMP_NONINVERTING_xxx definitions renamed to COMP_INPUT_PLUS_xxx</li> |
| </ul></li> |
| <li>Blanking sources renaming to highlight Comparator & Timer instances connections (previous definitions preserved for legacy compatibility) |
| <ul> |
| <li>COMP_BLANKINGSRCE_TIM1OC5 renamed to COMP_BLANKINGSRC_TIM1_OC5_COMP1</li> |
| <li>COMP_BLANKINGSRCE_TIM2OC3 renamed to COMP_BLANKINGSRC_TIM2_OC3_COMP1</li> |
| <li>COMP_BLANKINGSRCE_TIM3OC3 renamed to COMP_BLANKINGSRC_TIM3_OC3_COMP1</li> |
| <li>COMP_BLANKINGSRCE_TIM3OC4 renamed to COMP_BLANKINGSRC_TIM3_OC4_COMP2</li> |
| <li>COMP_BLANKINGSRCE_TIM8OC5 renamed to COMP_BLANKINGSRC_TIM8_OC5_COMP2</li> |
| <li>COMP_BLANKINGSRCE_TIM15OC1 renamed to COMP_BLANKINGSRC_TIM15_OC1_COMP2</li> |
| <li>COMP_BLANKINGSRCE_NONE renamed to COMP_BLANKINGSRC_NONE</li> |
| </ul></li> |
| </ul></li> |
| <li><strong>HAL CRYP</strong> driver |
| <ul> |
| <li>Software workaround for AES issue on GCM encryption with payload length not a multiple of 128 bits</li> |
| <li>Add support of payload length not multiple of 32 bits<br /> |
| </li> |
| </ul></li> |
| <li><p><strong>HAL GPIO</strong> driver</p> |
| <ul> |
| <li>Add missing GPIO_AF6_COMP1 for STM32L431xx/STM32L432xx/STM32L433xx/STM32L442xx/STM32L443xx</li> |
| <li>DFSDM renaming to DFSDM1 (previous definitions preserved for legacy compatibility) |
| <ul> |
| <li>GPIO_AF6_DFSDM renamed to GPIO_AF6_DFSDM1<br /> |
| </li> |
| </ul></li> |
| </ul></li> |
| <li><strong>HAL HCD</strong> driver |
| <ul> |
| <li>Clear NACK flag before re-enabling the channel for new IN request</li> |
| </ul></li> |
| <li><p><strong>HAL PCD</strong> driver</p> |
| <ul> |
| <li>Host mode |
| <ul> |
| <li>Use HCLK frequency to set TRDT value</li> |
| </ul></li> |
| <li>Device mode |
| <ul> |
| <li>Force suspend and low-power mode before going to L1 state</li> |
| </ul></li> |
| <li>Unmask Start Of Frame interrupt<br /> |
| </li> |
| </ul></li> |
| <li><p><strong>HAL TIM</strong> driver</p> |
| <ul> |
| <li>DFSDM renaming to DFSDM1 (previous definitions preserved for legacy compatibility)</li> |
| <li>TIM_BREAKINPUTSOURCE_DFSDM renamed to TIM_BREAKINPUTSOURCE_DFSDM1</li> |
| </ul></li> |
| <li><p><strong>HAL SAI</strong> driver</p> |
| <ul> |
| <li><p>Update HAL_SAI_IRQHandler:</p></li> |
| <li><p>Add error management in case of DMA transfer through HAL_DMA_Abort_IT() and DMAXferAbortCallback()</p></li> |
| </ul></li> |
| <li><p><strong>HAL SWPMI</strong> driver</p> |
| <ul> |
| <li>Update initialization sequence in voltage class B</li> |
| </ul></li> |
| </ul> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">LL drivers changes</span></span></strong></p> |
| <ul> |
| <li><strong>LL ADC</strong> driver |
| <ul> |
| <li>Fix injected conversion configuration with SW start in LL_ADC_INJ_ConfigQueueContext()</li> |
| </ul></li> |
| <li><strong>LL BUS</strong> driver |
| <ul> |
| <li>DFSDM renaming to DFSDM1 (previous definitions preserved for legacy compatibility)</li> |
| <li>LL_APB2_GRP1_PERIPH_DFSDM renamed to LL_APB2_GRP1_PERIPH_DFSDM1</li> |
| </ul></li> |
| <li><strong>LL COMP</strong> driver |
| <ul> |
| <li>Window mode renaming to highlight Comparator instances connection (previous definitions preserved for legacy compatibility)</li> |
| <li>LL_COMP_WINDOWMODE_ENABLE renamed to LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON<br /> |
| </li> |
| <li>Blanking sources renaming to highlight Comparator & Timer instances connections (previous definitions preserved for legacy compatibility)</li> |
| <li>LL_COMP_BLANKINGSRCE_TIM1OC5 renamed to LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1</li> |
| <li>LL_COMP_BLANKINGSRCE_TIM2OC3 renamed to LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1</li> |
| <li>LL_COMP_BLANKINGSRCE_TIM3OC3 renamed to LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1</li> |
| <li>LL_COMP_BLANKINGSRCE_TIM3OC4 renamed to LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2</li> |
| <li>LL_COMP_BLANKINGSRCE_TIM8OC5 renamed to LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2</li> |
| <li>LL_COMP_BLANKINGSRCE_TIM15OC1 renamed to LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2</li> |
| </ul></li> |
| <li><strong>LL I2C</strong> driver |
| <ul> |
| <li>Add SMBus feature support |
| <ul> |
| <li>LL_I2C_InitTypeDef structure enriched with new PeripheralMode field to indicate I2C or SMBus modes</li> |
| <li>New APIs LL_I2C_EnableSMBusAlert(), LL_I2C_DisableSMBusAlert(), LL_I2C_IsEnabledSMBusAlert(), LL_I2C_EnableSMBusPEC(), LL_I2C_DisableSMBusPEC(), LL_I2C_IsEnabledSMBusPEC(), LL_I2C_ConfigSMBusTimeout(), LL_I2C_EnableSMBusTimeout(), LL_I2C_DisableSMBusTimeout(), LL_I2C_IsEnabledSMBusTimeout(), LL_I2C_SetSMBusTimeoutA(), LL_I2C_GetSMBusTimeoutA(), LL_I2C_SetSMBusTimeoutAMode(), LL_I2C_GetSMBusTimeoutAMode(), LL_I2C_SetSMBusTimeoutB(), LL_I2C_GetSMBusTimeoutB(), LL_I2C_SetSMBusTimeoutBMode(), LL_I2C_GetSMBusTimeoutBMode(), LL_I2C_IsActiveSMBusFlag_PECERR(), LL_I2C_IsActiveSMBusFlag_TIMEOUT(), LL_I2C_IsActiveSMBusFlag_ALERT(), LL_I2C_ClearSMBusFlag_PECERR(), LL_I2C_ClearSMBusFlag_TIMEOUT(), LL_I2C_ClearSMBusFlag_ALERT(), LL_I2C_EnableSMBusPECCompare(), LL_I2C_IsEnabledSMBusPECCompare() and LL_I2C_GetSMBusPEC()</li> |
| </ul></li> |
| <li>New APIs LL_I2C_SetMode() and LL_I2C_GetMode()</li> |
| <li>New APIs LL_I2C_EnableAutoEndMode(), LL_I2C_DisableAutoEndMode() and LL_I2C_IsEnabledAutoEndMode()</li> |
| <li>New APIs LL_I2C_EnableReloadMode(), LL_I2C_DisableReloadMode() and LL_I2C_IsEnabledReloadMode()</li> |
| <li>New APIs LL_I2C_EnableSlaveByteControl(), LL_I2C_DisableSlaveByteControl() and LL_I2C_IsEnabledSlaveByteControl()</li> |
| <li>New APIs LL_I2C_SetTransferRequest(), LL_I2C_GetTransferRequest(), LL_I2C_SetSlaveAddr() and LL_I2C_GetSlaveAdd()</li> |
| <li>New APIs LL_I2C_SetTransferSize() and LL_I2C_GetTransferSize()</li> |
| <li>New APIs LL_I2C_GenerateStopCondition(), L_I2C_GenerateStartCondition()</li> |
| <li>New APIs LL_I2C_EnableAuto10BitRead(), LL_I2C_DisableAuto10BitRead() and LL_I2C_IsEnabledAuto10BitRead()</li> |
| </ul></li> |
| <li><strong>LL PWR</strong> driver |
| <ul> |
| <li>New APIs LL_PWR_EnterLowPowerRunMode() and LL_PWR_ExitLowPowerRunMode()</li> |
| </ul></li> |
| <li><p><strong>LL RCC</strong> driver</p> |
| <ul> |
| <li>DFSDM renaming to DFSDM1 (previous definitions preserved for legacy compatibility)</li> |
| <li>LL_RCC_DFSDM_CLKSOURCE renamed to LL_RCC_DFSDM1_CLKSOURCE</li> |
| <li>LL_RCC_DFSDM_CLKSOURCE_PCLK renamed to LL_RCC_DFSDM1_CLKSOURCE_PCLK</li> |
| <li>LL_RCC_DFSDM_CLKSOURCE_SYSCLK renamed to LL_RCC_DFSDM1_CLKSOURCE_SYSCLK </li> |
| </ul></li> |
| <li><p><strong>LL SYSTEM</strong> driver</p></li> |
| <li><p>New API LL_FLASH_IsPrefetchEnabled()</p></li> |
| <li><strong>LL TIM</strong> driver |
| <ul> |
| <li>DFSDM renaming to DFSDM1 (previous definitions preserved for legacy compatibility)</li> |
| <li>LL_TIM_BKIN_SOURCE_DFBK renamed to LL_TIM_BKIN_SOURCE_DF1BK</li> |
| <li>New OCRef clear input selection definitions LL_TIM_OCREF_CLR_INT_NC and LL_TIM_OCREF_CLR_INT_ETR</li> |
| <li>New OCRef clear API LL_TIM_SetOCRefClearInputSource()</li> |
| </ul></li> |
| </ul> |
| </div> |
| </div> |
| <div class="collapse"> |
| <input type="checkbox" id="collapse-section14" aria-hidden="true"> <label for="collapse-section14" aria-hidden="true">V1.4.0 / 26-February-2016</label> |
| <div> |
| <h2 id="main-changes-17">Main Changes</h2> |
| <ul> |
| <li>Release of <strong>HAL and Low Layer drivers</strong> to add support of <strong>STM32L431xx/STM32L432xx/STM32L433xx/STM32L442xx/STM32L443xx</strong> devices</li> |
| <li><strong>Low Layer driver initialization/de-initialization APIs</strong> applicable to all STM32L4xx devices</li> |
| <li><strong>CRS</strong> peripheral implemented as an extension of HAL RCC (HAL_RCCEx_CRS_xxxx APIs)</li> |
| <li>Superset features device STM32L443xx API User Manual available (STM32L443xx_User_Manual.chm) <br /> |
| </li> |
| </ul> |
| <h2 id="contents-18">Contents</h2> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p> |
| <ul> |
| <li><p><strong>HAL</strong> generic update</p> |
| <ul> |
| <li>Add default HSI48_VALUE in stm32l4xx_hal_conf_template</li> |
| </ul></li> |
| <li><strong>HAL CRYP</strong> update |
| <ul> |
| <li>New error code HAL_CRYP_BUSY_ERROR to reject new request while ongoing processing</li> |
| </ul></li> |
| <li><p><strong>HAL IRDA/SMARTCARD/UART/USART </strong> update</p> |
| <ul> |
| <li>Improvement of baud rate computation at initialization</li> |
| </ul></li> |
| </ul> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">LL drivers changes</span></span></strong></p> |
| <ul> |
| <li>New C files requiring to use USE_FULL_LL_DRIVER compilation switch in user project to benefit from new APIs |
| <ul> |
| <li>stm32l4xx_ll_crs.c</li> |
| </ul></li> |
| <li><strong>LL BUS</strong> update |
| <ul> |
| <li>Add read-back register on clock enable functions to take into account any delay on bus</li> |
| </ul></li> |
| <li><p><strong>LL ADC</strong> update</p> |
| <ul> |
| <li><p>Trigger sources renaming:</p> |
| <ul> |
| <li>LL_ADC_REG_TRIG_SW_START renamed to LL_ADC_REG_TRIG_SOFTWARE</li> |
| <li>LL_ADC_REG_TRIG_EXT_TIMx_CCy renamed to LL_ADC_REG_TRIG_EXT_TIMx_CHy</li> |
| <li>LL_ADC_INJ_TRIG_SW_START renamed to LL_ADC_INJ_TRIG_SOFTWARE</li> |
| <li>LL_ADC_INJ_TRIG_EXT_TIMx_CCy renamed to LL_ADC_INJ_TRIG_EXT_TIMx_CHy</li> |
| </ul></li> |
| <li><p>Oversamping data shift renaming:</p> |
| <ul> |
| <li>LL_ADC_OVS_DATA_SHIFT_NONE renamed to LL_ADC_OVS_SHIFT_NONE</li> |
| <li>LL_ADC_OVS_DATA_SHIFT_xxx renamed to LL_ADC_OVS_SHIFT_xxx</li> |
| </ul></li> |
| </ul></li> |
| <li><strong>LL DAC</strong> update |
| <ul> |
| <li><p>Trigger sources renaming:</p> |
| <ul> |
| <li>LL_DAC_TRIGGER_SOFTWARE renamed to LL_DAC_TRIG_SOFTWARE</li> |
| <li>LL_DAC_TRIGGER_TIMx_TRGO renamed to LL_DAC_TRIG_EXT_TIMx_TRGO</li> |
| <li>LL_DAC_TRIGGER_EXT_IT9 renamed to LL_DAC_TRIG_EXT_EXTI_LINE9</li> |
| </ul></li> |
| </ul></li> |
| <li><strong>LL LPUART</strong> update |
| <ul> |
| <li>Improvement of LPUARTDIV value in baud rate computation in __LL_LPUART_DIV() macro</li> |
| </ul></li> |
| <li><strong>LL USART</strong> update |
| <ul> |
| <li>Improvement of USARTDIV value in baud rate computation in __LL_USART_DIV_SAMPLING8() and __LL_USART_DIV_SAMPLING16() macros</li> |
| </ul></li> |
| </ul> |
| </div> |
| </div> |
| <div class="collapse"> |
| <input type="checkbox" id="collapse-section15" aria-hidden="true"> <label for="collapse-section15" aria-hidden="true">V1.3.0 / 29-January-2016</label> |
| <div> |
| <h2 id="main-changes-18">Main Changes</h2> |
| <ul> |
| <li><strong>New Low Layer driver initialization/de-initialization APIs</strong> |
| <ul> |
| <li>Naming rule is LL_PPP_Init(), LL_PPP_StructInit(), LL_PPP_DeInit() and more initialization APIs when applicable for peripheral PPP: ADC, COMP, CRC, DAC, DMA, EXTI, GPIO, I2C, LPTIM, LPUART, OPAMP, PWR, RCC, RNG, RTC, SPI, SWPMI, TIM and USART. </li> |
| </ul></li> |
| <li>New C files requiring to use USE_FULL_LL_DRIVER compilation switch in user project to benefit from new APIs |
| <ul> |
| <li>stm32l4xx_ll_adc.c, stm32l4xx_ll_comp.c, stm32l4xx_ll_crc.c, stm32l4xx_ll_dac.c, stm32l4xx_ll_dma.c, stm32l4xx_ll_exti.c, stm32l4xx_ll_gpio.c, stm32l4xx_ll_i2c.c, stm32l4xx_ll_lptim.c, stm32l4xx_ll_lpuart.c, stm32l4xx_ll_opamp.c, stm32l4xx_ll_pwr.c, stm32l4xx_ll_rcc.c, stm32l4xx_ll_rng.c, stm32l4xx_ll_rtc.c, stm32l4xx_ll_spi.c, stm32l4xx_ll_swpmi.c, stm32l4xx_ll_tim.c and stm32l4xx_ll_usart.c</li> |
| <li>stm32l4xx_ll_utils.c contains some Low Layer utilities for SysTick, Flash latency and clock configuration. </li> |
| </ul></li> |
| <li>Fix "parameter unused" GCC compilation warnings on __weak functions</li> |
| </ul> |
| <h2 id="contents-19">Contents</h2> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p> |
| <ul> |
| <li><p><strong>HAL generic</strong> update</p> |
| <ul> |
| <li>Declare uwTick as global variable to allow weak HAL_IncTick() API updates in user application </li> |
| <li>Add new API HAL_SYSCFG_EnableIOAnalogSwitchBooster() and HAL_SYSCFG_DisableIOAnalogSwitchBooster()<br /> |
| </li> |
| </ul></li> |
| <li><p><strong>HAL COMP</strong> update</p> |
| <ul> |
| <li>Allow comparator lock from the reset state with HAL_COMP_Lock()</li> |
| </ul></li> |
| <li><p><strong>HAL CRYP</strong> update</p> |
| <ul> |
| <li>Fix state issue to resume AES calculations</li> |
| </ul></li> |
| <li><p><strong>HAL DMA</strong> update</p> |
| <ul> |
| <li>Fix state issue after DMA transfer error </li> |
| </ul></li> |
| <li><p><strong>HAL FLASH</strong> update</p> |
| <ul> |
| <li>Fix __HAL_FLASH_INSTRUCTION_CACHE_RESET() and __HAL_FLASH_DATA_CACHE_RESET() to allow multiple resets</li> |
| </ul></li> |
| <li><p><strong>HAL I2C</strong> update</p> |
| <ul> |
| <li>Add support of repeated start feature with the following new APIs |
| <ul> |
| <li>HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Sequential_Receive_IT() and HAL_I2C_Master_Abort_IT(), </li> |
| <li>HAL_I2C_Slave_Sequential_Transmit_IT() and HAL_I2C_Slave_Sequential_Receive_IT()</li> |
| <li>HAL_I2C_EnableListen_IT() and HAL_I2C_DisableListen_IT()</li> |
| <li>New user callbacks HAL_I2C_ListenCpltCallback() and HAL_I2C_AddrCallback()<br /> |
| </li> |
| </ul></li> |
| <li>Fix acknowledge failure error management (STOP being automatically generated)</li> |
| <li>Review state machine and provide new API HAL_I2C_GetMode() to return HAL_I2C_MODE_MASTER, HAL_I2C_MODE_SLAVE or HAL_I2C_MODE_NONE<br /> |
| </li> |
| </ul></li> |
| <li><p><strong>HAL IRDA</strong> update</p> |
| <ul> |
| <li>Add missing IRDA_CLEAR_IDLEF definition for IDLE flag clear with __HAL_IRDA_CLEAR_FLAG()</li> |
| </ul></li> |
| <li><p><strong>HAL SD</strong> update</p> |
| <ul> |
| <li>Fix SD card capacity calculation for cards with capacity over 4GB in HAL_SD_Get_CardInfo()</li> |
| </ul></li> |
| <li><p><strong>HAL SMARTCARD</strong> update</p> |
| <ul> |
| <li>Add missing SMARTCARD_STOPBITS_0_5 definition for frame with 0.5 stop bit</li> |
| <li>HAL SMARTCARD guardtime correction to not expect a minimum of 12 etu</li> |
| </ul></li> |
| <li><p><strong>HAL UART</strong> update</p> |
| <ul> |
| <li>Add missing UART_STOPBITS_0_5 definition for frame with 0.5 stop bit</li> |
| <li>RX Buffer flush request should not be called at each RXNE processing</li> |
| <li>Fix wrong macro used in assert_param in HAL_LIN_SendBreak()<br /> |
| </li> |
| </ul></li> |
| <li><p><strong>HAL USART</strong> update</p> |
| <ul> |
| <li>Add missing USART_STOPBITS_0_5 definition for frame with 0.5 stop bit</li> |
| </ul></li> |
| </ul> |
| <p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">LL drivers changes</span></span></strong></p> |
| <ul> |
| <li><p><strong>LL UTILS</strong> update (user code impacted!)</p> |
| <ul> |
| <li><p>Move the following functions declaration from stm32l4xx_ll_utils.h to stm32l4xx_ll_utils.c file</p></li> |
| <li><p>LL_mDelay(), LL_Init1msTick() and LL_SetSystemCoreClock()</p></li> |
| </ul></li> |
| <li><p><strong>LL ADC</strong> update</p> |
| <ul> |
| <li>FLAG & IT definition name change</li> |
| </ul></li> |
| <li><p><strong>LL COMP</strong> update</p> |
| <ul> |
| <li><p>Rename InputInverting and InputNonInverting APIs</p> |
| <ul> |
| <li>LL_COMP_Set{/Get}InputNonInverting() renamed to LL_COMP_Set{/Get}InputMinus</li> |
| <li>LL_COMP_Set{/Get}InputInverting() renamed to LL_COMP_Set{/Get}InputPlus</li> |
| </ul></li> |
| <li><p>Remove LL_COMP_SetWindowMode() and LL_COMP_GetWindowMode()<br /> |
| </p></li> |
| </ul></li> |
| <li><p><strong>LL DMA</strong> update</p> |
| <ul> |
| <li>Add helper macro __LL_DMA_GET_CHANNEL_INSTANCE()</li> |
| </ul></li> |
| <li><p><strong>LL GPIO</strong> update</p> |
| <ul> |
| <li>Fix definition LL_GPIO_OUTPUT_OPENDRAIN</li> |
| <li>Add the explicit possible values in the API description of LL_GPIO_GetPinMode(), LL_GPIO_GetPinOutputType(), LL_GPIO_GetPinSpeed(), LL_GPIO_GetPinPull(), LL_GPIO_GetAFPin_0_7() and LL_GPIO_GetAFPin_8_15()</li> |
| <li>Add GPIO speed definitions LL_GPIO_SPEED_FREQ_LOW, LL_GPIO_SPEED_FREQ_MEDIUM, LL_GPIO_SPEED_FREQ_HIGH and LL_GPIO_SPEED_FREQ_VERY_HIGH to align with HAL GPIO<br /> |
| </li> |
| </ul></li> |
| <li><p><strong>LL I2C</strong> update</p> |
| <ul> |
| <li>Add missing function LL_I2C_ConfigFilters() to configure noise filters<br /> |
| </li> |
| </ul></li> |
| <li><p><strong>LL LPTIM</strong> update</p> |
| <ul> |
| <li><p>Add missing functions</p> |
| <ul> |
| <li>LL_LPTIM_IsEnabled()</li> |
| <li>LL_LPTIM_SetWaveform()</li> |
| <li>LL_LPTIM_SetPolarity()<br /> |
| </li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>LL OPAMP</strong> update</p> |
| <ul> |
| <li><p>Rename power range APIs</p> |
| <ul> |
| <li>LL_OPAMP_Get{/Set}PowerRange() renamed to LL_OPAMP_Get{/Set}CommonPowerRange()</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>LL SPI</strong> update</p> |
| <ul> |
| <li>Fix LL_SPI_IsEnabled(), LL_SPI_IsEnabledCRC() and LL_SPI_IsEnabledNSSPulse()</li> |
| <li>Remove LL_SPI_Set{/Get}HalfDuplexDirection() functions: this is managed with TransferDirection parameter in LL_SPI_Set{/Get}TransferDirection()<br /> |
| </li> |
| </ul></li> |
| <li><p><strong>LL SWPMI</strong> update</p> |
| <ul> |
| <li>Add missing function LL_SWPMI_IsActivated()</li> |
| </ul></li> |
| <li><p><strong>LL TIM</strong> update</p> |
| <ul> |
| <li><p>Add missing functions</p> |
| <ul> |
| <li>LL_TIM_CC_IsEnabledChannel()</li> |
| <li>LL_TIM_OC_IsEnabledFast(), LL_TIM_OC_IsEnabledPreload() and LL_TIM_OC_IsEnabledClear()</li> |
| <li>LL_TIM_IsEnabledMasterSlaveMode()</li> |
| <li>LL_TIM_EnableExternalClock(), LL_TIM_DisableExternalClock() and LL_TIM_IsEnabledExternalClock()</li> |
| </ul></li> |
| </ul></li> |
| <li><p><strong>LL USART</strong> update</p> |
| <ul> |
| <li>Add LL_USART_STOPBITS_0_5 definition for usage in LL_USART_Set{/Get}StopBitsLength() and LL_USART_ConfigCharacter()</li> |
| </ul></li> |
| </ul> |
| </div> |
| </div> |
| <div class="collapse"> |
| <input type="checkbox" id="collapse-section16" aria-hidden="true"> <label for="collapse-section16" aria-hidden="true">V1.2.0 / 25-November-2015</label> |
| <div> |
| <h2 id="main-changes-19">Main Changes</h2> |
| <ul> |
| <li><strong>HAL generic</strong> update |
| <ul> |
| <li>Reduce default HSE startup timeout value to 100ms in Inc\stm32l4xx_hal_conf_template.h file</li> |
| </ul></li> |
| <li><strong>HAL PWR</strong> update (User application code impacted) |
| <ul> |
| <li>Stop 1 with main regulator renamed into Stop 0, to be aligned with latest version of Reference Manual</li> |
| <li>Change HAL_PWREx_EnterSTOP1Mode(uint32_t Regulator, uint8_t STOPEntry) into HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)</li> |
| <li><em>Application code using HAL_PWREx_EnterSTOP1Mode(PWR_LOWPOWERREGULATOR_ON, STOPEntry) must be updated to use HAL_PWREx_EnterSTOP1Mode(STOPEntry)</em></li> |
| <li>Add new API HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)</li> |
| <li><em>Application code using HAL_PWREx_EnterSTOP1Mode(PWR_MAINREGULATOR_ON, STOPEntry) must be updated to use HAL_PWREx_EnterSTOP0Mode(STOPEntry)</em> </li> |
| </ul></li> |
| <li><p><strong>HAL OPAMP</strong> update</p> |
| <ul> |
| <li>Provide capability to run calibration despite PGA mode by switching temporary to standalone mode</li> |
| </ul></li> |
| <li><strong>HAL SAI</strong> update |
| <ul> |
| <li><p>update SAI block synchronization selection (User application code impacted)</p></li> |
| <li><p>Replace incomplete SAI_SYNCHRONOUS_EXT value for with SAI_SYNCHRONOUS_EXT_SAI1 and SAI_SYNCHRONOUS_EXT_SAI2</p></li> |
| <li><p>Update external synchronization input selection (User application code impacted)</p></li> |
| <li><p>Remove useless SAI_SYNCEXT_IN_ENABLE value for SynchroExt field in SAI_InitTypeDef structure</p></li> |
| <li><p>Add support of 24bits configuration in PCM protocol</p></li> |
| <li><p>Add codec not ready interrupt management</p></li> |
| <li><p>Fix computation of data size, frame length, active frame length, slot size and first bit offset in I2S protocol</p></li> |
| <li><p>Fix mute counter setting in HAL_SAI_EnableRxMuteMode()</p></li> |
| <li><p>Fix ambiguous clock strobing values: fix HAL_SAI_Init() to set correct CKSTR bits in SAI_xCR1 according to ClockStrobing and AudioMode parameters</p></li> |
| <li><p>Fill in the Fifo before enable interrupt in HAL_SAI_Transmit_IT()</p></li> |
| <li>Fix assert on active slot selection in HAL_SAI_Init()</li> |
| <li><p>Fix companding mode management in HAL_SAI_Init()<br /> |
| </p></li> |
| </ul></li> |
| <li><p><strong>HAL TSC</strong> update</p> |
| <ul> |
| <li>Improve IODefault state management</li> |
| </ul></li> |
| <li><p><strong>HAL NOR/HAL SRAM/FMC</strong> update</p> |
| <ul> |
| <li>WriteFifo field of FMC_NORSRAM_InitTypeDef structure is not applicable on STM32L47x/STM32L48x devices</li> |
| </ul></li> |
| <li><p><strong>LL PWR</strong> update (User application code impacted)</p> |
| <ul> |
| <li><p>LL PWR API change to add new Stop 0 mode and update Stop 1 mode definition</p></li> |
| <li><p>Change LL_PWR_SetPowerMode(uint32_t LowPowerMode) possible LowPowerMode]{style=“font-style: italic;”} values** update </p></li> |
| <li><p>LL_PWR_MODE_STOP1_LP_REGU renamed into LL_PWR_MODE_STOP1</p></li> |
| <li><p>Application code using LL_PWR_SetPowerMode(LL_PWR_MODE_STOP1_LP_REGU) must be updated to use LL_PWR_SetPowerMode(LL_PWR_MODE_STOP1)</p></li> |
| <li><p>LL_PWR_MODE_STOP1_MAIN_REGU renamed into LL_PWR_MODE_STOP0</p></li> |
| <li><p>Application code using LL_PWR_SetPowerMode(LL_PWR_MODE_STOP1_MAIN_REGU) must be updated to use LL_PWR_SetPowerMode(LL_PWR_MODE_STOP0)</p></li> |
| </ul></li> |
| </ul> |
| </div> |
| </div> |
| <div class="collapse"> |
| <input type="checkbox" id="collapse-section17" aria-hidden="true"> <label for="collapse-section17" aria-hidden="true">V1.1.1 / 16-October-2015</label> |
| <div> |
| <h2 id="main-changes-20">Main Changes</h2> |
| <ul> |
| <li><p><strong>HAL generic</strong> update</p> |
| <ul> |
| <li>Fine tuning of Inc\stm32l4xx_hal_conf_template.h file to keep Flash prefetch off as default system configuration (PREFETCH_ENABLE set to 0)<br /> |
| </li> |
| </ul></li> |
| <li><p><strong>HAL TIM</strong> update</p> |
| <ul> |
| <li>Removed useless assert_param() macro check on input parameters in HAL_TIM_OC_ConfigChannel(), HAL_TIM_PWM_ConfigChannel() and HAL_TIM_ConfigClockSource(), </li> |
| </ul></li> |
| <li><p><strong>LL ADC</strong> update</p> |
| <ul> |
| <li>Fix LL_ADC_GetAnalogWDMonitChannels() for AWD2 and AWD3</li> |
| </ul></li> |
| <li><p><strong>LL RCC</strong> update</p> |
| <ul> |
| <li>Add new API LL_RCC_LSE_DisableCSS()</li> |
| </ul></li> |
| <li><p><strong>LL UTILS</strong> update</p> |
| <ul> |
| <li>Fix LL_GetPackageType()<br /> |
| </li> |
| </ul></li> |
| </ul> |
| </div> |
| </div> |
| <div class="collapse"> |
| <input type="checkbox" id="collapse-section20" aria-hidden="true"> <label for="collapse-section20" aria-hidden="true">V1.1.0 / 26-September-2015</label> |
| <div> |
| <h2 id="main-changes-21">Main Changes</h2> |
| <p><strong>Add Low Layer drivers allowing performance and footprint optimization</strong></p> |
| <ul> |
| <li>Low Layer drivers APIs provide register level programming: they require deep knowledge of peripherals described in STM32L4x6 Reference Manual</li> |
| <li><p>Low Layer drivers are available for: ADC, COMP, Cortex, CRC, DAC, DMA, EXTI, GPIO, I2C, IWDG, LPYIM, LPUART, OPAMP, PWR, RCC, RNG, RTC, SPI, SWPMI, TIM, USART, WWDG peripherals and additional Low Level Bus, System and Utilities APIs.<br /> |
| </p></li> |
| <li><p>Low Layer drivers APIs are implemented as static inline function in new Inc/stm32l4xx_ll_ppp.h files for PPP peripherals, there is no configuration file and each stm32l4xx_ll_ppp.h file must be included in user code.</p></li> |
| </ul> |
| <h2 id="contents-20">Contents</h2> |
| <ul> |
| <li><p><strong>HAL ADC</strong> update</p> |
| <ul> |
| <li>Channel 5 is not usable for ADC3</li> |
| </ul></li> |
| <li><p><strong>HAL CAN</strong> update</p> |
| <ul> |
| <li>Update HAL_CAN_IRQHandler() to clear ERRI bit prior to call HAL_CAN_ErrorCallback()</li> |
| </ul></li> |
| <li><p><strong>HAL COMP</strong> update</p> |
| <ul> |
| <li>Update HAL_COMP_Init() for low power optimization in case of COMP_INVERTINGINPUT_VREFINT</li> |
| </ul></li> |
| <li><p><strong>HAL CRC</strong> update</p> |
| <ul> |
| <li>Add new API HAL_CRYPEx_ProcessSuspend()</li> |
| </ul></li> |
| <li><p><strong>HAL DMA</strong> update</p> |
| <ul> |
| <li>Update HAL_DMA_IRQHandler() to set HAL_DMA_ERROR_TE error bit in handle ErrorCode field</li> |
| </ul></li> |
| <li><p><strong>HAL FLASH</strong> update</p> |
| <ul> |
| <li>Add option byte OB_USER_nRST_SHDW to be used with HAL_FLASHEx_OBProgram()</li> |
| </ul></li> |
| <li><p><strong>HAL GPIO</strong> update</p> |
| <ul> |
| <li>Rename GPIO speed definitions to GPIO_SPEED_FREQ_LOW, GPIO_SPEED_FREQ_MEDIUM, GPIO_SPEED_FREQ_HIGH and GPIO_SPEED_FREQ_VERY_HIGH</li> |
| <li>Fix macro __HAL_GPIO_EXTI_GENERATE_SWIT()</li> |
| </ul></li> |
| <li><p><strong>HAL PWR</strong> update</p> |
| <ul> |
| <li>Fix HAL_PWR_DisableWakeUpPin() to clear only appropriate bits in PWR CR3 register</li> |
| <li>Combination of GPIO pins possible in HAL_PWREx_EnableGPIOPullUp(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown() and HAL_PWREx_DisableGPIOPullDown()</li> |
| </ul></li> |
| <li><p><strong>HAL RCC</strong> update</p> |
| <ul> |
| <li>Add LSE Clock Security System (CSS) management with new APIs: HAL_RCCEx_EnableLSECSS_IT(), HAL_RCCEx_LSECSS_IRQHandler() and HAL_RCCEx_LSECSS_Callback()</li> |
| <li>Add RCC_MCO1SOURCE_NOCLOCK to provide capability to disable MCO output in HAL_RCC_MCOConfig()</li> |
| <li>Update HAL_RCC_OscConfig() and HAL_RCCEx_PeriphCLKConfig() to keep backup domain enabled when configuring respectively LSE and RTC clock source</li> |
| <li>Update HAL_RCCEx_DisablePLLSAI1() and HAL_RCCEx_DisablePLLSAI2() to disable respectively PLLSAI1 and PLLSAI2 clock outputs</li> |
| <li><p>Update HAL_RCCEx_GetPeriphCLKFreq() to return the frequency in Hz applied to peripherals via HAL_RCCEx_PeriphCLKConfig()<br /> |
| </p></li> |
| <li>Update HAL_RCC_DeInit() to set default MSI range</li> |
| <li><p>Remove old workaround on LSE drive medium configuration values</p></li> |
| </ul></li> |
| <li><p><strong>HAL SPI</strong> update</p> |
| <ul> |
| <li>Fix issue to receive CRC in RX 2 lines mode 8-bit dataSize and even buffer size.</li> |
| </ul></li> |
| <li><p><strong>HAL TIM</strong> update</p> |
| <ul> |
| <li>Fix macro __HAL_TIM_SET_COMPARE()</li> |
| </ul></li> |
| <li><p><strong>HAL UART</strong> update</p> |
| <ul> |
| <li>Remove enable of Error interrupt in HAL_UART_Transmit_IT()</li> |
| </ul></li> |
| </ul> |
| </div> |
| </div> |
| <div class="collapse"> |
| <input type="checkbox" id="collapse-section18" aria-hidden="true"> <label for="collapse-section18" aria-hidden="true">V1.0.0 / 26-June-2015</label> |
| <div> |
| <h2 id="main-changes-22">Main Changes</h2> |
| <ul> |
| <li>First official release of <strong>STM32L4xx HAL Drivers</strong> for <strong>STM32L471xx/STM32L475xx/STM32L476xx/STM32L485xx</strong> and <strong>STM32L486xx</strong> devices</li> |
| </ul> |
| </div> |
| </div> |
| </div> |
| </div> |
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| <p>For complete documentation on <mark>STM32 Microcontrollers</mark> , visit: <a href="http://www.st.com/STM32">http://www.st.com/STM32</a></p> |
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