commit 49aacb861d9f2b4c43238989e7ba19d82c230641
author Ali Labbene <ali.labbene@st.com> Thu Jan 20 18:29:52 2022 +0100
committer Ali Labbene <ali.labbene@st.com> Thu Jan 20 19:13:52 2022 +0100
tree 8b54e3080e148fdc82da9e8b001e8ff2f32c0f9b
parent 4ba2c74a0d59fb10bd47ea381b30ba3909b829fe

[HAL][OSPI] Update HAL_OSPI_Init() to fix DelayBlockBypass parameter configuration issue

Inc/stm32l4xx_hal_ospi.h

diff --git a/Inc/stm32l4xx_hal_ospi.h b/Inc/stm32l4xx_hal_ospi.h
index 6f68f67..0f504db 100644
--- a/Inc/stm32l4xx_hal_ospi.h
+++ b/Inc/stm32l4xx_hal_ospi.h
@@ -1004,6 +1004,9 @@
 #define IS_OSPI_TIMEOUT_PERIOD(PERIOD)     ((PERIOD) <= 0xFFFFU)
 
 #define IS_OSPI_CS_BOUNDARY(BOUNDARY)      ((BOUNDARY) <= 31U)
+
+#define IS_OSPI_DLYBYP(MODE)               (((MODE) == HAL_OSPI_DELAY_BLOCK_USED) || \
+                                            ((MODE) == HAL_OSPI_DELAY_BLOCK_BYPASSED))
 #if   defined (OCTOSPI_DCR3_MAXTRAN)
 
 #define IS_OSPI_MAXTRAN(NB_BYTES)          ((NB_BYTES) <= 255U)

Src/stm32l4xx_hal_ospi.c

diff --git a/Src/stm32l4xx_hal_ospi.c b/Src/stm32l4xx_hal_ospi.c
index 118ce2d..de02f21 100644
--- a/Src/stm32l4xx_hal_ospi.c
+++ b/Src/stm32l4xx_hal_ospi.c
@@ -341,6 +341,7 @@
     assert_param(IS_OSPI_SAMPLE_SHIFTING(hospi->Init.SampleShifting));
     assert_param(IS_OSPI_DHQC           (hospi->Init.DelayHoldQuarterCycle));
     assert_param(IS_OSPI_CS_BOUNDARY    (hospi->Init.ChipSelectBoundary));
+    assert_param(IS_OSPI_DLYBYP         (hospi->Init.DelayBlockBypass));
 #if   defined (OCTOSPI_DCR3_MAXTRAN)
     assert_param(IS_OSPI_MAXTRAN        (hospi->Init.MaxTran));
 #endif
@@ -379,11 +380,14 @@
       /* Configure the default timeout for the OSPI memory access */
       (void)HAL_OSPI_SetTimeout(hospi, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
 
-     /* Configure memory type, device size, chip select high time, free running clock, clock mode */
-      MODIFY_REG(hospi->Instance->DCR1, (OCTOSPI_DCR1_MTYP | OCTOSPI_DCR1_DEVSIZE | OCTOSPI_DCR1_CSHT |
-                                         OCTOSPI_DCR1_FRCK | OCTOSPI_DCR1_CKMODE),
+      /* Configure memory type, device size, chip select high time, delay block bypass,
+         free running clock, clock mode */
+      MODIFY_REG(hospi->Instance->DCR1,
+                 (OCTOSPI_DCR1_MTYP | OCTOSPI_DCR1_DEVSIZE | OCTOSPI_DCR1_CSHT | OCTOSPI_DCR1_DLYBYP |
+                  OCTOSPI_DCR1_FRCK | OCTOSPI_DCR1_CKMODE),
                  (hospi->Init.MemoryType | ((hospi->Init.DeviceSize - 1U) << OCTOSPI_DCR1_DEVSIZE_Pos) |
-                  ((hospi->Init.ChipSelectHighTime - 1U) << OCTOSPI_DCR1_CSHT_Pos) | hospi->Init.ClockMode));
+                  ((hospi->Init.ChipSelectHighTime - 1U) << OCTOSPI_DCR1_CSHT_Pos) |
+                  hospi->Init.DelayBlockBypass | hospi->Init.ClockMode));
 
 #if   defined (OCTOSPI_DCR3_MAXTRAN)
       /* Configure chip select boundary and maximum transfer */