Release v1.13.2
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index 1f40166..48aff55 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -7,13 +7,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -38,6 +37,14 @@
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
+#if defined(STM32U5)
+#define CRYP_DATATYPE_32B CRYP_NO_SWAP
+#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
+#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
+#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
+#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
+#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
+#endif /* STM32U5 */
/**
* @}
*/
@@ -206,6 +213,20 @@
* @{
*/
#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
+#if defined(STM32U5)
+#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE
+#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE
+#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE
+#endif /* STM32U5 */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Aliases CRC API aliases
+ * @{
+ */
+#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
+#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
/**
* @}
*/
@@ -235,11 +256,18 @@
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
-#if defined(STM32G4) || defined(STM32H7)
+#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
+#if defined(STM32U5)
+#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1
+#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1
+#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
+#endif
+
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
@@ -469,15 +497,24 @@
#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
#endif
#if defined(STM32H7)
-#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
-#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
-#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
-#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
-#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
-#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
-#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
-#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
+#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
+#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
+#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
+#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
+#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
+#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
+#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
+#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
#endif /* STM32H7 */
+#if defined(STM32U5)
+#define OB_USER_nRST_STOP OB_USER_NRST_STOP
+#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
+#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
+#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0
+#define OB_USER_nBOOT0 OB_USER_NBOOT0
+#define OB_nBOOT0_RESET OB_NBOOT0_RESET
+#define OB_nBOOT0_SET OB_NBOOT0_SET
+#endif /* STM32U5 */
/**
* @}
@@ -520,6 +557,7 @@
#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
#endif /* STM32G4 */
+
/**
* @}
*/
@@ -594,12 +632,12 @@
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB)
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/
#if defined(STM32L1)
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
@@ -615,6 +653,20 @@
#endif /* STM32F0 || STM32F3 || STM32F1 */
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
+
+#if defined(STM32U5)
+#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
+#endif /* STM32U5 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32U5)
+#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
+#endif /* STM32U5 */
/**
* @}
*/
@@ -851,6 +903,21 @@
#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue
+/**
+ * @}
+ */
+
+#if defined(STM32U5)
+#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
+#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
+#define LPTIM_CHANNEL_ALL 0x00000000U
+#endif /* STM32U5 */
/**
* @}
*/
@@ -1189,6 +1256,10 @@
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
#endif
+#if defined(STM32U5) || defined(STM32MP2)
+#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
+#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
+#endif
/**
* @}
*/
@@ -1377,6 +1448,20 @@
*/
#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+ || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
+ || defined(STM32H7) || defined(STM32U5)
+/** @defgroup DMA2D_Aliases DMA2D API Aliases
+ * @{
+ */
+#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
+ for compatibility with legacy code */
+/**
+ * @}
+ */
+
+#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */
+
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
* @{
*/
@@ -1395,6 +1480,29 @@
* @}
*/
+/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose
+ * @{
+ */
+
+#if defined(STM32U5)
+#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr
+#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT
+#endif /* STM32U5 */
+
+/**
+ * @}
+ */
+
+#if !defined(STM32F2)
+/** @defgroup HASH_alias HASH API alias
+ * @{
+ */
+#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */
+/**
+ *
+ * @}
+ */
+#endif /* STM32F2 */
/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
* @{
*/
@@ -3327,6 +3435,31 @@
#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
+#if defined(STM32U5)
+#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
+#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
+#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
+#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
+#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
+#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE
+#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE
+#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE
+#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE
+#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE
+#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE
+#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT
+#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK
+#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48
+#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
+#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
+#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
+#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#endif
/**
* @}
@@ -3344,7 +3477,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL)
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3401,13 +3534,22 @@
* @}
*/
-/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
+/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose
* @{
*/
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
+#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
+#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
+#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
+#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
+
+#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV
+#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV
+#endif
+
#if defined(STM32F4) || defined(STM32F2)
#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
@@ -3750,5 +3892,4 @@
#endif /* STM32_HAL_LEGACY */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/Legacy/stm32l4xx_hal_can_legacy.h b/Inc/Legacy/stm32l4xx_hal_can_legacy.h
index b221774..e42dc3f 100644
--- a/Inc/Legacy/stm32l4xx_hal_can_legacy.h
+++ b/Inc/Legacy/stm32l4xx_hal_can_legacy.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -748,6 +747,3 @@
#endif
#endif /* __STM32L4xx_HAL_CAN_LEGACY_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32_assert_template.h b/Inc/stm32_assert_template.h
index 5370447..118bbf4 100644
--- a/Inc/stm32_assert_template.h
+++ b/Inc/stm32_assert_template.h
@@ -8,13 +8,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -52,6 +51,3 @@
#endif
#endif /* STM32_ASSERT_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal.h b/Inc/stm32l4xx_hal.h
index c1ba9cf..32a8e85 100644
--- a/Inc/stm32l4xx_hal.h
+++ b/Inc/stm32l4xx_hal.h
@@ -7,13 +7,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -725,5 +724,3 @@
#endif
#endif /* STM32L4xx_HAL_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_adc.h b/Inc/stm32l4xx_hal_adc.h
index 2a5eed2..84f0e16 100644
--- a/Inc/stm32l4xx_hal_adc.h
+++ b/Inc/stm32l4xx_hal_adc.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -1822,5 +1821,3 @@
#endif /* STM32L4xx_HAL_ADC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_adc_ex.h b/Inc/stm32l4xx_hal_adc_ex.h
index c6cf3e8..996ce0d 100644
--- a/Inc/stm32l4xx_hal_adc_ex.h
+++ b/Inc/stm32l4xx_hal_adc_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -1269,6 +1268,3 @@
#endif
#endif /* STM32L4xx_HAL_ADC_EX_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_can.h b/Inc/stm32l4xx_hal_can.h
index 8572b01..b02d18b 100644
--- a/Inc/stm32l4xx_hal_can.h
+++ b/Inc/stm32l4xx_hal_can.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -255,7 +254,7 @@
HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID = 0x08U, /*!< CAN Rx FIFO 1 message pending callback ID */
HAL_CAN_RX_FIFO1_FULL_CB_ID = 0x09U, /*!< CAN Rx FIFO 1 full callback ID */
HAL_CAN_SLEEP_CB_ID = 0x0AU, /*!< CAN Sleep callback ID */
- HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up fropm Rx msg callback ID */
+ HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up from Rx msg callback ID */
HAL_CAN_ERROR_CB_ID = 0x0CU, /*!< CAN Error callback ID */
HAL_CAN_MSPINIT_CB_ID = 0x0DU, /*!< CAN MspInit callback ID */
@@ -295,11 +294,11 @@
#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */
#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */
#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
-#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 1 transmit failure due to transmit error */
-#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
+#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 0 transmit failure due to transmit error */
+#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 1 transmit failure due to arbitration lost */
#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */
-#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
-#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 1 transmit failure due to transmit error */
+#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 2 transmit failure due to arbitration lost */
+#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 2 transmit failure due to transmit error */
#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */
#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */
#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */
@@ -845,6 +844,3 @@
#endif
#endif /* STM32L4xx_HAL_CAN_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_comp.h b/Inc/stm32l4xx_hal_comp.h
index 00d1817..9068e06 100644
--- a/Inc/stm32l4xx_hal_comp.h
+++ b/Inc/stm32l4xx_hal_comp.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -102,7 +101,7 @@
typedef struct __COMP_HandleTypeDef
#else
typedef struct
-#endif
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
{
COMP_TypeDef *Instance; /*!< Register base address */
COMP_InitTypeDef Init; /*!< COMP required parameters */
@@ -163,7 +162,7 @@
/**
* @}
*/
-#endif
+#endif /* COMP2 */
/** @defgroup COMP_PowerMode COMP power mode
* @{
@@ -200,14 +199,14 @@
#define COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */
#if defined(DAC_CHANNEL2_SUPPORT)
#define COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */
-#endif
+#endif /* DAC_CHANNEL2_SUPPORT */
#define COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2) */
#define COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2) */
#if defined(COMP_CSR_INMESEL_1)
#define COMP_INPUT_MINUS_IO3 ( COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO3 (pin PA0 for COMP1, pin PA2 for COMP2) */
#define COMP_INPUT_MINUS_IO4 (COMP_CSR_INMESEL_1 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO4 (pin PA4 for COMP1, pin PA4 for COMP2) */
#define COMP_INPUT_MINUS_IO5 (COMP_CSR_INMESEL_1 | COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO5 (pin PA5 for COMP1, pin PA5 for COMP2) */
-#endif
+#endif /* COMP_CSR_INMESEL_1 */
/**
* @}
*/
@@ -302,7 +301,7 @@
} while(0)
#else
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
-#endif
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
/**
* @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
@@ -591,7 +590,7 @@
#if defined(COMP2)
#define IS_COMP_WINDOWMODE(__WINDOWMODE__) (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE) || \
((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) )
-#endif
+#endif /* COMP2 */
#define IS_COMP_POWERMODE(__POWERMODE__) (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED) || \
((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED) || \
@@ -650,7 +649,7 @@
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2))
-#endif
+#endif /* COMP_CSR_INMESEL_1 && DAC_CHANNEL2_SUPPORT */
#define IS_COMP_HYSTERESIS(__HYSTERESIS__) (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE) || \
((__HYSTERESIS__) == COMP_HYSTERESIS_LOW) || \
@@ -812,5 +811,3 @@
#endif
#endif /* STM32L4xx_HAL_COMP_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_conf_template.h b/Inc/stm32l4xx_hal_conf_template.h
index 26fb6c4..7939703 100644
--- a/Inc/stm32l4xx_hal_conf_template.h
+++ b/Inc/stm32l4xx_hal_conf_template.h
@@ -8,13 +8,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -475,6 +474,3 @@
#endif
#endif /* STM32L4xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_cortex.h b/Inc/stm32l4xx_hal_cortex.h
index 64f140b..2aca387 100644
--- a/Inc/stm32l4xx_hal_cortex.h
+++ b/Inc/stm32l4xx_hal_cortex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -419,4 +418,3 @@
#endif /* STM32L4xx_HAL_CORTEX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_crc.h b/Inc/stm32l4xx_hal_crc.h
index 342427d..f4d9db4 100644
--- a/Inc/stm32l4xx_hal_crc.h
+++ b/Inc/stm32l4xx_hal_crc.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -60,19 +59,22 @@
{
uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
- X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
+ X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 +
+ X^4 + X^2+ X +1.
In that case, there is no need to set GeneratingPolynomial field.
- If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */
+ If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and
+ CRCLength fields must be set. */
uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
- 0xFFFFFFFF value. In that case, there is no need to set InitValue field.
- If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
+ 0xFFFFFFFF value. In that case, there is no need to set InitValue field. If
+ otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
- respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
- e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
- No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE. */
+ respectively equal to 7, 8, 16 or 32. This field is written in normal,
+ representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1
+ is written 0x65. No need to specify it if DefaultPolynomialUse is set to
+ DEFAULT_POLYNOMIAL_ENABLE. */
uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
Value can be either one of
@@ -87,14 +89,18 @@
uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
Can be either one of the following values
@arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion
- @arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
- @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
- @arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
+ @arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D
+ becomes 0x58D43CB2
+ @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion,
+ 0x1A2B3C4D becomes 0xD458B23C
+ @arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D
+ becomes 0xB23CD458 */
uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
Can be either
@arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion,
- @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */
+ @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted
+ into 0x22CC4488 */
} CRC_InitTypeDef;
/**
@@ -112,12 +118,16 @@
uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
Can be either
- @arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data)
- @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data)
- @arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bit data)
+ @arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes
+ (8-bit data)
+ @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of
+ half-words (16-bit data)
+ @arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words
+ (32-bit data)
- Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
- must occur if InputBufferFormat is not one of the three values listed above */
+ Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization
+ error must occur if InputBufferFormat is not one of the three values listed
+ above */
} CRC_HandleTypeDef;
/**
* @}
@@ -199,15 +209,6 @@
* @}
*/
-/** @defgroup CRC_Aliases CRC API aliases
- * @{
- */
-#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
-#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
-/**
- * @}
- */
-
/**
* @}
*/
@@ -267,7 +268,6 @@
#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
-
#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
@@ -340,5 +340,3 @@
#endif
#endif /* STM32L4xx_HAL_CRC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_crc_ex.h b/Inc/stm32l4xx_hal_crc_ex.h
index 11dad82..4fec05b 100644
--- a/Inc/stm32l4xx_hal_crc_ex.h
+++ b/Inc/stm32l4xx_hal_crc_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -149,5 +148,3 @@
#endif
#endif /* STM32L4xx_HAL_CRC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_cryp.h b/Inc/stm32l4xx_hal_cryp.h
index ed32dee..c5d642a 100644
--- a/Inc/stm32l4xx_hal_cryp.h
+++ b/Inc/stm32l4xx_hal_cryp.h
@@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -729,5 +727,3 @@
#endif
#endif /* STM32L4xx_HAL_CRYP_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_cryp_ex.h b/Inc/stm32l4xx_hal_cryp_ex.h
index e1ce98b..fa88a1e 100644
--- a/Inc/stm32l4xx_hal_cryp_ex.h
+++ b/Inc/stm32l4xx_hal_cryp_ex.h
@@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -125,5 +123,3 @@
#endif
#endif /* STM32L4xx_HAL_CRYP_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_dac.h b/Inc/stm32l4xx_hal_dac.h
index 94394da..0601fd2 100644
--- a/Inc/stm32l4xx_hal_dac.h
+++ b/Inc/stm32l4xx_hal_dac.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -609,5 +608,4 @@
#endif /*STM32L4xx_HAL_DAC_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_dac_ex.h b/Inc/stm32l4xx_hal_dac_ex.h
index afb64d9..b82d999 100644
--- a/Inc/stm32l4xx_hal_dac_ex.h
+++ b/Inc/stm32l4xx_hal_dac_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -287,4 +286,3 @@
#endif /*STM32L4xx_HAL_DAC_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_dcmi.h b/Inc/stm32l4xx_hal_dcmi.h
index e08ea91..fe78b6e 100644
--- a/Inc/stm32l4xx_hal_dcmi.h
+++ b/Inc/stm32l4xx_hal_dcmi.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -679,5 +678,3 @@
#endif
#endif /* STM32L4xx_HAL_DCMI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_def.h b/Inc/stm32l4xx_hal_def.h
index 055b1f1..4c55db6 100644
--- a/Inc/stm32l4xx_hal_def.h
+++ b/Inc/stm32l4xx_hal_def.h
@@ -7,13 +7,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -208,5 +207,3 @@
#endif
#endif /* STM32L4xx_HAL_DEF_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_dfsdm.h b/Inc/stm32l4xx_hal_dfsdm.h
index 40ca745..d2c0f9b 100644
--- a/Inc/stm32l4xx_hal_dfsdm.h
+++ b/Inc/stm32l4xx_hal_dfsdm.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -64,7 +63,7 @@
{
FunctionalState Activation; /*!< Output clock enable/disable */
uint32_t Selection; /*!< Output clock is system clock or audio clock.
- This parameter can be a value of @ref DFSDM_Channel_OuputClock */
+ This parameter can be a value of @ref DFSDM_Channel_OutputClock */
uint32_t Divider; /*!< Output clock divider.
This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
} DFSDM_Channel_OutputClockTypeDef;
@@ -308,11 +307,11 @@
* @{
*/
-/** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection
+/** @defgroup DFSDM_Channel_OutputClock DFSDM channel output clock selection
* @{
*/
-#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for ouput clock is system clock */
-#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */
+#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for output clock is system clock */
+#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for output clock is audio clock */
/**
* @}
*/
@@ -893,5 +892,3 @@
#endif
#endif /* STM32L4xx_HAL_DFSDM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_dfsdm_ex.h b/Inc/stm32l4xx_hal_dfsdm_ex.h
index d749fe5..0082399 100644
--- a/Inc/stm32l4xx_hal_dfsdm_ex.h
+++ b/Inc/stm32l4xx_hal_dfsdm_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -90,5 +89,3 @@
#endif
#endif /* STM32L4xx_HAL_DFSDM_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_dma.h b/Inc/stm32l4xx_hal_dma.h
index 9fc7226..f354c4f 100644
--- a/Inc/stm32l4xx_hal_dma.h
+++ b/Inc/stm32l4xx_hal_dma.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -860,5 +859,3 @@
#endif
#endif /* STM32L4xx_HAL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_dma2d.h b/Inc/stm32l4xx_hal_dma2d.h
index 82ed6f1..ea2af19 100644
--- a/Inc/stm32l4xx_hal_dma2d.h
+++ b/Inc/stm32l4xx_hal_dma2d.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -22,7 +21,7 @@
#define STM32L4xx_HAL_DMA2D_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -71,7 +70,8 @@
This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
uint32_t OutputOffset; /*!< Specifies the Offset value.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
+ This parameter must be a number between
+ Min_Data = 0x0000 and Max_Data = 0x3FFF. */
uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter.
This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
@@ -86,7 +86,8 @@
#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
- uint32_t LineOffsetMode; /*!< Configures how is expressed the line offset for the foreground, background and output.
+ uint32_t LineOffsetMode; /*!< Configures how is expressed the line offset
+ for the foreground, background and output.
This parameter can be one value of @ref DMA2D_Line_Offset_Mode. */
#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
@@ -99,7 +100,8 @@
typedef struct
{
uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
+ This parameter must be a number between
+ Min_Data = 0x0000 and Max_Data = 0x3FFF. */
uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode.
This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
@@ -107,9 +109,12 @@
uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode.
This parameter can be one value of @ref DMA2D_Alpha_Mode. */
- uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below.
- @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between
+ uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value
+ in case of A8 or A4 color mode.
+ This parameter must be a number between Min_Data = 0x00
+ and Max_Data = 0xFF except for the color modes detailed below.
+ @note In case of A8 or A4 color mode (ARGB),
+ this parameter must be a number between
Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
- InputAlpha[24:31] is the alpha value ALPHA[0:7]
- InputAlpha[16:23] is the red value RED[0:7]
@@ -135,46 +140,46 @@
HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */
HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */
-}HAL_DMA2D_StateTypeDef;
+} HAL_DMA2D_StateTypeDef;
/**
* @brief DMA2D handle Structure definition
*/
typedef struct __DMA2D_HandleTypeDef
{
- DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */
+ DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */
- DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */
+ DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */
- void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */
+ void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer complete callback. */
- void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */
+ void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer error callback. */
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
- void (* LineEventCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D line event callback. */
+ void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D line event callback. */
- void (* CLUTLoadingCpltCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D CLUT loading completion callback. */
+ void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D CLUT loading completion callback */
- void (* MspInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp Init callback. */
+ void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp Init callback. */
- void (* MspDeInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp DeInit callback. */
+ void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp DeInit callback. */
#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
- DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
+ DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
- HAL_LockTypeDef Lock; /*!< DMA2D lock. */
+ HAL_LockTypeDef Lock; /*!< DMA2D lock. */
- __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */
+ __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */
- __IO uint32_t ErrorCode; /*!< DMA2D error code. */
+ __IO uint32_t ErrorCode; /*!< DMA2D error code. */
} DMA2D_HandleTypeDef;
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
/**
* @brief HAL DMA2D Callback pointer definition
*/
-typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Pointer to a DMA2D common callback function */
+typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointer to a DMA2D common callback function */
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
/**
* @}
@@ -249,10 +254,10 @@
/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
* @{
*/
-#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */
+#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */
#define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */
#define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value
- with original alpha channel value */
+ with original alpha channel value */
/**
* @}
*/
@@ -335,14 +340,6 @@
* @}
*/
-/** @defgroup DMA2D_Aliases DMA2D API Aliases
- * @{
- */
-#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */
-/**
- * @}
- */
-
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
/**
* @brief HAL DMA2D common Callback ID enumeration definition
@@ -355,7 +352,7 @@
HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */
HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */
HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */
-}HAL_DMA2D_CallbackIDTypeDef;
+} HAL_DMA2D_CallbackIDTypeDef;
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
@@ -372,10 +369,10 @@
* @retval None
*/
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
-#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
+#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
}while(0)
#else
#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
@@ -481,12 +478,13 @@
/* Initialization and de-initialization functions *******************************/
HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
-HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
-void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
-void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d);
+void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d);
+void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID,
+ pDMA2D_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
@@ -500,16 +498,22 @@
*/
/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
-HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
-HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
-HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+ uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
+ uint32_t DstAddress, uint32_t Width, uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+ uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
+ uint32_t DstAddress, uint32_t Width, uint32_t Height);
HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
+ uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
+ uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
@@ -629,7 +633,8 @@
/** @defgroup DMA2D_Private_Macros DMA2D Private Macros
* @{
*/
-#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER) || ((LAYER) == DMA2D_FOREGROUND_LAYER))
+#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER)\
+ || ((LAYER) == DMA2D_FOREGROUND_LAYER))
#if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT)
#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
@@ -640,8 +645,10 @@
((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
#endif /* DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT */
-#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
- ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
+#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \
+ ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
+ ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || \
+ ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
@@ -649,11 +656,16 @@
#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
-#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
- ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
- ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \
- ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \
- ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \
+#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \
+ ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
+ ((INPUT_CM) == DMA2D_INPUT_RGB565) || \
+ ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
+ ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \
+ ((INPUT_CM) == DMA2D_INPUT_L8) || \
+ ((INPUT_CM) == DMA2D_INPUT_AL44) || \
+ ((INPUT_CM) == DMA2D_INPUT_AL88) || \
+ ((INPUT_CM) == DMA2D_INPUT_L4) || \
+ ((INPUT_CM) == DMA2D_INPUT_A8) || \
((INPUT_CM) == DMA2D_INPUT_A4))
#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
@@ -681,11 +693,11 @@
#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
- ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
- ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
+ ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
+ ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
- ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
- ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
+ ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
+ ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
/**
* @}
*/
@@ -705,6 +717,3 @@
#endif
#endif /* STM32L4xx_HAL_DMA2D_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_dma_ex.h b/Inc/stm32l4xx_hal_dma_ex.h
index 8e4c2ba..77b89df 100644
--- a/Inc/stm32l4xx_hal_dma_ex.h
+++ b/Inc/stm32l4xx_hal_dma_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -283,5 +282,3 @@
#endif
#endif /* STM32L4xx_HAL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_dsi.h b/Inc/stm32l4xx_hal_dsi.h
index 53f553c..a044589 100644
--- a/Inc/stm32l4xx_hal_dsi.h
+++ b/Inc/stm32l4xx_hal_dsi.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -40,6 +39,9 @@
*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup DSI_Exported_Types DSI Exported Types
+ * @{
+ */
/**
* @brief DSI Init Structure definition
*/
@@ -61,14 +63,14 @@
*/
typedef struct
{
- uint32_t PLLNDIV; /*!< PLL Loop Division Factor
- This parameter must be a value between 10 and 125 */
+ uint32_t PLLNDIV; /*!< PLL Loop Division Factor
+ This parameter must be a value between 10 and 125 */
- uint32_t PLLIDF; /*!< PLL Input Division Factor
- This parameter can be any value of @ref DSI_PLL_IDF */
+ uint32_t PLLIDF; /*!< PLL Input Division Factor
+ This parameter can be any value of @ref DSI_PLL_IDF */
- uint32_t PLLODF; /*!< PLL Output Division Factor
- This parameter can be any value of @ref DSI_PLL_ODF */
+ uint32_t PLLODF; /*!< PLL Output Division Factor
+ This parameter can be any value of @ref DSI_PLL_ODF */
} DSI_PLLInitTypeDef;
@@ -346,6 +348,9 @@
typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to an DSI callback function */
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
/** @defgroup DSI_Exported_Constants DSI Exported Constants
@@ -700,8 +705,8 @@
#define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE
#define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE
#define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE
-#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \
- DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \
+#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \
+ DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \
DSI_FLOW_CONTROL_EOTP_TX)
/**
* @}
@@ -841,18 +846,18 @@
* @{
*/
#define HAL_DSI_ERROR_NONE 0U
-#define HAL_DSI_ERROR_ACK 0x00000001U /*!< acknowledge errors */
-#define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */
-#define HAL_DSI_ERROR_TX 0x00000004U /*!< transmission error */
-#define HAL_DSI_ERROR_RX 0x00000008U /*!< reception error */
-#define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */
-#define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */
-#define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */
-#define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */
-#define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */
-#define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */
+#define HAL_DSI_ERROR_ACK 0x00000001U /*!< Acknowledge errors */
+#define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */
+#define HAL_DSI_ERROR_TX 0x00000004U /*!< Transmission error */
+#define HAL_DSI_ERROR_RX 0x00000008U /*!< Reception error */
+#define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */
+#define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */
+#define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */
+#define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */
+#define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */
+#define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */
#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
-#define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /*!< DSI Invalid Callback error */
+#define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /*!< DSI Invalid Callback error */
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
/**
* @}
@@ -912,6 +917,7 @@
* @}
*/
+
/**
* @}
*/
@@ -955,11 +961,11 @@
* @retval None.
*/
#define __HAL_DSI_DISABLE(__HANDLE__) do { \
- __IO uint32_t tmpreg = 0x00U; \
- CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
- /* Delay after an DSI Host disabling */ \
- tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
- UNUSED(tmpreg); \
+ __IO uint32_t tmpreg = 0x00U; \
+ CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
+ /* Delay after an DSI Host disabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
+ UNUSED(tmpreg); \
} while(0U)
/**
@@ -968,11 +974,11 @@
* @retval None.
*/
#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
- /* Delay after an DSI warpper enabling */ \
- tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
- UNUSED(tmpreg); \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+ /* Delay after an DSI warpper enabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+ UNUSED(tmpreg); \
} while(0U)
/**
@@ -981,11 +987,11 @@
* @retval None.
*/
#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \
- __IO uint32_t tmpreg = 0x00U; \
- CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
- /* Delay after an DSI warpper disabling*/ \
- tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
- UNUSED(tmpreg); \
+ __IO uint32_t tmpreg = 0x00U; \
+ CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+ /* Delay after an DSI warpper disabling*/ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+ UNUSED(tmpreg); \
} while(0U)
/**
@@ -994,11 +1000,11 @@
* @retval None.
*/
#define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
- /* Delay after an DSI PLL enabling */ \
- tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
- UNUSED(tmpreg); \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+ /* Delay after an DSI PLL enabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+ UNUSED(tmpreg); \
} while(0U)
/**
@@ -1007,11 +1013,11 @@
* @retval None.
*/
#define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \
- __IO uint32_t tmpreg = 0x00U; \
- CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
- /* Delay after an DSI PLL disabling */ \
- tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
- UNUSED(tmpreg); \
+ __IO uint32_t tmpreg = 0x00U; \
+ CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+ /* Delay after an DSI PLL disabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+ UNUSED(tmpreg); \
} while(0U)
/**
@@ -1033,11 +1039,11 @@
* @retval None.
*/
#define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \
- __IO uint32_t tmpreg = 0x00U; \
- CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
- /* Delay after an DSI regulator disabling */ \
- tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
- UNUSED(tmpreg); \
+ __IO uint32_t tmpreg = 0x00U; \
+ CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
+ /* Delay after an DSI regulator disabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
+ UNUSED(tmpreg); \
} while(0U)
/**
@@ -1121,23 +1127,41 @@
/** @defgroup DSI_Exported_Functions DSI Exported Functions
* @{
*/
+/** @defgroup DSI_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ * @{
+ */
HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit);
HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi);
void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi);
void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi);
-
-void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
-void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
-void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
-void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
-
+HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID,
pDSI_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+/** @defgroup DSI_Group2 IO operation functions
+ * @brief IO operation functions
+ * @{
+ */
+void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
+void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
+void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
+void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ * @{
+ */
HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);
HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg);
HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg);
@@ -1190,40 +1214,28 @@
HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State);
HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State);
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Group4 Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
+ * @{
+ */
uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);
-HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
+
+/**
+ * @}
+ */
+
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
-/** @defgroup DSI_Private_Types DSI Private Types
- * @{
- */
-
-/**
- * @}
- */
-
/* Private defines -----------------------------------------------------------*/
-/** @defgroup DSI_Private_Defines DSI Private Defines
- * @{
- */
-
-/**
- * @}
- */
-
/* Private variables ---------------------------------------------------------*/
-/** @defgroup DSI_Private_Variables DSI Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
/* Private constants ---------------------------------------------------------*/
/** @defgroup DSI_Private_Constants DSI Private Constants
* @{
@@ -1249,45 +1261,73 @@
((ODF) == DSI_PLL_OUT_DIV2) || \
((ODF) == DSI_PLL_OUT_DIV4) || \
((ODF) == DSI_PLL_OUT_DIV8))
-#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
-#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES))
+#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE)\
+ || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
+#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE)\
+ || ((NumberOfLanes) == DSI_TWO_DATA_LANES))
#define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)
#define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U)
-#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
-#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
-#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
-#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
+#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE)\
+ || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
+#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH)\
+ || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
+#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH)\
+ || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
+#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH)\
+ || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \
((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \
((VideoModeType) == DSI_VID_MODE_BURST))
-#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT))
+#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL)\
+ || ((ColorMode) == DSI_COLOR_MODE_EIGHT))
#define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF))
-#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE))
+#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE)\
+ || ((LPCommand) == DSI_LP_COMMAND_ENABLE))
#define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE))
#define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE))
-#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE))
+#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE)\
+ || ((LPVActive) == DSI_LP_VACT_ENABLE))
#define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE))
#define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE))
-#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
-#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
+#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE)\
+ || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
+#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE)\
+ || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
#define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL))
-#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE))
-#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE))
-#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING))
-#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
-#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
-#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
-#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
-#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
-#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
-#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
-#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
-#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE))
-#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
-#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
-#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
-#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE))
-#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
+#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE)\
+ || ((TEPolarity) == DSI_TE_FALLING_EDGE))
+#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE)\
+ || ((AutomaticRefresh) == DSI_AR_ENABLE))
+#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING)\
+ || ((VSPolarity) == DSI_VSYNC_RISING))
+#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE)\
+ || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
+#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE)\
+ || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
+#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE)\
+ || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
+#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE)\
+ || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
+#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE)\
+ || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
+#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE)\
+ || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
+#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE)\
+ || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
+#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE)\
+ || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
+#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE)\
+ || ((LP_GLW) == DSI_LP_GLW_ENABLE))
+#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE)\
+ || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
+#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE)\
+ || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
+#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE)\
+ || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
+#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE)\
+ || ((LP_DLW) == DSI_LP_DLW_ENABLE))
+#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE)\
+ || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
#define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \
((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \
((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \
@@ -1299,10 +1339,14 @@
((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \
((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \
((MODE) == DSI_GEN_SHORT_PKT_READ_P2))
-#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY))
+#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || \
+ ((CommDelay) == DSI_SLEW_RATE_LPTX) || \
+ ((CommDelay) == DSI_HS_DELAY))
#define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES))
-#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL))
-#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))
+#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS)\
+ || ((CustomLane) == DSI_INVERT_HS_SIGNAL))
+#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || \
+ ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))
#define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \
((Timing) == DSI_TLPX_CLK ) || \
((Timing) == DSI_THS_EXIT ) || \
@@ -1317,24 +1361,6 @@
* @}
*/
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DSI_Private_Functions DSI Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
/**
* @}
*/
@@ -1349,5 +1375,3 @@
#endif
#endif /* STM32L4xx_HAL_DSI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_exti.h b/Inc/stm32l4xx_hal_exti.h
index 67d624d..aa70f20 100644
--- a/Inc/stm32l4xx_hal_exti.h
+++ b/Inc/stm32l4xx_hal_exti.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -857,4 +856,3 @@
#endif /* STM32L4xx_HAL_EXTI_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_firewall.h b/Inc/stm32l4xx_hal_firewall.h
index 59d6030..010f3d4 100644
--- a/Inc/stm32l4xx_hal_firewall.h
+++ b/Inc/stm32l4xx_hal_firewall.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -350,5 +349,3 @@
#endif
#endif /* STM32L4xx_HAL_FIREWALL_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_flash.h b/Inc/stm32l4xx_hal_flash.h
index b96ba8c..663a92d 100644
--- a/Inc/stm32l4xx_hal_flash.h
+++ b/Inc/stm32l4xx_hal_flash.h
@@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -1027,4 +1025,3 @@
#endif /* STM32L4xx_HAL_FLASH_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_flash_ex.h b/Inc/stm32l4xx_hal_flash_ex.h
index 7eec0e9..36ec888 100644
--- a/Inc/stm32l4xx_hal_flash_ex.h
+++ b/Inc/stm32l4xx_hal_flash_ex.h
@@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -125,4 +123,3 @@
#endif /* STM32L4xx_HAL_FLASH_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_flash_ramfunc.h b/Inc/stm32l4xx_hal_flash_ramfunc.h
index 9360335..b5852fc 100644
--- a/Inc/stm32l4xx_hal_flash_ramfunc.h
+++ b/Inc/stm32l4xx_hal_flash_ramfunc.h
@@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -74,4 +72,3 @@
#endif /* STM32L4xx_FLASH_RAMFUNC_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_gfxmmu.h b/Inc/stm32l4xx_hal_gfxmmu.h
index 289b450..2f11932 100644
--- a/Inc/stm32l4xx_hal_gfxmmu.h
+++ b/Inc/stm32l4xx_hal_gfxmmu.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -71,7 +70,7 @@
FunctionalState Activation; /*!< Interrupts enable/disable */
uint32_t UsedInterrupts; /*!< Interrupts used.
This parameter can be a values combination of @ref GFXMMU_Interrupts.
- @note: Usefull only when interrupts are enabled. */
+ @note: Useful only when interrupts are enabled. */
}GFXMMU_InterruptsTypeDef;
/**
@@ -332,4 +331,3 @@
#endif /* STM32L4xx_HAL_GFXMMU_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_gpio.h b/Inc/stm32l4xx_hal_gpio.h
index 074a268..aaa7b6d 100644
--- a/Inc/stm32l4xx_hal_gpio.h
+++ b/Inc/stm32l4xx_hal_gpio.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -60,7 +59,7 @@
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
-}GPIO_InitTypeDef;
+} GPIO_InitTypeDef;
/**
* @brief GPIO Bit SET and Bit RESET enumeration
@@ -69,7 +68,7 @@
{
GPIO_PIN_RESET = 0U,
GPIO_PIN_SET
-}GPIO_PinState;
+} GPIO_PinState;
/**
* @}
*/
@@ -99,34 +98,33 @@
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
-#define GPIO_PIN_MASK (0x0000FFFFu) /* PIN mask for assert test */
+#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
/**
* @}
*/
/** @defgroup GPIO_mode GPIO mode
* @brief GPIO Configuration Mode
- * Elements values convention: 0xX0yz00YZ
- * - X : GPIO mode or EXTI Mode
- * - y : External IT or Event trigger detection
- * - z : IO configuration on External IT or Event
- * - Y : Output type (Push Pull or Open Drain)
- * - Z : IO Direction mode (Input, Output, Alternate or Analog)
+ * Elements values convention: 0x00WX00YZ
+ * - W : EXTI trigger detection on 3 bits
+ * - X : EXTI mode (IT or Event) on 2 bits
+ * - Y : Output type (Push Pull or Open Drain) on 1 bit
+ * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
* @{
*/
-#define GPIO_MODE_INPUT (0x00000000u) /*!< Input Floating Mode */
-#define GPIO_MODE_OUTPUT_PP (0x00000001u) /*!< Output Push Pull Mode */
-#define GPIO_MODE_OUTPUT_OD (0x00000011u) /*!< Output Open Drain Mode */
-#define GPIO_MODE_AF_PP (0x00000002u) /*!< Alternate Function Push Pull Mode */
-#define GPIO_MODE_AF_OD (0x00000012u) /*!< Alternate Function Open Drain Mode */
-#define GPIO_MODE_ANALOG (0x00000003u) /*!< Analog Mode */
-#define GPIO_MODE_ANALOG_ADC_CONTROL (0x0000000Bu) /*!< Analog Mode for ADC conversion */
-#define GPIO_MODE_IT_RISING (0x10110000u) /*!< External Interrupt Mode with Rising edge trigger detection */
-#define GPIO_MODE_IT_FALLING (0x10210000u) /*!< External Interrupt Mode with Falling edge trigger detection */
-#define GPIO_MODE_IT_RISING_FALLING (0x10310000u) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define GPIO_MODE_EVT_RISING (0x10120000u) /*!< External Event Mode with Rising edge trigger detection */
-#define GPIO_MODE_EVT_FALLING (0x10220000u) /*!< External Event Mode with Falling edge trigger detection */
-#define GPIO_MODE_EVT_RISING_FALLING (0x10320000u) /*!< External Event Mode with Rising/Falling edge trigger detection */
+#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
+#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */
+#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */
+#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */
+#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */
+#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
+#define GPIO_MODE_ANALOG_ADC_CONTROL (MODE_ANALOG | 0x8uL) /*!< Analog Mode for ADC conversion (0x0000000Bu)*/
+#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */
+#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */
+#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
@@ -135,21 +133,21 @@
* @brief GPIO Output Maximum frequency
* @{
*/
-#define GPIO_SPEED_FREQ_LOW (0x00000000u) /*!< range up to 5 MHz, please refer to the product datasheet */
-#define GPIO_SPEED_FREQ_MEDIUM (0x00000001u) /*!< range 5 MHz to 25 MHz, please refer to the product datasheet */
-#define GPIO_SPEED_FREQ_HIGH (0x00000002u) /*!< range 25 MHz to 50 MHz, please refer to the product datasheet */
-#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003u) /*!< range 50 MHz to 80 MHz, please refer to the product datasheet */
+#define GPIO_SPEED_FREQ_LOW 0x00000000u /*!< Low speed */
+#define GPIO_SPEED_FREQ_MEDIUM 0x00000001u /*!< Medium speed */
+#define GPIO_SPEED_FREQ_HIGH 0x00000002u /*!< High speed */
+#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003u /*!< Very high speed */
/**
* @}
*/
- /** @defgroup GPIO_pull GPIO pull
- * @brief GPIO Pull-Up or Pull-Down Activation
- * @{
- */
-#define GPIO_NOPULL (0x00000000u) /*!< No Pull-up or Pull-down activation */
-#define GPIO_PULLUP (0x00000001u) /*!< Pull-up activation */
-#define GPIO_PULLDOWN (0x00000002u) /*!< Pull-down activation */
+/** @defgroup GPIO_pull GPIO pull
+ * @brief GPIO Pull-Up or Pull-Down Activation
+ * @{
+ */
+#define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */
+#define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */
+#define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */
/**
* @}
*/
@@ -208,6 +206,32 @@
*/
/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Constants GPIO Private Constants
+ * @{
+ */
+#define GPIO_MODE_Pos 0u
+#define GPIO_MODE (0x3uL << GPIO_MODE_Pos)
+#define MODE_INPUT (0x0uL << GPIO_MODE_Pos)
+#define MODE_OUTPUT (0x1uL << GPIO_MODE_Pos)
+#define MODE_AF (0x2uL << GPIO_MODE_Pos)
+#define MODE_ANALOG (0x3uL << GPIO_MODE_Pos)
+#define OUTPUT_TYPE_Pos 4u
+#define OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos)
+#define OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos)
+#define OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos)
+#define EXTI_MODE_Pos 16u
+#define EXTI_MODE (0x3uL << EXTI_MODE_Pos)
+#define EXTI_IT (0x1uL << EXTI_MODE_Pos)
+#define EXTI_EVT (0x2uL << EXTI_MODE_Pos)
+#define TRIGGER_MODE_Pos 20u
+#define TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos)
+#define TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos)
+#define TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos)
+
+/**
+ * @}
+ */
+
/** @addtogroup GPIO_Private_Macros GPIO Private Macros
* @{
*/
@@ -297,4 +321,3 @@
#endif /* STM32L4xx_HAL_GPIO_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_gpio_ex.h b/Inc/stm32l4xx_hal_gpio_ex.h
index 3d01e60..550ae96 100644
--- a/Inc/stm32l4xx_hal_gpio_ex.h
+++ b/Inc/stm32l4xx_hal_gpio_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -1058,4 +1057,3 @@
#endif /* STM32L4xx_HAL_GPIO_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_hash.h b/Inc/stm32l4xx_hal_hash.h
index 005e5ea..867fb0c 100644
--- a/Inc/stm32l4xx_hal_hash.h
+++ b/Inc/stm32l4xx_hal_hash.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -22,7 +21,7 @@
#define STM32L4xx_HAL_HASH_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -51,7 +50,7 @@
uint32_t KeySize; /*!< The key size is used only in HMAC operation. */
- uint8_t* pKey; /*!< The key is used only in HMAC operation. */
+ uint8_t *pKey; /*!< The key is used only in HMAC operation. */
} HASH_InitTypeDef;
@@ -66,7 +65,7 @@
HAL_HASH_STATE_TIMEOUT = 0x06U, /*!< Timeout state */
HAL_HASH_STATE_ERROR = 0x07U, /*!< Error state */
HAL_HASH_STATE_SUSPENDED = 0x08U /*!< Suspended state */
-}HAL_HASH_StateTypeDef;
+} HAL_HASH_StateTypeDef;
/**
* @brief HAL phase structures definition
@@ -81,7 +80,7 @@
(step 2 consists in entering the message text) */
HAL_HASH_PHASE_HMAC_STEP_3 = 0x05U /*!< HASH peripheral is in HMAC step 3 processing phase
(step 3 consists in entering the outer hash function key) */
-}HAL_HASH_PhaseTypeDef;
+} HAL_HASH_PhaseTypeDef;
/**
* @brief HAL HASH mode suspend definitions
@@ -90,7 +89,7 @@
{
HAL_HASH_SUSPEND_NONE = 0x00U, /*!< HASH peripheral suspension not requested */
HAL_HASH_SUSPEND = 0x01U /*!< HASH peripheral suspension is requested */
-}HAL_HASH_SuspendTypeDef;
+} HAL_HASH_SuspendTypeDef;
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
/**
@@ -103,7 +102,7 @@
HAL_HASH_INPUTCPLT_CB_ID = 0x02U, /*!< HASH input completion callback ID */
HAL_HASH_DGSTCPLT_CB_ID = 0x03U, /*!< HASH digest computation completion callback ID */
HAL_HASH_ERROR_CB_ID = 0x04U, /*!< HASH error callback ID */
-}HAL_HASH_CallbackIDTypeDef;
+} HAL_HASH_CallbackIDTypeDef;
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
@@ -155,15 +154,15 @@
__IO uint32_t Accumulation; /*!< HASH multi buffers accumulation flag */
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
- void (* InCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH input completion callback */
+ void (* InCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH input completion callback */
- void (* DgstCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH digest computation completion callback */
+ void (* DgstCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH digest computation completion callback */
- void (* ErrorCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH error callback */
+ void (* ErrorCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH error callback */
- void (* MspInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp Init callback */
+ void (* MspInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp Init callback */
- void (* MspDeInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp DeInit callback */
+ void (* MspDeInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp DeInit callback */
#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
} HASH_HandleTypeDef;
@@ -172,7 +171,7 @@
/**
* @brief HAL HASH Callback pointer definition
*/
-typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer to a HASH common callback functions */
+typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef *hhash); /*!< pointer to a HASH common callback functions */
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
/**
@@ -247,13 +246,6 @@
/**
* @}
*/
-/** @defgroup HASH_alias HASH API alias
- * @{
- */
-#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< HAL_HASHEx_IRQHandler() is re-directed to HAL_HASH_IRQHandler() for compatibility with legacy code */
-/**
- * @}
- */
/** @defgroup HASH_Error_Definition HASH Error Definition
* @{
@@ -288,8 +280,8 @@
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? \
- ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
- ((HASH->SR & (__FLAG__)) == (__FLAG__)) )
+ ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
+ ((HASH->SR & (__FLAG__)) == (__FLAG__)) )
/** @brief Clear the specified HASH flag.
@@ -366,7 +358,7 @@
* @brief Set the number of valid bits in the last word written in data register DIN.
* @param __SIZE__ size in bytes of last data written in Data register.
* @retval None
-*/
+ */
#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U))
/**
@@ -389,8 +381,8 @@
* @retval Digest length
*/
#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20U : \
- ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28U : \
- ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32U : 16U ) ) )
+ ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28U : \
+ ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32U : 16U ) ) )
/**
* @brief Return number of words already pushed in the FIFO.
* @retval Number of words already pushed in the FIFO
@@ -424,7 +416,8 @@
* @param __SIZE__ input data buffer size.
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
*/
-#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4U) == 0U))
+#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET)\
+ || (((__SIZE__) % 4U) == 0U))
/**
* @brief Ensure that handle phase is set to HASH processing.
* @param __HANDLE__ HASH handle.
@@ -467,7 +460,8 @@
void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID,
+ pHASH_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
@@ -482,12 +476,16 @@
/* HASH processing using polling *********************************************/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
/**
@@ -499,12 +497,16 @@
*/
/* HASH processing using IT **************************************************/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
/**
* @}
@@ -516,9 +518,9 @@
/* HASH processing using DMA *************************************************/
HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
/**
* @}
@@ -529,8 +531,10 @@
*/
/* HASH-MAC processing using polling *****************************************/
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout);
/**
* @}
@@ -540,8 +544,10 @@
* @{
*/
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
/**
* @}
@@ -567,8 +573,8 @@
/* Peripheral State methods **************************************************/
HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash);
-void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
-void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
+void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
+void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
@@ -588,14 +594,18 @@
*/
/* Private functions */
-HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Algorithm);
HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
-HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout, uint32_t Algorithm);
+HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Algorithm);
HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
/**
@@ -618,4 +628,3 @@
#endif /* STM32L4xx_HAL_HASH_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_hash_ex.h b/Inc/stm32l4xx_hal_hash_ex.h
index 618e402..8df276a 100644
--- a/Inc/stm32l4xx_hal_hash_ex.h
+++ b/Inc/stm32l4xx_hal_hash_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -22,7 +21,7 @@
#define STM32L4xx_HAL_HASH_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -51,12 +50,16 @@
* @{
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
/**
* @}
@@ -66,12 +69,16 @@
* @{
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
/**
* @}
@@ -81,9 +88,9 @@
* @{
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
/**
* @}
@@ -92,8 +99,10 @@
/** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
* @{
*/
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
/**
* @}
*/
@@ -102,8 +111,10 @@
* @{
*/
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
/**
* @}
@@ -162,4 +173,3 @@
#endif /* STM32L4xx_HAL_HASH_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_hcd.h b/Inc/stm32l4xx_hal_hcd.h
index da363f7..e9714fe 100644
--- a/Inc/stm32l4xx_hal_hcd.h
+++ b/Inc/stm32l4xx_hal_hcd.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -110,10 +109,16 @@
*/
#define HCD_SPEED_FULL USBH_FSLS_SPEED
#define HCD_SPEED_LOW USBH_FSLS_SPEED
+/**
+ * @}
+ */
+/** @defgroup HCD_Device_Speed HCD Device Speed
+ * @{
+ */
+#define HCD_DEVICE_SPEED_HIGH 0U
#define HCD_DEVICE_SPEED_FULL 1U
#define HCD_DEVICE_SPEED_LOW 2U
-
/**
* @}
*/
@@ -151,7 +156,8 @@
#define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\
+ & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
@@ -294,11 +300,11 @@
/* Private functions prototypes ----------------------------------------------*/
/**
- * @}
- */
+ * @}
+ */
/**
- * @}
- */
+ * @}
+ */
#endif /* defined (USB_OTG_FS) */
#ifdef __cplusplus
@@ -306,5 +312,3 @@
#endif
#endif /* STM32L4xx_HAL_HCD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_i2c.h b/Inc/stm32l4xx_hal_i2c.h
index 128a11b..f291048 100644
--- a/Inc/stm32l4xx_hal_i2c.h
+++ b/Inc/stm32l4xx_hal_i2c.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -48,29 +47,30 @@
typedef struct
{
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
- This parameter calculated by referring to I2C initialization
- section in Reference manual */
+ This parameter calculated by referring to I2C initialization section
+ in Reference manual */
uint32_t OwnAddress1; /*!< Specifies the first device own address.
- This parameter can be a 7-bit or 10-bit address. */
+ This parameter can be a 7-bit or 10-bit address. */
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
- This parameter can be a value of @ref I2C_ADDRESSING_MODE */
+ This parameter can be a value of @ref I2C_ADDRESSING_MODE */
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
- This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
+ This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
- This parameter can be a 7-bit address. */
+ This parameter can be a 7-bit address. */
- uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
- This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
+ uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing
+ mode is selected.
+ This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
- This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
+ This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
- This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
+ This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
} I2C_InitTypeDef;
@@ -200,7 +200,8 @@
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
- HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */
+ HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+ /*!< I2C transfer IRQ handler function pointer */
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
@@ -217,20 +218,32 @@
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */
- void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */
- void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */
- void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */
- void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */
- void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */
- void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */
- void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */
- void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */
+ void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+ /*!< I2C Master Tx Transfer completed callback */
+ void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+ /*!< I2C Master Rx Transfer completed callback */
+ void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+ /*!< I2C Slave Tx Transfer completed callback */
+ void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+ /*!< I2C Slave Rx Transfer completed callback */
+ void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+ /*!< I2C Listen Complete callback */
+ void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+ /*!< I2C Memory Tx Transfer completed callback */
+ void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+ /*!< I2C Memory Rx Transfer completed callback */
+ void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
+ /*!< I2C Error callback */
+ void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+ /*!< I2C Abort callback */
- void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */
+ void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
+ /*!< I2C Slave Address Match callback */
- void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */
- void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */
+ void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
+ /*!< I2C Msp Init callback */
+ void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
+ /*!< I2C Msp DeInit callback */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
} I2C_HandleTypeDef;
@@ -259,8 +272,11 @@
/**
* @brief HAL I2C Callback pointer definition
*/
-typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
-typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
+typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
+/*!< pointer to an I2C callback function */
+typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
+ uint16_t AddrMatchCode);
+/*!< pointer to an I2C Address Match callback function */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
@@ -440,14 +456,14 @@
* @retval None
*/
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_I2C_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_I2C_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
-#endif
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/** @brief Enable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
@@ -542,26 +558,27 @@
*
* @retval None
*/
-#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
- : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
+ ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
+ ((__HANDLE__)->Instance->ICR = (__FLAG__)))
/** @brief Enable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
-#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Disable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
-#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
-#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
+#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
/**
* @}
*/
@@ -601,12 +618,14 @@
*/
/* IO operation functions ****************************************************/
/******* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
- uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
@@ -757,10 +776,14 @@
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
- (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+ (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
+ I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
+ I2C_CR2_RD_WRN)))
-#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))
-#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))
+#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
+ >> 16U))
+#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
+ >> 16U))
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
@@ -772,10 +795,15 @@
(uint16_t)(0xFF00U))) >> 8U)))
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
-#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
- (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
+ (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
+ (~I2C_CR2_RD_WRN)) : \
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
+ (I2C_CR2_ADD10) | (I2C_CR2_START)) & \
+ (~I2C_CR2_RD_WRN)))
-#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
+#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
/**
@@ -805,5 +833,3 @@
#endif /* STM32L4xx_HAL_I2C_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_i2c_ex.h b/Inc/stm32l4xx_hal_i2c_ex.h
index 14b4381..15ed69a 100644
--- a/Inc/stm32l4xx_hal_i2c_ex.h
+++ b/Inc/stm32l4xx_hal_i2c_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -63,19 +62,19 @@
#else
#define I2C_FASTMODEPLUS_PB8 (uint32_t)(0x00000010U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB8 not supported */
#define I2C_FASTMODEPLUS_PB9 (uint32_t)(0x00000012U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB9 not supported */
-#endif
+#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
#if defined(SYSCFG_CFGR1_I2C2_FMP)
#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
#else
#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */
-#endif
+#endif /* SYSCFG_CFGR1_I2C2_FMP */
#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
#if defined(SYSCFG_CFGR1_I2C4_FMP)
#define I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
#else
#define I2C_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported */
-#endif
+#endif /* SYSCFG_CFGR1_I2C4_FMP */
/**
* @}
*/
@@ -98,7 +97,7 @@
* @{
*/
-/** @addtogroup I2CEx_Exported_Functions_Group1 I2C Extended Filter Mode Functions
+/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
* @{
*/
/* Peripheral Control functions ************************************************/
@@ -108,7 +107,7 @@
* @}
*/
-/** @addtogroup I2CEx_Exported_Functions_Group2 I2C Extended WakeUp Mode Functions
+/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
* @{
*/
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
@@ -117,7 +116,7 @@
* @}
*/
-/** @addtogroup I2CEx_Exported_Functions_Group3 I2C Extended FastModePlus Functions
+/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
* @{
*/
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
@@ -126,7 +125,6 @@
* @}
*/
-
/**
* @}
*/
@@ -184,5 +182,3 @@
#endif
#endif /* STM32L4xx_HAL_I2C_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_irda.h b/Inc/stm32l4xx_hal_irda.h
index c362909..9ec1b76 100644
--- a/Inc/stm32l4xx_hal_irda.h
+++ b/Inc/stm32l4xx_hal_irda.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -80,7 +79,8 @@
/**
* @brief HAL IRDA State definition
- * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState (see @ref IRDA_State_Definition).
+ * @note HAL IRDA State value is a combination of 2 different substates:
+ * gState and RxState (see @ref IRDA_State_Definition).
* - gState contains IRDA state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
@@ -145,7 +145,7 @@
IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
- uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
+ const uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
@@ -250,7 +250,8 @@
Value is allowed for RxState only */
#define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
Not to be used for neither gState nor RxState.
- Value is result of combination (Or) between gState and RxState values */
+ Value is result of combination (Or) between
+ gState and RxState values */
#define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
Value is allowed for gState only */
#define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error
@@ -262,15 +263,15 @@
/** @defgroup IRDA_Error_Definition IRDA Error Code Definition
* @{
*/
-#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
-#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
-#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */
-#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
-#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
-#define HAL_IRDA_ERROR_BUSY ((uint32_t)0x00000020U) /*!< Busy Error */
+#define HAL_IRDA_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_IRDA_ERROR_PE (0x00000001U) /*!< Parity error */
+#define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */
+#define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */
+#define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */
+#define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-#define HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
+#define HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/**
* @}
@@ -306,7 +307,7 @@
*/
#if defined(USART_PRESC_PRESCALER)
-/** @defgroup IRDA_ClockPrescaler Clock Prescaler
+/** @defgroup IRDA_ClockPrescaler IRDA Clock Prescaler
* @{
*/
#define IRDA_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */
@@ -583,9 +584,14 @@
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
+#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
+ ((__HANDLE__)->Instance->CR1 |= (1U << \
+ ((__INTERRUPT__) & IRDA_IT_MASK))):\
+ ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
+ ((__HANDLE__)->Instance->CR2 |= (1U << \
+ ((__INTERRUPT__) & IRDA_IT_MASK))):\
+ ((__HANDLE__)->Instance->CR3 |= (1U << \
+ ((__INTERRUPT__) & IRDA_IT_MASK))))
/** @brief Disable the specified IRDA interrupt.
* @param __HANDLE__ specifies the IRDA Handle.
@@ -599,10 +605,14 @@
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
-
+#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
+ ((__HANDLE__)->Instance->CR1 &= ~ (1U << \
+ ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
+ ((__HANDLE__)->Instance->CR2 &= ~ (1U << \
+ ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U << \
+ ((__INTERRUPT__) & IRDA_IT_MASK))))
/** @brief Check whether the specified IRDA interrupt has occurred or not.
* @param __HANDLE__ specifies the IRDA Handle.
@@ -618,8 +628,8 @@
* @arg @ref IRDA_IT_PE Parity Error interrupt
* @retval The new state of __IT__ (SET or RESET).
*/
-#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
- & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)
+#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) \
+ ((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified IRDA interrupt source is enabled or not.
* @param __HANDLE__ specifies the IRDA Handle.
@@ -633,9 +643,10 @@
* @arg @ref IRDA_IT_PE Parity Error interrupt
* @retval The new state of __IT__ (SET or RESET).
*/
-#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
- (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
- (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
+#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ ((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__) \
+ & IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3)) \
+ & (0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the IRDA Handle.
@@ -830,11 +841,11 @@
*/
/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
@@ -893,4 +904,3 @@
#endif /* STM32L4xx_HAL_IRDA_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_irda_ex.h b/Inc/stm32l4xx_hal_irda_ex.h
index 0c10788..327a189 100644
--- a/Inc/stm32l4xx_hal_irda_ex.h
+++ b/Inc/stm32l4xx_hal_irda_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -32,7 +31,8 @@
* @{
*/
-/** @addtogroup IRDAEx
+/** @defgroup IRDAEx IRDAEx
+ * @brief IRDA Extended HAL module driver
* @{
*/
@@ -400,6 +400,7 @@
} while(0)
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx ||
* STM32L496xx || STM32L4A6xx ||
+ * STM32L4P5xx || STM32L4Q5xx ||
* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx
*/
@@ -476,4 +477,3 @@
#endif /* STM32L4xx_HAL_IRDA_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_iwdg.h b/Inc/stm32l4xx_hal_iwdg.h
index 23d4902..e9061b8 100644
--- a/Inc/stm32l4xx_hal_iwdg.h
+++ b/Inc/stm32l4xx_hal_iwdg.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -87,7 +86,6 @@
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
-
/**
* @}
*/
@@ -100,7 +98,6 @@
* @}
*/
-
/**
* @}
*/
@@ -138,7 +135,7 @@
* @{
*/
/* Initialization/Start functions ********************************************/
-HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
@@ -147,7 +144,7 @@
* @{
*/
/* I/O operation functions ****************************************************/
-HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
@@ -238,5 +235,3 @@
#endif
#endif /* STM32L4xx_HAL_IWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_lcd.h b/Inc/stm32l4xx_hal_lcd.h
index 2e9d3a8..8d1c8da 100644
--- a/Inc/stm32l4xx_hal_lcd.h
+++ b/Inc/stm32l4xx_hal_lcd.h
@@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -767,5 +765,3 @@
#endif
#endif /* STM32L4xx_HAL_LCD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_lptim.h b/Inc/stm32l4xx_hal_lptim.h
index db8d2e7..9ce6ef2 100644
--- a/Inc/stm32l4xx_hal_lptim.h
+++ b/Inc/stm32l4xx_hal_lptim.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -98,38 +97,40 @@
*/
typedef struct
{
- LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */
+ LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */
- LPTIM_ULPClockConfigTypeDef UltraLowPowerClock; /*!< Specifies the Ultra Low Power clock parameters */
+ LPTIM_ULPClockConfigTypeDef UltraLowPowerClock;/*!< Specifies the Ultra Low Power clock parameters */
- LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */
+ LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */
- uint32_t OutputPolarity; /*!< Specifies the Output polarity.
- This parameter can be a value of @ref LPTIM_Output_Polarity */
+ uint32_t OutputPolarity; /*!< Specifies the Output polarity.
+ This parameter can be a value of @ref LPTIM_Output_Polarity */
- uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare
- values is done immediately or after the end of current period.
- This parameter can be a value of @ref LPTIM_Updating_Mode */
+ uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare
+ values is done immediately or after the end of current period.
+ This parameter can be a value of @ref LPTIM_Updating_Mode */
- uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event
- or each external event.
- This parameter can be a value of @ref LPTIM_Counter_Source */
+ uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event
+ or each external event.
+ This parameter can be a value of @ref LPTIM_Counter_Source */
- uint32_t Input1Source; /*!< Specifies source selected for input1 (GPIO or comparator output).
- This parameter can be a value of @ref LPTIM_Input1_Source */
+ uint32_t Input1Source; /*!< Specifies source selected for input1 (GPIO or comparator output).
+ This parameter can be a value of @ref LPTIM_Input1_Source */
- uint32_t Input2Source; /*!< Specifies source selected for input2 (GPIO or comparator output).
- Note: This parameter is used only for encoder feature so is used only
- for LPTIM1 instance.
- This parameter can be a value of @ref LPTIM_Input2_Source */
+ uint32_t Input2Source; /*!< Specifies source selected for input2 (GPIO or comparator output).
+ Note: This parameter is used only for encoder feature so is used only
+ for LPTIM1 instance.
+ This parameter can be a value of @ref LPTIM_Input2_Source */
#if defined(LPTIM_RCR_REP)
- uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
- reaches zero, an update event is generated and counting restarts
- from the RCR value (N).
- Note: When using repetition counter the UpdateMode field must be set to
- LPTIM_UPDATE_ENDOFPERIOD otherwise unpredictable behavior may occur.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+ uint32_t RepetitionCounter;/*!< Specifies the repetition counter value.
+ Each time the RCR downcounter reaches zero, an update event is
+ generated and counting restarts from the RCR value (N).
+ Note: When using repetition counter the UpdateMode field must be
+ set to LPTIM_UPDATE_ENDOFPERIOD otherwise unpredictable
+ behavior may occur.
+ This parameter must be a number between Min_Data = 0x00 and
+ Max_Data = 0xFF. */
#endif
} LPTIM_InitTypeDef;
@@ -443,6 +444,24 @@
*/
#define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
+#if defined(LPTIM_CR_COUNTRST)
+/**
+ * @brief Reset the LPTIM Counter register in synchronous mode.
+ * @param __HANDLE__ LPTIM handle
+ * @retval None
+ */
+#define __HAL_LPTIM_RESET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_COUNTRST)
+#endif /* LPTIM_CR_COUNTRST */
+
+#if defined(LPTIM_CR_RSTARE)
+/**
+ * @brief Reset after read of the LPTIM Counter register in asynchronous mode.
+ * @param __HANDLE__ LPTIM handle
+ * @retval None
+ */
+#define __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_RSTARE)
+#endif /* LPTIM_CR_RSTARE */
+
/**
* @brief Write the passed parameter in the Autoreload register.
* @param __HANDLE__ LPTIM handle
@@ -902,5 +921,3 @@
#endif
#endif /* STM32L4xx_HAL_LPTIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_ltdc.h b/Inc/stm32l4xx_hal_ltdc.h
index a48b37e..267826b 100644
--- a/Inc/stm32l4xx_hal_ltdc.h
+++ b/Inc/stm32l4xx_hal_ltdc.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -692,5 +691,3 @@
#endif
#endif /* STM32L4xx_HAL_LTDC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_ltdc_ex.h b/Inc/stm32l4xx_hal_ltdc_ex.h
index 82147aa..71da6c8 100644
--- a/Inc/stm32l4xx_hal_ltdc_ex.h
+++ b/Inc/stm32l4xx_hal_ltdc_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -82,5 +81,3 @@
#endif
#endif /* STM32L4xx_HAL_LTDC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_mmc.h b/Inc/stm32l4xx_hal_mmc.h
index 4c5afe1..9e2d738 100644
--- a/Inc/stm32l4xx_hal_mmc.h
+++ b/Inc/stm32l4xx_hal_mmc.h
@@ -6,16 +6,15 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_MMC_H
@@ -26,6 +25,7 @@
#endif
/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
#include "stm32l4xx_ll_sdmmc.h"
/** @addtogroup STM32L4xx_HAL_Driver
@@ -55,7 +55,7 @@
HAL_MMC_STATE_BUSY = ((uint32_t)0x00000003U), /*!< MMC process ongoing */
HAL_MMC_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< MMC Programming State */
HAL_MMC_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< MMC Receinving State */
- HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< MMC Transfert State */
+ HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< MMC Transfer State */
HAL_MMC_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< MMC is in error state */
}HAL_MMC_StateTypeDef;
/**
@@ -67,15 +67,18 @@
*/
typedef uint32_t HAL_MMC_CardStateTypeDef;
-#define HAL_MMC_CARD_READY 0x00000001U /*!< Card state is ready */
-#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */
-#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */
-#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */
-#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */
-#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */
-#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */
-#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */
-#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error */
+#define HAL_MMC_CARD_IDLE 0x00000000U /*!< Card is in idle state (can't be checked by CMD13) */
+#define HAL_MMC_CARD_READY 0x00000001U /*!< Card is in ready state (can't be checked by CMD13) */
+#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state (can't be checked by CMD13) */
+#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */
+#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */
+#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */
+#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */
+#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */
+#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */
+#define HAL_MMC_CARD_BUSTEST 0x00000009U /*!< Card is in bus test state */
+#define HAL_MMC_CARD_SLEEP 0x0000000AU /*!< Card is in sleep state (can't be checked by CMD13) */
+#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error (can't be checked by CMD13) */
/**
* @}
*/
@@ -356,9 +359,9 @@
#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< High voltage in byte mode */
#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< Dual voltage in byte mode */
#define MMC_LOW_VOLTAGE_RANGE 0x80000080U /*!< Low voltage in byte mode */
-#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< High voltage in sector mode */
-#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< Dual voltage in sector mode */
-#define eMMC_LOW_VOLTAGE_RANGE 0xC0000080U /*!< Low voltage in sector mode */
+#define EMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< High voltage in sector mode */
+#define EMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< Dual voltage in sector mode */
+#define EMMC_LOW_VOLTAGE_RANGE 0xC0000080U /*!< Low voltage in sector mode */
#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U
/**
* @}
@@ -435,12 +438,12 @@
#else
#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MMC_STATE_RESET)
#endif
-
+
#if !defined(STM32L4P5xx) && !defined(STM32L4Q5xx) && !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
/**
* @brief Enable the MMC device.
* @retval None
- */
+ */
#define __HAL_MMC_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance)
/**
@@ -452,7 +455,7 @@
/**
* @brief Enable the SDMMC DMA transfer.
* @retval None
- */
+ */
#define __HAL_MMC_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance)
/**
@@ -461,7 +464,7 @@
*/
#define __HAL_MMC_DMA_DISABLE(__HANDLE__) __SDMMC_DMA_DISABLE((__HANDLE__)->Instance)
#endif
-
+
/**
* @brief Enable the MMC device interrupt.
* @param __HANDLE__ MMC Handle
@@ -792,6 +795,15 @@
/**
* @}
*/
+
+/** @defgroup MMC_Exported_Functions_Group8 Peripheral Sleep management
+ * @{
+ */
+HAL_StatusTypeDef HAL_MMC_SleepDevice(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc);
+/**
+ * @}
+ */
#endif /* defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) */
/**
@@ -882,5 +894,3 @@
#endif /* STM32L4xx_HAL_MMC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_mmc_ex.h b/Inc/stm32l4xx_hal_mmc_ex.h
index d742b1d..255c8b5 100644
--- a/Inc/stm32l4xx_hal_mmc_ex.h
+++ b/Inc/stm32l4xx_hal_mmc_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -113,5 +112,3 @@
#endif /* STM32L4xx_HAL_MMCEx_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_nand.h b/Inc/stm32l4xx_hal_nand.h
index f1a2ebd..52a911c 100644
--- a/Inc/stm32l4xx_hal_nand.h
+++ b/Inc/stm32l4xx_hal_nand.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -325,8 +324,10 @@
* @retval NAND Raw address value
*/
#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
- (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * \
- ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
+ (((__ADDRESS__)->Block + \
+ (((__ADDRESS__)->Plane) * \
+ ((__HANDLE__)->Config.PlaneSize))) * \
+ ((__HANDLE__)->Config.BlockSize)))
/**
* @brief NAND memory Column address computation.
@@ -376,5 +377,3 @@
#endif
#endif /* STM32L4xx_HAL_NAND_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_nor.h b/Inc/stm32l4xx_hal_nor.h
index 62d00c2..42806cb 100644
--- a/Inc/stm32l4xx_hal_nor.h
+++ b/Inc/stm32l4xx_hal_nor.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -325,5 +324,3 @@
#endif
#endif /* STM32L4xx_HAL_NOR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_opamp.h b/Inc/stm32l4xx_hal_opamp.h
index 4e520c7..5cf6184 100644
--- a/Inc/stm32l4xx_hal_opamp.h
+++ b/Inc/stm32l4xx_hal_opamp.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -383,7 +382,7 @@
((GAIN) == OPAMP_PGA_GAIN_8) || \
((GAIN) == OPAMP_PGA_GAIN_16))
-#define IS_OPAMP_POWERMODE(TRIMMING) (((TRIMMING) == OPAMP_POWERMODE_NORMAL) || \
+#define IS_OPAMP_POWERMODE(TRIMMING) (((TRIMMING) == OPAMP_POWERMODE_NORMALPOWER) || \
((TRIMMING) == OPAMP_POWERMODE_LOWPOWER) )
#define IS_OPAMP_POWER_SUPPLY_RANGE(RANGE) (((RANGE) == OPAMP_POWERSUPPLY_LOW) || \
@@ -481,5 +480,3 @@
#endif
#endif /* STM32L4xx_HAL_OPAMP_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_opamp_ex.h b/Inc/stm32l4xx_hal_opamp_ex.h
index 052fad3..d1a7dae 100644
--- a/Inc/stm32l4xx_hal_opamp_ex.h
+++ b/Inc/stm32l4xx_hal_opamp_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -87,5 +86,3 @@
#endif
#endif /* STM32L4xx_HAL_OPAMP_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_ospi.h b/Inc/stm32l4xx_hal_ospi.h
index 35210ee..6f68f67 100644
--- a/Inc/stm32l4xx_hal_ospi.h
+++ b/Inc/stm32l4xx_hal_ospi.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -61,7 +60,7 @@
it corresponds to the number of address bits required to access
the external device.
This parameter can be a value between 1 and 32 */
- uint32_t ChipSelectHighTime; /*!< It defines the minimun number of clocks which the chip select
+ uint32_t ChipSelectHighTime; /*!< It defines the minimum number of clocks which the chip select
must remain high between commands.
This parameter can be a value between 1 and 8 */
uint32_t FreeRunningClock; /*!< It enables or not the free running clock.
@@ -102,7 +101,7 @@
typedef struct __OSPI_HandleTypeDef
#else
typedef struct
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
{
OCTOSPI_TypeDef *Instance; /*!< OSPI registers base address */
OSPI_InitTypeDef Init; /*!< OSPI initialization parameters */
@@ -127,7 +126,7 @@
void (* MspInitCallback) (struct __OSPI_HandleTypeDef *hospi);
void (* MspDeInitCallback) (struct __OSPI_HandleTypeDef *hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}OSPI_HandleTypeDef;
/**
@@ -135,7 +134,7 @@
*/
typedef struct
{
- uint32_t OperationType; /*!< It indicates if the configuration applies to the common regsiters or
+ uint32_t OperationType; /*!< It indicates if the configuration applies to the common registers or
to the registers for the write operation (these registers are only
used for memory-mapped mode).
This parameter can be a value of @ref OSPI_OperationType */
@@ -188,7 +187,7 @@
{
uint32_t RWRecoveryTime; /*!< It indicates the number of cycles for the device read write recovery time.
This parameter can be a value between 0 and 255 */
- uint32_t AccessTime; /*!< It indicates the number of cycles for the device acces time.
+ uint32_t AccessTime; /*!< It indicates the number of cycles for the device access time.
This parameter can be a value between 0 and 255 */
uint32_t WriteZeroLatency; /*!< It enables or not the latency for the write access.
This parameter can be a value of @ref OSPI_WriteZeroLatency */
@@ -259,7 +258,7 @@
uint32_t IOHighPort; /*!< It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins.
This parameter can be a value of @ref OSPIM_IOPort */
#if defined (OCTOSPIM_CR_MUXEN)
- uint32_t Req2AckTime; /*!< It indicates the minimum switching duration (in number of clock cycles) expected
+ uint32_t Req2AckTime; /*!< It indicates the minimum switching duration (in number of clock cycles) expected
if some signals are multiplexed in the OSPI IO Manager with the other OSPI.
This parameter can be a value between 1 and 256 */
#endif
@@ -290,7 +289,7 @@
* @brief HAL OSPI Callback pointer definition
*/
typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
/**
* @}
*/
@@ -331,7 +330,7 @@
#define HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U) /*!< Sequence of the state machine is incorrect */
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
#define HAL_OSPI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid callback error */
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
/**
* @}
*/
@@ -676,7 +675,7 @@
} while(0)
#else
#define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OSPI_STATE_RESET)
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
/** @brief Enable the OSPI peripheral.
* @param __HANDLE__ specifies the OSPI Handle.
@@ -728,7 +727,8 @@
* @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\
+ == (__INTERRUPT__))
/**
* @brief Check whether the selected OSPI flag is set or not.
@@ -743,7 +743,8 @@
* @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag
* @retval None
*/
-#define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
+#define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) \
+ != 0U) ? SET : RESET)
/** @brief Clears the specified OSPI's flag status.
* @param __HANDLE__ specifies the OSPI Handle.
@@ -787,22 +788,22 @@
void HAL_OSPI_IRQHandler (OSPI_HandleTypeDef *hospi);
/* OSPI command configuration functions */
-HAL_StatusTypeDef HAL_OSPI_Command (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout);
-HAL_StatusTypeDef HAL_OSPI_Command_IT (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd);
-HAL_StatusTypeDef HAL_OSPI_HyperbusCfg (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout);
-HAL_StatusTypeDef HAL_OSPI_HyperbusCmd (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout);
+HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout);
+HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd);
+HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout);
+HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout);
/* OSPI indirect mode functions */
-HAL_StatusTypeDef HAL_OSPI_Transmit (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_OSPI_Receive (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_OSPI_Transmit_IT (OSPI_HandleTypeDef *hospi, uint8_t *pData);
-HAL_StatusTypeDef HAL_OSPI_Receive_IT (OSPI_HandleTypeDef *hospi, uint8_t *pData);
-HAL_StatusTypeDef HAL_OSPI_Transmit_DMA (OSPI_HandleTypeDef *hospi, uint8_t *pData);
-HAL_StatusTypeDef HAL_OSPI_Receive_DMA (OSPI_HandleTypeDef *hospi, uint8_t *pData);
+HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData);
+HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData);
+HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData);
+HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData);
/* OSPI status flag polling mode functions */
-HAL_StatusTypeDef HAL_OSPI_AutoPolling (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
-HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg);
+HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
+HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg);
/* OSPI memory-mapped mode functions */
HAL_StatusTypeDef HAL_OSPI_MemoryMapped (OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg);
@@ -827,9 +828,10 @@
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
/* OSPI callback registering/unregistering */
-HAL_StatusTypeDef HAL_OSPI_RegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, pOSPI_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID);
-#endif
+HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID,
+ pOSPI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID);
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
/**
* @}
*/
@@ -854,7 +856,7 @@
/** @addtogroup OSPI_Exported_Functions_Group4
* @{
*/
-HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout);
+HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout);
/**
* @}
@@ -1002,9 +1004,6 @@
#define IS_OSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
#define IS_OSPI_CS_BOUNDARY(BOUNDARY) ((BOUNDARY) <= 31U)
-
-#define IS_OSPI_DLYBYP(MODE) (((MODE) == HAL_OSPI_DELAY_BLOCK_USED) || \
- ((MODE) == HAL_OSPI_DELAY_BLOCK_BYPASSED))
#if defined (OCTOSPI_DCR3_MAXTRAN)
#define IS_OSPI_MAXTRAN(NB_BYTES) ((NB_BYTES) <= 255U)
@@ -1020,9 +1019,9 @@
((PORT) == HAL_OSPIM_IOPORT_2_LOW) || \
((PORT) == HAL_OSPIM_IOPORT_2_HIGH))
-#if defined (OCTOSPIM_CR_MUXEN)
-#define IS_OSPIM_REQ2ACKTIME(TIME) (((TIME) >= 1) && ((TIME) <= 256))
-#endif
+#if defined (OCTOSPIM_CR_MUXEN)
+#define IS_OSPIM_REQ2ACKTIME(TIME) (((TIME) >= 1U) && ((TIME) <= 256U))
+#endif /*(OCTOSPIM_CR_MUXEN)*/
/**
@endcond
*/
@@ -1044,5 +1043,3 @@
#endif
#endif /* STM32L4xx_HAL_OSPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_pcd.h b/Inc/stm32l4xx_hal_pcd.h
index c36508b..5c9db6b 100644
--- a/Inc/stm32l4xx_hal_pcd.h
+++ b/Inc/stm32l4xx_hal_pcd.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -206,29 +205,36 @@
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \
+ ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
+#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \
+ *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK)
-#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK)
+#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \
+ *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
-#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
-
-#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
+#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) \
+ ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
-#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= (uint16_t)(~(__INTERRUPT__)))
+#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\
+ & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE
-#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE)
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\
+ &= (uint16_t)(~(__INTERRUPT__)))
+
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE
+#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE)
#endif /* defined (USB) */
/**
@@ -372,13 +378,12 @@
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint8_t *pBuf, uint32_t len);
-
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
-
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
/**
* @}
@@ -458,27 +463,27 @@
#if defined (USB_OTG_FS)
#ifndef USB_OTG_DOEPINT_OTEPSPR
#define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */
-#endif
+#endif /* defined USB_OTG_DOEPINT_OTEPSPR */
#ifndef USB_OTG_DOEPMSK_OTEPSPRM
#define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */
-#endif
+#endif /* defined USB_OTG_DOEPMSK_OTEPSPRM */
#ifndef USB_OTG_DOEPINT_NAK
#define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */
-#endif
+#endif /* defined USB_OTG_DOEPINT_NAK */
#ifndef USB_OTG_DOEPMSK_NAKM
#define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */
-#endif
+#endif /* defined USB_OTG_DOEPMSK_NAKM */
#ifndef USB_OTG_DOEPINT_STPKTRX
#define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */
-#endif
+#endif /* defined USB_OTG_DOEPINT_STPKTRX */
#ifndef USB_OTG_DOEPMSK_NYETM
#define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */
-#endif
+#endif /* defined USB_OTG_DOEPMSK_NYETM */
#endif /* defined (USB_OTG_FS) */
/* Private macros ------------------------------------------------------------*/
@@ -491,7 +496,8 @@
#define USB_CNTRX_BLSIZE (0x1U << 15)
/* SetENDPOINT */
-#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
+#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)\
+ (&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
/* GetENDPOINT */
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
@@ -506,7 +512,9 @@
* @param wType Endpoint Type.
* @retval None
*/
-#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
+#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), ((PCD_GET_ENDPOINT((USBx), (bEpNum))\
+ & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
+
/**
* @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
@@ -523,7 +531,7 @@
* @param bEpNum, bDir
* @retval None
*/
-#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) \
+#define PCD_FREE_USER_BUFFER(USBx, bEpNum, bDir) \
do { \
if ((bDir) == 0U) \
{ \
@@ -691,8 +699,8 @@
* @param bEpNum Endpoint Number.
* @retval None
*/
-#define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
-#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
+#define PCD_SET_BULK_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
+#define PCD_CLEAR_BULK_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
/**
* @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
@@ -795,8 +803,12 @@
*/
#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
-#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
-#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
+#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE\
+ + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
+
+#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE\
+ + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
+
/**
* @brief sets address of the tx/rx buffer.
@@ -864,18 +876,22 @@
#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \
do { \
uint32_t wNBlocks; \
- if ((wCount) == 0U) \
+ \
+ if ((wCount) > 62U) \
{ \
- *(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \
- *(pdwReg) |= USB_CNTRX_BLSIZE; \
- } \
- else if((wCount) <= 62U) \
- { \
- PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
+ PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
} \
else \
{ \
- PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
+ if ((wCount) == 0U) \
+ { \
+ *(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \
+ *(pdwReg) |= USB_CNTRX_BLSIZE; \
+ } \
+ else \
+ { \
+ PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
+ } \
} \
} while(0) /* PCD_SET_EP_CNT_RX_REG */
@@ -1048,5 +1064,3 @@
#endif
#endif /* STM32L4xx_HAL_PCD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_pcd_ex.h b/Inc/stm32l4xx_hal_pcd_ex.h
index ea54722..d86c89c 100644
--- a/Inc/stm32l4xx_hal_pcd_ex.h
+++ b/Inc/stm32l4xx_hal_pcd_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -23,7 +22,7 @@
#ifdef __cplusplus
extern "C" {
-#endif
+#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
@@ -87,9 +86,7 @@
#ifdef __cplusplus
}
-#endif
+#endif /* __cplusplus */
#endif /* STM32L4xx_HAL_PCD_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_pka.h b/Inc/stm32l4xx_hal_pka.h
index 385bb0c..97ba96c 100644
--- a/Inc/stm32l4xx_hal_pka.h
+++ b/Inc/stm32l4xx_hal_pka.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -29,19 +28,19 @@
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
+ * @{
+ */
#if defined(PKA) && defined(HAL_PKA_MODULE_ENABLED)
/** @addtogroup PKA
- * @{
- */
+ * @{
+ */
/* Exported types ------------------------------------------------------------*/
/** @defgroup PKA_Exported_Types PKA Exported Types
- * @{
- */
+ * @{
+ */
/** @defgroup HAL_state_structure_definition HAL state structure definition
* @brief HAL State structures definition
@@ -364,7 +363,7 @@
} while(0)
#else
#define __HAL_PKA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PKA_STATE_RESET)
-#endif
+#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
/** @brief Enable the specified PKA interrupt.
* @param __HANDLE__ specifies the PKA Handle
@@ -397,7 +396,8 @@
* @arg @ref PKA_IT_RAMERR RAM error interrupt enable
* @retval The new state of __INTERRUPT__ (SET or RESET)
*/
-#define __HAL_PKA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_PKA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified PKA flag is set or not.
* @param __HANDLE__ specifies the PKA Handle
@@ -408,7 +408,8 @@
* @arg @ref PKA_FLAG_RAMERR RAM error
* @retval The new state of __FLAG__ (SET or RESET)
*/
-#define __HAL_PKA_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+#define __HAL_PKA_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR)\
+ & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
/** @brief Clear the PKA pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__ specifies the PKA Handle
@@ -459,7 +460,8 @@
#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
-HAL_StatusTypeDef HAL_PKA_RegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID, pPKA_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PKA_RegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID,
+ pPKA_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
@@ -480,7 +482,8 @@
HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in, uint32_t Timeout);
HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in);
-void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out, PKA_ECDSASignOutExtParamTypeDef *outExt);
+void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out,
+ PKA_ECDSASignOutExtParamTypeDef *outExt);
HAL_StatusTypeDef HAL_PKA_ECDSAVerif(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in, uint32_t Timeout);
HAL_StatusTypeDef HAL_PKA_ECDSAVerif_IT(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in);
@@ -563,5 +566,3 @@
#endif
#endif /* STM32L4xx_HAL_PKA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_pssi.h b/Inc/stm32l4xx_hal_pssi.h
index 0a74420..6051f00 100644
--- a/Inc/stm32l4xx_hal_pssi.h
+++ b/Inc/stm32l4xx_hal_pssi.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -236,7 +235,7 @@
#define PSSI_CR_OUTEN_OUTPUT PSSI_CR_OUTEN /*!< Output Mode */
#define PSSI_CR_DMA_ENABLE PSSI_CR_DMAEN /*!< DMA Mode Enable */
-#define PSSI_CR_DMA_DISABLE (~PSSI_CR_DMAEN) /*!< DMA Mode Disble */
+#define PSSI_CR_DMA_DISABLE (~PSSI_CR_DMAEN) /*!< DMA Mode Disable */
#define PSSI_CR_16BITS PSSI_CR_EDM /*!< 16 Lines Mode */
#define PSSI_CR_8BITS (~PSSI_CR_EDM) /*!< 8 Lines Mode */
@@ -511,6 +510,3 @@
#endif
#endif /* STM32L4xx_HAL_PSSI_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_pwr.h b/Inc/stm32l4xx_hal_pwr.h
index c006a0d..e90fcb7 100644
--- a/Inc/stm32l4xx_hal_pwr.h
+++ b/Inc/stm32l4xx_hal_pwr.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -410,5 +409,3 @@
#endif /* STM32L4xx_HAL_PWR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_pwr_ex.h b/Inc/stm32l4xx_hal_pwr_ex.h
index 0b4d703..71dbbb3 100644
--- a/Inc/stm32l4xx_hal_pwr_ex.h
+++ b/Inc/stm32l4xx_hal_pwr_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -928,5 +927,3 @@
#endif /* STM32L4xx_HAL_PWR_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_qspi.h b/Inc/stm32l4xx_hal_qspi.h
index 1f10f89..519e33b 100644
--- a/Inc/stm32l4xx_hal_qspi.h
+++ b/Inc/stm32l4xx_hal_qspi.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -464,7 +463,7 @@
* @{
*/
/** @brief Reset QSPI handle state.
- * @param __HANDLE__ : QSPI handle.
+ * @param __HANDLE__ QSPI handle.
* @retval None
*/
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
@@ -478,20 +477,20 @@
#endif
/** @brief Enable the QSPI peripheral.
- * @param __HANDLE__ : specifies the QSPI Handle.
+ * @param __HANDLE__ specifies the QSPI Handle.
* @retval None
*/
#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
/** @brief Disable the QSPI peripheral.
- * @param __HANDLE__ : specifies the QSPI Handle.
+ * @param __HANDLE__ specifies the QSPI Handle.
* @retval None
*/
#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
/** @brief Enable the specified QSPI interrupt.
- * @param __HANDLE__ : specifies the QSPI Handle.
- * @param __INTERRUPT__ : specifies the QSPI interrupt source to enable.
+ * @param __HANDLE__ specifies the QSPI Handle.
+ * @param __INTERRUPT__ specifies the QSPI interrupt source to enable.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
@@ -504,8 +503,8 @@
/** @brief Disable the specified QSPI interrupt.
- * @param __HANDLE__ : specifies the QSPI Handle.
- * @param __INTERRUPT__ : specifies the QSPI interrupt source to disable.
+ * @param __HANDLE__ specifies the QSPI Handle.
+ * @param __INTERRUPT__ specifies the QSPI interrupt source to disable.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
@@ -517,8 +516,8 @@
#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
/** @brief Check whether the specified QSPI interrupt source is enabled or not.
- * @param __HANDLE__ : specifies the QSPI Handle.
- * @param __INTERRUPT__ : specifies the QSPI interrupt source to check.
+ * @param __HANDLE__ specifies the QSPI Handle.
+ * @param __INTERRUPT__ specifies the QSPI interrupt source to check.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
@@ -531,8 +530,8 @@
/**
* @brief Check whether the selected QSPI flag is set or not.
- * @param __HANDLE__ : specifies the QSPI Handle.
- * @param __FLAG__ : specifies the QSPI flag to check.
+ * @param __HANDLE__ specifies the QSPI Handle.
+ * @param __FLAG__ specifies the QSPI flag to check.
* This parameter can be one of the following values:
* @arg QSPI_FLAG_BUSY: QSPI Busy flag
* @arg QSPI_FLAG_TO: QSPI Timeout flag
@@ -545,8 +544,8 @@
#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
/** @brief Clears the specified QSPI's flag status.
- * @param __HANDLE__ : specifies the QSPI Handle.
- * @param __FLAG__ : specifies the QSPI clear register flag that needs to be set
+ * @param __HANDLE__ specifies the QSPI Handle.
+ * @param __FLAG__ specifies the QSPI clear register flag that needs to be set
* This parameter can be one of the following values:
* @arg QSPI_FLAG_TO: QSPI Timeout flag
* @arg QSPI_FLAG_SM: QSPI Status match flag
@@ -758,12 +757,10 @@
* @}
*/
-#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */
+#endif /* defined(QUADSPI) */
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_QSPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_rcc.h b/Inc/stm32l4xx_hal_rcc.h
index 5d13394..260918d 100644
--- a/Inc/stm32l4xx_hal_rcc.h
+++ b/Inc/stm32l4xx_hal_rcc.h
@@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -4628,6 +4626,31 @@
#endif /* RCC_HSI48_SUPPORT */
#define RCC_FLAG_MASK 0x1FU
+
+/* Defines Oscillator Masks */
+#if defined(RCC_HSI48_SUPPORT)
+#define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE) /*!< All Oscillator to configure */
+#else
+#define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE) /*!< All Oscillator to configure */
+#endif /* RCC_HSI48_SUPPORT */
+
+/** @defgroup RCC_Reset_Flag Reset Flag
+ * @{
+ */
+#define RCC_RESET_FLAG_OBL RCC_CSR_OBLRSTF /*!< Option Byte Loader reset flag */
+#define RCC_RESET_FLAG_PIN RCC_CSR_PINRSTF /*!< PIN reset flag */
+#define RCC_RESET_FLAG_PWR RCC_CSR_BORRSTF /*!< BOR or POR/PDR reset flag */
+#define RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF /*!< Software Reset flag */
+#define RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
+#define RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
+#define RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF /*!< Low power reset flag */
+#define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \
+ RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \
+ RCC_RESET_FLAG_LPWR)
+/**
+ * @}
+ */
+
/**
* @}
*/
@@ -4637,22 +4660,8 @@
* @{
*/
-#if defined(RCC_HSI48_SUPPORT)
-#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
-#else
-#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
-#endif /* RCC_HSI48_SUPPORT */
+#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
+ (((__OSCILLATOR__) & ~RCC_OSCILLATORTYPE_ALL) == 0x00U))
#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
((__HSE__) == RCC_HSE_BYPASS))
@@ -4849,6 +4858,7 @@
/* User Callbacks in non blocking mode (IT mode) */
void HAL_RCC_CSSCallback(void);
+uint32_t HAL_RCC_GetResetSource(void);
/**
* @}
*/
@@ -4871,4 +4881,3 @@
#endif /* STM32L4xx_HAL_RCC_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_rcc_ex.h b/Inc/stm32l4xx_hal_rcc_ex.h
index ebedaf5..e0db863 100644
--- a/Inc/stm32l4xx_hal_rcc_ex.h
+++ b/Inc/stm32l4xx_hal_rcc_ex.h
@@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -2348,14 +2346,14 @@
#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
/**
- * @brief Enable the automatic hardware adjustement of TRIM bits.
+ * @brief Enable the automatic hardware adjustment of TRIM bits.
* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
* @retval None
*/
#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
/**
- * @brief Enable or disable the automatic hardware adjustement of TRIM bits.
+ * @brief Enable or disable the automatic hardware adjustment of TRIM bits.
* @retval None
*/
#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
@@ -2493,6 +2491,146 @@
* @}
*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup RCCEx_Private_Constants
+ * @{
+ */
+/* Define used for IS_RCC_* macros below */
+#if defined(STM32L412xx) || defined(STM32L422xx)
+#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
+ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
+ RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_RNG)
+#elif defined(STM32L431xx)
+#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
+ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
+ RCC_PERIPHCLK_SAI1 | \
+ RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \
+ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1)
+#elif defined(STM32L432xx) || defined(STM32L442xx)
+#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
+ RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C3 | \
+ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
+ RCC_PERIPHCLK_SAI1 | \
+ RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC | \
+ RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG)
+#elif defined(STM32L433xx) || defined(STM32L443xx)
+#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\
+ RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
+ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
+ RCC_PERIPHCLK_SAI1 | \
+ RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \
+ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1)
+#elif defined(STM32L451xx)
+#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\
+ RCC_PERIPHCLK_UART4 | \
+ RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
+ RCC_PERIPHCLK_I2C4 | \
+ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
+ RCC_PERIPHCLK_SAI1 | \
+ RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \
+ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1)
+#elif defined(STM32L452xx) || defined(STM32L462xx)
+#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\
+ RCC_PERIPHCLK_UART4 | \
+ RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
+ RCC_PERIPHCLK_I2C4 | \
+ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
+ RCC_PERIPHCLK_SAI1 | \
+ RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \
+ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1)
+#elif defined(STM32L471xx)
+#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
+ RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
+ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
+ RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \
+ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1)
+#elif defined(STM32L496xx) || defined(STM32L4A6xx)
+#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
+ RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
+ RCC_PERIPHCLK_I2C4 | \
+ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
+ RCC_PERIPHCLK_USB | \
+ RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \
+ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1)
+#elif defined(STM32L4P5xx) || defined(STM32L4Q5xx)
+#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
+ RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
+ RCC_PERIPHCLK_I2C4 | \
+ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
+ RCC_PERIPHCLK_USB | \
+ RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1AUDIO | \
+ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1 | \
+ RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC)
+#elif defined(STM32L4R5xx) || defined(STM32L4S5xx)
+#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
+ RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
+ RCC_PERIPHCLK_I2C4 | \
+ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
+ RCC_PERIPHCLK_USB | \
+ RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1AUDIO | \
+ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1 | \
+ RCC_PERIPHCLK_OSPI)
+#elif defined(STM32L4R7xx) || defined(STM32L4S7xx)
+#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
+ RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
+ RCC_PERIPHCLK_I2C4 | \
+ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
+ RCC_PERIPHCLK_USB | \
+ RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1AUDIO | \
+ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1 | \
+ RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC)
+#elif defined(STM32L4R9xx) || defined(STM32L4S9xx)
+#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
+ RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
+ RCC_PERIPHCLK_I2C4 | \
+ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
+ RCC_PERIPHCLK_USB | \
+ RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1AUDIO | \
+ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1 | \
+ RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_DSI)
+#else
+#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
+ RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
+ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
+ RCC_PERIPHCLK_USB | \
+ RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \
+ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1)
+#endif /* STM32L412xx || STM32L422xx */
+
+/**
+ * @}
+ */
+
/* Private macros ------------------------------------------------------------*/
/** @addtogroup RCCEx_Private_Macros
* @{
@@ -2501,303 +2639,8 @@
#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
((__SOURCE__) == RCC_LSCOSOURCE_LSE))
-#if defined(STM32L412xx) || defined(STM32L422xx)
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
- ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG))
-
-#elif defined(STM32L431xx)
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
- ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
-
-#elif defined(STM32L432xx) || defined(STM32L442xx)
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
- ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG))
-
-#elif defined(STM32L433xx) || defined(STM32L443xx)
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
- ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
-
-#elif defined(STM32L451xx)
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
- ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
-
-#elif defined(STM32L452xx) || defined(STM32L462xx)
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
- ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
-
-#elif defined(STM32L471xx)
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
- ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
- (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
-
-#elif defined(STM32L496xx) || defined(STM32L4A6xx)
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
- ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
- (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
-
-#elif defined(STM32L4P5xx) || defined(STM32L4Q5xx)
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
- ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
- (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
-
-#elif defined(STM32L4R5xx) || defined(STM32L4S5xx)
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
- ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
- (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI))
-
-#elif defined(STM32L4R7xx) || defined(STM32L4S7xx)
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
- ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
- (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
-
-#elif defined(STM32L4R9xx) || defined(STM32L4S9xx)
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
- ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
- (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI))
-
-#else
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
- ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
- (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
-
-#endif /* STM32L412xx || STM32L422xx */
+#define IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__) & RCC_PERIPHCLOCK_ALL) != 0x00u) && \
+ (((__SELECTION__) & ~RCC_PERIPHCLOCK_ALL) == 0x00u))
#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \
@@ -3200,4 +3043,3 @@
#endif /* STM32L4xx_HAL_RCC_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_rng.h b/Inc/stm32l4xx_hal_rng.h
index 526dfe5..dd15099 100644
--- a/Inc/stm32l4xx_hal_rng.h
+++ b/Inc/stm32l4xx_hal_rng.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -390,5 +389,3 @@
#endif /* STM32L4xx_HAL_RNG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_rng_ex.h b/Inc/stm32l4xx_hal_rng_ex.h
index 235750d..7d39f89 100644
--- a/Inc/stm32l4xx_hal_rng_ex.h
+++ b/Inc/stm32l4xx_hal_rng_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -226,5 +225,3 @@
#endif /* STM32L4xx_HAL_RNGEX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_rtc.h b/Inc/stm32l4xx_hal_rtc.h
index fe79fd9..99c1658 100644
--- a/Inc/stm32l4xx_hal_rtc.h
+++ b/Inc/stm32l4xx_hal_rtc.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -662,7 +661,7 @@
/**
* @brief Subtract 1 hour (winter time change).
- * @note This interface is deprecated.
+ * @note This interface is deprecated.
* To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions
* @param __HANDLE__ specifies the RTC handle.
* @param __BKP__ Backup
@@ -1135,6 +1134,3 @@
#endif
#endif /* STM32L4xx_HAL_RTC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Inc/stm32l4xx_hal_rtc_ex.h b/Inc/stm32l4xx_hal_rtc_ex.h
index 171a4bf..a022b1b 100644
--- a/Inc/stm32l4xx_hal_rtc_ex.h
+++ b/Inc/stm32l4xx_hal_rtc_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -1739,5 +1738,3 @@
#endif /* __cplusplus */
#endif /* STM32L4xx_HAL_RTC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_sai.h b/Inc/stm32l4xx_hal_sai.h
index 63d6eae..b36604a 100644
--- a/Inc/stm32l4xx_hal_sai.h
+++ b/Inc/stm32l4xx_hal_sai.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -996,4 +995,3 @@
#endif /* STM32L4xx_HAL_SAI_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_sai_ex.h b/Inc/stm32l4xx_hal_sai_ex.h
index 0da376d..cbd6e38 100644
--- a/Inc/stm32l4xx_hal_sai_ex.h
+++ b/Inc/stm32l4xx_hal_sai_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -108,4 +107,3 @@
#endif /* STM32L4xx_HAL_SAI_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_sd.h b/Inc/stm32l4xx_hal_sd.h
index 55a5f37..acda387 100644
--- a/Inc/stm32l4xx_hal_sd.h
+++ b/Inc/stm32l4xx_hal_sd.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -25,9 +24,10 @@
extern "C" {
#endif
-#if defined(SDMMC1)
-
/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+#if defined(SDMMC1)
#include "stm32l4xx_ll_sdmmc.h"
/** @addtogroup STM32L4xx_HAL_Driver
@@ -55,7 +55,7 @@
HAL_SD_STATE_BUSY = ((uint32_t)0x00000003U), /*!< SD process ongoing */
HAL_SD_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< SD Programming State */
HAL_SD_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< SD Receiving State */
- HAL_SD_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< SD Transfert State */
+ HAL_SD_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< SD Transfer State */
HAL_SD_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< SD is in error state */
}HAL_SD_StateTypeDef;
/**
@@ -860,5 +860,3 @@
#endif /* STM32L4xx_HAL_SD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_sd_ex.h b/Inc/stm32l4xx_hal_sd_ex.h
index 227a992..b258060 100644
--- a/Inc/stm32l4xx_hal_sd_ex.h
+++ b/Inc/stm32l4xx_hal_sd_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -125,5 +124,3 @@
#endif /* STM32L4xx_HAL_SDEx_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_smartcard.h b/Inc/stm32l4xx_hal_smartcard.h
index 63c52b9..52239aa 100644
--- a/Inc/stm32l4xx_hal_smartcard.h
+++ b/Inc/stm32l4xx_hal_smartcard.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -52,7 +51,8 @@
where usart_ker_ckpres is the USART input clock divided by a prescaler */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
+ This parameter @ref SMARTCARD_Word_Length can only be
+ set to 9 (8 data + 1 parity bits). */
uint32_t StopBits; /*!< Specifies the number of stop bits.
This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
@@ -76,13 +76,14 @@
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref SMARTCARD_Last_Bit */
- uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
- Selecting the single sample method increases the receiver tolerance to clock
- deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */
+ uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote
+ is selected. Selecting the single sample method increases
+ the receiver tolerance to clock deviations. This parameter can be a value
+ of @ref SMARTCARD_OneBit_Sampling. */
uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler.
- This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied
- by 2 to give the division factor of the source clock frequency */
+ This parameter can be any value from 0x01 to 0x1F. Prescaler value is
+ multiplied by 2 to give the division factor of the source clock frequency */
uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */
@@ -143,14 +144,16 @@
uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
This parameter can be a value of @ref SMARTCARD_MSB_First */
- uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when
- relevant flag is available) or once guard time period has elapsed.
- This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */
+ uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when
+ relevant flag is available) or once guard time period has elapsed.
+ This parameter can be a value
+ of @ref SMARTCARDEx_Transmission_Completion_Indication. */
} SMARTCARD_AdvFeatureInitTypeDef;
/**
* @brief HAL SMARTCARD State definition
- * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState (see @ref SMARTCARD_State_Definition).
+ * @note HAL SMARTCARD State value is a combination of 2 different substates:
+ * gState and RxState (see @ref SMARTCARD_State_Definition).
* - gState contains SMARTCARD state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
@@ -200,7 +203,7 @@
SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */
- uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */
+ const uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */
uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */
@@ -218,7 +221,8 @@
uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */
uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used.
- This parameter can be a value of @ref SMARTCARDEx_FIFO_mode. */
+ This parameter can be a value of
+ @ref SMARTCARDEx_FIFO_mode. */
#endif /* USART_CR1_FIFOEN */
void (*RxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
@@ -231,12 +235,14 @@
HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management
- and also related to Tx operations.
- This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
+ __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global
+ Handle management and also related to Tx operations.
+ This parameter can be a value
+ of @ref HAL_SMARTCARD_StateTypeDef */
__IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations.
- This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
+ This parameter can be a value
+ of @ref HAL_SMARTCARD_StateTypeDef */
__IO uint32_t ErrorCode; /*!< SmartCard Error code */
@@ -320,23 +326,26 @@
/** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition
* @{
*/
-#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized
- Value is allowed for gState and RxState */
-#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use
- Value is allowed for gState and RxState */
+#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized. Value
+ is allowed for gState and RxState */
+#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for
+ use. Value is allowed for gState
+ and RxState */
#define HAL_SMARTCARD_STATE_BUSY 0x00000024U /*!< an internal process is ongoing
- Value is allowed for gState only */
+ Value is allowed for gState only */
#define HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing
- Value is allowed for gState only */
+ Value is allowed for gState only */
#define HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
Value is allowed for RxState only */
-#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
- Not to be used for neither gState nor RxState.
- Value is result of combination (Or) between gState and RxState values */
+#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception
+ process is ongoing Not to be used for
+ neither gState nor RxState.
+ Value is result of combination (Or)
+ between gState and RxState values */
#define HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
- Value is allowed for gState only */
+ Value is allowed for gState only */
#define HAL_SMARTCARD_STATE_ERROR 0x000000E0U /*!< Error
- Value is allowed for gState only */
+ Value is allowed for gState only */
/**
* @}
*/
@@ -344,15 +353,15 @@
/** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition
* @{
*/
-#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
-#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
-#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */
-#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
-#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
-#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver TimeOut error */
+#define HAL_SMARTCARD_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_SMARTCARD_ERROR_PE (0x00000001U) /*!< Parity error */
+#define HAL_SMARTCARD_ERROR_NE (0x00000002U) /*!< Noise error */
+#define HAL_SMARTCARD_ERROR_FE (0x00000004U) /*!< frame error */
+#define HAL_SMARTCARD_ERROR_ORE (0x00000008U) /*!< Overrun error */
+#define HAL_SMARTCARD_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_SMARTCARD_ERROR_RTO (0x00000020U) /*!< Receiver TimeOut error */
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
+#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/**
* @}
@@ -676,7 +685,8 @@
* @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
* @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
* @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
- * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
+ * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before
+ * guard time interrupt (when interruption available)
* @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
* @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
* @arg @ref SMARTCARD_IT_PE Parity error interrupt
@@ -689,9 +699,16 @@
* @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
* @retval None
*/
-#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
+#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 1U)?\
+ ((__HANDLE__)->Instance->CR1 |= (1UL <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))):\
+ ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 2U)?\
+ ((__HANDLE__)->Instance->CR2 |= (1UL <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= (1UL <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
/** @brief Disable the specified SmartCard interrupt.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@@ -701,7 +718,8 @@
* @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
* @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
* @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
- * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
+ * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard
+ * time interrupt (when interruption available)
* @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
* @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
* @arg @ref SMARTCARD_IT_PE Parity error interrupt
@@ -714,9 +732,16 @@
* @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
* @retval None
*/
-#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
+#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 1U)?\
+ ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 2U)?\
+ ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
/** @brief Check whether the specified SmartCard interrupt has occurred or not.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@@ -726,7 +751,8 @@
* @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
* @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
* @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
- * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
+ * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time
+ * interrupt (when interruption available)
* @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
* @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
* @arg @ref SMARTCARD_IT_PE Parity error interrupt
@@ -739,8 +765,10 @@
* @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
-#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
- & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET)
+#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) (\
+ (((__HANDLE__)->Instance->ISR & (0x01UL << (((__INTERRUPT__)\
+ & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS)))!= 0U)\
+ ? SET : RESET)
/** @brief Check whether the specified SmartCard interrupt source is enabled or not.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@@ -750,7 +778,8 @@
* @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
* @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
* @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
- * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
+ * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time
+ * interrupt (when interruption available)
* @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
* @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
* @arg @ref SMARTCARD_IT_PE Parity error interrupt
@@ -763,9 +792,16 @@
* @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
-#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
- (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
- (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET)
+#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 0x01U)?\
+ (__HANDLE__)->Instance->CR1 : \
+ (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 0x02U)?\
+ (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) &\
+ (0x01UL << (((uint16_t)(__INTERRUPT__))\
+ & SMARTCARD_IT_MASK))) != 0U)\
+ ? SET : RESET)
/** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@@ -1167,7 +1203,8 @@
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
- HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
+ HAL_SMARTCARD_CallbackIDTypeDef CallbackID,
+ pSMARTCARD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
@@ -1181,13 +1218,13 @@
* @{
*/
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
/* Transfer Abort functions */
HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard);
@@ -1239,4 +1276,3 @@
#endif /* STM32L4xx_HAL_SMARTCARD_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_smartcard_ex.h b/Inc/stm32l4xx_hal_smartcard_ex.h
index be029f8..85ba88f 100644
--- a/Inc/stm32l4xx_hal_smartcard_ex.h
+++ b/Inc/stm32l4xx_hal_smartcard_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -386,4 +385,3 @@
#endif /* STM32L4xx_HAL_SMARTCARD_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_smbus.h b/Inc/stm32l4xx_hal_smbus.h
index dfb422e..83ff066 100644
--- a/Inc/stm32l4xx_hal_smbus.h
+++ b/Inc/stm32l4xx_hal_smbus.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -27,7 +26,6 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
-#include "stm32l4xx_hal_smbus_ex.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
@@ -49,42 +47,43 @@
typedef struct
{
uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value.
- This parameter calculated by referring to SMBUS initialization
- section in Reference manual */
+ This parameter calculated by referring to SMBUS initialization section
+ in Reference manual */
uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
- This parameter can be a value of @ref SMBUS_Analog_Filter */
+ This parameter can be a value of @ref SMBUS_Analog_Filter */
uint32_t OwnAddress1; /*!< Specifies the first device own address.
- This parameter can be a 7-bit or 10-bit address. */
+ This parameter can be a 7-bit or 10-bit address. */
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
- This parameter can be a value of @ref SMBUS_addressing_mode */
+ This parameter can be a value of @ref SMBUS_addressing_mode */
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
- This parameter can be a value of @ref SMBUS_dual_addressing_mode */
+ This parameter can be a value of @ref SMBUS_dual_addressing_mode */
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
- This parameter can be a 7-bit address. */
+ This parameter can be a 7-bit address. */
- uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
- This parameter can be a value of @ref SMBUS_own_address2_masks. */
+ uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address
+ if dual addressing mode is selected
+ This parameter can be a value of @ref SMBUS_own_address2_masks. */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
- This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
+ This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
- This parameter can be a value of @ref SMBUS_nostretch_mode */
+ This parameter can be a value of @ref SMBUS_nostretch_mode */
uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
- This parameter can be a value of @ref SMBUS_packet_error_check_mode */
+ This parameter can be a value of @ref SMBUS_packet_error_check_mode */
uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
- This parameter can be a value of @ref SMBUS_peripheral_mode */
+ This parameter can be a value of @ref SMBUS_peripheral_mode */
uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
- (Enable bits and different timeout values)
- This parameter calculated by referring to SMBUS initialization
- section in Reference manual */
+ (Enable bits and different timeout values)
+ This parameter calculated by referring to SMBUS initialization section
+ in Reference manual */
} SMBUS_InitTypeDef;
/**
* @}
@@ -103,7 +102,7 @@
#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
-#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
+#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
/**
* @}
*/
@@ -122,7 +121,7 @@
#define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */
#define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
+#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
#define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
/**
@@ -160,17 +159,26 @@
__IO uint32_t ErrorCode; /*!< SMBUS Error code */
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
- void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Tx Transfer completed callback */
- void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Rx Transfer completed callback */
- void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Tx Transfer completed callback */
- void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Rx Transfer completed callback */
- void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Listen Complete callback */
- void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Error callback */
+ void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+ /*!< SMBUS Master Tx Transfer completed callback */
+ void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+ /*!< SMBUS Master Rx Transfer completed callback */
+ void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+ /*!< SMBUS Slave Tx Transfer completed callback */
+ void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+ /*!< SMBUS Slave Rx Transfer completed callback */
+ void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+ /*!< SMBUS Listen Complete callback */
+ void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+ /*!< SMBUS Error callback */
- void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< SMBUS Slave Address Match callback */
+ void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
+ /*!< SMBUS Slave Address Match callback */
- void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp Init callback */
- void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp DeInit callback */
+ void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+ /*!< SMBUS Msp Init callback */
+ void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+ /*!< SMBUS Msp DeInit callback */
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
} SMBUS_HandleTypeDef;
@@ -196,8 +204,11 @@
/**
* @brief HAL SMBUS Callback pointer definition
*/
-typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); /*!< pointer to an SMBUS callback function */
-typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an SMBUS Address Match callback function */
+typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus);
+/*!< pointer to an SMBUS callback function */
+typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection,
+ uint16_t AddrMatchCode);
+/*!< pointer to an SMBUS Address Match callback function */
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
/**
@@ -359,9 +370,10 @@
#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
#define SMBUS_IT_RXI I2C_CR1_RXIE
#define SMBUS_IT_TXI I2C_CR1_TXIE
-#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | \
- SMBUS_IT_TXI)
-#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
+#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \
+ SMBUS_IT_NACKI | SMBUS_IT_TXI)
+#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \
+ SMBUS_IT_RXI)
#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
/**
@@ -409,14 +421,14 @@
* @retval None
*/
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \
+#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
-#endif
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
/** @brief Enable the specified SMBUS interrupts.
* @param __HANDLE__ specifies the SMBUS Handle.
@@ -492,12 +504,14 @@
*/
#define SMBUS_FLAG_MASK (0x0001FFFFU)
#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \
- (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
+ (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
+ ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__ specifies the SMBUS Handle.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
+ * @arg @ref SMBUS_FLAG_TXE Transmit data register empty
* @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
* @arg @ref SMBUS_FLAG_AF NACK received flag
* @arg @ref SMBUS_FLAG_STOPF STOP detection flag
@@ -510,7 +524,9 @@
*
* @retval None
*/
-#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == SMBUS_FLAG_TXE) ? \
+ ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
+ ((__HANDLE__)->Instance->ICR = (__FLAG__)))
/** @brief Enable the specified SMBUS peripheral.
* @param __HANDLE__ specifies the SMBUS Handle.
@@ -575,43 +591,52 @@
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
-#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
- ((MODE) == SMBUS_AUTOEND_MODE) || \
- ((MODE) == SMBUS_SOFTEND_MODE) || \
- ((MODE) == SMBUS_SENDPEC_MODE) || \
- ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
- ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
- ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
- ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
+#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
+ ((MODE) == SMBUS_AUTOEND_MODE) || \
+ ((MODE) == SMBUS_SOFTEND_MODE) || \
+ ((MODE) == SMBUS_SENDPEC_MODE) || \
+ ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
+ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
+ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
+ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \
+ SMBUS_RELOAD_MODE )))
#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
- ((REQUEST) == SMBUS_GENERATE_START_READ) || \
- ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
+ ((REQUEST) == SMBUS_GENERATE_START_READ) || \
+ ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
((REQUEST) == SMBUS_NO_STARTSTOP))
-#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
- ((REQUEST) == SMBUS_FIRST_FRAME) || \
- ((REQUEST) == SMBUS_NEXT_FRAME) || \
- ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
- ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
- ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \
- ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
- ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
+#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
+ ((REQUEST) == SMBUS_FIRST_FRAME) || \
+ ((REQUEST) == SMBUS_NEXT_FRAME) || \
+ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \
+ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
+ ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
-#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
- ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
- ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \
+#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
-#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \
- (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
-#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
- (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \
+ (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \
+ I2C_CR1_PECEN)))
+#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
+ (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
+ I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
+ I2C_CR2_RD_WRN)))
-#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
- (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
+ (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
+ (~I2C_CR2_RD_WRN)) : \
+ (uint32_t)((((uint32_t)(__ADDRESS__) & \
+ (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \
+ (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
@@ -630,6 +655,9 @@
* @}
*/
+/* Include SMBUS HAL Extended module */
+#include "stm32l4xx_hal_smbus_ex.h"
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
* @{
@@ -649,11 +677,14 @@
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID,
+HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus,
+ HAL_SMBUS_CallbackIDTypeDef CallbackID,
pSMBUS_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus,
+ HAL_SMBUS_CallbackIDTypeDef CallbackID);
-HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus,
+ pSMBUS_AddrCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
/**
@@ -679,10 +710,10 @@
* @{
*/
/******* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
- uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
- uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
+ uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
+ uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
@@ -758,5 +789,3 @@
#endif /* STM32L4xx_HAL_SMBUS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_smbus_ex.h b/Inc/stm32l4xx_hal_smbus_ex.h
index 702058f..95efcb8 100644
--- a/Inc/stm32l4xx_hal_smbus_ex.h
+++ b/Inc/stm32l4xx_hal_smbus_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -37,7 +36,6 @@
*/
/* Exported types ------------------------------------------------------------*/
-
/* Exported constants --------------------------------------------------------*/
/** @defgroup SMBUSEx_Exported_Constants SMBUS Extended Exported Constants
* @{
@@ -55,19 +53,19 @@
#else
#define SMBUS_FASTMODEPLUS_PB8 (uint32_t)(0x00000010U | SMBUS_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB8 not supported */
#define SMBUS_FASTMODEPLUS_PB9 (uint32_t)(0x00000012U | SMBUS_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB9 not supported */
-#endif
+#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
#define SMBUS_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
#if defined(SYSCFG_CFGR1_I2C2_FMP)
#define SMBUS_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
#else
#define SMBUS_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | SMBUS_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */
-#endif
+#endif /* SYSCFG_CFGR1_I2C2_FMP */
#define SMBUS_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
#if defined(SYSCFG_CFGR1_I2C4_FMP)
#define SMBUS_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
#else
#define SMBUS_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | SMBUS_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported */
-#endif
+#endif /* SYSCFG_CFGR1_I2C4_FMP */
/**
* @}
*/
@@ -90,7 +88,17 @@
* @{
*/
-/** @addtogroup SMBUSEx_Exported_Functions_Group3 SMBUS Extended FastModePlus Functions
+/** @addtogroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions
+ * @{
+ */
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus);
+/**
+ * @}
+ */
+
+/** @addtogroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions
* @{
*/
void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
@@ -117,13 +125,13 @@
* @{
*/
#define IS_SMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & SMBUS_FMP_NOT_SUPPORTED) != SMBUS_FMP_NOT_SUPPORTED) && \
- ((((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB6)) == SMBUS_FASTMODEPLUS_PB6) || \
- (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB7)) == SMBUS_FASTMODEPLUS_PB7) || \
- (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB8)) == SMBUS_FASTMODEPLUS_PB8) || \
- (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB9)) == SMBUS_FASTMODEPLUS_PB9) || \
- (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C1)) == SMBUS_FASTMODEPLUS_I2C1) || \
- (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C2)) == SMBUS_FASTMODEPLUS_I2C2) || \
- (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C3)) == SMBUS_FASTMODEPLUS_I2C3) || \
+ ((((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB6)) == SMBUS_FASTMODEPLUS_PB6) || \
+ (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB7)) == SMBUS_FASTMODEPLUS_PB7) || \
+ (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB8)) == SMBUS_FASTMODEPLUS_PB8) || \
+ (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB9)) == SMBUS_FASTMODEPLUS_PB9) || \
+ (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C1)) == SMBUS_FASTMODEPLUS_I2C1) || \
+ (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C2)) == SMBUS_FASTMODEPLUS_I2C2) || \
+ (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C3)) == SMBUS_FASTMODEPLUS_I2C3) || \
(((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C4)) == SMBUS_FASTMODEPLUS_I2C4)))
/**
* @}
@@ -151,5 +159,3 @@
#endif
#endif /* STM32L4xx_HAL_SMBUS_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_spi.h b/Inc/stm32l4xx_hal_spi.h
index 1eb436b..a7b6b2a 100644
--- a/Inc/stm32l4xx_hal_spi.h
+++ b/Inc/stm32l4xx_hal_spi.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -778,7 +777,8 @@
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
+ pSPI_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/**
@@ -849,4 +849,3 @@
#endif /* STM32L4xx_HAL_SPI_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_spi_ex.h b/Inc/stm32l4xx_hal_spi_ex.h
index ce59e85..359d30e 100644
--- a/Inc/stm32l4xx_hal_spi_ex.h
+++ b/Inc/stm32l4xx_hal_spi_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -72,4 +71,3 @@
#endif /* STM32L4xx_HAL_SPI_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_sram.h b/Inc/stm32l4xx_hal_sram.h
index 410a00f..a654be2 100644
--- a/Inc/stm32l4xx_hal_sram.h
+++ b/Inc/stm32l4xx_hal_sram.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -231,5 +230,3 @@
#endif
#endif /* STM32L4xx_HAL_SRAM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_swpmi.h b/Inc/stm32l4xx_hal_swpmi.h
index 514c5ba..586259c 100644
--- a/Inc/stm32l4xx_hal_swpmi.h
+++ b/Inc/stm32l4xx_hal_swpmi.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -22,7 +21,7 @@
#define STM32L4xx_HAL_SWPMI_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -63,7 +62,7 @@
uint32_t RxBufferingMode; /*!< Specifies the reception buffering mode.
This parameter can be a value of @ref SWPMI_Rx_Buffering_Mode */
-}SWPMI_InitTypeDef;
+} SWPMI_InitTypeDef;
/**
@@ -79,7 +78,7 @@
HAL_SWPMI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
HAL_SWPMI_STATE_TIMEOUT = 0x03, /*!< Timeout state */
HAL_SWPMI_STATE_ERROR = 0x04 /*!< Error */
-}HAL_SWPMI_StateTypeDef;
+} HAL_SWPMI_StateTypeDef;
/**
* @brief SWPMI handle Structure definition
@@ -117,16 +116,16 @@
__IO uint32_t ErrorCode; /*!< SWPMI Error code */
#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
- void (*RxCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI receive complete callback */
- void (*RxHalfCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI receive half complete callback */
- void (*TxCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI transmit complete callback */
- void (*TxHalfCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI transmit half complete callback */
- void (*ErrorCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI error callback */
- void (*MspInitCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP init callback */
- void (*MspDeInitCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP de-init callback */
+ void (*RxCpltCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI receive complete callback */
+ void (*RxHalfCpltCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI receive half complete callback */
+ void (*TxCpltCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI transmit complete callback */
+ void (*TxHalfCpltCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI transmit half complete callback */
+ void (*ErrorCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI error callback */
+ void (*MspInitCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP init callback */
+ void (*MspDeInitCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP de-init callback */
#endif
-}SWPMI_HandleTypeDef;
+} SWPMI_HandleTypeDef;
#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
/**
@@ -141,7 +140,7 @@
HAL_SWPMI_ERROR_CB_ID = 0x04U, /*!< SWPMI error callback ID */
HAL_SWPMI_MSPINIT_CB_ID = 0x05U, /*!< SWPMI MSP init callback ID */
HAL_SWPMI_MSPDEINIT_CB_ID = 0x06U /*!< SWPMI MSP de-init callback ID */
-}HAL_SWPMI_CallbackIDTypeDef;
+} HAL_SWPMI_CallbackIDTypeDef;
/**
* @brief SWPMI callback pointer definition
@@ -495,5 +494,3 @@
#endif
#endif /* STM32L4xx_HAL_SWPMI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_tim.h b/Inc/stm32l4xx_hal_tim.h
index f1d40b7..a1768ed 100644
--- a/Inc/stm32l4xx_hal_tim.h
+++ b/Inc/stm32l4xx_hal_tim.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -65,8 +64,10 @@
This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
- GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
- Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+ GP timers: this parameter must be a number between Min_Data = 0x00 and
+ Max_Data = 0xFF.
+ Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
+ Max_Data = 0xFFFF. */
uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
This parameter can be a value of @ref TIM_AutoReloadPreload */
@@ -218,7 +219,8 @@
uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
This parameter can be a value of @ref TIM_ClearInput_Polarity */
uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
- This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+ This parameter must be 0: When OCRef clear feature is used with ETR source,
+ ETR prescaler must be off */
uint32_t ClearInputFilter; /*!< TIM Clear Input filter
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_ClearInputConfigTypeDef;
@@ -268,28 +270,28 @@
*/
typedef struct
{
- uint32_t OffStateRunMode; /*!< TIM off state in run mode
- This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
- uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
- This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
- uint32_t LockLevel; /*!< TIM Lock level
- This parameter can be a value of @ref TIM_Lock_level */
- uint32_t DeadTime; /*!< TIM dead Time
- This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
- uint32_t BreakState; /*!< TIM Break State
- This parameter can be a value of @ref TIM_Break_Input_enable_disable */
- uint32_t BreakPolarity; /*!< TIM Break input polarity
- This parameter can be a value of @ref TIM_Break_Polarity */
- uint32_t BreakFilter; /*!< Specifies the break input filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
- uint32_t Break2State; /*!< TIM Break2 State
- This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
- uint32_t Break2Polarity; /*!< TIM Break2 input polarity
- This parameter can be a value of @ref TIM_Break2_Polarity */
- uint32_t Break2Filter; /*!< TIM break2 input filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
- uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
- This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+ uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+
+ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+
+ uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */
+
+ uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+
+ uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+
+ uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */
+
+ uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+ uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
+
+ uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */
+
+ uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+
} TIM_BreakDeadTimeConfigTypeDef;
/**
@@ -659,10 +661,8 @@
/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
* @{
*/
-#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */
#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
/**
* @}
@@ -901,19 +901,18 @@
* @{
*/
#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
-#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
- (if none of the break inputs BRK and BRK2 is active) */
+#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */
/**
* @}
*/
-/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
+/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3
* @{
*/
-#define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
-#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
-#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
-#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
+#define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
+#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
+#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
+#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
/**
* @}
*/
@@ -1202,7 +1201,8 @@
* @brief Disable the TIM main Output.
* @param __HANDLE__ TIM handle
* @retval None
- * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
+ * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been
+ * disabled
*/
#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
do { \
@@ -1369,7 +1369,8 @@
/**
* @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
- * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
+ * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
+ * in an atomic way.
* @param __HANDLE__ TIM handle.
* @retval None
mode.
@@ -1396,8 +1397,8 @@
* @brief Indicates whether or not the TIM Counter is used as downcounter.
* @param __HANDLE__ TIM handle.
* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
- * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
-mode.
+ * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode
+ * or Encoder mode.
*/
#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
@@ -1411,7 +1412,8 @@
/**
* @brief Set the TIM Counter Register value on runtime.
- * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance.
+ * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in
+ * case of 32 bits counter TIM instance.
* Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
* @param __HANDLE__ TIM handle.
* @param __COUNTER__ specifies the Counter register new value.
@@ -1473,7 +1475,8 @@
#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
/**
- * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
+ * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel()
+ * function.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
@@ -2042,13 +2045,19 @@
((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))
#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
- (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \
- } while(0)
+ (__HANDLE__)->ChannelState[0] = \
+ (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[1] = \
+ (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[2] = \
+ (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[3] = \
+ (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[4] = \
+ (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[5] = \
+ (__CHANNEL_STATE__); \
+ } while(0)
#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
@@ -2063,11 +2072,15 @@
((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
- (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \
- } while(0)
+ (__HANDLE__)->ChannelNState[0] = \
+ (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelNState[1] = \
+ (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelNState[2] = \
+ (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelNState[3] = \
+ (__CHANNEL_STATE__); \
+ } while(0)
/**
* @}
@@ -2241,14 +2254,14 @@
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
- uint32_t DataLength);
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+ uint32_t BurstLength, uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
- uint32_t DataLength);
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+ uint32_t BurstLength, uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
@@ -2346,5 +2359,3 @@
#endif
#endif /* STM32L4xx_HAL_TIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_tim_ex.h b/Inc/stm32l4xx_hal_tim_ex.h
index b699a5a..a5ba3a5 100644
--- a/Inc/stm32l4xx_hal_tim_ex.h
+++ b/Inc/stm32l4xx_hal_tim_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -72,8 +71,7 @@
uint32_t Polarity; /*!< Specifies the break input source polarity.
This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
Not relevant when analog watchdog output of the DFSDM1 used as break input source */
-}
-TIMEx_BreakInputConfigTypeDef;
+} TIMEx_BreakInputConfigTypeDef;
/**
* @}
@@ -193,8 +191,8 @@
/** @defgroup TIMEx_Break_Input TIM Extended Break input
* @{
*/
-#define TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */
-#define TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */
+#define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */
+#define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */
/**
* @}
*/
@@ -215,8 +213,8 @@
/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
* @{
*/
-#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */
-#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */
+#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /*!< Break input source is disabled */
+#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /*!< Break input source is enabled */
/**
* @}
*/
@@ -224,8 +222,8 @@
/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
* @{
*/
-#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */
-#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */
+#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /*!< Break input source is active low */
+#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /*!< Break input source is active_high */
/**
* @}
*/
@@ -413,7 +411,7 @@
/* End of exported functions -------------------------------------------------*/
/* Private functions----------------------------------------------------------*/
-/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
+/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions
* @{
*/
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
@@ -437,5 +435,3 @@
#endif /* STM32L4xx_HAL_TIM_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_tsc.h b/Inc/stm32l4xx_hal_tsc.h
index 12f9a7b..3cd7887 100644
--- a/Inc/stm32l4xx_hal_tsc.h
+++ b/Inc/stm32l4xx_hal_tsc.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -137,16 +136,16 @@
TSC_GROUP4_IDX,
#if defined(TSC_IOCCR_G5_IO1)
TSC_GROUP5_IDX,
-#endif
+#endif /* TSC_IOCCR_G5_IO1 */
#if defined(TSC_IOCCR_G6_IO1)
TSC_GROUP6_IDX,
-#endif
+#endif /* TSC_IOCCR_G6_IO1 */
#if defined(TSC_IOCCR_G7_IO1)
TSC_GROUP7_IDX,
-#endif
+#endif /* TSC_IOCCR_G7_IO1 */
#if defined(TSC_IOCCR_G8_IO1)
TSC_GROUP8_IDX,
-#endif
+#endif /* TSC_IOCCR_G8_IO1 */
TSC_NB_OF_GROUPS
};
@@ -195,22 +194,38 @@
/** @defgroup TSC_CTPulseHL_Config CTPulse High Length
* @{
*/
-#define TSC_CTPH_1CYCLE 0x00000000UL /*!< Charge transfer pulse high during 1 cycle (PGCLK) */
-#define TSC_CTPH_2CYCLES TSC_CR_CTPH_0 /*!< Charge transfer pulse high during 2 cycles (PGCLK) */
-#define TSC_CTPH_3CYCLES TSC_CR_CTPH_1 /*!< Charge transfer pulse high during 3 cycles (PGCLK) */
-#define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 4 cycles (PGCLK) */
-#define TSC_CTPH_5CYCLES TSC_CR_CTPH_2 /*!< Charge transfer pulse high during 5 cycles (PGCLK) */
-#define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 6 cycles (PGCLK) */
-#define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 7 cycles (PGCLK) */
-#define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 8 cycles (PGCLK) */
-#define TSC_CTPH_9CYCLES TSC_CR_CTPH_3 /*!< Charge transfer pulse high during 9 cycles (PGCLK) */
-#define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 10 cycles (PGCLK) */
-#define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 11 cycles (PGCLK) */
-#define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 12 cycles (PGCLK) */
-#define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2) /*!< Charge transfer pulse high during 13 cycles (PGCLK) */
-#define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 14 cycles (PGCLK) */
-#define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 15 cycles (PGCLK) */
-#define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 16 cycles (PGCLK) */
+#define TSC_CTPH_1CYCLE 0x00000000UL
+/*!< Charge transfer pulse high during 1 cycle (PGCLK) */
+#define TSC_CTPH_2CYCLES TSC_CR_CTPH_0
+/*!< Charge transfer pulse high during 2 cycles (PGCLK) */
+#define TSC_CTPH_3CYCLES TSC_CR_CTPH_1
+/*!< Charge transfer pulse high during 3 cycles (PGCLK) */
+#define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0)
+/*!< Charge transfer pulse high during 4 cycles (PGCLK) */
+#define TSC_CTPH_5CYCLES TSC_CR_CTPH_2
+/*!< Charge transfer pulse high during 5 cycles (PGCLK) */
+#define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0)
+/*!< Charge transfer pulse high during 6 cycles (PGCLK) */
+#define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1)
+/*!< Charge transfer pulse high during 7 cycles (PGCLK) */
+#define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0)
+/*!< Charge transfer pulse high during 8 cycles (PGCLK) */
+#define TSC_CTPH_9CYCLES TSC_CR_CTPH_3
+/*!< Charge transfer pulse high during 9 cycles (PGCLK) */
+#define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0)
+/*!< Charge transfer pulse high during 10 cycles (PGCLK) */
+#define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1)
+/*!< Charge transfer pulse high during 11 cycles (PGCLK) */
+#define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0)
+/*!< Charge transfer pulse high during 12 cycles (PGCLK) */
+#define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2)
+/*!< Charge transfer pulse high during 13 cycles (PGCLK) */
+#define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0)
+/*!< Charge transfer pulse high during 14 cycles (PGCLK) */
+#define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1)
+/*!< Charge transfer pulse high during 15 cycles (PGCLK) */
+#define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0)
+/*!< Charge transfer pulse high during 16 cycles (PGCLK) */
/**
* @}
*/
@@ -218,22 +233,38 @@
/** @defgroup TSC_CTPulseLL_Config CTPulse Low Length
* @{
*/
-#define TSC_CTPL_1CYCLE 0x00000000UL /*!< Charge transfer pulse low during 1 cycle (PGCLK) */
-#define TSC_CTPL_2CYCLES TSC_CR_CTPL_0 /*!< Charge transfer pulse low during 2 cycles (PGCLK) */
-#define TSC_CTPL_3CYCLES TSC_CR_CTPL_1 /*!< Charge transfer pulse low during 3 cycles (PGCLK) */
-#define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 4 cycles (PGCLK) */
-#define TSC_CTPL_5CYCLES TSC_CR_CTPL_2 /*!< Charge transfer pulse low during 5 cycles (PGCLK) */
-#define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 6 cycles (PGCLK) */
-#define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 7 cycles (PGCLK) */
-#define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 8 cycles (PGCLK) */
-#define TSC_CTPL_9CYCLES TSC_CR_CTPL_3 /*!< Charge transfer pulse low during 9 cycles (PGCLK) */
-#define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 10 cycles (PGCLK) */
-#define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 11 cycles (PGCLK) */
-#define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 12 cycles (PGCLK) */
-#define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2) /*!< Charge transfer pulse low during 13 cycles (PGCLK) */
-#define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 14 cycles (PGCLK) */
-#define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 15 cycles (PGCLK) */
-#define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 16 cycles (PGCLK) */
+#define TSC_CTPL_1CYCLE 0x00000000UL
+/*!< Charge transfer pulse low during 1 cycle (PGCLK) */
+#define TSC_CTPL_2CYCLES TSC_CR_CTPL_0
+/*!< Charge transfer pulse low during 2 cycles (PGCLK) */
+#define TSC_CTPL_3CYCLES TSC_CR_CTPL_1
+/*!< Charge transfer pulse low during 3 cycles (PGCLK) */
+#define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
+/*!< Charge transfer pulse low during 4 cycles (PGCLK) */
+#define TSC_CTPL_5CYCLES TSC_CR_CTPL_2
+/*!< Charge transfer pulse low during 5 cycles (PGCLK) */
+#define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0)
+/*!< Charge transfer pulse low during 6 cycles (PGCLK) */
+#define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1)
+/*!< Charge transfer pulse low during 7 cycles (PGCLK) */
+#define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
+/*!< Charge transfer pulse low during 8 cycles (PGCLK) */
+#define TSC_CTPL_9CYCLES TSC_CR_CTPL_3
+/*!< Charge transfer pulse low during 9 cycles (PGCLK) */
+#define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0)
+/*!< Charge transfer pulse low during 10 cycles (PGCLK) */
+#define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1)
+/*!< Charge transfer pulse low during 11 cycles (PGCLK) */
+#define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
+/*!< Charge transfer pulse low during 12 cycles (PGCLK) */
+#define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2)
+/*!< Charge transfer pulse low during 13 cycles (PGCLK) */
+#define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0)
+/*!< Charge transfer pulse low during 14 cycles (PGCLK) */
+#define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1)
+/*!< Charge transfer pulse low during 15 cycles (PGCLK) */
+#define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
+/*!< Charge transfer pulse low during 16 cycles (PGCLK) */
/**
* @}
*/
@@ -297,8 +328,11 @@
/** @defgroup TSC_Acquisition_Mode Acquisition Mode
* @{
*/
-#define TSC_ACQ_MODE_NORMAL 0x00000000UL /*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */
-#define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM /*!< Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) */
+#define TSC_ACQ_MODE_NORMAL 0x00000000UL
+/*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */
+#define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM
+/*!< Synchronized acquisition mode (acquisition starts if START bit is set and
+when the selected signal is detected on the SYNC input pin) */
/**
* @}
*/
@@ -330,16 +364,16 @@
#define TSC_GROUP4 (0x1UL << TSC_GROUP4_IDX)
#if defined(TSC_IOCCR_G5_IO1)
#define TSC_GROUP5 (0x1UL << TSC_GROUP5_IDX)
-#endif
+#endif /* TSC_IOCCR_G5_IO1 */
#if defined(TSC_IOCCR_G6_IO1)
#define TSC_GROUP6 (0x1UL << TSC_GROUP6_IDX)
-#endif
+#endif /* TSC_IOCCR_G6_IO1 */
#if defined(TSC_IOCCR_G7_IO1)
#define TSC_GROUP7 (0x1UL << TSC_GROUP7_IDX)
-#endif
+#endif /* TSC_IOCCR_G7_IO1 */
#if defined(TSC_IOCCR_G8_IO1)
#define TSC_GROUP8 (0x1UL << TSC_GROUP8_IDX)
-#endif
+#endif /* TSC_IOCCR_G8_IO1 */
#define TSC_GROUPX_NOT_SUPPORTED 0xFF000000UL /*!< TSC GroupX not supported */
@@ -374,7 +408,7 @@
#define TSC_GROUP5_IO2 TSC_GROUP5_IO1 /*!< TSC Group5 IO2 not supported */
#define TSC_GROUP5_IO3 TSC_GROUP5_IO1 /*!< TSC Group5 IO3 not supported */
#define TSC_GROUP5_IO4 TSC_GROUP5_IO1 /*!< TSC Group5 IO4 not supported */
-#endif
+#endif /* TSC_IOCCR_G5_IO1 */
#if defined(TSC_IOCCR_G6_IO1)
#define TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1 /*!< TSC Group6 IO1 */
@@ -387,7 +421,7 @@
#define TSC_GROUP6_IO2 TSC_GROUP6_IO1 /*!< TSC Group6 IO2 not supported */
#define TSC_GROUP6_IO3 TSC_GROUP6_IO1 /*!< TSC Group6 IO3 not supported */
#define TSC_GROUP6_IO4 TSC_GROUP6_IO1 /*!< TSC Group6 IO4 not supported */
-#endif
+#endif /* TSC_IOCCR_G6_IO1 */
#if defined(TSC_IOCCR_G7_IO1)
#define TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1 /*!< TSC Group7 IO1 */
@@ -400,7 +434,7 @@
#define TSC_GROUP7_IO2 TSC_GROUP7_IO1 /*!< TSC Group7 IO2 not supported */
#define TSC_GROUP7_IO3 TSC_GROUP7_IO1 /*!< TSC Group7 IO3 not supported */
#define TSC_GROUP7_IO4 TSC_GROUP7_IO1 /*!< TSC Group7 IO4 not supported */
-#endif
+#endif /* TSC_IOCCR_G7_IO1 */
#if defined(TSC_IOCCR_G8_IO1)
#define TSC_GROUP8_IO1 TSC_IOCCR_G8_IO1 /*!< TSC Group8 IO1 */
@@ -413,7 +447,7 @@
#define TSC_GROUP8_IO2 TSC_GROUP8_IO1 /*!< TSC Group8 IO2 not supported */
#define TSC_GROUP8_IO3 TSC_GROUP8_IO1 /*!< TSC Group8 IO3 not supported */
#define TSC_GROUP8_IO4 TSC_GROUP8_IO1 /*!< TSC Group8 IO4 not supported */
-#endif
+#endif /* TSC_IOCCR_G8_IO1 */
/**
* @}
*/
@@ -433,14 +467,14 @@
* @retval None
*/
#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
-#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_TSC_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
+#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_TSC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
-#endif
+#endif /* (USE_HAL_TSC_REGISTER_CALLBACKS == 1) */
/**
* @brief Enable the TSC peripheral.
@@ -519,7 +553,9 @@
* @param __INTERRUPT__ TSC interrupt
* @retval SET or RESET
*/
-#define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET :\
+ RESET)
/**
* @brief Check whether the specified TSC flag is set or not.
@@ -527,7 +563,8 @@
* @param __FLAG__ TSC flag
* @retval SET or RESET
*/
-#define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+#define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR\
+ & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
/**
* @brief Clear the TSC's pending flag.
@@ -551,7 +588,8 @@
* @param __GX_IOY_MASK__ IOs mask
* @retval None
*/
-#define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (~(__GX_IOY_MASK__)))
+#define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR\
+ &= (~(__GX_IOY_MASK__)))
/**
* @brief Open analog switch on a group of IOs.
@@ -559,7 +597,8 @@
* @param __GX_IOY_MASK__ IOs mask
* @retval None
*/
-#define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (~(__GX_IOY_MASK__)))
+#define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR\
+ &= (~(__GX_IOY_MASK__)))
/**
* @brief Close analog switch on a group of IOs.
@@ -583,7 +622,8 @@
* @param __GX_IOY_MASK__ IOs mask
* @retval None
*/
-#define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (~(__GX_IOY_MASK__)))
+#define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR\
+ &= (~(__GX_IOY_MASK__)))
/**
* @brief Enable a group of IOs in sampling mode.
@@ -623,7 +663,8 @@
* @retval SET or RESET
*/
#define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \
-((((__HANDLE__)->Instance->IOGCSR & (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) == (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
+ ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) == \
+ (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
/**
* @}
@@ -669,7 +710,8 @@
((__VALUE__) == TSC_CTPL_15CYCLES) || \
((__VALUE__) == TSC_CTPL_16CYCLES))
-#define IS_TSC_SS(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE) || ((FunctionalState)(__VALUE__) == ENABLE))
+#define IS_TSC_SS(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\
+ || ((FunctionalState)(__VALUE__) == ENABLE))
#define IS_TSC_SSD(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < 128UL)))
@@ -684,9 +726,13 @@
((__VALUE__) == TSC_PG_PRESC_DIV64) || \
((__VALUE__) == TSC_PG_PRESC_DIV128))
-#define IS_TSC_PG_PRESC_VS_CTPL(__PGPSC__, __CTPL__) ((((__PGPSC__) == TSC_PG_PRESC_DIV1) && ((__CTPL__) > TSC_CTPL_2CYCLES)) || \
- (((__PGPSC__) == TSC_PG_PRESC_DIV2) && ((__CTPL__) > TSC_CTPL_1CYCLE)) || \
- (((__PGPSC__) > TSC_PG_PRESC_DIV2) && (((__CTPL__) == TSC_CTPL_1CYCLE) || ((__CTPL__) > TSC_CTPL_1CYCLE))))
+#define IS_TSC_PG_PRESC_VS_CTPL(__PGPSC__, __CTPL__) ((((__PGPSC__) == TSC_PG_PRESC_DIV1) && \
+ ((__CTPL__) > TSC_CTPL_2CYCLES)) || \
+ (((__PGPSC__) == TSC_PG_PRESC_DIV2) && \
+ ((__CTPL__) > TSC_CTPL_1CYCLE)) || \
+ (((__PGPSC__) > TSC_PG_PRESC_DIV2) && \
+ (((__CTPL__) == TSC_CTPL_1CYCLE) || \
+ ((__CTPL__) > TSC_CTPL_1CYCLE))))
#define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \
((__VALUE__) == TSC_MCV_511) || \
@@ -698,13 +744,16 @@
#define IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT))
-#define IS_TSC_SYNC_POL(__VALUE__) (((__VALUE__) == TSC_SYNC_POLARITY_FALLING) || ((__VALUE__) == TSC_SYNC_POLARITY_RISING))
+#define IS_TSC_SYNC_POL(__VALUE__) (((__VALUE__) == TSC_SYNC_POLARITY_FALLING)\
+ || ((__VALUE__) == TSC_SYNC_POLARITY_RISING))
#define IS_TSC_ACQ_MODE(__VALUE__) (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO))
-#define IS_TSC_MCE_IT(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE) || ((FunctionalState)(__VALUE__) == ENABLE))
+#define IS_TSC_MCE_IT(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\
+ || ((FunctionalState)(__VALUE__) == ENABLE))
-#define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS)))
+#define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL)\
+ || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS)))
#define IS_TSC_GROUP(__VALUE__) ((((__VALUE__) & TSC_GROUPX_NOT_SUPPORTED) != TSC_GROUPX_NOT_SUPPORTED) && \
@@ -762,7 +811,8 @@
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, pTSC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID,
+ pTSC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
/**
@@ -831,5 +881,3 @@
#endif
#endif /* STM32L4xx_HAL_TSC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_uart.h b/Inc/stm32l4xx_hal_uart.h
index b061dcd..af47468 100644
--- a/Inc/stm32l4xx_hal_uart.h
+++ b/Inc/stm32l4xx_hal_uart.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -46,54 +45,57 @@
*/
typedef struct
{
- uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
- The baud rate register is computed using the following formula:
- LPUART:
- =======
- Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate)))
- where lpuart_ker_ck_pres is the UART input clock
- (divided by a prescaler if applicable)
- UART:
- =====
- - If oversampling is 16 or in LIN mode,
- Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))
- - If oversampling is 8,
- Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[15:4]
- Baud Rate Register[3] = 0
- Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[3:0]) >> 1
- where uart_ker_ck_pres is the UART input clock (divided by a prescaler if applicable) */
+ uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
+ The baud rate register is computed using the following formula:
+ LPUART:
+ =======
+ Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate)))
+ where lpuart_ker_ck_pres is the UART input clock
+ (divided by a prescaler if applicable)
+ UART:
+ =====
+ - If oversampling is 16 or in LIN mode,
+ Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))
+ - If oversampling is 8,
+ Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) /
+ ((huart->Init.BaudRate)))[15:4]
+ Baud Rate Register[3] = 0
+ Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) /
+ ((huart->Init.BaudRate)))[3:0]) >> 1
+ where uart_ker_ck_pres is the UART input clock
+ (divided by a prescaler if applicable) */
- uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref UARTEx_Word_Length. */
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref UARTEx_Word_Length. */
- uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref UART_Stop_Bits. */
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref UART_Stop_Bits. */
- uint32_t Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref UART_Parity
- @note When parity is enabled, the computed parity is inserted
- at the MSB position of the transmitted data (9th bit when
- the word length is set to 9 data bits; 8th bit when the
- word length is set to 8 data bits). */
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref UART_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
- uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref UART_Mode. */
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref UART_Mode. */
- uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
- or disabled.
- This parameter can be a value of @ref UART_Hardware_Flow_Control. */
+ uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
+ or disabled.
+ This parameter can be a value of @ref UART_Hardware_Flow_Control. */
- uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled,
- to achieve higher speed (up to f_PCLK/8).
- This parameter can be a value of @ref UART_Over_Sampling. */
+ uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled,
+ to achieve higher speed (up to f_PCLK/8).
+ This parameter can be a value of @ref UART_Over_Sampling. */
- uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
- Selecting the single sample method increases the receiver tolerance to clock
- deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
+ uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
+ Selecting the single sample method increases the receiver tolerance to clock
+ deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
#if defined(USART_PRESC_PRESCALER)
- uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source.
- This parameter can be a value of @ref UART_ClockPrescaler. */
+ uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source.
+ This parameter can be a value of @ref UART_ClockPrescaler. */
#endif /* USART_PRESC_PRESCALER */
} UART_InitTypeDef;
@@ -215,7 +217,7 @@
UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */
- uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
+ const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
uint16_t TxXferSize; /*!< UART Tx Transfer size */
@@ -309,8 +311,9 @@
/**
* @brief HAL UART Callback pointer definition
*/
-typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
-typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */
+typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
+typedef void (*pUART_RxEventCallbackTypeDef)
+(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
@@ -1166,10 +1169,10 @@
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
-#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
- do{ \
- SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
- (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
+#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
+ do{ \
+ ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
} while(0U)
/** @brief Disable CTS flow control.
@@ -1185,10 +1188,10 @@
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
-#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
- do{ \
- CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
- (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
+#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
+ do{ \
+ ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
} while(0U)
/** @brief Enable RTS flow control.
@@ -1204,10 +1207,10 @@
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
-#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
- do{ \
- SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
- (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
+#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
+ do{ \
+ ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
} while(0U)
/** @brief Disable RTS flow control.
@@ -1223,10 +1226,10 @@
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
-#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
- do{ \
- CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
- (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
+#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
+ do{ \
+ ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
} while(0U)
/**
* @}
@@ -1631,14 +1634,6 @@
/* Include UART HAL Extended module */
#include "stm32l4xx_hal_uart_ex.h"
-#if defined(USART_PRESC_PRESCALER)
-
-/* Prescaler Table used in BRR computation macros.
- Declared as extern here to allow use of private UART macros, outside of HAL UART functions */
-extern const uint16_t UARTPrescTable[12];
-
-#endif /* USART_PRESC_PRESCALER */
-
/* Exported functions --------------------------------------------------------*/
/** @addtogroup UART_Exported_Functions UART Exported Functions
* @{
@@ -1676,11 +1671,11 @@
*/
/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
@@ -1764,6 +1759,19 @@
* @}
*/
+/* Private variables -----------------------------------------------------------*/
+#if defined(USART_PRESC_PRESCALER)
+/** @defgroup UART_Private_variables UART Private variables
+ * @{
+ */
+/* Prescaler Table used in BRR computation macros.
+ Declared as extern here to allow use of private UART macros, outside of HAL UART functions */
+extern const uint16_t UARTPrescTable[12];
+/**
+ * @}
+ */
+
+#endif /* USART_PRESC_PRESCALER */
/**
* @}
*/
@@ -1778,4 +1786,3 @@
#endif /* STM32L4xx_HAL_UART_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_uart_ex.h b/Inc/stm32l4xx_hal_uart_ex.h
index 9ab3741..a44e08d 100644
--- a/Inc/stm32l4xx_hal_uart_ex.h
+++ b/Inc/stm32l4xx_hal_uart_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -100,12 +99,12 @@
* @brief UART TXFIFO threshold level
* @{
*/
-#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */
-#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */
-#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */
-#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */
-#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */
-#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */
+#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */
+#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */
+#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */
+#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */
+#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */
+#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */
/**
* @}
*/
@@ -114,12 +113,12 @@
* @brief UART RXFIFO threshold level
* @{
*/
-#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */
-#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */
-#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */
-#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */
-#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */
-#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */
+#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */
+#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */
+#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */
+#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */
+#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */
+#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */
/**
* @}
*/
@@ -185,7 +184,8 @@
HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
#endif /* USART_CR1_FIFOEN */
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
+ uint32_t Timeout);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
@@ -741,4 +741,3 @@
#endif /* STM32L4xx_HAL_UART_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_usart.h b/Inc/stm32l4xx_hal_usart.h
index a09944f..4064764 100644
--- a/Inc/stm32l4xx_hal_usart.h
+++ b/Inc/stm32l4xx_hal_usart.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -48,11 +47,15 @@
{
uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
The baud rate is computed using the following formula:
- Baud Rate Register[15:4] = ((2 * fclk_pres) / ((huart->Init.BaudRate)))[15:4]
+ Baud Rate Register[15:4] = ((2 * fclk_pres) /
+ ((huart->Init.BaudRate)))[15:4]
Baud Rate Register[3] = 0
- Baud Rate Register[2:0] = (((2 * fclk_pres) / ((huart->Init.BaudRate)))[3:0]) >> 1
- where fclk_pres is the USART input clock frequency (fclk) (divided by a prescaler if applicable)
- @note Oversampling by 8 is systematically applied to achieve high baud rates. */
+ Baud Rate Register[2:0] = (((2 * fclk_pres) /
+ ((huart->Init.BaudRate)))[3:0]) >> 1
+ where fclk_pres is the USART input clock frequency (fclk)
+ (divided by a prescaler if applicable)
+ @note Oversampling by 8 is systematically applied to
+ achieve high baud rates. */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USARTEx_Word_Length. */
@@ -123,7 +126,7 @@
USART_InitTypeDef Init; /*!< USART communication parameters */
- uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */
+ const uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */
uint16_t TxXferSize; /*!< USART Tx Transfer size */
@@ -228,18 +231,19 @@
/** @defgroup USART_Error_Definition USART Error Definition
* @{
*/
-#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_USART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
-#define HAL_USART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
-#define HAL_USART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
-#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
-#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
+#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */
+#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */
+#define HAL_USART_ERROR_FE (0x00000004U) /*!< Frame error */
+#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */
+#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#if defined(USART_CR2_SLVEN)
-#define HAL_USART_ERROR_UDR ((uint32_t)0x00000020U) /*!< SPI slave underrun error */
+#define HAL_USART_ERROR_UDR (0x00000020U) /*!< SPI slave underrun error */
#endif /* USART_CR2_SLVEN */
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-#define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
+#define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+#define HAL_USART_ERROR_RTO (0x00000080U) /*!< Receiver Timeout error */
/**
* @}
*/
@@ -275,15 +279,6 @@
* @}
*/
-/** @defgroup USART_Over_Sampling USART Over Sampling
- * @{
- */
-#define USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */
-#define USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
-/**
- * @}
- */
-
/** @defgroup USART_Clock USART Clock
* @{
*/
@@ -374,6 +369,7 @@
#else
#define USART_FLAG_TXE USART_ISR_TXE /*!< USART transmit data register empty */
#endif /* USART_CR1_FIFOEN */
+#define USART_FLAG_RTOF USART_ISR_RTOF /*!< USART receiver timeout flag */
#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */
#if defined(USART_CR1_FIFOEN)
#define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< USART read data register not empty */
@@ -442,6 +438,7 @@
#if defined(USART_CR1_FIFOEN)
#define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO Empty Clear Flag */
#endif /* USART_CR1_FIFOEN */
+#define USART_CLEAR_RTOF USART_ICR_RTOCF /*!< USART receiver timeout clear flag */
/**
* @}
*/
@@ -498,6 +495,7 @@
* @arg @ref USART_FLAG_TC Transmission Complete flag
* @arg @ref USART_FLAG_RXNE Receive data register not empty flag
* @arg @ref USART_FLAG_RXFNE RXFIFO not empty flag
+ * @arg @ref USART_FLAG_RTOF Receiver Timeout flag
* @arg @ref USART_FLAG_IDLE Idle Line detection flag
* @arg @ref USART_FLAG_ORE OverRun Error flag
* @arg @ref USART_FLAG_NE Noise Error flag
@@ -518,6 +516,7 @@
* @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
* @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag
* @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
+ * @arg @ref USART_CLEAR_RTOF Receiver Timeout clear flag
* @arg @ref USART_CLEAR_UDRF SPI slave underrun error Clear Flag
* @retval None
*/
@@ -587,9 +586,12 @@
* @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))
+#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\
+ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
+ ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
+ ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
/** @brief Disable the specified USART interrupt.
* @param __HANDLE__ specifies the USART Handle.
@@ -609,10 +611,12 @@
* @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))
-
+#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\
+ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
+ ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
+ ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
/** @brief Check whether the specified USART interrupt has occurred or not.
* @param __HANDLE__ specifies the USART Handle.
@@ -635,7 +639,8 @@
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
- & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET)
+ & (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\
+ USART_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified USART interrupt source is enabled or not.
* @param __HANDLE__ specifies the USART Handle.
@@ -657,10 +662,13 @@
* @arg @ref USART_IT_PE Parity Error interrupt
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
-#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \
- (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \
- (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET)
-
+#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\
+ (__HANDLE__)->Instance->CR1 : \
+ (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\
+ (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) & (0x01U <<\
+ (((uint16_t)(__INTERRUPT__)) &\
+ USART_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the USART Handle.
@@ -672,6 +680,7 @@
* @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
* @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag
* @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
+ * @arg @ref USART_CLEAR_RTOF Receiver timeout clear flag
* @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag
* @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
* @retval None
@@ -747,8 +756,9 @@
* @param __CLOCKPRESCALER__ USART prescaler value.
* @retval Division result
*/
-#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\
- + ((__BAUD__)/2U)) / (__BAUD__))
+#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)\
+ (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\
+ + ((__BAUD__)/2U)) / (__BAUD__))
#else
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
* @param __PCLK__ USART clock.
@@ -798,14 +808,6 @@
#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
/**
- * @brief Ensure that USART oversampling is valid.
- * @param __SAMPLING__ USART oversampling.
- * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
- */
-#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
- ((__SAMPLING__) == USART_OVERSAMPLING_8))
-
-/**
* @brief Ensure that USART clock state is valid.
* @param __CLOCK__ USART clock state.
* @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
@@ -901,17 +903,17 @@
*/
/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
@@ -963,4 +965,3 @@
#endif /* STM32L4xx_HAL_USART_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_usart_ex.h b/Inc/stm32l4xx_hal_usart_ex.h
index c59cf4b..e94dce2 100644
--- a/Inc/stm32l4xx_hal_usart_ex.h
+++ b/Inc/stm32l4xx_hal_usart_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,9 +44,9 @@
/** @defgroup USARTEx_Word_Length USARTEx Word Length
* @{
*/
-#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */
-#define USART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long USART frame */
-#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */
+#define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */
+#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
+#define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */
/**
* @}
*/
@@ -112,8 +111,8 @@
/**
* @}
*/
-#endif /* USART_CR1_FIFOEN */
+#endif /* USART_CR1_FIFOEN */
/**
* @}
*/
@@ -301,7 +300,6 @@
} \
} while(0U)
-
/**
* @brief Ensure that USART frame length is valid.
* @param __LENGTH__ USART frame length.
@@ -424,4 +422,3 @@
#endif /* STM32L4xx_HAL_USART_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_hal_wwdg.h b/Inc/stm32l4xx_hal_wwdg.h
index 2d4c642..4b4910e 100644
--- a/Inc/stm32l4xx_hal_wwdg.h
+++ b/Inc/stm32l4xx_hal_wwdg.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -184,7 +183,7 @@
/**
* @brief Enable the WWDG early wakeup interrupt.
- * @param __HANDLE__ WWDG handle
+ * @param __HANDLE__ WWDG handle
* @param __INTERRUPT__ specifies the interrupt to enable.
* This parameter can be one of the following values:
* @arg WWDG_IT_EWI: Early wakeup interrupt
@@ -297,5 +296,3 @@
#endif
#endif /* STM32L4xx_HAL_WWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_adc.h b/Inc/stm32l4xx_ll_adc.h
index 3c44efb..c5efa1d 100644
--- a/Inc/stm32l4xx_ll_adc.h
+++ b/Inc/stm32l4xx_ll_adc.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -5213,7 +5212,7 @@
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
+ ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
- uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
+ uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & ADC_AWD_CR_ALL_CHANNEL_MASK);
/* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */
/* (parameter value LL_ADC_AWD_DISABLE). */
@@ -7456,5 +7455,3 @@
#endif
#endif /* STM32L4xx_LL_ADC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_bus.h b/Inc/stm32l4xx_ll_bus.h
index cf79193..55927f3 100644
--- a/Inc/stm32l4xx_ll_bus.h
+++ b/Inc/stm32l4xx_ll_bus.h
@@ -23,14 +23,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -1954,4 +1952,3 @@
#endif /* STM32L4xx_LL_BUS_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_comp.h b/Inc/stm32l4xx_ll_comp.h
index 9061dfe..261cf5b 100644
--- a/Inc/stm32l4xx_ll_comp.h
+++ b/Inc/stm32l4xx_ll_comp.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -142,7 +141,7 @@
#define LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */
#if defined(COMP_CSR_INPSEL_1)
#define LL_COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1) /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2) */
-#endif
+#endif /* COMP_CSR_INPSEL_1 */
/**
* @}
*/
@@ -184,13 +183,13 @@
#define LL_COMP_INVERTINGINPUT_IO3 LL_COMP_INPUT_MINUS_IO3
#define LL_COMP_INVERTINGINPUT_IO4 LL_COMP_INPUT_MINUS_IO4
#define LL_COMP_INVERTINGINPUT_IO5 LL_COMP_INPUT_MINUS_IO5
-#endif
+#endif /* COMP_CSR_INMESEL_1 */
#define LL_COMP_NONINVERTINGINPUT_IO1 LL_COMP_INPUT_PLUS_IO1
#define LL_COMP_NONINVERTINGINPUT_IO2 LL_COMP_INPUT_PLUS_IO2
#if defined(COMP_CSR_INPSEL_1)
#define LL_COMP_NONINVERTINGINPUT_IO3 LL_COMP_INPUT_PLUS_IO3
-#endif
+#endif /* COMP_CSR_INPSEL_1 */
/**
* @}
*/
@@ -563,7 +562,7 @@
MODIFY_REG(COMPx->CSR, COMP_CSR_INMESEL | COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN, InputMinus);
#else
MODIFY_REG(COMPx->CSR, COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN, InputMinus);
-#endif
+#endif /* COMP_CSR_INMESEL_1 */
}
/**
@@ -596,7 +595,7 @@
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INMESEL | COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN));
#else
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN));
-#endif
+#endif /* COMP_CSR_INMESEL_1 */
}
/**
@@ -886,5 +885,3 @@
#endif
#endif /* STM32L4xx_LL_COMP_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_cortex.h b/Inc/stm32l4xx_ll_cortex.h
index 2cb0a88..4ad94d6 100644
--- a/Inc/stm32l4xx_ll_cortex.h
+++ b/Inc/stm32l4xx_ll_cortex.h
@@ -21,13 +21,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -636,4 +635,3 @@
#endif /* STM32L4xx_LL_CORTEX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_crc.h b/Inc/stm32l4xx_ll_crc.h
index 6ca1a28..18690cf 100644
--- a/Inc/stm32l4xx_ll_crc.h
+++ b/Inc/stm32l4xx_ll_crc.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -236,7 +235,7 @@
}
/**
- * @brief Configure the reversal of the bit order of the Output data
+ * @brief Return type of reversal of the bit order of the Output data
* @rmtoll CR REV_OUT LL_CRC_GetOutputDataReverseMode
* @param CRCx CRC Instance
* @retval Returned value can be one of the following values:
@@ -466,5 +465,3 @@
#endif
#endif /* STM32L4xx_LL_CRC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_crs.h b/Inc/stm32l4xx_ll_crs.h
index 13dabf7..1d2b333 100644
--- a/Inc/stm32l4xx_ll_crs.h
+++ b/Inc/stm32l4xx_ll_crs.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -94,7 +93,7 @@
/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
* @{
*/
-#define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal soucre GPIO */
+#define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal source GPIO */
#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
/**
@@ -784,5 +783,3 @@
#endif
#endif /* STM32L4xx_LL_CRS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_dac.h b/Inc/stm32l4xx_ll_dac.h
index 37ae202..565e142 100644
--- a/Inc/stm32l4xx_ll_dac.h
+++ b/Inc/stm32l4xx_ll_dac.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -1978,4 +1977,3 @@
#endif /* STM32L4xx_LL_DAC_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_dma.h b/Inc/stm32l4xx_ll_dma.h
index 5b3b909..add3c4a 100644
--- a/Inc/stm32l4xx_ll_dma.h
+++ b/Inc/stm32l4xx_ll_dma.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -2429,5 +2428,3 @@
#endif
#endif /* STM32L4xx_LL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_dma2d.h b/Inc/stm32l4xx_ll_dma2d.h
index b3a6b45..d5b5f1d 100644
--- a/Inc/stm32l4xx_ll_dma2d.h
+++ b/Inc/stm32l4xx_ll_dma2d.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -66,97 +65,132 @@
uint32_t Mode; /*!< Specifies the DMA2D transfer mode.
- This parameter can be one value of @ref DMA2D_LL_EC_MODE.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetMode().*/
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetMode(). */
uint32_t ColorMode; /*!< Specifies the color format of the output image.
- This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
+ This parameter can be modified afterwards using,
+ unitary function @ref LL_DMA2D_SetOutputColorMode(). */
uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ This parameter can be modified afterwards
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputRed; /*!< Specifies the Red value of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ This parameter can be modified afterwards
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
- This parameter is not considered if RGB888 or RGB565 color mode is selected.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ This parameter can be modified afterwards using,
+ unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputMemoryAddress; /*!< Specifies the memory address.
- - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
+ - This parameter must be a number between:
+ Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
uint32_t OutputSwapMode; /*!< Specifies the output swap mode color format of the output image.
- This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_SWAP_MODE.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputSwapMode(). */
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputSwapMode(). */
#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
uint32_t LineOffsetMode; /*!< Specifies the output line offset mode.
- This parameter can be one value of @ref DMA2D_LL_EC_LINE_OFFSET_MODE.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffsetMode(). */
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetLineOffsetMode(). */
#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
uint32_t LineOffset; /*!< Specifies the output line offset value.
- - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF on devices
+ - This parameter must be a number between:
+ Min_Data = 0x0000 and Max_Data = 0x3FFF on devices
where the Line Offset Mode feature is available.
else between Min_Data = 0x0000 and Max_Data = 0xFFFF on other devices.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffset(). */
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetLineOffset(). */
uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred.
- - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
+ - This parameter must be a number between:
+ Min_Data = 0x0000 and Max_Data = 0xFFFF.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
- uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transfered.
+ uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transferred.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
+ This parameter can be modified afterwards using,
+ unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
uint32_t AlphaInversionMode; /*!< Specifies the output alpha inversion mode.
- This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */
uint32_t RBSwapMode; /*!< Specifies the output Red Blue swap mode.
- This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */
} LL_DMA2D_InitTypeDef;
@@ -166,7 +200,8 @@
typedef struct
{
uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address.
- - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
+ - This parameter must be a number between:
+ Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
This parameter can be modified afterwards using unitary functions
- @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,
@@ -236,7 +271,8 @@
- @ref LL_DMA2D_BGND_SetRedColor() for background layer. */
uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address.
- - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
+ - This parameter must be a number between:
+ Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
This parameter can be modified afterwards using unitary functions
- @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,
@@ -267,45 +303,68 @@
uint32_t ColorMode; /*!< Specifies the color format of the output image.
- This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
+ This parameter can be modified afterwards using
+ unitary function @ref LL_DMA2D_SetOutputColorMode(). */
uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ This parameter can be modified afterwards using,
+ unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputRed; /*!< Specifies the Red value of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
- This parameter is not considered if RGB888 or RGB565 color mode is selected.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
} LL_DMA2D_ColorTypeDef;
@@ -397,9 +456,11 @@
* @{
*/
#define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */
-#define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by programmed alpha value */
-#define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by programmed alpha value
- with original alpha channel value */
+#define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by
+ programmed alpha value */
+#define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by
+ programmed alpha value with,
+ original alpha channel value */
/**
* @}
*/
@@ -2153,5 +2214,3 @@
#endif
#endif /* STM32L4xx_LL_DMA2D_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_dmamux.h b/Inc/stm32l4xx_ll_dmamux.h
index 2769c21..6de6976 100644
--- a/Inc/stm32l4xx_ll_dmamux.h
+++ b/Inc/stm32l4xx_ll_dmamux.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -417,8 +416,8 @@
#define LL_DMAMUX_SYNC_DMAMUX_CH1 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel1 Event */
#define LL_DMAMUX_SYNC_DMAMUX_CH2 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from DMAMUX channel2 Event */
#define LL_DMAMUX_SYNC_DMAMUX_CH3 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel3 Event */
-#define LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from LPTIM1 Ouput */
-#define LL_DMAMUX_SYNC_LPTIM2_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from LPTIM2 Ouput */
+#define LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from LPTIM1 Output */
+#define LL_DMAMUX_SYNC_LPTIM2_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from LPTIM2 Output */
#define LL_DMAMUX_SYNC_DSI_TE (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from DSI Tearing Effect */
#define LL_DMAMUX_SYNC_DSI_REFRESH_END (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DSI End of Refresh */
#define LL_DMAMUX_SYNC_DMA2D_TX_END (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_3) /*!< Synchronization signal from DMA2D End of Transfer */
@@ -472,8 +471,8 @@
#define LL_DMAMUX_REQ_GEN_DMAMUX_CH1 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel1 Event */
#define LL_DMAMUX_REQ_GEN_DMAMUX_CH2 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from DMAMUX channel2 Event */
#define LL_DMAMUX_REQ_GEN_DMAMUX_CH3 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel3 Event */
-#define LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from LPTIM1 Ouput */
-#define LL_DMAMUX_REQ_GEN_LPTIM2_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from LPTIM2 Ouput */
+#define LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from LPTIM1 Output */
+#define LL_DMAMUX_REQ_GEN_LPTIM2_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from LPTIM2 Output */
#define LL_DMAMUX_REQ_GEN_DSI_TE (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from DSI Tearing Effect */
#define LL_DMAMUX_REQ_GEN_DSI_REFRESH_END (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DSI End of Refresh */
#define LL_DMAMUX_REQ_GEN_DMA2D_TX_END (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_3) /*!< Request signal generation from DMA2D End of Transfer */
@@ -1980,5 +1979,3 @@
#endif
#endif /* STM32L4xx_LL_DMAMUX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_exti.h b/Inc/stm32l4xx_ll_exti.h
index 6e06963..a1ee112 100644
--- a/Inc/stm32l4xx_ll_exti.h
+++ b/Inc/stm32l4xx_ll_exti.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -1124,7 +1123,7 @@
/**
* @brief Generate a software Interrupt Event for Lines in range 32 to 63
- * @note If the interrupt is enabled on this line inthe EXTI_IMR2, writing a 1 to
+ * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to
* this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2
* resulting in an interrupt request generation.
* This bit is cleared by clearing the corresponding bit in the EXTI_PR2
@@ -1358,4 +1357,3 @@
#endif /* STM32L4xx_LL_EXTI_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_fmc.h b/Inc/stm32l4xx_ll_fmc.h
index d362572..5be0292 100644
--- a/Inc/stm32l4xx_ll_fmc.h
+++ b/Inc/stm32l4xx_ll_fmc.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -104,7 +103,7 @@
#endif /* FMC_PCSCNTR_CSCOUNT */
#endif /* FMC_BANK1 */
-#if defined(FMC_BANK3)
+#if defined(FMC_BANK3)
#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3)
#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \
@@ -507,11 +506,13 @@
* @}
*/
+#if defined(FMC_BCR1_WFDIS)
/** @defgroup FMC_Write_FIFO FMC Write FIFO
* @{
*/
#define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS
#define FMC_WRITE_FIFO_ENABLE (0x00000000U)
+ #endif /* FMC_BCR1_WFDIS */
/**
* @}
*/
@@ -700,7 +701,7 @@
/**
* @}
*/
-#endif
+#endif /* FMC_BANK3 */
#if defined(FMC_BANK3)
/** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt
@@ -862,5 +863,3 @@
#endif
#endif /* STM32L4xx_LL_FMC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_gpio.h b/Inc/stm32l4xx_ll_gpio.h
index 0285810..72bb307 100644
--- a/Inc/stm32l4xx_ll_gpio.h
+++ b/Inc/stm32l4xx_ll_gpio.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -1055,4 +1054,3 @@
#endif /* STM32L4xx_LL_GPIO_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_i2c.h b/Inc/stm32l4xx_ll_i2c.h
index 46f5f78..d67822e 100644
--- a/Inc/stm32l4xx_ll_i2c.h
+++ b/Inc/stm32l4xx_ll_i2c.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -69,38 +68,46 @@
uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE.
- This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_I2C_SetMode(). */
uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
This parameter must be set by referring to the STM32CubeMX Tool and
the helper macro @ref __LL_I2C_CONVERT_TIMINGS().
- This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_I2C_SetTiming(). */
uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION.
- This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
+ This feature can be modified afterwards using unitary functions
+ @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
uint32_t DigitalFilter; /*!< Configures the digital noise filter.
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
- This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_I2C_SetDigitalFilter(). */
uint32_t OwnAddress1; /*!< Specifies the device own address 1.
This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
- This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_I2C_SetOwnAddress1(). */
- uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
+ uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive
+ match code or next received byte.
This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE.
- This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_I2C_AcknowledgeNextData(). */
uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1.
- This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_I2C_SetOwnAddress1(). */
} LL_I2C_InitTypeDef;
/**
* @}
@@ -170,10 +177,11 @@
/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
* @{
*/
-#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
-#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */
-#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode (Default address not acknowledge) */
-#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */
+#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
+#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */
+#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode
+ (Default address not acknowledge) */
+#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */
/**
* @}
*/
@@ -208,14 +216,15 @@
/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
* @{
*/
-#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */
-#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. All Address2 are acknowledged.*/
+#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */
+#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done.
+ All Address2 are acknowledged. */
/**
* @}
*/
@@ -250,14 +259,21 @@
/** @defgroup I2C_LL_EC_MODE Transfer End Mode
* @{
*/
-#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */
-#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode with no HW PEC comparison. */
-#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode with no HW PEC comparison. */
-#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
-#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
-#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode with HW PEC comparison. */
-#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
-#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Software end mode with HW PEC comparison. */
+#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */
+#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode
+ with no HW PEC comparison. */
+#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode
+ with no HW PEC comparison. */
+#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode
+ with HW PEC comparison. */
+#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode
+ with HW PEC comparison. */
+#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode
+ with HW PEC comparison. */
+#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
+/*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
+#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
+/*!< Enable SMBUS Software end mode with HW PEC comparison. */
/**
* @}
*/
@@ -265,14 +281,23 @@
/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
* @{
*/
-#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */
-#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) /*!< Generate Stop condition (Size should be set to 0). */
-#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */
-#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Start for write request. */
-#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */
-#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 7Bit address. */
-#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
-#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 10Bit address.*/
+#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U
+/*!< Don't Generate Stop and Start condition. */
+#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
+/*!< Generate Stop condition (Size should be set to 0). */
+#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+/*!< Generate Start for read request. */
+#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
+/*!< Generate Start for write request. */
+#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+/*!< Generate Restart for read request, slave 7Bit address. */
+#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
+/*!< Generate Restart for write request, slave 7Bit address. */
+#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | \
+ I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
+/*!< Generate Restart for read request, slave 10Bit address. */
+#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
+/*!< Generate Restart for write request, slave 10Bit address.*/
/**
* @}
*/
@@ -280,8 +305,10 @@
/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
* @{
*/
-#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, slave enters receiver mode. */
-#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, slave enters transmitter mode.*/
+#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master,
+ slave enters receiver mode. */
+#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master,
+ slave enters transmitter mode.*/
/**
* @}
*/
@@ -289,8 +316,10 @@
/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
* @{
*/
-#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
-#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
+#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for
+ transmission */
+#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for
+ reception */
/**
* @}
*/
@@ -298,8 +327,10 @@
/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
* @{
*/
-#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect SCL low level timeout. */
-#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/
+#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect
+ SCL low level timeout. */
+#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect
+ both SCL and SDA high level timeout.*/
/**
* @}
*/
@@ -307,9 +338,12 @@
/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
* @{
*/
-#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */
-#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) enable bit */
-#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */
+#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */
+#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock)
+ enable bit */
+#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \
+ I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB
+(extended clock) enable bits */
/**
* @}
*/
@@ -353,18 +387,22 @@
/**
* @brief Configure the SDA setup, hold time and the SCL high, low period.
* @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
- * @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
- * @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
- * @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
- * @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
+ * @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
+ (tscldel = (SCLDEL+1)xtpresc)
+ * @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
+ (tsdadel = SDADELxtpresc)
+ * @param __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
+ (tsclh = (SCLH+1)xtpresc)
+ * @param __SCLL_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
+ (tscll = (SCLL+1)xtpresc)
* @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
*/
-#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \
- ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
- (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
- (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
- (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
- (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
+#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \
+ ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
+ (((uint32_t)(__SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
+ (((uint32_t)(__HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
+ (((uint32_t)(__SCLH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
+ (((uint32_t)(__SCLL_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
/**
* @}
*/
@@ -428,7 +466,8 @@
* @param AnalogFilter This parameter can be one of the following values:
* @arg @ref LL_I2C_ANALOGFILTER_ENABLE
* @arg @ref LL_I2C_ANALOGFILTER_DISABLE
- * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
+ * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
+ and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
* This parameter is used to configure the digital noise filter on SDA and SCL input.
* The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
* @retval None
@@ -444,7 +483,8 @@
* This filter can only be programmed when the I2C is disabled (PE = 0).
* @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
* @param I2Cx I2C Instance.
- * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
+ * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
+ and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
* This parameter is used to configure the digital noise filter on SDA and SCL input.
* The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
* @retval None
@@ -664,7 +704,7 @@
/**
* @brief Enable Wakeup from STOP.
- * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
* WakeUpFromStop feature is supported by the I2Cx Instance.
* @note This bit can only be programmed when Digital Filter is disabled.
* @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop
@@ -678,7 +718,7 @@
/**
* @brief Disable Wakeup from STOP.
- * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
* WakeUpFromStop feature is supported by the I2Cx Instance.
* @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop
* @param I2Cx I2C Instance.
@@ -691,7 +731,7 @@
/**
* @brief Check if Wakeup from STOP is enabled or disabled.
- * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
* WakeUpFromStop feature is supported by the I2Cx Instance.
* @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
* @param I2Cx I2C Instance.
@@ -941,7 +981,7 @@
/**
* @brief Configure peripheral mode.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
* CR1 SMBDEN LL_I2C_SetMode
@@ -960,7 +1000,7 @@
/**
* @brief Get peripheral mode.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
* CR1 SMBDEN LL_I2C_GetMode
@@ -978,7 +1018,7 @@
/**
* @brief Enable SMBus alert (Host or Device mode)
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note SMBus Device mode:
* - SMBus Alert pin is drived low and
@@ -996,7 +1036,7 @@
/**
* @brief Disable SMBus alert (Host or Device mode)
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note SMBus Device mode:
* - SMBus Alert pin is not drived (can be used as a standard GPIO) and
@@ -1014,7 +1054,7 @@
/**
* @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
* @param I2Cx I2C Instance.
@@ -1027,7 +1067,7 @@
/**
* @brief Enable SMBus Packet Error Calculation (PEC).
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
* @param I2Cx I2C Instance.
@@ -1040,7 +1080,7 @@
/**
* @brief Disable SMBus Packet Error Calculation (PEC).
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
* @param I2Cx I2C Instance.
@@ -1053,7 +1093,7 @@
/**
* @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
* @param I2Cx I2C Instance.
@@ -1066,7 +1106,7 @@
/**
* @brief Configure the SMBus Clock Timeout.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
@@ -1089,7 +1129,7 @@
/**
* @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note These bits can only be programmed when TimeoutA is disabled.
* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
@@ -1104,7 +1144,7 @@
/**
* @brief Get the SMBus Clock TimeoutA setting.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
* @param I2Cx I2C Instance.
@@ -1117,7 +1157,7 @@
/**
* @brief Set the SMBus Clock TimeoutA mode.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note This bit can only be programmed when TimeoutA is disabled.
* @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
@@ -1134,7 +1174,7 @@
/**
* @brief Get the SMBus Clock TimeoutA mode.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
* @param I2Cx I2C Instance.
@@ -1149,7 +1189,7 @@
/**
* @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note These bits can only be programmed when TimeoutB is disabled.
* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
@@ -1164,7 +1204,7 @@
/**
* @brief Get the SMBus Extended Cumulative Clock TimeoutB setting.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
* @param I2Cx I2C Instance.
@@ -1177,7 +1217,7 @@
/**
* @brief Enable the SMBus Clock Timeout.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
* TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
@@ -1195,7 +1235,7 @@
/**
* @brief Disable the SMBus Clock Timeout.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
* TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
@@ -1213,7 +1253,7 @@
/**
* @brief Check if the SMBus Clock Timeout is enabled or disabled.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
* TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
@@ -1226,7 +1266,8 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
{
- return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)) ? 1UL : 0UL);
+ return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
+ (ClockTimeout)) ? 1UL : 0UL);
}
/**
@@ -1443,7 +1484,7 @@
/**
* @brief Enable Error interrupts.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note Any of these errors will generate interrupt :
* Arbitration Loss (ARLO)
@@ -1463,7 +1504,7 @@
/**
* @brief Disable Error interrupts.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note Any of these errors will generate interrupt :
* Arbitration Loss (ARLO)
@@ -1645,7 +1686,7 @@
/**
* @brief Indicate the status of SMBus PEC error flag in reception.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note RESET: Clear default value.
* SET: When the received PEC does not match with the PEC register content.
@@ -1660,7 +1701,7 @@
/**
* @brief Indicate the status of SMBus Timeout detection flag.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note RESET: Clear default value.
* SET: When a timeout or extended clock timeout occurs.
@@ -1675,7 +1716,7 @@
/**
* @brief Indicate the status of SMBus alert flag.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note RESET: Clear default value.
* SET: When SMBus host configuration, SMBus alert enabled and
@@ -1782,7 +1823,7 @@
/**
* @brief Clear SMBus PEC error flag.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
* @param I2Cx I2C Instance.
@@ -1795,7 +1836,7 @@
/**
* @brief Clear SMBus Timeout detection flag.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
* @param I2Cx I2C Instance.
@@ -1808,7 +1849,7 @@
/**
* @brief Clear SMBus Alert flag.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
* @param I2Cx I2C Instance.
@@ -1923,7 +1964,8 @@
}
/**
- * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
+ * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code
+ or next received byte.
* @note Usage in Slave mode only.
* @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
* @param I2Cx I2C Instance.
@@ -1964,7 +2006,8 @@
/**
* @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
* @note The master sends the complete 10bit slave address read sequence :
- * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
+ * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address
+ in Read direction.
* @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead
* @param I2Cx I2C Instance.
* @retval None
@@ -2125,9 +2168,10 @@
/**
* @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
- * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
+ * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition
+ or an Address Matched is received.
* This bit has no effect when RELOAD bit is set.
* This bit has no effect in device mode when SBC bit is not set.
* @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
@@ -2141,7 +2185,7 @@
/**
* @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
* @param I2Cx I2C Instance.
@@ -2154,7 +2198,7 @@
/**
* @brief Get the SMBus Packet Error byte calculated.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll PECR PEC LL_I2C_GetSMBusPEC
* @param I2Cx I2C Instance.
@@ -2226,5 +2270,3 @@
#endif
#endif /* STM32L4xx_LL_I2C_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_iwdg.h b/Inc/stm32l4xx_ll_iwdg.h
index bac7d56..6bf901a 100644
--- a/Inc/stm32l4xx_ll_iwdg.h
+++ b/Inc/stm32l4xx_ll_iwdg.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -304,8 +303,8 @@
/**
* @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not
* @rmtoll SR PVU LL_IWDG_IsReady\n
- * SR WVU LL_IWDG_IsReady\n
- * SR RVU LL_IWDG_IsReady
+ * SR RVU LL_IWDG_IsReady\n
+ * SR WVU LL_IWDG_IsReady
* @param IWDGx IWDG Instance
* @retval State of bits (1 or 0).
*/
@@ -318,7 +317,6 @@
* @}
*/
-
/**
* @}
*/
@@ -338,5 +336,3 @@
#endif
#endif /* STM32L4xx_LL_IWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_lptim.h b/Inc/stm32l4xx_ll_lptim.h
index ad78047..6d92db1 100644
--- a/Inc/stm32l4xx_ll_lptim.h
+++ b/Inc/stm32l4xx_ll_lptim.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -67,22 +66,26 @@
uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
- This feature can be modified afterwards using unitary function @ref LL_LPTIM_SetClockSource().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_LPTIM_SetClockSource().*/
uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
- This feature can be modified afterwards using using unitary function @ref LL_LPTIM_SetPrescaler().*/
+ This feature can be modified afterwards using using unitary
+ function @ref LL_LPTIM_SetPrescaler().*/
uint32_t Waveform; /*!< Specifies the waveform shape.
This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
- This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_LPTIM_ConfigOutput().*/
uint32_t Polarity; /*!< Specifies waveform polarity.
This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
- This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_LPTIM_ConfigOutput().*/
} LL_LPTIM_InitTypeDef;
/**
@@ -100,9 +103,9 @@
* @{
*/
#define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */
+#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */
#define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
#define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
-#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */
#define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
#define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
#define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
@@ -118,16 +121,16 @@
* @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
* @{
*/
-#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match Interrupt Enable */
-#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match Interrupt Enable */
-#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger valid edge Interrupt Enable */
-#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK Interrupt Enable */
-#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK Interrupt Enable */
-#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Direction change to UP Interrupt Enable */
-#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Direction change to down Interrupt Enable */
+#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match */
+#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK */
+#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match */
+#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger edge event */
+#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK */
+#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Counter direction change down to up */
+#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Counter direction change up to down */
#if defined(LPTIM_RCR_REP)
-#define LL_LPTIM_IER_UEIE LPTIM_IER_UEIE /*!< Update event Interrupt Enable */
-#define LL_LPTIM_IER_REPOKIE LPTIM_IER_REPOKIE /*!< Repetition register update OK Interrupt Enable */
+#define LL_LPTIM_IER_UEIE LPTIM_IER_UEIE /*!< Update event */
+#define LL_LPTIM_IER_REPOKIE LPTIM_IER_REPOKIE /*!< Repetition register update OK */
#endif
/**
* @}
@@ -929,7 +932,8 @@
}
/**
- * @brief Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
+ * @brief Configure the active edge or edges used by the counter when
+ the LPTIM is clocked by an external clock source.
* @note This function must be called when the LPTIM instance is disabled.
* @note When both external clock signal edges are considered active ones,
* the LPTIM must also be clocked by an internal clock source with a
@@ -1147,7 +1151,8 @@
}
/**
- * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated.
+ * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully
+ completed. If so, a new one can be initiated.
* @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
@@ -1169,7 +1174,8 @@
}
/**
- * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated.
+ * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully
+ completed. If so, a new one can be initiated.
* @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
@@ -1191,7 +1197,8 @@
}
/**
- * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
+ * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance
+ operates in encoder mode).
* @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
@@ -1213,7 +1220,8 @@
}
/**
- * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).
+ * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance
+ operates in encoder mode).
* @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
@@ -1236,7 +1244,8 @@
}
/**
- * @brief Informs application whether the APB bus write operation to the LPTIMx_RCR register has been successfully completed; If so, a new one can be initiated.
+ * @brief Informs application whether the APB bus write operation to the LPTIMx_RCR register has been successfully
+ completed; If so, a new one can be initiated.
* @rmtoll ISR REPOK LL_LPTIM_IsActiveFlag_REPOK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
@@ -1411,7 +1420,7 @@
/**
* @brief Enable autoreload register write completed interrupt (ARROKIE).
- * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK
+ * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
@@ -1422,7 +1431,7 @@
/**
* @brief Disable autoreload register write completed interrupt (ARROKIE).
- * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK
+ * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
@@ -1433,7 +1442,7 @@
/**
* @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
- * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
+ * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit(1 or 0).
*/
@@ -1444,7 +1453,7 @@
/**
* @brief Enable direction change to up interrupt (UPIE).
- * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP
+ * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
@@ -1455,7 +1464,7 @@
/**
* @brief Disable direction change to up interrupt (UPIE).
- * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP
+ * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
@@ -1466,7 +1475,7 @@
/**
* @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
- * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
+ * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
* @param LPTIMx Low-Power Timer instance
* @retval State of bit(1 or 0).
*/
@@ -1477,7 +1486,7 @@
/**
* @brief Enable direction change to down interrupt (DOWNIE).
- * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN
+ * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
@@ -1488,7 +1497,7 @@
/**
* @brief Disable direction change to down interrupt (DOWNIE).
- * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN
+ * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
@@ -1499,7 +1508,7 @@
/**
* @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
- * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
+ * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
* @param LPTIMx Low-Power Timer instance
* @retval State of bit(1 or 0).
*/
@@ -1511,7 +1520,7 @@
#if defined(LPTIM_RCR_REP)
/**
* @brief Enable repetition register update successfully completed interrupt (REPOKIE).
- * @rmtoll IER REPOKIE LL_LPTIM_EnableIT_REPOK
+ * @rmtoll IER REPOKIE LL_LPTIM_EnableIT_REPOK
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
@@ -1522,7 +1531,7 @@
/**
* @brief Disable repetition register update successfully completed interrupt (REPOKIE).
- * @rmtoll IER REPOKIE LL_LPTIM_DisableIT_REPOK
+ * @rmtoll IER REPOKIE LL_LPTIM_DisableIT_REPOK
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
@@ -1533,7 +1542,7 @@
/**
* @brief Indicates whether the repetition register update successfully completed interrupt (REPOKIE) is enabled.
- * @rmtoll IER REPOKIE LL_LPTIM_IsEnabledIT_REPOK
+ * @rmtoll IER REPOKIE LL_LPTIM_IsEnabledIT_REPOK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit(1 or 0).
*/
@@ -1544,7 +1553,7 @@
/**
* @brief Enable update event interrupt (UEIE).
- * @rmtoll IER UEIE LL_LPTIM_EnableIT_UE
+ * @rmtoll IER UEIE LL_LPTIM_EnableIT_UE
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
@@ -1555,7 +1564,7 @@
/**
* @brief Disable update event interrupt (UEIE).
- * @rmtoll IER UEIE LL_LPTIM_DisableIT_UE
+ * @rmtoll IER UEIE LL_LPTIM_DisableIT_UE
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
@@ -1566,7 +1575,7 @@
/**
* @brief Indicates whether the update event interrupt (UEIE) is enabled.
- * @rmtoll IER UEIE LL_LPTIM_IsEnabledIT_UE
+ * @rmtoll IER UEIE LL_LPTIM_IsEnabledIT_UE
* @param LPTIMx Low-Power Timer instance
*@ retval State of bit(1 or 0).
*/
@@ -1598,5 +1607,3 @@
#endif
#endif /* STM32L4xx_LL_LPTIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_lpuart.h b/Inc/stm32l4xx_ll_lpuart.h
index 82be58a..ddcb259 100644
--- a/Inc/stm32l4xx_ll_lpuart.h
+++ b/Inc/stm32l4xx_ll_lpuart.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -158,18 +157,15 @@
* @brief Flags defines which can be used with LL_LPUART_WriteReg function
* @{
*/
-#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */
-#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */
-#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected flag */
-#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */
-#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */
-#if defined(USART_CR1_FIFOEN)
-#define LL_LPUART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty Clear flag */
-#endif /* USART_CR1_FIFOEN */
-#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */
-#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */
-#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */
-#define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */
+#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */
+#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */
+#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */
+#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */
+#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */
+#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */
+#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */
+#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */
+#define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */
/**
* @}
*/
@@ -178,36 +174,36 @@
* @brief Flags defines which can be used with LL_LPUART_ReadReg function
* @{
*/
-#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */
-#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */
-#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
-#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
-#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
+#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */
+#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */
+#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
+#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
+#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
#if defined(USART_CR1_FIFOEN)
-#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
+#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
#else
-#define LL_LPUART_ISR_RXNE USART_ISR_RXNE /*!< Read data register not empty flag */
+#define LL_LPUART_ISR_RXNE USART_ISR_RXNE /*!< Read data register not empty flag */
#endif /* USART_CR1_FIFOEN */
-#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
+#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
#if defined(USART_CR1_FIFOEN)
-#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/
+#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/
#else
-#define LL_LPUART_ISR_TXE USART_ISR_TXE /*!< Transmit data register empty flag */
+#define LL_LPUART_ISR_TXE USART_ISR_TXE /*!< Transmit data register empty flag */
#endif /* USART_CR1_FIFOEN */
-#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
-#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
-#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
-#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
-#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
-#define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
-#define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
-#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
-#define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
+#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
+#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
+#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
+#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
+#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
+#define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
+#define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
+#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
+#define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
#if defined(USART_CR1_FIFOEN)
-#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */
-#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */
-#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */
-#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */
+#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */
+#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */
+#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */
+#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */
#endif /* USART_CR1_FIFOEN */
/**
* @}
@@ -217,30 +213,32 @@
* @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions
* @{
*/
-#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
+#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
#if defined(USART_CR1_FIFOEN)
-#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */
+#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty
+ interrupt enable */
#else
-#define LL_LPUART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */
+#define LL_LPUART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */
#endif /* USART_CR1_FIFOEN */
-#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
+#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
#if defined(USART_CR1_FIFOEN)
-#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */
+#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO
+ not full interrupt enable */
#else
-#define LL_LPUART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */
+#define LL_LPUART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */
#endif /* USART_CR1_FIFOEN */
-#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
-#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */
+#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
+#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */
#if defined(USART_CR1_FIFOEN)
-#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */
-#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */
+#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */
+#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */
#endif /* USART_CR1_FIFOEN */
-#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
-#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
-#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
+#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
+#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
+#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
#if defined(USART_CR1_FIFOEN)
-#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */
-#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */
+#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */
+#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */
#endif /* USART_CR1_FIFOEN */
/**
* @}
@@ -264,10 +262,10 @@
/** @defgroup LPUART_LL_EC_DIRECTION Direction
* @{
*/
-#define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
-#define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
-#define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
-#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
+#define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
+#define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
/**
* @}
*/
@@ -275,9 +273,9 @@
/** @defgroup LPUART_LL_EC_PARITY Parity Control
* @{
*/
-#define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
-#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
-#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
+#define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
+#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
+#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
/**
* @}
*/
@@ -285,8 +283,8 @@
/** @defgroup LPUART_LL_EC_WAKEUP Wakeup
* @{
*/
-#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */
-#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */
+#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */
+#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */
/**
* @}
*/
@@ -294,9 +292,9 @@
/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
* @{
*/
-#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
-#define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
-#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
+#define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
/**
* @}
*/
@@ -305,18 +303,27 @@
/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
* @{
*/
-#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
-#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
-#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
-#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
-#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
-#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
-#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
-#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
-#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
-#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
-#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
-#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
+#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
+#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
+#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
+#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 |\
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
+#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
+#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 |\
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
+#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 |\
+ USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
+#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 |\
+ USART_PRESC_PRESCALER_1 |\
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
+#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
+#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 |\
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
+#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\
+ USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
+#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\
+ USART_PRESC_PRESCALER_1 |\
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
/**
* @}
*/
@@ -325,8 +332,8 @@
/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
* @{
*/
-#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
-#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
+#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
+#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
/**
* @}
*/
@@ -334,8 +341,8 @@
/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
* @{
*/
-#define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
-#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
+#define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
+#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
/**
* @}
*/
@@ -343,8 +350,8 @@
/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
* @{
*/
-#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */
-#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
+#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */
+#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
/**
* @}
*/
@@ -352,8 +359,8 @@
/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
* @{
*/
-#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */
-#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
+#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */
+#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
/**
* @}
*/
@@ -361,8 +368,11 @@
/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
* @{
*/
-#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
-#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
+#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received
+ in positive/direct logic. (1=H, 0=L) */
+#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received
+ in negative/inverse logic. (1=L, 0=H).
+ The parity bit is also inverted. */
/**
* @}
*/
@@ -370,8 +380,10 @@
/** @defgroup LPUART_LL_EC_BITORDER Bit Order
* @{
*/
-#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */
-#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */
+#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first,
+ following the start bit */
+#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first,
+ following the start bit */
/**
* @}
*/
@@ -379,8 +391,8 @@
/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
* @{
*/
-#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */
-#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
+#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */
+#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
/**
* @}
*/
@@ -388,10 +400,12 @@
/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
* @{
*/
-#define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
-#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
-#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
-#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
+#define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
+#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested
+ when there is space in the receive buffer */
+#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted
+ when the nCTS input is asserted (tied to 0)*/
+#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
/**
* @}
*/
@@ -399,9 +413,9 @@
/** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
* @{
*/
-#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */
-#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */
-#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */
+#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */
+#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */
+#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */
/**
* @}
*/
@@ -409,8 +423,8 @@
/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
* @{
*/
-#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */
-#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
+#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */
+#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
/**
* @}
*/
@@ -418,8 +432,8 @@
/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
* @{
*/
-#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
-#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
+#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
+#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
/**
* @}
*/
@@ -599,7 +613,7 @@
*/
__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
{
- MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
+ ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
}
/**
@@ -634,7 +648,7 @@
*/
__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
{
- MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
+ ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
}
/**
@@ -677,8 +691,8 @@
*/
__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
{
- MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \
- (RXThreshold << USART_CR3_RXFTCFG_Pos));
+ ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \
+ (RXThreshold << USART_CR3_RXFTCFG_Pos));
}
#endif /* USART_CR1_FIFOEN */
@@ -692,7 +706,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
}
/**
@@ -704,7 +718,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
}
/**
@@ -729,7 +743,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableClockInStopMode(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR3, USART_CR3_UCESM);
+ ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_UCESM);
}
/**
@@ -741,7 +755,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableClockInStopMode(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR3, USART_CR3_UCESM);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_UCESM);
}
/**
@@ -764,7 +778,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR1, USART_CR1_RE);
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE);
}
/**
@@ -775,7 +789,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
}
/**
@@ -786,7 +800,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR1, USART_CR1_TE);
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE);
}
/**
@@ -797,7 +811,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
}
/**
@@ -815,7 +829,7 @@
*/
__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
{
- MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+ ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
}
/**
@@ -932,7 +946,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR1, USART_CR1_MME);
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME);
}
/**
@@ -943,7 +957,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
}
/**
@@ -1990,19 +2004,6 @@
WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
}
-#if defined(USART_CR1_FIFOEN)
-/**
- * @brief Clear TX FIFO Empty Flag
- * @rmtoll ICR TXFECF LL_LPUART_ClearFlag_TXFE
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_ClearFlag_TXFE(USART_TypeDef *LPUARTx)
-{
- WRITE_REG(LPUARTx->ICR, USART_ICR_TXFECF);
-}
-#endif /* USART_CR1_FIFOEN */
-
/**
* @brief Clear Transmission Complete Flag
* @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC
@@ -2063,7 +2064,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
}
#if defined(USART_CR1_FIFOEN)
@@ -2078,7 +2079,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
}
#else
@@ -2090,7 +2091,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableIT_RXNE(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);
}
#endif /* USART_CR1_FIFOEN */
@@ -2102,7 +2103,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
}
#if defined(USART_CR1_FIFOEN)
@@ -2117,7 +2118,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
}
#else
@@ -2129,7 +2130,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableIT_TXE(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE);
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE);
}
#endif /* USART_CR1_FIFOEN */
@@ -2141,7 +2142,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
}
/**
@@ -2152,7 +2153,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
}
#if defined(USART_CR1_FIFOEN)
@@ -2164,7 +2165,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
}
/**
@@ -2175,7 +2176,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
}
#endif /* USART_CR1_FIFOEN */
@@ -2191,7 +2192,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
+ ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
}
/**
@@ -2202,7 +2203,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
+ ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
}
/**
@@ -2213,7 +2214,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
+ ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
}
#if defined(USART_CR1_FIFOEN)
@@ -2225,7 +2226,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
+ ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
}
/**
@@ -2236,7 +2237,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
+ ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
}
#endif /* USART_CR1_FIFOEN */
@@ -2248,7 +2249,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
}
#if defined(USART_CR1_FIFOEN)
@@ -2263,7 +2264,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
}
#else
@@ -2275,7 +2276,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableIT_RXNE(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);
}
#endif /* USART_CR1_FIFOEN */
@@ -2287,7 +2288,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
}
#if defined(USART_CR1_FIFOEN)
@@ -2302,7 +2303,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
}
#else
@@ -2314,7 +2315,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableIT_TXE(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE);
}
#endif /* USART_CR1_FIFOEN */
@@ -2326,7 +2327,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
}
/**
@@ -2337,7 +2338,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
}
#if defined(USART_CR1_FIFOEN)
@@ -2349,7 +2350,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
}
/**
@@ -2360,7 +2361,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
}
#endif /* USART_CR1_FIFOEN */
@@ -2376,7 +2377,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
}
/**
@@ -2387,7 +2388,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
}
/**
@@ -2398,7 +2399,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
}
#if defined(USART_CR1_FIFOEN)
@@ -2410,7 +2411,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
}
/**
@@ -2421,7 +2422,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
}
#endif /* USART_CR1_FIFOEN */
@@ -2622,7 +2623,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
+ ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
}
/**
@@ -2633,7 +2634,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
}
/**
@@ -2655,7 +2656,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
+ ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
}
/**
@@ -2666,7 +2667,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
}
/**
@@ -2878,4 +2879,3 @@
#endif /* STM32L4xx_LL_LPUART_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_opamp.h b/Inc/stm32l4xx_ll_opamp.h
index af5e226..ac53d3d 100644
--- a/Inc/stm32l4xx_ll_opamp.h
+++ b/Inc/stm32l4xx_ll_opamp.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -245,7 +244,7 @@
*/
/** @defgroup OPAMP_LL_EC_HW_DELAYS Definitions of OPAMP hardware constraints delays
- * @note Only OPAMP IP HW delays are defined in OPAMP LL driver driver,
+ * @note Only OPAMP peripheral HW delays are defined in OPAMP LL driver driver,
* not timeout values.
* For details on delays values, refer to descriptions in source code
* above each literal definition.
@@ -417,7 +416,7 @@
* @rmtoll CSR OPALPM LL_OPAMP_SetPowerMode
* @param OPAMPx OPAMP instance
* @param PowerMode This parameter can be one of the following values:
- * @arg @ref LL_OPAMP_POWERMODE_NORMAL
+ * @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER
* @arg @ref LL_OPAMP_POWERMODE_LOWPOWER
* @retval None
*/
@@ -431,7 +430,7 @@
* @rmtoll CSR OPALPM LL_OPAMP_GetPowerMode
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
- * @arg @ref LL_OPAMP_POWERMODE_NORMAL
+ * @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER
* @arg @ref LL_OPAMP_POWERMODE_LOWPOWER
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode(OPAMP_TypeDef *OPAMPx)
@@ -740,7 +739,7 @@
* LPOTR TRIMLPOFFSETP LL_OPAMP_SetTrimmingValue
* @param OPAMPx OPAMP instance
* @param PowerMode This parameter can be one of the following values:
- * @arg @ref LL_OPAMP_POWERMODE_NORMAL
+ * @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER
* @arg @ref LL_OPAMP_POWERMODE_LOWPOWER
* @param TransistorsDiffPair This parameter can be one of the following values:
* @arg @ref LL_OPAMP_TRIMMING_NMOS
@@ -750,7 +749,7 @@
*/
__STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair, uint32_t TrimmingValue)
{
- uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK));
+ __IO uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK));
/* Set bits with position in register depending on parameter */
/* "TransistorsDiffPair". */
@@ -771,7 +770,7 @@
* LPOTR TRIMLPOFFSETP LL_OPAMP_GetTrimmingValue
* @param OPAMPx OPAMP instance
* @param PowerMode This parameter can be one of the following values:
- * @arg @ref LL_OPAMP_POWERMODE_NORMAL
+ * @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER
* @arg @ref LL_OPAMP_POWERMODE_LOWPOWER
* @param TransistorsDiffPair This parameter can be one of the following values:
* @arg @ref LL_OPAMP_TRIMMING_NMOS
@@ -780,7 +779,7 @@
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair)
{
- const uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK));
+ const __IO uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK));
/* Retrieve bits with position in register depending on parameter */
/* "TransistorsDiffPair". */
@@ -800,7 +799,7 @@
/**
* @brief Enable OPAMP instance.
* @note After enable from off state, OPAMP requires a delay
- * to fullfill wake up time specification.
+ * to fulfill wake up time specification.
* Refer to device datasheet, parameter "tWAKEUP".
* @rmtoll CSR OPAMPXEN LL_OPAMP_Enable
* @param OPAMPx OPAMP instance
@@ -871,5 +870,3 @@
#endif
#endif /* STM32L4xx_LL_OPAMP_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_pka.h b/Inc/stm32l4xx_ll_pka.h
index e714f91..9bb222b 100644
--- a/Inc/stm32l4xx_ll_pka.h
+++ b/Inc/stm32l4xx_ll_pka.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -94,7 +93,7 @@
*/
/** @defgroup PKA_LL_EC_MODE Operation Mode
- * @brief List of opearation mode.
+ * @brief List of operation mode.
* @{
*/
#define LL_PKA_MODE_MONTGOMERY_PARAM_MOD_EXP ((uint32_t)0x00000000U) /*!< Compute Montgomery parameter and modular exponentiation */
@@ -173,9 +172,9 @@
* @param PKAx PKA Instance.
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM_MOD_EXP
+ * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM_ECC
* @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM
* @arg @ref LL_PKA_MODE_MODULAR_EXP
- * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM_ECC
* @arg @ref LL_PKA_MODE_ECC_KP_PRIMITIVE
* @arg @ref LL_PKA_MODE_ECDSA_SIGNATURE
* @arg @ref LL_PKA_MODE_ECDSA_VERIFICATION
@@ -235,9 +234,9 @@
* @param PKAx PKA Instance.
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM_MOD_EXP
+ * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM_ECC
* @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM
* @arg @ref LL_PKA_MODE_MODULAR_EXP
- * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM_ECC
* @arg @ref LL_PKA_MODE_ECC_KP_PRIMITIVE
* @arg @ref LL_PKA_MODE_ECDSA_SIGNATURE
* @arg @ref LL_PKA_MODE_ECDSA_VERIFICATION
@@ -265,9 +264,9 @@
* @param PKAx PKA Instance.
* @retval Returned value can be one of the following values:
* @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM_MOD_EXP
+ * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM_ECC
* @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM
* @arg @ref LL_PKA_MODE_MODULAR_EXP
- * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM_ECC
* @arg @ref LL_PKA_MODE_ECC_KP_PRIMITIVE
* @arg @ref LL_PKA_MODE_ECDSA_SIGNATURE
* @arg @ref LL_PKA_MODE_ECDSA_VERIFICATION
@@ -533,5 +532,3 @@
#endif
#endif /* STM32L4xx_LL_PKA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_pwr.h b/Inc/stm32l4xx_ll_pwr.h
index 436649c..4660f30 100644
--- a/Inc/stm32l4xx_ll_pwr.h
+++ b/Inc/stm32l4xx_ll_pwr.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -1674,5 +1673,3 @@
#endif
#endif /* STM32L4xx_LL_PWR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_rcc.h b/Inc/stm32l4xx_ll_rcc.h
index fa04e5c..cc05c56 100644
--- a/Inc/stm32l4xx_ll_rcc.h
+++ b/Inc/stm32l4xx_ll_rcc.h
@@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -476,11 +474,11 @@
* @{
*/
#if defined(RCC_CCIPR2_SAI1SEL)
-#define LL_RCC_SAI1_CLKSOURCE_PLL (RCC_CCIPR2_SAI1SEL << 16U) /*!< PLL clock used as SAI1 clock source */
-#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_0) /*!< PLLSAI1 clock used as SAI1 clock source */
-#define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_1) /*!< PLLSAI2 clock used as SAI1 clock source */
-#define LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_2) /*!< HSI clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 (RCC_CCIPR2_SAI1SEL << 16U) /*!< PLLSAI1 (PLLSAI1CLK) clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_0) /*!< PLLSAI2 (PLLSAI2CLK) clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PLL ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_1) /*!< PLL (PLLSAI3CLK) clock used as SAI1 clock source */
#define LL_RCC_SAI1_CLKSOURCE_PIN ((RCC_CCIPR2_SAI1SEL << 16U) | (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0)) /*!< External input clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_2) /*!< HSI clock used as SAI1 clock source */
#elif defined(RCC_CCIPR_SAI1SEL)
#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI1SEL /*!< PLLSAI1 clock used as SAI1 clock source */
#if defined(RCC_PLLSAI2_SUPPORT)
@@ -491,11 +489,11 @@
#endif /* RCC_CCIPR2_SAI1SEL */
#if defined(RCC_CCIPR2_SAI2SEL)
-#define LL_RCC_SAI2_CLKSOURCE_PLL (RCC_CCIPR2_SAI2SEL << 16U) /*!< PLL clock used as SAI2 clock source */
-#define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_0) /*!< PLLSAI1 clock used as SAI2 clock source */
-#define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_1) /*!< PLLSAI2 clock used as SAI2 clock source */
-#define LL_RCC_SAI2_CLKSOURCE_HSI ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_2) /*!< HSI clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (RCC_CCIPR2_SAI2SEL << 16U) /*!< PLLSAI1 (PLLSAI1CLK) clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_0) /*!< PLLSAI2 (PLLSAI2CLK) clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_PLL ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_1) /*!< PLL (PLLSAI3CLK) clock used as SAI2 clock source */
#define LL_RCC_SAI2_CLKSOURCE_PIN ((RCC_CCIPR2_SAI2SEL << 16U) | (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0)) /*!< External input clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_HSI ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_2) /*!< HSI clock used as SAI2 clock source */
#elif defined(RCC_CCIPR_SAI2SEL)
#define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI2SEL /*!< PLLSAI1 clock used as SAI2 clock source */
#if defined(RCC_PLLSAI2_SUPPORT)
@@ -4144,6 +4142,17 @@
{
CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
}
+
+/**
+ * @brief Check if PLL output mapped on SAI domain clock is enabled
+ * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_IsEnabledDomain_SAI
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SAI(void)
+{
+ return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN)) ? 1UL : 0UL);
+}
+
#endif /* RCC_PLLP_SUPPORT */
/**
@@ -4171,6 +4180,16 @@
}
/**
+ * @brief Check if PLL output mapped on 48MHz domain clock is enabled
+ * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_48M
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_48M(void)
+{
+ return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL);
+}
+
+/**
* @brief Enable PLL output mapped on SYSCLK domain
* @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
* @retval None
@@ -4195,6 +4214,16 @@
}
/**
+ * @brief Check if PLL output mapped on SYSCLK domain clock is enabled
+ * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_IsEnabledDomain_SYS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SYS(void)
+{
+ return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN) == (RCC_PLLCFGR_PLLREN)) ? 1UL : 0UL);
+}
+
+/**
* @}
*/
@@ -4727,6 +4756,16 @@
}
/**
+ * @brief Check if PLLSAI1 output mapped on SAI domain clock is enabled
+ * @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_IsEnabledDomain_SAI
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsEnabledDomain_SAI(void)
+{
+ return ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN) == (RCC_PLLSAI1CFGR_PLLSAI1PEN)) ? 1UL : 0UL);
+}
+
+/**
* @brief Enable PLLSAI1 output mapped on 48MHz domain clock
* @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_EnableDomain_48M
* @retval None
@@ -4749,6 +4788,16 @@
}
/**
+ * @brief Check if PLLSAI1 output mapped on SAI domain clock is enabled
+ * @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_IsEnabledDomain_48M
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsEnabledDomain_48M(void)
+{
+ return ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN) == (RCC_PLLSAI1CFGR_PLLSAI1QEN)) ? 1UL : 0UL);
+}
+
+/**
* @brief Enable PLLSAI1 output mapped on ADC domain clock
* @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_EnableDomain_ADC
* @retval None
@@ -4771,6 +4820,16 @@
}
/**
+ * @brief Check if PLLSAI1 output mapped on ADC domain clock is enabled
+ * @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_IsEnabledDomain_ADC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsEnabledDomain_ADC(void)
+{
+ return ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN) == (RCC_PLLSAI1CFGR_PLLSAI1REN)) ? 1UL : 0UL);
+}
+
+/**
* @}
*/
#endif /* RCC_PLLSAI1_SUPPORT */
@@ -5290,6 +5349,16 @@
CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
}
+/**
+ * @brief Check if PLLSAI2 output mapped on SAI domain clock is enabled
+ * @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_IsEnabledDomain_SAI
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsEnabledDomain_SAI(void)
+{
+ return ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN) == (RCC_PLLSAI2CFGR_PLLSAI2PEN)) ? 1UL : 0UL);
+}
+
#if defined(DSI)
/**
* @brief Enable PLLSAI2 output mapped on DSI domain clock
@@ -5312,6 +5381,16 @@
{
CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN);
}
+
+/**
+ * @brief Check if PLLSAI2 output mapped on DSI domain clock is enabled
+ * @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_IsEnabledDomain_DSI
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsEnabledDomain_DSI(void)
+{
+ return ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN) == (RCC_PLLSAI2CFGR_PLLSAI2QEN)) ? 1UL : 0UL);
+}
#endif /* DSI */
#if defined(LTDC)
@@ -5336,6 +5415,16 @@
{
CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
}
+
+/**
+ * @brief Check if PLLSAI2 output mapped on LTDC domain clock is enabled
+ * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_IsEnabledDomain_LTDC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsEnabledDomain_LTDC(void)
+{
+ return ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN) == (RCC_PLLSAI2CFGR_PLLSAI2REN)) ? 1UL : 0UL);
+}
#else
/**
* @brief Enable PLLSAI2 output mapped on ADC domain clock
@@ -5358,6 +5447,16 @@
{
CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
}
+
+/**
+ * @brief Check if PLLSAI2 output mapped on ADC domain clock is enabled
+ * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_IsEnabledDomain_ADC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsEnabledDomain_ADC(void)
+{
+ return ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN) == (RCC_PLLSAI2CFGR_PLLSAI2REN)) ? 1UL : 0UL);
+}
#endif /* LTDC */
/**
@@ -6132,4 +6231,3 @@
#endif /* STM32L4xx_LL_RCC_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_rng.h b/Inc/stm32l4xx_ll_rng.h
index 6dc5f52..b4f4cfa 100644
--- a/Inc/stm32l4xx_ll_rng.h
+++ b/Inc/stm32l4xx_ll_rng.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -699,6 +698,4 @@
}
#endif
-#endif /* __STM32L4xx_LL_RNG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+#endif /* STM32L4xx_LL_RNG_H */
diff --git a/Inc/stm32l4xx_ll_rtc.h b/Inc/stm32l4xx_ll_rtc.h
index 47009b2..8d23198 100644
--- a/Inc/stm32l4xx_ll_rtc.h
+++ b/Inc/stm32l4xx_ll_rtc.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -5573,5 +5572,3 @@
#endif
#endif /* STM32L4xx_LL_RTC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_sdmmc.h b/Inc/stm32l4xx_ll_sdmmc.h
index 9fe81fe..08607a4 100644
--- a/Inc/stm32l4xx_ll_sdmmc.h
+++ b/Inc/stm32l4xx_ll_sdmmc.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -250,6 +249,11 @@
#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */
/**
+ * @brief Following commands are MMC Specific commands.
+ */
+#define SDMMC_CMD_MMC_SLEEP_AWAKE ((uint8_t)5U) /*!< Toggle the device between Sleep state and Standby state. */
+
+/**
* @brief Following commands are SD Card Specific security commands.
* SDMMC_CMD_APP_CMD should be sent before sending these commands.
*/
@@ -525,7 +529,7 @@
*/
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-/** @defgroup SDMMC_LL_Data_Length Data Lenght
+/** @defgroup SDMMC_LL_Data_Length Data Length
* @{
*/
#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
@@ -804,13 +808,13 @@
#define SDMMC_INIT_CLK_DIV ((uint8_t)0x8A)
/* SDMMC Default Speed Frequency (25Mhz max) for Peripheral CLK 110MHz*/
-#define SDMMC_NSpeed_CLK_DIV ((uint8_t)0x3)
+#define SDMMC_NSPEED_CLK_DIV ((uint8_t)0x3)
/* SDMMC High Speed Frequency (50Mhz max) for Peripheral CLK 110MHz*/
-#define SDMMC_HSpeed_CLK_DIV ((uint8_t)0x2)
+#define SDMMC_HSPEED_CLK_DIV ((uint8_t)0x2)
/* SDMMC Data Transfer Frequency (25MHz max) */
-#define SDMMC_TRANSFER_CLK_DIV SDMMC_NSpeed_CLK_DIV
+#define SDMMC_TRANSFER_CLK_DIV SDMMC_NSPEED_CLK_DIV
#else
/* SDMMC Initialization Frequency (400KHz max) */
#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */
@@ -1249,6 +1253,7 @@
uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA);
uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA);
+uint32_t SDMMC_CmdSleepMmc(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx);
#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
@@ -1295,5 +1300,3 @@
#endif
#endif /* STM32L4xx_LL_SDMMC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_spi.h b/Inc/stm32l4xx_ll_spi.h
index 1f94578..d377cca 100644
--- a/Inc/stm32l4xx_ll_spi.h
+++ b/Inc/stm32l4xx_ll_spi.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -1333,7 +1332,7 @@
*/
__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
{
- return (uint8_t)(READ_REG(SPIx->DR));
+ return (*((__IO uint8_t *)&SPIx->DR));
}
/**
@@ -1417,4 +1416,3 @@
#endif /* STM32L4xx_LL_SPI_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_swpmi.h b/Inc/stm32l4xx_ll_swpmi.h
index a1a8522..03678f3 100644
--- a/Inc/stm32l4xx_ll_swpmi.h
+++ b/Inc/stm32l4xx_ll_swpmi.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -1149,5 +1148,3 @@
#endif
#endif /* STM32L4xx_LL_SWPMI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_system.h b/Inc/stm32l4xx_ll_system.h
index f153225..94b722b 100644
--- a/Inc/stm32l4xx_ll_system.h
+++ b/Inc/stm32l4xx_ll_system.h
@@ -3,6 +3,18 @@
* @file stm32l4xx_ll_system.h
* @author MCD Application Team
* @brief Header file of SYSTEM LL module.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -17,17 +29,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@@ -1624,5 +1625,3 @@
#endif
#endif /* STM32L4xx_LL_SYSTEM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_tim.h b/Inc/stm32l4xx_ll_tim.h
index e1602ac..53a2e90 100644
--- a/Inc/stm32l4xx_ll_tim.h
+++ b/Inc/stm32l4xx_ll_tim.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -227,24 +226,29 @@
uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetPrescaler().*/
uint32_t CounterMode; /*!< Specifies the counter mode.
This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetCounterMode().*/
uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
Auto-Reload Register at the next update event.
This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
- Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
+ Some timer instances may support 32 bits counters. In that case this parameter must
+ be a number between 0x0000 and 0xFFFFFFFF.
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetAutoReload().*/
uint32_t ClockDivision; /*!< Specifies the clock division.
This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetClockDivision().*/
uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
reaches zero, an update event is generated and counting restarts
@@ -252,10 +256,13 @@
This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
- GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
- Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
+ GP timers: this parameter must be a number between Min_Data = 0x00 and
+ Max_Data = 0xFF.
+ Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
+ Max_Data = 0xFFFF.
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetRepetitionCounter().*/
} LL_TIM_InitTypeDef;
/**
@@ -266,43 +273,51 @@
uint32_t OCMode; /*!< Specifies the output mode.
This parameter can be a value of @ref TIM_LL_EC_OCMODE.
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_OC_SetMode().*/
uint32_t OCState; /*!< Specifies the TIM Output Compare state.
This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
- This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+ This feature can be modified afterwards using unitary functions
+ @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
- This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+ This feature can be modified afterwards using unitary functions
+ @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
- This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
+ This feature can be modified afterwards using unitary function
+ LL_TIM_OC_SetCompareCHx (x=1..6).*/
uint32_t OCPolarity; /*!< Specifies the output polarity.
This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_OC_SetPolarity().*/
uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_OC_SetPolarity().*/
uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_OC_SetIdleState().*/
uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_OC_SetIdleState().*/
} LL_TIM_OC_InitTypeDef;
/**
@@ -315,22 +330,26 @@
uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPolarity().*/
uint32_t ICActiveInput; /*!< Specifies the input.
This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetActiveInput().*/
uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_LL_EC_ICPSC.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPrescaler().*/
uint32_t ICFilter; /*!< Specifies the input capture filter.
This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetFilter().*/
} LL_TIM_IC_InitTypeDef;
@@ -342,47 +361,56 @@
uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetEncoderMode().*/
uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPolarity().*/
uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetActiveInput().*/
uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
This parameter can be a value of @ref TIM_LL_EC_ICPSC.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPrescaler().*/
uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetFilter().*/
uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPolarity().*/
uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetActiveInput().*/
uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
This parameter can be a value of @ref TIM_LL_EC_ICPSC.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPrescaler().*/
uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetFilter().*/
} LL_TIM_ENCODER_InitTypeDef;
@@ -395,26 +423,31 @@
uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPolarity().*/
uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
Prescaler must be set to get a maximum counter period longer than the
time interval between 2 consecutive changes on the Hall inputs.
This parameter can be a value of @ref TIM_LL_EC_ICPSC.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPrescaler().*/
uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
- This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+ This parameter can be a value of
+ @ref TIM_LL_EC_IC_FILTER.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetFilter().*/
uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
A positive pulse (TRGO event) is generated with a programmable delay every time
a change occurs on the Hall inputs.
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_OC_SetCompareCH2().*/
} LL_TIM_HALLSENSOR_InitTypeDef;
/**
@@ -425,79 +458,99 @@
uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
This parameter can be a value of @ref TIM_LL_EC_OSSR
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetOffStates()
- @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
+ @note This bit-field cannot be modified as long as LOCK level 2 has been
+ programmed. */
uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
This parameter can be a value of @ref TIM_LL_EC_OSSI
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetOffStates()
- @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
+ @note This bit-field cannot be modified as long as LOCK level 2 has been
+ programmed. */
uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
- @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
- has been written, their content is frozen until the next reset.*/
+ @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
+ register has been written, their content is frozen until the next reset.*/
uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
switching-on of the outputs.
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_OC_SetDeadTime()
- @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
+ @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
+ programmed. */
uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
- This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
+ This feature can be modified afterwards using unitary functions
+ @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
- @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
- This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_ConfigBRK()
- @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
- This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_ConfigBRK()
- @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
- This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
+ This feature can be modified afterwards using unitary functions
+ @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
- @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
- This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_ConfigBRK2()
- @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
- This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_ConfigBRK2()
- @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
- This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
+ This feature can be modified afterwards using unitary functions
+ @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
- @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
} LL_TIM_BDTR_InitTypeDef;
/**
@@ -1332,10 +1385,17 @@
* @retval DTG[0:7]
*/
#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
- ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
- (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
- (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
- (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
+ ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
+ (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
+ (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
+ (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
+ (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
+ (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
+ (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
+ (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
+ (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
+ (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
+ (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
0U)
/**
@@ -1360,7 +1420,8 @@
((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
/**
- * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
+ * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
+ * active/inactive delay.
* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
* @param __TIMCLK__ timer input clock frequency (in Hz)
* @param __PSC__ prescaler
@@ -1372,7 +1433,8 @@
/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
/**
- * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
+ * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
+ * (when the timer operates in one pulse mode).
* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
* @param __TIMCLK__ timer input clock frequency (in Hz)
* @param __PSC__ prescaler
@@ -1629,7 +1691,8 @@
}
/**
- * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
+ * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
+ * (when supported) and the digital filters.
* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
* whether or not the clock division feature is supported by the timer
* instance.
@@ -1647,7 +1710,8 @@
}
/**
- * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
+ * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
+ * generators (when supported) and the digital filters.
* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
* whether or not the clock division feature is supported by the timer
* instance.
@@ -1789,7 +1853,8 @@
/**
* @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
- * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
+ * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
+ * in an atomic way.
* @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
* @param TIMx Timer instance
* @retval None
@@ -2094,7 +2159,7 @@
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
+ MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
}
/**
@@ -2133,7 +2198,7 @@
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
+ return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
}
/**
@@ -2511,7 +2576,8 @@
}
/**
- * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
+ * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
+ * the Ocx and OCxN signals).
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* dead-time insertion feature is supported by a timer instance.
* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
@@ -2778,7 +2844,8 @@
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
- ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
+ ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
+ << SHIFT_TAB_ICxx[iChannel]);
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
(Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
}
@@ -3754,11 +3821,11 @@
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
* @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
- * @arg @ref LL_TIM_DMABURST_BASEADDR_OR2
- * @arg @ref LL_TIM_DMABURST_BASEADDR_OR3
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_OR2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_OR3
* @param DMABurstLength This parameter can be one of the following values:
* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
@@ -4260,7 +4327,8 @@
}
/**
- * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
+ * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
+ * (Capture/Compare 1 interrupt is pending).
* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
@@ -4282,7 +4350,8 @@
}
/**
- * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
+ * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
+ * (Capture/Compare 2 over-capture interrupt is pending).
* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
@@ -4304,7 +4373,8 @@
}
/**
- * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
+ * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
+ * (Capture/Compare 3 over-capture interrupt is pending).
* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
@@ -4326,7 +4396,8 @@
}
/**
- * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
+ * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
+ * (Capture/Compare 4 over-capture interrupt is pending).
* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
@@ -4633,7 +4704,7 @@
* @}
*/
-/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
+/** @defgroup TIM_LL_EF_DMA_Management DMA Management
* @{
*/
/**
@@ -5019,4 +5090,3 @@
#endif
#endif /* __STM32L4xx_LL_TIM_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_usart.h b/Inc/stm32l4xx_ll_usart.h
index 57681f5..05aa926 100644
--- a/Inc/stm32l4xx_ll_usart.h
+++ b/Inc/stm32l4xx_ll_usart.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -91,42 +90,50 @@
uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate.
This parameter can be a value of @ref USART_LL_EC_PRESCALER.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetPrescaler().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetPrescaler().*/
#endif /* USART_PRESC_PRESCALER */
uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetBaudRate().*/
uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetDataWidth().*/
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref USART_LL_EC_STOPBITS.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetStopBitsLength().*/
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref USART_LL_EC_PARITY.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetParity().*/
uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_LL_EC_DIRECTION.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetTransferDirection().*/
uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetHWFlowCtrl().*/
uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8.
This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetOverSampling().*/
} LL_USART_InitTypeDef;
@@ -145,20 +152,23 @@
uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock.
This parameter can be a value of @ref USART_LL_EC_POLARITY.
- USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().
+ USART HW configuration can be modified afterwards using unitary
+ functions @ref LL_USART_SetClockPolarity().
For more details, refer to description of this function. */
uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref USART_LL_EC_PHASE.
- USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().
+ USART HW configuration can be modified afterwards using unitary
+ functions @ref LL_USART_SetClockPhase().
For more details, refer to description of this function. */
uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
- USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().
+ USART HW configuration can be modified afterwards using unitary
+ functions @ref LL_USART_SetLastClkPulseOutput().
For more details, refer to description of this function. */
} LL_USART_ClockInitTypeDef;
@@ -177,27 +187,27 @@
* @brief Flags defines which can be used with LL_USART_WriteReg function
* @{
*/
-#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */
-#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */
-#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected flag */
-#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */
-#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */
+#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */
+#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */
+#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected clear flag */
+#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */
+#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */
#if defined(USART_CR1_FIFOEN)
-#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty Clear flag */
+#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */
#endif /* USART_CR1_FIFOEN */
-#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */
+#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */
#if defined(USART_TCBGT_SUPPORT)
-#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time flag */
+#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time clear flag */
#endif /* USART_TCBGT_SUPPORT */
-#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection flag */
-#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */
-#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout flag */
-#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block flag */
+#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection clear flag */
+#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */
+#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout clear flag */
+#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block clear flag */
#if defined(USART_CR2_SLVEN)
-#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun Clear flag */
+#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun clear flag */
#endif /* USART_CR2_SLVEN */
-#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */
-#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */
+#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */
+#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */
/**
* @}
*/
@@ -402,18 +412,18 @@
/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler
* @{
*/
-#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not devided */
-#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock devided by 2 */
-#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock devided by 4 */
-#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 6 */
-#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock devided by 8 */
-#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 10 */
-#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 12 */
-#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */
-#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock devided by 32 */
-#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 64 */
-#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 128 */
-#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */
+#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
+#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
+#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
+#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
+#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
+#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
+#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
+#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
+#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
+#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
+#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
+#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
/**
* @}
*/
@@ -612,8 +622,9 @@
* @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
*/
#if defined(USART_PRESC_PRESCALER)
-#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
- + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
+ (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
+ + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
#else
#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2U)\
+ ((__BAUDRATE__)/2U))/(__BAUDRATE__))
@@ -642,8 +653,9 @@
* @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
*/
#if defined(USART_PRESC_PRESCALER)
-#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
- + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
+ ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
+ + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
#else
#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
#endif /* USART_PRESC_PRESCALER */
@@ -705,7 +717,7 @@
#if defined(USART_CR1_FIFOEN)
/**
* @brief FIFO Mode Enable
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 FIFOEN LL_USART_EnableFIFO
* @param USARTx USART Instance
@@ -718,7 +730,7 @@
/**
* @brief FIFO Mode Disable
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 FIFOEN LL_USART_DisableFIFO
* @param USARTx USART Instance
@@ -731,7 +743,7 @@
/**
* @brief Indicate if FIFO Mode is enabled
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 FIFOEN LL_USART_IsEnabledFIFO
* @param USARTx USART Instance
@@ -744,7 +756,7 @@
/**
* @brief Configure TX FIFO Threshold
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTCFG LL_USART_SetTXFIFOThreshold
* @param USARTx USART Instance
@@ -759,12 +771,12 @@
*/
__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
{
- MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
+ ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
}
/**
* @brief Return TX FIFO Threshold Configuration
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTCFG LL_USART_GetTXFIFOThreshold
* @param USARTx USART Instance
@@ -783,7 +795,7 @@
/**
* @brief Configure RX FIFO Threshold
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 RXFTCFG LL_USART_SetRXFIFOThreshold
* @param USARTx USART Instance
@@ -798,12 +810,12 @@
*/
__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
{
- MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
+ ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
}
/**
* @brief Return RX FIFO Threshold Configuration
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 RXFTCFG LL_USART_GetRXFIFOThreshold
* @param USARTx USART Instance
@@ -822,7 +834,7 @@
/**
* @brief Configure TX and RX FIFOs Threshold
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTCFG LL_USART_ConfigFIFOsThreshold\n
* CR3 RXFTCFG LL_USART_ConfigFIFOsThreshold
@@ -845,7 +857,8 @@
*/
__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
{
- MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos));
+ ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) |
+ (RXThreshold << USART_CR3_RXFTCFG_Pos));
}
#endif /* USART_CR1_FIFOEN */
@@ -853,7 +866,7 @@
* @brief USART enabled in STOP Mode.
* @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
* USART clock selection is HSI or LSE in RCC.
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR1 UESM LL_USART_EnableInStopMode
* @param USARTx USART Instance
@@ -861,13 +874,13 @@
*/
__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_UESM);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM);
}
/**
* @brief USART disabled in STOP Mode.
* @note When this function is disabled, USART is not able to wake up the MCU from Stop mode
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR1 UESM LL_USART_DisableInStopMode
* @param USARTx USART Instance
@@ -875,12 +888,12 @@
*/
__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
}
/**
* @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode
* @param USARTx USART Instance
@@ -901,7 +914,7 @@
*/
__STATIC_INLINE void LL_USART_EnableClockInStopMode(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR3, USART_CR3_UCESM);
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_UCESM);
}
/**
@@ -913,7 +926,7 @@
*/
__STATIC_INLINE void LL_USART_DisableClockInStopMode(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR3, USART_CR3_UCESM);
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_UCESM);
}
/**
@@ -936,7 +949,7 @@
*/
__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_RE);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE);
}
/**
@@ -947,7 +960,7 @@
*/
__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
}
/**
@@ -958,7 +971,7 @@
*/
__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_TE);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE);
}
/**
@@ -969,7 +982,7 @@
*/
__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
}
/**
@@ -987,7 +1000,7 @@
*/
__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
{
- MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+ ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
}
/**
@@ -1106,7 +1119,7 @@
*/
__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_MME);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME);
}
/**
@@ -1117,7 +1130,7 @@
*/
__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
}
/**
@@ -1160,7 +1173,7 @@
/**
* @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput
* @param USARTx USART Instance
@@ -1177,7 +1190,7 @@
/**
* @brief Retrieve Clock pulse of the last data bit output configuration
* (Last bit Clock pulse output to the SCLK pin or not)
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput
* @param USARTx USART Instance
@@ -1192,7 +1205,7 @@
/**
* @brief Select the phase of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPHA LL_USART_SetClockPhase
* @param USARTx USART Instance
@@ -1208,7 +1221,7 @@
/**
* @brief Return phase of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPHA LL_USART_GetClockPhase
* @param USARTx USART Instance
@@ -1223,7 +1236,7 @@
/**
* @brief Select the polarity of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPOL LL_USART_SetClockPolarity
* @param USARTx USART Instance
@@ -1239,7 +1252,7 @@
/**
* @brief Return polarity of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPOL LL_USART_GetClockPolarity
* @param USARTx USART Instance
@@ -1254,7 +1267,7 @@
/**
* @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
@@ -1283,7 +1296,7 @@
#if defined(USART_PRESC_PRESCALER)
/**
* @brief Configure Clock source prescaler for baudrate generator and oversampling
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll PRESC PRESCALER LL_USART_SetPrescaler
* @param USARTx USART Instance
@@ -1309,7 +1322,7 @@
/**
* @brief Retrieve the Clock source prescaler for baudrate generator and oversampling
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll PRESC PRESCALER LL_USART_GetPrescaler
* @param USARTx USART Instance
@@ -1335,7 +1348,7 @@
#endif /* USART_PRESC_PRESCALER */
/**
* @brief Enable Clock output on SCLK pin
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput
* @param USARTx USART Instance
@@ -1348,7 +1361,7 @@
/**
* @brief Disable Clock output on SCLK pin
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput
* @param USARTx USART Instance
@@ -1361,7 +1374,7 @@
/**
* @brief Indicate if Clock output on SCLK pin is enabled
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput
* @param USARTx USART Instance
@@ -1580,7 +1593,7 @@
/**
* @brief Enable Auto Baud-Rate Detection
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate
* @param USARTx USART Instance
@@ -1593,7 +1606,7 @@
/**
* @brief Disable Auto Baud-Rate Detection
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate
* @param USARTx USART Instance
@@ -1606,7 +1619,7 @@
/**
* @brief Indicate if Auto Baud-Rate Detection mechanism is enabled
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud
* @param USARTx USART Instance
@@ -1619,7 +1632,7 @@
/**
* @brief Set Auto Baud-Rate mode bits
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode
* @param USARTx USART Instance
@@ -1637,7 +1650,7 @@
/**
* @brief Return Auto Baud-Rate mode
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode
* @param USARTx USART Instance
@@ -1744,7 +1757,7 @@
/**
* @brief Enable RTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl
* @param USARTx USART Instance
@@ -1757,7 +1770,7 @@
/**
* @brief Disable RTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl
* @param USARTx USART Instance
@@ -1770,7 +1783,7 @@
/**
* @brief Enable CTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl
* @param USARTx USART Instance
@@ -1783,7 +1796,7 @@
/**
* @brief Disable CTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl
* @param USARTx USART Instance
@@ -1796,7 +1809,7 @@
/**
* @brief Configure HW Flow Control mode (both CTS and RTS)
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n
* CR3 CTSE LL_USART_SetHWFlowCtrl
@@ -1815,7 +1828,7 @@
/**
* @brief Return HW Flow Control configuration (both CTS and RTS)
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n
* CR3 CTSE LL_USART_GetHWFlowCtrl
@@ -1899,7 +1912,7 @@
/**
* @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUS LL_USART_SetWKUPType
* @param USARTx USART Instance
@@ -1916,7 +1929,7 @@
/**
* @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUS LL_USART_GetWKUPType
* @param USARTx USART Instance
@@ -1978,6 +1991,10 @@
{
/* Do not overstep the size of USART_PRESCALER_TAB */
}
+ else if (BaudRate == 0U)
+ {
+ /* Can Not divide per 0 */
+ }
else if (OverSampling == LL_USART_OVERSAMPLING_8)
#else
if (OverSampling == LL_USART_OVERSAMPLING_8)
@@ -2131,7 +2148,7 @@
/**
* @brief Enable IrDA mode
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IREN LL_USART_EnableIrda
* @param USARTx USART Instance
@@ -2144,7 +2161,7 @@
/**
* @brief Disable IrDA mode
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IREN LL_USART_DisableIrda
* @param USARTx USART Instance
@@ -2157,7 +2174,7 @@
/**
* @brief Indicate if IrDA mode is enabled
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IREN LL_USART_IsEnabledIrda
* @param USARTx USART Instance
@@ -2170,7 +2187,7 @@
/**
* @brief Configure IrDA Power Mode (Normal or Low Power)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode
* @param USARTx USART Instance
@@ -2186,7 +2203,7 @@
/**
* @brief Retrieve IrDA Power Mode configuration (Normal or Low Power)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode
* @param USARTx USART Instance
@@ -2202,7 +2219,7 @@
/**
* @brief Set Irda prescaler value, used for dividing the USART clock source
* to achieve the Irda Low Power frequency (8 bits value)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler
* @param USARTx USART Instance
@@ -2211,13 +2228,13 @@
*/
__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
{
- MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);
+ MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
}
/**
* @brief Return Irda prescaler value, used for dividing the USART clock source
* to achieve the Irda Low Power frequency (8 bits value)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler
* @param USARTx USART Instance
@@ -2238,7 +2255,7 @@
/**
* @brief Enable Smartcard NACK transmission
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK
* @param USARTx USART Instance
@@ -2251,7 +2268,7 @@
/**
* @brief Disable Smartcard NACK transmission
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK
* @param USARTx USART Instance
@@ -2264,7 +2281,7 @@
/**
* @brief Indicate if Smartcard NACK transmission is enabled
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK
* @param USARTx USART Instance
@@ -2277,7 +2294,7 @@
/**
* @brief Enable Smartcard mode
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCEN LL_USART_EnableSmartcard
* @param USARTx USART Instance
@@ -2290,7 +2307,7 @@
/**
* @brief Disable Smartcard mode
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCEN LL_USART_DisableSmartcard
* @param USARTx USART Instance
@@ -2303,7 +2320,7 @@
/**
* @brief Indicate if Smartcard mode is enabled
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard
* @param USARTx USART Instance
@@ -2316,7 +2333,7 @@
/**
* @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
* In transmission mode, it specifies the number of automatic retransmission retries, before
@@ -2335,7 +2352,7 @@
/**
* @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount
* @param USARTx USART Instance
@@ -2349,7 +2366,7 @@
/**
* @brief Set Smartcard prescaler value, used for dividing the USART clock
* source to provide the SMARTCARD Clock (5 bits value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler
* @param USARTx USART Instance
@@ -2358,13 +2375,13 @@
*/
__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
{
- MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);
+ MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
}
/**
* @brief Return Smartcard prescaler value, used for dividing the USART clock
* source to provide the SMARTCARD Clock (5 bits value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler
* @param USARTx USART Instance
@@ -2378,7 +2395,7 @@
/**
* @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods
* (GT[7:0] bits : Guard time value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime
* @param USARTx USART Instance
@@ -2387,13 +2404,13 @@
*/
__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
{
- MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
+ MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
}
/**
* @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods
* (GT[7:0] bits : Guard time value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime
* @param USARTx USART Instance
@@ -2414,7 +2431,7 @@
/**
* @brief Enable Single Wire Half-Duplex mode
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex
* @param USARTx USART Instance
@@ -2427,7 +2444,7 @@
/**
* @brief Disable Single Wire Half-Duplex mode
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex
* @param USARTx USART Instance
@@ -2440,7 +2457,7 @@
/**
* @brief Indicate if Single Wire Half-Duplex mode is enabled
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex
* @param USARTx USART Instance
@@ -2461,7 +2478,7 @@
*/
/**
* @brief Enable SPI Synchronous Slave mode
- * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll CR2 SLVEN LL_USART_EnableSPISlave
* @param USARTx USART Instance
@@ -2474,7 +2491,7 @@
/**
* @brief Disable SPI Synchronous Slave mode
- * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll CR2 SLVEN LL_USART_DisableSPISlave
* @param USARTx USART Instance
@@ -2487,7 +2504,7 @@
/**
* @brief Indicate if SPI Synchronous Slave mode is enabled
- * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll CR2 SLVEN LL_USART_IsEnabledSPISlave
* @param USARTx USART Instance
@@ -2500,7 +2517,7 @@
/**
* @brief Enable SPI Slave Selection using NSS input pin
- * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @note SPI Slave Selection depends on NSS input pin
* (The slave is selected when NSS is low and deselected when NSS is high).
@@ -2515,7 +2532,7 @@
/**
* @brief Disable SPI Slave Selection using NSS input pin
- * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @note SPI Slave will be always selected and NSS input pin will be ignored.
* @rmtoll CR2 DIS_NSS LL_USART_DisableSPISlaveSelect
@@ -2529,7 +2546,7 @@
/**
* @brief Indicate if SPI Slave Selection depends on NSS input pin
- * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll CR2 DIS_NSS LL_USART_IsEnabledSPISlaveSelect
* @param USARTx USART Instance
@@ -2551,7 +2568,7 @@
/**
* @brief Set LIN Break Detection Length
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen
* @param USARTx USART Instance
@@ -2567,7 +2584,7 @@
/**
* @brief Return LIN Break Detection Length
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen
* @param USARTx USART Instance
@@ -2582,7 +2599,7 @@
/**
* @brief Enable LIN mode
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LINEN LL_USART_EnableLIN
* @param USARTx USART Instance
@@ -2595,7 +2612,7 @@
/**
* @brief Disable LIN mode
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LINEN LL_USART_DisableLIN
* @param USARTx USART Instance
@@ -2608,7 +2625,7 @@
/**
* @brief Indicate if LIN mode is enabled
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LINEN LL_USART_IsEnabledLIN
* @param USARTx USART Instance
@@ -2629,7 +2646,7 @@
/**
* @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime
* @param USARTx USART Instance
@@ -2643,7 +2660,7 @@
/**
* @brief Return DEDT (Driver Enable De-Assertion Time)
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime
* @param USARTx USART Instance
@@ -2656,7 +2673,7 @@
/**
* @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime
* @param USARTx USART Instance
@@ -2670,7 +2687,7 @@
/**
* @brief Return DEAT (Driver Enable Assertion Time)
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime
* @param USARTx USART Instance
@@ -2683,7 +2700,7 @@
/**
* @brief Enable Driver Enable (DE) Mode
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEM LL_USART_EnableDEMode
* @param USARTx USART Instance
@@ -2696,7 +2713,7 @@
/**
* @brief Disable Driver Enable (DE) Mode
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEM LL_USART_DisableDEMode
* @param USARTx USART Instance
@@ -2709,7 +2726,7 @@
/**
* @brief Indicate if Driver Enable (DE) Mode is enabled
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEM LL_USART_IsEnabledDEMode
* @param USARTx USART Instance
@@ -2722,7 +2739,7 @@
/**
* @brief Select Driver Enable Polarity
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEP LL_USART_SetDESignalPolarity
* @param USARTx USART Instance
@@ -2738,7 +2755,7 @@
/**
* @brief Return Driver Enable Polarity
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEP LL_USART_GetDESignalPolarity
* @param USARTx USART Instance
@@ -2788,7 +2805,8 @@
{
/* In Asynchronous mode, the following bits must be kept cleared:
- LINEN, CLKEN bits in the USART_CR2 register,
- - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
+ - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
}
@@ -2801,7 +2819,7 @@
* - IREN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* This function also sets the USART in Synchronous mode.
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
@@ -2824,7 +2842,8 @@
{
/* In Synchronous mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register,
- - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
+ - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
/* set the UART/USART in Synchronous mode */
@@ -2839,7 +2858,7 @@
* - IREN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* This function also set the UART/USART in LIN mode.
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
@@ -2864,7 +2883,8 @@
{
/* In LIN mode, the following bits must be kept cleared:
- STOP and CLKEN bits in the USART_CR2 register,
- - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
+ - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
/* Set the UART/USART in LIN mode */
@@ -2879,7 +2899,7 @@
* - SCEN bit in the USART_CR3 register,
* - IREN bit in the USART_CR3 register,
* This function also sets the UART/USART in Half Duplex mode.
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
@@ -2902,7 +2922,8 @@
{
/* In Half Duplex mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN and IREN bits in the USART_CR3 register.*/
+ - SCEN and IREN bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
/* set the UART/USART in Half Duplex mode */
@@ -2918,7 +2939,7 @@
* This function also configures Stop bits to 1.5 bits and
* sets the USART in Smartcard mode (SCEN bit).
* Clock Output is also enabled (CLKEN).
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
@@ -2942,7 +2963,8 @@
{
/* In Smartcard mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register,
- - IREN and HDSEL bits in the USART_CR3 register.*/
+ - IREN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
/* Configure Stop bits to 1.5 bits */
@@ -2960,7 +2982,7 @@
* - SCEN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* This function also sets the UART/USART in IRDA mode (IREN bit).
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
@@ -2985,7 +3007,8 @@
{
/* In IRDA mode, the following bits must be kept cleared:
- LINEN, STOP and CLKEN bits in the USART_CR2 register,
- - SCEN and HDSEL bits in the USART_CR3 register.*/
+ - SCEN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
/* set the UART/USART in IRDA mode */
@@ -3023,7 +3046,8 @@
{
/* In Multi Processor mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
+ - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
}
@@ -3097,7 +3121,7 @@
/**
* @brief Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR RXNE_RXFNE LL_USART_IsActiveFlag_RXNE_RXFNE
* @param USARTx USART Instance
@@ -3138,7 +3162,7 @@
/**
* @brief Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR TXE_TXFNF LL_USART_IsActiveFlag_TXE_TXFNF
* @param USARTx USART Instance
@@ -3164,7 +3188,7 @@
#endif /* USART_CR1_FIFOEN */
/**
* @brief Check if the USART LIN Break Detection Flag is set or not
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD
* @param USARTx USART Instance
@@ -3177,7 +3201,7 @@
/**
* @brief Check if the USART CTS interrupt Flag is set or not
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS
* @param USARTx USART Instance
@@ -3190,7 +3214,7 @@
/**
* @brief Check if the USART CTS Flag is set or not
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS
* @param USARTx USART Instance
@@ -3214,7 +3238,7 @@
/**
* @brief Check if the USART End Of Block Flag is set or not
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB
* @param USARTx USART Instance
@@ -3228,7 +3252,7 @@
#if defined(USART_CR2_SLVEN)
/**
* @brief Check if the SPI Slave Underrun error flag is set or not
- * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll ISR UDR LL_USART_IsActiveFlag_UDR
* @param USARTx USART Instance
@@ -3242,7 +3266,7 @@
#endif /* USART_CR2_SLVEN */
/**
* @brief Check if the USART Auto-Baud Rate Error Flag is set or not
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE
* @param USARTx USART Instance
@@ -3255,7 +3279,7 @@
/**
* @brief Check if the USART Auto-Baud Rate Flag is set or not
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR
* @param USARTx USART Instance
@@ -3312,7 +3336,7 @@
/**
* @brief Check if the USART Wake Up from stop mode Flag is set or not
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP
* @param USARTx USART Instance
@@ -3348,7 +3372,7 @@
#if defined(USART_CR1_FIFOEN)
/**
* @brief Check if the USART TX FIFO Empty Flag is set or not
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR TXFE LL_USART_IsActiveFlag_TXFE
* @param USARTx USART Instance
@@ -3361,7 +3385,7 @@
/**
* @brief Check if the USART RX FIFO Full Flag is set or not
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR RXFF LL_USART_IsActiveFlag_RXFF
* @param USARTx USART Instance
@@ -3385,12 +3409,12 @@
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);
}
-#endif /* USART_TCBGT_SUPPORT */
+#endif /* USART_TCBGT_SUPPORT */
#if defined(USART_CR1_FIFOEN)
/**
* @brief Check if the USART TX FIFO Threshold Flag is set or not
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR TXFT LL_USART_IsActiveFlag_TXFT
* @param USARTx USART Instance
@@ -3403,7 +3427,7 @@
/**
* @brief Check if the USART RX FIFO Threshold Flag is set or not
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR RXFT LL_USART_IsActiveFlag_RXFT
* @param USARTx USART Instance
@@ -3473,7 +3497,7 @@
#if defined(USART_CR1_FIFOEN)
/**
* @brief Clear TX FIFO Empty Flag
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ICR TXFECF LL_USART_ClearFlag_TXFE
* @param USARTx USART Instance
@@ -3512,7 +3536,7 @@
/**
* @brief Clear LIN Break Detection Flag
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD
* @param USARTx USART Instance
@@ -3525,7 +3549,7 @@
/**
* @brief Clear CTS Interrupt Flag
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS
* @param USARTx USART Instance
@@ -3549,7 +3573,7 @@
/**
* @brief Clear End Of Block Flag
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB
* @param USARTx USART Instance
@@ -3563,7 +3587,7 @@
#if defined(USART_CR2_SLVEN)
/**
* @brief Clear SPI Slave Underrun Flag
- * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll ICR UDRCF LL_USART_ClearFlag_UDR
* @param USARTx USART Instance
@@ -3588,7 +3612,7 @@
/**
* @brief Clear Wake Up from stop mode Flag
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP
* @param USARTx USART Instance
@@ -3615,7 +3639,7 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
}
#if defined(USART_CR1_FIFOEN)
@@ -3624,7 +3648,7 @@
/**
* @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_EnableIT_RXNE_RXFNE
* @param USARTx USART Instance
@@ -3632,7 +3656,7 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
}
#else
@@ -3644,7 +3668,7 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_RXNEIE);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE);
}
#endif /* USART_CR1_FIFOEN */
@@ -3656,7 +3680,7 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_TCIE);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE);
}
#if defined(USART_CR1_FIFOEN)
@@ -3665,7 +3689,7 @@
/**
* @brief Enable TX Empty and TX FIFO Not Full Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXEIE_TXFNFIE LL_USART_EnableIT_TXE_TXFNF
* @param USARTx USART Instance
@@ -3673,7 +3697,7 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
}
#else
@@ -3685,7 +3709,7 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_TXEIE);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE);
}
#endif /* USART_CR1_FIFOEN */
@@ -3697,7 +3721,7 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_PEIE);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE);
}
/**
@@ -3708,7 +3732,7 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_CMIE);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE);
}
/**
@@ -3719,12 +3743,12 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
}
/**
* @brief Enable End Of Block Interrupt
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB
* @param USARTx USART Instance
@@ -3732,13 +3756,13 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
}
#if defined(USART_CR1_FIFOEN)
/**
* @brief Enable TX FIFO Empty Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXFEIE LL_USART_EnableIT_TXFE
* @param USARTx USART Instance
@@ -3746,7 +3770,7 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_TXFEIE);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE);
}
/**
@@ -3757,13 +3781,13 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_RXFFIE);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE);
}
#endif /* USART_CR1_FIFOEN */
/**
* @brief Enable LIN Break Detection Interrupt
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD
* @param USARTx USART Instance
@@ -3786,12 +3810,12 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR3, USART_CR3_EIE);
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE);
}
/**
* @brief Enable CTS Interrupt
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS
* @param USARTx USART Instance
@@ -3799,12 +3823,12 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
}
/**
* @brief Enable Wake Up from Stop Mode Interrupt
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP
* @param USARTx USART Instance
@@ -3812,13 +3836,13 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
}
#if defined(USART_CR1_FIFOEN)
/**
* @brief Enable TX FIFO Threshold Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTIE LL_USART_EnableIT_TXFT
* @param USARTx USART Instance
@@ -3826,7 +3850,7 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR3, USART_CR3_TXFTIE);
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE);
}
#endif /* USART_CR1_FIFOEN */
@@ -3834,7 +3858,7 @@
/* Function available only on devices supporting Transmit Complete before Guard Time feature */
/**
* @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT
* @param USARTx USART Instance
@@ -3842,14 +3866,14 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
}
#endif /* USART_TCBGT_SUPPORT */
#if defined(USART_CR1_FIFOEN)
/**
* @brief Enable RX FIFO Threshold Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 RXFTIE LL_USART_EnableIT_RXFT
* @param USARTx USART Instance
@@ -3857,7 +3881,7 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR3, USART_CR3_RXFTIE);
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE);
}
#endif /* USART_CR1_FIFOEN */
@@ -3869,7 +3893,7 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
}
#if defined(USART_CR1_FIFOEN)
@@ -3878,7 +3902,7 @@
/**
* @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_DisableIT_RXNE_RXFNE
* @param USARTx USART Instance
@@ -3886,7 +3910,7 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
}
#else
@@ -3898,7 +3922,7 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE);
}
#endif /* USART_CR1_FIFOEN */
@@ -3910,7 +3934,7 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
}
#if defined(USART_CR1_FIFOEN)
@@ -3919,7 +3943,7 @@
/**
* @brief Disable TX Empty and TX FIFO Not Full Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXEIE_TXFNFIE LL_USART_DisableIT_TXE_TXFNF
* @param USARTx USART Instance
@@ -3927,7 +3951,7 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
}
#else
@@ -3939,7 +3963,7 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE);
}
#endif /* USART_CR1_FIFOEN */
@@ -3951,7 +3975,7 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
}
/**
@@ -3962,7 +3986,7 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
}
/**
@@ -3973,12 +3997,12 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
}
/**
* @brief Disable End Of Block Interrupt
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB
* @param USARTx USART Instance
@@ -3986,13 +4010,13 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
}
#if defined(USART_CR1_FIFOEN)
/**
* @brief Disable TX FIFO Empty Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXFEIE LL_USART_DisableIT_TXFE
* @param USARTx USART Instance
@@ -4000,12 +4024,12 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE);
}
/**
* @brief Disable RX FIFO Full Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 RXFFIE LL_USART_DisableIT_RXFF
* @param USARTx USART Instance
@@ -4013,13 +4037,13 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE);
}
#endif /* USART_CR1_FIFOEN */
/**
* @brief Disable LIN Break Detection Interrupt
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD
* @param USARTx USART Instance
@@ -4042,12 +4066,12 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
}
/**
* @brief Disable CTS Interrupt
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS
* @param USARTx USART Instance
@@ -4055,12 +4079,12 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
}
/**
* @brief Disable Wake Up from Stop Mode Interrupt
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP
* @param USARTx USART Instance
@@ -4068,13 +4092,13 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
}
#if defined(USART_CR1_FIFOEN)
/**
* @brief Disable TX FIFO Threshold Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTIE LL_USART_DisableIT_TXFT
* @param USARTx USART Instance
@@ -4082,7 +4106,7 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE);
}
#endif /* USART_CR1_FIFOEN */
@@ -4090,7 +4114,7 @@
/* Function available only on devices supporting Transmit Complete before Guard Time feature */
/**
* @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT
* @param USARTx USART Instance
@@ -4098,14 +4122,14 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
}
#endif /* USART_TCBGT_SUPPORT */
#if defined(USART_CR1_FIFOEN)
/**
* @brief Disable RX FIFO Threshold Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 RXFTIE LL_USART_DisableIT_RXFT
* @param USARTx USART Instance
@@ -4113,7 +4137,7 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE);
}
#endif /* USART_CR1_FIFOEN */
@@ -4134,7 +4158,7 @@
/**
* @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_IsEnabledIT_RXNE_RXFNE
* @param USARTx USART Instance
@@ -4175,7 +4199,7 @@
/**
* @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXEIE_TXFNFIE LL_USART_IsEnabledIT_TXE_TXFNF
* @param USARTx USART Instance
@@ -4234,7 +4258,7 @@
/**
* @brief Check if the USART End Of Block Interrupt is enabled or disabled.
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB
* @param USARTx USART Instance
@@ -4248,7 +4272,7 @@
#if defined(USART_CR1_FIFOEN)
/**
* @brief Check if the USART TX FIFO Empty Interrupt is enabled or disabled
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXFEIE LL_USART_IsEnabledIT_TXFE
* @param USARTx USART Instance
@@ -4261,7 +4285,7 @@
/**
* @brief Check if the USART RX FIFO Full Interrupt is enabled or disabled
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 RXFFIE LL_USART_IsEnabledIT_RXFF
* @param USARTx USART Instance
@@ -4275,7 +4299,7 @@
#endif /* USART_CR1_FIFOEN */
/**
* @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled.
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD
* @param USARTx USART Instance
@@ -4299,7 +4323,7 @@
/**
* @brief Check if the USART CTS Interrupt is enabled or disabled.
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS
* @param USARTx USART Instance
@@ -4312,7 +4336,7 @@
/**
* @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP
* @param USARTx USART Instance
@@ -4326,7 +4350,7 @@
#if defined(USART_CR1_FIFOEN)
/**
* @brief Check if USART TX FIFO Threshold Interrupt is enabled or disabled
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTIE LL_USART_IsEnabledIT_TXFT
* @param USARTx USART Instance
@@ -4342,7 +4366,7 @@
/* Function available only on devices supporting Transmit Complete before Guard Time feature */
/**
* @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT
* @param USARTx USART Instance
@@ -4357,7 +4381,7 @@
#if defined(USART_CR1_FIFOEN)
/**
* @brief Check if USART RX FIFO Threshold Interrupt is enabled or disabled
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 RXFTIE LL_USART_IsEnabledIT_RXFT
* @param USARTx USART Instance
@@ -4385,7 +4409,7 @@
*/
__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR3, USART_CR3_DMAR);
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR);
}
/**
@@ -4396,7 +4420,7 @@
*/
__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
}
/**
@@ -4418,7 +4442,7 @@
*/
__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR3, USART_CR3_DMAT);
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT);
}
/**
@@ -4429,7 +4453,7 @@
*/
__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
}
/**
@@ -4568,7 +4592,7 @@
/**
* @brief Request an Automatic Baud Rate measurement on next received data frame
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate
* @param USARTx USART Instance
@@ -4604,7 +4628,7 @@
/**
@if USART_CR1_FIFOEN
* @brief Request a Receive Data and FIFO flush
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @note Allows to discard the received data without reading them, and avoid an overrun
* condition.
@@ -4623,7 +4647,7 @@
/**
@if USART_CR1_FIFOEN
* @brief Request a Transmit data and FIFO flush
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
@else
* @brief Request a Transmit data flush
@@ -4675,4 +4699,3 @@
#endif /* STM32L4xx_LL_USART_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_usb.h b/Inc/stm32l4xx_ll_usb.h
index 571f0c4..ddc9348 100644
--- a/Inc/stm32l4xx_ll_usb.h
+++ b/Inc/stm32l4xx_ll_usb.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -23,7 +22,7 @@
#ifdef __cplusplus
extern "C" {
-#endif
+#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
@@ -80,6 +79,7 @@
HC_DATATGLERR
} USB_OTG_HCStateTypeDef;
+
/**
* @brief USB Instance Initialization Structure definition
*/
@@ -94,14 +94,15 @@
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t speed; /*!< USB Core speed.
- This parameter can be any value of @ref USB_Core_Speed */
+ This parameter can be any value of @ref PCD_Speed/HCD_Speed
+ (HCD_SPEED_xxx, HCD_SPEED_xxx) */
uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
uint32_t phy_itface; /*!< Select the used PHY interface.
- This parameter can be any value of @ref USB_Core_PHY */
+ This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
@@ -131,7 +132,7 @@
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t type; /*!< Endpoint type
- This parameter can be any value of @ref USB_EP_Type_ */
+ This parameter can be any value of @ref USB_LL_EP_Type */
uint8_t data_pid_start; /*!< Initial data PID
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
@@ -168,15 +169,16 @@
uint8_t ep_is_in; /*!< Endpoint direction
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
- uint8_t speed; /*!< USB Host speed.
- This parameter can be any value of @ref USB_Core_Speed_ */
+ uint8_t speed; /*!< USB Host Channel speed.
+ This parameter can be any value of @ref HCD_Device_Speed:
+ (HCD_DEVICE_SPEED_xxx) */
uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */
uint8_t ep_type; /*!< Endpoint Type.
- This parameter can be any value of @ref USB_EP_Type_ */
+ This parameter can be any value of @ref USB_LL_EP_Type */
uint16_t max_packet; /*!< Endpoint Max packet size.
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
@@ -186,7 +188,7 @@
uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
- uint32_t XferSize; /*!< OTG Channel transfer size. */
+ uint32_t XferSize; /*!< OTG Channel transfer size. */
uint32_t xfer_len; /*!< Current transfer length. */
@@ -227,12 +229,13 @@
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t speed; /*!< USB Core speed.
- This parameter can be any value of @ref USB_Core_Speed */
+ This parameter can be any value of @ref PCD_Speed/HCD_Speed
+ (HCD_SPEED_xxx, HCD_SPEED_xxx) */
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
uint32_t phy_itface; /*!< Select the used PHY interface.
- This parameter can be any value of @ref USB_Core_PHY */
+ This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
@@ -241,6 +244,8 @@
uint32_t lpm_enable; /*!< Enable or disable Battery charging. */
uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
+
+ uint32_t dma_enable; /*!< dma_enable state unused, DMA not supported by FS instance */
} USB_CfgTypeDef;
typedef struct
@@ -338,7 +343,6 @@
/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY
* @{
*/
-#define USB_OTG_ULPI_PHY 1U
#define USB_OTG_EMBEDDED_PHY 2U
/**
* @}
@@ -388,10 +392,10 @@
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
* @{
*/
-#define EP_MPS_64 0U
-#define EP_MPS_32 1U
-#define EP_MPS_16 2U
-#define EP_MPS_8 3U
+#define EP_MPS_64 0U
+#define EP_MPS_32 1U
+#define EP_MPS_16 2U
+#define EP_MPS_8 3U
/**
* @}
*/
@@ -469,12 +473,19 @@
#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)
#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))
-#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
-#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
+#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\
+ + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
+
+#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\
+ + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
+
#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))
-#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
+#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\
+ + USB_OTG_HOST_CHANNEL_BASE\
+ + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
+
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
@@ -518,6 +529,10 @@
#if defined (USB)
#define EP_ADDR_MSK 0x7U
#endif /* defined (USB) */
+
+#ifndef USE_USB_DOUBLE_BUFFER
+#define USE_USB_DOUBLE_BUFFER 1U
+#endif /* USE_USB_DOUBLE_BUFFER */
/**
* @}
*/
@@ -563,6 +578,7 @@
void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address);
HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx);
@@ -614,7 +630,8 @@
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
-#endif
+HAL_StatusTypeDef USB_EPStopXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
+#endif /* defined (HAL_PCD_MODULE_ENABLED) */
HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address);
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx);
@@ -660,9 +677,7 @@
#ifdef __cplusplus
}
-#endif
+#endif /* __cplusplus */
#endif /* STM32L4xx_LL_USB_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_utils.h b/Inc/stm32l4xx_ll_utils.h
index eedac72..d465c0d 100644
--- a/Inc/stm32l4xx_ll_utils.h
+++ b/Inc/stm32l4xx_ll_utils.h
@@ -3,6 +3,18 @@
* @file stm32l4xx_ll_utils.h
* @author MCD Application Team
* @brief Header file of UTILS LL module.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -16,17 +28,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@@ -326,5 +327,3 @@
#endif
#endif /* STM32L4xx_LL_UTILS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l4xx_ll_wwdg.h b/Inc/stm32l4xx_ll_wwdg.h
index 93b871f..32e27b9 100644
--- a/Inc/stm32l4xx_ll_wwdg.h
+++ b/Inc/stm32l4xx_ll_wwdg.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -315,5 +314,3 @@
#endif
#endif /* STM32L4xx_LL_WWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/License.md b/License.md
index f8a5385..479c4f6 100644
--- a/License.md
+++ b/License.md
@@ -1,3 +1,27 @@
-# Copyright (c) 2017 STMicroelectronics
+Copyright 2017 STMicroelectronics.
+All rights reserved.
-This software component is licensed by STMicroelectronics under the **BSD 3-Clause** license. You may not use this file except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/BSD-3-Clause).
\ No newline at end of file
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice,
+this list of conditions and the following disclaimer in the documentation and/or
+other materials provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors
+may be used to endorse or promote products derived from this software without
+specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/README.md b/README.md
index a4ee9f6..7ed0668 100644
--- a/README.md
+++ b/README.md
@@ -1,14 +1,16 @@
# STM32CubeL4 HAL Driver MCU Component
+
+
## Overview
-**STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost.
+**STM32Cube** is an STMicroelectronics original initiative to ease developers' life by reducing efforts, time and cost.
**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series.
* The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product.
* The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio.
* The BSP drivers of each evaluation, demonstration or nucleo board provided for this STM32 series.
- * A consistent set of middleware components such as RTOS, USB, FatFS, graphics, touch sensing library...
+ * A consistent set of middleware libraries such as RTOS, USB, FatFS, graphics, touch sensing library...
* A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series.
Two models of publication are proposed for the STM32Cube embedded software:
@@ -19,13 +21,6 @@
This **stm32l4xx_hal_driver** MCU component repo is one element of the STM32CubeL4 MCU embedded software package, providing the **HAL-LL Drivers** part.
-## License
-
-Copyright (c) 2017 STMicroelectronics.
-
-This software component is licensed by STMicroelectronics under BSD 3-Clause license. You may not use this file except in compliance with the License.
-You may obtain a copy of the License [here](https://opensource.org/licenses/BSD-3-Clause).
-
## Release note
Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/stm32l4xx_hal_driver/blob/master/Release_Notes.html).
@@ -43,6 +38,7 @@
Tag v1.11.1 | Tag v1.6.1 | Tag v5.4.0_cm4 | Tag v1.15.1 (and following, if any, till next HAL tag)
Tag v1.12.0 | Tag v1.7.0 | Tag v5.6.0_cm4 | Tag v1.16.0 (and following, if any, till next HAL tag)
Tag v1.13.0 | Tag v1.7.1 | Tag v5.6.0_cm4 | Tag v1.17.0 (and following, if any, till next HAL tag)
+Tag v1.13.1 | Tag v1.7.2 | Tag v5.6.0_cm4 | Tag v1.17.1 (and following, if any, till next HAL tag)
Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/stm32l4xx_hal_driver/blob/master/Release_Notes.html).
@@ -50,6 +46,6 @@
## Troubleshooting
-If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/stm32l4xx_hal_driver/issues/new).
+If you have any issue with the **Software content** of this repository, you can file an issue [here](https://github.com/STMicroelectronics/stm32l4xx_hal_driver/issues/new/choose).
-For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
\ No newline at end of file
+For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
diff --git a/Release_Notes.html b/Release_Notes.html
index 2a83f2a..5d12fc0 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -27,9 +27,6 @@
</p>
<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
</center>
-<h1 id="license">License</h1>
-<p>Licensed by ST under BSD 3-Clause license (the "License"). You may not use this package except in compliance with the License. You may obtain a copy of the License at:</p>
-<p><a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a></p>
<h1 id="purpose">Purpose</h1>
<p>The STM32Cube HAL and LL, an STM32 abstraction layer embedded software, ensure maximized portability across STM32 portfolio.</p>
<p>The portable APIs layer provides a generic, multi instanced and simple set of APIs to interact with the upper layer (application, libraries and stacks). It is composed of native and extended APIs set. It is directly built around a generic architecture and allows the build-upon layers, like the middleware layer, to implement its functions without knowing in-depth the used STM32 device. This improves the library code reusability and guarantees an easy portability on other devices and STM32 families.</p>
@@ -44,10 +41,235 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section29" checked aria-hidden="true"> <label for="collapse-section29" aria-hidden="true">V1.13.0 / 11-February-2021</label>
+<input type="checkbox" id="collapse-section31" checked aria-hidden="true"> <label for="collapse-section32" aria-hidden="true">V1.13.2 / 26-November-2021</label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
+<li>Maintenance release of <strong>HAL and Low Layer</strong> drivers to include latest corrections</li>
+</ul>
+<h2 id="contents">Contents</h2>
+<ul>
+<li><strong>RCC_HAL</strong>
+<ul>
+<li>Update IS_RCC_PERIPHCLOCK() macro definition depending on targeted derivative.</li>
+<li>Add new HAL_RCC_GetResetSource() API to get all reset sources and clear flags.</li>
+<li>Update PLL clock source configuration to fix warnings with the GCC compiler.</li>
+<li>Add check of PLL enable bit when a peripheral using PPL P or PLL Q.</li>
+<li>Add new LL inline APIs to check specific PLL, PLLSAI1 and PLLSAI2 domains output:
+<ul>
+<li>LL_RCC_PLL_IsEnabledDomain_SAI()</li>
+<li>LL_RCC_PLL_IsEnabledDomain_48M()</li>
+<li>LL_RCC_PLL_IsEnabledDomain_SYS()</li>
+<li>LL_RCC_PLLSAI1_IsEnabledDomain_SAI()</li>
+<li>LL_RCC_PLLSAI1_IsEnabledDomain_48M()</li>
+<li>LL_RCC_PLLSAI1_IsEnabledDomain_ADC()</li>
+<li>LL_RCC_PLLSAI2_IsEnabledDomain_SAI()</li>
+<li>LL_RCC_PLLSAI2_IsEnabledDomain_DSI()</li>
+<li>LL_RCC_PLLSAI2_IsEnabledDomain_LTDC()</li>
+<li>LL_RCC_PLLSAI2_IsEnabledDomain_ADC()</li>
+</ul></li>
+<li>Fix SAI clock source definition when RCC_CCIPR2_SAI1SEL and RCC_CCIPR2_SAI2SEL are present.</li>
+<li>Update IS_RCC_PERIPHCLOCK() macro definition depending on targeted derivative.</li>
+</ul></li>
+<li><strong>EXTI_HAL</strong>
+<ul>
+<li>Update HAL_EXTI_GetConfigLine() API to set default configuration value of Trigger and GPIOSel before checking each corresponding registers.</li>
+</ul></li>
+<li><strong>FLASH_HAL</strong>
+<ul>
+<li>Disable ICache while Flash programming.</li>
+<li>Update HAL_FLASHEx_Erase() to remove __HAL_FLASH_INSTRUCTION_CACHE_DISABLE().</li>
+</ul></li>
+<li><strong>GPIO_HAL</strong>
+<ul>
+<li>Update HAL_GPIO_Init() API to avoid the configuration of PUPDR register when Analog mode is selected.</li>
+<li>Optimize assertion control for GPIO Pull mode in HAL_GPIO_Init() API.</li>
+<li>Reorder EXTI configuration sequence in order to avoid unexpected level detection.</li>
+</ul></li>
+<li><strong>ADC_HAL/LL</strong>
+<ul>
+<li>Update of the TEMPSENSOR_CAL2_TEMP value in the ll_adc.h file.</li>
+<li>Remove useless binary mask.</li>
+<li>Update LL_ADC driver to prevent unused argument compilation warning.</li>
+</ul></li>
+<li><strong>OPAMP_HAL/LL</strong>
+<ul>
+<li>LL_OPAMP_SetTrimmingValue()/LL_OPAMP_GetTrimmingValue(): redefinition of registers address MUST be volatile (_IO)</li>
+</ul></li>
+<li><strong>RTC_BKP_HAL/LL</strong>
+<ul>
+<li>Update __HAL_RTC_…(<strong>HANDLE</strong>, …) macros to access registers through (<strong>HANDLE</strong>)->Instance pointer and avoid "unused variable" warnings.</li>
+<li>Fix bad reference to RTC handle in LL_RTC_TIME_Init() & LL_RTC_DATE_Init() APIs</li>
+</ul></li>
+<li><strong>CAN_HAL</strong>
+<ul>
+<li>Update HAL_CAN_Init() API to be aligned with reference manual and to avoid timeout error:
+<ul>
+<li>Update CAN Initialization sequence to set "request initialization" bit before exit from sleep mode.</li>
+</ul></li>
+</ul></li>
+<li><strong>SPI_HAL/LL</strong>
+<ul>
+<li>General update to fix MISRA-C 2012 Rule-13.2 issue.</li>
+<li>Update LL_SPI_TransmitData8() API to avoid casting the result to 8 bits.</li>
+</ul></li>
+<li><strong>I2C_HAL</strong>
+<ul>
+<li>Fix written reserved bit 28 in I2C_CR2 register</li>
+<li>Updated I2C_IsAcknowledgeFailed() API to avoid I2C in busy state if NACK received after transmitting register address.</li>
+<li>Update to handle errors in polling mode.
+<ul>
+<li>Rename I2C_IsAcknowledgeFailed() to I2C_IsErrorOccurred() and correctly manage when error occurs.</li>
+</ul></li>
+<li>Update to fix issue detected due to low system frequency execution (HSI).</li>
+<li>Declare an internal macro link to DMA macro to check remaining data: I2C_GET_DMA_REMAIN_DATA</li>
+</ul></li>
+<li><strong>SMBUS_HAL</strong>
+<ul>
+<li>Update to fix issue of mismatched data received by master in case of data size to be transmitted by the slave is greater than the data size to be received by the master.
+<ul>
+<li>Add flush on TX register.</li>
+</ul></li>
+<li>Add the support of wake up capability.
+<ul>
+<li>Add new APIs:
+<ul>
+<li>HAL_SMBUSEx_EnableWakeUp()</li>
+<li>HAL_SMBUSEx_DisableWakeUp()</li>
+</ul></li>
+</ul></li>
+</ul></li>
+<li><strong>UART_HAL</strong>
+<ul>
+<li>Fix erroneous UART’s handle state in case of error returned after DMA reception start within UART_Start_Receive_DMA().</li>
+<li>Correction on UART ReceptionType management in case of ReceptionToIdle API are called from RxEvent callback</li>
+<li>Handling of UART concurrent register access in case of race condition between Tx and Rx transfers (HAL UART and LL LPUART)</li>
+<li>Improve header description of UART_WaitOnFlagUntilTimeout() function</li>
+<li>Add a check on the UART parity before enabling the parity error interruption.</li>
+<li>Add const qualifier for read only pointers.</li>
+<li>Fix wrong cast when computing the USARTDIV value in UART_SetConfig().</li>
+</ul></li>
+<li><strong>LPUART_LL</strong>
+<ul>
+<li>Remove TXFECF reference from LL LPUART driver</li>
+</ul></li>
+<li><strong>USART_HAL/LL</strong>
+<ul>
+<li>Handling of UART concurrent register access in case of race condition between Tx and Rx transfers (HAL UART and LL LPUART)</li>
+<li>Fix compilation warnings generated with ARMV6 compiler</li>
+<li>Improve header description of USART_WaitOnFlagUntilTimeout() function</li>
+<li>Add a check on the USART parity before enabling the parity error interrupt.</li>
+<li>Add const qualifier for read only pointers.</li>
+</ul></li>
+<li><strong>SMARTCARD_HAL</strong>
+<ul>
+<li>Improve header description of SMARTCARD_WaitOnFlagUntilTimeout() function</li>
+<li>Add const qualifier for read only pointers.</li>
+<li>Fix wrong cast when computing the USARTDIV value in SMARTCARD_SetConfig().</li>
+</ul></li>
+<li><strong>IRDA_HAL</strong>
+<ul>
+<li>Improve header description of IRDA_WaitOnFlagUntilTimeout() function</li>
+<li>Add a check on the IRDA parity before enabling the parity error interrupt.</li>
+<li>Add const qualifier for read only pointers.</li>
+<li>Fix wrong cast when computing the USARTDIV value in IRDA_SetConfig().</li>
+</ul></li>
+<li><strong>DSI_HAL</strong>
+<ul>
+<li>Update HAL_DSI_Read() to avoid HAL_TIMEOUT when a DSI read command is issued to the panel and the read data is not captured by the DSI Host which returns Packet Size Error.</li>
+<li>Update HAL_DSI_ExitULPM() to force DSI refresh</li>
+</ul></li>
+<li><strong>DCMI_HAL</strong>
+<ul>
+<li>Add const qualifier for read only pointers.</li>
+</ul></li>
+<li><strong>TIM_HAL</strong>
+<ul>
+<li>Fix compilation warnings with MDK-ARM</li>
+<li>Update HAL_TIMEx_ConfigBreakInput to use CMSIS TIM1_OR2_BKDF1BK0E_Pos definition instead of its hard coded value.</li>
+</ul></li>
+<li><strong>LPTIM_HAL</strong>RNG
+<ul>
+<li>Add __HAL_LPTIM_RESET_COUNTER() and __HAL_LPTIM_RESET_COUNTER_AFTERREAD() macros managing the synchronous/asynchronous LPTIM counter reset.</li>
+<li>Add check on PRIMASK register to prevent from enabling unwanted global interrupts within LPTIM_Disable() and LL_LPTIM_Disable()</li>
+</ul></li>
+<li><strong>NOR_HAL</strong>
+<ul>
+<li>Align HAL_NOR_Init() API with core of the function when write operation is disabled to avoid HardFault.</li>
+</ul></li>
+<li><strong>SDMMC_HAL</strong>
+<ul>
+<li>Fix Incorrect command sent in MMC_PowerOn
+<ul>
+<li>Update SEND_OP_COND (CMD1) to indicate as argument that the sector mode is supported by the host.</li>
+</ul></li>
+<li>Add new HAL_MMC_SleepDevice() API to Switch device from Standby State to Sleep State.</li>
+<li>Fix MMC & SD chapters generation for PDF User Manual</li>
+</ul></li>
+<li><strong>PKA_HAL</strong>
+<ul>
+<li>Update to fix Montgomery multiplication in PKA.</li>
+</ul></li>
+<li><strong>USB_LL/HAL</strong>
+<ul>
+<li>Update in USB_SetCurrentMode() API to improve required wait timing to change core mode.</li>
+<li>Remove non required 200ms delay during host initialization.</li>
+<li>Update USB_FlushRxFifo() and USB_FlushTxFifo() APIs by adding check on AHB master IDLE state before flushing the USB FIFO.</li>
+<li>Fix isochronous transfer in double buffer mode.</li>
+<li>Update to avoid compiler optimization on count variable used for USB HAL timeout loop check.</li>
+<li>Add missing registres callbacks check for HAL_HCD_HC_NotifyURBChange_Callback() API.</li>
+<li>Add new HAL_PCD_SetTestMode() API to handle USB device high speed Test modes.</li>
+<li>Update to set SNAK for EPs not required during device reset.</li>
+<li>Add new API HAL_PCD_EP_Abort() to abort current USB endpoint transfer.</li>
+<li>Footprint optimization in case USB double buffer mode not used, code protected with new define USE_USB_DOUBLE_BUFFER</li>
+<li>Update to avoid multiple reads of USB ISR register</li>
+</ul></li>
+<li><strong>RNG_HAL</strong>
+<ul>
+<li>Fix Seed error due to a wrong HTCR value</li>
+</ul></li>
+<li><strong>IWDG_HAL</strong>
+<ul>
+<li>Update HAL_IWDG_Init() API in order to fix HAL_GetTick() timeout vulnerability issue.</li>
+<li>Add LSI startup time in default IWDG timeout calculation (HAL_IWDG_DEFAULT_TIMEOUT).</li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section30" aria-hidden="true"> <label for="collapse-section30" aria-hidden="true">V1.13.1 / 24-September-2021</label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
+<li>Patch release only of ** USB HAL and Low Layer** drivers to include latest corrections</li>
+</ul>
+<h2 id="contents-1">Contents</h2>
+<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
+<ul>
+<li><strong>HAL USB PCD</strong> driver
+<ul>
+<li>Fix double buffer mode isochronous IN transfer</li>
+<li>Optimize USB IRQ handler by removing multiple reads from USB interrupt registers</li>
+</ul></li>
+<li><strong>HAL USB HCD</strong> driver
+<ul>
+<li>Optimize USB IRQ handler by removing multiple reads on USB interrupt registers</li>
+</ul></li>
+</ul>
+<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">LL drivers changes</span></span></strong></p>
+<ul>
+<li><strong>LL USB</strong> driver
+<ul>
+<li>Correction added on USB_ReadPacket() to ensure a byte by byte read from USB FiFO</li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section29" aria-hidden="true"> <label for="collapse-section29" aria-hidden="true">V1.13.0 / 11-February-2021</label>
+<div>
+<h2 id="main-changes-2">Main Changes</h2>
+<ul>
<li>Maintenance release of <strong>HAL and Low Layer</strong> drivers to include latest corrections
<ul>
<li>Update of HAL SMBUS driver to introduce fast mode and fast mode plus
@@ -66,7 +288,7 @@
</ul></li>
</ul></li>
</ul>
-<h2 id="contents">Contents</h2>
+<h2 id="contents-2">Contents</h2>
<h3 id="halll-generic-updates"><strong>HAL/LL generic</strong> updates</h3>
<ul>
<li>stm32l4xx_hal_timebase_tim_template.c
@@ -232,12 +454,12 @@
<div class="collapse">
<input type="checkbox" id="collapse-section28" aria-hidden="true"> <label for="collapse-section28" aria-hidden="true">V1.12.0 / 26-June-2020</label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
<ul>
<li>Maintenance release of <strong>HAL and Low Layer</strong> drivers to include latest corrections</li>
<li>Update of <strong>HAL OSPI</strong> driver introducing <strong>compatibility break</strong> with previous versions</li>
</ul>
-<h2 id="contents-1">Contents</h2>
+<h2 id="contents-3">Contents</h2>
<h3 id="halll-generic-updates-1"><strong>HAL/LL generic</strong> updates</h3>
<ul>
<li>Remove the use of keyword register in HAL/LL drivers</li>
@@ -402,11 +624,11 @@
<div class="collapse">
<input type="checkbox" id="collapse-section27" aria-hidden="true"> <label for="collapse-section27" aria-hidden="true">V1.11.1 / 07-February-2020</label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
<ul>
<li>Patch release of <strong>HAL and Low Layer</strong> drivers to include latest corrections</li>
</ul>
-<h2 id="contents-2">Contents</h2>
+<h2 id="contents-4">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<ul>
<li><strong>HAL GPIO</strong> driver
@@ -449,7 +671,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section26" aria-hidden="true"> <label for="collapse-section26" aria-hidden="true">V1.11.0 / 22-November-2019</label>
<div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-5">Main Changes</h2>
<ul>
<li>Release of <strong>HAL and Low Layer</strong> drivers to add support of <strong>STM32L4P5xx/STM32L4Q5xx</strong> devices
<ul>
@@ -459,7 +681,7 @@
</li>
<li>Correction of several issues applicable to other devices</li>
</ul>
-<h2 id="contents-3">Contents</h2>
+<h2 id="contents-5">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<ul>
<li><strong>HAL</strong> driver
@@ -770,7 +992,7 @@
</li>
</ul></li>
</ul></li>
-<li>Correct <em>LL_RTC_SCR_ALRAF</em> constant mispelling</li>
+<li>Correct <em>LL_RTC_SCR_ALRAF</em> constant misspelling</li>
</ul></li>
<li><strong>LL TIM</strong> driver
<ul>
@@ -799,11 +1021,11 @@
<div class="collapse">
<input type="checkbox" id="collapse-section22" aria-hidden="true"> <label for="collapse-section22" aria-hidden="true">V1.10.0 / 03-April-2019</label>
<div>
-<h2 id="main-changes-4">Main Changes</h2>
+<h2 id="main-changes-6">Main Changes</h2>
<ul>
<li>Delivery of the new HAL MMC driver</li>
</ul>
-<h2 id="contents-4">Contents</h2>
+<h2 id="contents-6">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<ul>
<li><strong>HAL ADC</strong> driver
@@ -945,7 +1167,7 @@
<ul>
<li>Correct MISRA C:2012 Rule-2.4 warning in structure __QSPI_HandleTypeDef definition</li>
<li>Remove the compilation switches related to QUADSPI1 and QUADSPI2 as all STM32 families have only one instance called QUADSPI</li>
-<li>Fix HAL_QSPI_TIMEOUT_DEFAULT_VALUE mispelling</li>
+<li>Fix HAL_QSPI_TIMEOUT_DEFAULT_VALUE misspelling</li>
</ul></li>
<li><strong>HAL RCC</strong> driver
<ul>
@@ -1091,13 +1313,13 @@
<div class="collapse">
<input type="checkbox" id="collapse-section21" aria-hidden="true"> <label for="collapse-section21" aria-hidden="true">V1.9.0 / 27-July-2018</label>
<div>
-<h2 id="main-changes-5">Main Changes</h2>
+<h2 id="main-changes-7">Main Changes</h2>
<ul>
<li>Release of <strong>HAL and Low Layer drivers</strong> to add support of <strong>STM32L412xx/STM32L422xx</strong></li>
<li>Superset features device STM32L422xx API User Manual available (STM32L422xx_User_Manual.chm) </li>
<li>MISRA C:2012 corrections</li>
</ul>
-<h2 id="contents-5">Contents</h2>
+<h2 id="contents-7">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<p>MISRA C:2012 corrections listed hereafter are applicable to LL driver as well.</p>
<ul>
@@ -1283,7 +1505,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section19" aria-hidden="true"> <label for="collapse-section19" aria-hidden="true">V1.8.3 / 22-May-2018</label>
<div>
-<h2 id="main-changes-6">Main Changes</h2>
+<h2 id="main-changes-8">Main Changes</h2>
<p>Maintenance Release of <strong>HAL and Low Layer drivers</strong></p>
<p><strong>Add support of HAL callback registration feature</strong></p>
<ul>
@@ -1293,7 +1515,7 @@
<li><p>Once enabled, the user application may resort to HAL_PPP_RegisterCallback() to register specific callback function(s) and unregister it(them) with HAL_PPP_UnRegisterCallback().</p></li>
</ul>
<p>MISRA C:2012 corrections</p>
-<h2 id="contents-6">Contents</h2>
+<h2 id="contents-8">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<ul>
<li><p><strong>HAL generic</strong> driver</p>
@@ -1641,11 +1863,11 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.8.2 / 22-December-2017</label>
<div>
-<h2 id="main-changes-7">Main Changes</h2>
+<h2 id="main-changes-9">Main Changes</h2>
<ul>
<li>Maintenance Release of <strong>HAL and Low Layer drivers</strong></li>
</ul>
-<h2 id="contents-7">Contents</h2>
+<h2 id="contents-9">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<ul>
<li><strong>HAL CAN</strong> driver</li>
@@ -1723,11 +1945,11 @@
<div class="collapse">
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">V1.8.1 / 13-October-2017</label>
<div>
-<h2 id="main-changes-8">Main Changes</h2>
+<h2 id="main-changes-10">Main Changes</h2>
<ul>
<li>Maintenance Release of <strong>HAL and Low Layer drivers</strong></li>
</ul>
-<h2 id="contents-8">Contents</h2>
+<h2 id="contents-10">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<ul>
<li><p><strong>HAL generic</strong> driver</p>
@@ -1805,7 +2027,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">V1.8.0 / 25-August-2017</label>
<div>
-<h2 id="main-changes-9">Main Changes</h2>
+<h2 id="main-changes-11">Main Changes</h2>
<ul>
<li><p>Release of <strong>HAL and Low Layer drivers</strong> to add support of <strong>STM32L4R5xx/STM32L4R7xx/STM32L4R9xx/STM32L4S5xx/STM32L4S7xx/STM32L4S9xx</strong> devices</p></li>
<li><p>New OctoSPI, DSI, LTDC, GFXMMU peripherals supported in <strong>new HAL OSPI, HAL DSI, HAL LTDC</strong> and <strong>HAL GFXMMU</strong> drivers</p></li>
@@ -1929,11 +2151,11 @@
<li><p><strong>HAL SMBUS</strong> driver</p>
<ul>
<li>Add Analog and digital filter configuration APIs: HAL_SMBUS_ConfigAnalogFilter() and HAL_SMBUS_ConfigDigitalFilter() </li>
-<li>Add error management if occuring during STOP process</li>
+<li>Add error management if occurring during STOP process</li>
</ul></li>
<li><p><strong>HAL SPI</strong> driver</p>
<ul>
-<li>Add control of RXFIFO emty at end of transmissing in Master transmission 2 lines mode</li>
+<li>Add control of RXFIFO empty at end of transmissing in Master transmission 2 lines mode</li>
</ul></li>
<li><p><strong>HAL SWPMI</strong> driver</p>
<ul>
@@ -2005,7 +2227,7 @@
<li><p>LL_PWR_EnableSRAM3Retention(), LL_PWR_DisableSRAM3Retention() and LL_PWR_IsEnabledSRAM3Retention()</p></li>
<li><p>Add voltage range 1 boost mode APIs</p></li>
<li><p>LL_PWR_EnableRange1BoostMode(), LL_PWR_DisableRange1BoostMode() and LL_PWR_IsEnabledRange1BoostMode()</p></li>
-<li><p>For compatibility purpose accross STM32 series, rename LL_PWR_IsActiveFlag_VOSF() to LL_PWR_IsActiveFlag_VOS()</p></li>
+<li><p>For compatibility purpose across STM32 series, rename LL_PWR_IsActiveFlag_VOSF() to LL_PWR_IsActiveFlag_VOS()</p></li>
<li><p>Add DSI pins pull-down management</p></li>
<li><p>new LL_PWR_EnableDSIPinsPDActivation(), LL_PWR_DisableDSIPinsPDActivation() and LL_PWR_IsEnabledDSIPinsPDActivation APIs</p></li>
</ul></li>
@@ -2062,11 +2284,11 @@
<div class="collapse">
<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">V1.7.2 / 16-June-2017</label>
<div>
-<h2 id="main-changes-10">Main Changes</h2>
+<h2 id="main-changes-12">Main Changes</h2>
<ul>
<li>Maintenance Release of <strong>HAL and Low Layer drivers</strong></li>
</ul>
-<h2 id="contents-9">Contents</h2>
+<h2 id="contents-11">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<ul>
<li><p><strong>HAL CAN</strong> driver</p>
@@ -2118,11 +2340,11 @@
<div class="collapse">
<input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true">V1.7.1 / 21-April-2017</label>
<div>
-<h2 id="main-changes-11">Main Changes</h2>
+<h2 id="main-changes-13">Main Changes</h2>
<ul>
<li>Maintenance Release of <strong>HAL and Low Layer drivers</strong></li>
</ul>
-<h2 id="contents-10">Contents</h2>
+<h2 id="contents-12">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<ul>
<li><p><strong>HAL generic</strong> driver</p>
@@ -2162,7 +2384,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true">V1.7.0 / 17-February-2017</label>
<div>
-<h2 id="main-changes-12">Main Changes</h2>
+<h2 id="main-changes-14">Main Changes</h2>
<ul>
<li>Release of <strong>HAL and Low Layer drivers</strong> to add support of <strong>STM32L496xx/STM32L4A6xx</strong> devices</li>
<li>New DCMI, DMA2D, HASH peripherals supported in <strong>new HAL DCMI, HAL & LL DMA2D and HAL HASH</strong> drivers</li>
@@ -2171,7 +2393,7 @@
<li>Superset features device STM32L4A6xx API User Manual available (STM32L4A6xx_User_Manual.chm) <br />
</li>
</ul>
-<h2 id="contents-11">Contents</h2>
+<h2 id="contents-13">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<ul>
<li><strong>HAL DCMI</strong> driver <strong>(NEW)</strong>: stm32l4xx_hal_dcmi.h/.c files</li>
@@ -2251,7 +2473,7 @@
</ul></li>
<li><p><strong>LL PWR</strong></p>
<ul>
-<li>For compatibility purpose accross STM32 series, rename LL_PWR_IsActiveFlag_VOSF() to LL_PWR_IsActiveFlag_VOS()</li>
+<li>For compatibility purpose across STM32 series, rename LL_PWR_IsActiveFlag_VOSF() to LL_PWR_IsActiveFlag_VOS()</li>
</ul></li>
<li><p><strong>LL RCC</strong></p>
<ul>
@@ -2271,12 +2493,12 @@
<div class="collapse">
<input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true">V1.6.0 / 28-October-2016</label>
<div>
-<h2 id="main-changes-13">Main Changes</h2>
+<h2 id="main-changes-15">Main Changes</h2>
<ul>
<li>Release of <strong>HAL and Low Layer drivers</strong> to add support of <strong>STM32L451xx/STM32L452xx/STM32L462xx</strong> devices</li>
<li>Superset features device STM32L462xx API User Manual available (STM32L462xx_User_Manual.chm)</li>
</ul>
-<h2 id="contents-12">Contents</h2>
+<h2 id="contents-14">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<ul>
<li><p><strong>HAL CRYP</strong> driver</p>
@@ -2336,7 +2558,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true">V1.5.2 / 12-September-2016</label>
<div>
-<h2 id="contents-13">Contents</h2>
+<h2 id="contents-15">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<ul>
<li><p><strong>HAL ADC</strong> driver</p>
@@ -2403,14 +2625,14 @@
</ul></li>
<li><p><strong>HAL UART</strong> driver</p>
<ul>
-<li>New APIs to abort UART tranfer with associated callbacks added
+<li>New APIs to abort UART transfer with associated callbacks added
<ul>
<li>HAL_UART_Abort(), HAL_UART_AbortTransmit(), HAL_UART_AbortReceive(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit_IT(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortCpltCallback(), HAL_UART_AbortTransmitCpltCallback() and HAL_UART_AbortReceiveCpltCallback()</li>
</ul></li>
</ul></li>
<li><p><strong>HAL USART</strong> driver</p>
<ul>
-<li><p>New APIs to abort USART tranfer with associated callbacks added</p>
+<li><p>New APIs to abort USART transfer with associated callbacks added</p>
<ul>
<li>HAL_USART_Abort(), HAL_USART_Abort_IT() and HAL_USART_AbortCpltCallback()</li>
</ul></li>
@@ -2428,7 +2650,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true">V1.5.1 / 31-May-2016</label>
<div>
-<h2 id="contents-14">Contents</h2>
+<h2 id="contents-16">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<ul>
<li><p><strong>HAL ADC</strong> driver</p>
@@ -2456,11 +2678,11 @@
<div class="collapse">
<input type="checkbox" id="collapse-section13" aria-hidden="true"> <label for="collapse-section13" aria-hidden="true">V1.5.0 / 29-April-2016</label>
<div>
-<h2 id="main-changes-14">Main Changes</h2>
+<h2 id="main-changes-16">Main Changes</h2>
<ul>
<li>Maintenance Release of <strong>HAL and Low Layer drivers</strong></li>
</ul>
-<h2 id="contents-15">Contents</h2>
+<h2 id="contents-17">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<p>Enhance HAL delay and timebase implementation</p>
<ul>
@@ -2706,7 +2928,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section14" aria-hidden="true"> <label for="collapse-section14" aria-hidden="true">V1.4.0 / 26-February-2016</label>
<div>
-<h2 id="main-changes-15">Main Changes</h2>
+<h2 id="main-changes-17">Main Changes</h2>
<ul>
<li>Release of <strong>HAL and Low Layer drivers</strong> to add support of <strong>STM32L431xx/STM32L432xx/STM32L433xx/STM32L442xx/STM32L443xx</strong> devices</li>
<li><strong>Low Layer driver initialization/de-initialization APIs</strong> applicable to all STM32L4xx devices</li>
@@ -2714,7 +2936,7 @@
<li>Superset features device STM32L443xx API User Manual available (STM32L443xx_User_Manual.chm) <br />
</li>
</ul>
-<h2 id="contents-16">Contents</h2>
+<h2 id="contents-18">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<ul>
<li><p><strong>HAL</strong> generic update</p>
@@ -2778,7 +3000,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section15" aria-hidden="true"> <label for="collapse-section15" aria-hidden="true">V1.3.0 / 29-January-2016</label>
<div>
-<h2 id="main-changes-16">Main Changes</h2>
+<h2 id="main-changes-18">Main Changes</h2>
<ul>
<li><strong>New Low Layer driver initialization/de-initialization APIs</strong>
<ul>
@@ -2791,7 +3013,7 @@
</ul></li>
<li>Fix "parameter unused" GCC compilation warnings on __weak functions</li>
</ul>
-<h2 id="contents-17">Contents</h2>
+<h2 id="contents-19">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<ul>
<li><p><strong>HAL generic</strong> update</p>
@@ -2939,7 +3161,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section16" aria-hidden="true"> <label for="collapse-section16" aria-hidden="true">V1.2.0 / 25-November-2015</label>
<div>
-<h2 id="main-changes-17">Main Changes</h2>
+<h2 id="main-changes-19">Main Changes</h2>
<ul>
<li><strong>HAL generic</strong> update
<ul>
@@ -2960,7 +3182,7 @@
<li><strong>HAL SAI</strong> update
<ul>
<li><p>update SAI block synchronization selection (User application code impacted)</p></li>
-<li><p>Replace uncomplete SAI_SYNCHRONOUS_EXT value for with SAI_SYNCHRONOUS_EXT_SAI1 and SAI_SYNCHRONOUS_EXT_SAI2</p></li>
+<li><p>Replace incomplete SAI_SYNCHRONOUS_EXT value for with SAI_SYNCHRONOUS_EXT_SAI1 and SAI_SYNCHRONOUS_EXT_SAI2</p></li>
<li><p>Update external synchronization input selection (User application code impacted)</p></li>
<li><p>Remove useless SAI_SYNCEXT_IN_ENABLE value for SynchroExt field in SAI_InitTypeDef structure</p></li>
<li><p>Add support of 24bits configuration in PCM protocol</p></li>
@@ -2996,7 +3218,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section17" aria-hidden="true"> <label for="collapse-section17" aria-hidden="true">V1.1.1 / 16-October-2015</label>
<div>
-<h2 id="main-changes-18">Main Changes</h2>
+<h2 id="main-changes-20">Main Changes</h2>
<ul>
<li><p><strong>HAL generic</strong> update</p>
<ul>
@@ -3026,15 +3248,15 @@
<div class="collapse">
<input type="checkbox" id="collapse-section20" aria-hidden="true"> <label for="collapse-section20" aria-hidden="true">V1.1.0 / 26-September-2015</label>
<div>
-<h2 id="main-changes-19">Main Changes</h2>
+<h2 id="main-changes-21">Main Changes</h2>
<p><strong>Add Low Layer drivers allowing performance and footprint optimization</strong></p>
<ul>
<li>Low Layer drivers APIs provide register level programming: they require deep knowledge of peripherals described in STM32L4x6 Reference Manual</li>
-<li><p>Low Layer drivers are available for: ADC, COMP, Cortex, CRC, DAC, DMA, EXTI, GPIO, I2C, IWDG, LPYIM, LPUART, OPAMP, PWR, RCC, RNG, RTC, SPI, SWPMI, TIM, USART, WWDG peripherals and additionnal Low Level Bus, System and Utilities APIs.<br />
+<li><p>Low Layer drivers are available for: ADC, COMP, Cortex, CRC, DAC, DMA, EXTI, GPIO, I2C, IWDG, LPYIM, LPUART, OPAMP, PWR, RCC, RNG, RTC, SPI, SWPMI, TIM, USART, WWDG peripherals and additional Low Level Bus, System and Utilities APIs.<br />
</p></li>
<li><p>Low Layer drivers APIs are implemented as static inline function in new Inc/stm32l4xx_ll_ppp.h files for PPP peripherals, there is no configuration file and each stm32l4xx_ll_ppp.h file must be included in user code.</p></li>
</ul>
-<h2 id="contents-18">Contents</h2>
+<h2 id="contents-20">Contents</h2>
<ul>
<li><p><strong>HAL ADC</strong> update</p>
<ul>
@@ -3099,7 +3321,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section18" aria-hidden="true"> <label for="collapse-section18" aria-hidden="true">V1.0.0 / 26-June-2015</label>
<div>
-<h2 id="main-changes-20">Main Changes</h2>
+<h2 id="main-changes-22">Main Changes</h2>
<ul>
<li>First official release of <strong>STM32L4xx HAL Drivers</strong> for <strong>STM32L471xx/STM32L475xx/STM32L476xx/STM32L485xx</strong> and <strong>STM32L486xx</strong> devices</li>
</ul>
diff --git a/Src/Legacy/stm32l4xx_hal_can.c b/Src/Legacy/stm32l4xx_hal_can.c
index 8797ec0..07a8226 100644
--- a/Src/Legacy/stm32l4xx_hal_can.c
+++ b/Src/Legacy/stm32l4xx_hal_can.c
@@ -10,6 +10,17 @@
* + Peripheral Control functions
* + Peripheral State and Error functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### User NOTE #####
@@ -76,17 +87,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
diff --git a/Src/stm32l4xx_hal.c b/Src/stm32l4xx_hal.c
index be40072..9b5cb1d 100644
--- a/Src/stm32l4xx_hal.c
+++ b/Src/stm32l4xx_hal.c
@@ -5,6 +5,17 @@
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -19,17 +30,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -53,7 +53,7 @@
*/
#define STM32L4XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define STM32L4XX_HAL_VERSION_SUB1 (0x0DU) /*!< [23:16] sub1 version */
-#define STM32L4XX_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
+#define STM32L4XX_HAL_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define STM32L4XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define STM32L4XX_HAL_VERSION ((STM32L4XX_HAL_VERSION_MAIN << 24U)\
|(STM32L4XX_HAL_VERSION_SUB1 << 16U)\
@@ -762,5 +762,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_adc.c b/Src/stm32l4xx_hal_adc.c
index a86b3e9..2d7b906 100644
--- a/Src/stm32l4xx_hal_adc.c
+++ b/Src/stm32l4xx_hal_adc.c
@@ -6,19 +6,22 @@
* functionalities of the Analog to Digital Converter (ADC)
* peripheral:
* + Initialization and de-initialization functions
- * ++ Initialization and Configuration of ADC
- * + Operation functions
- * ++ Start, stop, get result of conversions of regular
- * group, using 3 possible modes: polling, interruption or DMA.
- * + Control functions
- * ++ Channels configuration on regular group
- * ++ Analog Watchdog configuration
- * + State functions
- * ++ ADC state machine management
- * ++ Interrupts and flags management
+ * + Peripheral Control functions
+ * + Peripheral State functions
* Other functions (extended functions) are available in file
* "stm32l4xx_hal_adc_ex.c".
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### ADC peripheral features #####
@@ -217,11 +220,11 @@
The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_ADC_RegisterCallback()
+ Use Functions HAL_ADC_RegisterCallback()
to register an interrupt callback.
[..]
- Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
+ Function HAL_ADC_RegisterCallback() allows to register following callbacks:
(+) ConvCpltCallback : ADC conversion complete callback
(+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
(+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
@@ -237,11 +240,11 @@
and a pointer to the user callback function.
[..]
- Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
+ Use function HAL_ADC_UnRegisterCallback to reset a callback to the default
weak function.
[..]
- @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) ConvCpltCallback : ADC conversion complete callback
@@ -257,27 +260,27 @@
(+) MspDeInitCallback : ADC Msp DeInit callback
[..]
- By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
+ By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET
all callbacks are set to the corresponding weak functions:
- examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
+ examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
+ reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when
these callbacks are null (not registered beforehand).
[..]
- If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
+ If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
- Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
+ Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
- in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
+ in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
[..]
Then, the user first registers the MspInit/MspDeInit user callbacks
- using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
- or @ref HAL_ADC_Init() function.
+ using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit()
+ or HAL_ADC_Init() function.
[..]
When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
@@ -286,17 +289,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -2009,11 +2001,12 @@
#if defined(ADC_MULTIMODE_SUPPORT)
/* Ensure that multimode regular conversions are not enabled. */
/* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */
- if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ if ((ADC_IS_INDEPENDENT(hadc) != RESET)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
)
-#endif
+#endif /* ADC_MULTIMODE_SUPPORT */
{
/* Enable the ADC peripheral */
tmp_hal_status = ADC_Enable(hadc);
@@ -3651,5 +3644,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_adc_ex.c b/Src/stm32l4xx_hal_adc_ex.c
index 14f979f..a0714a7 100644
--- a/Src/stm32l4xx_hal_adc_ex.c
+++ b/Src/stm32l4xx_hal_adc_ex.c
@@ -5,20 +5,21 @@
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Converter (ADC)
* peripheral:
- * + Operation functions
- * ++ Start, stop, get result of conversions of ADC group injected,
- * using 2 possible modes: polling, interruption.
- * ++ Calibration
- * +++ ADC automatic self-calibration
- * +++ Calibration factors get or set
- * ++ Multimode feature when available
- * + Control functions
- * ++ Channels configuration on ADC group injected
- * + State functions
- * ++ ADC group injected contexts queue management
+ * + Peripheral Control functions
* Other functions (generic functions) are available in file
* "stm32l4xx_hal_adc.c".
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
[..]
(@) Sections "ADC peripheral features" and "How to use this driver" are
@@ -26,17 +27,6 @@
[..]
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -2372,5 +2362,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_can.c b/Src/stm32l4xx_hal_can.c
index e1679fc..ee2cbb4 100644
--- a/Src/stm32l4xx_hal_can.c
+++ b/Src/stm32l4xx_hal_can.c
@@ -12,6 +12,17 @@
* + Callbacks functions
* + Peripheral State and Error functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -120,7 +131,7 @@
submitted (the sleep mode is not yet entered), and become
HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective.
- (#) The wake-up from sleep mode can be trigged by two ways:
+ (#) The wake-up from sleep mode can be triggered by two ways:
(++) Using HAL_CAN_WakeUp(). When returning from this function,
the sleep mode is exited (if return status is HAL_OK).
(++) When a start of Rx CAN frame is detected by the CAN peripheral,
@@ -131,9 +142,9 @@
The compilation define USE_HAL_CAN_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Function @ref HAL_CAN_RegisterCallback() to register an interrupt callback.
+ Use Function HAL_CAN_RegisterCallback() to register an interrupt callback.
- Function @ref HAL_CAN_RegisterCallback() allows to register following callbacks:
+ Function HAL_CAN_RegisterCallback() allows to register following callbacks:
(+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback.
(+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback.
(+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback.
@@ -152,9 +163,9 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- Use function @ref HAL_CAN_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_CAN_UnRegisterCallback() to reset a callback to the default
weak function.
- @ref HAL_CAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ HAL_CAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback.
@@ -173,13 +184,13 @@
(+) MspInitCallback : CAN MspInit.
(+) MspDeInitCallback : CAN MspDeInit.
- By default, after the @ref HAL_CAN_Init() and when the state is HAL_CAN_STATE_RESET,
+ By default, after the HAL_CAN_Init() and when the state is HAL_CAN_STATE_RESET,
all callbacks are set to the corresponding weak functions:
- example @ref HAL_CAN_ErrorCallback().
+ example HAL_CAN_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak function in the @ref HAL_CAN_Init()/ @ref HAL_CAN_DeInit() only when
+ reset to the legacy weak function in the HAL_CAN_Init()/ HAL_CAN_DeInit() only when
these callbacks are null (not registered beforehand).
- if not, MspInit or MspDeInit are not null, the @ref HAL_CAN_Init()/ @ref HAL_CAN_DeInit()
+ if not, MspInit or MspDeInit are not null, the HAL_CAN_Init()/ HAL_CAN_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in HAL_CAN_STATE_READY state only.
@@ -187,8 +198,8 @@
in HAL_CAN_STATE_READY or HAL_CAN_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_CAN_RegisterCallback() before calling @ref HAL_CAN_DeInit()
- or @ref HAL_CAN_Init() function.
+ using HAL_CAN_RegisterCallback() before calling HAL_CAN_DeInit()
+ or HAL_CAN_Init() function.
When The compilation define USE_HAL_CAN_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
@@ -196,17 +207,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -330,14 +330,14 @@
}
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
- /* Exit from sleep mode */
- CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+ /* Request initialisation */
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
/* Get tick */
tickstart = HAL_GetTick();
- /* Check Sleep mode leave acknowledge */
- while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
+ /* Wait initialisation acknowledge */
+ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
{
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
{
@@ -351,14 +351,14 @@
}
}
- /* Request initialisation */
- SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
+ /* Exit from sleep mode */
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
/* Get tick */
tickstart = HAL_GetTick();
- /* Wait initialisation acknowledge */
- while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
+ /* Check Sleep mode leave acknowledge */
+ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
{
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
{
@@ -1873,7 +1873,7 @@
/* Check if message is still pending */
if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U)
{
- /* Receive FIFO 0 mesage pending Callback */
+ /* Receive FIFO 0 message pending Callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo0MsgPendingCallback(hcan);
@@ -1922,7 +1922,7 @@
/* Check if message is still pending */
if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U)
{
- /* Receive FIFO 1 mesage pending Callback */
+ /* Receive FIFO 1 message pending Callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo1MsgPendingCallback(hcan);
@@ -2432,5 +2432,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_comp.c b/Src/stm32l4xx_hal_comp.c
index bfb7dae..c5d1096 100644
--- a/Src/stm32l4xx_hal_comp.c
+++ b/Src/stm32l4xx_hal_comp.c
@@ -6,11 +6,20 @@
* This file provides firmware functions to manage the following
* functionalities of the COMP peripheral:
* + Initialization and de-initialization functions
- * + Start/Stop operation functions in polling mode
- * + Start/Stop operation functions in interrupt mode (through EXTI interrupt)
* + Peripheral control functions
* + Peripheral state functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
================================================================================
##### COMP Peripheral features #####
@@ -177,18 +186,6 @@
(3) Only STM32L43x/L44x
(4) Not applicable to STM32L412x/L422x
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -359,7 +356,7 @@
COMP_CSR_BLANKING | COMP_CSR_BRGEN | COMP_CSR_SCALEN | COMP_CSR_INMESEL,
tmp_csr
);
-#endif
+#endif /* COMP_CSR_WINMODE */
#else
MODIFY_REG(hcomp->Instance->CSR,
COMP_CSR_PWRMODE | COMP_CSR_INMSEL | COMP_CSR_INPSEL |
@@ -367,7 +364,7 @@
COMP_CSR_BLANKING | COMP_CSR_BRGEN | COMP_CSR_SCALEN,
tmp_csr
);
-#endif
+#endif /* COMP_CSR_INMESEL */
#if defined(COMP2)
/* Set window mode */
@@ -1048,5 +1045,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_cortex.c b/Src/stm32l4xx_hal_cortex.c
index 149d4ba..f95efa9 100644
--- a/Src/stm32l4xx_hal_cortex.c
+++ b/Src/stm32l4xx_hal_cortex.c
@@ -90,13 +90,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -516,4 +515,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_crc.c b/Src/stm32l4xx_hal_crc.c
index b530e46..8e14df5 100644
--- a/Src/stm32l4xx_hal_crc.c
+++ b/Src/stm32l4xx_hal_crc.c
@@ -9,6 +9,17 @@
* + Peripheral Control functions
* + Peripheral State functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
@@ -29,17 +40,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -62,8 +62,8 @@
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup CRC_Private_Functions CRC Private Functions
- * @{
- */
+ * @{
+ */
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
/**
@@ -77,8 +77,8 @@
*/
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions.
- *
+ * @brief Initialization and Configuration functions.
+ *
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
@@ -250,8 +250,8 @@
*/
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
- * @brief management functions.
- *
+ * @brief management functions.
+ *
@verbatim
===============================================================================
##### Peripheral Control functions #####
@@ -385,8 +385,8 @@
*/
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
- * @brief Peripheral State functions.
- *
+ * @brief Peripheral State functions.
+ *
@verbatim
===============================================================================
##### Peripheral State functions #####
@@ -418,8 +418,8 @@
*/
/** @addtogroup CRC_Private_Functions
- * @{
- */
+ * @{
+ */
/**
* @brief Enter 8-bit input data to the CRC calculator.
@@ -514,5 +514,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_crc_ex.c b/Src/stm32l4xx_hal_crc_ex.c
index cc8ee03..6f66833 100644
--- a/Src/stm32l4xx_hal_crc_ex.c
+++ b/Src/stm32l4xx_hal_crc_ex.c
@@ -6,27 +6,27 @@
* This file provides firmware functions to manage the extended
* functionalities of the CRC peripheral.
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
================================================================================
##### How to use this driver #####
================================================================================
[..]
- (+) Set user-defined generating polynomial thru HAL_CRCEx_Polynomial_Set()
+ (+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set()
(+) Configure Input or Output data inversion
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -221,5 +221,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_cryp.c b/Src/stm32l4xx_hal_cryp.c
index 708271b..49de5c7 100644
--- a/Src/stm32l4xx_hal_cryp.c
+++ b/Src/stm32l4xx_hal_cryp.c
@@ -11,6 +11,16 @@
* + Processing functions using DMA mode
* + Peripheral State functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -107,17 +117,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -1733,5 +1732,3 @@
#endif /* AES */
#endif /* HAL_CRYP_MODULE_ENABLED */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_cryp_ex.c b/Src/stm32l4xx_hal_cryp_ex.c
index daf6ba3..abe65c8 100644
--- a/Src/stm32l4xx_hal_cryp_ex.c
+++ b/Src/stm32l4xx_hal_cryp_ex.c
@@ -9,14 +9,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -344,7 +342,7 @@
* @note No DMA channel is provided for key derivation only and therefore, access to AES_KEYRx
* registers must be done by software.
* @note This API is not applicable to key derivation only; for such a mode, access to AES_KEYRx
- * registers must be done by software thru HAL_CRYPEx_AES() or HAL_CRYPEx_AES_IT() APIs.
+ * registers must be done by software through HAL_CRYPEx_AES() or HAL_CRYPEx_AES_IT() APIs.
* @note pInputData and pOutputData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
* @retval HAL status
*/
@@ -2460,7 +2458,7 @@
intermediate_data[((difflength+3U)/4U)+index] = 0;
}
- /* Insert intermediate data to trigger an additional DOUTR reading round */
+ /* Insert intermediate data to trigger an additional Data Output register reading round */
/* Clear Computation Complete Flag before entering new block */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
for(index=0U ; index < 4U; index ++)
@@ -2515,7 +2513,7 @@
#if !defined(AES_CR_NPBLB)
else
{
- /* Software work-around: additional DOUTR reading round to discard the data */
+ /* Software work-around: additional Data Output Register reading round to discard the data */
for(index=0U ; index < 4U; index ++)
{
intermediate_data[index] = hcryp->Instance->DOUTR;
@@ -3208,7 +3206,7 @@
hcryp->Instance->DINR = intermediate_data[index];
}
- /* Wait for completion, and read data on DOUT. This data is to discard. */
+ /* Wait for completion, and read data on Data Output Register. This data is to discard. */
if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
{
hcryp->State = HAL_CRYP_STATE_READY;
@@ -3245,4 +3243,3 @@
#endif /* AES */
#endif /* HAL_CRYP_MODULE_ENABLED */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_dac.c b/Src/stm32l4xx_hal_dac.c
index 889aaab..814ef66 100644
--- a/Src/stm32l4xx_hal_dac.c
+++ b/Src/stm32l4xx_hal_dac.c
@@ -6,11 +6,21 @@
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:
* + Initialization and de-initialization functions
- * + IO operation functions
* + Peripheral Control functions
* + Peripheral State and Errors functions
*
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### DAC Peripheral features #####
@@ -238,7 +248,7 @@
The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback,
+ Use Functions HAL_DAC_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
(+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
@@ -253,7 +263,7 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
(+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
@@ -268,12 +278,12 @@
(+) All Callbacks
This function) takes as parameters the HAL peripheral handle and the Callback ID.
- By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
+ By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init
- and @ref HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit
+ reset to the legacy weak (surcharged) functions in the HAL_DAC_Init
+ and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
@@ -281,8 +291,8 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit
- or @ref HAL_DAC_Init function.
+ using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit
+ or HAL_DAC_Init function.
When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
@@ -303,17 +313,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -1551,7 +1550,7 @@
* @param hdac DAC handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
- * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 tranfer Complete Callback ID
+ * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 transfer Complete Callback ID
* @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
* @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
* @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
@@ -1759,4 +1758,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_dac_ex.c b/Src/stm32l4xx_hal_dac_ex.c
index 155ed34..994811f 100644
--- a/Src/stm32l4xx_hal_dac_ex.c
+++ b/Src/stm32l4xx_hal_dac_ex.c
@@ -7,6 +7,17 @@
* functionalities of the DAC peripheral.
*
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -32,17 +43,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
@@ -656,4 +656,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_dcmi.c b/Src/stm32l4xx_hal_dcmi.c
index 20664b0..58995e7 100644
--- a/Src/stm32l4xx_hal_dcmi.c
+++ b/Src/stm32l4xx_hal_dcmi.c
@@ -10,6 +10,17 @@
* + Peripheral Control functions
* + Peripheral State and Error functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -54,7 +65,7 @@
(++) during capture, the driver copies the image data samples from DCMI DR register
at the end of the final destination buffer used as a work buffer,
(++) at each DMA half (respectively complete) transfer interrupt, the first
- (resp. second) half of the work buffer is copied to the final destination thru
+ (resp. second) half of the work buffer is copied to the final destination through
a second DMA channel.
(++) Parameters of this second DMA channel are contained in the memory to memory DMA
handle "DMAM2M_Handle", itself field of the DCMI handle structure.
@@ -145,17 +156,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -453,10 +453,10 @@
* the API uses the end of the destination buffer as a work area: HAL_DCMI_Start_DMA()
* initiates a circular DMA transfer from DCMI DR to the ad-hoc work buffer and each
* half and complete transfer interrupt triggers a copy from the work buffer to
- * the final destination pData thru a second DMA channel.
+ * the final destination pData through a second DMA channel.
* @note Following HAL_DCMI_Init() call, all interruptions are enabled (line end,
* frame end, overrun, VSYNC and embedded synchronization error interrupts).
- * User can disable unwanted interrupts thru __HAL_DCMI_DISABLE_IT() macro
+ * User can disable unwanted interrupts through __HAL_DCMI_DISABLE_IT() macro
* before invoking HAL_DCMI_Start_DMA().
* @note For length less than 0xFFFF (DMA maximum transfer length) and in snapshot mode,
* frame interrupt is disabled before DMA transfer. FRAME capture flag is checked
@@ -1449,7 +1449,7 @@
/**
* @brief Sub-buffers transfer size computation.
* @note In the case of a frame size larger than the maximum DMA transfer length (0xFFFF),
- * the tranfer from DCMI DR register to the final output buffer is carried out by a sequence
+ * the transfer from DCMI DR register to the final output buffer is carried out by a sequence
* of intermediate sub-copies to temporary buffers of size less than 0xFFFF.
* To optimize the number of DMA transfers, the API computes the temporary buffer
* size so that the latter is an even number less than 0xFFFF, that divides the final
@@ -1465,7 +1465,7 @@
uint32_t temp = InputSize;
uint32_t aPrime[NPRIME] = {0};
uint32_t output = 2; /* Want a result which is an even number */
- uint32_t PrimeArray[NPRIME] = { 1UL, 2UL, 3UL, 5UL,
+ static const uint32_t PrimeArray[NPRIME] = { 1UL, 2UL, 3UL, 5UL,
7UL, 11UL, 13UL, 17UL,
19UL, 23UL, 29UL, 31UL,
37UL, 41UL, 43UL, 47UL};
@@ -1488,7 +1488,7 @@
}
/* Search for the biggest even divisor less or equal to 0xFFFE = 65534 */
- aPrime[1] -= 1U; /* output is initialized to 2, so don't count dividor 2 twice */
+ aPrime[1] -= 1U; /* output is initialized to 2, so don't count divider 2 twice */
/* The algorithm below yields a sub-optimal solution
but in an acceptable time. */
@@ -1530,5 +1530,3 @@
#endif /* DCMI */
#endif /* HAL_DCMI_MODULE_ENABLED */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_dfsdm.c b/Src/stm32l4xx_hal_dfsdm.c
index cf826b0..9963140 100644
--- a/Src/stm32l4xx_hal_dfsdm.c
+++ b/Src/stm32l4xx_hal_dfsdm.c
@@ -16,6 +16,17 @@
* + Clock absence detector feature
* + Break generation on analog watchdog or short-circuit event
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -251,17 +262,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -3574,5 +3574,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_dfsdm_ex.c b/Src/stm32l4xx_hal_dfsdm_ex.c
index e4c3598..42ddd98 100644
--- a/Src/stm32l4xx_hal_dfsdm_ex.c
+++ b/Src/stm32l4xx_hal_dfsdm_ex.c
@@ -10,13 +10,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -132,5 +131,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_dma.c b/Src/stm32l4xx_hal_dma.c
index 24856b9..c0f1fab 100644
--- a/Src/stm32l4xx_hal_dma.c
+++ b/Src/stm32l4xx_hal_dma.c
@@ -8,6 +8,18 @@
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral State and errors functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -73,17 +85,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -892,7 +893,7 @@
* @brief Register callbacks
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
- * @param CallbackID User Callback identifer
+ * @param CallbackID User Callback identifier
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @param pCallback pointer to private callbacsk function which has pointer to
* a DMA_HandleTypeDef structure as parameter.
@@ -945,7 +946,7 @@
* @brief UnRegister callbacks
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
- * @param CallbackID User Callback identifer
+ * @param CallbackID User Callback identifier
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @retval HAL status
*/
@@ -1171,5 +1172,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_dma2d.c b/Src/stm32l4xx_hal_dma2d.c
index 640a855..1f601e3 100644
--- a/Src/stm32l4xx_hal_dma2d.c
+++ b/Src/stm32l4xx_hal_dma2d.c
@@ -10,6 +10,17 @@
* + Peripheral Control functions
* + Peripheral State and Errors functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -147,17 +158,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -201,7 +201,8 @@
/** @addtogroup DMA2D_Private_Functions DMA2D Private Functions
* @{
*/
-static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
+static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+ uint32_t Height);
/**
* @}
*/
@@ -213,8 +214,8 @@
*/
/** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
@@ -237,9 +238,9 @@
HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
{
/* Check the DMA2D peripheral state */
- if(hdma2d == NULL)
+ if (hdma2d == NULL)
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
/* Check the parameters */
@@ -262,7 +263,7 @@
/* Reset Callback pointers in HAL_DMA2D_STATE_RESET only */
hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
- if(hdma2d->MspInitCallback == NULL)
+ if (hdma2d->MspInitCallback == NULL)
{
hdma2d->MspInitCallback = HAL_DMA2D_MspInit;
}
@@ -271,7 +272,7 @@
hdma2d->MspInitCallback(hdma2d);
}
#else
- if(hdma2d->State == HAL_DMA2D_STATE_RESET)
+ if (hdma2d->State == HAL_DMA2D_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hdma2d->Lock = HAL_UNLOCKED;
@@ -292,7 +293,8 @@
/* DMA2D OPFCCR register configuration ---------------------------------------*/
#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
- MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM | DMA2D_OPFCCR_SB, hdma2d->Init.ColorMode | hdma2d->Init.BytesSwap);
+ MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM | DMA2D_OPFCCR_SB,
+ hdma2d->Init.ColorMode | hdma2d->Init.BytesSwap);
#else
MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
@@ -300,7 +302,9 @@
/* DMA2D OOR register configuration ------------------------------------------*/
MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
/* DMA2D OPFCCR AI and RBS fields setting (Output Alpha Inversion)*/
- MODIFY_REG(hdma2d->Instance->OPFCCR,(DMA2D_OPFCCR_AI|DMA2D_OPFCCR_RBS), ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos)));
+ MODIFY_REG(hdma2d->Instance->OPFCCR, (DMA2D_OPFCCR_AI | DMA2D_OPFCCR_RBS),
+ ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | \
+ (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos)));
/* Update error code */
@@ -324,9 +328,9 @@
{
/* Check the DMA2D peripheral state */
- if(hdma2d == NULL)
+ if (hdma2d == NULL)
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
/* Before aborting any DMA2D transfer or CLUT loading, check
@@ -379,13 +383,13 @@
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
- if(hdma2d->MspDeInitCallback == NULL)
- {
- hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;
- }
+ if (hdma2d->MspDeInitCallback == NULL)
+ {
+ hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;
+ }
- /* DeInit the low level hardware */
- hdma2d->MspDeInitCallback(hdma2d);
+ /* DeInit the low level hardware */
+ hdma2d->MspDeInitCallback(hdma2d);
#else
/* Carry on with de-initialization of low level hardware */
@@ -410,7 +414,7 @@
* the configuration information for the DMA2D.
* @retval None
*/
-__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
+__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdma2d);
@@ -426,7 +430,7 @@
* the configuration information for the DMA2D.
* @retval None
*/
-__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
+__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdma2d);
@@ -453,11 +457,12 @@
* @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
* @retval status
*/
-HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID,
+ pDMA2D_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
/* Update the error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
@@ -466,68 +471,68 @@
/* Process locked */
__HAL_LOCK(hdma2d);
- if(HAL_DMA2D_STATE_READY == hdma2d->State)
+ if (HAL_DMA2D_STATE_READY == hdma2d->State)
{
switch (CallbackID)
{
- case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
- hdma2d->XferCpltCallback = pCallback;
- break;
+ case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
+ hdma2d->XferCpltCallback = pCallback;
+ break;
- case HAL_DMA2D_TRANSFERERROR_CB_ID :
- hdma2d->XferErrorCallback = pCallback;
- break;
+ case HAL_DMA2D_TRANSFERERROR_CB_ID :
+ hdma2d->XferErrorCallback = pCallback;
+ break;
- case HAL_DMA2D_LINEEVENT_CB_ID :
- hdma2d->LineEventCallback = pCallback;
- break;
+ case HAL_DMA2D_LINEEVENT_CB_ID :
+ hdma2d->LineEventCallback = pCallback;
+ break;
- case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
- hdma2d->CLUTLoadingCpltCallback = pCallback;
- break;
+ case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
+ hdma2d->CLUTLoadingCpltCallback = pCallback;
+ break;
- case HAL_DMA2D_MSPINIT_CB_ID :
- hdma2d->MspInitCallback = pCallback;
- break;
+ case HAL_DMA2D_MSPINIT_CB_ID :
+ hdma2d->MspInitCallback = pCallback;
+ break;
- case HAL_DMA2D_MSPDEINIT_CB_ID :
- hdma2d->MspDeInitCallback = pCallback;
- break;
+ case HAL_DMA2D_MSPDEINIT_CB_ID :
+ hdma2d->MspDeInitCallback = pCallback;
+ break;
- default :
- /* Update the error code */
- hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(HAL_DMA2D_STATE_RESET == hdma2d->State)
+ else if (HAL_DMA2D_STATE_RESET == hdma2d->State)
{
switch (CallbackID)
{
- case HAL_DMA2D_MSPINIT_CB_ID :
- hdma2d->MspInitCallback = pCallback;
- break;
+ case HAL_DMA2D_MSPINIT_CB_ID :
+ hdma2d->MspInitCallback = pCallback;
+ break;
- case HAL_DMA2D_MSPDEINIT_CB_ID :
- hdma2d->MspDeInitCallback = pCallback;
- break;
+ case HAL_DMA2D_MSPDEINIT_CB_ID :
+ hdma2d->MspDeInitCallback = pCallback;
+ break;
- default :
- /* Update the error code */
- hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
{
/* Update the error code */
- hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
}
/* Release Lock */
@@ -552,73 +557,73 @@
*/
HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID)
{
-HAL_StatusTypeDef status = HAL_OK;
+ HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hdma2d);
- if(HAL_DMA2D_STATE_READY == hdma2d->State)
+ if (HAL_DMA2D_STATE_READY == hdma2d->State)
{
switch (CallbackID)
{
- case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
- hdma2d->XferCpltCallback = NULL;
- break;
+ case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
+ hdma2d->XferCpltCallback = NULL;
+ break;
- case HAL_DMA2D_TRANSFERERROR_CB_ID :
- hdma2d->XferErrorCallback = NULL;
- break;
+ case HAL_DMA2D_TRANSFERERROR_CB_ID :
+ hdma2d->XferErrorCallback = NULL;
+ break;
- case HAL_DMA2D_LINEEVENT_CB_ID :
- hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
- break;
+ case HAL_DMA2D_LINEEVENT_CB_ID :
+ hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
+ break;
- case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
- hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
- break;
+ case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
+ hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
+ break;
- case HAL_DMA2D_MSPINIT_CB_ID :
- hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
- break;
+ case HAL_DMA2D_MSPINIT_CB_ID :
+ hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
+ break;
- case HAL_DMA2D_MSPDEINIT_CB_ID :
- hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
- break;
+ case HAL_DMA2D_MSPDEINIT_CB_ID :
+ hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
+ break;
- default :
- /* Update the error code */
- hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(HAL_DMA2D_STATE_RESET == hdma2d->State)
+ else if (HAL_DMA2D_STATE_RESET == hdma2d->State)
{
switch (CallbackID)
{
- case HAL_DMA2D_MSPINIT_CB_ID :
- hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
- break;
+ case HAL_DMA2D_MSPINIT_CB_ID :
+ hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
+ break;
- case HAL_DMA2D_MSPDEINIT_CB_ID :
- hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
- break;
+ case HAL_DMA2D_MSPDEINIT_CB_ID :
+ hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
+ break;
- default :
- /* Update the error code */
- hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
{
- /* Update the error code */
- hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
}
/* Release Lock */
@@ -633,8 +638,8 @@
/** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
- *
+ * @brief IO operation functions
+ *
@verbatim
===============================================================================
##### IO operation functions #####
@@ -676,11 +681,13 @@
* conversion mode is selected, or configure
* the color value if Register-to-Memory mode is selected.
* @param DstAddress The destination memory Buffer address.
- * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
+ * @param Width The width of data to be transferred from source
+ * to destination (expressed in number of pixels per line).
* @param Height The height of data to be transferred from source to destination (expressed in number of lines).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
+HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+ uint32_t Height)
{
/* Check the parameters */
assert_param(IS_DMA2D_LINE(Height));
@@ -710,11 +717,13 @@
* conversion mode is selected, or configure
* the color value if Register-to-Memory mode is selected.
* @param DstAddress The destination memory Buffer address.
- * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
+ * @param Width The width of data to be transferred from source
+ * to destination (expressed in number of pixels per line).
* @param Height The height of data to be transferred from source to destination (expressed in number of lines).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
+HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+ uint32_t Height)
{
/* Check the parameters */
assert_param(IS_DMA2D_LINE(Height));
@@ -730,7 +739,7 @@
DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
/* Enable the transfer complete, transfer error and configuration error interrupts */
- __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
/* Enable the Peripheral */
__HAL_DMA2D_ENABLE(hdma2d);
@@ -745,11 +754,13 @@
* @param SrcAddress1 The source memory Buffer address for the foreground layer.
* @param SrcAddress2 The source memory Buffer address for the background layer.
* @param DstAddress The destination memory Buffer address.
- * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
+ * @param Width The width of data to be transferred from source
+ * to destination (expressed in number of pixels per line).
* @param Height The height of data to be transferred from source to destination (expressed in number of lines).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
+ uint32_t DstAddress, uint32_t Width, uint32_t Height)
{
/* Check the parameters */
assert_param(IS_DMA2D_LINE(Height));
@@ -762,7 +773,7 @@
hdma2d->State = HAL_DMA2D_STATE_BUSY;
#if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT)
- if(hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG)
+ if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG)
{
/*blending & fixed FG*/
WRITE_REG(hdma2d->Instance->FGCOLR, SrcAddress1);
@@ -806,11 +817,13 @@
* @param SrcAddress1 The source memory Buffer address for the foreground layer.
* @param SrcAddress2 The source memory Buffer address for the background layer.
* @param DstAddress The destination memory Buffer address.
- * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
+ * @param Width The width of data to be transferred from source
+ * to destination (expressed in number of pixels per line).
* @param Height The height of data to be transferred from source to destination (expressed in number of lines).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
+ uint32_t DstAddress, uint32_t Width, uint32_t Height)
{
/* Check the parameters */
assert_param(IS_DMA2D_LINE(Height));
@@ -823,7 +836,7 @@
hdma2d->State = HAL_DMA2D_STATE_BUSY;
#if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT)
- if(hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG)
+ if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG)
{
/*blending & fixed FG*/
WRITE_REG(hdma2d->Instance->FGCOLR, SrcAddress1);
@@ -854,7 +867,7 @@
#endif /*DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT*/
/* Enable the transfer complete, transfer error and configuration error interrupts */
- __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
/* Enable the Peripheral */
__HAL_DMA2D_ENABLE(hdma2d);
@@ -876,15 +889,15 @@
/* START bit is reset to make sure not to set it again, in the event the HW clears it
between the register read and the register write by the CPU (writing 0 has no
effect on START bitvalue) */
- MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT);
+ MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
/* Get tick */
tickstart = HAL_GetTick();
/* Check if the DMA2D is effectively disabled */
- while((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
+ while ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
{
- if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
+ if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_ABORT)
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
@@ -900,7 +913,7 @@
}
/* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
- __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
/* Change the DMA2D state*/
hdma2d->State = HAL_DMA2D_STATE_READY;
@@ -925,7 +938,7 @@
/* START bit is reset to make sure not to set it again, in the event the HW clears it
between the register read and the register write by the CPU (writing 0 has no
effect on START bitvalue). */
- MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);
+ MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
/* Get tick */
tickstart = HAL_GetTick();
@@ -933,7 +946,7 @@
/* Check if the DMA2D is effectively suspended */
while ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == DMA2D_CR_START)
{
- if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
+ if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_SUSPEND)
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
@@ -945,7 +958,7 @@
}
}
- /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
+ /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
{
hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
@@ -953,7 +966,7 @@
else
{
/* Make sure SUSP bit is cleared since it is meaningless
- when no tranfer is on-going */
+ when no transfer is on-going */
CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
}
@@ -969,7 +982,7 @@
HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
{
/* Check the SUSP and START bits */
- if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
+ if ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
{
/* Ongoing transfer is suspended: change the DMA2D state before resuming */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
@@ -979,7 +992,7 @@
/* START bit is reset to make sure not to set it again, in the event the HW clears it
between the register read and the register write by the CPU (writing 0 has no
effect on START bitvalue). */
- CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));
+ CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP | DMA2D_CR_START));
return HAL_OK;
}
@@ -1005,7 +1018,7 @@
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
- if(LayerIdx == DMA2D_BACKGROUND_LAYER)
+ if (LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Enable the background CLUT loading */
SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
@@ -1044,14 +1057,14 @@
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Configure the CLUT of the background DMA2D layer */
- if(LayerIdx == DMA2D_BACKGROUND_LAYER)
+ if (LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Write background CLUT memory address */
WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);
/* Write background CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
- ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
+ ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
/* Enable the CLUT loading for the background */
SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
@@ -1064,9 +1077,9 @@
/* Write foreground CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
- ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+ ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
- /* Enable the CLUT loading for the foreground */
+ /* Enable the CLUT loading for the foreground */
SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
}
@@ -1084,7 +1097,8 @@
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx)
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
+ uint32_t LayerIdx)
{
/* Check the parameters */
assert_param(IS_DMA2D_LAYER(LayerIdx));
@@ -1098,17 +1112,17 @@
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Configure the CLUT of the background DMA2D layer */
- if(LayerIdx == DMA2D_BACKGROUND_LAYER)
+ if (LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Write background CLUT memory address */
WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);
/* Write background CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
- ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
+ ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
/* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
- __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
/* Enable the CLUT loading for the background */
SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
@@ -1121,10 +1135,10 @@
/* Write foreground CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
- ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+ ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
/* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
- __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
/* Enable the CLUT loading for the foreground */
SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
@@ -1161,14 +1175,14 @@
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Configure the CLUT of the background DMA2D layer */
- if(LayerIdx == DMA2D_BACKGROUND_LAYER)
+ if (LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Write background CLUT memory address */
WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
/* Write background CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
+ ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
/* Enable the CLUT loading for the background */
SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
@@ -1181,9 +1195,9 @@
/* Write foreground CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+ ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
- /* Enable the CLUT loading for the foreground */
+ /* Enable the CLUT loading for the foreground */
SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
}
@@ -1218,17 +1232,17 @@
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Configure the CLUT of the background DMA2D layer */
- if(LayerIdx == DMA2D_BACKGROUND_LAYER)
+ if (LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Write background CLUT memory address */
WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
/* Write background CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
+ ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
/* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
- __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
/* Enable the CLUT loading for the background */
SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
@@ -1241,10 +1255,10 @@
/* Write foreground CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+ ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
/* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
- __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
/* Enable the CLUT loading for the foreground */
SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
@@ -1265,13 +1279,13 @@
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
{
uint32_t tickstart;
- const __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
+ const __IO uint32_t *reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
/* Abort the CLUT loading */
SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
/* If foreground CLUT loading is considered, update local variables */
- if(LayerIdx == DMA2D_FOREGROUND_LAYER)
+ if (LayerIdx == DMA2D_FOREGROUND_LAYER)
{
reg = &(hdma2d->Instance->FGPFCCR);
}
@@ -1281,9 +1295,9 @@
tickstart = HAL_GetTick();
/* Check if the CLUT loading is aborted */
- while((*reg & DMA2D_BGPFCCR_START) != 0U)
+ while ((*reg & DMA2D_BGPFCCR_START) != 0U)
{
- if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
+ if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_ABORT)
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
@@ -1299,7 +1313,7 @@
}
/* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
- __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
/* Change the DMA2D state*/
hdma2d->State = HAL_DMA2D_STATE_READY;
@@ -1323,13 +1337,13 @@
{
uint32_t tickstart;
uint32_t loadsuspended;
- const __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
+ const __IO uint32_t *reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
/* Suspend the CLUT loading */
SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
/* If foreground CLUT loading is considered, update local variables */
- if(LayerIdx == DMA2D_FOREGROUND_LAYER)
+ if (LayerIdx == DMA2D_FOREGROUND_LAYER)
{
reg = &(hdma2d->Instance->FGPFCCR);
}
@@ -1338,11 +1352,13 @@
tickstart = HAL_GetTick();
/* Check if the CLUT loading is suspended */
- loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/
- loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */
+ /* 1st condition: Suspend Check */
+ loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) ? 1UL : 0UL;
+ /* 2nd condition: Not Start Check */
+ loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START) ? 1UL : 0UL;
while (loadsuspended == 0UL)
{
- if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
+ if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_SUSPEND)
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
@@ -1352,11 +1368,13 @@
return HAL_TIMEOUT;
}
- loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/
- loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */
+ /* 1st condition: Suspend Check */
+ loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) ? 1UL : 0UL;
+ /* 2nd condition: Not Start Check */
+ loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START) ? 1UL : 0UL;
}
- /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
+ /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
if ((*reg & DMA2D_BGPFCCR_START) != 0U)
{
hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
@@ -1364,7 +1382,7 @@
else
{
/* Make sure SUSP bit is cleared since it is meaningless
- when no tranfer is on-going */
+ when no transfer is on-going */
CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
}
@@ -1383,18 +1401,18 @@
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
{
/* Check the SUSP and START bits for background or foreground CLUT loading */
- if(LayerIdx == DMA2D_BACKGROUND_LAYER)
+ if (LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Background CLUT loading suspension check */
if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
{
- if((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
+ if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
{
- /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
- hdma2d->State = HAL_DMA2D_STATE_BUSY;
+ /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+ }
}
}
- }
else
{
/* Foreground CLUT loading suspension check */
@@ -1402,11 +1420,11 @@
{
if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
{
- /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
- hdma2d->State = HAL_DMA2D_STATE_BUSY;
+ /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+ }
}
}
- }
/* Resume the CLUT loading */
CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
@@ -1430,15 +1448,15 @@
__IO uint32_t isrflags = 0x0U;
/* Polling for DMA2D transfer */
- if((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
+ if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
{
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* Get tick */
+ tickstart = HAL_GetTick();
- while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
+ while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
{
isrflags = READ_REG(hdma2d->Instance->ISR);
- if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
+ if ((isrflags & (DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U)
{
if ((isrflags & DMA2D_FLAG_CE) != 0U)
{
@@ -1460,9 +1478,9 @@
return HAL_ERROR;
}
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
@@ -1486,10 +1504,10 @@
/* Get tick */
tickstart = HAL_GetTick();
- while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
+ while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
{
isrflags = READ_REG(hdma2d->Instance->ISR);
- if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
+ if ((isrflags & (DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U)
{
if ((isrflags & DMA2D_FLAG_CAE) != 0U)
{
@@ -1507,7 +1525,7 @@
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
/* Change DMA2D state */
- hdma2d->State= HAL_DMA2D_STATE_ERROR;
+ hdma2d->State = HAL_DMA2D_STATE_ERROR;
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
@@ -1515,15 +1533,15 @@
return HAL_ERROR;
}
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
/* Change the DMA2D state */
- hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
+ hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
@@ -1535,7 +1553,7 @@
}
/* Clear the transfer complete and CLUT loading flags */
- __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC | DMA2D_FLAG_CTC);
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_READY;
@@ -1576,7 +1594,7 @@
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
- if(hdma2d->XferErrorCallback != NULL)
+ if (hdma2d->XferErrorCallback != NULL)
{
/* Transfer error Callback */
hdma2d->XferErrorCallback(hdma2d);
@@ -1603,7 +1621,7 @@
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
- if(hdma2d->XferErrorCallback != NULL)
+ if (hdma2d->XferErrorCallback != NULL)
{
/* Transfer error Callback */
hdma2d->XferErrorCallback(hdma2d);
@@ -1630,7 +1648,7 @@
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
- if(hdma2d->XferErrorCallback != NULL)
+ if (hdma2d->XferErrorCallback != NULL)
{
/* Transfer error Callback */
hdma2d->XferErrorCallback(hdma2d);
@@ -1677,7 +1695,7 @@
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
- if(hdma2d->XferCpltCallback != NULL)
+ if (hdma2d->XferCpltCallback != NULL)
{
/* Transfer complete Callback */
hdma2d->XferCpltCallback(hdma2d);
@@ -1752,8 +1770,8 @@
*/
/** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
- *
+ * @brief Peripheral Control functions
+ *
@verbatim
===============================================================================
##### Peripheral Control functions #####
@@ -1783,15 +1801,16 @@
HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
{
DMA2D_LayerCfgTypeDef *pLayerCfg;
- uint32_t regMask, regValue;
+ uint32_t regMask;
+ uint32_t regValue;
/* Check the parameters */
assert_param(IS_DMA2D_LAYER(LayerIdx));
assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset));
- if(hdma2d->Init.Mode != DMA2D_R2M)
+ if (hdma2d->Init.Mode != DMA2D_R2M)
{
assert_param(IS_DMA2D_INPUT_COLOR_MODE(hdma2d->LayerCfg[LayerIdx].InputColorMode));
- if(hdma2d->Init.Mode != DMA2D_M2M)
+ if (hdma2d->Init.Mode != DMA2D_M2M)
{
assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode));
}
@@ -1808,7 +1827,7 @@
pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
/* Prepare the value to be written to the BGPFCCR or FGPFCCR register */
- regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) |\
+ regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) | \
(pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos) | (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos);
regMask = (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS);
@@ -1819,11 +1838,11 @@
}
else
{
- regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
+ regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
}
/* Configure the background DMA2D layer */
- if(LayerIdx == DMA2D_BACKGROUND_LAYER)
+ if (LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Write DMA2D BGPFCCR register */
MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
@@ -1834,7 +1853,8 @@
/* DMA2D BGCOLR register configuration -------------------------------------*/
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
{
- WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));
+ WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | \
+ DMA2D_BGCOLR_RED));
}
}
/* Configure the foreground DMA2D layer */
@@ -1842,7 +1862,7 @@
{
- /* Write DMA2D FGPFCCR register */
+ /* Write DMA2D FGPFCCR register */
MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
/* DMA2D FGOR register configuration -------------------------------------*/
@@ -1851,7 +1871,8 @@
/* DMA2D FGCOLR register configuration -------------------------------------*/
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
{
- WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));
+ WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | \
+ DMA2D_FGCOLR_RED));
}
}
/* Initialize the DMA2D state*/
@@ -1891,24 +1912,24 @@
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Configure the CLUT of the background DMA2D layer */
- if(LayerIdx == DMA2D_BACKGROUND_LAYER)
+ if (LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Write background CLUT memory address */
WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
/* Write background CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
- }
- /* Configure the CLUT of the foreground DMA2D layer */
- else
- {
- /* Write foreground CLUT memory address */
+ ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
+ }
+ /* Configure the CLUT of the foreground DMA2D layer */
+ else
+ {
+ /* Write foreground CLUT memory address */
WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
/* Write foreground CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+ ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
}
/* Set the DMA2D state to Ready*/
@@ -1934,8 +1955,6 @@
HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
{
/* Check the parameters */
- assert_param(IS_DMA2D_LINEWATERMARK(Line));
-
if (Line > DMA2D_LWR_LW)
{
return HAL_ERROR;
@@ -2042,8 +2061,8 @@
/** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
- * @brief Peripheral State functions
- *
+ * @brief Peripheral State functions
+ *
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
@@ -2102,7 +2121,8 @@
* @param Height The height of data to be transferred from source to destination.
* @retval HAL status
*/
-static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
+static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+ uint32_t Height)
{
uint32_t tmp;
uint32_t tmp1;
@@ -2111,7 +2131,7 @@
uint32_t tmp4;
/* Configure DMA2D data size */
- MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_NLR_PL_Pos)));
+ MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL | DMA2D_NLR_PL), (Height | (Width << DMA2D_NLR_PL_Pos)));
/* Configure DMA2D destination address */
WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
@@ -2127,7 +2147,7 @@
/* Prepare the value to be written to the OCOLR register according to the color mode */
if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
{
- tmp = (tmp3 | tmp2 | tmp1| tmp4);
+ tmp = (tmp3 | tmp2 | tmp1 | tmp4);
}
else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
{
@@ -2137,7 +2157,7 @@
{
tmp2 = (tmp2 >> 19U);
tmp3 = (tmp3 >> 10U);
- tmp4 = (tmp4 >> 3U );
+ tmp4 = (tmp4 >> 3U);
tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
}
else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
@@ -2145,7 +2165,7 @@
tmp1 = (tmp1 >> 31U);
tmp2 = (tmp2 >> 19U);
tmp3 = (tmp3 >> 11U);
- tmp4 = (tmp4 >> 3U );
+ tmp4 = (tmp4 >> 3U);
tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
}
else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
@@ -2153,16 +2173,16 @@
tmp1 = (tmp1 >> 28U);
tmp2 = (tmp2 >> 20U);
tmp3 = (tmp3 >> 12U);
- tmp4 = (tmp4 >> 4U );
+ tmp4 = (tmp4 >> 4U);
tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
}
/* Write to DMA2D OCOLR register */
WRITE_REG(hdma2d->Instance->OCOLR, tmp);
}
#if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT)
- else if(hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG) /*M2M_blending with fixed color FG DMA2D Mode selected*/
+ else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG) /*M2M_blending with fixed color FG DMA2D Mode selected*/
{
- WRITE_REG(hdma2d->Instance->BGMAR , pdata);
+ WRITE_REG(hdma2d->Instance->BGMAR, pdata);
}
else /* M2M, M2M_PFC,M2M_Blending or M2M_blending with fixed color BG DMA2D Mode */
#else
@@ -2187,5 +2207,3 @@
*/
#endif /* DMA2D */
#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_dma_ex.c b/Src/stm32l4xx_hal_dma_ex.c
index 0a8f922..e6684a2 100644
--- a/Src/stm32l4xx_hal_dma_ex.c
+++ b/Src/stm32l4xx_hal_dma_ex.c
@@ -7,6 +7,17 @@
* functionalities of the DMA Extension peripheral:
* + Extended features functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -33,17 +44,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -305,5 +305,3 @@
*/
#endif /* DMAMUX1 */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_dsi.c b/Src/stm32l4xx_hal_dsi.c
index e1fc3d1..521d38f 100644
--- a/Src/stm32l4xx_hal_dsi.c
+++ b/Src/stm32l4xx_hal_dsi.c
@@ -9,6 +9,17 @@
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State and Errors functions
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -140,17 +151,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -173,7 +173,7 @@
/** @addtogroup DSI_Private_Constants
* @{
*/
-#define DSI_TIMEOUT_VALUE ((uint32_t)1000U) /* 1s */
+#define DSI_TIMEOUT_VALUE ((uint32_t)100U) /* 100ms */
#define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \
DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \
@@ -200,12 +200,14 @@
uint32_t Data1);
static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
- uint32_t ChannelID,
- uint32_t Mode,
- uint32_t Param1,
- uint32_t Param2);
-
+ uint32_t ChannelID,
+ uint32_t Mode,
+ uint32_t Param1,
+ uint32_t Param2);
/* Private functions ---------------------------------------------------------*/
+/** @defgroup DSI_Private_Functions DSI Private Functions
+ * @{
+ */
/**
* @brief Generic DSI packet header configuration
* @param DSIx Pointer to DSI register base
@@ -255,10 +257,10 @@
tickstart = HAL_GetTick();
/* Wait for Command FIFO Empty */
- while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
+ while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
{
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -271,6 +273,10 @@
return HAL_OK;
}
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DSI_Exported_Functions
* @{
@@ -365,11 +371,17 @@
/* Set the PLL division factors */
hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);
- hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << 2U) | ((PLLInit->PLLIDF) << 11U) | ((PLLInit->PLLODF) << 16U));
+ hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << DSI_WRPCR_PLL_NDIV_Pos) | \
+ ((PLLInit->PLLIDF) << DSI_WRPCR_PLL_IDF_Pos) | \
+ ((PLLInit->PLLODF) << DSI_WRPCR_PLL_ODF_Pos));
/* Enable the DSI PLL */
__HAL_DSI_PLL_ENABLE(hdsi);
+ /* Requires min of 400µs delay before reading the PLLLS flag */
+ /* 1ms delay is inserted that is the minimum HAL delay granularity */
+ HAL_Delay(1);
+
/* Get tick */
tickstart = HAL_GetTick();
@@ -419,7 +431,7 @@
hdsi->Instance->IER[1U] = 0U;
hdsi->ErrorMsk = 0U;
- /* Initialise the error code */
+ /* Initialize the error code */
hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
/* Initialize the DSI state*/
@@ -473,7 +485,7 @@
HAL_DSI_MspDeInit(hdsi);
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
- /* Initialise the error code */
+ /* Initialize the error code */
hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
/* Initialize the DSI state*/
@@ -733,11 +745,11 @@
break;
case HAL_DSI_MSPINIT_CB_ID :
- hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legcay weak MspInit Callback */
+ hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legacy weak MspInit Callback */
break;
case HAL_DSI_MSPDEINIT_CB_ID :
- hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legcay weak MspDeInit Callback */
+ hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legacy weak MspDeInit Callback */
break;
default :
@@ -753,11 +765,11 @@
switch (CallbackID)
{
case HAL_DSI_MSPINIT_CB_ID :
- hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legcay weak MspInit Callback */
+ hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legacy weak MspInit Callback */
break;
case HAL_DSI_MSPDEINIT_CB_ID :
- hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legcay weak MspDeInit Callback */
+ hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legacy weak MspDeInit Callback */
break;
default :
@@ -808,7 +820,8 @@
*/
void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)
{
- uint32_t ErrorStatus0, ErrorStatus1;
+ uint32_t ErrorStatus0;
+ uint32_t ErrorStatus1;
/* Tearing Effect Interrupt management ***************************************/
if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != 0U)
@@ -1365,7 +1378,8 @@
High-Speed transmission.
To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed
to Low-Power and from Low-Power to High-Speed.
- This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR).
+ This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration
+ Register (DSI_CLTCR).
But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME.
Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME.
@@ -1587,7 +1601,7 @@
/* Process locked */
__HAL_LOCK(hdsi);
- status = DSI_ShortWrite(hdsi, ChannelID, Mode, Param1, Param2);
+ status = DSI_ShortWrite(hdsi, ChannelID, Mode, Param1, Param2);
/* Process unlocked */
__HAL_UNLOCK(hdsi);
@@ -1616,7 +1630,9 @@
uint32_t Param1,
uint8_t *ParametersTable)
{
- uint32_t uicounter, nbBytes, count;
+ uint32_t uicounter;
+ uint32_t nbBytes;
+ uint32_t count;
uint32_t tickstart;
uint32_t fifoword;
uint8_t *pparams = ParametersTable;
@@ -1721,7 +1737,7 @@
{
/* set max return packet size */
if (DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize) & 0xFFU),
- (((datasize) >> 8U) & 0xFFU)) != HAL_OK)
+ (((datasize) >> 8U) & 0xFFU)) != HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
@@ -1782,6 +1798,21 @@
return HAL_TIMEOUT;
}
+
+ /* Software workaround to avoid HAL_TIMEOUT when a DSI read command is */
+ /* issued to the panel and the read data is not captured by the DSI Host */
+ /* which returns Packet Size Error. */
+ /* Need to ensure that the Read command has finished before checking PSE */
+ if ((hdsi->Instance->GPSR & DSI_GPSR_RCB) == 0U)
+ {
+ if ((hdsi->Instance->ISR[1U] & DSI_ISR1_PSE) == DSI_ISR1_PSE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
+ }
}
/* Process unlocked */
@@ -2027,6 +2058,10 @@
}
}
+ /* Reset the digital section of the D-PHY */
+ CLEAR_BIT(hdsi->Instance->PCTLR, DSI_PCTLR_DEN);
+ SET_BIT(hdsi->Instance->PCTLR, DSI_PCTLR_DEN);
+
/* Exit ULPS on Clock and Data Lanes */
hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL);
@@ -2077,7 +2112,7 @@
/* De-assert the ULPM requests and the ULPM exit bits */
hdsi->Instance->PUCR = 0U;
- /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */
+ /* Switch the lane byte clock source in the RCC from system PLL to D-PHY */
__HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY);
/* Restore clock lane configuration to HS */
@@ -2289,7 +2324,7 @@
* @brief Custom lane pins configuration
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param CustomLane Function to be applyed on selected lane.
+ * @param CustomLane Function to be applied on selected lane.
* This parameter can be any value of @arg DSI_CustomLane
* @param Lane select between clock or data lane 0 or data lane 1.
* This parameter can be any value of @arg DSI_Lane_Select
@@ -2727,5 +2762,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_exti.c b/Src/stm32l4xx_hal_exti.c
index dafb7a0..662203c 100644
--- a/Src/stm32l4xx_hal_exti.c
+++ b/Src/stm32l4xx_hal_exti.c
@@ -8,6 +8,17 @@
* + Initialization and de-initialization functions
* + IO operation functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### EXTI Peripheral features #####
@@ -69,18 +80,6 @@
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -315,6 +314,10 @@
pExtiConfig->Mode |= EXTI_MODE_EVENT;
}
+ /* Get default Trigger and GPIOSel configuration */
+ pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+ pExtiConfig->GPIOSel = 0x00u;
+
/* 2] Get trigger for configurable lines : rising */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
{
@@ -326,10 +329,6 @@
{
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
}
- else
- {
- pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
- }
/* Get falling configuration */
regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
@@ -349,15 +348,6 @@
regval = SYSCFG->EXTICR[linepos >> 2u];
pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
}
- else
- {
- pExtiConfig->GPIOSel = 0x00u;
- }
- }
- else
- {
- pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
- pExtiConfig->GPIOSel = 0x00u;
}
return HAL_OK;
@@ -640,4 +630,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_firewall.c b/Src/stm32l4xx_hal_firewall.c
index 3eee028..86af2e9 100644
--- a/Src/stm32l4xx_hal_firewall.c
+++ b/Src/stm32l4xx_hal_firewall.c
@@ -6,7 +6,17 @@
* This file provides firmware functions to manage the Firewall
* Peripheral initialization and enabling.
*
+ ******************************************************************************
+ * @attention
*
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
@@ -30,17 +40,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -79,7 +78,7 @@
This subsection provides the functions allowing to initialize the Firewall.
Initialization is done by HAL_FIREWALL_Config():
- (+) Enable the Firewall clock thru __HAL_RCC_FIREWALL_CLK_ENABLE() macro.
+ (+) Enable the Firewall clock through __HAL_RCC_FIREWALL_CLK_ENABLE() macro.
(+) Set the protected code segment address start and length.
@@ -291,5 +290,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_flash.c b/Src/stm32l4xx_hal_flash.c
index d32aa85..75fa3ea 100644
--- a/Src/stm32l4xx_hal_flash.c
+++ b/Src/stm32l4xx_hal_flash.c
@@ -75,14 +75,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -764,4 +762,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_flash_ex.c b/Src/stm32l4xx_hal_flash_ex.c
index c889f63..d9b1205 100644
--- a/Src/stm32l4xx_hal_flash_ex.c
+++ b/Src/stm32l4xx_hal_flash_ex.c
@@ -48,14 +48,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -145,9 +143,6 @@
/* Deactivate the cache if they are activated to avoid data misbehavior */
if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)
{
- /* Disable instruction cache */
- __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
-
if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
{
/* Disable data cache */
@@ -245,9 +240,6 @@
/* Deactivate the cache if they are activated to avoid data misbehavior */
if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)
{
- /* Disable instruction cache */
- __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
-
if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
{
/* Disable data cache */
@@ -607,6 +599,8 @@
if((cache == FLASH_CACHE_ICACHE_ENABLED) ||
(cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
{
+ /* Disable instruction cache */
+ __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
/* Reset instruction cache */
__HAL_FLASH_INSTRUCTION_CACHE_RESET();
/* Enable instruction cache */
@@ -1320,4 +1314,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_flash_ramfunc.c b/Src/stm32l4xx_hal_flash_ramfunc.c
index 3aa7baa..82599f9 100644
--- a/Src/stm32l4xx_hal_flash_ramfunc.c
+++ b/Src/stm32l4xx_hal_flash_ramfunc.c
@@ -35,14 +35,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -249,6 +247,5 @@
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_gfxmmu.c b/Src/stm32l4xx_hal_gfxmmu.c
index 11c7697..084c590 100644
--- a/Src/stm32l4xx_hal_gfxmmu.c
+++ b/Src/stm32l4xx_hal_gfxmmu.c
@@ -6,9 +6,20 @@
* functionalities of the Graphic MMU (GFXMMU) peripheral:
* + Initialization and De-initialization.
* + LUT configuration.
- * + Modify physical buffer adresses.
+ * + Modify physical buffer addresses.
* + Error management.
- *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -32,7 +43,7 @@
(#) Use HAL_GFXMMU_ConfigLut() to copy LUT from flash to look up RAM.
(#) Use HAL_GFXMMU_ConfigLutLine() to configure one line of LUT.
- *** Modify physical buffer adresses ***
+ *** Modify physical buffer addresses ***
=======================================
[..]
(#) Use HAL_GFXMMU_ModifyBuffers() to modify physical buffer addresses.
@@ -106,17 +117,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -213,7 +213,7 @@
/* Configure default value on GFXMMU_DVR register */
hgfxmmu->Instance->DVR = hgfxmmu->Init.DefaultValue;
- /* Configure physical buffer adresses on GFXMMU_BxCR registers */
+ /* Configure physical buffer addresses on GFXMMU_BxCR registers */
hgfxmmu->Instance->B0CR = hgfxmmu->Init.Buffers.Buf0Address;
hgfxmmu->Instance->B1CR = hgfxmmu->Init.Buffers.Buf1Address;
hgfxmmu->Instance->B2CR = hgfxmmu->Init.Buffers.Buf2Address;
@@ -457,7 +457,7 @@
==============================================================================
[..] This section provides functions allowing to:
(+) Configure LUT.
- (+) Modify physical buffer adresses.
+ (+) Modify physical buffer addresses.
(+) Manage error.
@endverbatim
* @{
@@ -639,7 +639,7 @@
}
else
{
- /* Modify physical buffer adresses on GFXMMU_BxCR registers */
+ /* Modify physical buffer addresses on GFXMMU_BxCR registers */
hgfxmmu->Instance->B0CR = Buffers->Buf0Address;
hgfxmmu->Instance->B1CR = Buffers->Buf1Address;
hgfxmmu->Instance->B2CR = Buffers->Buf2Address;
@@ -767,4 +767,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_gpio.c b/Src/stm32l4xx_hal_gpio.c
index 66f01e1..6ba7d60 100644
--- a/Src/stm32l4xx_hal_gpio.c
+++ b/Src/stm32l4xx_hal_gpio.c
@@ -8,6 +8,17 @@
* + Initialization and de-initialization functions
* + IO operation functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### GPIO Peripheral features #####
@@ -89,17 +100,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -124,18 +124,9 @@
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
-/** @defgroup GPIO_Private_Defines GPIO Private Defines
+/** @addtogroup GPIO_Private_Defines GPIO Private Defines
* @{
*/
-#define GPIO_MODE (0x00000003u)
-#define ANALOG_MODE (0x00000008u)
-#define EXTI_MODE (0x10000000u)
-#define GPIO_MODE_IT (0x00010000u)
-#define GPIO_MODE_EVT (0x00020000u)
-#define RISING_EDGE (0x00100000u)
-#define FALLING_EDGE (0x00200000u)
-#define GPIO_OUTPUT_TYPE (0x00000010u)
-
#define GPIO_NUMBER (16u)
/**
* @}
@@ -179,7 +170,6 @@
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
- assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
@@ -191,11 +181,11 @@
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
- if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
- (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
@@ -205,7 +195,7 @@
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
temp &= ~(GPIO_OTYPER_OT0 << position) ;
- temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4u) << position);
+ temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
GPIOx->OTYPER = temp;
}
@@ -217,20 +207,26 @@
/* Configure the IO Output Type */
temp = GPIOx->ASCR;
temp &= ~(GPIO_ASCR_ASC0 << position) ;
- temp |= (((GPIO_Init->Mode & ANALOG_MODE) >> 3) << position);
+ temp |= (((GPIO_Init->Mode & GPIO_MODE_ANALOG_ADC_CONTROL) >> 3) << position);
GPIOx->ASCR = temp;
}
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
/* Activate the Pull-up or Pull down resistor for the current IO */
- temp = GPIOx->PUPDR;
- temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
- temp |= ((GPIO_Init->Pull) << (position * 2u));
- GPIOx->PUPDR = temp;
+ if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
+ {
+ /* Check the Pull parameter */
+ assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
+ temp = GPIOx->PUPDR;
+ temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
+ temp |= ((GPIO_Init->Pull) << (position * 2U));
+ GPIOx->PUPDR = temp;
+ }
/* In case of Alternate function mode selection */
- if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
@@ -251,7 +247,7 @@
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
- if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
@@ -261,27 +257,10 @@
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
SYSCFG->EXTICR[position >> 2u] = temp;
- /* Clear EXTI line configuration */
- temp = EXTI->IMR1;
- temp &= ~(iocurrent);
- if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
- {
- temp |= iocurrent;
- }
- EXTI->IMR1 = temp;
-
- temp = EXTI->EMR1;
- temp &= ~(iocurrent);
- if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
- {
- temp |= iocurrent;
- }
- EXTI->EMR1 = temp;
-
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
temp &= ~(iocurrent);
- if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+ if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
{
temp |= iocurrent;
}
@@ -289,11 +268,28 @@
temp = EXTI->FTSR1;
temp &= ~(iocurrent);
- if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+ if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
{
temp |= iocurrent;
}
EXTI->FTSR1 = temp;
+
+ /* Clear EXTI line configuration */
+ temp = EXTI->EMR1;
+ temp &= ~(iocurrent);
+ if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
+ {
+ temp |= iocurrent;
+ }
+ EXTI->EMR1 = temp;
+
+ temp = EXTI->IMR1;
+ temp &= ~(iocurrent);
+ if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
+ {
+ temp |= iocurrent;
+ }
+ EXTI->IMR1 = temp;
}
}
@@ -338,8 +334,8 @@
EXTI->EMR1 &= ~(iocurrent);
/* Clear Rising Falling edge configuration */
- EXTI->RTSR1 &= ~(iocurrent);
EXTI->FTSR1 &= ~(iocurrent);
+ EXTI->RTSR1 &= ~(iocurrent);
tmp = 0x0FuL << (4u * (position & 0x03u));
SYSCFG->EXTICR[position >> 2u] &= ~tmp;
@@ -457,7 +453,7 @@
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
- /* get current Ouput Data Register value */
+ /* get current Output Data Register value */
odr = GPIOx->ODR;
/* Set selected pins that were at low level, and reset ones that were high */
@@ -553,4 +549,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_hash.c b/Src/stm32l4xx_hal_hash.c
index c780247..30baead 100644
--- a/Src/stm32l4xx_hal_hash.c
+++ b/Src/stm32l4xx_hal_hash.c
@@ -12,6 +12,17 @@
* + Peripheral State methods
* + HASH or HMAC processing suspension/resumption
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
@@ -28,13 +39,13 @@
(##) When resorting to DMA-based APIs (e.g. HAL_HASH_xxx_Start_DMA())
(+++) Enable the DMAx interface clock using
__DMAx_CLK_ENABLE()
- (+++) Configure and enable one DMA stream to manage data transfer from
- memory to peripheral (input stream). Managing data transfer from
+ (+++) Configure and enable one DMA channel to manage data transfer from
+ memory to peripheral (input channel). Managing data transfer from
peripheral to memory can be performed only using CPU.
(+++) Associate the initialized DMA handle to the HASH DMA handle
using __HAL_LINKDMA()
(+++) Configure the priority and enable the NVIC for the transfer complete
- interrupt on the DMA Stream: use
+ interrupt on the DMA channel: use
HAL_NVIC_SetPriority() and
HAL_NVIC_EnableIRQ()
@@ -71,10 +82,11 @@
well the computed digest.
(##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
- (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
- From that point, each buffer can be fed to the Peripheral thru HAL_HASH_xxx_Start_DMA() API.
+ (+++) HASH processing: once initialization is done, MDMAT bit must be set
+ through __HAL_HASH_SET_MDMAT() macro.
+ From that point, each buffer can be fed to the Peripheral through HAL_HASH_xxx_Start_DMA() API.
Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
- macro then wrap-up the HASH processing in feeding the last input buffer thru the
+ macro then wrap-up the HASH processing in feeding the last input buffer through the
same API HAL_HASH_xxx_Start_DMA(). The digest can then be retrieved with a call to
API HAL_HASH_xxx_Finish().
(+++) HMAC processing (requires to resort to extended functions):
@@ -119,34 +131,36 @@
and not extra bits.
(##) If user needs to perform a hash computation of a large input buffer that is spread around various places
- in memory and where each piece of this input buffer is not necessarily a multiple of 4 bytes in size, it
- becomes necessary to use a temporary buffer to format the data accordingly before feeding them to the Peripheral.
+ in memory and where each piece of this input buffer is not necessarily a multiple of 4 bytes in size, it becomes
+ necessary to use a temporary buffer to format the data accordingly before feeding them to the Peripheral.
It is advised to the user to
(+++) achieve the first formatting operation by software then enter the data
- (+++) while the Peripheral is processing the first input set, carry out the second formatting operation by software, to be ready when DINIS occurs.
+ (+++) while the Peripheral is processing the first input set, carry out the second formatting
+ operation by software, to be ready when DINIS occurs.
(+++) repeat step 2 until the whole message is processed.
[..]
(#) HAL in DMA mode
(##) Again, due to hardware design, the DMA transfer to feed the data can only be done on a word-basis.
- The same field described above in HASH_STR is used to specify which bits to discard at the end of the DMA transfer
- to process only the message bits and not extra bits. Due to hardware implementation, this is possible only at the
- end of the complete message. When several DMA transfers are needed to enter the message, this is not applicable at
- the end of the intermediary transfers.
+ The same field described above in HASH_STR is used to specify which bits to discard at the end of the
+ DMA transfer to process only the message bits and not extra bits. Due to hardware implementation,
+ this is possible only at the end of the complete message. When several DMA transfers are needed to
+ enter the message, this is not applicable at the end of the intermediary transfers.
- (##) Similarly to the interruption-driven mode, it is suggested to the user to format the consecutive chunks of data
- by software while the DMA transfer and processing is on-going for the first parts of the message. Due to the 32-bit alignment
- required for the DMA transfer, it is underlined that the software formatting operation is more complex than in the IT mode.
+ (##) Similarly to the interruption-driven mode, it is suggested to the user to format the consecutive
+ chunks of data by software while the DMA transfer and processing is on-going for the first parts of
+ the message. Due to the 32-bit alignment required for the DMA transfer, it is underlined that the
+ software formatting operation is more complex than in the IT mode.
*** Callback registration ***
===================================
[..]
(#) The compilation define USE_HAL_HASH_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use function @ref HAL_HASH_RegisterCallback() to register a user callback.
+ Use function HAL_HASH_RegisterCallback() to register a user callback.
- (#) Function @ref HAL_HASH_RegisterCallback() allows to register following callbacks:
+ (#) Function HAL_HASH_RegisterCallback() allows to register following callbacks:
(+) InCpltCallback : callback for input completion.
(+) DgstCpltCallback : callback for digest computation completion.
(+) ErrorCallback : callback for error.
@@ -155,9 +169,9 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- (#) Use function @ref HAL_HASH_UnRegisterCallback() to reset a callback to the default
+ (#) Use function HAL_HASH_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
- @ref HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) InCpltCallback : callback for input completion.
@@ -166,13 +180,13 @@
(+) MspInitCallback : HASH MspInit.
(+) MspDeInitCallback : HASH MspDeInit.
- (#) By default, after the @ref HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET
+ (#) By default, after the HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions:
- examples @ref HAL_HASH_InCpltCallback(), @ref HAL_HASH_DgstCpltCallback()
+ examples HAL_HASH_InCpltCallback(), HAL_HASH_DgstCpltCallback()
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_HASH_Init
- and @ref HAL_HASH_DeInit only when these callbacks are null (not registered beforehand)
- If not, MspInit or MspDeInit are not null, the @ref HAL_HASH_Init and @ref HAL_HASH_DeInit
+ reset to the legacy weak (surcharged) functions in the HAL_HASH_Init
+ and HAL_HASH_DeInit only when these callbacks are null (not registered beforehand)
+ If not, MspInit or MspDeInit are not null, the HAL_HASH_Init and HAL_HASH_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
Callbacks can be registered/unregistered in READY state only.
@@ -180,8 +194,8 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_HASH_RegisterCallback before calling @ref HAL_HASH_DeInit
- or @ref HAL_HASH_Init function.
+ using HAL_HASH_RegisterCallback before calling HAL_HASH_DeInit
+ or HAL_HASH_Init function.
When The compilation define USE_HAL_HASH_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
@@ -189,17 +203,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -270,7 +273,8 @@
static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
static void HASH_DMAError(DMA_HandleTypeDef *hdma);
static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
-static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status,
+ uint32_t Timeout);
static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash);
static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash);
@@ -284,8 +288,8 @@
*/
/** @defgroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization, configuration and call-back functions.
- *
+ * @brief Initialization, configuration and call-back functions.
+ *
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
@@ -324,11 +328,11 @@
HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
{
/* Check the hash handle allocation */
- if(hhash == NULL)
+ if (hhash == NULL)
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
@@ -340,9 +344,10 @@
/* Reset Callback pointers in HAL_HASH_STATE_RESET only */
hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak (surcharged) input completion callback */
- hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation completion callback */
+ hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation
+ completion callback */
hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak (surcharged) error callback */
- if(hhash->MspInitCallback == NULL)
+ if (hhash->MspInitCallback == NULL)
{
hhash->MspInitCallback = HAL_HASH_MspInit;
}
@@ -351,7 +356,7 @@
hhash->MspInitCallback(hhash);
}
#else
- if(hhash->State == HAL_HASH_STATE_RESET)
+ if (hhash->State == HAL_HASH_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hhash->Lock = HAL_UNLOCKED;
@@ -361,7 +366,7 @@
}
#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
- /* Change the HASH state */
+ /* Change the HASH state */
hhash->State = HAL_HASH_STATE_BUSY;
/* Reset HashInCount, HashITCounter, HashBuffSize and NbWordsAlreadyPushed */
@@ -379,7 +384,7 @@
/* Set the data type bit */
MODIFY_REG(HASH->CR, HASH_CR_DATATYPE, hhash->Init.DataType);
/* Reset MDMAT bit */
-__HAL_HASH_RESET_MDMAT();
+ __HAL_HASH_RESET_MDMAT();
/* Reset HASH handle status */
hhash->Status = HAL_OK;
@@ -401,7 +406,7 @@
HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
{
/* Check the HASH handle allocation */
- if(hhash == NULL)
+ if (hhash == NULL)
{
return HAL_ERROR;
}
@@ -420,13 +425,13 @@
hhash->DigestCalculationDisable = RESET;
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
- if(hhash->MspDeInitCallback == NULL)
- {
- hhash->MspDeInitCallback = HAL_HASH_MspDeInit;
- }
+ if (hhash->MspDeInitCallback == NULL)
+ {
+ hhash->MspDeInitCallback = HAL_HASH_MspDeInit;
+ }
- /* DeInit the low level hardware */
- hhash->MspDeInitCallback(hhash);
+ /* DeInit the low level hardware */
+ hhash->MspDeInitCallback(hhash);
#else
/* DeInit the low level hardware: CLOCK, NVIC */
HAL_HASH_MspDeInit(hhash);
@@ -483,7 +488,7 @@
* @brief Input data transfer complete call back.
* @note HAL_HASH_InCpltCallback() is called when the complete input message
* has been fed to the Peripheral. This API is invoked only when input data are
- * entered under interruption or thru DMA.
+ * entered under interruption or through DMA.
* @note In case of HASH or HMAC multi-buffer DMA feeding case (MDMAT bit set),
* HAL_HASH_InCpltCallback() is called at the end of each buffer feeding
* to the Peripheral.
@@ -549,11 +554,12 @@
* @param pCallback pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID,
+ pHASH_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
/* Update the error code */
hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
@@ -562,64 +568,64 @@
/* Process locked */
__HAL_LOCK(hhash);
- if(HAL_HASH_STATE_READY == hhash->State)
+ if (HAL_HASH_STATE_READY == hhash->State)
{
switch (CallbackID)
{
- case HAL_HASH_INPUTCPLT_CB_ID :
- hhash->InCpltCallback = pCallback;
- break;
+ case HAL_HASH_INPUTCPLT_CB_ID :
+ hhash->InCpltCallback = pCallback;
+ break;
- case HAL_HASH_DGSTCPLT_CB_ID :
- hhash->DgstCpltCallback = pCallback;
- break;
+ case HAL_HASH_DGSTCPLT_CB_ID :
+ hhash->DgstCpltCallback = pCallback;
+ break;
- case HAL_HASH_ERROR_CB_ID :
- hhash->ErrorCallback = pCallback;
- break;
+ case HAL_HASH_ERROR_CB_ID :
+ hhash->ErrorCallback = pCallback;
+ break;
- case HAL_HASH_MSPINIT_CB_ID :
- hhash->MspInitCallback = pCallback;
- break;
+ case HAL_HASH_MSPINIT_CB_ID :
+ hhash->MspInitCallback = pCallback;
+ break;
- case HAL_HASH_MSPDEINIT_CB_ID :
- hhash->MspDeInitCallback = pCallback;
- break;
+ case HAL_HASH_MSPDEINIT_CB_ID :
+ hhash->MspDeInitCallback = pCallback;
+ break;
- default :
- /* Update the error code */
- hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(HAL_HASH_STATE_RESET == hhash->State)
+ else if (HAL_HASH_STATE_RESET == hhash->State)
{
switch (CallbackID)
{
- case HAL_HASH_MSPINIT_CB_ID :
- hhash->MspInitCallback = pCallback;
- break;
+ case HAL_HASH_MSPINIT_CB_ID :
+ hhash->MspInitCallback = pCallback;
+ break;
- case HAL_HASH_MSPDEINIT_CB_ID :
- hhash->MspDeInitCallback = pCallback;
- break;
+ case HAL_HASH_MSPDEINIT_CB_ID :
+ hhash->MspDeInitCallback = pCallback;
+ break;
- default :
- /* Update the error code */
- hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
{
/* Update the error code */
- hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
}
/* Release Lock */
@@ -642,69 +648,70 @@
*/
HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID)
{
-HAL_StatusTypeDef status = HAL_OK;
+ HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hhash);
- if(HAL_HASH_STATE_READY == hhash->State)
+ if (HAL_HASH_STATE_READY == hhash->State)
{
switch (CallbackID)
{
- case HAL_HASH_INPUTCPLT_CB_ID :
- hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak (surcharged) input completion callback */
- break;
+ case HAL_HASH_INPUTCPLT_CB_ID :
+ hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak (surcharged) input completion callback */
+ break;
- case HAL_HASH_DGSTCPLT_CB_ID :
- hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation completion callback */
- break;
+ case HAL_HASH_DGSTCPLT_CB_ID :
+ hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation
+ completion callback */
+ break;
- case HAL_HASH_ERROR_CB_ID :
- hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak (surcharged) error callback */
- break;
+ case HAL_HASH_ERROR_CB_ID :
+ hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak (surcharged) error callback */
+ break;
- case HAL_HASH_MSPINIT_CB_ID :
- hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */
- break;
+ case HAL_HASH_MSPINIT_CB_ID :
+ hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */
+ break;
- case HAL_HASH_MSPDEINIT_CB_ID :
- hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
- break;
+ case HAL_HASH_MSPDEINIT_CB_ID :
+ hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
+ break;
- default :
- /* Update the error code */
- hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(HAL_HASH_STATE_RESET == hhash->State)
+ else if (HAL_HASH_STATE_RESET == hhash->State)
{
switch (CallbackID)
{
- case HAL_HASH_MSPINIT_CB_ID :
- hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */
- break;
+ case HAL_HASH_MSPINIT_CB_ID :
+ hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */
+ break;
- case HAL_HASH_MSPDEINIT_CB_ID :
- hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
- break;
+ case HAL_HASH_MSPDEINIT_CB_ID :
+ hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
+ break;
- default :
- /* Update the error code */
- hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
{
- /* Update the error code */
- hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
}
/* Release Lock */
@@ -718,8 +725,8 @@
*/
/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode
- * @brief HASH processing functions using polling mode.
- *
+ * @brief HASH processing functions using polling mode.
+ *
@verbatim
===============================================================================
##### Polling mode HASH processing functions #####
@@ -757,7 +764,8 @@
* @param Timeout Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
}
@@ -784,7 +792,7 @@
*/
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_MD5);
+ return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
}
/**
@@ -797,7 +805,8 @@
* @param Timeout Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
}
@@ -813,7 +822,8 @@
* @param Timeout Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
}
@@ -840,7 +850,7 @@
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA1);
+ return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
}
/**
@@ -853,7 +863,8 @@
* @param Timeout Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
}
@@ -863,8 +874,8 @@
*/
/** @defgroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode
- * @brief HASH processing functions using interrupt mode.
- *
+ * @brief HASH processing functions using interrupt mode.
+ *
@verbatim
===============================================================================
##### Interruption mode HASH processing functions #####
@@ -900,9 +911,10 @@
* @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
{
- return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_MD5);
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
}
/**
@@ -925,7 +937,7 @@
*/
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_MD5);
+ return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
}
/**
@@ -937,9 +949,10 @@
* @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
{
- return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_MD5);
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
}
/**
@@ -952,9 +965,10 @@
* @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
{
- return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA1);
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
}
@@ -978,7 +992,7 @@
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA1);
+ return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
}
/**
@@ -990,9 +1004,10 @@
* @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
{
- return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA1);
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
}
/**
@@ -1025,8 +1040,8 @@
*/
/** @defgroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode
- * @brief HASH processing functions using DMA mode.
- *
+ * @brief HASH processing functions using DMA mode.
+ *
@verbatim
===============================================================================
##### DMA mode HASH processing functions #####
@@ -1077,9 +1092,9 @@
* @param Timeout Timeout value.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
{
- return HASH_Finish(hhash, pOutBuffer, Timeout);
+ return HASH_Finish(hhash, pOutBuffer, Timeout);
}
/**
@@ -1108,9 +1123,9 @@
* @param Timeout Timeout value.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
{
- return HASH_Finish(hhash, pOutBuffer, Timeout);
+ return HASH_Finish(hhash, pOutBuffer, Timeout);
}
/**
@@ -1118,8 +1133,8 @@
*/
/** @defgroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode
- * @brief HMAC processing functions using polling mode.
- *
+ * @brief HMAC processing functions using polling mode.
+ *
@verbatim
===============================================================================
##### Polling mode HMAC processing functions #####
@@ -1149,7 +1164,8 @@
* @param Timeout Timeout value.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout)
{
return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
}
@@ -1167,7 +1183,8 @@
* @param Timeout Timeout value.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout)
{
return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
}
@@ -1178,8 +1195,8 @@
/** @defgroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode
- * @brief HMAC processing functions using interrupt mode.
- *
+ * @brief HMAC processing functions using interrupt mode.
+ *
@verbatim
===============================================================================
##### Interrupt mode HMAC processing functions #####
@@ -1208,7 +1225,8 @@
* @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
{
return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
}
@@ -1225,7 +1243,8 @@
* @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
{
return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
}
@@ -1237,8 +1256,8 @@
/** @defgroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
- * @brief HMAC processing functions using DMA modes.
- *
+ * @brief HMAC processing functions using DMA modes.
+ *
@verbatim
===============================================================================
##### DMA mode HMAC processing functions #####
@@ -1313,8 +1332,8 @@
*/
/** @defgroup HASH_Exported_Functions_Group8 Peripheral states functions
- * @brief Peripheral State functions.
- *
+ * @brief Peripheral State functions.
+ *
@verbatim
===============================================================================
##### Peripheral State methods #####
@@ -1381,7 +1400,7 @@
* must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long.
* @retval None
*/
-void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer)
+void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer)
{
uint32_t mem_ptr = (uint32_t)pMemBuffer;
uint32_t csr_ptr = (uint32_t)HASH->CSR;
@@ -1391,20 +1410,21 @@
UNUSED(hhash);
/* Save IMR register content */
- *(uint32_t*)(mem_ptr) = READ_BIT(HASH->IMR,HASH_IT_DINI|HASH_IT_DCI);
- mem_ptr+=4U;
+ *(uint32_t *)(mem_ptr) = READ_BIT(HASH->IMR, HASH_IT_DINI | HASH_IT_DCI);
+ mem_ptr += 4U;
/* Save STR register content */
- *(uint32_t*)(mem_ptr) = READ_BIT(HASH->STR,HASH_STR_NBLW);
- mem_ptr+=4U;
+ *(uint32_t *)(mem_ptr) = READ_BIT(HASH->STR, HASH_STR_NBLW);
+ mem_ptr += 4U;
/* Save CR register content */
- *(uint32_t*)(mem_ptr) = READ_BIT(HASH->CR,HASH_CR_DMAE|HASH_CR_DATATYPE|HASH_CR_MODE|HASH_CR_ALGO|HASH_CR_LKEY|HASH_CR_MDMAT);
- mem_ptr+=4U;
+ *(uint32_t *)(mem_ptr) = READ_BIT(HASH->CR, HASH_CR_DMAE | HASH_CR_DATATYPE | HASH_CR_MODE | HASH_CR_ALGO |
+ HASH_CR_LKEY | HASH_CR_MDMAT);
+ mem_ptr += 4U;
/* By default, save all CSRs registers */
- for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0U; i--)
+ for (i = HASH_NUMBER_OF_CSR_REGISTERS; i > 0U; i--)
{
- *(uint32_t*)(mem_ptr) = *(uint32_t*)(csr_ptr);
- mem_ptr+=4U;
- csr_ptr+=4U;
+ *(uint32_t *)(mem_ptr) = *(uint32_t *)(csr_ptr);
+ mem_ptr += 4U;
+ csr_ptr += 4U;
}
}
@@ -1421,7 +1441,7 @@
* beforehand).
* @retval None
*/
-void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer)
+void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer)
{
uint32_t mem_ptr = (uint32_t)pMemBuffer;
uint32_t csr_ptr = (uint32_t)HASH->CSR;
@@ -1431,25 +1451,25 @@
UNUSED(hhash);
/* Restore IMR register content */
- WRITE_REG(HASH->IMR, (*(uint32_t*)(mem_ptr)));
- mem_ptr+=4U;
+ WRITE_REG(HASH->IMR, (*(uint32_t *)(mem_ptr)));
+ mem_ptr += 4U;
/* Restore STR register content */
- WRITE_REG(HASH->STR, (*(uint32_t*)(mem_ptr)));
- mem_ptr+=4U;
+ WRITE_REG(HASH->STR, (*(uint32_t *)(mem_ptr)));
+ mem_ptr += 4U;
/* Restore CR register content */
- WRITE_REG(HASH->CR, (*(uint32_t*)(mem_ptr)));
- mem_ptr+=4U;
+ WRITE_REG(HASH->CR, (*(uint32_t *)(mem_ptr)));
+ mem_ptr += 4U;
/* Reset the HASH processor before restoring the Context
Swap Registers (CSR) */
__HAL_HASH_INIT();
/* By default, restore all CSR registers */
- for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0U; i--)
+ for (i = HASH_NUMBER_OF_CSR_REGISTERS; i > 0U; i--)
{
- WRITE_REG((*(uint32_t*)(csr_ptr)), (*(uint32_t*)(mem_ptr)));
- mem_ptr+=4U;
- csr_ptr+=4U;
+ WRITE_REG((*(uint32_t *)(csr_ptr)), (*(uint32_t *)(mem_ptr)));
+ mem_ptr += 4U;
+ csr_ptr += 4U;
}
}
@@ -1492,7 +1512,7 @@
else
{
- /* Make sure there is enough time to suspend the processing */
+ /* Make sure there is enough time to suspend the processing */
tmp_remaining_DMATransferSize_inWords = ((DMA_Channel_TypeDef *)hhash->hdmain->Instance)->CNDTR;
if (tmp_remaining_DMATransferSize_inWords <= HASH_DMA_SUSPENSION_WORDS_LIMIT)
@@ -1505,7 +1525,7 @@
/* Wait for BUSY flag to be reset */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_TIMEOUT;
}
if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET)
@@ -1516,7 +1536,7 @@
/* Wait for BUSY flag to be set */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, RESET, HASH_TIMEOUTVALUE) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_TIMEOUT;
}
/* Disable DMA channel */
/* Note that the Abort function will
@@ -1524,13 +1544,13 @@
- Unlock
- Set the State
*/
- if (HAL_DMA_Abort(hhash->hdmain) !=HAL_OK)
+ if (HAL_DMA_Abort(hhash->hdmain) != HAL_OK)
{
return HAL_ERROR;
}
/* Clear DMAE bit */
- CLEAR_BIT(HASH->CR,HASH_CR_DMAE);
+ CLEAR_BIT(HASH->CR, HASH_CR_DMAE);
/* Wait for BUSY flag to be reset */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
@@ -1564,19 +1584,22 @@
{
/* Compute how many words were supposed to be transferred by DMA */
- tmp_initial_DMATransferSize_inWords = (((hhash->HashInCount%4U)!=0U) ? ((hhash->HashInCount+3U)/4U): (hhash->HashInCount/4U));
+ tmp_initial_DMATransferSize_inWords = (((hhash->HashInCount % 4U) != 0U) ? \
+ ((hhash->HashInCount + 3U) / 4U) : (hhash->HashInCount / 4U));
- /* If discrepancy between the number of words reported by DMA Peripheral and the numbers of words entered as reported
- by HASH Peripheral, correct it */
+ /* If discrepancy between the number of words reported by DMA Peripheral and
+ the numbers of words entered as reported by HASH Peripheral, correct it */
/* tmp_words_already_pushed reflects the number of words that were already pushed before
the start of DMA transfer (multi-buffer processing case) */
tmp_words_already_pushed = hhash->NbWordsAlreadyPushed;
- if (((tmp_words_already_pushed + tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) %16U) != HASH_NBW_PUSHED())
+ if (((tmp_words_already_pushed + tmp_initial_DMATransferSize_inWords - \
+ tmp_remaining_DMATransferSize_inWords) % 16U) != HASH_NBW_PUSHED())
{
tmp_remaining_DMATransferSize_inWords--; /* one less word to be transferred again */
}
- /* Accordingly, update the input pointer that points at the next word to be transferred to the Peripheral by DMA */
+ /* Accordingly, update the input pointer that points at the next word to be
+ transferred to the Peripheral by DMA */
hhash->pHashInBuffPtr += 4U * (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ;
/* And store in HashInCount the remaining size to transfer (in bytes) */
@@ -1596,7 +1619,7 @@
* @brief Return the HASH handle error code.
* @param hhash pointer to a HASH_HandleTypeDef structure.
* @retval HASH Error Code
-*/
+ */
uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash)
{
/* Return HASH Error Code */
@@ -1624,10 +1647,10 @@
*/
static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
{
- HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ HASH_HandleTypeDef *hhash = (HASH_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
uint32_t inputaddr;
uint32_t buffersize;
- HAL_StatusTypeDef status ;
+ HAL_StatusTypeDef status = HAL_OK;
if (hhash->State != HAL_HASH_STATE_SUSPENDED)
{
@@ -1726,19 +1749,21 @@
}
}
- /* Configure the Number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(buffersize);
+ /* Configure the Number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(buffersize);
- /* Set the HASH DMA transfert completion call back */
+ /* Set the HASH DMA transfer completion call back */
hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
- /* Enable the DMA In DMA Stream */
- status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((buffersize %4U)!=0U) ? ((buffersize+(4U-(buffersize %4U)))/4U):(buffersize/4U)));
+ /* Enable the DMA In DMA channel */
+ status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \
+ (((buffersize % 4U) != 0U) ? ((buffersize + (4U - (buffersize % 4U))) / 4U) : \
+ (buffersize / 4U)));
- /* Enable DMA requests */
- SET_BIT(HASH->CR, HASH_CR_DMAE);
+ /* Enable DMA requests */
+ SET_BIT(HASH->CR, HASH_CR_DMAE);
- /* Return function status */
+ /* Return function status */
if (status != HAL_OK)
{
/* Update HASH state machine to error */
@@ -1747,9 +1772,9 @@
else
{
/* Change HASH state */
- hhash->State = HAL_HASH_STATE_READY;
+ hhash->State = HAL_HASH_STATE_BUSY;
}
- }
+ }
}
return;
@@ -1764,14 +1789,14 @@
*/
static void HASH_DMAError(DMA_HandleTypeDef *hdma)
{
- HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ HASH_HandleTypeDef *hhash = (HASH_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
if (hhash->State != HAL_HASH_STATE_SUSPENDED)
{
hhash->ErrorCode |= HAL_HASH_ERROR_DMA;
/* Set HASH state to ready to prevent any blocking issue in user code
present in HAL_HASH_ErrorCallback() */
- hhash->State= HAL_HASH_STATE_READY;
+ hhash->State = HAL_HASH_STATE_READY;
/* Set HASH handle status to error */
hhash->Status = HAL_ERROR;
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
@@ -1801,15 +1826,15 @@
uint32_t buffercounter;
__IO uint32_t inputaddr = (uint32_t) pInBuffer;
- for(buffercounter = 0U; buffercounter < Size; buffercounter+=4U)
+ for (buffercounter = 0U; buffercounter < Size; buffercounter += 4U)
{
/* Write input data 4 bytes at a time */
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4U;
+ HASH->DIN = *(uint32_t *)inputaddr;
+ inputaddr += 4U;
/* If the suspension flag has been raised and if the processing is not about
to end, suspend processing */
- if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4U) < Size))
+ if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter + 4U) < Size))
{
/* Wait for DINIS = 1, which occurs when 16 32-bit locations are free
in the input buffer */
@@ -1823,14 +1848,14 @@
if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2))
{
/* Save current reading and writing locations of Input and Output buffers */
- hhash->pHashInBuffPtr = (uint8_t *)inputaddr;
+ hhash->pHashInBuffPtr = (uint8_t *)inputaddr;
/* Save the number of bytes that remain to be processed at this point */
hhash->HashInCount = Size - (buffercounter + 4U);
}
else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
{
/* Save current reading and writing locations of Input and Output buffers */
- hhash->pHashKeyBuffPtr = (uint8_t *)inputaddr;
+ hhash->pHashKeyBuffPtr = (uint8_t *)inputaddr;
/* Save the number of bytes that remain to be processed at this point */
hhash->HashKeyCount = Size - (buffercounter + 4U);
}
@@ -1864,63 +1889,63 @@
{
uint32_t msgdigest = (uint32_t)pMsgDigest;
- switch(Size)
+ switch (Size)
{
/* Read the message digest */
case 16: /* MD5 */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
- break;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[0]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[1]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[2]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[3]);
+ break;
case 20: /* SHA1 */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
- break;
- case 28: /* SHA224 */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
- break;
- case 32: /* SHA256 */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]);
- break;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[0]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[1]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[2]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[3]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[4]);
+ break;
+ case 28: /* SHA224 */
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[0]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[1]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[2]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[3]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[4]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
+ break;
+ case 32: /* SHA256 */
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[0]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[1]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[2]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[3]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[4]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[7]);
+ break;
default:
- break;
+ break;
}
}
@@ -1934,19 +1959,20 @@
* @param Timeout Timeout duration.
* @retval HAL status
*/
-static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status,
+ uint32_t Timeout)
{
uint32_t tickstart = HAL_GetTick();
/* Wait until flag is set */
- if(Status == RESET)
+ if (Status == RESET)
{
- while(__HAL_HASH_GET_FLAG(Flag) == RESET)
+ while (__HAL_HASH_GET_FLAG(Flag) == RESET)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Set State to Ready to be able to restart later on */
hhash->State = HAL_HASH_STATE_READY;
@@ -1963,12 +1989,12 @@
}
else
{
- while(__HAL_HASH_GET_FLAG(Flag) != RESET)
+ while (__HAL_HASH_GET_FLAG(Flag) != RESET)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Set State to Ready to be able to restart later on */
hhash->State = HAL_HASH_STATE_READY;
@@ -2001,10 +2027,10 @@
if (hhash->State == HAL_HASH_STATE_BUSY)
{
/* ITCounter must not be equal to 0 at this point. Report an error if this is the case. */
- if(hhash->HashITCounter == 0U)
+ if (hhash->HashITCounter == 0U)
{
/* Disable Interrupts */
- __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+ __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
/* HASH state set back to Ready to prevent any issue in user code
present in HAL_HASH_ErrorCallback() */
hhash->State = HAL_HASH_STATE_READY;
@@ -2012,9 +2038,9 @@
}
else if (hhash->HashITCounter == 1U)
{
- /* This is the first call to HASH_IT, the first input data are about to be
- entered in the Peripheral. A specific processing is carried out at this point to
- start-up the processing. */
+ /* This is the first call to HASH_IT, the first input data are about to be
+ entered in the Peripheral. A specific processing is carried out at this point to
+ start-up the processing. */
hhash->HashITCounter = 2U;
}
else
@@ -2031,7 +2057,7 @@
HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH());
/* Disable Interrupts */
- __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+ __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_READY;
/* Reset HASH state machine */
@@ -2052,10 +2078,10 @@
/* If the suspension flag has been raised and if the processing is not about
to end, suspend processing */
- if ( (hhash->HashInCount != 0U) && (hhash->SuspendRequest == HAL_HASH_SUSPEND))
+ if ((hhash->HashInCount != 0U) && (hhash->SuspendRequest == HAL_HASH_SUSPEND))
{
/* Disable Interrupts */
- __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+ __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
/* Reset SuspendRequest */
hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
@@ -2066,7 +2092,7 @@
return HAL_OK;
}
- /* Enter input data in the Peripheral thru HASH_Write_Block_Data() call and
+ /* Enter input data in the Peripheral through HASH_Write_Block_Data() call and
check whether the digest calculation has been triggered */
if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED)
{
@@ -2084,7 +2110,7 @@
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
{
/* Disable Interrupts */
- __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+ __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
return HAL_TIMEOUT;
}
/* Initialization start for HMAC STEP 2 */
@@ -2092,7 +2118,8 @@
__HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize); /* Set NBLW for the input message */
hhash->HashInCount = hhash->HashBuffSize; /* Set the input data size (in bytes) */
hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr; /* Set the input data address */
- hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start of a new phase */
+ hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start
+ of a new phase */
__HAL_HASH_ENABLE_IT(HASH_IT_DINI); /* Enable IT (was disabled in HASH_Write_Block_Data) */
}
else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
@@ -2101,7 +2128,7 @@
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
{
/* Disable Interrupts */
- __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+ __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
return HAL_TIMEOUT;
}
/* Initialization start for HMAC STEP 3 */
@@ -2109,7 +2136,8 @@
__HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); /* Set NBLW for the key */
hhash->HashInCount = hhash->Init.KeySize; /* Set the key size (in bytes) */
hhash->pHashInBuffPtr = hhash->Init.pKey; /* Set the key address */
- hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start of a new phase */
+ hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start
+ of a new phase */
__HAL_HASH_ENABLE_IT(HASH_IT_DINI); /* Enable IT (was disabled in HASH_Write_Block_Data) */
}
else
@@ -2143,28 +2171,28 @@
uint32_t ret = HASH_DIGEST_CALCULATION_NOT_STARTED;
/* If there are more than 64 bytes remaining to be entered */
- if(hhash->HashInCount > 64U)
+ if (hhash->HashInCount > 64U)
{
inputaddr = (uint32_t)hhash->pHashInBuffPtr;
/* Write the Input block in the Data IN register
(16 32-bit words, or 64 bytes are entered) */
- for(buffercounter = 0U; buffercounter < 64U; buffercounter+=4U)
+ for (buffercounter = 0U; buffercounter < 64U; buffercounter += 4U)
{
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4U;
+ HASH->DIN = *(uint32_t *)inputaddr;
+ inputaddr += 4U;
}
/* If this is the start of input data entering, an additional word
must be entered to start up the HASH processing */
- if(hhash->HashITCounter == 2U)
+ if (hhash->HashITCounter == 2U)
{
- HASH->DIN = *(uint32_t*)inputaddr;
- if(hhash->HashInCount >= 68U)
+ HASH->DIN = *(uint32_t *)inputaddr;
+ if (hhash->HashInCount >= 68U)
{
/* There are still data waiting to be entered in the Peripheral.
Decrement buffer counter and set pointer to the proper
memory location for the next data entering round. */
hhash->HashInCount -= 68U;
- hhash->pHashInBuffPtr+= 68U;
+ hhash->pHashInBuffPtr += 68U;
}
else
{
@@ -2178,7 +2206,7 @@
Decrement buffer counter and set pointer to the proper
memory location for the next data entering round.*/
hhash->HashInCount -= 64U;
- hhash->pHashInBuffPtr+= 64U;
+ hhash->pHashInBuffPtr += 64U;
}
}
else
@@ -2194,10 +2222,10 @@
__HAL_HASH_DISABLE_IT(HASH_IT_DINI);
/* Write the Input block in the Data IN register */
- for(buffercounter = 0U; buffercounter < ((inputcounter+3U)/4U); buffercounter++)
+ for (buffercounter = 0U; buffercounter < ((inputcounter + 3U) / 4U); buffercounter++)
{
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4U;
+ HASH->DIN = *(uint32_t *)inputaddr;
+ inputaddr += 4U;
}
if (hhash->Accumulation == 1U)
@@ -2211,9 +2239,9 @@
hhash->State = HAL_HASH_STATE_READY;
/* Call Input data transfer complete call back */
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
- hhash->InCpltCallback(hhash);
+ hhash->InCpltCallback(hhash);
#else
- HAL_HASH_InCpltCallback(hhash);
+ HAL_HASH_InCpltCallback(hhash);
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
}
else
@@ -2243,7 +2271,8 @@
static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout)
{
/* Ensure first that Phase is correct */
- if ((hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_1) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_2) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_3))
+ if ((hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_1) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_2)
+ && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_3))
{
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_READY;
@@ -2340,11 +2369,11 @@
}
- /* HMAC Step 3 processing.
- After phase check, HMAC_Processing() may
- - directly start up from this point in resumption case
- if the same Step 3 processing was suspended previously
- - or fall through from the Step 2 processing carried out hereabove */
+ /* HMAC Step 3 processing.
+ After phase check, HMAC_Processing() may
+ - directly start up from this point in resumption case
+ if the same Step 3 processing was suspended previously
+ - or fall through from the Step 2 processing carried out hereabove */
if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)
{
/************************** STEP 3 ******************************************/
@@ -2372,7 +2401,7 @@
__HAL_HASH_START_DIGEST();
/* Wait for DCIS flag to be set */
- if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -2384,14 +2413,14 @@
hhash->Phase = HAL_HASH_PHASE_READY;
}
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
- /* Process Unlock */
- __HAL_UNLOCK(hhash);
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
- /* Return function status */
- return HAL_OK;
+ /* Return function status */
+ return HAL_OK;
}
@@ -2407,7 +2436,8 @@
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
-HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
+HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout, uint32_t Algorithm)
{
uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */
uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */
@@ -2415,7 +2445,7 @@
/* Initiate HASH processing in case of start or resumption */
-if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
/* Check input parameters */
if ((pInBuffer == NULL) || (pOutBuffer == NULL))
@@ -2428,13 +2458,13 @@
__HAL_LOCK(hhash);
/* Check if initialization phase has not been already performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ if (hhash->Phase == HAL_HASH_PHASE_READY)
{
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_BUSY;
/* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
- MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT);
/* Configure the number of valid bits in last word of the message */
__HAL_HASH_SET_NBVALIDBITS(Size);
@@ -2556,7 +2586,7 @@
}
/* Initiate HASH processing in case of start or resumption */
-if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
/* Check input parameters */
if ((pInBuffer == NULL) || (Size == 0U))
@@ -2565,7 +2595,7 @@
return HAL_ERROR;
}
- /* Process Locked */
+ /* Process Locked */
__HAL_LOCK(hhash);
/* If resuming the HASH processing */
@@ -2592,10 +2622,10 @@
Size_tmp = Size; /* Size_tmp contains the input data size in bytes */
/* Check if initialization phase has already be performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ if (hhash->Phase == HAL_HASH_PHASE_READY)
{
/* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
- MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT);
}
/* Set the phase */
@@ -2659,7 +2689,7 @@
}
/* Initiate HASH processing in case of start or resumption */
- if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
/* Check input parameters */
if ((pInBuffer == NULL) || (Size == 0U))
@@ -2668,7 +2698,7 @@
return HAL_ERROR;
}
- /* Process Locked */
+ /* Process Locked */
__HAL_LOCK(hhash);
/* If resuming the HASH processing */
@@ -2683,15 +2713,15 @@
hhash->State = HAL_HASH_STATE_BUSY;
/* Check if initialization phase has already be performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ if (hhash->Phase == HAL_HASH_PHASE_READY)
{
/* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
- MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT);
hhash->HashITCounter = 1;
}
else
{
- hhash->HashITCounter = 3; /* 'cruise-speed' reached during a previous buffer processing */
+ hhash->HashITCounter = 3; /* 'cruise-speed' reached during a previous buffer processing */
}
/* Set the phase */
@@ -2701,13 +2731,13 @@
fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set.
Therefore, first words are manually entered until DINIS raises, or until there
is not more data to enter. */
- while((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 0U))
+ while ((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 0U))
{
/* Write input data 4 bytes at a time */
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4U;
- SizeVar-=4U;
+ HASH->DIN = *(uint32_t *)inputaddr;
+ inputaddr += 4U;
+ SizeVar -= 4U;
}
/* If DINIS is still not set or if all the data have been fed, stop here */
@@ -2728,10 +2758,10 @@
to be fed to the Peripheral */
hhash->pHashInBuffPtr = (uint8_t *)inputaddr; /* Points at data which will be fed to the Peripheral at
the next interruption */
- /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain
- the information describing where the HASH process is stopped.
- These variables are used later on to resume the HASH processing at the
- correct location. */
+ /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain
+ the information describing where the HASH process is stopped.
+ These variables are used later on to resume the HASH processing at the
+ correct location. */
}
@@ -2768,16 +2798,17 @@
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
-HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm)
+HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Algorithm)
{
- HAL_HASH_StateTypeDef State_tmp = hhash->State;
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
__IO uint32_t inputaddr = (uint32_t) pInBuffer;
uint32_t polling_step = 0U;
uint32_t initialization_skipped = 0U;
uint32_t SizeVar = Size;
/* If State is ready or suspended, start or resume IT-based HASH processing */
-if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
/* Check input parameters */
if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL))
@@ -2796,23 +2827,23 @@
hhash->HashITCounter = 1;
/* Check if initialization phase has already be performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ if (hhash->Phase == HAL_HASH_PHASE_READY)
{
/* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
- MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT);
/* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(SizeVar);
+ __HAL_HASH_SET_NBVALIDBITS(SizeVar);
hhash->HashInCount = SizeVar; /* Counter used to keep track of number of data
to be fed to the Peripheral */
hhash->pHashInBuffPtr = pInBuffer; /* Points at data which will be fed to the Peripheral at
the next interruption */
- /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain
- the information describing where the HASH process is stopped.
- These variables are used later on to resume the HASH processing at the
- correct location. */
+ /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain
+ the information describing where the HASH process is stopped.
+ These variables are used later on to resume the HASH processing at the
+ correct location. */
hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
}
@@ -2824,17 +2855,17 @@
/* Set the phase */
hhash->Phase = HAL_HASH_PHASE_PROCESS;
- /* If DINIS is equal to 0 (for example if an incomplete block has been previously
- fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set.
- Therefore, first words are manually entered until DINIS raises. */
- while((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 3U))
+ /* If DINIS is equal to 0 (for example if an incomplete block has been previously
+ fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set.
+ Therefore, first words are manually entered until DINIS raises. */
+ while ((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 3U))
{
polling_step = 1U; /* note that some words are entered before enabling the interrupt */
/* Write input data 4 bytes at a time */
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4U;
- SizeVar-=4U;
+ HASH->DIN = *(uint32_t *)inputaddr;
+ inputaddr += 4U;
+ SizeVar -= 4U;
}
if (polling_step == 1U)
@@ -2846,7 +2877,7 @@
hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
/* Start the Digest calculation */
- __HAL_HASH_START_DIGEST();
+ __HAL_HASH_START_DIGEST();
/* Process Unlock */
__HAL_UNLOCK(hhash);
@@ -2863,7 +2894,8 @@
Update HashInCount and pHashInBuffPtr accordingly. */
hhash->HashInCount = SizeVar;
hhash->pHashInBuffPtr = (uint8_t *)inputaddr;
- __HAL_HASH_SET_NBVALIDBITS(SizeVar); /* Update the configuration of the number of valid bits in last word of the message */
+ /* Update the configuration of the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(SizeVar);
hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
if (initialization_skipped == 1U)
{
@@ -2875,11 +2907,11 @@
/* DINIS is not set but it remains a few data to enter (not enough for a full word).
Manually enter the last bytes before enabling DCIE. */
__HAL_HASH_SET_NBVALIDBITS(SizeVar);
- HASH->DIN = *(uint32_t*)inputaddr;
+ HASH->DIN = *(uint32_t *)inputaddr;
- /* Start the Digest calculation */
+ /* Start the Digest calculation */
hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
- __HAL_HASH_START_DIGEST();
+ __HAL_HASH_START_DIGEST();
/* Process Unlock */
__HAL_UNLOCK(hhash);
@@ -2896,7 +2928,7 @@
__HAL_UNLOCK(hhash);
/* Enable Interrupts */
- __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+ __HAL_HASH_ENABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
/* Return function status */
return HAL_OK;
@@ -2936,15 +2968,15 @@
(case of multi-buffer HASH processing) */
assert_param(IS_HASH_DMA_MULTIBUFFER_SIZE(Size));
#endif /* MDMA defined*/
- /* If State is ready or suspended, start or resume polling-based HASH processing */
-if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ /* If State is ready or suspended, start or resume polling-based HASH processing */
+ if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
/* Check input parameters */
- if ( (pInBuffer == NULL ) || (Size == 0U) ||
- /* Check phase coherency. Phase must be
- either READY (fresh start)
- or PROCESS (multi-buffer HASH management) */
- ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HASH_PROCESSING(hhash)))))
+ if ((pInBuffer == NULL) || (Size == 0U) ||
+ /* Check phase coherency. Phase must be
+ either READY (fresh start)
+ or PROCESS (multi-buffer HASH management) */
+ ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HASH_PROCESSING(hhash)))))
{
hhash->State = HAL_HASH_STATE_READY;
return HAL_ERROR;
@@ -2964,10 +2996,10 @@
If Phase is already set to HAL_HASH_PHASE_PROCESS, this means the
API is processing a new input data message in case of multi-buffer HASH
computation. */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ if (hhash->Phase == HAL_HASH_PHASE_READY)
{
/* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
- MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT);
/* Set the phase */
hhash->Phase = HAL_HASH_PHASE_PROCESS;
@@ -2998,7 +3030,7 @@
}
- /* Set the HASH DMA transfert complete callback */
+ /* Set the HASH DMA transfer complete callback */
hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
/* Set the DMA error callback */
hhash->hdmain->XferErrorCallback = HASH_DMAError;
@@ -3006,8 +3038,10 @@
/* Store number of words already pushed to manage proper DMA processing suspension */
hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED();
- /* Enable the DMA In DMA Stream */
- status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U)));
+ /* Enable the DMA In DMA channel */
+ status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \
+ (((inputSize % 4U) != 0U) ? ((inputSize + (4U - (inputSize % 4U))) / 4U) : \
+ (inputSize / 4U)));
/* Enable DMA requests */
SET_BIT(HASH->CR, HASH_CR_DMAE);
@@ -3038,10 +3072,10 @@
* @param Timeout Timeout value.
* @retval HAL status
*/
-HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
{
- if(hhash->State == HAL_HASH_STATE_READY)
+ if (hhash->State == HAL_HASH_STATE_READY)
{
/* Check parameter */
if (pOutBuffer == NULL)
@@ -3099,15 +3133,17 @@
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
-HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
+HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout, uint32_t Algorithm)
{
- HAL_HASH_StateTypeDef State_tmp = hhash->State;
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
- /* If State is ready or suspended, start or resume polling-based HASH processing */
-if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ /* If State is ready or suspended, start or resume polling-based HASH processing */
+ if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
/* Check input parameters */
- if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL))
+ if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U)
+ || (pOutBuffer == NULL))
{
hhash->State = HAL_HASH_STATE_READY;
return HAL_ERROR;
@@ -3120,28 +3156,34 @@
hhash->State = HAL_HASH_STATE_BUSY;
/* Check if initialization phase has already be performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ if (hhash->Phase == HAL_HASH_PHASE_READY)
{
/* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
- if(hhash->Init.KeySize > 64U)
+ if (hhash->Init.KeySize > 64U)
{
- MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
+ Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
}
else
{
- MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
+ Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
}
/* Set the phase to Step 1 */
hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
/* Resort to hhash internal fields to feed the Peripheral.
Parameters will be updated in case of suspension to contain the proper
information at resumption time. */
- hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */
- hhash->pHashInBuffPtr = pInBuffer; /* Input data address, HMAC_Processing input parameter for Step 2 */
- hhash->HashInCount = Size; /* Input data size, HMAC_Processing input parameter for Step 2 */
- hhash->HashBuffSize = Size; /* Store the input buffer size for the whole HMAC process */
- hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address, HMAC_Processing input parameter for Step 1 and Step 3 */
- hhash->HashKeyCount = hhash->Init.KeySize; /* Key size, HMAC_Processing input parameter for Step 1 and Step 3 */
+ hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */
+ hhash->pHashInBuffPtr = pInBuffer; /* Input data address, HMAC_Processing input
+ parameter for Step 2 */
+ hhash->HashInCount = Size; /* Input data size, HMAC_Processing input
+ parameter for Step 2 */
+ hhash->HashBuffSize = Size; /* Store the input buffer size for the whole HMAC process*/
+ hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address, HMAC_Processing input parameter for Step
+ 1 and Step 3 */
+ hhash->HashKeyCount = hhash->Init.KeySize; /* Key size, HMAC_Processing input parameter for Step 1
+ and Step 3 */
}
/* Carry out HMAC processing */
@@ -3169,15 +3211,17 @@
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
-HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm)
+HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Algorithm)
{
- HAL_HASH_StateTypeDef State_tmp = hhash->State;
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
/* If State is ready or suspended, start or resume IT-based HASH processing */
-if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
/* Check input parameters */
- if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL))
+ if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U)
+ || (pOutBuffer == NULL))
{
hhash->State = HAL_HASH_STATE_READY;
return HAL_ERROR;
@@ -3196,13 +3240,15 @@
if (hhash->Phase == HAL_HASH_PHASE_READY)
{
/* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
- if(hhash->Init.KeySize > 64U)
+ if (hhash->Init.KeySize > 64U)
{
- MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
+ Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
}
else
{
- MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
+ Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
}
/* Resort to hhash internal fields hhash->pHashInBuffPtr and hhash->HashInCount
@@ -3247,7 +3293,7 @@
__HAL_UNLOCK(hhash);
/* Enable Interrupts */
- __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+ __HAL_HASH_ENABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
/* Return function status */
return HAL_OK;
@@ -3282,18 +3328,18 @@
uint32_t inputSize;
HAL_StatusTypeDef status ;
HAL_HASH_StateTypeDef State_tmp = hhash->State;
- /* Make sure the input buffer size (in bytes) is a multiple of 4 when digest calculation
- is disabled (multi-buffer HMAC processing, MDMAT bit to be set) */
- assert_param(IS_HMAC_DMA_MULTIBUFFER_SIZE(hhash, Size));
+ /* Make sure the input buffer size (in bytes) is a multiple of 4 when digest calculation
+ is disabled (multi-buffer HMAC processing, MDMAT bit to be set) */
+ assert_param(IS_HMAC_DMA_MULTIBUFFER_SIZE(hhash, Size));
/* If State is ready or suspended, start or resume DMA-based HASH processing */
-if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
/* Check input parameters */
- if ((pInBuffer == NULL ) || (Size == 0U) || (hhash->Init.pKey == NULL ) || (hhash->Init.KeySize == 0U) ||
- /* Check phase coherency. Phase must be
- either READY (fresh start)
- or one of HMAC PROCESS steps (multi-buffer HASH management) */
- ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HMAC_PROCESSING(hhash)))))
+ if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) ||
+ /* Check phase coherency. Phase must be
+ either READY (fresh start)
+ or one of HMAC PROCESS steps (multi-buffer HASH management) */
+ ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HMAC_PROCESSING(hhash)))))
{
hhash->State = HAL_HASH_STATE_READY;
return HAL_ERROR;
@@ -3306,63 +3352,65 @@
/* If not a case of resumption after suspension */
if (hhash->State == HAL_HASH_STATE_READY)
{
- /* Check whether or not initialization phase has already be performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
- /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits.
- At the same time, ensure MDMAT bit is cleared. */
- if(hhash->Init.KeySize > 64U)
+ /* Check whether or not initialization phase has already be performed */
+ if (hhash->Phase == HAL_HASH_PHASE_READY)
{
- MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+ /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits.
+ At the same time, ensure MDMAT bit is cleared. */
+ if (hhash->Init.KeySize > 64U)
+ {
+ MODIFY_REG(HASH->CR, HASH_CR_MDMAT | HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
+ Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ }
+ else
+ {
+ MODIFY_REG(HASH->CR, HASH_CR_MDMAT | HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
+ Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ }
+ /* Store input aparameters in handle fields to manage steps transition
+ or possible HMAC suspension/resumption */
+ hhash->HashInCount = hhash->Init.KeySize; /* Initial size for first DMA transfer (key size) */
+ hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address */
+ hhash->pHashInBuffPtr = hhash->Init.pKey ; /* First address passed to DMA (key address at Step 1) */
+ hhash->pHashMsgBuffPtr = pInBuffer; /* Input data address */
+ hhash->HashBuffSize = Size; /* input data size (in bytes) */
+
+ /* Set DMA input parameters */
+ inputaddr = (uint32_t)(hhash->Init.pKey); /* Address passed to DMA (start by entering Key message) */
+ inputSize = hhash->Init.KeySize; /* Size for first DMA transfer (in bytes) */
+
+ /* Configure the number of valid bits in last word of the key */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Set the phase to Step 1 */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
+
}
- else
- {
- MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
- }
- /* Store input aparameters in handle fields to manage steps transition
- or possible HMAC suspension/resumption */
- hhash->HashInCount = hhash->Init.KeySize; /* Initial size for first DMA transfer (key size) */
- hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address */
- hhash->pHashInBuffPtr = hhash->Init.pKey ; /* First address passed to DMA (key address at Step 1) */
- hhash->pHashMsgBuffPtr = pInBuffer; /* Input data address */
- hhash->HashBuffSize = Size; /* input data size (in bytes) */
-
- /* Set DMA input parameters */
- inputaddr = (uint32_t)(hhash->Init.pKey); /* Address passed to DMA (start by entering Key message) */
- inputSize = hhash->Init.KeySize; /* Size for first DMA transfer (in bytes) */
-
- /* Configure the number of valid bits in last word of the key */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Set the phase to Step 1 */
- hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
-
- }
else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
- {
- /* Process a new input data message in case of multi-buffer HMAC processing
- (this is not a resumption case) */
+ {
+ /* Process a new input data message in case of multi-buffer HMAC processing
+ (this is not a resumption case) */
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
- /* Save input parameters to be able to manage possible suspension/resumption */
+ /* Save input parameters to be able to manage possible suspension/resumption */
hhash->HashInCount = Size; /* Input message address */
hhash->pHashInBuffPtr = pInBuffer; /* Input message size in bytes */
- /* Set DMA input parameters */
+ /* Set DMA input parameters */
inputaddr = (uint32_t)pInBuffer; /* Input message address */
inputSize = Size; /* Input message size in bytes */
- if (hhash->DigestCalculationDisable == RESET)
- {
- /* This means this is the last buffer of the multi-buffer sequence: DCAL needs to be set. */
- __HAL_HASH_RESET_MDMAT();
- __HAL_HASH_SET_NBVALIDBITS(inputSize);
+ if (hhash->DigestCalculationDisable == RESET)
+ {
+ /* This means this is the last buffer of the multi-buffer sequence: DCAL needs to be set. */
+ __HAL_HASH_RESET_MDMAT();
+ __HAL_HASH_SET_NBVALIDBITS(inputSize);
+ }
}
- }
else
{
/* Phase not aligned with handle READY state */
@@ -3373,7 +3421,7 @@
}
else
{
- /* Resumption case (phase may be Step 1, 2 or 3) */
+ /* Resumption case (phase may be Step 1, 2 or 3) */
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_BUSY;
@@ -3387,7 +3435,7 @@
}
- /* Set the HASH DMA transfert complete callback */
+ /* Set the HASH DMA transfer complete callback */
hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
/* Set the DMA error callback */
hhash->hdmain->XferErrorCallback = HASH_DMAError;
@@ -3395,8 +3443,11 @@
/* Store number of words already pushed to manage proper DMA processing suspension */
hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED();
- /* Enable the DMA In DMA Stream */
- status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U)));
+ /* Enable the DMA In DMA channel */
+ status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \
+ (((inputSize % 4U) != 0U) ? ((inputSize + (4U - (inputSize % 4U))) / 4U) \
+ : (inputSize / 4U)));
+
/* Enable DMA requests */
SET_BIT(HASH->CR, HASH_CR_DMAE);
@@ -3432,6 +3483,3 @@
* @}
*/
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_hash_ex.c b/Src/stm32l4xx_hal_hash_ex.c
index 37f8637..0328dcf 100644
--- a/Src/stm32l4xx_hal_hash_ex.c
+++ b/Src/stm32l4xx_hal_hash_ex.c
@@ -5,7 +5,7 @@
* @brief Extended HASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the HASH peripheral for SHA-224 and SHA-256
- * alogrithms:
+ * algorithms:
* + HASH or HMAC processing in polling mode
* + HASH or HMAC processing in interrupt mode
* + HASH or HMAC processing in DMA mode
@@ -14,6 +14,17 @@
* and SHA-256.
*
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
===============================================================================
##### HASH peripheral extended features #####
@@ -39,17 +50,18 @@
User must resort to HAL_HASHEx_xxx_Accumulate_End() to enter the last one and retrieve as
well the computed digest.
- (##) In interrupt mode, API HAL_HASHEx_xxx_Accumulate_IT() must be called for each input buffer,
+ (##) In interrupt mode, API HAL_HASHEx_xxx_Accumulate_IT() must be called for each input buffer,
except for the last one.
User must resort to HAL_HASHEx_xxx_Accumulate_End_IT() to enter the last one and retrieve as
well the computed digest.
(##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
- (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
- From that point, each buffer can be fed to the Peripheral thru HAL_HASHEx_xxx_Start_DMA() API.
+ (+++) HASH processing: once initialization is done, MDMAT bit must be set through
+ __HAL_HASH_SET_MDMAT() macro.
+ From that point, each buffer can be fed to the Peripheral through HAL_HASHEx_xxx_Start_DMA() API.
Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
- macro then wrap-up the HASH processing in feeding the last input buffer thru the
+ macro then wrap-up the HASH processing in feeding the last input buffer through the
same API HAL_HASHEx_xxx_Start_DMA(). The digest can then be retrieved with a call to
API HAL_HASHEx_xxx_Finish().
@@ -68,17 +80,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -107,8 +108,8 @@
*/
/** @defgroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode
- * @brief HASH extended processing functions using polling mode.
- *
+ * @brief HASH extended processing functions using polling mode.
+ *
@verbatim
===============================================================================
##### Polling mode HASH extended processing functions #####
@@ -147,7 +148,8 @@
* @param Timeout Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
}
@@ -174,7 +176,7 @@
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224);
+ return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
}
/**
@@ -187,7 +189,8 @@
* @param Timeout Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
}
@@ -203,7 +206,8 @@
* @param Timeout Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
}
@@ -230,7 +234,7 @@
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256);
+ return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
}
/**
@@ -243,7 +247,8 @@
* @param Timeout Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
}
@@ -253,8 +258,8 @@
*/
/** @defgroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode
- * @brief HASH extended processing functions using interrupt mode.
- *
+ * @brief HASH extended processing functions using interrupt mode.
+ *
@verbatim
===============================================================================
##### Interruption mode HASH extended processing functions #####
@@ -285,9 +290,10 @@
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
{
- return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224);
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
}
/**
@@ -310,7 +316,7 @@
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224);
+ return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
}
/**
@@ -322,9 +328,10 @@
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
{
- return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224);
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
}
/**
@@ -337,9 +344,10 @@
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
{
- return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256);
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
}
/**
@@ -362,7 +370,7 @@
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256);
+ return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
}
/**
@@ -374,9 +382,10 @@
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
{
- return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256);
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
}
/**
@@ -384,11 +393,11 @@
*/
/** @defgroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
- * @brief HASH extended processing functions using DMA mode.
- *
+ * @brief HASH extended processing functions using DMA mode.
+ *
@verbatim
===============================================================================
- ##### DMA mode HASH extended processing functionss #####
+ ##### DMA mode HASH extended processing functions #####
===============================================================================
[..] This section provides functions allowing to calculate in DMA mode
the hash value using one of the following algorithms:
@@ -440,9 +449,9 @@
* @param Timeout Timeout value.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
{
- return HASH_Finish(hhash, pOutBuffer, Timeout);
+ return HASH_Finish(hhash, pOutBuffer, Timeout);
}
/**
@@ -470,9 +479,9 @@
* @param Timeout Timeout value.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
{
- return HASH_Finish(hhash, pOutBuffer, Timeout);
+ return HASH_Finish(hhash, pOutBuffer, Timeout);
}
/**
@@ -480,8 +489,8 @@
*/
/** @defgroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
- * @brief HMAC extended processing functions using polling mode.
- *
+ * @brief HMAC extended processing functions using polling mode.
+ *
@verbatim
===============================================================================
##### Polling mode HMAC extended processing functions #####
@@ -512,7 +521,8 @@
* @param Timeout Timeout value.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout)
{
return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
}
@@ -530,7 +540,8 @@
* @param Timeout Timeout value.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout)
{
return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
}
@@ -541,8 +552,8 @@
/** @defgroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode
- * @brief HMAC extended processing functions using interruption mode.
- *
+ * @brief HMAC extended processing functions using interruption mode.
+ *
@verbatim
===============================================================================
##### Interrupt mode HMAC extended processing functions #####
@@ -572,7 +583,8 @@
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
{
return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
}
@@ -589,7 +601,8 @@
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
{
return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
}
@@ -603,8 +616,8 @@
/** @defgroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode
- * @brief HMAC extended processing functions using DMA mode.
- *
+ * @brief HMAC extended processing functions using DMA mode.
+ *
@verbatim
===============================================================================
##### DMA mode HMAC extended processing functions #####
@@ -681,8 +694,8 @@
*/
/** @defgroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode
- * @brief HMAC extended processing functions in multi-buffer DMA mode.
- *
+ * @brief HMAC extended processing functions in multi-buffer DMA mode.
+ *
@verbatim
===============================================================================
##### Multi-buffer DMA mode HMAC extended processing functions #####
@@ -1025,6 +1038,3 @@
* @}
*/
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_hcd.c b/Src/stm32l4xx_hal_hcd.c
index 6be75db..aa7534f 100644
--- a/Src/stm32l4xx_hal_hcd.c
+++ b/Src/stm32l4xx_hal_hcd.c
@@ -10,6 +10,17 @@
* + Peripheral Control functions
* + Peripheral State functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -37,17 +48,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -58,7 +58,6 @@
*/
#ifdef HAL_HCD_MODULE_ENABLED
-
#if defined (USB_OTG_FS)
/** @defgroup HCD HCD
@@ -491,7 +490,8 @@
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t i, interrupt;
+ uint32_t i;
+ uint32_t interrupt;
/* Ensure that we are in device mode */
if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
@@ -533,14 +533,19 @@
if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U)
{
+ /* Flush USB Fifo */
+ (void)USB_FlushTxFifo(USBx, 0x10U);
+ (void)USB_FlushRxFifo(USBx);
+
+ /* Restore FS Clock */
+ (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
+
/* Handle Host Port Disconnect Interrupt */
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->DisconnectCallback(hhcd);
#else
HAL_HCD_Disconnect_Callback(hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
-
- (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
}
}
@@ -946,7 +951,8 @@
/**
* @brief Unregister the USB HCD Host Channel Notify URB Change Callback
- * USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
+ * USB HCD Host Channel Notify URB Change Callback is redirected
+ * to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
* @param hhcd HCD handle
* @retval HAL status
*/
@@ -1004,8 +1010,11 @@
HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
{
__HAL_LOCK(hhcd);
- __HAL_HCD_ENABLE(hhcd);
+ /* Enable port power */
(void)USB_DriveVbus(hhcd->Instance, 1U);
+
+ /* Enable global interrupt */
+ __HAL_HCD_ENABLE(hhcd);
__HAL_UNLOCK(hhcd);
return HAL_OK;
@@ -1168,13 +1177,13 @@
if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR)
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ hhcd->hc[ch_num].state = HC_XACTERR;
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_BBERR) == USB_OTG_HCINT_BBERR)
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_BBERR);
hhcd->hc[ch_num].state = HC_BBLERR;
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)
@@ -1183,26 +1192,21 @@
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL)
{
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
- hhcd->hc[ch_num].state = HC_STALL;
- __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL);
+ hhcd->hc[ch_num].state = HC_STALL;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
{
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
- hhcd->hc[ch_num].state = HC_DATATGLERR;
- __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);
+ hhcd->hc[ch_num].state = HC_DATATGLERR;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
{
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
hhcd->hc[ch_num].state = HC_XACTERR;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
- __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
}
else
{
@@ -1211,7 +1215,6 @@
if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR)
{
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR);
}
@@ -1224,7 +1227,6 @@
if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) ||
(hhcd->hc[ch_num].ep_type == EP_TYPE_BULK))
{
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
}
@@ -1269,8 +1271,6 @@
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH)
{
- __HAL_HCD_MASK_HALT_HC_INT(ch_num);
-
if (hhcd->hc[ch_num].state == HC_XFRC)
{
hhcd->hc[ch_num].urb_state = URB_DONE;
@@ -1319,14 +1319,18 @@
/* ... */
}
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH);
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#else
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK)
{
if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)
{
hhcd->hc[ch_num].ErrCnt = 0U;
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) ||
@@ -1334,7 +1338,6 @@
{
hhcd->hc[ch_num].ErrCnt = 0U;
hhcd->hc[ch_num].state = HC_NAK;
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else
@@ -1367,7 +1370,8 @@
if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR)
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ hhcd->hc[ch_num].state = HC_XACTERR;
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)
{
@@ -1376,16 +1380,14 @@
if (hhcd->hc[ch_num].do_ping == 1U)
{
hhcd->hc[ch_num].do_ping = 0U;
- hhcd->hc[ch_num].urb_state = URB_NOTREADY;
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ hhcd->hc[ch_num].urb_state = URB_NOTREADY;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR)
{
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
- (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC)
{
@@ -1397,77 +1399,66 @@
hhcd->hc[ch_num].do_ping = 1U;
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);
}
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
- (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC);
hhcd->hc[ch_num].state = HC_XFRC;
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET)
{
hhcd->hc[ch_num].state = HC_NYET;
hhcd->hc[ch_num].do_ping = 1U;
hhcd->hc[ch_num].ErrCnt = 0U;
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL)
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL);
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
- (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
hhcd->hc[ch_num].state = HC_STALL;
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK)
{
hhcd->hc[ch_num].ErrCnt = 0U;
hhcd->hc[ch_num].state = HC_NAK;
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
{
hhcd->hc[ch_num].state = HC_XACTERR;
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
{
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
- (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
- __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
- __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);
hhcd->hc[ch_num].state = HC_DATATGLERR;
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH)
{
- __HAL_HCD_MASK_HALT_HC_INT(ch_num);
-
if (hhcd->hc[ch_num].state == HC_XFRC)
{
hhcd->hc[ch_num].urb_state = URB_DONE;
if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) ||
(hhcd->hc[ch_num].ep_type == EP_TYPE_INTR))
{
- if (hhcd->Init.dma_enable == 1U)
- {
- if (hhcd->hc[ch_num].xfer_len > 0U)
- {
- num_packets = (hhcd->hc[ch_num].xfer_len + hhcd->hc[ch_num].max_packet - 1U) / hhcd->hc[ch_num].max_packet;
-
- if ((num_packets & 1U) != 0U)
- {
- hhcd->hc[ch_num].toggle_out ^= 1U;
- }
- }
- }
- else
+ if (hhcd->Init.dma_enable == 0U)
{
hhcd->hc[ch_num].toggle_out ^= 1U;
}
+
+ if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[ch_num].xfer_len > 0U))
+ {
+ num_packets = (hhcd->hc[ch_num].xfer_len + hhcd->hc[ch_num].max_packet - 1U) / hhcd->hc[ch_num].max_packet;
+
+ if ((num_packets & 1U) != 0U)
+ {
+ hhcd->hc[ch_num].toggle_out ^= 1U;
+ }
+ }
}
}
else if (hhcd->hc[ch_num].state == HC_NAK)
@@ -1508,7 +1499,12 @@
}
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH);
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#else
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
else
{
@@ -1591,7 +1587,8 @@
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
- __IO uint32_t hprt0, hprt0_dup;
+ __IO uint32_t hprt0;
+ __IO uint32_t hprt0_dup;
/* Handle Host Port Interrupts */
hprt0 = USBx_HPRT0;
@@ -1611,7 +1608,7 @@
HAL_HCD_Connect_Callback(hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
- hprt0_dup |= USB_OTG_HPRT_PCDET;
+ hprt0_dup |= USB_OTG_HPRT_PCDET;
}
/* Check whether Port Enable Changed */
@@ -1684,5 +1681,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_i2c.c b/Src/stm32l4xx_hal_i2c.c
index b05692d..4fa5c10 100644
--- a/Src/stm32l4xx_hal_i2c.c
+++ b/Src/stm32l4xx_hal_i2c.c
@@ -9,6 +9,17 @@
* + IO operation functions
* + Peripheral State and Errors functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -19,7 +30,7 @@
(#) Declare a I2C_HandleTypeDef handle structure, for example:
I2C_HandleTypeDef hi2c;
- (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API:
+ (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
(##) Enable the I2Cx interface clock
(##) I2C pins configuration
(+++) Enable the clock for the I2C GPIOs
@@ -28,7 +39,8 @@
(+++) Configure the I2Cx interrupt priority
(+++) Enable the NVIC I2C IRQ Channel
(##) DMA Configuration if you need to use DMA process
- (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
+ (+++) Declare a DMA_HandleTypeDef handle structure for
+ the transmit or receive channel
(+++) Enable the DMAx interface clock using
(+++) Configure the DMA handle parameters
(+++) Configure the DMA Tx or Rx channel
@@ -39,49 +51,49 @@
(#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
- (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware
- (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API.
+ (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
+ (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
- (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady()
+ (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
(#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
[..]
- (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit()
- (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive()
- (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit()
- (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive()
+ (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
+ (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
+ (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
+ (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
*** Polling mode IO MEM operation ***
=====================================
[..]
- (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write()
- (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read()
+ (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
+ (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
*** Interrupt mode IO operation ***
===================================
[..]
- (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT()
- (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
- (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT()
- (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
- (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT()
- (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
- (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT()
- (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
- (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
- (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
- (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
- (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
+ (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
+ (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+ (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
+ (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+ (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
+ (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+ (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
+ (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+ add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+ (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+ (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
This action will inform Master to generate a Stop condition to discard the communication.
@@ -92,120 +104,135 @@
when a direction change during transfer
[..]
(+) A specific option field manage the different steps of a sequential transfer
- (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
- (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode
+ (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
+ (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in
+ no sequential mode
(++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
and data to transfer without a final stop condition
- (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
- and data to transfer without a final stop condition, an then permit a call the same master sequential interface
- several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT()
- or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA())
+ (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with
+ start condition, address and data to transfer without a final stop condition,
+ an then permit a call the same master sequential interface several times
+ (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
+ or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
(++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
- and with new data to transfer if the direction change or manage only the new data to transfer
+ and with new data to transfer if the direction change or manage only the new data to
+ transfer
if no direction change and without a final stop condition in both cases
(++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
- and with new data to transfer if the direction change or manage only the new data to transfer
+ and with new data to transfer if the direction change or manage only the new data to
+ transfer
if no direction change and with a final stop condition in both cases
- (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
- interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).
- Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
- or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
- or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
- or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
- Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit
+ (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition
+ after several call of the same master sequential interface several times
+ (link with option I2C_FIRST_AND_NEXT_FRAME).
+ Usage can, transfer several bytes one by one using
+ HAL_I2C_Master_Seq_Transmit_IT
+ or HAL_I2C_Master_Seq_Receive_IT
+ or HAL_I2C_Master_Seq_Transmit_DMA
+ or HAL_I2C_Master_Seq_Receive_DMA
+ with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
+ Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or
+ Receive sequence permit to call the opposite interface Receive or Transmit
without stopping the communication and so generate a restart condition.
- (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
+ (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after
+ each call of the same master sequential
interface.
- Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
- or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
- or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
- or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
- Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
+ Usage can, transfer several bytes one by one with a restart with slave address between
+ each bytes using
+ HAL_I2C_Master_Seq_Transmit_IT
+ or HAL_I2C_Master_Seq_Receive_IT
+ or HAL_I2C_Master_Seq_Transmit_DMA
+ or HAL_I2C_Master_Seq_Receive_DMA
+ with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
+ Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic
+ generation of STOP condition.
(+) Different sequential I2C interfaces are listed below:
- (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()
- or using @ref HAL_I2C_Master_Seq_Transmit_DMA()
- (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
- (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT()
- or using @ref HAL_I2C_Master_Seq_Receive_DMA()
- (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
- (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
- (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
- (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT()
- (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can
- add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
- (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback()
- (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT()
- or using @ref HAL_I2C_Slave_Seq_Transmit_DMA()
- (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
- (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT()
- or using @ref HAL_I2C_Slave_Seq_Receive_DMA()
- (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
- (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
- (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
+ (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
+ HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
+ (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and
+ users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+ (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
+ HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
+ (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+ (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+ (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
+ HAL_I2C_DisableListen_IT()
+ (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
+ add their own code to check the Address Match Code and the transmission direction request by master
+ (Write/Read).
+ (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
+ (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
+ HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
+ (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and
+ users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+ (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
+ HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
+ (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+ (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+ add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+ (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
This action will inform Master to generate a Stop condition to discard the communication.
*** Interrupt mode IO MEM operation ***
=======================================
[..]
(+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
- @ref HAL_I2C_Mem_Write_IT()
- (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
+ HAL_I2C_Mem_Write_IT()
+ (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
(+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
- @ref HAL_I2C_Mem_Read_IT()
- (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
- (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+ HAL_I2C_Mem_Read_IT()
+ (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+ add their own code by customization of function pointer HAL_I2C_ErrorCallback()
*** DMA mode IO operation ***
==============================
[..]
(+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
- @ref HAL_I2C_Master_Transmit_DMA()
- (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
+ HAL_I2C_Master_Transmit_DMA()
+ (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
(+) Receive in master mode an amount of data in non-blocking mode (DMA) using
- @ref HAL_I2C_Master_Receive_DMA()
- (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
+ HAL_I2C_Master_Receive_DMA()
+ (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
(+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
- @ref HAL_I2C_Slave_Transmit_DMA()
- (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
+ HAL_I2C_Slave_Transmit_DMA()
+ (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
(+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
- @ref HAL_I2C_Slave_Receive_DMA()
- (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
- (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
- (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
- (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
- (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
+ HAL_I2C_Slave_Receive_DMA()
+ (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+ add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+ (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+ (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
This action will inform Master to generate a Stop condition to discard the communication.
*** DMA mode IO MEM operation ***
=================================
[..]
(+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
- @ref HAL_I2C_Mem_Write_DMA()
- (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
+ HAL_I2C_Mem_Write_DMA()
+ (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
(+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
- @ref HAL_I2C_Mem_Read_DMA()
- (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
- (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+ HAL_I2C_Mem_Read_DMA()
+ (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+ add their own code by customization of function pointer HAL_I2C_ErrorCallback()
*** I2C HAL driver macros list ***
@@ -213,23 +240,23 @@
[..]
Below the list of most used macros in I2C HAL driver.
- (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral
- (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral
- (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
- (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
- (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
- (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
- (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+ (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
+ (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
+ (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
+ (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
+ (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
+ (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
+ (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
*** Callback registration ***
=============================================
[..]
The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()
+ Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
to register an interrupt callback.
[..]
- Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:
+ Function HAL_I2C_RegisterCallback() allows to register following callbacks:
(+) MasterTxCpltCallback : callback for Master transmission end of transfer.
(+) MasterRxCpltCallback : callback for Master reception end of transfer.
(+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
@@ -244,11 +271,11 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
- For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().
+ For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
[..]
- Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default
+ Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
weak function.
- @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) MasterTxCpltCallback : callback for Master transmission end of transfer.
@@ -263,24 +290,24 @@
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
[..]
- For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().
+ For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
[..]
- By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET
+ By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
all callbacks are set to the corresponding weak functions:
- examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().
+ examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when
+ reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
these callbacks are null (not registered beforehand).
- If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()
+ If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
- Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
+ Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
- in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
+ in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
Then, the user first registers the MspInit/MspDeInit user callbacks
- using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()
- or @ref HAL_I2C_Init() function.
+ using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
+ or HAL_I2C_Init() function.
[..]
When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
@@ -290,18 +317,6 @@
(@) You can refer to the I2C HAL driver header file for more useful macros
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -336,28 +351,48 @@
#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */
#define MAX_NBYTE_SIZE 255U
-#define SlaveAddr_SHIFT 7U
-#define SlaveAddr_MSK 0x06U
+#define SLAVE_ADDR_SHIFT 7U
+#define SLAVE_ADDR_MSK 0x06U
/* Private define for @ref PreviousState usage */
-#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */
-#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */
-#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
+ (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
+ (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
+/*!< Mask State define, keep only RX and TX bits */
+#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
+/*!< Default Value */
+#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+ (uint32_t)HAL_I2C_MODE_MASTER))
+/*!< Master Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+ (uint32_t)HAL_I2C_MODE_MASTER))
+/*!< Master Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+ (uint32_t)HAL_I2C_MODE_SLAVE))
+/*!< Slave Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+ (uint32_t)HAL_I2C_MODE_SLAVE))
+/*!< Slave Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+ (uint32_t)HAL_I2C_MODE_MEM))
+/*!< Memory Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+ (uint32_t)HAL_I2C_MODE_MEM))
+/*!< Memory Busy RX, combinaison of State LSB and Mode enum */
/* Private define to centralize the enable/disable of Interrupts */
-#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
-#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
-#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */
+#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with
+ @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with
+ @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT
+ and @ref I2C_XFER_RX_IT */
-#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error and NACK treatment */
-#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */
-#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */
+#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error
+ and NACK treatment */
+#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */
+#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */
/* Private define Sequential Transfer Options default/reset value */
#define I2C_NO_OPTION_FRAME (0xFFFF0000U)
@@ -366,6 +401,9 @@
*/
/* Private macro -------------------------------------------------------------*/
+/* Macro to get remaining data to transfer on DMA side */
+#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__)
+
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -390,24 +428,34 @@
static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
/* Private functions to handle IT transfer */
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
- uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
- uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+ uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
+ uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+ uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
+ uint32_t Tickstart);
/* Private functions for I2C transfer IRQ handler */
-static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
-static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
-static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
-static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources);
/* Private functions to handle flags during polling transfer */
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ uint32_t Tickstart);
/* Private functions to centralize the enable/disable of Interrupts */
static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
@@ -559,7 +607,8 @@
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
/* Configure I2Cx: Dual mode and Own Address2 */
- hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
+ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
+ (hi2c->Init.OwnAddress2Masks << 8));
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
@@ -1065,8 +1114,8 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
- uint32_t Timeout)
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart;
@@ -1097,12 +1146,14 @@
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ I2C_GENERATE_START_WRITE);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_GENERATE_START_WRITE);
}
while (hi2c->XferCount > 0U)
@@ -1132,12 +1183,14 @@
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_NO_STARTSTOP);
}
}
}
@@ -1180,8 +1233,8 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
- uint32_t Timeout)
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart;
@@ -1212,12 +1265,14 @@
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ I2C_GENERATE_START_READ);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_GENERATE_START_READ);
}
while (hi2c->XferCount > 0U)
@@ -1248,12 +1303,14 @@
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_NO_STARTSTOP);
}
}
}
@@ -1294,7 +1351,8 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout)
{
uint32_t tickstart;
@@ -1376,22 +1434,27 @@
hi2c->XferCount--;
}
+ /* Wait until AF flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ /* Clear AF flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
/* Wait until STOP flag is set */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Normal use case for Transmitter mode */
- /* A NACK is generated to confirm the end of transfer */
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- }
- else
- {
- return HAL_ERROR;
- }
+ return HAL_ERROR;
}
/* Clear STOP flag */
@@ -1431,7 +1494,8 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout)
{
uint32_t tickstart;
@@ -1455,6 +1519,7 @@
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
hi2c->XferISR = NULL;
/* Enable Address Acknowledge */
@@ -1497,6 +1562,7 @@
hi2c->pBuffPtr++;
hi2c->XferCount--;
+ hi2c->XferSize--;
}
return HAL_ERROR;
@@ -1509,6 +1575,7 @@
hi2c->pBuffPtr++;
hi2c->XferCount--;
+ hi2c->XferSize--;
}
/* Wait until STOP flag is set */
@@ -1606,7 +1673,8 @@
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
return HAL_OK;
@@ -1627,7 +1695,8 @@
* @param Size Amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size)
{
uint32_t xfermode;
@@ -1675,7 +1744,8 @@
/* Enable ERR, TC, STOP, NACK, RXI interrupt */
/* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
return HAL_OK;
@@ -1724,7 +1794,8 @@
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
return HAL_OK;
@@ -1773,7 +1844,8 @@
/* Enable ERR, TC, STOP, NACK, RXI interrupt */
/* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
return HAL_OK;
@@ -1846,7 +1918,8 @@
hi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+ hi2c->XferSize);
}
else
{
@@ -1906,7 +1979,8 @@
/* Send Slave Address */
/* Set NBYTES to write and generate START condition */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1916,7 +1990,8 @@
process unlock */
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
}
@@ -1990,7 +2065,8 @@
hi2c->hdmarx->XferAbortCallback = NULL;
/* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+ hi2c->XferSize);
}
else
{
@@ -2050,7 +2126,8 @@
/* Send Slave Address */
/* Set NBYTES to read and generate START condition */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_GENERATE_START_READ);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2060,7 +2137,8 @@
process unlock */
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
}
@@ -2118,7 +2196,8 @@
hi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+ hi2c->XferSize);
}
else
{
@@ -2221,7 +2300,8 @@
hi2c->hdmarx->XferAbortCallback = NULL;
/* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+ hi2c->XferSize);
}
else
{
@@ -2374,12 +2454,14 @@
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_NO_STARTSTOP);
}
}
@@ -2474,12 +2556,14 @@
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ I2C_GENERATE_START_READ);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_GENERATE_START_READ);
}
do
@@ -2510,12 +2594,14 @@
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
+ I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_NO_STARTSTOP);
}
}
} while (hi2c->XferCount > 0U);
@@ -2608,7 +2694,8 @@
}
/* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart)
+ != HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2627,7 +2714,8 @@
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
return HAL_OK;
@@ -2719,7 +2807,8 @@
/* Enable ERR, TC, STOP, NACK, RXI interrupt */
/* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
return HAL_OK;
@@ -2792,7 +2881,8 @@
}
/* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart)
+ != HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2813,7 +2903,8 @@
hi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+ hi2c->XferSize);
}
else
{
@@ -2957,7 +3048,8 @@
hi2c->hdmarx->XferAbortCallback = NULL;
/* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+ hi2c->XferSize);
}
else
{
@@ -3028,7 +3120,8 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
+ uint32_t Timeout)
{
uint32_t tickstart;
@@ -3205,9 +3298,11 @@
xfermode = hi2c->XferOptions;
}
- /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+ /* If transfer direction not change and there is no request to start another frame,
+ do not generate Restart Condition */
/* Mean Previous state is same as current state */
- if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
+ (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
{
xferrequest = I2C_NO_STARTSTOP;
}
@@ -3291,9 +3386,11 @@
xfermode = hi2c->XferOptions;
}
- /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+ /* If transfer direction not change and there is no request to start another frame,
+ do not generate Restart Condition */
/* Mean Previous state is same as current state */
- if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
+ (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
{
xferrequest = I2C_NO_STARTSTOP;
}
@@ -3324,7 +3421,8 @@
hi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+ hi2c->XferSize);
}
else
{
@@ -3383,7 +3481,8 @@
/* Send Slave Address */
/* Set NBYTES to write and generate START condition */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -3393,7 +3492,8 @@
process unlock */
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
}
@@ -3453,9 +3553,11 @@
xfermode = hi2c->XferOptions;
}
- /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+ /* If transfer direction not change and there is no request to start another frame,
+ do not generate Restart Condition */
/* Mean Previous state is same as current state */
- if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
+ (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
{
xferrequest = I2C_NO_STARTSTOP;
}
@@ -3539,9 +3641,11 @@
xfermode = hi2c->XferOptions;
}
- /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+ /* If transfer direction not change and there is no request to start another frame,
+ do not generate Restart Condition */
/* Mean Previous state is same as current state */
- if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
+ (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
{
xferrequest = I2C_NO_STARTSTOP;
}
@@ -3572,7 +3676,8 @@
hi2c->hdmarx->XferAbortCallback = NULL;
/* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+ hi2c->XferSize);
}
else
{
@@ -3631,7 +3736,8 @@
/* Send Slave Address */
/* Set NBYTES to read and generate START condition */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_GENERATE_START_READ);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -3641,7 +3747,8 @@
process unlock */
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
}
@@ -3862,7 +3969,8 @@
hi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+ hi2c->XferSize);
}
else
{
@@ -3912,15 +4020,15 @@
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR, STOP, NACK, ADDR interrupts */
I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
-
return HAL_OK;
}
else
@@ -4138,7 +4246,8 @@
hi2c->hdmarx->XferAbortCallback = NULL;
/* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR,
+ (uint32_t)pData, hi2c->XferSize);
}
else
{
@@ -4188,15 +4297,15 @@
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* REnable ADDR interrupt */
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
-
return HAL_OK;
}
else
@@ -4356,7 +4465,8 @@
uint32_t tmperror;
/* I2C Bus error interrupt occurred ------------------------------------*/
- if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
@@ -4365,7 +4475,8 @@
}
/* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
- if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
@@ -4374,7 +4485,8 @@
}
/* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
- if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
@@ -4628,7 +4740,8 @@
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources)
{
uint16_t devaddress;
uint32_t tmpITFlags = ITFlags;
@@ -4636,7 +4749,8 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -4649,7 +4763,8 @@
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
}
- else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
{
/* Remove RXNE flag on temporary variable as read done */
tmpITFlags &= ~I2C_FLAG_RXNE;
@@ -4663,7 +4778,8 @@
hi2c->XferSize--;
hi2c->XferCount--;
}
- else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
{
/* Write data to TXDR */
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
@@ -4674,7 +4790,8 @@
hi2c->XferSize--;
hi2c->XferCount--;
}
- else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
{
@@ -4690,11 +4807,13 @@
hi2c->XferSize = hi2c->XferCount;
if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
{
- I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
+ hi2c->XferOptions, I2C_NO_STARTSTOP);
}
else
{
- I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
+ I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
}
}
@@ -4714,7 +4833,8 @@
}
}
}
- else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
if (hi2c->XferCount == 0U)
{
@@ -4745,7 +4865,8 @@
/* Nothing to do */
}
- if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Master complete process */
I2C_ITMasterCplt(hi2c, tmpITFlags);
@@ -4765,7 +4886,8 @@
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources)
{
uint32_t tmpoptions = hi2c->XferOptions;
uint32_t tmpITFlags = ITFlags;
@@ -4774,13 +4896,15 @@
__HAL_LOCK(hi2c);
/* Check if STOPF is set */
- if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, tmpITFlags);
}
- if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
@@ -4788,8 +4912,9 @@
/* So clear Flag NACKF only */
if (hi2c->XferCount == 0U)
{
- /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+ /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ Warning[Pa134]: left and right operands are identical */
{
/* Call I2C Listen complete process */
I2C_ITListenCplt(hi2c, tmpITFlags);
@@ -4828,7 +4953,8 @@
}
}
}
- else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
{
if (hi2c->XferCount > 0U)
{
@@ -4854,11 +4980,12 @@
{
I2C_ITAddrCplt(hi2c, tmpITFlags);
}
- else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
{
/* Write data to TXDR only if XferCount not reach "0" */
/* A TXIS flag can be set, during STOP treatment */
- /* Check if all data have already been sent */
+ /* Check if all Data have already been sent */
/* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
if (hi2c->XferCount > 0U)
{
@@ -4900,7 +5027,8 @@
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources)
{
uint16_t devaddress;
uint32_t xfermode;
@@ -4908,7 +5036,8 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -4924,7 +5053,8 @@
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
}
- else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
/* Disable TC interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
@@ -4985,7 +5115,8 @@
}
}
}
- else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
if (hi2c->XferCount == 0U)
{
@@ -5011,7 +5142,8 @@
I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
}
}
- else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Master complete process */
I2C_ITMasterCplt(hi2c, ITFlags);
@@ -5035,7 +5167,8 @@
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources)
{
uint32_t tmpoptions = hi2c->XferOptions;
uint32_t treatdmanack = 0U;
@@ -5045,13 +5178,15 @@
__HAL_LOCK(hi2c);
/* Check if STOPF is set */
- if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, ITFlags);
}
- if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
@@ -5065,7 +5200,7 @@
{
if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
{
- if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)
+ if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
{
treatdmanack = 1U;
}
@@ -5077,7 +5212,7 @@
{
if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
{
- if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)
+ if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
{
treatdmanack = 1U;
}
@@ -5086,8 +5221,9 @@
if (treatdmanack == 1U)
{
- /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+ /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ Warning[Pa134]: left and right operands are identical */
{
/* Call I2C Listen complete process */
I2C_ITListenCplt(hi2c, ITFlags);
@@ -5148,7 +5284,8 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
}
}
- else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
{
I2C_ITAddrCplt(hi2c, ITFlags);
}
@@ -5175,8 +5312,9 @@
* @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
- uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+ uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
+ uint32_t Tickstart)
{
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
@@ -5229,8 +5367,9 @@
* @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
- uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+ uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
+ uint32_t Tickstart)
{
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
@@ -5298,7 +5437,7 @@
/* If 10bits addressing mode is selected */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
{
- if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
+ if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
{
slaveaddrcode = ownadd1code;
hi2c->AddrEventCount++;
@@ -5684,7 +5823,7 @@
if (hi2c->hdmatx != NULL)
{
- hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx);
+ hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
}
}
else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
@@ -5694,7 +5833,7 @@
if (hi2c->hdmarx != NULL)
{
- hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx);
+ hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
}
}
else
@@ -6025,7 +6164,8 @@
*/
static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
@@ -6053,7 +6193,8 @@
}
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize) != HAL_OK)
+ if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
+ hi2c->XferSize) != HAL_OK)
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
@@ -6073,7 +6214,8 @@
*/
static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
uint32_t tmpoptions = hi2c->XferOptions;
if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
@@ -6100,7 +6242,8 @@
*/
static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
@@ -6128,7 +6271,8 @@
}
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize) != HAL_OK)
+ if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
+ hi2c->XferSize) != HAL_OK)
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
@@ -6148,10 +6292,11 @@
*/
static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
uint32_t tmpoptions = hi2c->XferOptions;
- if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \
+ if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \
(tmpoptions != I2C_NO_OPTION_FRAME))
{
/* Disable DMA Request */
@@ -6175,7 +6320,8 @@
*/
static void I2C_DMAError(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Disable Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -6192,7 +6338,8 @@
*/
static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Reset AbortCpltCallback */
if (hi2c->hdmatx != NULL)
@@ -6208,11 +6355,12 @@
}
/**
- * @brief This function handles I2C Communication Timeout.
+ * @brief This function handles I2C Communication Timeout. It waits
+ * until a flag is no longer in the specified status.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param Flag Specifies the I2C flag to check.
- * @param Status The new Flag status (SET or RESET).
+ * @param Status The actual Flag status (SET or RESET).
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
@@ -6248,12 +6396,13 @@
* @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ uint32_t Tickstart)
{
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
{
- /* Check if a NACK is detected */
- if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+ /* Check if an error is detected */
+ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
@@ -6285,12 +6434,13 @@
* @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ uint32_t Tickstart)
{
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
{
- /* Check if a NACK is detected */
- if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+ /* Check if an error is detected */
+ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
@@ -6319,12 +6469,13 @@
* @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ uint32_t Tickstart)
{
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
{
- /* Check if a NACK is detected */
- if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+ /* Check if an error is detected */
+ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
@@ -6342,13 +6493,22 @@
}
else
{
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ {
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ hi2c->ErrorCode = HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ }
+
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
@@ -6375,60 +6535,136 @@
}
/**
- * @brief This function handles Acknowledge failed detection during an I2C Communication.
+ * @brief This function handles errors detection during an I2C Communication.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t itflag = hi2c->Instance->ISR;
+ uint32_t error_code = 0;
+ uint32_t tickstart = Tickstart;
+ uint32_t tmp1;
+ HAL_I2C_ModeTypeDef tmp2;
+
+ if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
{
- /* Wait until STOP Flag is reset */
+ /* Clear NACKF Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Wait until STOP Flag is set or timeout occurred */
/* AutoEnd should be initiate after AF */
- while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+ while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
- if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
+ tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
+ tmp2 = hi2c->Mode;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
+ /* In case of I2C still busy, try to regenerate a STOP manually */
+ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
+ (tmp1 != I2C_CR2_STOP) && \
+ (tmp2 != HAL_I2C_MODE_SLAVE))
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;
+
+ /* Update Tick with new reference */
+ tickstart = HAL_GetTick();
+ }
+
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ status = HAL_ERROR;
+ }
+ }
}
}
}
- /* Clear NACKF Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ /* In case STOP Flag is detected, clear it */
+ if (status == HAL_OK)
+ {
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ }
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ error_code |= HAL_I2C_ERROR_AF;
+ status = HAL_ERROR;
+ }
+
+ /* Refresh Content of Status register */
+ itflag = hi2c->Instance->ISR;
+
+ /* Then verify if an additional errors occurs */
+ /* Check if a Bus error occurred */
+ if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
+ {
+ error_code |= HAL_I2C_ERROR_BERR;
+
+ /* Clear BERR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+
+ status = HAL_ERROR;
+ }
+
+ /* Check if an Over-Run/Under-Run error occurred */
+ if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
+ {
+ error_code |= HAL_I2C_ERROR_OVR;
+
+ /* Clear OVR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+
+ status = HAL_ERROR;
+ }
+
+ /* Check if an Arbitration Loss error occurred */
+ if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
+ {
+ error_code |= HAL_I2C_ERROR_ARLO;
+
+ /* Clear ARLO flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+
+ status = HAL_ERROR;
+ }
+
+ if (status != HAL_OK)
+ {
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ hi2c->ErrorCode |= error_code;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
}
- return HAL_OK;
+
+ return status;
}
/**
@@ -6458,12 +6694,16 @@
assert_param(IS_TRANSFER_MODE(Mode));
assert_param(IS_TRANSFER_REQUEST(Request));
+ /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
+ (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
+ (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
+
/* update CR2 register */
- MODIFY_REG(hi2c->Instance->CR2,
+ MODIFY_REG(hi2c->Instance->CR2, \
((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
- (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \
- (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) |
- (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
+ (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
+ I2C_CR2_START | I2C_CR2_STOP)), tmp);
}
/**
@@ -6642,5 +6882,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_i2c_ex.c b/Src/stm32l4xx_hal_i2c_ex.c
index c304bf6..f111b69 100644
--- a/Src/stm32l4xx_hal_i2c_ex.c
+++ b/Src/stm32l4xx_hal_i2c_ex.c
@@ -5,8 +5,21 @@
* @brief I2C Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2C Extended peripheral:
- * + Extended features functions
+ * + Filter Mode Functions
+ * + WakeUp Mode Functions
+ * + FastModePlus Functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### I2C peripheral Extended features #####
@@ -32,18 +45,6 @@
(++) HAL_I2CEx_EnableFastModePlus()
(++) HAL_I2CEx_DisableFastModePlus()
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -71,17 +72,15 @@
* @{
*/
-/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
- * @brief Extended features functions
+/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
+ * @brief Filter Mode Functions
*
@verbatim
===============================================================================
- ##### Extended features functions #####
+ ##### Filter Mode Functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Noise Filters
- (+) Configure Wake Up Feature
- (+) Configure Fast Mode Plus
@endverbatim
* @{
@@ -182,6 +181,23 @@
return HAL_BUSY;
}
}
+/**
+ * @}
+ */
+
+/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
+ * @brief WakeUp Mode Functions
+ *
+@verbatim
+ ===============================================================================
+ ##### WakeUp Mode Functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure Wake Up Feature
+
+@endverbatim
+ * @{
+ */
/**
* @brief Enable I2C wakeup from Stop mode(s).
@@ -260,6 +276,23 @@
return HAL_BUSY;
}
}
+/**
+ * @}
+ */
+
+/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
+ * @brief Fast Mode Plus Functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Fast Mode Plus Functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure Fast Mode Plus
+
+@endverbatim
+ * @{
+ */
/**
* @brief Enable the I2C fast mode plus driving capability.
@@ -318,11 +351,9 @@
/* Disable fast mode plus driving capability for selected pin */
CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
}
-
/**
* @}
*/
-
/**
* @}
*/
@@ -335,5 +366,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_irda.c b/Src/stm32l4xx_hal_irda.c
index bb18e8b..5a65445 100644
--- a/Src/stm32l4xx_hal_irda.c
+++ b/Src/stm32l4xx_hal_irda.c
@@ -11,6 +11,17 @@
* + Peripheral State and Errors functions
* + Peripheral Control functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -40,7 +51,8 @@
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx channel.
(+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+ (+++) Configure the priority and enable the NVIC for the transfer
+ complete interrupt on the DMA Tx/Rx channel.
(#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
the normal or low power mode and the clock prescaler in the hirda handle Init structure.
@@ -113,8 +125,8 @@
allows the user to configure dynamically the driver callbacks.
[..]
- Use Function @ref HAL_IRDA_RegisterCallback() to register a user callback.
- Function @ref HAL_IRDA_RegisterCallback() allows to register following callbacks:
+ Use Function HAL_IRDA_RegisterCallback() to register a user callback.
+ Function HAL_IRDA_RegisterCallback() allows to register following callbacks:
(+) TxHalfCpltCallback : Tx Half Complete Callback.
(+) TxCpltCallback : Tx Complete Callback.
(+) RxHalfCpltCallback : Rx Half Complete Callback.
@@ -129,9 +141,9 @@
and a pointer to the user callback function.
[..]
- Use function @ref HAL_IRDA_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
- @ref HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TxHalfCpltCallback : Tx Half Complete Callback.
@@ -146,13 +158,13 @@
(+) MspDeInitCallback : IRDA MspDeInit.
[..]
- By default, after the @ref HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
+ By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
all callbacks are set to the corresponding weak (surcharged) functions:
- examples @ref HAL_IRDA_TxCpltCallback(), @ref HAL_IRDA_RxHalfCpltCallback().
+ examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_IRDA_Init()
- and @ref HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_IRDA_Init() and @ref HAL_IRDA_DeInit()
+ reset to the legacy weak (surcharged) functions in the HAL_IRDA_Init()
+ and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
@@ -161,8 +173,8 @@
in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user)
MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_IRDA_RegisterCallback() before calling @ref HAL_IRDA_DeInit()
- or @ref HAL_IRDA_Init() function.
+ using HAL_IRDA_RegisterCallback() before calling HAL_IRDA_DeInit()
+ or HAL_IRDA_Init() function.
[..]
When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or
@@ -171,17 +183,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -621,43 +622,45 @@
switch (CallbackID)
{
case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
- hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
break;
case HAL_IRDA_TX_COMPLETE_CB_ID :
- hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */
break;
case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
- hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
break;
case HAL_IRDA_RX_COMPLETE_CB_ID :
- hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */
break;
case HAL_IRDA_ERROR_CB_ID :
- hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */
+ hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_IRDA_ABORT_COMPLETE_CB_ID :
- hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
break;
case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
- hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak
+ AbortTransmitCpltCallback */
break;
case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
- hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+ hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak
+ AbortReceiveCpltCallback */
break;
case HAL_IRDA_MSPINIT_CB_ID :
- hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */
+ hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */
break;
case HAL_IRDA_MSPDEINIT_CB_ID :
- hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */
+ hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */
break;
default :
@@ -727,6 +730,7 @@
While receiving data, transmission should be avoided as the data to be transmitted
could be corrupted.
+ [..]
(#) There are two modes of transfer:
(++) Blocking mode: the communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
@@ -764,28 +768,31 @@
(++) HAL_IRDA_ErrorCallback()
(#) Non-Blocking mode transfers could be aborted using Abort API's :
- (+) HAL_IRDA_Abort()
- (+) HAL_IRDA_AbortTransmit()
- (+) HAL_IRDA_AbortReceive()
- (+) HAL_IRDA_Abort_IT()
- (+) HAL_IRDA_AbortTransmit_IT()
- (+) HAL_IRDA_AbortReceive_IT()
+ (++) HAL_IRDA_Abort()
+ (++) HAL_IRDA_AbortTransmit()
+ (++) HAL_IRDA_AbortReceive()
+ (++) HAL_IRDA_Abort_IT()
+ (++) HAL_IRDA_AbortTransmit_IT()
+ (++) HAL_IRDA_AbortReceive_IT()
(#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
- (+) HAL_IRDA_AbortCpltCallback()
- (+) HAL_IRDA_AbortTransmitCpltCallback()
- (+) HAL_IRDA_AbortReceiveCpltCallback()
+ (++) HAL_IRDA_AbortCpltCallback()
+ (++) HAL_IRDA_AbortTransmitCpltCallback()
+ (++) HAL_IRDA_AbortReceiveCpltCallback()
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
- (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
- and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
- If user wants to abort it, Abort services should be called by user.
- (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
- This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
+ (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
+ in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
+ to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
+ Transfer is kept ongoing on IRDA side.
+ If user wants to abort it, Abort services should be called by user.
+ (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and
+ HAL_IRDA_ErrorCallback() user callback is executed.
@endverbatim
* @{
@@ -793,17 +800,20 @@
/**
* @brief Send an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be sent.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
* @param Timeout Specify timeout value.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint8_t *pdata8bits;
- uint16_t *pdata16bits;
+ const uint8_t *pdata8bits;
+ const uint16_t *pdata16bits;
uint32_t tickstart;
/* Check that a Tx process is not already ongoing */
@@ -820,7 +830,7 @@
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->gState = HAL_IRDA_STATE_BUSY_TX;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
hirda->TxXferSize = Size;
@@ -830,7 +840,7 @@
if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
{
pdata8bits = NULL;
- pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */
+ pdata16bits = (const uint16_t *) pData; /* Derogation R.11.3 */
}
else
{
@@ -879,10 +889,13 @@
/**
* @brief Receive an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @param Timeout Specify timeout value.
* @retval HAL status
*/
@@ -907,7 +920,7 @@
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
hirda->RxXferSize = Size;
@@ -967,13 +980,16 @@
/**
* @brief Send an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be sent.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
if (hirda->gState == HAL_IRDA_STATE_READY)
@@ -1013,10 +1029,13 @@
/**
* @brief Receive an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@@ -1046,11 +1065,28 @@
/* Process Unlocked */
__HAL_UNLOCK(hirda);
- /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
#if defined(USART_CR1_FIFOEN)
- SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ if (hirda->Init.Parity != IRDA_PARITY_NONE)
+ {
+ /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ }
+ else
+ {
+ /* Enable the IRDA Data Register not empty Interrupts */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ }
#else
- SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
+ if (hirda->Init.Parity != IRDA_PARITY_NONE)
+ {
+ /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
+ }
+ else
+ {
+ /* Enable the IRDA Data Register not empty Interrupts */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE);
+ }
#endif /* USART_CR1_FIFOEN */
/* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
@@ -1066,13 +1102,16 @@
/**
* @brief Send an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be sent.
+ * @param pData pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
if (hirda->gState == HAL_IRDA_STATE_READY)
@@ -1141,12 +1180,15 @@
/**
* @brief Receive an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
* @note When the IRDA parity is enabled (PCE = 1), the received data contains
* the parity bit (MSB position).
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@@ -1186,8 +1228,11 @@
/* Process Unlocked */
__HAL_UNLOCK(hirda);
- /* Enable the UART Parity Error Interrupt */
- SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ if (hirda->Init.Parity != IRDA_PARITY_NONE)
+ {
+ /* Enable the UART Parity Error Interrupt */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ }
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
@@ -1278,8 +1323,11 @@
/* Clear the Overrun flag before resuming the Rx transfer*/
__HAL_IRDA_CLEAR_OREFLAG(hirda);
- /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
- SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ if (hirda->Init.Parity != IRDA_PARITY_NONE)
+ {
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ }
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Enable the IRDA DMA Rx request */
@@ -1379,7 +1427,8 @@
{
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
#if defined(USART_CR1_FIFOEN)
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \
+ USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
#else
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
#endif /* USART_CR1_FIFOEN */
@@ -1589,7 +1638,8 @@
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
#if defined(USART_CR1_FIFOEN)
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \
+ USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
#else
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
#endif /* USART_CR1_FIFOEN */
@@ -2281,6 +2331,7 @@
#if defined(USART_PRESC_PRESCALER)
static const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
#endif /* USART_PRESC_PRESCALER */
+ uint32_t pclk;
/* Check the communication parameters */
assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
@@ -2321,38 +2372,41 @@
switch (clocksource)
{
case IRDA_CLOCKSOURCE_PCLK1:
+ pclk = HAL_RCC_GetPCLK1Freq();
#if defined(USART_PRESC_PRESCALER)
- tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
#else
- tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate));
+ tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate));
#endif /* USART_PRESC_PRESCALER */
break;
case IRDA_CLOCKSOURCE_PCLK2:
+ pclk = HAL_RCC_GetPCLK2Freq();
#if defined(USART_PRESC_PRESCALER)
- tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
#else
- tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate));
+ tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate));
#endif /* USART_PRESC_PRESCALER */
break;
case IRDA_CLOCKSOURCE_HSI:
#if defined(USART_PRESC_PRESCALER)
- tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
#else
- tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate));
+ tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate));
#endif /* USART_PRESC_PRESCALER */
break;
case IRDA_CLOCKSOURCE_SYSCLK:
+ pclk = HAL_RCC_GetSysClockFreq();
#if defined(USART_PRESC_PRESCALER)
- tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
#else
- tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), hirda->Init.BaudRate));
+ tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate));
#endif /* USART_PRESC_PRESCALER */
break;
case IRDA_CLOCKSOURCE_LSE:
#if defined(USART_PRESC_PRESCALER)
- tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
#else
- tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate));
+ tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate));
#endif /* USART_PRESC_PRESCALER */
break;
default:
@@ -2363,7 +2417,7 @@
/* USARTDIV must be greater than or equal to 0d16 */
if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
{
- hirda->Instance->BRR = tmpreg;
+ hirda->Instance->BRR = (uint16_t)tmpreg;
}
else
{
@@ -2386,7 +2440,7 @@
/* Initialize the IRDA ErrorCode */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
/* Check if the Transmitter is enabled */
@@ -2421,11 +2475,12 @@
}
/**
- * @brief Handle IRDA Communication Timeout.
+ * @brief Handle IRDA Communication Timeout. It waits
+ * until a flag is no longer in the specified status.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param Flag Specifies the IRDA flag to check.
- * @param Status Flag status (SET or RESET)
+ * @param Status The actual Flag status (SET or RESET)
* @param Tickstart Tick start value
* @param Timeout Timeout duration
* @retval HAL status
@@ -2441,7 +2496,8 @@
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
+ interrupts for the interrupt process */
#if defined(USART_CR1_FIFOEN)
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
#else
@@ -2837,7 +2893,7 @@
*/
static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
{
- uint16_t *tmp;
+ const uint16_t *tmp;
/* Check that a Tx process is ongoing */
if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
@@ -2858,7 +2914,7 @@
{
if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
{
- tmp = (uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */
+ tmp = (const uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */
hirda->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
hirda->pTxBuffPtr += 2U;
}
@@ -2970,4 +3026,4 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Src/stm32l4xx_hal_iwdg.c b/Src/stm32l4xx_hal_iwdg.c
index aea6508..51d1292 100644
--- a/Src/stm32l4xx_hal_iwdg.c
+++ b/Src/stm32l4xx_hal_iwdg.c
@@ -8,6 +8,17 @@
* + Initialization and Start functions
* + IO operation functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### IWDG Generic features #####
@@ -65,13 +76,13 @@
(++) Configure the IWDG prescaler and counter reload value. This reload
value will be loaded in the IWDG counter each time the watchdog is
reloaded, then the IWDG will start counting down from this value.
- (++) Wait for status flags to be reset.
(++) Depending on window parameter:
(+++) If Window Init parameter is same as Window register value,
nothing more is done but reload counter value in order to exit
function with exact time base.
(+++) Else modify Window register. This will automatically reload
watchdog counter.
+ (++) Wait for status flags to be reset.
(#) Then the application program must refresh the IWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
@@ -86,18 +97,6 @@
the reload register
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -121,11 +120,14 @@
/* Status register needs up to 5 LSI clock periods divided by the clock
prescaler to be updated. The number of LSI clock periods is upper-rounded to
6 for the timeout value calculation.
- The timeout value is also calculated using the highest prescaler (256) and
+ The timeout value is calculated using the highest prescaler (256) and
the LSI_VALUE constant. The value of this constant can be changed by the user
to take into account possible LSI clock period variations.
- The timeout value is multiplied by 1000 to be converted in milliseconds. */
-#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE)
+ The timeout value is multiplied by 1000 to be converted in milliseconds.
+ LSI startup time is also considered here by adding LSI_STARTUP_TIME
+ converted in milliseconds. */
+#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
+#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
/**
* @}
*/
@@ -196,11 +198,14 @@
tickstart = HAL_GetTick();
/* Wait for register to be updated */
- while (hiwdg->Instance->SR != 0x00u)
+ while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
{
if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
{
- return HAL_TIMEOUT;
+ if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
+ {
+ return HAL_TIMEOUT;
+ }
}
}
@@ -223,6 +228,7 @@
return HAL_OK;
}
+
/**
* @}
*/
@@ -242,7 +248,6 @@
* @{
*/
-
/**
* @brief Refresh the IWDG.
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
@@ -258,6 +263,7 @@
return HAL_OK;
}
+
/**
* @}
*/
@@ -274,5 +280,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_lcd.c b/Src/stm32l4xx_hal_lcd.c
index aeb68e7..f72887b 100644
--- a/Src/stm32l4xx_hal_lcd.c
+++ b/Src/stm32l4xx_hal_lcd.c
@@ -9,6 +9,16 @@
* + I/O operation methods
* + Peripheral State methods
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -66,17 +76,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -605,5 +604,3 @@
*/
#endif /* STM32L433xx || STM32L443xx || STM32L476xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_lptim.c b/Src/stm32l4xx_hal_lptim.c
index 64a905b..e2b1ee4 100644
--- a/Src/stm32l4xx_hal_lptim.c
+++ b/Src/stm32l4xx_hal_lptim.c
@@ -11,6 +11,17 @@
* + Reading operation functions.
* + Peripheral State functions.
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -96,13 +107,13 @@
The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
[..]
- Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback.
- @ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+ Use Function HAL_LPTIM_RegisterCallback() to register a callback.
+ HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
the Callback ID and a pointer to the user callback function.
[..]
- Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the
+ Use function HAL_LPTIM_UnRegisterCallback() to reset a callback to the
default weak function.
- @ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
[..]
These functions allow to register/unregister following callbacks:
@@ -120,7 +131,7 @@
[..]
By default, after the Init and when the state is HAL_LPTIM_STATE_RESET
all interrupt callbacks are set to the corresponding weak functions:
- examples @ref HAL_LPTIM_TriggerCallback(), @ref HAL_LPTIM_CompareMatchCallback().
+ examples HAL_LPTIM_TriggerCallback(), HAL_LPTIM_CompareMatchCallback().
[..]
Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
@@ -134,7 +145,7 @@
in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
+ using HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
[..]
When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
@@ -143,17 +154,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -253,8 +253,8 @@
assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
- if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
- || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+ if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
@@ -326,8 +326,8 @@
/* Get the LPTIMx CFGR value */
tmpcfgr = hlptim->Instance->CFGR;
- if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
- || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+ if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
}
@@ -357,8 +357,8 @@
}
/* Configure LPTIM external clock polarity and digital filter */
- if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
- || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+ if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
hlptim->Init.UltraLowPowerClock.SampleTime);
@@ -589,7 +589,7 @@
return HAL_TIMEOUT;
}
- /* Change the TIM state*/
+ /* Change the LPTIM state*/
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -741,7 +741,7 @@
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UPDATE);
#endif
- /* Change the TIM state*/
+ /* Change the LPTIM state*/
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -828,7 +828,7 @@
return HAL_TIMEOUT;
}
- /* Change the TIM state*/
+ /* Change the LPTIM state*/
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -980,7 +980,7 @@
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UPDATE);
#endif
- /* Change the TIM state*/
+ /* Change the LPTIM state*/
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1067,7 +1067,7 @@
return HAL_TIMEOUT;
}
- /* Change the TIM state*/
+ /* Change the LPTIM state*/
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1203,7 +1203,7 @@
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
}
- /* Change the TIM state*/
+ /* Change the LPTIM state*/
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -2364,48 +2364,59 @@
switch (CallbackID)
{
case HAL_LPTIM_MSPINIT_CB_ID :
- hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */
+ /* Legacy weak MspInit Callback */
+ hlptim->MspInitCallback = HAL_LPTIM_MspInit;
break;
case HAL_LPTIM_MSPDEINIT_CB_ID :
- hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak Msp DeInit Callback */
+ /* Legacy weak Msp DeInit Callback */
+ hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
break;
case HAL_LPTIM_COMPARE_MATCH_CB_ID :
- hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Legacy weak Compare match Callback */
+ /* Legacy weak Compare match Callback */
+ hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
break;
case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
- hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Legacy weak Auto-reload match Callback */
+ /* Legacy weak Auto-reload match Callback */
+ hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
break;
case HAL_LPTIM_TRIGGER_CB_ID :
- hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* Legacy weak External trigger event detection Callback */
+ /* Legacy weak External trigger event detection Callback */
+ hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
break;
case HAL_LPTIM_COMPARE_WRITE_CB_ID :
- hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Legacy weak Compare register write complete Callback */
+ /* Legacy weak Compare register write complete Callback */
+ hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
break;
case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
- hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Legacy weak Auto-reload register write complete Callback */
+ /* Legacy weak Auto-reload register write complete Callback */
+ hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
break;
case HAL_LPTIM_DIRECTION_UP_CB_ID :
- hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Legacy weak Up-counting direction change Callback */
+ /* Legacy weak Up-counting direction change Callback */
+ hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
break;
case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
- hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Legacy weak Down-counting direction change Callback */
+ /* Legacy weak Down-counting direction change Callback */
+ hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
break;
#if defined(LPTIM_RCR_REP)
case HAL_LPTIM_UPDATE_EVENT_CB_ID :
- hlptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback; /* Legacy weak Update event detection Callback */
+ /* Legacy weak Update event detection Callback */
+ hlptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback;
break;
case HAL_LPTIM_REP_COUNTER_WRITE_CB_ID :
- hlptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback; /* Legacy weak Repetition counter register write complete Callback */
+ /* Legacy weak Repetition counter register write complete Callback */
+ hlptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback;
break;
#endif
@@ -2420,11 +2431,13 @@
switch (CallbackID)
{
case HAL_LPTIM_MSPINIT_CB_ID :
- hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */
+ /* Legacy weak MspInit Callback */
+ hlptim->MspInitCallback = HAL_LPTIM_MspInit;
break;
case HAL_LPTIM_MSPDEINIT_CB_ID :
- hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak Msp DeInit Callback */
+ /* Legacy weak Msp DeInit Callback */
+ hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
break;
default :
@@ -2499,16 +2512,16 @@
static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim)
{
/* Reset the LPTIM callback to the legacy weak callbacks */
- lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Compare match Callback */
- lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Auto-reload match Callback */
- lptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* External trigger event detection Callback */
- lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Compare register write complete Callback */
- lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Auto-reload register write complete Callback */
- lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Up-counting direction change Callback */
- lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Down-counting direction change Callback */
+ lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
+ lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
+ lptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
+ lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
+ lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
+ lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
+ lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
#if defined(LPTIM_RCR_REP)
- lptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback; /* Update event detection Callback */
- lptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback; /* Repetition counter register write complete Callback */
+ lptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback;
+ lptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback;
#endif
}
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
@@ -2552,12 +2565,15 @@
uint32_t tmpCFGR;
uint32_t tmpCMP;
uint32_t tmpARR;
+ uint32_t primask_bit;
uint32_t tmpOR;
#if defined(LPTIM_RCR_REP)
uint32_t tmpRCR;
#endif
- __disable_irq();
+ /* Enter critical section */
+ primask_bit = __get_PRIMASK();
+ __set_PRIMASK(1) ;
/*********** Save LPTIM Config ***********/
/* Save LPTIM source clock */
@@ -2691,7 +2707,8 @@
hlptim->Instance->CFGR = tmpCFGR;
hlptim->Instance->OR = tmpOR;
- __enable_irq();
+ /* Exit critical section: restore previous priority mask */
+ __set_PRIMASK(primask_bit);
}
/**
* @}
@@ -2706,5 +2723,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_ltdc.c b/Src/stm32l4xx_hal_ltdc.c
index 8e27fad..78f82f2 100644
--- a/Src/stm32l4xx_hal_ltdc.c
+++ b/Src/stm32l4xx_hal_ltdc.c
@@ -10,6 +10,17 @@
* + Peripheral Control functions
* + Peripheral State and Errors functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -146,17 +157,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -2159,5 +2159,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_ltdc_ex.c b/Src/stm32l4xx_hal_ltdc_ex.c
index 99181bd..b6fcdf9 100644
--- a/Src/stm32l4xx_hal_ltdc_ex.c
+++ b/Src/stm32l4xx_hal_ltdc_ex.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -145,5 +144,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_mmc.c b/Src/stm32l4xx_hal_mmc.c
index 31ebfc4..585a48e 100644
--- a/Src/stm32l4xx_hal_mmc.c
+++ b/Src/stm32l4xx_hal_mmc.c
@@ -10,6 +10,17 @@
* + Peripheral Control functions
* + MMC card Control functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -193,7 +204,7 @@
The compilation define USE_HAL_MMC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_MMC_RegisterCallback() to register a user callback,
+ Use Functions HAL_MMC_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) TxCpltCallback : callback when a transmission transfer is completed.
(+) RxCpltCallback : callback when a reception transfer is completed.
@@ -208,7 +219,7 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- Use function @ref HAL_MMC_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_MMC_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) TxCpltCallback : callback when a transmission transfer is completed.
(+) RxCpltCallback : callback when a reception transfer is completed.
@@ -222,12 +233,12 @@
(+) MspDeInitCallback : MMC MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
- By default, after the @ref HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET
+ By default, after the HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_MMC_Init
- and @ref HAL_MMC_DeInit only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_MMC_Init and @ref HAL_MMC_DeInit
+ reset to the legacy weak (surcharged) functions in the HAL_MMC_Init
+ and HAL_MMC_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_MMC_Init and HAL_MMC_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
@@ -235,8 +246,8 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_MMC_RegisterCallback before calling @ref HAL_MMC_DeInit
- or @ref HAL_MMC_Init function.
+ using HAL_MMC_RegisterCallback before calling HAL_MMC_DeInit
+ or HAL_MMC_Init function.
When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
@@ -244,17 +255,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -278,7 +278,7 @@
* @{
*/
#if defined (VDD_VALUE) && (VDD_VALUE <= 1950U)
-#define MMC_VOLTAGE_RANGE MMC_LOW_VOLTAGE_RANGE
+#define MMC_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
#define MMC_EXT_CSD_PWR_CL_26_INDEX 201
#define MMC_EXT_CSD_PWR_CL_52_INDEX 200
@@ -288,7 +288,7 @@
#define MMC_EXT_CSD_PWR_CL_52_POS 0
#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 16
#else
-#define MMC_VOLTAGE_RANGE MMC_HIGH_VOLTAGE_RANGE
+#define MMC_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
#define MMC_EXT_CSD_PWR_CL_26_INDEX 203
#define MMC_EXT_CSD_PWR_CL_52_INDEX 202
@@ -299,6 +299,11 @@
#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 24
#endif
+#define MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_INDEX 216
+#define MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_POS 0
+#define MMC_EXT_CSD_S_A_TIMEOUT_INDEX 217
+#define MMC_EXT_CSD_S_A_TIMEOUT_POS 8
+
/* Frequencies used in the driver for clock divider calculation */
#define MMC_INIT_FREQ 400000U /* Initalization phase : 400 kHz max */
#define MMC_HIGH_SPEED_FREQ 52000000U /* High speed phase : 52 MHz max */
@@ -450,7 +455,6 @@
{
uint32_t errorstate;
MMC_InitTypeDef Init;
- HAL_StatusTypeDef status;
uint32_t sdmmc_clk;
/* Default SDMMC peripheral configuration for MMC card initialization */
@@ -478,11 +482,7 @@
#endif
/* Initialize SDMMC peripheral interface with default configuration */
- status = SDMMC_Init(hmmc->Instance, Init);
- if(status == HAL_ERROR)
- {
- return HAL_ERROR;
- }
+ (void)SDMMC_Init(hmmc->Instance, Init);
#if !defined(STM32L4P5xx) && !defined(STM32L4Q5xx) && !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
/* Disable SDMMC Clock */
@@ -490,11 +490,7 @@
#endif
/* Set Power State to ON */
- status = SDMMC_PowerState_ON(hmmc->Instance);
- if(status == HAL_ERROR)
- {
- return HAL_ERROR;
- }
+ (void)SDMMC_PowerState_ON(hmmc->Instance);
#if !defined(STM32L4P5xx) && !defined(STM32L4Q5xx) && !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
/* Enable MMC Clock */
@@ -3376,6 +3372,318 @@
return HAL_BUSY;
}
}
+
+/**
+ * @brief Switch the device from Standby State to Sleep State.
+ * @param hmmc pointer to MMC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_SleepDevice(MMC_HandleTypeDef *hmmc)
+{
+ uint32_t errorstate, sleep_timeout, timeout, count, response = 0U;
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the state of the driver */
+ if(hmmc->State == HAL_MMC_STATE_READY)
+ {
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Set the power-off notification to powered-on : Ext_CSD[34] = 1 */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03220100U));
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ count = SDMMC_MAX_TRIAL;
+ do
+ {
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ break;
+ }
+
+ /* Get command response */
+ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+ count--;
+ }while(((response & 0x100U) == 0U) && (count != 0U));
+
+ /* Check the status after the switch command execution */
+ if (count == 0U)
+ {
+ errorstate = SDMMC_ERROR_TIMEOUT;
+ }
+ else if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Check the bit SWITCH_ERROR of the device status */
+ if ((response & 0x80U) != 0U)
+ {
+ errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+ }
+ else
+ {
+ /* Set the power-off notification to sleep notification : Ext_CSD[34] = 4 */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03220400U));
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Field SLEEP_NOTIFICATION_TIME [216] */
+ sleep_timeout = ((hmmc->Ext_CSD[(MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_INDEX/4)] >> MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_POS) & 0x000000FFU);
+
+ /* Sleep/Awake Timeout = 10µs * 2^SLEEP_NOTIFICATION_TIME, max value of SLEEP_NOTIFICATION_TIME is 0x17 */
+ /* In HAL, the tick interrupt occurs each ms */
+ timeout = (((1UL << (sleep_timeout & 0x1FU)) / 100U) + 1U);
+
+ /* Wait that the device is ready by checking the D0 line */
+ while((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
+ {
+ if((HAL_GetTick() - tickstart) >= timeout)
+ {
+ errorstate = SDMMC_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear the flag corresponding to end D0 bus line */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
+
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ count = SDMMC_MAX_TRIAL;
+ do
+ {
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ break;
+ }
+
+ /* Get command response */
+ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+ count--;
+ }while(((response & 0x100U) == 0U) && (count != 0U));
+
+ /* Check the status after the switch command execution */
+ if (count == 0U)
+ {
+ errorstate = SDMMC_ERROR_TIMEOUT;
+ }
+ else if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Check the bit SWITCH_ERROR of the device status */
+ if ((response & 0x80U) != 0U)
+ {
+ errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+ }
+ else
+ {
+ /* Switch the device in stand-by mode */
+ (void)SDMMC_CmdSelDesel(hmmc->Instance, 0U);
+
+ /* Field S_A_TIEMOUT [217] */
+ sleep_timeout = ((hmmc->Ext_CSD[(MMC_EXT_CSD_S_A_TIMEOUT_INDEX/4)] >> MMC_EXT_CSD_S_A_TIMEOUT_POS) & 0x000000FFU);
+
+ /* Sleep/Awake Timeout = 100ns * 2^S_A_TIMEOUT, max value of S_A_TIMEOUT is 0x17 */
+ /* In HAL, the tick interrupt occurs each ms */
+ timeout = (((1UL << (sleep_timeout & 0x1FU)) / 10000U) + 1U);
+
+ if (HAL_MMC_GetCardState(hmmc) == HAL_MMC_CARD_STANDBY)
+ {
+ /* Send CMD5 CMD_MMC_SLEEP_AWAKE with RCA and SLEEP as argument */
+ errorstate = SDMMC_CmdSleepMmc(hmmc->Instance, ((hmmc->MmcCard.RelCardAdd << 16U) | (0x1U << 15U)));
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Wait that the device is ready by checking the D0 line */
+ while((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
+ {
+ if((HAL_GetTick() - tickstart) >= timeout)
+ {
+ errorstate = SDMMC_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear the flag corresponding to end D0 bus line */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
+ }
+ }
+ else
+ {
+ errorstate = SDMMC_ERROR_REQUEST_NOT_APPLICABLE;
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ /* Manage errors */
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+
+ if (errorstate != HAL_MMC_ERROR_TIMEOUT)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ else
+ {
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Switch the device from Sleep State to Standby State.
+ * @param hmmc pointer to MMC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc)
+{
+ uint32_t errorstate, sleep_timeout, timeout, count, response = 0U;
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the state of the driver */
+ if (hmmc->State == HAL_MMC_STATE_READY)
+ {
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Field S_A_TIEMOUT [217] */
+ sleep_timeout = ((hmmc->Ext_CSD[(MMC_EXT_CSD_S_A_TIMEOUT_INDEX/4)] >> MMC_EXT_CSD_S_A_TIMEOUT_POS) & 0x000000FFU);
+
+ /* Sleep/Awake Timeout = 100ns * 2^S_A_TIMEOUT, max value of S_A_TIMEOUT is 0x17 */
+ /* In HAL, the tick interrupt occurs each ms */
+ timeout = (((1UL << (sleep_timeout & 0x1FU)) / 10000U) + 1U);
+
+ /* Send CMD5 CMD_MMC_SLEEP_AWAKE with RCA and AWAKE as argument */
+ errorstate = SDMMC_CmdSleepMmc(hmmc->Instance, (hmmc->MmcCard.RelCardAdd << 16U));
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Wait that the device is ready by checking the D0 line */
+ while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
+ {
+ if((HAL_GetTick() - tickstart) >= timeout)
+ {
+ errorstate = SDMMC_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear the flag corresponding to end D0 bus line */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
+
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ if (HAL_MMC_GetCardState(hmmc) == HAL_MMC_CARD_STANDBY)
+ {
+ /* Switch the device in transfer mode */
+ errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ if (HAL_MMC_GetCardState(hmmc) == HAL_MMC_CARD_TRANSFER)
+ {
+ /* Set the power-off notification to powered-on : Ext_CSD[34] = 1 */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03220100U));
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ count = SDMMC_MAX_TRIAL;
+ do
+ {
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ break;
+ }
+
+ /* Get command response */
+ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+ count--;
+ }while(((response & 0x100U) == 0U) && (count != 0U));
+
+ /* Check the status after the switch command execution */
+ if (count == 0U)
+ {
+ errorstate = SDMMC_ERROR_TIMEOUT;
+ }
+ else if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Check the bit SWITCH_ERROR of the device status */
+ if ((response & 0x80U) != 0U)
+ {
+ errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+ else
+ {
+ errorstate = SDMMC_ERROR_REQUEST_NOT_APPLICABLE;
+ }
+ }
+ }
+ else
+ {
+ errorstate = SDMMC_ERROR_REQUEST_NOT_APPLICABLE;
+ }
+ }
+ }
+
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ /* Manage errors */
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+
+ if (errorstate != HAL_MMC_ERROR_TIMEOUT)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ else
+ {
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
#endif /* defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) */
/**
@@ -4304,5 +4612,3 @@
#endif /* HAL_MMC_MODULE_ENABLED */
#endif /* SDMMC1 */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_mmc_ex.c b/Src/stm32l4xx_hal_mmc_ex.c
index 9fefe0e..2345622 100644
--- a/Src/stm32l4xx_hal_mmc_ex.c
+++ b/Src/stm32l4xx_hal_mmc_ex.c
@@ -7,6 +7,17 @@
* functionalities of the Secure Digital (MMC) peripheral:
* + Extended features functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -19,17 +30,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -77,8 +77,8 @@
/**
* @brief Configure DMA Dual Buffer mode. The Data transfer is managed by an Internal DMA.
* @param hmmc MMC handle
- * @param pDataBuffer0 Pointer to the buffer0 that will contain/receive the transfered data
- * @param pDataBuffer1 Pointer to the buffer1 that will contain/receive the transfered data
+ * @param pDataBuffer0 Pointer to the buffer0 that will contain/receive the transferred data
+ * @param pDataBuffer1 Pointer to the buffer1 that will contain/receive the transferred data
* @param BufferSize Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size.
* @retval HAL status
*/
@@ -179,7 +179,7 @@
}
/**
- * @brief Write block(s) to a specified address in a card. The transfered Data are stored in Buffer0 and Buffer1.
+ * @brief Write block(s) to a specified address in a card. The transferred Data are stored in Buffer0 and Buffer1.
* Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function.
* @param hmmc MMC handle
* @param BlockAdd Block Address from where data is to be read
@@ -363,5 +363,3 @@
*/
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_msp_template.c b/Src/stm32l4xx_hal_msp_template.c
index 6752c8e..a621994 100644
--- a/Src/stm32l4xx_hal_msp_template.c
+++ b/Src/stm32l4xx_hal_msp_template.c
@@ -8,13 +8,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -101,5 +100,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_nand.c b/Src/stm32l4xx_hal_nand.c
index b9402ba..05ad32b 100644
--- a/Src/stm32l4xx_hal_nand.c
+++ b/Src/stm32l4xx_hal_nand.c
@@ -6,6 +6,17 @@
* This file provides a generic firmware to drive NAND memories mounted
* as external device.
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -58,25 +69,25 @@
The compilation define USE_HAL_NAND_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_NAND_RegisterCallback() to register a user callback,
+ Use Functions HAL_NAND_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) MspInitCallback : NAND MspInit.
(+) MspDeInitCallback : NAND MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- Use function @ref HAL_NAND_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_NAND_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) MspInitCallback : NAND MspInit.
(+) MspDeInitCallback : NAND MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
- By default, after the @ref HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET
+ By default, after the HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_NAND_Init
- and @ref HAL_NAND_DeInit only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_NAND_Init and @ref HAL_NAND_DeInit
+ reset to the legacy weak (surcharged) functions in the HAL_NAND_Init
+ and HAL_NAND_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_NAND_Init and HAL_NAND_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
@@ -84,8 +95,8 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_NAND_RegisterCallback before calling @ref HAL_NAND_DeInit
- or @ref HAL_NAND_Init function.
+ using HAL_NAND_RegisterCallback before calling HAL_NAND_DeInit
+ or HAL_NAND_Init function.
When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
@@ -93,17 +104,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -2239,5 +2239,3 @@
*/
#endif /* FMC_BANK3 */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_nor.c b/Src/stm32l4xx_hal_nor.c
index 2a69e4e..02f250b 100644
--- a/Src/stm32l4xx_hal_nor.c
+++ b/Src/stm32l4xx_hal_nor.c
@@ -6,6 +6,17 @@
* This file provides a generic firmware to drive NOR memories mounted
* as external device.
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -55,25 +66,25 @@
The compilation define USE_HAL_NOR_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_NOR_RegisterCallback() to register a user callback,
+ Use Functions HAL_NOR_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) MspInitCallback : NOR MspInit.
(+) MspDeInitCallback : NOR MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- Use function @ref HAL_NOR_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_NOR_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) MspInitCallback : NOR MspInit.
(+) MspDeInitCallback : NOR MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
- By default, after the @ref HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
+ By default, after the HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_NOR_Init
- and @ref HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_NOR_Init and @ref HAL_NOR_DeInit
+ reset to the legacy weak (surcharged) functions in the HAL_NOR_Init
+ and HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_NOR_Init and HAL_NOR_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
@@ -81,8 +92,8 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_NOR_RegisterCallback before calling @ref HAL_NOR_DeInit
- or @ref HAL_NOR_Init function.
+ using HAL_NOR_RegisterCallback before calling HAL_NOR_DeInit
+ or HAL_NOR_Init function.
When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
@@ -90,17 +101,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -230,6 +230,7 @@
FMC_NORSRAM_TimingTypeDef *ExtTiming)
{
uint32_t deviceaddress;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR handle parameter */
if (hnor == NULL)
@@ -299,11 +300,23 @@
deviceaddress = NOR_MEMORY_ADRESS4;
}
+ FMC_NORSRAM_WriteOperation_Enable(hnor->Instance,hnor->Init.NSBank);
+
/* Get the value of the command set */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
+
+ status = HAL_NOR_ReturnToReadMode(hnor);
- return HAL_NOR_ReturnToReadMode(hnor);
+ if (hnor->Init.WriteOperation == FMC_WRITE_OPERATION_DISABLE)
+ {
+ FMC_NORSRAM_WriteOperation_Disable(hnor->Instance,hnor->Init.NSBank);
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_PROTECTED;
+ }
+
+ return status;
}
/**
@@ -1508,5 +1521,3 @@
*/
#endif /* FMC_BANK1 */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_opamp.c b/Src/stm32l4xx_hal_opamp.c
index ca9488d..3796115 100644
--- a/Src/stm32l4xx_hal_opamp.c
+++ b/Src/stm32l4xx_hal_opamp.c
@@ -5,14 +5,22 @@
* @brief OPAMP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the operational amplifier(s) peripheral:
- * + OPAMP configuration
- * + OPAMP calibration
- * Thanks to
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
================================================================================
##### OPAMP Peripheral Features #####
@@ -91,7 +99,7 @@
(#) Configure the OPAMP using HAL_OPAMP_Init() function:
(++) Select OPAMP_POWERMODE_LOWPOWER
- (++) Otherwise select OPAMP_POWERMODE_NORMAL
+ (++) Otherwise select OPAMP_POWERMODE_NORMALPOWER
*** Calibration ***
============================================
@@ -114,14 +122,14 @@
(++) The compilation define USE_HAL_OPAMP_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- (++) Use Functions @ref HAL_OPAMP_RegisterCallback() to register a user callback,
+ (++) Use Functions HAL_OPAMP_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+++) MspInitCallback : OPAMP MspInit.
(+++) MspDeInitCallback : OPAMP MspFeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- (++) Use function @ref HAL_OPAMP_UnRegisterCallback() to reset a callback to the default
+ (++) Use function HAL_OPAMP_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+++) MspInitCallback : OPAMP MspInit.
(+++) MspDeInitCallback : OPAMP MspdeInit.
@@ -192,18 +200,6 @@
|-----------------|--------|-----------------------|---------------------|
(1): ADC1 or ADC2 shall select IN15.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -335,7 +331,7 @@
assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming));
if ((hopamp->Init.UserTrimming) == OPAMP_TRIMMING_USER)
{
- if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
+ if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER)
{
assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueP));
assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueN));
@@ -399,7 +395,7 @@
/* Set power mode and associated calibration parameters */
if (hopamp->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER)
{
- /* OPAMP_POWERMODE_NORMAL */
+ /* OPAMP_POWERMODE_NORMALPOWER */
/* Set calibration mode (factory or user) and values for */
/* transistors differential pair high (PMOS) and low (NMOS) for */
/* normal mode. */
@@ -681,7 +677,7 @@
SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_USERTRIM);
/* Select trimming settings depending on power mode */
- if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
+ if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER)
{
tmp_opamp_reg_trimming = &hopamp->Instance->OTR;
}
@@ -707,7 +703,7 @@
while (delta != 0U)
{
/* Set candidate trimming */
- /* OPAMP_POWERMODE_NORMAL */
+ /* OPAMP_POWERMODE_NORMALPOWER */
MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen);
/* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */
@@ -758,7 +754,7 @@
while (delta != 0U)
{
/* Set candidate trimming */
- /* OPAMP_POWERMODE_NORMAL */
+ /* OPAMP_POWERMODE_NORMALPOWER */
MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep<<OPAMP_INPUT_NONINVERTING));
/* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */
@@ -950,7 +946,7 @@
else
{
/* Select trimming settings depending on power mode */
- if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
+ if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER)
{
tmp_opamp_reg_trimming = &OPAMP->OTR;
}
@@ -1174,5 +1170,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_opamp_ex.c b/Src/stm32l4xx_hal_opamp_ex.c
index c995d40..89cb7cd 100644
--- a/Src/stm32l4xx_hal_opamp_ex.c
+++ b/Src/stm32l4xx_hal_opamp_ex.c
@@ -4,8 +4,7 @@
* @author MCD Application Team
* @brief Extended OPAMP HAL module driver.
* This file provides firmware functions to manage the following
- * functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc)
- * peripheral:
+ * functionalities of the operational amplifier(s) peripheral:
* + Extended Initialization and de-initialization functions
* + Extended Peripheral Control functions
*
@@ -13,13 +12,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -141,7 +139,7 @@
SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_USERTRIM);
/* Select trimming settings depending on power mode */
- if (hopamp1->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
+ if (hopamp1->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER)
{
tmp_opamp1_reg_trimming = &OPAMP1->OTR;
}
@@ -150,7 +148,7 @@
tmp_opamp1_reg_trimming = &OPAMP1->LPOTR;
}
- if (hopamp2->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
+ if (hopamp2->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER)
{
tmp_opamp2_reg_trimming = &OPAMP2->OTR;
}
@@ -180,7 +178,7 @@
while (delta != 0U)
{
/* Set candidate trimming */
- /* OPAMP_POWERMODE_NORMAL */
+ /* OPAMP_POWERMODE_NORMALPOWER */
MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1);
MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2);
@@ -252,7 +250,7 @@
while (delta != 0U)
{
/* Set candidate trimming */
- /* OPAMP_POWERMODE_NORMAL */
+ /* OPAMP_POWERMODE_NORMALPOWER */
MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<<OPAMP_INPUT_NONINVERTING));
MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep2<<OPAMP_INPUT_NONINVERTING));
@@ -438,5 +436,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_ospi.c b/Src/stm32l4xx_hal_ospi.c
index 9979053..118ce2d 100644
--- a/Src/stm32l4xx_hal_ospi.c
+++ b/Src/stm32l4xx_hal_ospi.c
@@ -15,6 +15,17 @@
+ Errors management and abort functionality
+ IO manager configuration
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
@@ -174,7 +185,7 @@
(+) MspInitCallback : OSPI MspInit.
(+) MspDeInitCallback : OSPI MspDeInit.
[..]
- This function takes as parameters the HAL peripheral handle, the Callback ID
+ This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
@@ -220,17 +231,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -280,7 +280,8 @@
static void OSPI_DMAHalfCplt (DMA_HandleTypeDef *hdma);
static void OSPI_DMAError (DMA_HandleTypeDef *hdma);
static void OSPI_DMAAbortCplt (DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout);
+static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State,
+ uint32_t Tickstart, uint32_t Timeout);
static HAL_StatusTypeDef OSPI_ConfigCmd (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd);
static HAL_StatusTypeDef OSPIM_GetConfig (uint8_t instance_nb, OSPIM_CfgTypeDef *cfg);
/**
@@ -340,7 +341,6 @@
assert_param(IS_OSPI_SAMPLE_SHIFTING(hospi->Init.SampleShifting));
assert_param(IS_OSPI_DHQC (hospi->Init.DelayHoldQuarterCycle));
assert_param(IS_OSPI_CS_BOUNDARY (hospi->Init.ChipSelectBoundary));
- assert_param(IS_OSPI_DLYBYP (hospi->Init.DelayBlockBypass));
#if defined (OCTOSPI_DCR3_MAXTRAN)
assert_param(IS_OSPI_MAXTRAN (hospi->Init.MaxTran));
#endif
@@ -374,22 +374,21 @@
#else
/* Initialization of the low level hardware */
HAL_OSPI_MspInit(hospi);
-#endif
+#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
/* Configure the default timeout for the OSPI memory access */
(void)HAL_OSPI_SetTimeout(hospi, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
- /* Configure memory type, device size, chip select high time, delay block bypass, free running clock, clock mode */
- MODIFY_REG(hospi->Instance->DCR1,
- (OCTOSPI_DCR1_MTYP | OCTOSPI_DCR1_DEVSIZE | OCTOSPI_DCR1_CSHT | OCTOSPI_DCR1_DLYBYP |
- OCTOSPI_DCR1_FRCK | OCTOSPI_DCR1_CKMODE),
+ /* Configure memory type, device size, chip select high time, free running clock, clock mode */
+ MODIFY_REG(hospi->Instance->DCR1, (OCTOSPI_DCR1_MTYP | OCTOSPI_DCR1_DEVSIZE | OCTOSPI_DCR1_CSHT |
+ OCTOSPI_DCR1_FRCK | OCTOSPI_DCR1_CKMODE),
(hospi->Init.MemoryType | ((hospi->Init.DeviceSize - 1U) << OCTOSPI_DCR1_DEVSIZE_Pos) |
- ((hospi->Init.ChipSelectHighTime - 1U) << OCTOSPI_DCR1_CSHT_Pos) |
- hospi->Init.DelayBlockBypass | hospi->Init.ClockMode));
+ ((hospi->Init.ChipSelectHighTime - 1U) << OCTOSPI_DCR1_CSHT_Pos) | hospi->Init.ClockMode));
#if defined (OCTOSPI_DCR3_MAXTRAN)
- /* Configure chip select boundary and maximun transfer */
- hospi->Instance->DCR3 = ((hospi->Init.ChipSelectBoundary << OCTOSPI_DCR3_CSBOUND_Pos) | (hospi->Init.MaxTran << OCTOSPI_DCR3_MAXTRAN_Pos));
+ /* Configure chip select boundary and maximum transfer */
+ hospi->Instance->DCR3 = ((hospi->Init.ChipSelectBoundary << OCTOSPI_DCR3_CSBOUND_Pos) |
+ (hospi->Init.MaxTran << OCTOSPI_DCR3_MAXTRAN_Pos));
#else
/* Configure chip select boundary */
hospi->Instance->DCR3 = (hospi->Init.ChipSelectBoundary << OCTOSPI_DCR3_CSBOUND_Pos);
@@ -409,13 +408,15 @@
if (status == HAL_OK)
{
/* Configure clock prescaler */
- MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER, ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos));
+ MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER,
+ ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos));
/* Configure Dual Quad mode */
MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DQM, hospi->Init.DualQuad);
/* Configure sample shifting and delay hold quarter cycle */
- MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC), (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle));
+ MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC),
+ (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle));
/* Enable OctoSPI */
__HAL_OSPI_ENABLE(hospi);
@@ -492,7 +493,7 @@
#else
/* De-initialize the low-level hardware */
HAL_OSPI_MspDeInit(hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
/* Reset the driver state */
hospi->State = HAL_OSPI_STATE_RESET;
@@ -587,7 +588,7 @@
hospi->FifoThresholdCallback(hospi);
#else
HAL_OSPI_FifoThresholdCallback(hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
}
/* OctoSPI transfer complete interrupt occurred ----------------------------*/
else if (((flag & HAL_OSPI_FLAG_TC) != 0U) && ((itsource & HAL_OSPI_IT_TC) != 0U))
@@ -617,7 +618,7 @@
hospi->RxCpltCallback(hospi);
#else
HAL_OSPI_RxCpltCallback(hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
else
{
@@ -642,7 +643,7 @@
hospi->TxCpltCallback(hospi);
#else
HAL_OSPI_TxCpltCallback(hospi);
-#endif
+#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
else if (currentstate == HAL_OSPI_STATE_BUSY_CMD)
{
@@ -651,7 +652,7 @@
hospi->CmdCpltCallback(hospi);
#else
HAL_OSPI_CmdCpltCallback(hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
else if (currentstate == HAL_OSPI_STATE_ABORT)
{
@@ -663,7 +664,7 @@
hospi->AbortCpltCallback(hospi);
#else
HAL_OSPI_AbortCpltCallback(hospi);
-#endif
+#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
}
else
{
@@ -673,7 +674,7 @@
hospi->ErrorCallback(hospi);
#else
HAL_OSPI_ErrorCallback(hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
}
else
@@ -703,7 +704,7 @@
hospi->StatusMatchCallback(hospi);
#else
HAL_OSPI_StatusMatchCallback(hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
/* OctoSPI transfer error interrupt occurred -------------------------------*/
else if (((flag & HAL_OSPI_FLAG_TE) != 0U) && ((itsource & HAL_OSPI_IT_TE) != 0U))
@@ -735,7 +736,7 @@
hospi->ErrorCallback(hospi);
#else
HAL_OSPI_ErrorCallback(hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
}
}
else
@@ -748,7 +749,7 @@
hospi->ErrorCallback(hospi);
#else
HAL_OSPI_ErrorCallback(hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
}
/* OctoSPI timeout interrupt occurred --------------------------------------*/
@@ -762,7 +763,7 @@
hospi->TimeOutCallback(hospi);
#else
HAL_OSPI_TimeOutCallback(hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
else
{
@@ -1475,21 +1476,21 @@
hospi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
MODIFY_REG(hospi->hdma->Instance->CCR, DMA_CCR_DIR, hospi->hdma->Init.Direction);
- /* Enable the transmit DMA Channel */
- if (HAL_DMA_Start_IT(hospi->hdma, (uint32_t)pData, (uint32_t)&hospi->Instance->DR, hospi->XferSize) == HAL_OK)
- {
- /* Enable the transfer error interrupt */
- __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
+ /* Enable the transmit DMA Channel */
+ if (HAL_DMA_Start_IT(hospi->hdma, (uint32_t)pData, (uint32_t)&hospi->Instance->DR, hospi->XferSize) == HAL_OK)
+ {
+ /* Enable the transfer error interrupt */
+ __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
- /* Enable the DMA transfer by setting the DMAEN bit */
- SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
- }
- else
- {
- status = HAL_ERROR;
- hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
- hospi->State = HAL_OSPI_STATE_READY;
- }
+ /* Enable the DMA transfer by setting the DMAEN bit */
+ SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
+ hospi->State = HAL_OSPI_STATE_READY;
+ }
}
}
else
@@ -1520,7 +1521,6 @@
uint32_t data_size = hospi->Instance->DLR + 1U;
uint32_t addr_reg = hospi->Instance->AR;
uint32_t ir_reg = hospi->Instance->IR;
-
/* Check the data pointer allocation */
if (pData == NULL)
{
@@ -1600,38 +1600,38 @@
hospi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
MODIFY_REG(hospi->hdma->Instance->CCR, DMA_CCR_DIR, hospi->hdma->Init.Direction);
- /* Enable the transmit DMA Channel */
- if (HAL_DMA_Start_IT(hospi->hdma, (uint32_t)&hospi->Instance->DR, (uint32_t)pData, hospi->XferSize) == HAL_OK)
- {
- /* Enable the transfer error interrupt */
- __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
+ /* Enable the transmit DMA Channel */
+ if (HAL_DMA_Start_IT(hospi->hdma, (uint32_t)&hospi->Instance->DR, (uint32_t)pData, hospi->XferSize) == HAL_OK)
+ {
+ /* Enable the transfer error interrupt */
+ __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
- /* Trig the transfer by re-writing address or instruction register */
- if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
- {
- WRITE_REG(hospi->Instance->AR, addr_reg);
- }
- else
- {
- if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE)
+ /* Trig the transfer by re-writing address or instruction register */
+ if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
{
WRITE_REG(hospi->Instance->AR, addr_reg);
}
else
{
- WRITE_REG(hospi->Instance->IR, ir_reg);
+ if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE)
+ {
+ WRITE_REG(hospi->Instance->AR, addr_reg);
+ }
+ else
+ {
+ WRITE_REG(hospi->Instance->IR, ir_reg);
+ }
}
- }
- /* Enable the DMA transfer by setting the DMAEN bit */
- SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
- }
- else
- {
- status = HAL_ERROR;
- hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
- hospi->State = HAL_OSPI_STATE_READY;
- }
+ /* Enable the DMA transfer by setting the DMAEN bit */
+ SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
+ hospi->State = HAL_OSPI_STATE_READY;
+ }
}
}
else
@@ -1662,7 +1662,7 @@
uint32_t ir_reg = hospi->Instance->IR;
#ifdef USE_FULL_ASSERT
uint32_t dlr_reg = hospi->Instance->DLR;
-#endif
+#endif /* USE_FULL_ASSERT */
/* Check the parameters of the autopolling configuration structure */
assert_param(IS_OSPI_MATCH_MODE (cfg->MatchMode));
@@ -1741,7 +1741,7 @@
uint32_t ir_reg = hospi->Instance->IR;
#ifdef USE_FULL_ASSERT
uint32_t dlr_reg = hospi->Instance->DLR;
-#endif
+#endif /* USE_FULL_ASSERT */
/* Check the parameters of the autopolling configuration structure */
assert_param(IS_OSPI_MATCH_MODE (cfg->MatchMode));
@@ -2028,7 +2028,8 @@
* @param pCallback : pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_OSPI_RegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, pOSPI_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID,
+ pOSPI_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -2216,7 +2217,7 @@
return status;
}
-#endif
+#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
/**
* @}
@@ -2347,7 +2348,7 @@
hospi->AbortCpltCallback(hospi);
#else
HAL_OSPI_AbortCpltCallback(hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
}
}
else
@@ -2373,7 +2374,7 @@
hospi->AbortCpltCallback(hospi);
#else
HAL_OSPI_AbortCpltCallback(hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
}
}
@@ -2487,7 +2488,9 @@
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t instance;
- uint8_t index, ospi_enabled = 0U, other_instance;
+ uint8_t index;
+ uint8_t ospi_enabled = 0U;
+ uint8_t other_instance;
OSPIM_CfgTypeDef IOM_cfg[OSPI_NB_INSTANCE];
/* Prevent unused argument(s) compilation warning */
@@ -2592,8 +2595,10 @@
(cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort))
{
#if defined (OCTOSPIM_CR_MUXEN)
- if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) && (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) &&
- (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) && (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort))
+ if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) &&
+ (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) &&
+ (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) &&
+ (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort))
{
/* Multiplexing should be performed */
SET_BIT(OCTOSPIM->CR, OCTOSPIM_CR_MUXEN);
@@ -2609,11 +2614,13 @@
CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN);
if (IOM_cfg[other_instance].IOLowPort != HAL_OSPIM_IOPORT_NONE)
{
- CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN);
+ CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
+ OCTOSPIM_PCR_IOLEN);
}
if (IOM_cfg[other_instance].IOHighPort != HAL_OSPIM_IOPORT_NONE)
{
- CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN);
+ CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
+ OCTOSPIM_PCR_IOHEN);
}
#if defined (OCTOSPIM_CR_MUXEN)
}
@@ -2621,7 +2628,8 @@
}
/******************** Activation of new configuration *********************/
- MODIFY_REG(OCTOSPIM->PCR[(cfg->NCSPort-1U)], (OCTOSPIM_PCR_NCSEN | OCTOSPIM_PCR_NCSSRC), (OCTOSPIM_PCR_NCSEN | (instance << OCTOSPIM_PCR_NCSSRC_Pos)));
+ MODIFY_REG(OCTOSPIM->PCR[(cfg->NCSPort - 1U)], (OCTOSPIM_PCR_NCSEN | OCTOSPIM_PCR_NCSSRC),
+ (OCTOSPIM_PCR_NCSEN | (instance << OCTOSPIM_PCR_NCSSRC_Pos)));
#if defined (OCTOSPIM_CR_MUXEN)
if ((cfg->Req2AckTime - 1U) > ((OCTOSPIM->CR & OCTOSPIM_CR_REQ2ACK_TIME) >> OCTOSPIM_CR_REQ2ACK_TIME_Pos))
@@ -2639,11 +2647,13 @@
if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), OCTOSPIM_PCR_IOLEN);
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), OCTOSPIM_PCR_IOLEN);
}
else if (cfg->IOLowPort != HAL_OSPIM_IOPORT_NONE)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), OCTOSPIM_PCR_IOHEN);
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), OCTOSPIM_PCR_IOHEN);
}
else
{
@@ -2652,11 +2662,13 @@
if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0));
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0));
}
else if (cfg->IOHighPort != HAL_OSPIM_IOPORT_NONE)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0));
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0));
}
else
{
@@ -2666,21 +2678,25 @@
else
{
#endif
- MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos)));
+ MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC),
+ (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos)));
if (cfg->DQSPort != 0U)
{
- MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos)));
+ MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC),
+ (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos)));
}
if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
- (OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
+ (OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
}
else if (cfg->IOLowPort != HAL_OSPIM_IOPORT_NONE)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
- (OCTOSPIM_PCR_IOHEN | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
+ (OCTOSPIM_PCR_IOHEN | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
}
else
{
@@ -2689,13 +2705,15 @@
if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
- (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
+ (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
}
else if (cfg->IOHighPort != HAL_OSPIM_IOPORT_NONE)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
- (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
+ (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
}
else
{
@@ -2763,7 +2781,7 @@
hospi->RxHalfCpltCallback(hospi);
#else
HAL_OSPI_RxHalfCpltCallback(hospi);
-#endif
+#endif /*(USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
else
{
@@ -2771,7 +2789,7 @@
hospi->TxHalfCpltCallback(hospi);
#else
HAL_OSPI_TxHalfCpltCallback(hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
}
}
@@ -2803,7 +2821,7 @@
hospi->ErrorCallback(hospi);
#else
HAL_OSPI_ErrorCallback(hospi);
-#endif
+#endif /*(USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
}
@@ -2842,7 +2860,7 @@
hospi->AbortCpltCallback(hospi);
#else
HAL_OSPI_AbortCpltCallback(hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
}
else
@@ -2856,7 +2874,7 @@
hospi->ErrorCallback(hospi);
#else
HAL_OSPI_ErrorCallback(hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
}
}
@@ -2899,7 +2917,10 @@
static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd)
{
HAL_StatusTypeDef status = HAL_OK;
- __IO uint32_t *ccr_reg, *tcr_reg, *ir_reg, *abr_reg;
+ __IO uint32_t *ccr_reg;
+ __IO uint32_t *tcr_reg;
+ __IO uint32_t *ir_reg;
+ __IO uint32_t *abr_reg;
/* Re-initialize the value of the functional mode */
MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, 0U);
@@ -3070,7 +3091,8 @@
static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *cfg)
{
HAL_StatusTypeDef status = HAL_OK;
- uint32_t reg, value = 0U;
+ uint32_t reg;
+ uint32_t value = 0U;
uint32_t index;
if ((instance_nb == 0U) || (instance_nb > OSPI_NB_INSTANCE) || (cfg == NULL))
@@ -3093,7 +3115,8 @@
if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) == 0U)
{
#endif
- value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1);
+ value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC
+ | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1);
#if defined (OCTOSPIM_CR_MUXEN)
}
else
@@ -3197,5 +3220,3 @@
*/
#endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_pcd.c b/Src/stm32l4xx_hal_pcd.c
index b018874..28ac991 100644
--- a/Src/stm32l4xx_hal_pcd.c
+++ b/Src/stm32l4xx_hal_pcd.c
@@ -10,6 +10,17 @@
* + Peripheral Control functions
* + Peripheral State functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -40,17 +51,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -94,8 +94,10 @@
#if defined (USB)
static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
+#if (USE_USB_DOUBLE_BUFFER == 1U)
static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal);
static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal);
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
#endif /* defined (USB) */
/**
* @}
@@ -235,7 +237,7 @@
hpcd->USB_Address = 0U;
hpcd->State = HAL_PCD_STATE_READY;
-
+
/* Activate LPM */
if (hpcd->Init.lpm_enable == 1U)
{
@@ -732,7 +734,8 @@
/**
* @brief Unregister the USB PCD Iso OUT incomplete Callback
- * USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
+ * USB PCD Iso OUT incomplete Callback is redirected
+ * to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
*/
@@ -806,7 +809,8 @@
/**
* @brief Unregister the USB PCD Iso IN incomplete Callback
- * USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
+ * USB PCD Iso IN incomplete Callback is redirected
+ * to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
*/
@@ -1068,9 +1072,13 @@
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t i, ep_intr, epint, epnum;
- uint32_t fifoemptymsk, temp;
USB_OTG_EPTypeDef *ep;
+ uint32_t i;
+ uint32_t ep_intr;
+ uint32_t epint;
+ uint32_t epnum;
+ uint32_t fifoemptymsk;
+ uint32_t temp;
/* ensure that we are in device mode */
if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
@@ -1116,6 +1124,7 @@
{
/* ... */
}
+
USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
}
@@ -1207,6 +1216,7 @@
}
if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
{
+ (void)USB_FlushTxFifo(USBx, epnum);
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
}
if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
@@ -1297,7 +1307,6 @@
{
USBx_INEP(i)->DIEPINT = 0xFB7FU;
USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
- USBx_INEP(i)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
@@ -1439,14 +1448,18 @@
*/
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
- if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_CTR))
+ uint32_t wIstr = USB_ReadInterrupts(hpcd->Instance);
+
+ if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR)
{
/* servicing of the endpoint correct transfer interrupt */
/* clear of the CTR flag into the sub */
(void)PCD_EP_ISR_Handler(hpcd);
+
+ return;
}
- if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_RESET))
+ if ((wIstr & USB_ISTR_RESET) == USB_ISTR_RESET)
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
@@ -1457,19 +1470,25 @@
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
(void)HAL_PCD_SetAddress(hpcd, 0U);
+
+ return;
}
- if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_PMAOVR))
+ if ((wIstr & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR)
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
+
+ return;
}
- if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_ERR))
+ if ((wIstr & USB_ISTR_ERR) == USB_ISTR_ERR)
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
+
+ return;
}
- if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_WKUP))
+ if ((wIstr & USB_ISTR_WKUP) == USB_ISTR_WKUP)
{
hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LPMODE);
hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
@@ -1491,9 +1510,11 @@
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
+
+ return;
}
- if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SUSP))
+ if ((wIstr & USB_ISTR_SUSP) == USB_ISTR_SUSP)
{
/* Force low-power mode in the macrocell */
hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
@@ -1508,10 +1529,12 @@
#else
HAL_PCD_SuspendCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ return;
}
/* Handle LPM Interrupt */
- if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_L1REQ))
+ if ((wIstr & USB_ISTR_L1REQ) == USB_ISTR_L1REQ)
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ);
if (hpcd->LPM_State == LPM_L0)
@@ -1536,9 +1559,11 @@
HAL_PCD_SuspendCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
+
+ return;
}
- if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SOF))
+ if ((wIstr & USB_ISTR_SOF) == USB_ISTR_SOF)
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
@@ -1547,12 +1572,16 @@
#else
HAL_PCD_SOFCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ return;
}
- if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_ESOF))
+ if ((wIstr & USB_ISTR_ESOF) == USB_ISTR_ESOF)
{
/* clear ESOF flag in ISTR */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
+
+ return;
}
}
#endif /* defined (USB) */
@@ -2053,6 +2082,32 @@
}
/**
+ * @brief Abort an USB EP transaction.
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ HAL_StatusTypeDef ret;
+ PCD_EPTypeDef *ep;
+
+ if ((0x80U & ep_addr) == 0x80U)
+ {
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+ }
+
+ /* Stop Xfer */
+ ret = USB_EPStopXfer(hpcd->Instance, ep);
+
+ return ret;
+}
+
+/**
* @brief Flush an endpoint
* @param hpcd PCD handle
* @param ep_addr endpoint address
@@ -2283,7 +2338,10 @@
static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
{
PCD_EPTypeDef *ep;
- uint16_t count, wIstr, wEPVal, TxByteNbre;
+ uint16_t count;
+ uint16_t wIstr;
+ uint16_t wEPVal;
+ uint16_t TxPctSize;
uint8_t epindex;
/* stay in loop while pending interrupts */
@@ -2403,6 +2461,7 @@
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
}
}
+#if (USE_USB_DOUBLE_BUFFER == 1U)
else
{
/* manage double buffer bulk out */
@@ -2413,7 +2472,7 @@
else /* manage double buffer iso out */
{
/* free EP OUT Buffer */
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
+ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)
{
@@ -2437,6 +2496,8 @@
}
}
}
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
/* multi-packet on the NON control OUT endpoint */
ep->xfer_count += count;
ep->xfer_buff += count;
@@ -2454,7 +2515,6 @@
{
(void) USB_EPStartXfer(hpcd->Instance, ep);
}
-
}
if ((wEPVal & USB_EP_CTR_TX) != 0U)
@@ -2464,43 +2524,73 @@
/* clear int flag */
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
- /* Manage Bulk Single Buffer Transaction */
- if ((ep->type == EP_TYPE_BULK) && ((wEPVal & USB_EP_KIND) == 0U))
+ if (ep->type != EP_TYPE_BULK)
{
- /* multi-packet on the NON control IN endpoint */
- TxByteNbre = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+ ep->xfer_len = 0U;
- if (ep->xfer_len > TxByteNbre)
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+ if (ep->doublebuffer != 0U)
{
- ep->xfer_len -= TxByteNbre;
+ if ((wEPVal & USB_EP_DTOG_TX) != 0U)
+ {
+ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ }
+ else
+ {
+ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ }
}
- else
- {
- ep->xfer_len = 0U;
- }
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
- /* Zero Length Packet? */
- if (ep->xfer_len == 0U)
- {
- /* TX COMPLETE */
+ /* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->DataInStageCallback(hpcd, ep->num);
+ hpcd->DataInStageCallback(hpcd, ep->num);
#else
- HAL_PCD_DataInStageCallback(hpcd, ep->num);
+ HAL_PCD_DataInStageCallback(hpcd, ep->num);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
- }
- else
- {
- /* Transfer is not yet Done */
- ep->xfer_buff += TxByteNbre;
- ep->xfer_count += TxByteNbre;
- (void)USB_EPStartXfer(hpcd->Instance, ep);
- }
}
- /* Double Buffer Iso/bulk IN (bulk transfer Len > Ep_Mps) */
else
{
- (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
+ /* Manage Bulk Single Buffer Transaction */
+ if ((wEPVal & USB_EP_KIND) == 0U)
+ {
+ /* multi-packet on the NON control IN endpoint */
+ TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+
+ if (ep->xfer_len > TxPctSize)
+ {
+ ep->xfer_len -= TxPctSize;
+ }
+ else
+ {
+ ep->xfer_len = 0U;
+ }
+
+ /* Zero Length Packet? */
+ if (ep->xfer_len == 0U)
+ {
+ /* TX COMPLETE */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataInStageCallback(hpcd, ep->num);
+#else
+ HAL_PCD_DataInStageCallback(hpcd, ep->num);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Transfer is not yet Done */
+ ep->xfer_buff += TxPctSize;
+ ep->xfer_count += TxPctSize;
+ (void)USB_EPStartXfer(hpcd->Instance, ep);
+ }
+ }
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+ /* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */
+ else
+ {
+ (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
+ }
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
}
}
}
@@ -2510,6 +2600,7 @@
}
+#if (USE_USB_DOUBLE_BUFFER == 1U)
/**
* @brief Manage double buffer bulk out transaction from ISR
* @param hpcd PCD handle
@@ -2543,10 +2634,10 @@
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
}
- /* Check if Buffer1 is in blocked sate which requires to toggle */
+ /* Check if Buffer1 is in blocked state which requires to toggle */
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
{
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
+ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
}
if (count != 0U)
@@ -2578,7 +2669,7 @@
/*Need to FreeUser Buffer*/
if ((wEPVal & USB_EP_DTOG_TX) == 0U)
{
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
+ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
}
if (count != 0U)
@@ -2602,22 +2693,23 @@
PCD_EPTypeDef *ep, uint16_t wEPVal)
{
uint32_t len;
- uint16_t TxByteNbre;
+ uint16_t TxPctSize;
/* Data Buffer0 ACK received */
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
{
/* multi-packet on the NON control IN endpoint */
- TxByteNbre = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+ TxPctSize = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_len > TxByteNbre)
+ if (ep->xfer_len > TxPctSize)
{
- ep->xfer_len -= TxByteNbre;
+ ep->xfer_len -= TxPctSize;
}
else
{
ep->xfer_len = 0U;
}
+
/* Transfer is completed */
if (ep->xfer_len == 0U)
{
@@ -2633,7 +2725,7 @@
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
{
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
+ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
}
}
else /* Transfer is not yet Done */
@@ -2641,14 +2733,14 @@
/* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
{
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
+ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
}
/* Still there is data to Fill in the next Buffer */
if (ep->xfer_fill_db == 1U)
{
- ep->xfer_buff += TxByteNbre;
- ep->xfer_count += TxByteNbre;
+ ep->xfer_buff += TxPctSize;
+ ep->xfer_count += TxPctSize;
/* Calculate the len of the new buffer to fill */
if (ep->xfer_len_db >= ep->maxpacket)
@@ -2658,7 +2750,7 @@
}
else if (ep->xfer_len_db == 0U)
{
- len = TxByteNbre;
+ len = TxPctSize;
ep->xfer_fill_db = 0U;
}
else
@@ -2680,11 +2772,11 @@
else /* Data Buffer1 ACK received */
{
/* multi-packet on the NON control IN endpoint */
- TxByteNbre = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+ TxPctSize = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_len >= TxByteNbre)
+ if (ep->xfer_len >= TxPctSize)
{
- ep->xfer_len -= TxByteNbre;
+ ep->xfer_len -= TxPctSize;
}
else
{
@@ -2707,7 +2799,7 @@
/* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
{
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
+ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
}
}
else /* Transfer is not yet Done */
@@ -2715,14 +2807,14 @@
/* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
{
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
+ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
}
/* Still there is data to Fill in the next Buffer */
if (ep->xfer_fill_db == 1U)
{
- ep->xfer_buff += TxByteNbre;
- ep->xfer_count += TxByteNbre;
+ ep->xfer_buff += TxPctSize;
+ ep->xfer_count += TxPctSize;
/* Calculate the len of the new buffer to fill */
if (ep->xfer_len_db >= ep->maxpacket)
@@ -2732,7 +2824,7 @@
}
else if (ep->xfer_len_db == 0U)
{
- len = TxByteNbre;
+ len = TxPctSize;
ep->xfer_fill_db = 0U;
}
else
@@ -2756,6 +2848,7 @@
return HAL_OK;
}
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
#endif /* defined (USB) */
@@ -2772,5 +2865,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_pcd_ex.c b/Src/stm32l4xx_hal_pcd_ex.c
index a32f1f4..2b3567a 100644
--- a/Src/stm32l4xx_hal_pcd_ex.c
+++ b/Src/stm32l4xx_hal_pcd_ex.c
@@ -10,13 +10,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -164,7 +163,7 @@
/* Enable DCD : Data Contact Detect */
USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
- /* Wait Detect flag or a timeout is happen*/
+ /* Wait Detect flag or a timeout is happen */
while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U)
{
/* Check for the Timeout */
@@ -333,6 +332,7 @@
/* Configure the PMA */
ep->pmaadress = (uint16_t)pmaadress;
}
+#if (USE_USB_DOUBLE_BUFFER == 1U)
else /* USB_DBL_BUF */
{
/* Double Buffer Endpoint */
@@ -341,6 +341,7 @@
ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
}
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
return HAL_OK;
}
@@ -392,7 +393,7 @@
USB_TypeDef *USBx = hpcd->Instance;
uint32_t tickstart = HAL_GetTick();
- /* Wait Detect flag or a timeout is happen*/
+ /* Wait Detect flag or a timeout is happen */
while ((USBx->BCDR & USB_BCDR_DCDET) == 0U)
{
/* Check for the Timeout */
@@ -564,5 +565,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_pka.c b/Src/stm32l4xx_hal_pka.c
index 2c8ffef..101d091 100644
--- a/Src/stm32l4xx_hal_pka.c
+++ b/Src/stm32l4xx_hal_pka.c
@@ -9,6 +9,17 @@
* + Start an operation
* + Retrieve the operation result
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -94,7 +105,7 @@
(++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
The resulting size can be the input parameter or the input parameter size + 1 (overflow).
- (+) Arithmetic substraction using:
+ (+) Arithmetic subtraction using:
(++) HAL_PKA_Sub().
(++) HAL_PKA_Sub_IT().
(++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
@@ -114,7 +125,7 @@
(++) HAL_PKA_ModAdd_IT().
(++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
- (+) Modular substraction using:
+ (+) Modular subtraction using:
(++) HAL_PKA_ModSub().
(++) HAL_PKA_ModSub_IT().
(++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
@@ -156,7 +167,7 @@
[..]
(+) Add HAL_PKA_IRQHandler to the IRQHandler of PKA.
(+) Enable the IRQ using HAL_NVIC_EnableIRQ().
- (+) When an operation is started in interrupt mode, the function returns immediatly.
+ (+) When an operation is started in interrupt mode, the function returns immediately.
(+) When the operation is completed, the callback HAL_PKA_OperationCpltCallback is called.
(+) When an error is encountered, the callback HAL_PKA_ErrorCallback is called.
(+) To stop any operation in interrupt mode, use HAL_PKA_Abort().
@@ -174,11 +185,11 @@
The compilation flag USE_HAL_PKA_REGISTER_CALLBACKS, when set to 1,
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_PKA_RegisterCallback()
+ Use Functions HAL_PKA_RegisterCallback()
to register an interrupt callback.
[..]
- Function @ref HAL_PKA_RegisterCallback() allows to register following callbacks:
+ Function HAL_PKA_RegisterCallback() allows to register following callbacks:
(+) OperationCpltCallback : callback for End of operation.
(+) ErrorCallback : callback for error detection.
(+) MspInitCallback : callback for Msp Init.
@@ -187,11 +198,11 @@
and a pointer to the user callback function.
[..]
- Use function @ref HAL_PKA_UnRegisterCallback to reset a callback to the default
+ Use function HAL_PKA_UnRegisterCallback to reset a callback to the default
weak function.
[..]
- @ref HAL_PKA_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ HAL_PKA_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) OperationCpltCallback : callback for End of operation.
@@ -200,27 +211,27 @@
(+) MspDeInitCallback : callback for Msp DeInit.
[..]
- By default, after the @ref HAL_PKA_Init() and when the state is @ref HAL_PKA_STATE_RESET
+ By default, after the HAL_PKA_Init() and when the state is HAL_PKA_STATE_RESET
all callbacks are set to the corresponding weak functions:
- examples @ref HAL_PKA_OperationCpltCallback(), @ref HAL_PKA_ErrorCallback().
+ examples HAL_PKA_OperationCpltCallback(), HAL_PKA_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak functions in the @ref HAL_PKA_Init()/ @ref HAL_PKA_DeInit() only when
+ reset to the legacy weak functions in the HAL_PKA_Init()/ HAL_PKA_DeInit() only when
these callbacks are null (not registered beforehand).
[..]
- If MspInit or MspDeInit are not null, the @ref HAL_PKA_Init()/ @ref HAL_PKA_DeInit()
+ If MspInit or MspDeInit are not null, the HAL_PKA_Init()/ HAL_PKA_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
- Callbacks can be registered/unregistered in @ref HAL_PKA_STATE_READY state only.
+ Callbacks can be registered/unregistered in HAL_PKA_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
- in @ref HAL_PKA_STATE_READY or @ref HAL_PKA_STATE_RESET state,
+ in HAL_PKA_STATE_READY or HAL_PKA_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
[..]
Then, the user first registers the MspInit/MspDeInit user callbacks
- using @ref HAL_PKA_RegisterCallback() before calling @ref HAL_PKA_DeInit()
- or @ref HAL_PKA_Init() function.
+ using HAL_PKA_RegisterCallback() before calling HAL_PKA_DeInit()
+ or HAL_PKA_Init() function.
[..]
When the compilation flag USE_HAL_PKA_REGISTER_CALLBACKS is set to 0 or
@@ -229,17 +240,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -252,7 +252,7 @@
#if defined(PKA) && defined(HAL_PKA_MODULE_ENABLED)
/** @defgroup PKA PKA
- * @brief PKA HAL module driver.
+ * @brief PKA HAL module driver.
* @{
*/
@@ -263,14 +263,14 @@
*/
#define PKA_RAM_SIZE 894U
#define PKA_RAM_ERASE_TIMEOUT 1000U
-/**
- * @}
- */
/* Private macro -------------------------------------------------------------*/
#define __PKA_RAM_PARAM_END(TAB,INDEX) do{ \
TAB[INDEX] = 0UL; \
} while(0)
+/**
+ * @}
+ */
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -300,7 +300,8 @@
void PKA_ModRed_Set(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in);
void PKA_ModInv_Set(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in);
void PKA_MontgomeryParam_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint8_t *pOp1);
-void PKA_ARI_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint32_t *pOp1, const uint32_t *pOp2, const uint8_t *pOp3);
+void PKA_ARI_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint32_t *pOp1, const uint32_t *pOp2,
+ const uint8_t *pOp3);
/**
* @}
*/
@@ -312,8 +313,8 @@
*/
/** @defgroup PKA_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and de-initialization functions
- *
+ * @brief Initialization and de-initialization functions
+ *
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
@@ -324,9 +325,7 @@
(+) User must implement HAL_PKA_MspInit() function in which he configures
all related peripherals resources (CLOCK, IT and NVIC ).
- (+) Call the function HAL_PKA_Init() to configure the selected device with
- the selected configuration:
- (++) Security level
+ (+) Call the function HAL_PKA_Init() to configure the device.
(+) Call the function HAL_PKA_DeInit() to restore the default configuration
of the selected PKAx peripheral.
@@ -440,7 +439,7 @@
hpka->State = HAL_PKA_STATE_BUSY;
/* Reset the control register */
- /* This abort any operation in progress (PKA RAM content is not guaranted in this case) */
+ /* This abort any operation in progress (PKA RAM content is not guaranteed in this case) */
hpka->Instance->CR = 0;
/* Reset any pending flag */
@@ -518,7 +517,8 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_PKA_RegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID, pPKA_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_PKA_RegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID,
+ pPKA_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -678,8 +678,8 @@
*/
/** @defgroup PKA_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
- *
+ * @brief IO operation functions
+ *
@verbatim
===============================================================================
##### IO operation functions #####
@@ -692,7 +692,7 @@
(++) Blocking mode : The operation is performed in the polling mode.
These functions return when data operation is completed.
(++) No-Blocking mode : The operation is performed using Interrupts.
- These functions return immediatly.
+ These functions return immediately.
The end of the operation is indicated by HAL_PKA_ErrorCallback in case of error.
The end of the operation is indicated by HAL_PKA_OperationCpltCallback in case of success.
To stop any operation in interrupt mode, use HAL_PKA_Abort().
@@ -893,7 +893,8 @@
* @param out Output information
* @param outExt Additional Output information (facultative)
*/
-void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out, PKA_ECDSASignOutExtParamTypeDef *outExt)
+void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out,
+ PKA_ECDSASignOutExtParamTypeDef *outExt)
{
uint32_t size;
@@ -931,7 +932,8 @@
}
/**
- * @brief Verify the validity of a signature using elliptic curves over prime fields in non-blocking mode with Interrupt.
+ * @brief Verify the validity of a signature using elliptic curves
+ * over prime fields in non-blocking mode with Interrupt.
* @param hpka PKA handle
* @param in Input information
* @retval HAL status
@@ -1041,8 +1043,8 @@
*/
uint32_t HAL_PKA_PointCheck_IsOnCurve(PKA_HandleTypeDef const *const hpka)
{
- #define PKA_POINT_IS_ON_CURVE 0UL
- /* Invert the value of the PKA RAM containig the result of the operation */
+#define PKA_POINT_IS_ON_CURVE 0UL
+ /* Invert the value of the PKA RAM containing the result of the operation */
return (hpka->Instance->RAM[PKA_POINT_CHECK_OUT_ERROR] == PKA_POINT_IS_ON_CURVE) ? 1UL : 0UL;
}
@@ -1160,7 +1162,7 @@
}
/**
- * @brief Arithmetic substraction in blocking mode.
+ * @brief Arithmetic subtraction in blocking mode.
* @param hpka PKA handle
* @param in Input information
* @param Timeout Timeout duration
@@ -1176,7 +1178,7 @@
}
/**
- * @brief Arithmetic substraction in non-blocking mode with Interrupt.
+ * @brief Arithmetic subtraction in non-blocking mode with Interrupt.
* @param hpka PKA handle
* @param in Input information
* @retval HAL status
@@ -1315,7 +1317,7 @@
}
/**
- * @brief Modular substraction in blocking mode.
+ * @brief Modular subtraction in blocking mode.
* @param hpka PKA handle
* @param in Input information
* @param Timeout Timeout duration
@@ -1331,7 +1333,7 @@
}
/**
- * @brief Modular substraction in non-blocking mode with Interrupt.
+ * @brief Modular subtraction in non-blocking mode with Interrupt.
* @param hpka PKA handle
* @param in Input information
* @retval HAL status
@@ -1528,7 +1530,7 @@
HAL_StatusTypeDef err = HAL_OK;
/* Clear EN bit */
- /* This abort any operation in progress (PKA RAM content is not guaranted in this case) */
+ /* This abort any operation in progress (PKA RAM content is not guaranteed in this case) */
CLEAR_BIT(hpka->Instance->CR, PKA_CR_EN);
SET_BIT(hpka->Instance->CR, PKA_CR_EN);
@@ -1662,8 +1664,8 @@
*/
/** @defgroup PKA_Exported_Functions_Group3 Peripheral State and Error functions
- * @brief Peripheral State and Error functions
- *
+ * @brief Peripheral State and Error functions
+ *
@verbatim
===============================================================================
##### Peripheral State and Error functions #####
@@ -1690,7 +1692,7 @@
* @brief Return the PKA error code.
* @param hpka PKA handle
* @retval PKA error code
-*/
+ */
uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka)
{
/* Return PKA handle error code */
@@ -1973,7 +1975,8 @@
tickstart = HAL_GetTick();
/* Set the mode and deactivate the interrupts */
- MODIFY_REG(hpka->Instance->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE, mode << PKA_CR_MODE_Pos);
+ MODIFY_REG(hpka->Instance->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE,
+ mode << PKA_CR_MODE_Pos);
/* Start the computation */
hpka->Instance->CR |= PKA_CR_START;
@@ -2031,7 +2034,8 @@
hpka->ErrorCode = HAL_PKA_ERROR_NONE;
/* Set the mode and activate interrupts */
- MODIFY_REG(hpka->Instance->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE, (mode << PKA_CR_MODE_Pos) | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE);
+ MODIFY_REG(hpka->Instance->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE,
+ (mode << PKA_CR_MODE_Pos) | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE);
/* Start the computation */
hpka->Instance->CR |= PKA_CR_START;
@@ -2058,15 +2062,15 @@
/* Move the input parameters pOp1 to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT_BASE], in->pOp1, in->OpSize);
- __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT_BASE + (in->OpSize / 4UL));
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT_BASE + ((in->OpSize + 3UL) / 4UL));
/* Move the exponent to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT], in->pExp, in->expSize);
- __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT + (in->expSize / 4UL));
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT + ((in->expSize + 3UL) / 4UL));
/* Move the modulus to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MODULUS], in->pMod, in->OpSize);
- __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MODULUS + (in->OpSize / 4UL));
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MODULUS + ((in->OpSize + 3UL) / 4UL));
}
/**
@@ -2095,8 +2099,9 @@
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MODULUS + (in->OpSize / 4UL));
/* Move the Montgomery parameter to PKA RAM */
- PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM], in->pMontgomeryParam, in->expSize / 4UL);
- __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM + (in->expSize / 4UL));
+ PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM], in->pMontgomeryParam,
+ in->OpSize / 4UL);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM + (in->OpSize / 4UL));
}
@@ -2182,11 +2187,13 @@
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters public-key curve point Q coordinate xQ to PKA RAM */
- PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X], in->pPubKeyCurvePtX, in->modulusSize);
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X], in->pPubKeyCurvePtX,
+ in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters public-key curve point Q coordinate xQ to PKA RAM */
- PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y], in->pPubKeyCurvePtY, in->modulusSize);
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y], in->pPubKeyCurvePtY,
+ in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters signature part r to PKA RAM */
@@ -2305,12 +2312,12 @@
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_K + ((in->scalarMulSize + 3UL) / 4UL));
/* Move the input parameters Point P coordinate x to PKA RAM */
- PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_X], in->pointX, in->modulusSize);
- __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL));
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X], in->pointX, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters Point P coordinate y to PKA RAM */
- PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize);
- __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL));
+ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize);
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL));
}
@@ -2352,7 +2359,8 @@
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL));
/* Move the Montgomery parameter to PKA RAM */
- PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM], in->pMontgomeryParam, (in->modulusSize + 3UL) / 4UL);
+ PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM], in->pMontgomeryParam,
+ (in->modulusSize + 3UL) / 4UL);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM + ((in->modulusSize + 3UL) / 4UL));
}
/**
@@ -2404,10 +2412,22 @@
*/
void PKA_MontgomeryParam_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint8_t *pOp1)
{
+ uint32_t bytetoskip = 0UL;
+ uint32_t newSize;
+
if (pOp1 != NULL)
{
+ /* Count the number of zero bytes */
+ while ((bytetoskip < size) && (pOp1[bytetoskip] == 0UL))
+ {
+ bytetoskip++;
+ }
+
+ /* Get new size after skipping zero bytes */
+ newSize = size - bytetoskip;
+
/* Get the number of bit per operand */
- hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS] = PKA_GetOptBitSize_u8(size, *pOp1);
+ hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS] = PKA_GetOptBitSize_u8(newSize, pOp1[bytetoskip]);
/* Move the input parameters pOp1 to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_IN_MODULUS], pOp1, size);
@@ -2423,7 +2443,8 @@
* @param pOp2 Generic pointer to input data
* @param pOp3 Generic pointer to input data
*/
-void PKA_ARI_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint32_t *pOp1, const uint32_t *pOp2, const uint8_t *pOp3)
+void PKA_ARI_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint32_t *pOp1, const uint32_t *pOp2,
+ const uint8_t *pOp3)
{
/* Get the number of bit per operand */
hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_NB_BITS] = PKA_GetBitSize_u32(size);
@@ -2463,5 +2484,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_pssi.c b/Src/stm32l4xx_hal_pssi.c
index 46d9816..882e338 100644
--- a/Src/stm32l4xx_hal_pssi.c
+++ b/Src/stm32l4xx_hal_pssi.c
@@ -9,6 +9,17 @@
* + IO operation functions
* + Peripheral State and Errors functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -132,17 +143,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -1789,5 +1789,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_pwr.c b/Src/stm32l4xx_hal_pwr.c
index bee73b0..8638eec 100644
--- a/Src/stm32l4xx_hal_pwr.c
+++ b/Src/stm32l4xx_hal_pwr.c
@@ -11,13 +11,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -188,7 +187,7 @@
=========================================
[..]
(+) Entry:
- The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API
+ The Sleep mode / Low-power Sleep mode is entered through HAL_PWR_EnterSLEEPMode() API
in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
(++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
(++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
@@ -210,7 +209,7 @@
===============================
[..]
(+) Entry:
- The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:
+ The Stop 0, Stop 1 or Stop 2 modes are entered through the following API's:
(++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().
(++) HAL_PWREx_EnterSTOP2Mode() for mode 2.
(+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
@@ -244,7 +243,7 @@
and Standby circuitry.
(++) Entry:
- (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API.
+ (+++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API.
SRAM1 and register contents are lost except for registers in the Backup domain and
Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
@@ -265,7 +264,7 @@
SRAM and registers contents are lost except for backup domain registers.
(+) Entry:
- The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API.
+ The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API.
(+) Exit:
(++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
@@ -657,5 +656,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_pwr_ex.c b/Src/stm32l4xx_hal_pwr_ex.c
index 972a0d8..0b6eb2f 100644
--- a/Src/stm32l4xx_hal_pwr_ex.c
+++ b/Src/stm32l4xx_hal_pwr_ex.c
@@ -11,13 +11,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -273,7 +272,7 @@
/**
* @brief Enable battery charging.
- * When VDD is present, charge the external battery on VBAT thru an internal resistor.
+ * When VDD is present, charge the external battery on VBAT through an internal resistor.
* @param ResistorSelection specifies the resistor impedance.
* This parameter can be one of the following values:
* @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor
@@ -975,7 +974,7 @@
/* Configure EXTI 35 to 38 interrupts if so required:
- scan thru PVMType to detect which PVMx is set and
+ scan through PVMType to detect which PVMx is set and
configure the corresponding EXTI line accordingly. */
switch (sConfigPVM->PVMType)
{
@@ -1473,5 +1472,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_qspi.c b/Src/stm32l4xx_hal_qspi.c
index 6d9c715..b063f1a 100644
--- a/Src/stm32l4xx_hal_qspi.c
+++ b/Src/stm32l4xx_hal_qspi.c
@@ -14,6 +14,17 @@
* + Errors management and abort functionality
*
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
@@ -111,7 +122,7 @@
=================================================
[..]
(#) HAL_QSPI_GetError() function gives the error raised during the last operation.
- (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
+ (#) HAL_QSPI_Abort() and HAL_QSPI_Abort_IT() functions aborts any on-going operation and
flushes the fifo :
(++) In polling mode, the output of the function is done when the transfer
complete bit is set and the busy bit cleared.
@@ -133,7 +144,7 @@
The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_QSPI_RegisterCallback() to register a user callback,
+ Use Functions HAL_QSPI_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) ErrorCallback : callback when error occurs.
(+) AbortCpltCallback : callback when abort is completed.
@@ -150,7 +161,7 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- Use function @ref HAL_QSPI_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_QSPI_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) ErrorCallback : callback when error occurs.
(+) AbortCpltCallback : callback when abort is completed.
@@ -166,12 +177,12 @@
(+) MspDeInitCallback : QSPI MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
- By default, after the @ref HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET
+ By default, after the HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_QSPI_Init
- and @ref HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_QSPI_Init and @ref HAL_QSPI_DeInit
+ reset to the legacy weak (surcharged) functions in the HAL_QSPI_Init
+ and HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_QSPI_Init and HAL_QSPI_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
@@ -179,8 +190,8 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_QSPI_RegisterCallback before calling @ref HAL_QSPI_DeInit
- or @ref HAL_QSPI_Init function.
+ using HAL_QSPI_RegisterCallback before calling HAL_QSPI_DeInit
+ or HAL_QSPI_Init function.
When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
@@ -194,17 +205,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -285,7 +285,7 @@
/**
* @brief Initialize the QSPI mode according to the specified parameters
* in the QSPI_InitTypeDef and initialize the associated handle.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
@@ -394,7 +394,7 @@
/**
* @brief De-Initialize the QSPI peripheral.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
@@ -435,7 +435,7 @@
/**
* @brief Initialize the QSPI MSP.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
@@ -450,7 +450,7 @@
/**
* @brief DeInitialize the QSPI MSP.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
@@ -489,7 +489,7 @@
/**
* @brief Handle QSPI interrupt request.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
@@ -738,7 +738,7 @@
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
-
+
/* Error callback */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
hqspi->ErrorCallback(hqspi);
@@ -783,9 +783,9 @@
/**
* @brief Set the command configuration.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @param cmd : structure that contains the command configuration information
- * @param Timeout : Timeout duration
+ * @param Timeout Timeout duration
* @note This function is used only in Indirect Read or Write Modes
* @retval HAL status
*/
@@ -873,8 +873,8 @@
/**
* @brief Set the command configuration in interrupt mode.
- * @param hqspi : QSPI handle
- * @param cmd : structure that contains the command configuration information
+ * @param hqspi QSPI handle
+ * @param cmd structure that contains the command configuration information
* @note This function is used only in Indirect Read or Write Modes
* @retval HAL status
*/
@@ -972,9 +972,9 @@
/**
* @brief Transmit an amount of data in blocking mode.
- * @param hqspi : QSPI handle
- * @param pData : pointer to data buffer
- * @param Timeout : Timeout duration
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer
+ * @param Timeout Timeout duration
* @note This function is used only in Indirect Write Mode
* @retval HAL status
*/
@@ -1059,9 +1059,9 @@
/**
* @brief Receive an amount of data in blocking mode.
- * @param hqspi : QSPI handle
- * @param pData : pointer to data buffer
- * @param Timeout : Timeout duration
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer
+ * @param Timeout Timeout duration
* @note This function is used only in Indirect Read Mode
* @retval HAL status
*/
@@ -1149,8 +1149,8 @@
/**
* @brief Send an amount of data in non-blocking mode with interrupt.
- * @param hqspi : QSPI handle
- * @param pData : pointer to data buffer
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer
* @note This function is used only in Indirect Write Mode
* @retval HAL status
*/
@@ -1209,8 +1209,8 @@
/**
* @brief Receive an amount of data in non-blocking mode with interrupt.
- * @param hqspi : QSPI handle
- * @param pData : pointer to data buffer
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer
* @note This function is used only in Indirect Read Mode
* @retval HAL status
*/
@@ -1273,8 +1273,8 @@
/**
* @brief Send an amount of data in non-blocking mode with DMA.
- * @param hqspi : QSPI handle
- * @param pData : pointer to data buffer
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer
* @note This function is used only in Indirect Write Mode
* @note If DMA peripheral access is configured as halfword, the number
* of data and the fifo threshold should be aligned on halfword
@@ -1377,10 +1377,10 @@
{
/* Process unlocked */
__HAL_UNLOCK(hqspi);
-
+
/* Enable the QSPI transfer error Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
-
+
/* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
}
@@ -1417,8 +1417,8 @@
/**
* @brief Receive an amount of data in non-blocking mode with DMA.
- * @param hqspi : QSPI handle
- * @param pData : pointer to data buffer.
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer.
* @note This function is used only in Indirect Read Mode
* @note If DMA peripheral access is configured as halfword, the number
* of data and the fifo threshold should be aligned on halfword
@@ -1525,10 +1525,10 @@
/* Process unlocked */
__HAL_UNLOCK(hqspi);
-
+
/* Enable the QSPI transfer error Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
-
+
/* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
}
@@ -1565,10 +1565,10 @@
/**
* @brief Configure the QSPI Automatic Polling Mode in blocking mode.
- * @param hqspi : QSPI handle
- * @param cmd : structure that contains the command configuration information.
- * @param cfg : structure that contains the polling configuration information.
- * @param Timeout : Timeout duration
+ * @param hqspi QSPI handle
+ * @param cmd structure that contains the command configuration information.
+ * @param cfg structure that contains the polling configuration information.
+ * @param Timeout Timeout duration
* @note This function is used only in Automatic Polling Mode
* @retval HAL status
*/
@@ -1666,9 +1666,9 @@
/**
* @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
- * @param hqspi : QSPI handle
- * @param cmd : structure that contains the command configuration information.
- * @param cfg : structure that contains the polling configuration information.
+ * @param hqspi QSPI handle
+ * @param cmd structure that contains the command configuration information.
+ * @param cfg structure that contains the polling configuration information.
* @note This function is used only in Automatic Polling Mode
* @retval HAL status
*/
@@ -1770,9 +1770,9 @@
/**
* @brief Configure the Memory Mapped mode.
- * @param hqspi : QSPI handle
- * @param cmd : structure that contains the command configuration information.
- * @param cfg : structure that contains the memory mapped configuration information.
+ * @param hqspi QSPI handle
+ * @param cmd structure that contains the command configuration information.
+ * @param cfg structure that contains the memory mapped configuration information.
* @note This function is used only in Memory mapped Mode
* @retval HAL status
*/
@@ -1859,7 +1859,7 @@
/**
* @brief Transfer Error callback.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
@@ -1874,7 +1874,7 @@
/**
* @brief Abort completed callback.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1889,7 +1889,7 @@
/**
* @brief Command completed callback.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1904,7 +1904,7 @@
/**
* @brief Rx Transfer completed callback.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1919,7 +1919,7 @@
/**
* @brief Tx Transfer completed callback.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1934,7 +1934,7 @@
/**
* @brief Rx Half Transfer completed callback.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1949,7 +1949,7 @@
/**
* @brief Tx Half Transfer completed callback.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1964,7 +1964,7 @@
/**
* @brief FIFO Threshold callback.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
@@ -1979,7 +1979,7 @@
/**
* @brief Status Match callback.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
@@ -1994,7 +1994,7 @@
/**
* @brief Timeout callback.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
@@ -2010,8 +2010,8 @@
/**
* @brief Register a User QSPI Callback
* To be used instead of the weak (surcharged) predefined callback
- * @param hqspi : QSPI handle
- * @param CallbackId : ID of the callback to be registered
+ * @param hqspi QSPI handle
+ * @param CallbackId ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID
* @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID
@@ -2025,7 +2025,7 @@
* @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID
* @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID
* @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID
- * @param pCallback : pointer to the Callback function
+ * @param pCallback pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback)
@@ -2124,8 +2124,8 @@
/**
* @brief Unregister a User QSPI Callback
* QSPI Callback is redirected to the weak (surcharged) predefined callback
- * @param hqspi : QSPI handle
- * @param CallbackId : ID of the callback to be unregistered
+ * @param hqspi QSPI handle
+ * @param CallbackId ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID
* @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID
@@ -2252,7 +2252,7 @@
/**
* @brief Return the QSPI handle state.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval HAL state
*/
HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
@@ -2263,7 +2263,7 @@
/**
* @brief Return the QSPI error code.
-* @param hqspi : QSPI handle
+* @param hqspi QSPI handle
* @retval QSPI Error Code
*/
uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
@@ -2273,7 +2273,7 @@
/**
* @brief Abort the current transmission.
-* @param hqspi : QSPI handle
+* @param hqspi QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
@@ -2329,7 +2329,7 @@
/**
* @brief Abort the current transmission (non-blocking function)
-* @param hqspi : QSPI handle
+* @param hqspi QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
@@ -2359,7 +2359,7 @@
{
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
-
+
/* Abort Complete callback */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
hqspi->AbortCpltCallback(hqspi);
@@ -2384,8 +2384,8 @@
}
/** @brief Set QSPI timeout.
- * @param hqspi : QSPI handle.
- * @param Timeout : Timeout for the QSPI memory access.
+ * @param hqspi QSPI handle.
+ * @param Timeout Timeout for the QSPI memory access.
* @retval None
*/
void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
@@ -2394,8 +2394,8 @@
}
/** @brief Set QSPI Fifo threshold.
- * @param hqspi : QSPI handle.
- * @param Threshold : Threshold of the Fifo (value between 1 and 16).
+ * @param hqspi QSPI handle.
+ * @param Threshold Threshold of the Fifo (value between 1 and 16).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
@@ -2427,7 +2427,7 @@
}
/** @brief Get QSPI Fifo threshold.
- * @param hqspi : QSPI handle.
+ * @param hqspi QSPI handle.
* @retval Fifo threshold (value between 1 and 16)
*/
uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
@@ -2437,8 +2437,8 @@
#if defined(QUADSPI_CR_DFM)
/** @brief Set FlashID.
- * @param hqspi : QSPI handle.
- * @param FlashID : Index of the flash memory to be accessed.
+ * @param hqspi QSPI handle.
+ * @param FlashID Index of the flash memory to be accessed.
* This parameter can be a value of @ref QSPI_Flash_Select.
* @note The FlashID is ignored when dual flash mode is enabled.
* @retval HAL status
@@ -2488,7 +2488,7 @@
/**
* @brief DMA QSPI receive process complete callback.
- * @param hdma : DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
@@ -2502,7 +2502,7 @@
/**
* @brief DMA QSPI transmit process complete callback.
- * @param hdma : DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
@@ -2516,7 +2516,7 @@
/**
* @brief DMA QSPI receive process half complete callback.
- * @param hdma : DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
@@ -2532,7 +2532,7 @@
/**
* @brief DMA QSPI transmit process half complete callback.
- * @param hdma : DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
@@ -2548,7 +2548,7 @@
/**
* @brief DMA QSPI communication error callback.
- * @param hdma : DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
@@ -2569,7 +2569,7 @@
/**
* @brief DMA QSPI abort complete callback.
- * @param hdma : DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
@@ -2608,11 +2608,11 @@
/**
* @brief Wait for a flag state until timeout.
- * @param hqspi : QSPI handle
- * @param Flag : Flag checked
- * @param State : Value of the flag expected
- * @param Tickstart : Tick start value
- * @param Timeout : Duration of the timeout
+ * @param hqspi QSPI handle
+ * @param Flag Flag checked
+ * @param State Value of the flag expected
+ * @param Tickstart Tick start value
+ * @param Timeout Duration of the timeout
* @retval HAL status
*/
static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
@@ -2638,9 +2638,9 @@
/**
* @brief Configure the communication registers.
- * @param hqspi : QSPI handle
- * @param cmd : structure that contains the command configuration information
- * @param FunctionalMode : functional mode to configured
+ * @param hqspi QSPI handle
+ * @param cmd structure that contains the command configuration information
+ * @param FunctionalMode functional mode to configured
* This parameter can be one of the following values:
* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
@@ -2803,6 +2803,4 @@
* @}
*/
-#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+#endif /* defined(QUADSPI) */
diff --git a/Src/stm32l4xx_hal_rcc.c b/Src/stm32l4xx_hal_rcc.c
index 552a471..71da794 100644
--- a/Src/stm32l4xx_hal_rcc.c
+++ b/Src/stm32l4xx_hal_rcc.c
@@ -38,14 +38,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -134,7 +132,7 @@
(+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through
the PLL as System clock source.
- (+) MSI (Mutiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ.
+ (+) MSI (Multiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ.
It can be used to generate the clock for the USB OTG FS (48 MHz).
The number of flash wait states is automatically adjusted when MSI range is updated with
HAL_RCC_OscConfig() and the MSI is used as System clock source.
@@ -940,14 +938,20 @@
}
/* Configure the main PLL clock source, multiplication and division factors. */
+#if defined(RCC_PLLP_SUPPORT)
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
RCC_OscInitStruct->PLL.PLLM,
RCC_OscInitStruct->PLL.PLLN,
-#if defined(RCC_PLLP_SUPPORT)
RCC_OscInitStruct->PLL.PLLP,
-#endif
RCC_OscInitStruct->PLL.PLLQ,
RCC_OscInitStruct->PLL.PLLR);
+#else
+ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ RCC_OscInitStruct->PLL.PLLM,
+ RCC_OscInitStruct->PLL.PLLN,
+ RCC_OscInitStruct->PLL.PLLQ,
+ RCC_OscInitStruct->PLL.PLLR);
+#endif
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
@@ -1303,7 +1307,7 @@
[..]
This subsection provides a set of functions allowing to:
- (+) Ouput clock to MCO pin.
+ (+) Output clock to MCO pin.
(+) Retrieve current clock frequencies.
(+) Enable the Clock Security System.
@@ -1354,7 +1358,7 @@
/* MCO Clock Enable */
__MCO1_CLK_ENABLE();
- /* Configue the MCO1 pin in alternate function mode */
+ /* Configure the MCO1 pin in alternate function mode */
GPIO_InitStruct.Pin = MCO1_PIN;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
@@ -1751,7 +1755,26 @@
}
/**
- * @}
+ * @brief Get and clear reset flags
+ * @param None
+ * @note Once reset flags are retrieved, this API is clearing them in order
+ * to isolate next reset reason.
+ * @retval can be a combination of @ref RCC_Reset_Flag
+ */
+uint32_t HAL_RCC_GetResetSource(void)
+{
+ uint32_t reset;
+
+ /* Get all reset flags */
+ reset = RCC->CSR & RCC_RESET_FLAG_ALL;
+
+ /* Clear Reset flags */
+ RCC->CSR |= RCC_CSR_RMVF;
+
+ return reset;
+}
+
+/** * @}
*/
/**
@@ -1923,4 +1946,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_rcc_ex.c b/Src/stm32l4xx_hal_rcc_ex.c
index 135f9f4..2457b7f 100644
--- a/Src/stm32l4xx_hal_rcc_ex.c
+++ b/Src/stm32l4xx_hal_rcc_ex.c
@@ -12,14 +12,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -2414,7 +2412,7 @@
/* LSCO Pin Clock Enable */
__LSCO_CLK_ENABLE();
- /* Configue the LSCO pin in analog mode */
+ /* Configure the LSCO pin in analog mode */
GPIO_InitStruct.Pin = LSCO_PIN;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
@@ -2533,7 +2531,7 @@
##### Extended Clock Recovery System Control functions #####
===============================================================================
[..]
- For devices with Clock Recovery System feature (CRS), RCC Extention HAL driver can be used as follows:
+ For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:
(#) In System clock config, HSI48 needs to be enabled
@@ -3313,7 +3311,7 @@
uint32_t pllp = 0U;
#endif /* RCC_PLLP_SUPPORT */
- /* Handle SAIs */
+ /* Handle SAIx */
if(PeriphClk == RCC_PERIPHCLK_SAI1)
{
srcclk = __HAL_RCC_GET_SAI1_SOURCE();
@@ -3551,5 +3549,4 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_rng.c b/Src/stm32l4xx_hal_rng.c
index 4930f20..336a66f 100644
--- a/Src/stm32l4xx_hal_rng.c
+++ b/Src/stm32l4xx_hal_rng.c
@@ -9,6 +9,17 @@
* + Peripheral Control functions
* + Peripheral State functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -31,8 +42,8 @@
allows the user to configure dynamically the driver callbacks.
[..]
- Use Function @ref HAL_RNG_RegisterCallback() to register a user callback.
- Function @ref HAL_RNG_RegisterCallback() allows to register following callbacks:
+ Use Function HAL_RNG_RegisterCallback() to register a user callback.
+ Function HAL_RNG_RegisterCallback() allows to register following callbacks:
(+) ErrorCallback : RNG Error Callback.
(+) MspInitCallback : RNG MspInit.
(+) MspDeInitCallback : RNG MspDeInit.
@@ -40,9 +51,9 @@
and a pointer to the user callback function.
[..]
- Use function @ref HAL_RNG_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
- @ref HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) ErrorCallback : RNG Error Callback.
@@ -51,16 +62,16 @@
[..]
For specific callback ReadyDataCallback, use dedicated register callbacks:
- respectively @ref HAL_RNG_RegisterReadyDataCallback() , @ref HAL_RNG_UnRegisterReadyDataCallback().
+ respectively HAL_RNG_RegisterReadyDataCallback() , HAL_RNG_UnRegisterReadyDataCallback().
[..]
- By default, after the @ref HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET
+ By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET
all callbacks are set to the corresponding weak (surcharged) functions:
- example @ref HAL_RNG_ErrorCallback().
+ example HAL_RNG_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_RNG_Init()
- and @ref HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_RNG_Init() and @ref HAL_RNG_DeInit()
+ reset to the legacy weak (surcharged) functions in the HAL_RNG_Init()
+ and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
@@ -69,8 +80,8 @@
in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user)
MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_RNG_RegisterCallback() before calling @ref HAL_RNG_DeInit()
- or @ref HAL_RNG_Init() function.
+ using HAL_RNG_RegisterCallback() before calling HAL_RNG_DeInit()
+ or HAL_RNG_Init() function.
[..]
When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or
@@ -79,17 +90,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -155,6 +155,9 @@
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
{
uint32_t tickstart;
+#if defined(RNG_CR_CONDRST)
+ uint32_t cr_value;
+#endif /* RNG_CR_CONDRST */
/* Check the RNG handle allocation */
if (hrng == NULL)
{
@@ -201,8 +204,23 @@
/* Disable RNG */
__HAL_RNG_DISABLE(hrng);
- /* Clock Error Detection Configuration when CONDRT bit is set to 1 */
- MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST);
+ /* RNG CR register configuration. Set value in CR register for CONFIG 1, CONFIG 2 and CONFIG 3 values */
+ cr_value = (uint32_t) (RNG_CR_CONFIG_VAL);
+
+ /* Configuration of
+ - Clock Error Detection
+ - CONFIG1, CONFIG2, CONFIG3 fields
+ when CONDRT bit is set to 1 */
+ MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST | RNG_CR_RNG_CONFIG1
+ | RNG_CR_RNG_CONFIG2 | RNG_CR_RNG_CONFIG3,
+ (uint32_t) (RNG_CR_CONDRST | hrng->Init.ClockErrorDetection | cr_value));
+
+#if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
+ /*!< magic number must be written immediately before to RNG_HTCRG */
+ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1);
+ /* for best latency and to be compliant with NIST */
+ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG);
+#endif /* RNG_VER_3_2 || RNG_VER_3_1 || RNG_VER_3_0 */
/* Writing bits CONDRST=0*/
CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
@@ -215,9 +233,13 @@
{
if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
{
- hrng->State = HAL_RNG_STATE_READY;
- hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
- return HAL_ERROR;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
+ {
+ hrng->State = HAL_RNG_STATE_READY;
+ hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+ return HAL_ERROR;
+ }
}
}
#else
@@ -243,9 +265,13 @@
{
if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
{
- hrng->State = HAL_RNG_STATE_ERROR;
- hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
- return HAL_ERROR;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET)
+ {
+ hrng->State = HAL_RNG_STATE_ERROR;
+ hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+ return HAL_ERROR;
+ }
}
}
@@ -291,18 +317,22 @@
{
if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
{
- hrng->State = HAL_RNG_STATE_READY;
- hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
- /* Process Unlocked */
- __HAL_UNLOCK(hrng);
- return HAL_ERROR;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
+ {
+ hrng->State = HAL_RNG_STATE_READY;
+ hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
+ return HAL_ERROR;
+ }
}
}
#else
#if defined(RNG_CR_CED)
/* Clear Clock Error Detection bit */
CLEAR_BIT(hrng->Instance->CR, RNG_CR_CED);
-#endif /* defined(RNG_CR_CED) */
+#endif /* RNG_CR_CED */
#endif /* RNG_CR_CONDRST */
/* Disable the RNG Peripheral */
CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
@@ -957,5 +987,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_rng_ex.c b/Src/stm32l4xx_hal_rng_ex.c
index 5273aed..8788784 100644
--- a/Src/stm32l4xx_hal_rng_ex.c
+++ b/Src/stm32l4xx_hal_rng_ex.c
@@ -11,13 +11,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -46,9 +45,10 @@
/** @addtogroup RNGEx_Private_Defines
* @{
*/
-/* Health test control register information to use in CCM algorithm */
-#define RNG_HTCFG 0x00005A4EU /*!< for best latency and To be compliant with NIST */
-#define RNG_HTCFG_1 0x17590ABCU /*!< magic number */
+/* Health test control register information to use in CCM algorithm are defined in CMSIS Device file.
+ - RNG_HTCFG : Default HTCR register value for best latency and NIST Compliance
+ - RNG_HTCFG_1 : Magic number value that must be written to RNG_HTCR register
+ immediately before reading or writing RNG_HTCR register */
/**
* @}
*/
@@ -126,51 +126,51 @@
/* Disable RNG */
__HAL_RNG_DISABLE(hrng);
- /* RNG CR register configuration. Set value in CR register for :
+ /* RNG CR register configuration. Set value in CR register for :
- NIST Compliance setting
- Clock divider value
- CONFIG 1, CONFIG 2 and CONFIG 3 values */
- cr_value = (uint32_t) ( pConf->ClockDivider | pConf->NistCompliance
- | (pConf->Config1 << RNG_CR_RNG_CONFIG1_Pos)
- | (pConf->Config2 << RNG_CR_RNG_CONFIG2_Pos)
- | (pConf->Config3 << RNG_CR_RNG_CONFIG3_Pos));
+ cr_value = (uint32_t) ( pConf->ClockDivider | pConf->NistCompliance
+ | (pConf->Config1 << RNG_CR_RNG_CONFIG1_Pos)
+ | (pConf->Config2 << RNG_CR_RNG_CONFIG2_Pos)
+ | (pConf->Config3 << RNG_CR_RNG_CONFIG3_Pos));
- MODIFY_REG(hrng->Instance->CR, RNG_CR_NISTC | RNG_CR_CLKDIV | RNG_CR_RNG_CONFIG1
- | RNG_CR_RNG_CONFIG2 | RNG_CR_RNG_CONFIG3,
- (uint32_t) (RNG_CR_CONDRST | cr_value));
+ MODIFY_REG(hrng->Instance->CR, RNG_CR_NISTC | RNG_CR_CLKDIV | RNG_CR_RNG_CONFIG1
+ | RNG_CR_RNG_CONFIG2 | RNG_CR_RNG_CONFIG3,
+ (uint32_t) (RNG_CR_CONDRST | cr_value));
#if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
-/*!< magic number must be written immediately before to RNG_HTCRG */
-WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1);
-/* for best latency and to be compliant with NIST */
-WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG);
+ /*!< magic number must be written immediately before to RNG_HTCRG */
+ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1);
+ /* for best latency and to be compliant with NIST */
+ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG);
#endif
- /* Writing bits CONDRST=0*/
- CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* Writing bits CONDRST=0*/
+ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
+ /* Get tick */
+ tickstart = HAL_GetTick();
- /* Wait for conditioning reset process to be completed */
- while(HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
- {
- if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
+ /* Wait for conditioning reset process to be completed */
+ while(HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
{
- hrng->State = HAL_RNG_STATE_READY;
- hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
- return HAL_ERROR;
+ if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
+ {
+ hrng->State = HAL_RNG_STATE_READY;
+ hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+ return HAL_ERROR;
+ }
}
- }
- /* Enable RNG */
- __HAL_RNG_ENABLE(hrng);
+ /* Enable RNG */
+ __HAL_RNG_ENABLE(hrng);
- /* Initialize the RNG state */
- hrng->State = HAL_RNG_STATE_READY;
+ /* Initialize the RNG state */
+ hrng->State = HAL_RNG_STATE_READY;
- /* function status */
- status = HAL_OK;
+ /* function status */
+ status = HAL_OK;
}
else
{
@@ -235,7 +235,7 @@
/**
* @brief RNG current configuration lock.
* @note This function allows to lock RNG peripheral configuration.
- * Once locked, HW RNG reset has to be perfomed prior any further
+ * Once locked, HW RNG reset has to be performed prior any further
* configuration update.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
@@ -296,5 +296,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_rtc.c b/Src/stm32l4xx_hal_rtc.c
index 86c8335..d0c9f1b 100644
--- a/Src/stm32l4xx_hal_rtc.c
+++ b/Src/stm32l4xx_hal_rtc.c
@@ -15,6 +15,17 @@
* + RTC Tamper and TimeStamp Pins Selection
* + Interrupts and flags management
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
===============================================================================
##### RTC Operating Condition #####
@@ -101,10 +112,10 @@
[..]
The compilation define USE_RTC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback.
+ Use Function HAL_RTC_RegisterCallback() to register an interrupt callback.
[..]
- Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks:
+ Function HAL_RTC_RegisterCallback() allows to register following callbacks:
(+) AlarmAEventCallback : RTC Alarm A Event callback.
(+) AlarmBEventCallback : RTC Alarm B Event callback.
(+) TimeStampEventCallback : RTC TimeStamp Event callback.
@@ -121,9 +132,9 @@
and a pointer to the user callback function.
[..]
- Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_RTC_UnRegisterCallback() to reset a callback to the default
weak function.
- @ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) AlarmAEventCallback : RTC Alarm A Event callback.
@@ -140,13 +151,13 @@
(+) MspDeInitCallback : RTC MspDeInit callback.
[..]
- By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
+ By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
all callbacks are set to the corresponding weak functions :
- examples @ref AlarmAEventCallback(), @ref TimeStampEventCallback().
+ examples AlarmAEventCallback(), TimeStampEventCallback().
Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function
- in the @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() only when these callbacks are null
+ in the HAL_RTC_Init()/HAL_RTC_DeInit() only when these callbacks are null
(not registered beforehand).
- If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit()
+ If not, MspInit or MspDeInit are not null, HAL_RTC_Init()/HAL_RTC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
[..]
@@ -155,26 +166,15 @@
in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit()
- or @ref HAL_RTC_Init() function.
+ using HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit()
+ or HAL_RTC_Init() function.
[..]
When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ @endverbatim
******************************************************************************
*/
@@ -362,7 +362,7 @@
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
- hrtc->State = HAL_RTC_STATE_READY;
+ hrtc->State = HAL_RTC_STATE_READY;
}
}
}
@@ -2274,23 +2274,21 @@
*/
void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc)
{
- UNUSED(hrtc);
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- SET_BIT(RTC->CR, RTC_CR_ADD1H);
+ SET_BIT(hrtc->Instance->CR, RTC_CR_ADD1H);
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
}
/**
- * @brief Daylight Saving Time, Substract one hour from the calendar in one
+ * @brief Daylight Saving Time, Subtract one hour from the calendar in one
* single operation without going through the initialization procedure.
* @param hrtc RTC handle
* @retval None
*/
void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc)
{
- UNUSED(hrtc);
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- SET_BIT(RTC->CR, RTC_CR_SUB1H);
+ SET_BIT(hrtc->Instance->CR, RTC_CR_SUB1H);
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
}
@@ -2302,9 +2300,8 @@
*/
void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc)
{
- UNUSED(hrtc);
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- SET_BIT(RTC->CR, RTC_CR_BKP);
+ SET_BIT(hrtc->Instance->CR, RTC_CR_BKP);
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
}
@@ -2315,9 +2312,8 @@
*/
void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc)
{
- UNUSED(hrtc);
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- CLEAR_BIT(RTC->CR, RTC_CR_BKP);
+ CLEAR_BIT(hrtc->Instance->CR, RTC_CR_BKP);
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
}
@@ -2328,8 +2324,7 @@
*/
uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc)
{
- UNUSED(hrtc);
- return READ_BIT(RTC->CR, RTC_CR_BKP);
+ return READ_BIT(hrtc->Instance->CR, RTC_CR_BKP);
}
/**
@@ -2701,5 +2696,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_rtc_ex.c b/Src/stm32l4xx_hal_rtc_ex.c
index 010084d..d13157f 100644
--- a/Src/stm32l4xx_hal_rtc_ex.c
+++ b/Src/stm32l4xx_hal_rtc_ex.c
@@ -11,6 +11,17 @@
* + Extended Control functions
* + Extended RTC features functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -93,18 +104,7 @@
(+) STM32L412xx and STM32L422xx only : Before calling these functions you have to call HAL_RTC_Init() in order to
perform TAMP base address offset calculation.
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ @endverbatim
******************************************************************************
*/
@@ -515,14 +515,14 @@
#else
HAL_RTCEx_TimeStampEventCallback(hrtc);
#endif
- /* Not immediatly clear flags because the content of RTC_TSTR and RTC_TSDR arecleared when TSF bit is reset.*/
+ /* Not immediately clear flags because the content of RTC_TSTR and RTC_TSDR arecleared when TSF bit is reset.*/
hrtc->Instance->SCR = RTC_SCR_CTSF;
}
/* Get interrupt status */
uint32_t tmp = tamp->MISR;
- /* Immediatly clear flags */
+ /* Immediately clear flags */
tamp->SCR = tmp;
#if defined(RTC_TAMPER1_SUPPORT)
@@ -1613,7 +1613,7 @@
{
if ((RTC->MISR & RTC_MISR_SSRUMF) != 0u)
{
- /* Immediatly clear flags */
+ /* Immediately clear flags */
RTC->SCR = RTC_SCR_CSSRUF;
/* SSRU callback */
@@ -1847,7 +1847,7 @@
(RTC_TAMPCR_TAMP1E | RTC_TAMPCR_TAMP1TRG | RTC_TAMPCR_TAMPIE | RTC_TAMPCR_TAMP1IE | RTC_TAMPCR_TAMP1NOERASE | RTC_TAMPCR_TAMP1MF), \
sTamper->Tamper | \
(sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE ? 0U : RTC_TAMPCR_TAMP1TRG) | \
- (sTamper->NoErase == RTC_TAMPER_ERASE_BACKUP_ENABLE ? 0U : RTC_TAMPCR_TAMP1NOERASE ) | \
+ (sTamper->NoErase == RTC_TAMPER_ERASE_BACKUP_ENABLE ? 0U : RTC_TAMPCR_TAMP1NOERASE) | \
(sTamper->MaskFlag == RTC_TAMPERMASK_FLAG_ENABLE ? RTC_TAMPCR_TAMP1MF : 0U) \
);
}
@@ -1860,7 +1860,7 @@
(RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP2TRG | RTC_TAMPCR_TAMPIE | RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP2NOERASE | RTC_TAMPCR_TAMP2MF), \
sTamper->Tamper | \
(sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE ? 0U : RTC_TAMPCR_TAMP2TRG) | \
- (sTamper->NoErase == RTC_TAMPER_ERASE_BACKUP_ENABLE ? 0U : RTC_TAMPCR_TAMP2NOERASE ) | \
+ (sTamper->NoErase == RTC_TAMPER_ERASE_BACKUP_ENABLE ? 0U : RTC_TAMPCR_TAMP2NOERASE) | \
(sTamper->MaskFlag == RTC_TAMPERMASK_FLAG_ENABLE ? RTC_TAMPCR_TAMP2MF : 0U) \
);
}
@@ -1873,7 +1873,7 @@
(RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP3TRG | RTC_TAMPCR_TAMPIE | RTC_TAMPCR_TAMP3IE | RTC_TAMPCR_TAMP3NOERASE | RTC_TAMPCR_TAMP3MF), \
sTamper->Tamper | \
(sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE ? 0U : RTC_TAMPCR_TAMP3TRG) | \
- (sTamper->NoErase == RTC_TAMPER_ERASE_BACKUP_ENABLE ? 0U : RTC_TAMPCR_TAMP3NOERASE ) | \
+ (sTamper->NoErase == RTC_TAMPER_ERASE_BACKUP_ENABLE ? 0U : RTC_TAMPCR_TAMP3NOERASE) | \
(sTamper->MaskFlag == RTC_TAMPERMASK_FLAG_ENABLE ? RTC_TAMPCR_TAMP3MF : 0U) \
);
}
@@ -1884,10 +1884,10 @@
(RTC_TAMPCR_TAMPTS | RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPPRCH | RTC_TAMPCR_TAMPPUDIS), \
sTamper->Filter | sTamper->SamplingFrequency | sTamper->PrechargeDuration | sTamper->TamperPullUp | \
sTamper->TimeStampOnTamperDetection \
- );
+ );
/* Set register */
- WRITE_REG (hrtc->Instance->TAMPCR, tmpreg);
+ WRITE_REG(hrtc->Instance->TAMPCR, tmpreg);
hrtc->State = HAL_RTC_STATE_READY;
@@ -2012,7 +2012,7 @@
(RTC_TAMPCR_TAMP1E | RTC_TAMPCR_TAMP1TRG | RTC_TAMPCR_TAMPIE | RTC_TAMPCR_TAMP1IE | RTC_TAMPCR_TAMP1NOERASE | RTC_TAMPCR_TAMP1MF), \
sTamper->Tamper | sTamper->Interrupt | \
(sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE ? 0U : RTC_TAMPCR_TAMP1TRG) | \
- (sTamper->NoErase == RTC_TAMPER_ERASE_BACKUP_ENABLE ? 0U : RTC_TAMPCR_TAMP1NOERASE ) | \
+ (sTamper->NoErase == RTC_TAMPER_ERASE_BACKUP_ENABLE ? 0U : RTC_TAMPCR_TAMP1NOERASE) | \
(sTamper->MaskFlag == RTC_TAMPERMASK_FLAG_ENABLE ? RTC_TAMPCR_TAMP1MF : 0U) \
);
}
@@ -2025,7 +2025,7 @@
(RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP2TRG | RTC_TAMPCR_TAMPIE | RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP2NOERASE | RTC_TAMPCR_TAMP2MF), \
sTamper->Tamper | sTamper->Interrupt | \
(sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE ? 0U : RTC_TAMPCR_TAMP2TRG) | \
- (sTamper->NoErase == RTC_TAMPER_ERASE_BACKUP_ENABLE ? 0U : RTC_TAMPCR_TAMP2NOERASE ) | \
+ (sTamper->NoErase == RTC_TAMPER_ERASE_BACKUP_ENABLE ? 0U : RTC_TAMPCR_TAMP2NOERASE) | \
(sTamper->MaskFlag == RTC_TAMPERMASK_FLAG_ENABLE ? RTC_TAMPCR_TAMP2MF : 0U) \
);
}
@@ -2038,7 +2038,7 @@
(RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP3TRG | RTC_TAMPCR_TAMPIE | RTC_TAMPCR_TAMP3IE | RTC_TAMPCR_TAMP3NOERASE | RTC_TAMPCR_TAMP3MF), \
sTamper->Tamper | sTamper->Interrupt | \
(sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE ? 0U : RTC_TAMPCR_TAMP3TRG) | \
- (sTamper->NoErase == RTC_TAMPER_ERASE_BACKUP_ENABLE ? 0U : RTC_TAMPCR_TAMP3NOERASE ) | \
+ (sTamper->NoErase == RTC_TAMPER_ERASE_BACKUP_ENABLE ? 0U : RTC_TAMPCR_TAMP3NOERASE) | \
(sTamper->MaskFlag == RTC_TAMPERMASK_FLAG_ENABLE ? RTC_TAMPCR_TAMP3MF : 0U) \
);
}
@@ -2049,10 +2049,10 @@
(RTC_TAMPCR_TAMPTS | RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPPRCH | RTC_TAMPCR_TAMPPUDIS), \
sTamper->Filter | sTamper->SamplingFrequency | sTamper->PrechargeDuration | sTamper->TamperPullUp | \
sTamper->TimeStampOnTamperDetection \
- );
+ );
/* Set register */
- WRITE_REG (hrtc->Instance->TAMPCR, tmpreg);
+ WRITE_REG(hrtc->Instance->TAMPCR, tmpreg);
/* RTC Tamper Interrupt Configuration: EXTI configuration */
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
@@ -2412,6 +2412,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Src/stm32l4xx_hal_sai.c b/Src/stm32l4xx_hal_sai.c
index f0e8325..f13aac6 100644
--- a/Src/stm32l4xx_hal_sai.c
+++ b/Src/stm32l4xx_hal_sai.c
@@ -10,6 +10,17 @@
* + Peripheral Control functions
* + Peripheral State functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -197,18 +208,6 @@
and weak (surcharged) callbacks are used.
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -1598,7 +1597,7 @@
/* Enable SAI Tx DMA Request */
hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
- /* Wait untill FIFO is not empty */
+ /* Wait until FIFO is not empty */
while ((hsai->Instance->SR & SAI_xSR_FLVL) == SAI_FIFOSTATUS_EMPTY)
{
/* Check for the Timeout */
@@ -2852,4 +2851,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_sai_ex.c b/Src/stm32l4xx_hal_sai_ex.c
index ad7c64b..9c9e0ae 100644
--- a/Src/stm32l4xx_hal_sai_ex.c
+++ b/Src/stm32l4xx_hal_sai_ex.c
@@ -10,13 +10,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -132,4 +131,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_sd.c b/Src/stm32l4xx_hal_sd.c
index baa3f7c..c818215 100644
--- a/Src/stm32l4xx_hal_sd.c
+++ b/Src/stm32l4xx_hal_sd.c
@@ -10,6 +10,17 @@
* + Peripheral Control functions
* + Peripheral State functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -200,7 +211,7 @@
The compilation define USE_HAL_SD_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_SD_RegisterCallback() to register a user callback,
+ Use Functions HAL_SD_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) TxCpltCallback : callback when a transmission transfer is completed.
(+) RxCpltCallback : callback when a reception transfer is completed.
@@ -215,9 +226,9 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
For specific callbacks TransceiverCallback use dedicated register callbacks:
- respectively @ref HAL_SD_RegisterTransceiverCallback().
+ respectively HAL_SD_RegisterTransceiverCallback().
- Use function @ref HAL_SD_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_SD_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) TxCpltCallback : callback when a transmission transfer is completed.
(+) RxCpltCallback : callback when a reception transfer is completed.
@@ -231,14 +242,14 @@
(+) MspDeInitCallback : SD MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
For specific callbacks TransceiverCallback use dedicated unregister callbacks:
- respectively @ref HAL_SD_UnRegisterTransceiverCallback().
+ respectively HAL_SD_UnRegisterTransceiverCallback().
- By default, after the @ref HAL_SD_Init and if the state is HAL_SD_STATE_RESET
+ By default, after the HAL_SD_Init and if the state is HAL_SD_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_SD_Init
- and @ref HAL_SD_DeInit only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_SD_Init and @ref HAL_SD_DeInit
+ reset to the legacy weak (surcharged) functions in the HAL_SD_Init
+ and HAL_SD_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_SD_Init and HAL_SD_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
@@ -246,8 +257,8 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_SD_RegisterCallback before calling @ref HAL_SD_DeInit
- or @ref HAL_SD_Init function.
+ using HAL_SD_RegisterCallback before calling HAL_SD_DeInit
+ or HAL_SD_Init function.
When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
@@ -255,17 +266,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -289,7 +289,7 @@
* @{
*/
/* Frequencies used in the driver for clock divider calculation */
-#define SD_INIT_FREQ 400000U /* Initalization phase : 400 kHz max */
+#define SD_INIT_FREQ 400000U /* Initialization phase : 400 kHz max */
#define SD_NORMAL_SPEED_FREQ 25000000U /* Normal speed phase : 25 MHz max */
#define SD_HIGH_SPEED_FREQ 50000000U /* High speed phase : 50 MHz max */
/**
@@ -484,7 +484,6 @@
HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
{
uint32_t errorstate;
- HAL_StatusTypeDef status;
SD_InitTypeDef Init;
uint32_t sdmmc_clk;
@@ -521,11 +520,7 @@
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
/* Initialize SDMMC peripheral interface with default configuration */
- status = SDMMC_Init(hsd->Instance, Init);
- if(status != HAL_OK)
- {
- return HAL_ERROR;
- }
+ (void)SDMMC_Init(hsd->Instance, Init);
#if !defined(STM32L4P5xx) && !defined(STM32L4Q5xx) && !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
/* Disable SDMMC Clock */
@@ -533,11 +528,7 @@
#endif /* !STM32L4P5xx && !STM32L4Q5xx && !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */
/* Set Power State to ON */
- status = SDMMC_PowerState_ON(hsd->Instance);
- if(status != HAL_OK)
- {
- return HAL_ERROR;
- }
+ (void)SDMMC_PowerState_ON(hsd->Instance);
#if !defined(STM32L4P5xx) && !defined(STM32L4Q5xx) && !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
/* Enable SDMMC Clock */
@@ -604,7 +595,7 @@
hsd->State = HAL_SD_STATE_BUSY;
#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
- /* Desactivate the 1.8V Mode */
+ /* Deactivate the 1.8V Mode */
if(hsd->Init.Transceiver == SDMMC_TRANSCEIVER_ENABLE)
{
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
@@ -2757,7 +2748,7 @@
Init.Transceiver = hsd->Init.Transceiver;
#else
- if ((sdmmc_clk / (Init.ClockDiv + 2U)) > SD_NORMAL_SPEED_FREQ)
+ if ((sdmmc_clk / (hsd->Init.ClockDiv + 2U)) > SD_NORMAL_SPEED_FREQ)
{
Init.ClockDiv = ((sdmmc_clk / SD_NORMAL_SPEED_FREQ) - 2U);
}
@@ -4138,11 +4129,7 @@
sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;
- if ( SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK)
- {
- return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
- }
-
+ (void)SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure);
errorstate = SDMMC_CmdSwitch(hsd->Instance,SDMMC_SDR25_SWITCH_PATTERN);
if(errorstate != HAL_SD_ERROR_NONE)
@@ -4252,10 +4239,7 @@
sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;
- if ( SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK)
- {
- return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
- }
+ (void)SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure);
errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_SDR104_SWITCH_PATTERN);
if(errorstate != HAL_SD_ERROR_NONE)
@@ -4381,10 +4365,7 @@
sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;
- if ( SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK)
- {
- return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
- }
+ (void)SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure);
errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_DDR50_SWITCH_PATTERN);
if(errorstate != HAL_SD_ERROR_NONE)
@@ -4484,5 +4465,3 @@
*/
#endif /* SDMMC1 */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_sd_ex.c b/Src/stm32l4xx_hal_sd_ex.c
index 783236e..3bf2ff4 100644
--- a/Src/stm32l4xx_hal_sd_ex.c
+++ b/Src/stm32l4xx_hal_sd_ex.c
@@ -7,6 +7,17 @@
* functionalities of the Secure Digital (SD) peripheral:
* + Extended features functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -19,17 +30,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -124,8 +124,8 @@
/**
* @brief Configure DMA Dual Buffer mode. The Data transfer is managed by an Internal DMA.
* @param hsd SD handle
- * @param pDataBuffer0 Pointer to the buffer0 that will contain/receive the transfered data
- * @param pDataBuffer1 Pointer to the buffer1 that will contain/receive the transfered data
+ * @param pDataBuffer0 Pointer to the buffer0 that will contain/receive the transferred data
+ * @param pDataBuffer1 Pointer to the buffer1 that will contain/receive the transferred data
* @param BufferSize Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size.
* @retval HAL status
*/
@@ -228,7 +228,7 @@
}
/**
- * @brief Write block(s) to a specified address in a card. The transfered Data are stored in Buffer0 and Buffer1.
+ * @brief Write block(s) to a specified address in a card. The transferred Data are stored in Buffer0 and Buffer1.
* Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function.
* @param hsd SD handle
* @param BlockAdd Block Address from where data is to be read
@@ -412,5 +412,3 @@
*/
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_smartcard.c b/Src/stm32l4xx_hal_smartcard.c
index 5e694ce..042a0ef 100644
--- a/Src/stm32l4xx_hal_smartcard.c
+++ b/Src/stm32l4xx_hal_smartcard.c
@@ -10,6 +10,17 @@
* + Peripheral Control functions
* + Peripheral State and Error functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -35,7 +46,8 @@
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx channel.
(+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+ (+++) Configure the priority and enable the NVIC for the transfer complete
+ interrupt on the DMA Tx/Rx channel.
(#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
@@ -166,17 +178,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -198,32 +199,34 @@
/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
* @{
*/
-#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */
+#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */
#if defined(USART_CR1_FIFOEN)
-#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
- USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \
- USART_CR1_FIFOEN )) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
+ USART_CR1_RE | USART_CR1_OVER8| \
+ USART_CR1_FIFOEN)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
#else
-#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
- USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
+ USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
#endif /* USART_CR1_FIFOEN */
-#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | \
- USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
+#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
+ USART_CR2_CPHA | USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
-#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | \
+ USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
#if defined(USART_CR1_FIFOEN)
-#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \
- USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \
+ USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
#else
-#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT)) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | \
+ USART_CR3_SCARCNT)) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
#endif /* USART_CR1_FIFOEN */
-#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */
+#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */
-#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */
+#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */
/**
* @}
*/
@@ -496,7 +499,8 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
- HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
+ HAL_SMARTCARD_CallbackIDTypeDef CallbackID,
+ pSMARTCARD_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -633,45 +637,47 @@
switch (CallbackID)
{
case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
- hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
break;
case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
- hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
break;
case HAL_SMARTCARD_ERROR_CB_ID :
- hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
+ hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
- hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
break;
case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
- hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak
+ AbortTransmitCpltCallback*/
break;
case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
- hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+ hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak
+ AbortReceiveCpltCallback */
break;
#if defined(USART_CR1_FIFOEN)
case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID :
- hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
+ hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
break;
case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID :
- hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+ hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
break;
#endif /* USART_CR1_FIFOEN */
case HAL_SMARTCARD_MSPINIT_CB_ID :
- hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */
+ hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */
break;
case HAL_SMARTCARD_MSPDEINIT_CB_ID :
- hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */
+ hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */
break;
default :
@@ -783,7 +789,8 @@
(##) HAL_SMARTCARD_AbortTransmit_IT()
(##) HAL_SMARTCARD_AbortReceive_IT()
- (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+ (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT),
+ a set of Abort Complete Callbacks are provided:
(##) HAL_SMARTCARD_AbortCpltCallback()
(##) HAL_SMARTCARD_AbortTransmitCpltCallback()
(##) HAL_SMARTCARD_AbortReceiveCpltCallback()
@@ -791,13 +798,17 @@
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
(##) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ to be evaluated by user : this concerns Frame Error,
+ Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer,
+ Error code is set to allow user to identify error type,
and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
If user wants to abort it, Abort services should be called by user.
(##) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
- This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
+ This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt
+ mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type,
+ and HAL_SMARTCARD_ErrorCallback() user callback is executed.
@endverbatim
* @{
@@ -816,11 +827,11 @@
* @param Timeout Timeout duration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size,
uint32_t Timeout)
{
uint32_t tickstart;
- uint8_t *ptmpdata = pData;
+ const uint8_t *ptmpdata = pData;
/* Check that a Tx process is not already ongoing */
if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
@@ -845,7 +856,7 @@
the bidirectional line to detect a NACK signal in case of parity error.
Therefore, the receiver block must be enabled as well (RE bit must be set). */
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
- && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
}
@@ -872,8 +883,8 @@
hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU);
ptmpdata++;
}
- if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart,
- Timeout) != HAL_OK)
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET,
+ tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -881,14 +892,14 @@
/* Disable the Peripheral first to update mode */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
- && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
/* In case of TX only mode, if NACK is enabled, receiver block has been enabled
for Transmit phase. Disable this receiver block. */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
}
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
- || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
/* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
__HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
@@ -990,7 +1001,7 @@
* @param Size amount of data to be sent.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
@@ -1018,7 +1029,7 @@
the bidirectional line to detect a NACK signal in case of parity error.
Therefore, the receiver block must be enabled as well (RE bit must be set). */
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
- && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
}
@@ -1173,7 +1184,7 @@
* @param Size amount of data to be sent.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
@@ -1200,7 +1211,7 @@
the bidirectional line to detect a NACK signal in case of parity error.
Therefore, the receiver block must be enabled as well (RE bit must be set). */
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
- && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
}
@@ -1354,7 +1365,8 @@
HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
{
#if defined(USART_CR1_FIFOEN)
- /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
+ /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and
+ ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsmartcard->Instance->CR1,
(USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE |
USART_CR1_EOBIE));
@@ -1362,7 +1374,8 @@
#else
/* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsmartcard->Instance->CR1,
- (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+ (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE |
+ USART_CR1_EOBIE));
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
#endif /* USART_CR1_FIFOEN */
@@ -1422,8 +1435,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@@ -1520,7 +1533,8 @@
{
#if defined(USART_CR1_FIFOEN)
/* Disable RTOIE, EOBIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE |
+ USART_CR1_EOBIE));
CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
#else
/* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
@@ -1565,8 +1579,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@@ -1594,7 +1608,8 @@
uint32_t abortcplt = 1U;
#if defined(USART_CR1_FIFOEN)
- /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
+ /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and
+ ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsmartcard->Instance->CR1,
(USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE |
USART_CR1_EOBIE));
@@ -1602,12 +1617,14 @@
#else
/* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsmartcard->Instance->CR1,
- (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+ (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE |
+ USART_CR1_EOBIE));
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
#endif /* USART_CR1_FIFOEN */
- /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
- before any call to DMA Abort functions */
+ /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle,
+ DMA Abort complete callbacks should be initialised before any call
+ to DMA Abort functions */
/* DMA Tx Handle is valid */
if (hsmartcard->hdmatx != NULL)
{
@@ -1701,8 +1718,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
+ SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@@ -1840,7 +1857,8 @@
{
#if defined(USART_CR1_FIFOEN)
/* Disable RTOIE, EOBIE, RXNE, PE, RXFT and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE |
+ USART_CR1_EOBIE));
CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
#else
/* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
@@ -1884,8 +1902,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
+ SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@@ -1910,8 +1928,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
+ SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@@ -2411,15 +2429,19 @@
void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Init the SMARTCARD Callback settings */
- hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
- hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
- hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
- hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
- hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
- hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+ hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
+ hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak
+ AbortTransmitCpltCallback */
+ hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak
+ AbortReceiveCpltCallback */
#if defined(USART_CR1_FIFOEN)
- hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
- hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+ hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak
+ RxFifoFullCallback */
+ hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak
+ TxFifoEmptyCallback */
#endif /* USART_CR1_FIFOEN */
}
@@ -2465,7 +2487,8 @@
* Configure the Parity and Mode:
* set PS bit according to hsmartcard->Init.Parity value
* set TE and RE bits according to hsmartcard->Init.Mode value */
- tmpreg = (uint32_t)(hsmartcard->Init.Parity | hsmartcard->Init.Mode | hsmartcard->Init.WordLength);
+ tmpreg = (((uint32_t)hsmartcard->Init.Parity) | ((uint32_t)hsmartcard->Init.Mode) |
+ ((uint32_t)hsmartcard->Init.WordLength));
MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
/*-------------------------- USART CR2 Configuration -----------------------*/
@@ -2516,39 +2539,44 @@
case SMARTCARD_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
#if defined(USART_PRESC_PRESCALER)
- tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
#else
- tmpreg = (uint16_t)((pclk + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint32_t)((pclk + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
#endif /* USART_PRESC_PRESCALER */
break;
case SMARTCARD_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
#if defined(USART_PRESC_PRESCALER)
- tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
#else
- tmpreg = (uint16_t)((pclk + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint32_t)((pclk + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
#endif /* USART_PRESC_PRESCALER */
break;
case SMARTCARD_CLOCKSOURCE_HSI:
#if defined(USART_PRESC_PRESCALER)
- tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint32_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
#else
- tmpreg = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint32_t)((HSI_VALUE + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
#endif /* USART_PRESC_PRESCALER */
break;
case SMARTCARD_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
#if defined(USART_PRESC_PRESCALER)
- tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
#else
- tmpreg = (uint16_t)((pclk + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint32_t)((pclk + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
#endif /* USART_PRESC_PRESCALER */
break;
case SMARTCARD_CLOCKSOURCE_LSE:
#if defined(USART_PRESC_PRESCALER)
- tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint32_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
#else
- tmpreg = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint32_t)((LSE_VALUE + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
#endif /* USART_PRESC_PRESCALER */
break;
default:
@@ -2559,7 +2587,7 @@
/* USARTDIV must be greater than or equal to 0d16 */
if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
{
- hsmartcard->Instance->BRR = tmpreg;
+ hsmartcard->Instance->BRR = (uint16_t)tmpreg;
}
else
{
@@ -2692,11 +2720,12 @@
}
/**
- * @brief Handle SMARTCARD Communication Timeout.
+ * @brief Handle SMARTCARD Communication Timeout. It waits
+ * until a flag is no longer in the specified status.
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @param Flag Specifies the SMARTCARD flag to check.
- * @param Status The new Flag status (SET or RESET).
+ * @param Status The actual Flag status (SET or RESET).
* @param Tickstart Tick start value
* @param Timeout Timeout duration.
* @retval HAL status
@@ -2712,7 +2741,8 @@
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
+ interrupts for the interrupt process */
#if defined(USART_CR1_FIFOEN)
CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
#else
@@ -2918,8 +2948,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@@ -2967,8 +2997,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@@ -3029,8 +3059,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@@ -3142,14 +3172,14 @@
/* Disable the Peripheral first to update mode */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
- && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
/* In case of TX only mode, if NACK is enabled, receiver block has been enabled
for Transmit phase. Disable this receiver block. */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
}
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
- || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
/* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
__HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
@@ -3319,4 +3349,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_smartcard_ex.c b/Src/stm32l4xx_hal_smartcard_ex.c
index 04ef543..c2df17f 100644
--- a/Src/stm32l4xx_hal_smartcard_ex.c
+++ b/Src/stm32l4xx_hal_smartcard_ex.c
@@ -8,6 +8,17 @@
* + Initialization and de-initialization functions
* + Peripheral Control functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
=============================================================================
##### SMARTCARD peripheral extended features #####
@@ -27,17 +38,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -479,8 +479,10 @@
tx_fifo_depth = TX_FIFO_DEPTH;
rx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
tx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
- hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];
- hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];
+ hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / \
+ (uint16_t)denominator[tx_fifo_threshold];
+ hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / \
+ (uint16_t)denominator[rx_fifo_threshold];
}
}
@@ -499,4 +501,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_smbus.c b/Src/stm32l4xx_hal_smbus.c
index c05f765..b5a9ed3 100644
--- a/Src/stm32l4xx_hal_smbus.c
+++ b/Src/stm32l4xx_hal_smbus.c
@@ -10,6 +10,17 @@
* + IO operation functions
* + Peripheral State and Errors functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -20,7 +31,7 @@
(#) Declare a SMBUS_HandleTypeDef handle structure, for example:
SMBUS_HandleTypeDef hsmbus;
- (#)Initialize the SMBUS low level resources by implementing the @ref HAL_SMBUS_MspInit() API:
+ (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
(##) Enable the SMBUSx interface clock
(##) SMBUS pins configuration
(+++) Enable the clock for the SMBUS GPIOs
@@ -33,69 +44,75 @@
Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
- (#) Initialize the SMBUS registers by calling the @ref HAL_SMBUS_Init() API:
+ (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
(++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customized @ref HAL_SMBUS_MspInit(&hsmbus) API.
+ by calling the customized HAL_SMBUS_MspInit(&hsmbus) API.
- (#) To check if target device is ready for communication, use the function @ref HAL_SMBUS_IsDeviceReady()
+ (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
(#) For SMBUS IO operations, only one mode of operations is available within this driver
*** Interrupt mode IO operation ***
===================================
[..]
- (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Transmit_IT()
- (++) At transmission end of transfer @ref HAL_SMBUS_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_SMBUS_MasterTxCpltCallback()
- (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Receive_IT()
- (++) At reception end of transfer @ref HAL_SMBUS_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_SMBUS_MasterRxCpltCallback()
- (+) Abort a master/host SMBUS process communication with Interrupt using @ref HAL_SMBUS_Master_Abort_IT()
+ (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode
+ using HAL_SMBUS_Master_Transmit_IT()
+ (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback()
+ (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode
+ using HAL_SMBUS_Master_Receive_IT()
+ (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback()
+ (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT()
(++) The associated previous transfer callback is called at the end of abort process
- (++) mean @ref HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
- (++) mean @ref HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
+ (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
+ (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
(+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
- using @ref HAL_SMBUS_EnableListen_IT() @ref HAL_SMBUS_DisableListen_IT()
- (++) When address slave/device SMBUS match, @ref HAL_SMBUS_AddrCallback() is executed and user can
- add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
- (++) At Listen mode end @ref HAL_SMBUS_ListenCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_SMBUS_ListenCpltCallback()
- (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Transmit_IT()
- (++) At transmission end of transfer @ref HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_SMBUS_SlaveTxCpltCallback()
- (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Receive_IT()
- (++) At reception end of transfer @ref HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_SMBUS_SlaveRxCpltCallback()
- (+) Enable/Disable the SMBUS alert mode using @ref HAL_SMBUS_EnableAlert_IT() @ref HAL_SMBUS_DisableAlert_IT()
- (++) When SMBUS Alert is generated @ref HAL_SMBUS_ErrorCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback()
- to check the Alert Error Code using function @ref HAL_SMBUS_GetError()
- (+) Get HAL state machine or error values using @ref HAL_SMBUS_GetState() or @ref HAL_SMBUS_GetError()
- (+) In case of transfer Error, @ref HAL_SMBUS_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback()
- to check the Error Code using function @ref HAL_SMBUS_GetError()
+ using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT()
+ (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and users can
+ add their own code to check the Address Match Code and the transmission direction
+ request by master/host (Write/Read).
+ (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_SMBUS_ListenCpltCallback()
+ (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode
+ using HAL_SMBUS_Slave_Transmit_IT()
+ (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback()
+ (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode
+ using HAL_SMBUS_Slave_Receive_IT()
+ (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback()
+ (+) Enable/Disable the SMBUS alert mode using
+ HAL_SMBUS_EnableAlert_IT() or HAL_SMBUS_DisableAlert_IT()
+ (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and users can
+ add their own code by customization of function pointer HAL_SMBUS_ErrorCallback()
+ to check the Alert Error Code using function HAL_SMBUS_GetError()
+ (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
+ (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and users can
+ add their own code by customization of function pointer HAL_SMBUS_ErrorCallback()
+ to check the Error Code using function HAL_SMBUS_GetError()
*** SMBUS HAL driver macros list ***
==================================
[..]
Below the list of most used macros in SMBUS HAL driver.
- (+) @ref __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral
- (+) @ref __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral
- (+) @ref __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not
- (+) @ref __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag
- (+) @ref __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt
- (+) @ref __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt
+ (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral
+ (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral
+ (+) __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not
+ (+) __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag
+ (+) __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt
+ (+) __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt
*** Callback registration ***
=============================================
[..]
The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterAddrCallback()
+ Use Functions HAL_SMBUS_RegisterCallback() or HAL_SMBUS_RegisterAddrCallback()
to register an interrupt callback.
[..]
- Function @ref HAL_SMBUS_RegisterCallback() allows to register following callbacks:
+ Function HAL_SMBUS_RegisterCallback() allows to register following callbacks:
(+) MasterTxCpltCallback : callback for Master transmission end of transfer.
(+) MasterRxCpltCallback : callback for Master reception end of transfer.
(+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
@@ -107,11 +124,11 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
- For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback.
+ For specific callback AddrCallback use dedicated register callbacks : HAL_SMBUS_RegisterAddrCallback.
[..]
- Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default
+ Use function HAL_SMBUS_UnRegisterCallback to reset a callback to the default
weak function.
- @ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) MasterTxCpltCallback : callback for Master transmission end of transfer.
@@ -123,24 +140,24 @@
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
[..]
- For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback.
+ For callback AddrCallback use dedicated register callbacks : HAL_SMBUS_UnRegisterAddrCallback.
[..]
- By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_I2C_STATE_RESET
+ By default, after the HAL_SMBUS_Init() and when the state is HAL_I2C_STATE_RESET
all callbacks are set to the corresponding weak functions:
- examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback().
+ examples HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_MasterRxCpltCallback().
Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak functions in the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() only when
+ reset to the legacy weak functions in the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit() only when
these callbacks are null (not registered beforehand).
- If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit()
+ If MspInit or MspDeInit are not null, the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
- Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
+ Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
- in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
+ in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
Then, the user first registers the MspInit/MspDeInit user callbacks
- using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit()
- or @ref HAL_SMBUS_Init() function.
+ using HAL_SMBUS_RegisterCallback() before calling HAL_SMBUS_DeInit()
+ or HAL_SMBUS_Init() function.
[..]
When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
@@ -150,18 +167,6 @@
(@) You can refer to the SMBUS HAL driver header file for more useful macros
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -203,20 +208,28 @@
/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
* @{
*/
-static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status,
- uint32_t Timeout);
+/* Private functions to handle flags during polling transfer */
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag,
+ FlagStatus Status, uint32_t Timeout);
-static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
-static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
+/* Private functions for SMBUS transfer IRQ handler */
static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
-
-static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
-
static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus);
-static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
- uint32_t Request);
+/* Private functions to centralize the enable/disable of Interrupts */
+static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
+static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
+
+/* Private function to flush TXDR register */
+static void SMBUS_Flush_TXDR(SMBUS_HandleTypeDef *hsmbus);
+
+/* Private function to handle start, restart or stop a transfer */
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size,
+ uint32_t Mode, uint32_t Request);
+
+/* Private function to Convert Specific options */
+static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
/**
* @}
*/
@@ -364,15 +377,20 @@
/*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
/* Configure SMBUSx: Dual mode and Own Address2 */
- hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8U));
+ hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | \
+ (hsmbus->Init.OwnAddress2Masks << 8U));
/*---------------------------- SMBUSx CR1 Configuration ------------------------*/
/* Configure SMBUSx: Generalcall and NoStretch mode */
- hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter);
+ hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | \
+ hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | \
+ hsmbus->Init.AnalogFilter);
- /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */
- if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE)
- && ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)))
+ /* Enable Slave Byte Control only in case of Packet Error Check is enabled
+ and SMBUS Peripheral is set in Slave mode */
+ if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) && \
+ ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
+ (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)))
{
hsmbus->Instance->CR1 |= I2C_CR1_SBC;
}
@@ -581,7 +599,8 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID,
+HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus,
+ HAL_SMBUS_CallbackIDTypeDef CallbackID,
pSMBUS_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -695,7 +714,8 @@
* @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID)
+HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus,
+ HAL_SMBUS_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -790,7 +810,8 @@
* @param pCallback pointer to the Address Match Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus,
+ pSMBUS_AddrCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -914,8 +935,8 @@
* @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
- uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
+ uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
uint32_t tmp;
@@ -955,7 +976,8 @@
if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
{
SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
- SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
+ SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
+ SMBUS_GENERATE_START_WRITE);
}
else
{
@@ -965,9 +987,11 @@
/* Store current volatile XferOptions, misra rule */
tmp = hsmbus->XferOptions;
- if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
+ if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && \
+ (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
{
- SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+ SMBUS_NO_STARTSTOP);
}
/* Else transfer direction change, so generate Restart with new transfer direction */
else
@@ -976,7 +1000,9 @@
SMBUS_ConvertOtherXferOptions(hsmbus);
/* Handle Transfer */
- SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
+ hsmbus->XferOptions,
+ SMBUS_GENERATE_START_WRITE);
}
/* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
@@ -1057,7 +1083,8 @@
if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
{
SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
- SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
+ SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
+ SMBUS_GENERATE_START_READ);
}
else
{
@@ -1067,9 +1094,11 @@
/* Store current volatile XferOptions, Misra rule */
tmp = hsmbus->XferOptions;
- if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
+ if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && \
+ (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
{
- SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+ SMBUS_NO_STARTSTOP);
}
/* Else transfer direction change, so generate Restart with new transfer direction */
else
@@ -1078,7 +1107,9 @@
SMBUS_ConvertOtherXferOptions(hsmbus);
/* Handle Transfer */
- SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
+ hsmbus->XferOptions,
+ SMBUS_GENERATE_START_READ);
}
}
@@ -1222,12 +1253,14 @@
if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
{
SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize,
- SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
+ SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
+ SMBUS_NO_STARTSTOP);
}
else
{
/* Set NBYTE to transmit */
- SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+ SMBUS_NO_STARTSTOP);
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
@@ -1313,7 +1346,8 @@
/* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
if (((SMBUS_GET_PEC_MODE(hsmbus) != 0UL) && (hsmbus->XferSize == 2U)) || (hsmbus->XferSize == 1U))
{
- SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+ SMBUS_NO_STARTSTOP);
}
else
{
@@ -1576,7 +1610,8 @@
uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1);
/* SMBUS in mode Transmitter ---------------------------------------------------*/
- if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) &&
+ if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI |
+ SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) &&
((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) ||
(SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) ||
(SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) ||
@@ -1600,7 +1635,8 @@
}
/* SMBUS in mode Receiver ----------------------------------------------------*/
- if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) &&
+ if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI |
+ SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) &&
((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) ||
(SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) ||
(SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) ||
@@ -1720,7 +1756,8 @@
* @param AddrMatchCode Address Match Code
* @retval None
*/
-__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
+__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection,
+ uint16_t AddrMatchCode)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsmbus);
@@ -1842,6 +1879,9 @@
/* No need to generate STOP, it is automatically done */
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
+ /* Flush TX register */
+ SMBUS_Flush_TXDR(hsmbus);
+
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
@@ -1967,13 +2007,15 @@
if (hsmbus->XferCount > MAX_NBYTE_SIZE)
{
SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE,
- (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
+ (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)),
+ SMBUS_NO_STARTSTOP);
hsmbus->XferSize = MAX_NBYTE_SIZE;
}
else
{
hsmbus->XferSize = hsmbus->XferCount;
- SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+ SMBUS_NO_STARTSTOP);
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
@@ -2130,6 +2172,9 @@
/* Clear NACK Flag */
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+ /* Flush TX register */
+ SMBUS_Flush_TXDR(hsmbus);
+
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
}
@@ -2151,6 +2196,9 @@
/* Set ErrorCode corresponding to a Non-Acknowledge */
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
+ /* Flush TX register */
+ SMBUS_Flush_TXDR(hsmbus);
+
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
@@ -2225,7 +2273,9 @@
else
{
/* Set Reload for next Bytes */
- SMBUS_TransferConfig(hsmbus, 0, 1, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0, 1,
+ SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
+ SMBUS_NO_STARTSTOP);
/* Ack last Byte Read */
hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
@@ -2237,14 +2287,16 @@
{
if (hsmbus->XferCount > MAX_NBYTE_SIZE)
{
- SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)),
+ SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE,
+ (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)),
SMBUS_NO_STARTSTOP);
hsmbus->XferSize = MAX_NBYTE_SIZE;
}
else
{
hsmbus->XferSize = hsmbus->XferCount;
- SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+ SMBUS_NO_STARTSTOP);
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
@@ -2489,7 +2541,8 @@
uint32_t tmperror;
/* SMBUS Bus error interrupt occurred ------------------------------------*/
- if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+ if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && \
+ ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
{
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
@@ -2498,7 +2551,8 @@
}
/* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
- if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+ if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && \
+ ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
{
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
@@ -2507,7 +2561,8 @@
}
/* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
- if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+ if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && \
+ ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
{
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
@@ -2516,7 +2571,8 @@
}
/* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
- if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+ if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && \
+ ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
{
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
@@ -2525,7 +2581,8 @@
}
/* SMBUS Alert error interrupt occurred -----------------------------------------------*/
- if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+ if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && \
+ ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
{
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
@@ -2534,7 +2591,8 @@
}
/* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
- if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+ if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && \
+ ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
{
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
@@ -2542,7 +2600,10 @@
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
}
- /* Store current volatile hsmbus->State, misra rule */
+ /* Flush TX register */
+ SMBUS_Flush_TXDR(hsmbus);
+
+ /* Store current volatile hsmbus->ErrorCode, misra rule */
tmperror = hsmbus->ErrorCode;
/* Call the Error Callback in case of Error detected */
@@ -2582,8 +2643,8 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status,
- uint32_t Timeout)
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag,
+ FlagStatus Status, uint32_t Timeout)
{
uint32_t tickstart = HAL_GetTick();
@@ -2613,6 +2674,27 @@
}
/**
+ * @brief SMBUS Tx data register flush process.
+ * @param hsmbus SMBUS handle.
+ * @retval None
+ */
+static void SMBUS_Flush_TXDR(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* If a pending TXIS flag is set */
+ /* Write a dummy data in TXDR to clear it */
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
+ {
+ hsmbus->Instance->TXDR = 0x00U;
+ }
+
+ /* Flush TX register if not empty */
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXE) == RESET)
+ {
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TXE);
+ }
+}
+
+/**
* @brief Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
* @param hsmbus SMBUS handle.
* @param DevAddress specifies the slave address to be programmed.
@@ -2632,8 +2714,8 @@
* @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request.
* @retval None
*/
-static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
- uint32_t Request)
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size,
+ uint32_t Mode, uint32_t Request)
{
/* Check the parameters */
assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
@@ -2644,9 +2726,10 @@
MODIFY_REG(hsmbus->Instance->CR2,
((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | \
- I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \
+ I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \
(uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
- (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
+ (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
+ (uint32_t)Mode | (uint32_t)Request));
}
/**
@@ -2703,5 +2786,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_smbus_ex.c b/Src/stm32l4xx_hal_smbus_ex.c
index 59c78b6..5b66c80 100644
--- a/Src/stm32l4xx_hal_smbus_ex.c
+++ b/Src/stm32l4xx_hal_smbus_ex.c
@@ -7,6 +7,17 @@
* functionalities of SMBUS Extended peripheral:
* + Extended features functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### SMBUS peripheral Extended features #####
@@ -15,26 +26,18 @@
[..] Comparing to other previous devices, the SMBUS interface for STM32L4xx
devices contains the following additional features
+ (+) Disable or enable wakeup from Stop mode(s)
(+) Disable or enable Fast Mode Plus
##### How to use this driver #####
==============================================================================
+ (#) Configure the enable or disable of SMBUS Wake Up Mode using the functions :
+ (++) HAL_SMBUSEx_EnableWakeUp()
+ (++) HAL_SMBUSEx_DisableWakeUp()
(#) Configure the enable or disable of fast mode plus driving capability using the functions :
(++) HAL_SMBUSEx_EnableFastModePlus()
(++) HAL_SMBUSEx_DisableFastModePlus()
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -62,15 +65,109 @@
* @{
*/
-/** @defgroup SMBUSEx_Exported_Functions_Group1 Extended features functions
- * @brief Extended features functions
- *
+/** @defgroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions
+ * @brief WakeUp Mode Functions
+ *
@verbatim
===============================================================================
- ##### Extended features functions #####
+ ##### WakeUp Mode Functions #####
===============================================================================
[..] This section provides functions allowing to:
+ (+) Configure Wake Up Feature
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable SMBUS wakeup from Stop mode(s).
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUSx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /* Enable wakeup from stop mode */
+ hsmbus->Instance->CR1 |= I2C_CR1_WUPEN;
+
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Disable SMBUS wakeup from Stop mode(s).
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUSx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /* Disable wakeup from stop mode */
+ hsmbus->Instance->CR1 &= ~(I2C_CR1_WUPEN);
+
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @}
+ */
+
+/** @defgroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions
+ * @brief Fast Mode Plus Functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Fast Mode Plus Functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
(+) Configure Fast Mode Plus
@endverbatim
@@ -82,16 +179,16 @@
* @param ConfigFastModePlus Selects the pin.
* This parameter can be one of the @ref SMBUSEx_FastModePlus values
* @note For I2C1, fast mode plus driving capability can be enabled on all selected
- * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+ * I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently
* on each one of the following pins PB6, PB7, PB8 and PB9.
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
- * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+ * can be enabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter.
* @note For all I2C2 pins fast mode plus driving capability can be enabled
- * only by using I2C_FASTMODEPLUS_I2C2 parameter.
+ * only by using SMBUS_FASTMODEPLUS_I2C2 parameter.
* @note For all I2C3 pins fast mode plus driving capability can be enabled
- * only by using I2C_FASTMODEPLUS_I2C3 parameter.
+ * only by using SMBUS_FASTMODEPLUS_I2C3 parameter.
* @note For all I2C4 pins fast mode plus driving capability can be enabled
- * only by using I2C_FASTMODEPLUS_I2C4 parameter.
+ * only by using SMBUS_FASTMODEPLUS_I2C4 parameter.
* @retval None
*/
void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
@@ -111,16 +208,16 @@
* @param ConfigFastModePlus Selects the pin.
* This parameter can be one of the @ref SMBUSEx_FastModePlus values
* @note For I2C1, fast mode plus driving capability can be disabled on all selected
- * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+ * I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently
* on each one of the following pins PB6, PB7, PB8 and PB9.
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
- * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+ * can be disabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter.
* @note For all I2C2 pins fast mode plus driving capability can be disabled
- * only by using I2C_FASTMODEPLUS_I2C2 parameter.
+ * only by using SMBUS_FASTMODEPLUS_I2C2 parameter.
* @note For all I2C3 pins fast mode plus driving capability can be disabled
- * only by using I2C_FASTMODEPLUS_I2C3 parameter.
+ * only by using SMBUS_FASTMODEPLUS_I2C3 parameter.
* @note For all I2C4 pins fast mode plus driving capability can be disabled
- * only by using I2C_FASTMODEPLUS_I2C4 parameter.
+ * only by using SMBUS_FASTMODEPLUS_I2C4 parameter.
* @retval None
*/
void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
@@ -135,6 +232,9 @@
CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
}
+/**
+ * @}
+ */
/**
* @}
@@ -152,5 +252,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_spi.c b/Src/stm32l4xx_hal_spi.c
index 25f60fd..c317c06 100644
--- a/Src/stm32l4xx_hal_spi.c
+++ b/Src/stm32l4xx_hal_spi.c
@@ -9,7 +9,17 @@
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State functions
+ ******************************************************************************
+ * @attention
*
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -184,18 +194,6 @@
(#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
(#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -1009,6 +1007,8 @@
{
#if (USE_SPI_CRC != 0U)
__IO uint32_t tmpreg = 0U;
+ __IO uint8_t *ptmpreg8;
+ __IO uint8_t tmpreg8 = 0;
#endif /* USE_SPI_CRC */
uint32_t tickstart;
HAL_StatusTypeDef errorcode = HAL_OK;
@@ -1182,10 +1182,12 @@
}
else
{
+ /* Initialize the 8bit temporary pointer */
+ ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
/* Read 8bit CRC */
- tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ tmpreg8 = *ptmpreg8;
/* To avoid GCC warning */
- UNUSED(tmpreg);
+ UNUSED(tmpreg8);
if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
{
@@ -1197,9 +1199,9 @@
goto error;
}
/* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
- tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ tmpreg8 = *ptmpreg8;
/* To avoid GCC warning */
- UNUSED(tmpreg);
+ UNUSED(tmpreg8);
}
}
}
@@ -1244,17 +1246,17 @@
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
uint32_t Timeout)
{
-#if (USE_SPI_CRC != 0U)
- __IO uint32_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
uint16_t initial_TxXferCount;
uint16_t initial_RxXferCount;
uint32_t tmp_mode;
HAL_SPI_StateTypeDef tmp_state;
uint32_t tickstart;
#if (USE_SPI_CRC != 0U)
+ __IO uint32_t tmpreg = 0U;
uint32_t spi_cr1;
uint32_t spi_cr2;
+ __IO uint8_t *ptmpreg8;
+ __IO uint8_t tmpreg8 = 0;
#endif /* USE_SPI_CRC */
/* Variable used to alternate Rx and Tx during transfer */
@@ -1494,10 +1496,12 @@
}
else
{
+ /* Initialize the 8bit temporary pointer */
+ ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
/* Read 8bit CRC */
- tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ tmpreg8 = *ptmpreg8;
/* To avoid GCC warning */
- UNUSED(tmpreg);
+ UNUSED(tmpreg8);
if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
{
@@ -1509,9 +1513,9 @@
goto error;
}
/* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
- tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ tmpreg8 = *ptmpreg8;
/* To avoid GCC warning */
- UNUSED(tmpreg);
+ UNUSED(tmpreg8);
}
}
}
@@ -3068,6 +3072,8 @@
uint32_t tickstart;
#if (USE_SPI_CRC != 0U)
__IO uint32_t tmpreg = 0U;
+ __IO uint8_t *ptmpreg8;
+ __IO uint8_t tmpreg8 = 0;
#endif /* USE_SPI_CRC */
/* Init tickstart for timeout management*/
@@ -3099,10 +3105,12 @@
}
else
{
+ /* Initialize the 8bit temporary pointer */
+ ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
/* Read 8bit CRC */
- tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ tmpreg8 = *ptmpreg8;
/* To avoid GCC warning */
- UNUSED(tmpreg);
+ UNUSED(tmpreg8);
if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
{
@@ -3112,9 +3120,9 @@
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
}
/* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
- tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ tmpreg8 = *ptmpreg8;
/* To avoid GCC warning */
- UNUSED(tmpreg);
+ UNUSED(tmpreg8);
}
}
}
@@ -3181,6 +3189,8 @@
uint32_t tickstart;
#if (USE_SPI_CRC != 0U)
__IO uint32_t tmpreg = 0U;
+ __IO uint8_t *ptmpreg8;
+ __IO uint8_t tmpreg8 = 0;
#endif /* USE_SPI_CRC */
/* Init tickstart for timeout management*/
@@ -3204,10 +3214,12 @@
/* Error on the CRC reception */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
}
- /* Read CRC to Flush DR and RXNE flag */
- tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ /* Initialize the 8bit temporary pointer */
+ ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
+ /* Read 8bit CRC */
+ tmpreg8 = *ptmpreg8;
/* To avoid GCC warning */
- UNUSED(tmpreg);
+ UNUSED(tmpreg8);
}
else
{
@@ -3554,12 +3566,15 @@
*/
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- __IO uint32_t tmpreg = 0U;
+ __IO uint8_t *ptmpreg8;
+ __IO uint8_t tmpreg8 = 0;
+ /* Initialize the 8bit temporary pointer */
+ ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
/* Read 8bit CRC to flush Data Register */
- tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ tmpreg8 = *ptmpreg8;
/* To avoid GCC warning */
- UNUSED(tmpreg);
+ UNUSED(tmpreg8);
hspi->CRCSize--;
@@ -3671,7 +3686,7 @@
/* Read 16bit CRC to flush Data Register */
tmpreg = READ_REG(hspi->Instance->DR);
/* To avoid GCC warning */
- UNUSED(tmpreg);
+ UNUSED(tmpreg);
/* Disable RXNE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
@@ -3726,12 +3741,15 @@
*/
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- __IO uint32_t tmpreg = 0U;
+ __IO uint8_t *ptmpreg8;
+ __IO uint8_t tmpreg8 = 0;
+ /* Initialize the 8bit temporary pointer */
+ ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
/* Read 8bit CRC to flush Data Register */
- tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ tmpreg8 = *ptmpreg8;
/* To avoid GCC warning */
- UNUSED(tmpreg);
+ UNUSED(tmpreg8);
hspi->CRCSize--;
@@ -3940,7 +3958,7 @@
return HAL_TIMEOUT;
}
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
- if(count == 0U)
+ if (count == 0U)
{
tmp_timeout = 0U;
}
@@ -3964,15 +3982,19 @@
static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
uint32_t Timeout, uint32_t Tickstart)
{
- __IO uint32_t tmpreg;
__IO uint32_t count;
uint32_t tmp_timeout;
uint32_t tmp_tickstart;
+ __IO uint8_t *ptmpreg8;
+ __IO uint8_t tmpreg8 = 0;
/* Adjust Timeout value in case of end of transfer */
tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
tmp_tickstart = HAL_GetTick();
+ /* Initialize the 8bit temporary pointer */
+ ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
+
/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U);
@@ -3981,9 +4003,9 @@
if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
{
/* Flush Data Register by a blank read */
- tmpreg = READ_REG(*((__IO uint8_t *)&hspi->Instance->DR));
+ tmpreg8 = *ptmpreg8;
/* To avoid GCC warning */
- UNUSED(tmpreg);
+ UNUSED(tmpreg8);
}
if (Timeout != HAL_MAX_DELAY)
@@ -4018,10 +4040,10 @@
return HAL_TIMEOUT;
}
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
- if(count == 0U)
+ if (count == 0U)
{
tmp_timeout = 0U;
- }
+ }
count--;
}
}
@@ -4412,4 +4434,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_spi_ex.c b/Src/stm32l4xx_hal_spi_ex.c
index a21bbce..ad50589 100644
--- a/Src/stm32l4xx_hal_spi_ex.c
+++ b/Src/stm32l4xx_hal_spi_ex.c
@@ -10,13 +10,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -111,5 +110,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_sram.c b/Src/stm32l4xx_hal_sram.c
index 444a501..2a0ffbe 100644
--- a/Src/stm32l4xx_hal_sram.c
+++ b/Src/stm32l4xx_hal_sram.c
@@ -6,6 +6,17 @@
* This file provides a generic firmware to drive SRAM memories
* mounted as external device.
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -64,25 +75,25 @@
The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_SRAM_RegisterCallback() to register a user callback,
+ Use Functions HAL_SRAM_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) MspInitCallback : SRAM MspInit.
(+) MspDeInitCallback : SRAM MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- Use function @ref HAL_SRAM_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) MspInitCallback : SRAM MspInit.
(+) MspDeInitCallback : SRAM MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
- By default, after the @ref HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
+ By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_SRAM_Init
- and @ref HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_SRAM_Init and @ref HAL_SRAM_DeInit
+ reset to the legacy weak (surcharged) functions in the HAL_SRAM_Init
+ and HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
@@ -90,8 +101,8 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_SRAM_RegisterCallback before calling @ref HAL_SRAM_DeInit
- or @ref HAL_SRAM_Init function.
+ using HAL_SRAM_RegisterCallback before calling HAL_SRAM_DeInit
+ or HAL_SRAM_Init function.
When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
@@ -99,17 +110,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -1108,5 +1108,3 @@
*/
#endif /* FMC_BANK1 */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_swpmi.c b/Src/stm32l4xx_hal_swpmi.c
index 3c547a6..5de228d 100644
--- a/Src/stm32l4xx_hal_swpmi.c
+++ b/Src/stm32l4xx_hal_swpmi.c
@@ -9,6 +9,17 @@
* + Data transfers functions
* + DMA transfers management
* + Interrupts and flags management
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
@@ -144,7 +155,7 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using HAL_SWPMI_RegisterCallback before calling @ref HAL_SWPMI_DeInit
+ using HAL_SWPMI_RegisterCallback before calling HAL_SWPMI_DeInit
or HAL_SWPMI_Init function.
[..]
When the compilation define USE_HAL_SWPMI_REGISTER_CALLBACKS is set to 0 or
@@ -152,18 +163,6 @@
and weak (surcharged) callbacks are used.
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -241,7 +240,7 @@
__IO uint32_t wait_loop_index = 0U;
/* Check the SWPMI handle allocation */
- if(hswpmi == NULL)
+ if (hswpmi == NULL)
{
status = HAL_ERROR;
}
@@ -253,7 +252,7 @@
assert_param(IS_SWPMI_TX_BUFFERING_MODE(hswpmi->Init.TxBufferingMode));
assert_param(IS_SWPMI_RX_BUFFERING_MODE(hswpmi->Init.RxBufferingMode));
- if(hswpmi->State == HAL_SWPMI_STATE_RESET)
+ if (hswpmi->State == HAL_SWPMI_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hswpmi->Lock = HAL_UNLOCKED;
@@ -267,7 +266,7 @@
hswpmi->ErrorCallback = HAL_SWPMI_ErrorCallback;
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- if(hswpmi->MspInitCallback == NULL)
+ if (hswpmi->MspInitCallback == NULL)
{
hswpmi->MspInitCallback = HAL_SWPMI_MspInit;
}
@@ -289,14 +288,14 @@
/* Apply Voltage class selection */
MODIFY_REG(hswpmi->Instance->OR, SWPMI_OR_CLASS, hswpmi->Init.VoltageClass);
- /* If Voltage class B, apply 300 µs delay */
- if(hswpmi->Init.VoltageClass == SWPMI_VOLTAGE_CLASS_B)
+ /* If Voltage class B, apply 300us delay */
+ if (hswpmi->Init.VoltageClass == SWPMI_VOLTAGE_CLASS_B)
{
- /* Insure 300 µs wait to insure SWPMI_IO output not higher than 1.8V */
+ /* Insure 300us wait to insure SWPMI_IO output not higher than 1.8V */
/* Wait loop initialization and execution */
/* Note: Variable divided by 4 to compensate partially CPU processing cycles. */
wait_loop_index = (300U * (SystemCoreClock / (1000000U * 4U))) + 150U;
- while(wait_loop_index != 0U)
+ while (wait_loop_index != 0U)
{
wait_loop_index--;
}
@@ -330,7 +329,7 @@
HAL_StatusTypeDef status = HAL_OK;
/* Check the SWPMI handle allocation */
- if(hswpmi == NULL)
+ if (hswpmi == NULL)
{
status = HAL_ERROR;
}
@@ -350,7 +349,7 @@
/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
- if(hswpmi->MspDeInitCallback == NULL)
+ if (hswpmi->MspDeInitCallback == NULL)
{
hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit;
}
@@ -417,12 +416,12 @@
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_SWPMI_RegisterCallback(SWPMI_HandleTypeDef *hswpmi,
- HAL_SWPMI_CallbackIDTypeDef CallbackID,
- pSWPMI_CallbackTypeDef pCallback)
+ HAL_SWPMI_CallbackIDTypeDef CallbackID,
+ pSWPMI_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
/* update the error code */
hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
@@ -431,55 +430,55 @@
}
else
{
- if(hswpmi->State == HAL_SWPMI_STATE_READY)
+ if (hswpmi->State == HAL_SWPMI_STATE_READY)
{
switch (CallbackID)
{
- case HAL_SWPMI_RX_COMPLETE_CB_ID :
- hswpmi->RxCpltCallback = pCallback;
- break;
- case HAL_SWPMI_RX_HALFCOMPLETE_CB_ID :
- hswpmi->RxHalfCpltCallback = pCallback;
- break;
- case HAL_SWPMI_TX_COMPLETE_CB_ID :
- hswpmi->TxCpltCallback = pCallback;
- break;
- case HAL_SWPMI_TX_HALFCOMPLETE_CB_ID :
- hswpmi->TxHalfCpltCallback = pCallback;
- break;
- case HAL_SWPMI_ERROR_CB_ID :
- hswpmi->ErrorCallback = pCallback;
- break;
- case HAL_SWPMI_MSPINIT_CB_ID :
- hswpmi->MspInitCallback = pCallback;
- break;
- case HAL_SWPMI_MSPDEINIT_CB_ID :
- hswpmi->MspDeInitCallback = pCallback;
- break;
- default :
- /* update the error code */
- hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SWPMI_RX_COMPLETE_CB_ID :
+ hswpmi->RxCpltCallback = pCallback;
+ break;
+ case HAL_SWPMI_RX_HALFCOMPLETE_CB_ID :
+ hswpmi->RxHalfCpltCallback = pCallback;
+ break;
+ case HAL_SWPMI_TX_COMPLETE_CB_ID :
+ hswpmi->TxCpltCallback = pCallback;
+ break;
+ case HAL_SWPMI_TX_HALFCOMPLETE_CB_ID :
+ hswpmi->TxHalfCpltCallback = pCallback;
+ break;
+ case HAL_SWPMI_ERROR_CB_ID :
+ hswpmi->ErrorCallback = pCallback;
+ break;
+ case HAL_SWPMI_MSPINIT_CB_ID :
+ hswpmi->MspInitCallback = pCallback;
+ break;
+ case HAL_SWPMI_MSPDEINIT_CB_ID :
+ hswpmi->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update the error code */
+ hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(hswpmi->State == HAL_SWPMI_STATE_RESET)
+ else if (hswpmi->State == HAL_SWPMI_STATE_RESET)
{
switch (CallbackID)
{
- case HAL_SWPMI_MSPINIT_CB_ID :
- hswpmi->MspInitCallback = pCallback;
- break;
- case HAL_SWPMI_MSPDEINIT_CB_ID :
- hswpmi->MspDeInitCallback = pCallback;
- break;
- default :
- /* update the error code */
- hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SWPMI_MSPINIT_CB_ID :
+ hswpmi->MspInitCallback = pCallback;
+ break;
+ case HAL_SWPMI_MSPDEINIT_CB_ID :
+ hswpmi->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update the error code */
+ hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -509,59 +508,59 @@
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_SWPMI_UnRegisterCallback(SWPMI_HandleTypeDef *hswpmi,
- HAL_SWPMI_CallbackIDTypeDef CallbackID)
+ HAL_SWPMI_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
- if(hswpmi->State == HAL_SWPMI_STATE_READY)
+ if (hswpmi->State == HAL_SWPMI_STATE_READY)
{
switch (CallbackID)
{
- case HAL_SWPMI_RX_COMPLETE_CB_ID :
- hswpmi->RxCpltCallback = HAL_SWPMI_RxCpltCallback;
- break;
- case HAL_SWPMI_RX_HALFCOMPLETE_CB_ID :
- hswpmi->RxHalfCpltCallback = HAL_SWPMI_RxHalfCpltCallback;
- break;
- case HAL_SWPMI_TX_COMPLETE_CB_ID :
- hswpmi->TxCpltCallback = HAL_SWPMI_TxCpltCallback;
- break;
- case HAL_SWPMI_TX_HALFCOMPLETE_CB_ID :
- hswpmi->TxHalfCpltCallback = HAL_SWPMI_TxHalfCpltCallback;
- break;
- case HAL_SWPMI_ERROR_CB_ID :
- hswpmi->ErrorCallback = HAL_SWPMI_ErrorCallback;
- break;
- case HAL_SWPMI_MSPINIT_CB_ID :
- hswpmi->MspInitCallback = HAL_SWPMI_MspInit;
- break;
- case HAL_SWPMI_MSPDEINIT_CB_ID :
- hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit;
- break;
- default :
- /* update the error code */
- hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SWPMI_RX_COMPLETE_CB_ID :
+ hswpmi->RxCpltCallback = HAL_SWPMI_RxCpltCallback;
+ break;
+ case HAL_SWPMI_RX_HALFCOMPLETE_CB_ID :
+ hswpmi->RxHalfCpltCallback = HAL_SWPMI_RxHalfCpltCallback;
+ break;
+ case HAL_SWPMI_TX_COMPLETE_CB_ID :
+ hswpmi->TxCpltCallback = HAL_SWPMI_TxCpltCallback;
+ break;
+ case HAL_SWPMI_TX_HALFCOMPLETE_CB_ID :
+ hswpmi->TxHalfCpltCallback = HAL_SWPMI_TxHalfCpltCallback;
+ break;
+ case HAL_SWPMI_ERROR_CB_ID :
+ hswpmi->ErrorCallback = HAL_SWPMI_ErrorCallback;
+ break;
+ case HAL_SWPMI_MSPINIT_CB_ID :
+ hswpmi->MspInitCallback = HAL_SWPMI_MspInit;
+ break;
+ case HAL_SWPMI_MSPDEINIT_CB_ID :
+ hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit;
+ break;
+ default :
+ /* update the error code */
+ hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(hswpmi->State == HAL_SWPMI_STATE_RESET)
+ else if (hswpmi->State == HAL_SWPMI_STATE_RESET)
{
switch (CallbackID)
{
- case HAL_SWPMI_MSPINIT_CB_ID :
- hswpmi->MspInitCallback = HAL_SWPMI_MspInit;
- break;
- case HAL_SWPMI_MSPDEINIT_CB_ID :
- hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit;
- break;
- default :
- /* update the error code */
- hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SWPMI_MSPINIT_CB_ID :
+ hswpmi->MspInitCallback = HAL_SWPMI_MspInit;
+ break;
+ case HAL_SWPMI_MSPDEINIT_CB_ID :
+ hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit;
+ break;
+ default :
+ /* update the error code */
+ hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -643,7 +642,7 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart = HAL_GetTick();
HAL_StatusTypeDef status = HAL_OK;
@@ -651,7 +650,7 @@
uint32_t *ptmp_data;
uint32_t tmp_size;
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
status = HAL_ERROR;
}
@@ -661,10 +660,10 @@
__HAL_LOCK(hswpmi);
tmp_state = hswpmi->State;
- if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX))
+ if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX))
{
/* Check if a non-blocking receive process is ongoing or not */
- if(tmp_state == HAL_SWPMI_STATE_READY)
+ if (tmp_state == HAL_SWPMI_STATE_READY)
{
hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
@@ -687,7 +686,7 @@
do
{
/* Wait the TXE to write data */
- if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_TXE))
+ if (HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_TXE))
{
hswpmi->Instance->TDR = *ptmp_data;
ptmp_data++;
@@ -696,19 +695,20 @@
else
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
status = HAL_TIMEOUT;
break;
}
}
}
- } while(tmp_size != 0U);
+ }
+ while (tmp_size != 0U);
/* Wait on TXBEF flag to be able to start a second transfer */
- if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, Timeout) != HAL_OK)
+ if (SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, Timeout) != HAL_OK)
{
/* Timeout occurred */
hswpmi->ErrorCode |= HAL_SWPMI_ERROR_TXBEF_TIMEOUT;
@@ -716,10 +716,10 @@
status = HAL_TIMEOUT;
}
- if(status == HAL_OK)
+ if (status == HAL_OK)
{
/* Check if a non-blocking receive Process is ongoing or not */
- if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
+ if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
{
hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
}
@@ -735,7 +735,7 @@
}
}
- if((status != HAL_OK) && (status != HAL_BUSY))
+ if ((status != HAL_OK) && (status != HAL_BUSY))
{
hswpmi->State = HAL_SWPMI_STATE_READY;
}
@@ -762,7 +762,7 @@
uint32_t *ptmp_data;
uint32_t tmp_size;
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
status = HAL_ERROR;
}
@@ -772,10 +772,10 @@
__HAL_LOCK(hswpmi);
tmp_state = hswpmi->State;
- if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX))
+ if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX))
{
/* Check if a non-blocking transmit process is ongoing or not */
- if(tmp_state == HAL_SWPMI_STATE_READY)
+ if (tmp_state == HAL_SWPMI_STATE_READY)
{
hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
@@ -795,7 +795,7 @@
do
{
/* Wait the RXNE to read data */
- if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXNE))
+ if (HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXNE))
{
*ptmp_data = hswpmi->Instance->RDR;
ptmp_data++;
@@ -804,27 +804,28 @@
else
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
status = HAL_TIMEOUT;
break;
}
}
}
- } while(tmp_size != 0U);
+ }
+ while (tmp_size != 0U);
- if(status == HAL_OK)
+ if (status == HAL_OK)
{
- if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXBFF))
+ if (HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXBFF))
{
/* Clear RXBFF at end of reception */
WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXBFF);
}
/* Check if a non-blocking transmit Process is ongoing or not */
- if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
+ if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
{
hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
}
@@ -840,7 +841,7 @@
}
}
- if((status != HAL_OK) && (status != HAL_BUSY))
+ if ((status != HAL_OK) && (status != HAL_BUSY))
{
hswpmi->State = HAL_SWPMI_STATE_READY;
}
@@ -863,7 +864,7 @@
HAL_StatusTypeDef status = HAL_OK;
HAL_SWPMI_StateTypeDef tmp_state;
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
status = HAL_ERROR;
}
@@ -873,7 +874,7 @@
__HAL_LOCK(hswpmi);
tmp_state = hswpmi->State;
- if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX))
+ if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX))
{
/* Update handle */
hswpmi->pTxBuffPtr = pData;
@@ -882,7 +883,7 @@
hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
/* Check if a receive process is ongoing or not */
- if(tmp_state == HAL_SWPMI_STATE_READY)
+ if (tmp_state == HAL_SWPMI_STATE_READY)
{
hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
@@ -930,7 +931,7 @@
HAL_StatusTypeDef status = HAL_OK;
HAL_SWPMI_StateTypeDef tmp_state;
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
status = HAL_ERROR;
}
@@ -940,7 +941,7 @@
__HAL_LOCK(hswpmi);
tmp_state = hswpmi->State;
- if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX))
+ if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX))
{
/* Update handle */
hswpmi->pRxBuffPtr = pData;
@@ -949,7 +950,7 @@
hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
/* Check if a transmit process is ongoing or not */
- if(tmp_state == HAL_SWPMI_STATE_READY)
+ if (tmp_state == HAL_SWPMI_STATE_READY)
{
hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
@@ -993,7 +994,7 @@
HAL_StatusTypeDef status = HAL_OK;
HAL_SWPMI_StateTypeDef tmp_state;
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
status = HAL_ERROR;
}
@@ -1003,7 +1004,7 @@
__HAL_LOCK(hswpmi);
tmp_state = hswpmi->State;
- if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX))
+ if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX))
{
/* Update handle */
hswpmi->pTxBuffPtr = pData;
@@ -1012,7 +1013,7 @@
hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
/* Check if a receive process is ongoing or not */
- if(tmp_state == HAL_SWPMI_STATE_READY)
+ if (tmp_state == HAL_SWPMI_STATE_READY)
{
hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
@@ -1034,7 +1035,7 @@
hswpmi->hdmatx->XferErrorCallback = SWPMI_DMAError;
/* Enable the SWPMI transmit DMA channel */
- if(HAL_DMA_Start_IT(hswpmi->hdmatx, (uint32_t)hswpmi->pTxBuffPtr, (uint32_t)&hswpmi->Instance->TDR, Size) != HAL_OK)
+ if (HAL_DMA_Start_IT(hswpmi->hdmatx, (uint32_t)hswpmi->pTxBuffPtr, (uint32_t)&hswpmi->Instance->TDR, Size) != HAL_OK)
{
hswpmi->State = tmp_state; /* Back to previous state */
hswpmi->ErrorCode = HAL_SWPMI_ERROR_DMA;
@@ -1080,7 +1081,7 @@
HAL_StatusTypeDef status = HAL_OK;
HAL_SWPMI_StateTypeDef tmp_state;
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
status = HAL_ERROR;
}
@@ -1090,7 +1091,7 @@
__HAL_LOCK(hswpmi);
tmp_state = hswpmi->State;
- if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX))
+ if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX))
{
/* Update handle */
hswpmi->pRxBuffPtr = pData;
@@ -1098,7 +1099,7 @@
hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
/* Check if a transmit process is ongoing or not */
- if(tmp_state == HAL_SWPMI_STATE_READY)
+ if (tmp_state == HAL_SWPMI_STATE_READY)
{
hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
@@ -1120,7 +1121,7 @@
hswpmi->hdmarx->XferErrorCallback = SWPMI_DMAError;
/* Enable the DMA request */
- if(HAL_DMA_Start_IT(hswpmi->hdmarx, (uint32_t)&hswpmi->Instance->RDR, (uint32_t)hswpmi->pRxBuffPtr, Size) != HAL_OK)
+ if (HAL_DMA_Start_IT(hswpmi->hdmarx, (uint32_t)&hswpmi->Instance->RDR, (uint32_t)hswpmi->pRxBuffPtr, Size) != HAL_OK)
{
hswpmi->State = tmp_state; /* Back to previous state */
hswpmi->ErrorCode = HAL_SWPMI_ERROR_DMA;
@@ -1170,18 +1171,18 @@
CLEAR_BIT(hswpmi->Instance->CR, (SWPMI_CR_TXDMA | SWPMI_CR_RXDMA));
/* Abort the SWPMI DMA tx channel */
- if(hswpmi->hdmatx != NULL)
+ if (hswpmi->hdmatx != NULL)
{
- if(HAL_DMA_Abort(hswpmi->hdmatx) != HAL_OK)
+ if (HAL_DMA_Abort(hswpmi->hdmatx) != HAL_OK)
{
hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA;
status = HAL_ERROR;
}
}
/* Abort the SWPMI DMA rx channel */
- if(hswpmi->hdmarx != NULL)
+ if (hswpmi->hdmarx != NULL)
{
- if(HAL_DMA_Abort(hswpmi->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort(hswpmi->hdmarx) != HAL_OK)
{
hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA;
status = HAL_ERROR;
@@ -1286,7 +1287,7 @@
uint32_t errcode = HAL_SWPMI_ERROR_NONE;
/* SWPMI CRC error interrupt occurred --------------------------------------*/
- if(((regisr & SWPMI_FLAG_RXBERF) != 0U) && ((regier & SWPMI_IT_RXBERIE) != 0U))
+ if (((regisr & SWPMI_FLAG_RXBERF) != 0U) && ((regier & SWPMI_IT_RXBERIE) != 0U))
{
/* Disable Receive CRC interrupt */
CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RXBERIE | SWPMI_IT_RXBFIE);
@@ -1297,7 +1298,7 @@
}
/* SWPMI Over-Run interrupt occurred -----------------------------------------*/
- if(((regisr & SWPMI_FLAG_RXOVRF) != 0U) && ((regier & SWPMI_IT_RXOVRIE) != 0U))
+ if (((regisr & SWPMI_FLAG_RXOVRF) != 0U) && ((regier & SWPMI_IT_RXOVRIE) != 0U))
{
/* Disable Receive overrun interrupt */
CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RXOVRIE);
@@ -1308,7 +1309,7 @@
}
/* SWPMI Under-Run interrupt occurred -----------------------------------------*/
- if(((regisr & SWPMI_FLAG_TXUNRF) != 0U) && ((regier & SWPMI_IT_TXUNRIE) != 0U))
+ if (((regisr & SWPMI_FLAG_TXUNRF) != 0U) && ((regier & SWPMI_IT_TXUNRIE) != 0U))
{
/* Disable Transmit under run interrupt */
CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TXUNRIE);
@@ -1318,27 +1319,27 @@
errcode |= HAL_SWPMI_ERROR_UDR;
}
- /* Call SWPMI Error Call back function if needed --------------------------*/
- if(errcode != HAL_SWPMI_ERROR_NONE)
+ /* Call SWPMI Error Call back function if needed --------------------------*/
+ if (errcode != HAL_SWPMI_ERROR_NONE)
{
hswpmi->ErrorCode |= errcode;
- if((errcode & HAL_SWPMI_ERROR_UDR) != 0U)
+ if ((errcode & HAL_SWPMI_ERROR_UDR) != 0U)
{
/* Check TXDMA transfer to abort */
- if(HAL_IS_BIT_SET(hswpmi->Instance->CR, SWPMI_CR_TXDMA))
+ if (HAL_IS_BIT_SET(hswpmi->Instance->CR, SWPMI_CR_TXDMA))
{
/* Disable DMA TX at SWPMI level */
CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA);
/* Abort the USART DMA Tx channel */
- if(hswpmi->hdmatx != NULL)
+ if (hswpmi->hdmatx != NULL)
{
/* Set the SWPMI Tx DMA Abort callback :
will lead to call HAL_SWPMI_ErrorCallback() at end of DMA abort procedure */
hswpmi->hdmatx->XferAbortCallback = SWPMI_DMAAbortOnError;
/* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hswpmi->hdmatx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hswpmi->hdmatx) != HAL_OK)
{
/* Call Directly hswpmi->hdmatx->XferAbortCallback function in case of error */
hswpmi->hdmatx->XferAbortCallback(hswpmi->hdmatx);
@@ -1371,19 +1372,19 @@
else
{
/* Check RXDMA transfer to abort */
- if(HAL_IS_BIT_SET(hswpmi->Instance->CR, SWPMI_CR_RXDMA))
+ if (HAL_IS_BIT_SET(hswpmi->Instance->CR, SWPMI_CR_RXDMA))
{
/* Disable DMA RX at SWPMI level */
CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA);
/* Abort the USART DMA Rx channel */
- if(hswpmi->hdmarx != NULL)
+ if (hswpmi->hdmarx != NULL)
{
/* Set the SWPMI Rx DMA Abort callback :
will lead to call HAL_SWPMI_ErrorCallback() at end of DMA abort procedure */
hswpmi->hdmarx->XferAbortCallback = SWPMI_DMAAbortOnError;
/* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hswpmi->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hswpmi->hdmarx) != HAL_OK)
{
/* Call Directly hswpmi->hdmarx->XferAbortCallback function in case of error */
hswpmi->hdmarx->XferAbortCallback(hswpmi->hdmarx);
@@ -1416,31 +1417,31 @@
}
/* SWPMI in mode Receiver ---------------------------------------------------*/
- if(((regisr & SWPMI_FLAG_RXNE) != 0U) && ((regier & SWPMI_IT_RIE) != 0U))
+ if (((regisr & SWPMI_FLAG_RXNE) != 0U) && ((regier & SWPMI_IT_RIE) != 0U))
{
SWPMI_Receive_IT(hswpmi);
}
/* SWPMI in mode Transmitter ------------------------------------------------*/
- if(((regisr & SWPMI_FLAG_TXE) != 0U) && ((regier & SWPMI_IT_TIE) != 0U))
+ if (((regisr & SWPMI_FLAG_TXE) != 0U) && ((regier & SWPMI_IT_TIE) != 0U))
{
SWPMI_Transmit_IT(hswpmi);
}
/* SWPMI in mode Transmitter (Transmit buffer empty) ------------------------*/
- if(((regisr & SWPMI_FLAG_TXBEF) != 0U) && ((regier & SWPMI_IT_TXBEIE) != 0U))
+ if (((regisr & SWPMI_FLAG_TXBEF) != 0U) && ((regier & SWPMI_IT_TXBEIE) != 0U))
{
SWPMI_EndTransmit_IT(hswpmi);
}
/* SWPMI in mode Receiver (Receive buffer full) -----------------------------*/
- if(((regisr & SWPMI_FLAG_RXBFF) != 0U) && ((regier & SWPMI_IT_RXBFIE) != 0U))
+ if (((regisr & SWPMI_FLAG_RXBFF) != 0U) && ((regier & SWPMI_IT_RXBFIE) != 0U))
{
SWPMI_EndReceive_IT(hswpmi);
}
/* Both Transmission and reception complete ---------------------------------*/
- if(((regisr & SWPMI_FLAG_TCF) != 0U) && ((regier & SWPMI_IT_TCIE) != 0U))
+ if (((regisr & SWPMI_FLAG_TCF) != 0U) && ((regier & SWPMI_IT_TCIE) != 0U))
{
SWPMI_EndTransmitReceive_IT(hswpmi);
}
@@ -1588,14 +1589,14 @@
if ((tmp_state == HAL_SWPMI_STATE_BUSY_TX) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX_RX))
{
- if(hswpmi->TxXferCount == 0U)
+ if (hswpmi->TxXferCount == 0U)
{
/* Disable the SWPMI TXE and Underrun Interrupts */
CLEAR_BIT(hswpmi->Instance->IER, (SWPMI_IT_TIE | SWPMI_IT_TXUNRIE));
}
else
{
- hswpmi->Instance->TDR = (uint32_t)*hswpmi->pTxBuffPtr;
+ hswpmi->Instance->TDR = (uint32_t) * hswpmi->pTxBuffPtr;
hswpmi->pTxBuffPtr++;
hswpmi->TxXferCount--;
}
@@ -1619,7 +1620,7 @@
CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TIE | SWPMI_IT_TXUNRIE | SWPMI_IT_TXBEIE);
/* Check if a receive Process is ongoing or not */
- if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
+ if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
{
hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
}
@@ -1645,13 +1646,13 @@
{
HAL_SWPMI_StateTypeDef tmp_state = hswpmi->State;
- if((tmp_state == HAL_SWPMI_STATE_BUSY_RX) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX_RX))
+ if ((tmp_state == HAL_SWPMI_STATE_BUSY_RX) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX_RX))
{
*hswpmi->pRxBuffPtr = (uint32_t)(hswpmi->Instance->RDR);
hswpmi->pRxBuffPtr++;
--hswpmi->RxXferCount;
- if(hswpmi->RxXferCount == 0U)
+ if (hswpmi->RxXferCount == 0U)
{
/* Wait for RXBFF flag to update state */
#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
@@ -1680,7 +1681,7 @@
CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RIE | SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE | SWPMI_IT_RXBFIE);
/* Check if a transmit Process is ongoing or not */
- if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
+ if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
{
hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
}
@@ -1703,11 +1704,11 @@
CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TCIE);
/* Check if a receive Process is ongoing or not */
- if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
+ if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
{
hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
}
- else if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX)
+ else if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX)
{
hswpmi->State = HAL_SWPMI_STATE_READY;
}
@@ -1724,11 +1725,11 @@
*/
static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
- SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
uint32_t tickstart;
/* DMA Normal mode*/
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{
hswpmi->TxXferCount = 0U;
@@ -1736,11 +1737,11 @@
in the SWPMI CR register */
CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA);
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
/* Wait the TXBEF */
- if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, SWPMI_TIMEOUT_VALUE) != HAL_OK)
+ if (SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, SWPMI_TIMEOUT_VALUE) != HAL_OK)
{
/* Timeout occurred */
hswpmi->ErrorCode |= HAL_SWPMI_ERROR_TXBEF_TIMEOUT;
@@ -1755,7 +1756,7 @@
{
/* No Timeout */
/* Check if a receive process is ongoing or not */
- if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
+ if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
{
hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
}
@@ -1789,7 +1790,7 @@
*/
static void SWPMI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
- SWPMI_HandleTypeDef* hswpmi = (SWPMI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
hswpmi->TxHalfCpltCallback(hswpmi);
@@ -1806,10 +1807,10 @@
*/
static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* DMA Normal mode*/
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{
hswpmi->RxXferCount = 0U;
@@ -1818,7 +1819,7 @@
CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA);
/* Check if a transmit Process is ongoing or not */
- if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
+ if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
{
hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
}
@@ -1841,7 +1842,7 @@
*/
static void SWPMI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
- SWPMI_HandleTypeDef* hswpmi = (SWPMI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
hswpmi->RxHalfCpltCallback(hswpmi);
@@ -1857,12 +1858,12 @@
*/
static void SWPMI_DMAError(DMA_HandleTypeDef *hdma)
{
- SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Update handle */
hswpmi->RxXferCount = 0U;
hswpmi->TxXferCount = 0U;
- hswpmi->State= HAL_SWPMI_STATE_READY;
+ hswpmi->State = HAL_SWPMI_STATE_READY;
hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA;
#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
@@ -1879,12 +1880,12 @@
*/
static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
- SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Update handle */
hswpmi->RxXferCount = 0U;
hswpmi->TxXferCount = 0U;
- hswpmi->State= HAL_SWPMI_STATE_READY;
+ hswpmi->State = HAL_SWPMI_STATE_READY;
#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
hswpmi->ErrorCallback(hswpmi);
@@ -1906,7 +1907,7 @@
HAL_StatusTypeDef status = HAL_OK;
/* Wait until flag is set */
- while(!(HAL_IS_BIT_SET(hswpmi->Instance->ISR, Flag)))
+ while (!(HAL_IS_BIT_SET(hswpmi->Instance->ISR, Flag)))
{
/* Check for the Timeout */
if ((((HAL_GetTick() - Tickstart) > Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
@@ -1937,5 +1938,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_tim.c b/Src/stm32l4xx_hal_tim.c
index 9ebce6e..c945979 100644
--- a/Src/stm32l4xx_hal_tim.c
+++ b/Src/stm32l4xx_hal_tim.c
@@ -29,6 +29,17 @@
* + Commutation Event configuration with Interruption and DMA
* + TIM OCRef clear configuration
* + TIM External Clock configuration
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### TIMER Generic features #####
@@ -103,14 +114,14 @@
allows the user to configure dynamically the driver callbacks.
[..]
- Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
- @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+ Use Function HAL_TIM_RegisterCallback() to register a callback.
+ HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
the Callback ID and a pointer to the user callback function.
[..]
- Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
weak function.
- @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
[..]
@@ -147,7 +158,7 @@
[..]
By default, after the Init and when the state is HAL_TIM_STATE_RESET
all interrupt callbacks are set to the corresponding weak functions:
- examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
+ examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
[..]
Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
@@ -161,7 +172,7 @@
in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
+ using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
[..]
When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
@@ -170,17 +181,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -561,7 +561,8 @@
htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -881,6 +882,7 @@
*/
HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
/* Check the parameters */
@@ -926,34 +928,38 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Enable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (status == HAL_OK)
{
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
}
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -969,6 +975,8 @@
*/
HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
@@ -1003,26 +1011,30 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Disable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (status == HAL_OK)
{
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
}
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -1040,6 +1052,7 @@
*/
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
/* Check the parameters */
@@ -1078,7 +1091,8 @@
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -1099,7 +1113,8 @@
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -1120,7 +1135,8 @@
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -1140,7 +1156,8 @@
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -1151,34 +1168,38 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Enable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (status == HAL_OK)
{
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
}
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -1194,6 +1215,8 @@
*/
HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
@@ -1232,26 +1255,30 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Disable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (status == HAL_OK)
{
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
}
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -1522,7 +1549,9 @@
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
@@ -1566,34 +1595,38 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (status == HAL_OK)
{
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
}
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -1609,6 +1642,8 @@
*/
HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
@@ -1643,26 +1678,30 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Disable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (status == HAL_OK)
{
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
}
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -1680,6 +1719,7 @@
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
/* Check the parameters */
@@ -1718,7 +1758,8 @@
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -1739,7 +1780,8 @@
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -1759,7 +1801,8 @@
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -1779,7 +1822,8 @@
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -1790,34 +1834,38 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (status == HAL_OK)
{
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
}
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -1833,6 +1881,8 @@
*/
HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
@@ -1871,26 +1921,30 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Disable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (status == HAL_OK)
{
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
}
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -2150,7 +2204,9 @@
*/
HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
+
HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
@@ -2199,27 +2255,32 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Enable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ if (status == HAL_OK)
{
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
}
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -2235,6 +2296,8 @@
*/
HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
@@ -2269,21 +2332,25 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Disable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+ if (status == HAL_OK)
+ {
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -2301,7 +2368,9 @@
*/
HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
+
HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
@@ -2336,20 +2405,6 @@
/* Enable the Input Capture channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -2362,7 +2417,8 @@
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -2382,7 +2438,8 @@
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -2402,7 +2459,8 @@
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -2422,7 +2480,8 @@
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -2433,11 +2492,26 @@
}
default:
+ status = HAL_ERROR;
break;
}
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -2453,6 +2527,8 @@
*/
HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
@@ -2495,18 +2571,22 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
+ if (status == HAL_OK)
+ {
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
* @}
@@ -2692,8 +2772,8 @@
* @brief Starts the TIM One Pulse signal generation.
* @note Though OutputChannel parameter is deprecated and ignored by the function
* it has been kept to avoid HAL_TIM API compatibility break.
- * @note The pulse output channel is determined when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
* @param OutputChannel See note above
* @retval HAL status
@@ -2749,8 +2829,8 @@
* @brief Stops the TIM One Pulse signal generation.
* @note Though OutputChannel parameter is deprecated and ignored by the function
* it has been kept to avoid HAL_TIM API compatibility break.
- * @note The pulse output channel is determined when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
* @param OutputChannel See note above
* @retval HAL status
@@ -2792,8 +2872,8 @@
* @brief Starts the TIM One Pulse signal generation in interrupt mode.
* @note Though OutputChannel parameter is deprecated and ignored by the function
* it has been kept to avoid HAL_TIM API compatibility break.
- * @note The pulse output channel is determined when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
* @param OutputChannel See note above
* @retval HAL status
@@ -2855,8 +2935,8 @@
* @brief Stops the TIM One Pulse signal generation in interrupt mode.
* @note Though OutputChannel parameter is deprecated and ignored by the function
* it has been kept to avoid HAL_TIM API compatibility break.
- * @note The pulse output channel is determined when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
* @param OutputChannel See note above
* @retval HAL status
@@ -3559,7 +3639,8 @@
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -3567,11 +3648,12 @@
/* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
break;
}
@@ -3584,7 +3666,8 @@
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -3592,15 +3675,16 @@
/* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
break;
}
- case TIM_CHANNEL_ALL:
+ default:
{
/* Set the DMA capture callbacks */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
@@ -3610,7 +3694,8 @@
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -3624,27 +3709,27 @@
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
/* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
/* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
break;
}
-
- default:
- break;
}
/* Return function status */
@@ -3972,6 +4057,8 @@
TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_CHANNELS(Channel));
assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
@@ -4043,12 +4130,13 @@
}
default:
+ status = HAL_ERROR;
break;
}
__HAL_UNLOCK(htim);
- return HAL_OK;
+ return status;
}
/**
@@ -4066,6 +4154,8 @@
*/
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
@@ -4122,7 +4212,7 @@
/* Set the IC3PSC value */
htim->Instance->CCMR2 |= sConfig->ICPrescaler;
}
- else
+ else if (Channel == TIM_CHANNEL_4)
{
/* TI4 Configuration */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
@@ -4138,10 +4228,14 @@
/* Set the IC4PSC value */
htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
}
+ else
+ {
+ status = HAL_ERROR;
+ }
__HAL_UNLOCK(htim);
- return HAL_OK;
+ return status;
}
/**
@@ -4163,6 +4257,8 @@
TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_CHANNELS(Channel));
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
@@ -4277,12 +4373,13 @@
}
default:
+ status = HAL_ERROR;
break;
}
__HAL_UNLOCK(htim);
- return HAL_OK;
+ return status;
}
/**
@@ -4307,6 +4404,7 @@
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
uint32_t OutputChannel, uint32_t InputChannel)
{
+ HAL_StatusTypeDef status = HAL_OK;
TIM_OC_InitTypeDef temp1;
/* Check the parameters */
@@ -4337,6 +4435,7 @@
TIM_OC1_SetConfig(htim->Instance, &temp1);
break;
}
+
case TIM_CHANNEL_2:
{
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
@@ -4344,60 +4443,67 @@
TIM_OC2_SetConfig(htim->Instance, &temp1);
break;
}
+
default:
+ status = HAL_ERROR;
break;
}
- switch (InputChannel)
+ if (status == HAL_OK)
{
- case TIM_CHANNEL_1:
+ switch (InputChannel)
{
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
- sConfig->ICSelection, sConfig->ICFilter);
+ TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
+ sConfig->ICSelection, sConfig->ICFilter);
- /* Reset the IC1PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
- /* Select the Trigger source */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= TIM_TS_TI1FP1;
+ /* Select the Trigger source */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI1FP1;
- /* Select the Slave Mode */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
- htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
- break;
+ /* Select the Slave Mode */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
+ sConfig->ICSelection, sConfig->ICFilter);
+
+ /* Reset the IC2PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+ /* Select the Trigger source */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI2FP2;
+
+ /* Select the Slave Mode */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
}
- case TIM_CHANNEL_2:
- {
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
- sConfig->ICSelection, sConfig->ICFilter);
-
- /* Reset the IC2PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
- /* Select the Trigger source */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= TIM_TS_TI2FP2;
-
- /* Select the Slave Mode */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
- htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
- break;
- }
-
- default:
- break;
}
htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
- return HAL_OK;
+ return status;
}
else
{
@@ -4429,9 +4535,9 @@
* @arg TIM_DMABASE_CCR4
* @arg TIM_DMABASE_BDTR
* @arg TIM_DMABASE_OR1
- * @arg TIM_DMABASE_CCMR3
- * @arg TIM_DMABASE_CCR5
- * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
* @arg TIM_DMABASE_OR2
* @arg TIM_DMABASE_OR3
* @param BurstRequestSrc TIM DMA Request sources
@@ -4452,8 +4558,14 @@
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
{
- return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
- ((BurstLength) >> 8U) + 1U);
+ HAL_StatusTypeDef status;
+
+ status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+ ((BurstLength) >> 8U) + 1U);
+
+
+
+ return status;
}
/**
@@ -4480,9 +4592,9 @@
* @arg TIM_DMABASE_CCR4
* @arg TIM_DMABASE_BDTR
* @arg TIM_DMABASE_OR1
- * @arg TIM_DMABASE_CCMR3
- * @arg TIM_DMABASE_CCR5
- * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
* @arg TIM_DMABASE_OR2
* @arg TIM_DMABASE_OR3
* @param BurstRequestSrc TIM DMA Request sources
@@ -4505,6 +4617,8 @@
uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
uint32_t BurstLength, uint32_t DataLength)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
@@ -4531,6 +4645,7 @@
{
/* nothing to do */
}
+
switch (BurstRequestSrc)
{
case TIM_DMA_UPDATE:
@@ -4544,7 +4659,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -4562,7 +4677,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -4580,7 +4695,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -4598,7 +4713,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -4616,7 +4731,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -4634,7 +4749,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -4652,7 +4767,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -4660,16 +4775,20 @@
break;
}
default:
+ status = HAL_ERROR;
break;
}
- /* Configure the DMA Burst Mode */
- htim->Instance->DCR = (BurstBaseAddress | BurstLength);
- /* Enable the TIM DMA Request */
- __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+ if (status == HAL_OK)
+ {
+ /* Configure the DMA Burst Mode */
+ htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+ /* Enable the TIM DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+ }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -4680,6 +4799,8 @@
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
@@ -4722,17 +4843,21 @@
break;
}
default:
+ status = HAL_ERROR;
break;
}
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+ if (status == HAL_OK)
+ {
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -4759,9 +4884,9 @@
* @arg TIM_DMABASE_CCR4
* @arg TIM_DMABASE_BDTR
* @arg TIM_DMABASE_OR1
- * @arg TIM_DMABASE_CCMR3
- * @arg TIM_DMABASE_CCR5
- * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
* @arg TIM_DMABASE_OR2
* @arg TIM_DMABASE_OR3
* @param BurstRequestSrc TIM DMA Request sources
@@ -4782,8 +4907,13 @@
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
{
- return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
- ((BurstLength) >> 8U) + 1U);
+ HAL_StatusTypeDef status;
+
+ status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+ ((BurstLength) >> 8U) + 1U);
+
+
+ return status;
}
/**
@@ -4810,9 +4940,9 @@
* @arg TIM_DMABASE_CCR4
* @arg TIM_DMABASE_BDTR
* @arg TIM_DMABASE_OR1
- * @arg TIM_DMABASE_CCMR3
- * @arg TIM_DMABASE_CCR5
- * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
* @arg TIM_DMABASE_OR2
* @arg TIM_DMABASE_OR3
* @param BurstRequestSrc TIM DMA Request sources
@@ -4835,6 +4965,8 @@
uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
uint32_t BurstLength, uint32_t DataLength)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
@@ -4874,7 +5006,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -4892,7 +5024,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -4910,7 +5042,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -4928,7 +5060,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -4946,7 +5078,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -4964,7 +5096,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -4982,7 +5114,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -4990,17 +5122,21 @@
break;
}
default:
+ status = HAL_ERROR;
break;
}
- /* Configure the DMA Burst Mode */
- htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+ if (status == HAL_OK)
+ {
+ /* Configure the DMA Burst Mode */
+ htim->Instance->DCR = (BurstBaseAddress | BurstLength);
- /* Enable the TIM DMA Request */
- __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+ /* Enable the TIM DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+ }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -5011,6 +5147,8 @@
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
@@ -5053,17 +5191,21 @@
break;
}
default:
+ status = HAL_ERROR;
break;
}
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+ if (status == HAL_OK)
+ {
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -5130,6 +5272,8 @@
TIM_ClearInputConfigTypeDef *sClearInputConfig,
uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
@@ -5151,8 +5295,8 @@
{
/* Clear the OCREF clear selection bit */
CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
+ break;
}
- break;
case TIM_CLEARINPUTSOURCE_ETR:
{
@@ -5180,104 +5324,108 @@
}
default:
+ status = HAL_ERROR;
break;
}
- switch (Channel)
+ if (status == HAL_OK)
{
- case TIM_CHANNEL_1:
+ switch (Channel)
{
- if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ case TIM_CHANNEL_1:
{
- /* Enable the OCREF clear feature for Channel 1 */
- SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 1 */
+ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 1 */
+ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+ }
+ break;
}
- else
+ case TIM_CHANNEL_2:
{
- /* Disable the OCREF clear feature for Channel 1 */
- CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 2 */
+ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 2 */
+ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+ }
+ break;
}
- break;
+ case TIM_CHANNEL_3:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 3 */
+ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 3 */
+ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+ }
+ break;
+ }
+ case TIM_CHANNEL_4:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 4 */
+ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 4 */
+ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+ }
+ break;
+ }
+ case TIM_CHANNEL_5:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 5 */
+ SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 5 */
+ CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+ }
+ break;
+ }
+ case TIM_CHANNEL_6:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 6 */
+ SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 6 */
+ CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+ }
+ break;
+ }
+ default:
+ break;
}
- case TIM_CHANNEL_2:
- {
- if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
- {
- /* Enable the OCREF clear feature for Channel 2 */
- SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
- }
- else
- {
- /* Disable the OCREF clear feature for Channel 2 */
- CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
- }
- break;
- }
- case TIM_CHANNEL_3:
- {
- if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
- {
- /* Enable the OCREF clear feature for Channel 3 */
- SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
- }
- else
- {
- /* Disable the OCREF clear feature for Channel 3 */
- CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
- }
- break;
- }
- case TIM_CHANNEL_4:
- {
- if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
- {
- /* Enable the OCREF clear feature for Channel 4 */
- SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
- }
- else
- {
- /* Disable the OCREF clear feature for Channel 4 */
- CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
- }
- break;
- }
- case TIM_CHANNEL_5:
- {
- if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
- {
- /* Enable the OCREF clear feature for Channel 5 */
- SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
- }
- else
- {
- /* Disable the OCREF clear feature for Channel 5 */
- CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
- }
- break;
- }
- case TIM_CHANNEL_6:
- {
- if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
- {
- /* Enable the OCREF clear feature for Channel 6 */
- SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
- }
- else
- {
- /* Disable the OCREF clear feature for Channel 6 */
- CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
- }
- break;
- }
- default:
- break;
}
htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
- return HAL_OK;
+ return status;
}
/**
@@ -5289,6 +5437,7 @@
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
/* Process Locked */
@@ -5409,22 +5558,23 @@
case TIM_CLOCKSOURCE_ITR1:
case TIM_CLOCKSOURCE_ITR2:
case TIM_CLOCKSOURCE_ITR3:
- {
- /* Check whether or not the timer instance supports internal trigger input */
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+ {
+ /* Check whether or not the timer instance supports internal trigger input */
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
- TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
- break;
- }
+ TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+ break;
+ }
default:
+ status = HAL_ERROR;
break;
}
htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
- return HAL_OK;
+ return status;
}
/**
@@ -5950,7 +6100,7 @@
default :
/* Return error status */
- status = HAL_ERROR;
+ status = HAL_ERROR;
break;
}
}
@@ -6016,14 +6166,14 @@
default :
/* Return error status */
- status = HAL_ERROR;
+ status = HAL_ERROR;
break;
}
}
else
{
/* Return error status */
- status = HAL_ERROR;
+ status = HAL_ERROR;
}
/* Release Lock */
@@ -6080,120 +6230,148 @@
switch (CallbackID)
{
case HAL_TIM_BASE_MSPINIT_CB_ID :
- htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
+ /* Legacy weak Base MspInit Callback */
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
break;
case HAL_TIM_BASE_MSPDEINIT_CB_ID :
- htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
+ /* Legacy weak Base Msp DeInit Callback */
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
break;
case HAL_TIM_IC_MSPINIT_CB_ID :
- htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
+ /* Legacy weak IC Msp Init Callback */
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
break;
case HAL_TIM_IC_MSPDEINIT_CB_ID :
- htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
+ /* Legacy weak IC Msp DeInit Callback */
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
break;
case HAL_TIM_OC_MSPINIT_CB_ID :
- htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
+ /* Legacy weak OC Msp Init Callback */
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
break;
case HAL_TIM_OC_MSPDEINIT_CB_ID :
- htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
+ /* Legacy weak OC Msp DeInit Callback */
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
break;
case HAL_TIM_PWM_MSPINIT_CB_ID :
- htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
+ /* Legacy weak PWM Msp Init Callback */
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
break;
case HAL_TIM_PWM_MSPDEINIT_CB_ID :
- htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
+ /* Legacy weak PWM Msp DeInit Callback */
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
break;
case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
- htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
+ /* Legacy weak One Pulse Msp Init Callback */
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
break;
case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
- htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
+ /* Legacy weak One Pulse Msp DeInit Callback */
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
break;
case HAL_TIM_ENCODER_MSPINIT_CB_ID :
- htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
+ /* Legacy weak Encoder Msp Init Callback */
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
break;
case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
- htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
+ /* Legacy weak Encoder Msp DeInit Callback */
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
break;
case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
- htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
+ /* Legacy weak Hall Sensor Msp Init Callback */
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
break;
case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
- htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
+ /* Legacy weak Hall Sensor Msp DeInit Callback */
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
break;
case HAL_TIM_PERIOD_ELAPSED_CB_ID :
- htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */
+ /* Legacy weak Period Elapsed Callback */
+ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
break;
case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
- htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */
+ /* Legacy weak Period Elapsed half complete Callback */
+ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
break;
case HAL_TIM_TRIGGER_CB_ID :
- htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */
+ /* Legacy weak Trigger Callback */
+ htim->TriggerCallback = HAL_TIM_TriggerCallback;
break;
case HAL_TIM_TRIGGER_HALF_CB_ID :
- htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */
+ /* Legacy weak Trigger half complete Callback */
+ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
break;
case HAL_TIM_IC_CAPTURE_CB_ID :
- htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */
+ /* Legacy weak IC Capture Callback */
+ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
break;
case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
- htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */
+ /* Legacy weak IC Capture half complete Callback */
+ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
break;
case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
- htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */
+ /* Legacy weak OC Delay Elapsed Callback */
+ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
break;
case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
- htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */
+ /* Legacy weak PWM Pulse Finished Callback */
+ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
break;
case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
- htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
+ /* Legacy weak PWM Pulse Finished half complete Callback */
+ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
break;
case HAL_TIM_ERROR_CB_ID :
- htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */
+ /* Legacy weak Error Callback */
+ htim->ErrorCallback = HAL_TIM_ErrorCallback;
break;
case HAL_TIM_COMMUTATION_CB_ID :
- htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */
+ /* Legacy weak Commutation Callback */
+ htim->CommutationCallback = HAL_TIMEx_CommutCallback;
break;
case HAL_TIM_COMMUTATION_HALF_CB_ID :
- htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */
+ /* Legacy weak Commutation half complete Callback */
+ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
break;
case HAL_TIM_BREAK_CB_ID :
- htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */
+ /* Legacy weak Break Callback */
+ htim->BreakCallback = HAL_TIMEx_BreakCallback;
break;
case HAL_TIM_BREAK2_CB_ID :
- htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2 Callback */
+ /* Legacy weak Break2 Callback */
+ htim->Break2Callback = HAL_TIMEx_Break2Callback;
break;
default :
/* Return error status */
- status = HAL_ERROR;
+ status = HAL_ERROR;
break;
}
}
@@ -6202,71 +6380,85 @@
switch (CallbackID)
{
case HAL_TIM_BASE_MSPINIT_CB_ID :
- htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
+ /* Legacy weak Base MspInit Callback */
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
break;
case HAL_TIM_BASE_MSPDEINIT_CB_ID :
- htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
+ /* Legacy weak Base Msp DeInit Callback */
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
break;
case HAL_TIM_IC_MSPINIT_CB_ID :
- htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
+ /* Legacy weak IC Msp Init Callback */
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
break;
case HAL_TIM_IC_MSPDEINIT_CB_ID :
- htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
+ /* Legacy weak IC Msp DeInit Callback */
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
break;
case HAL_TIM_OC_MSPINIT_CB_ID :
- htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
+ /* Legacy weak OC Msp Init Callback */
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
break;
case HAL_TIM_OC_MSPDEINIT_CB_ID :
- htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
+ /* Legacy weak OC Msp DeInit Callback */
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
break;
case HAL_TIM_PWM_MSPINIT_CB_ID :
- htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
+ /* Legacy weak PWM Msp Init Callback */
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
break;
case HAL_TIM_PWM_MSPDEINIT_CB_ID :
- htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
+ /* Legacy weak PWM Msp DeInit Callback */
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
break;
case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
- htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
+ /* Legacy weak One Pulse Msp Init Callback */
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
break;
case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
- htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
+ /* Legacy weak One Pulse Msp DeInit Callback */
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
break;
case HAL_TIM_ENCODER_MSPINIT_CB_ID :
- htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
+ /* Legacy weak Encoder Msp Init Callback */
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
break;
case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
- htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
+ /* Legacy weak Encoder Msp DeInit Callback */
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
break;
case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
- htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
+ /* Legacy weak Hall Sensor Msp Init Callback */
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
break;
case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
- htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
+ /* Legacy weak Hall Sensor Msp DeInit Callback */
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
break;
default :
/* Return error status */
- status = HAL_ERROR;
+ status = HAL_ERROR;
break;
}
}
else
{
/* Return error status */
- status = HAL_ERROR;
+ status = HAL_ERROR;
}
/* Release Lock */
@@ -7181,6 +7373,7 @@
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef *sSlaveConfig)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
uint32_t tmpccmr1;
uint32_t tmpccer;
@@ -7277,16 +7470,18 @@
case TIM_TS_ITR1:
case TIM_TS_ITR2:
case TIM_TS_ITR3:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- break;
- }
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ break;
+ }
default:
+ status = HAL_ERROR;
break;
}
- return HAL_OK;
+
+ return status;
}
/**
@@ -7662,20 +7857,20 @@
void TIM_ResetCallback(TIM_HandleTypeDef *htim)
{
/* Reset the TIM callback to the legacy weak callbacks */
- htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */
- htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */
- htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */
- htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */
- htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */
- htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */
- htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */
- htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */
- htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
- htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */
- htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */
- htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */
- htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */
- htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2Callback */
+ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
+ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
+ htim->TriggerCallback = HAL_TIM_TriggerCallback;
+ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
+ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
+ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
+ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
+ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
+ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
+ htim->ErrorCallback = HAL_TIM_ErrorCallback;
+ htim->CommutationCallback = HAL_TIMEx_CommutCallback;
+ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
+ htim->BreakCallback = HAL_TIMEx_BreakCallback;
+ htim->Break2Callback = HAL_TIMEx_Break2Callback;
}
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
@@ -7691,4 +7886,3 @@
/**
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_tim_ex.c b/Src/stm32l4xx_hal_tim_ex.c
index db658a7..6f231f7 100644
--- a/Src/stm32l4xx_hal_tim_ex.c
+++ b/Src/stm32l4xx_hal_tim_ex.c
@@ -12,6 +12,17 @@
* + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
* + Time OCRef clear configuration
* + Timer remapping capabilities configuration
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### TIMER Extended features #####
@@ -56,24 +67,16 @@
the commutation event).
(#) Activate the TIM peripheral using one of the start functions:
- (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
- (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
+ (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
+ HAL_TIMEx_OCN_Start_IT()
+ (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
+ HAL_TIMEx_PWMN_Start_IT()
(++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
- (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
+ (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
+ HAL_TIMEx_HallSensor_Start_IT().
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -337,7 +340,8 @@
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
@@ -369,7 +373,8 @@
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1, 2 and 3
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
/* Disable the Peripheral */
@@ -420,7 +425,8 @@
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
/* Enable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
@@ -452,7 +458,8 @@
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
/* Disable the capture compare Interrupts event */
@@ -512,7 +519,8 @@
}
/* Enable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
/* Set the DMA Input Capture 1 Callbacks */
@@ -559,7 +567,8 @@
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
@@ -699,6 +708,7 @@
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
/* Check the parameters */
@@ -738,34 +748,38 @@
default:
+ status = HAL_ERROR;
break;
}
- /* Enable the TIM Break interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
-
- /* Enable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ if (status == HAL_OK)
{
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ /* Enable the TIM Break interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
}
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -781,7 +795,9 @@
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpccer;
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
@@ -809,30 +825,34 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Disable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the TIM Break interrupt (only if no more channel is active) */
- tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+ if (status == HAL_OK)
{
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the TIM Break interrupt (only if no more channel is active) */
+ tmpccer = htim->Instance->CCER;
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+ {
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ }
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
}
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -850,6 +870,7 @@
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
/* Check the parameters */
@@ -888,7 +909,8 @@
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -908,7 +930,8 @@
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -928,7 +951,8 @@
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -939,31 +963,35 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Enable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ if (status == HAL_OK)
{
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
}
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -979,6 +1007,8 @@
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
@@ -1009,23 +1039,27 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Disable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+ if (status == HAL_OK)
+ {
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -1156,6 +1190,7 @@
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
/* Check the parameters */
@@ -1194,34 +1229,38 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Enable the TIM Break interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
-
- /* Enable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ if (status == HAL_OK)
{
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ /* Enable the TIM Break interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
}
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -1237,6 +1276,7 @@
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpccer;
/* Check the parameters */
@@ -1266,30 +1306,34 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Disable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the TIM Break interrupt (only if no more channel is active) */
- tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+ if (status == HAL_OK)
{
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the TIM Break interrupt (only if no more channel is active) */
+ tmpccer = htim->Instance->CCER;
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+ {
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ }
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
}
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -1307,6 +1351,7 @@
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
/* Check the parameters */
@@ -1345,7 +1390,8 @@
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -1365,7 +1411,8 @@
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -1385,7 +1432,8 @@
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -1396,31 +1444,35 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Enable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ if (status == HAL_OK)
{
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
}
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -1436,6 +1488,8 @@
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
@@ -1466,23 +1520,27 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Disable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+ if (status == HAL_OK)
+ {
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -1510,8 +1568,8 @@
/**
* @brief Starts the TIM One Pulse signal generation on the complementary
* output.
- * @note OutputChannel must match the pulse output channel chosen when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
* @param OutputChannel pulse output channel to enable
* This parameter can be one of the following values:
@@ -1531,7 +1589,7 @@
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
/* Check the TIM channels state */
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
@@ -1559,8 +1617,8 @@
/**
* @brief Stops the TIM One Pulse signal generation on the complementary
* output.
- * @note OutputChannel must match the pulse output channel chosen when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
* @param OutputChannel pulse output channel to disable
* This parameter can be one of the following values:
@@ -1598,8 +1656,8 @@
/**
* @brief Starts the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
- * @note OutputChannel must match the pulse output channel chosen when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
* @param OutputChannel pulse output channel to enable
* This parameter can be one of the following values:
@@ -1619,7 +1677,7 @@
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
/* Check the TIM channels state */
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
@@ -1653,8 +1711,8 @@
/**
* @brief Stops the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
- * @note OutputChannel must match the pulse output channel chosen when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
* @param OutputChannel pulse output channel to disable
* This parameter can be one of the following values:
@@ -2046,6 +2104,7 @@
TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmporx;
uint32_t bkin_enable_mask;
uint32_t bkin_polarity_mask;
@@ -2099,7 +2158,7 @@
case TIM_BREAKINPUTSOURCE_DFSDM1:
{
bkin_enable_mask = TIM1_OR2_BKDF1BK0E;
- bkin_enable_bitpos = 8U;
+ bkin_enable_bitpos = TIM1_OR2_BKDF1BK0E_Pos;
bkin_polarity_mask = 0U;
bkin_polarity_bitpos = 0U;
break;
@@ -2131,10 +2190,10 @@
#if defined(DFSDM1_Channel0)
if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
#endif /* DFSDM1_Channel0 */
- {
- tmporx &= ~bkin_polarity_mask;
- tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
- }
+ {
+ tmporx &= ~bkin_polarity_mask;
+ tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+ }
/* Set TIMx_OR2 */
htim->Instance->OR2 = tmporx;
@@ -2153,22 +2212,23 @@
#if defined(DFSDM1_Channel0)
if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
#endif /* DFSDM1_Channel0 */
- {
- tmporx &= ~bkin_polarity_mask;
- tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
- }
+ {
+ tmporx &= ~bkin_polarity_mask;
+ tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+ }
/* Set TIMx_OR3 */
htim->Instance->OR3 = tmporx;
break;
}
default:
+ status = HAL_ERROR;
break;
}
__HAL_UNLOCK(htim);
- return HAL_OK;
+ return status;
}
/**
@@ -2398,12 +2458,12 @@
uint32_t tmpor1;
uint32_t tmpor2;
- __HAL_LOCK(htim);
-
/* Check parameters */
assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
assert_param(IS_TIM_REMAP(Remap));
+ __HAL_LOCK(htim);
+
/* Set ETR_SEL bit field (if required) */
if (IS_TIM_ETRSEL_INSTANCE(htim->Instance))
{
@@ -2529,7 +2589,7 @@
/**
* @brief Hall Break2 detection callback in non blocking mode
- * @param htim TIM handle
+ * @param htim: TIM handle
* @retval None
*/
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
@@ -2600,7 +2660,7 @@
*/
/* Private functions ---------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
+/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
* @{
*/
@@ -2776,5 +2836,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_timebase_tim_template.c b/Src/stm32l4xx_hal_timebase_tim_template.c
index 4858c4e..7154a05 100644
--- a/Src/stm32l4xx_hal_timebase_tim_template.c
+++ b/Src/stm32l4xx_hal_timebase_tim_template.c
@@ -9,6 +9,17 @@
* + Initializes the TIM peripheral to generate a Period elapsed Event each 1ms
* + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -25,17 +36,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -207,5 +207,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_tsc.c b/Src/stm32l4xx_hal_tsc.c
index 2abff4a..9196b44 100644
--- a/Src/stm32l4xx_hal_tsc.c
+++ b/Src/stm32l4xx_hal_tsc.c
@@ -10,6 +10,17 @@
* + Read acquisition result
* + Interrupts and flags management
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
================================================================================
##### TSC specific features #####
@@ -82,10 +93,10 @@
[..]
The compilation flag USE_HAL_TSC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_TSC_RegisterCallback() to register an interrupt callback.
+ Use Functions HAL_TSC_RegisterCallback() to register an interrupt callback.
[..]
- Function @ref HAL_TSC_RegisterCallback() allows to register following callbacks:
+ Function HAL_TSC_RegisterCallback() allows to register following callbacks:
(+) ConvCpltCallback : callback for conversion complete process.
(+) ErrorCallback : callback for error detection.
(+) MspInitCallback : callback for Msp Init.
@@ -95,9 +106,9 @@
and a pointer to the user callback function.
[..]
- Use function @ref HAL_TSC_UnRegisterCallback to reset a callback to the default
+ Use function HAL_TSC_UnRegisterCallback to reset a callback to the default
weak function.
- @ref HAL_TSC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ HAL_TSC_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
[..]
This function allows to reset following callbacks:
@@ -107,23 +118,23 @@
(+) MspDeInitCallback : callback for Msp DeInit.
[..]
- By default, after the @ref HAL_TSC_Init() and when the state is @ref HAL_TSC_STATE_RESET
+ By default, after the HAL_TSC_Init() and when the state is HAL_TSC_STATE_RESET
all callbacks are set to the corresponding weak functions:
- examples @ref HAL_TSC_ConvCpltCallback(), @ref HAL_TSC_ErrorCallback().
+ examples HAL_TSC_ConvCpltCallback(), HAL_TSC_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak functions in the @ref HAL_TSC_Init()/ @ref HAL_TSC_DeInit() only when
+ reset to the legacy weak functions in the HAL_TSC_Init()/ HAL_TSC_DeInit() only when
these callbacks are null (not registered beforehand).
- If MspInit or MspDeInit are not null, the @ref HAL_TSC_Init()/ @ref HAL_TSC_DeInit()
+ If MspInit or MspDeInit are not null, the HAL_TSC_Init()/ HAL_TSC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
- Callbacks can be registered/unregistered in @ref HAL_TSC_STATE_READY state only.
+ Callbacks can be registered/unregistered in HAL_TSC_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
- in @ref HAL_TSC_STATE_READY or @ref HAL_TSC_STATE_RESET state,
+ in HAL_TSC_STATE_READY or HAL_TSC_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
Then, the user first registers the MspInit/MspDeInit user callbacks
- using @ref HAL_TSC_RegisterCallback() before calling @ref HAL_TSC_DeInit()
- or @ref HAL_TSC_Init() function.
+ using HAL_TSC_RegisterCallback() before calling HAL_TSC_DeInit()
+ or HAL_TSC_Init() function.
[..]
When the compilation flag USE_HAL_TSC_REGISTER_CALLBACKS is set to 0 or
@@ -181,18 +192,7 @@
| PD2 (AF) | |
+--------------------------------+
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
+
*/
/* Includes ------------------------------------------------------------------*/
@@ -223,8 +223,8 @@
*/
/** @defgroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
@@ -603,8 +603,8 @@
*/
/** @defgroup TSC_Exported_Functions_Group2 Input and Output operation functions
- * @brief Input and Output operation functions
- *
+ * @brief Input and Output operation functions
+ *
@verbatim
===============================================================================
##### IO Operation functions #####
@@ -854,8 +854,8 @@
*/
/** @defgroup TSC_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
- *
+ * @brief Peripheral Control functions
+ *
@verbatim
===============================================================================
##### Peripheral Control functions #####
@@ -943,8 +943,8 @@
*/
/** @defgroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions
- * @brief Peripheral State and Errors functions
- *
+ * @brief Peripheral State and Errors functions
+ *
@verbatim
===============================================================================
##### State and Errors functions #####
@@ -996,8 +996,8 @@
*/
/** @defgroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
+ * @{
+ */
/**
* @brief Handle TSC interrupt request.
@@ -1101,7 +1101,7 @@
for (idx = 0UL; idx < (uint32_t)TSC_NB_OF_GROUPS; idx++)
{
- if ((iomask & (0x0FUL << (idx * 4UL))) != 0UL )
+ if ((iomask & (0x0FUL << (idx * 4UL))) != 0UL)
{
groups |= (1UL << idx);
}
@@ -1124,4 +1124,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_uart.c b/Src/stm32l4xx_hal_uart.c
index 7ccc5f9..844cf7d 100644
--- a/Src/stm32l4xx_hal_uart.c
+++ b/Src/stm32l4xx_hal_uart.c
@@ -10,6 +10,17 @@
* + Peripheral Control functions
*
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
@@ -76,8 +87,8 @@
allows the user to configure dynamically the driver callbacks.
[..]
- Use Function @ref HAL_UART_RegisterCallback() to register a user callback.
- Function @ref HAL_UART_RegisterCallback() allows to register following callbacks:
+ Use Function HAL_UART_RegisterCallback() to register a user callback.
+ Function HAL_UART_RegisterCallback() allows to register following callbacks:
(+) TxHalfCpltCallback : Tx Half Complete Callback.
(+) TxCpltCallback : Tx Complete Callback.
(+) RxHalfCpltCallback : Rx Half Complete Callback.
@@ -97,9 +108,9 @@
and a pointer to the user callback function.
[..]
- Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_UART_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
- @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TxHalfCpltCallback : Tx Half Complete Callback.
@@ -120,16 +131,16 @@
[..]
For specific callback RxEventCallback, use dedicated registration/reset functions:
- respectively @ref HAL_UART_RegisterRxEventCallback() , @ref HAL_UART_UnRegisterRxEventCallback().
+ respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback().
[..]
- By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
+ By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
all callbacks are set to the corresponding weak (surcharged) functions:
- examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback().
+ examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init()
- and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit()
+ reset to the legacy weak (surcharged) functions in the HAL_UART_Init()
+ and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
@@ -138,8 +149,8 @@
in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit()
- or @ref HAL_UART_Init() function.
+ using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit()
+ or HAL_UART_Init() function.
[..]
When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
@@ -149,17 +160,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -182,19 +182,19 @@
* @{
*/
#if defined(USART_CR1_FIFOEN)
-#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
- USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \
- USART_CR1_FIFOEN )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \
+ USART_CR1_OVER8 | USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
#else
-#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
- USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \
+ USART_CR1_OVER8)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
#endif /* USART_CR1_FIFOEN */
#if defined(USART_CR1_FIFOEN)
-#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \
- USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \
+ USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
#else
-#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE |\
+ USART_CR3_ONEBIT)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
#endif /* USART_CR1_FIFOEN */
#define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */
@@ -202,17 +202,11 @@
#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */
#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */
-
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-#if defined(USART_PRESC_PRESCALER)
-const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
-
-#endif /* USART_PRESC_PRESCALER */
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup UART_Private_Functions
* @{
@@ -246,6 +240,18 @@
* @}
*/
+/* Private variables ---------------------------------------------------------*/
+#if defined(USART_PRESC_PRESCALER)
+/** @addtogroup UART_Private_variables
+ * @{
+ */
+const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+/**
+ * @}
+ */
+
+#endif /* USART_PRESC_PRESCALER */
+/* Exported Constants --------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup UART_Exported_Functions UART Exported Functions
@@ -1100,7 +1106,8 @@
(+) HAL_UART_AbortTransmitCpltCallback()
(+) HAL_UART_AbortReceiveCpltCallback()
- (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services:
+ (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced
+ reception services:
(+) HAL_UARTEx_RxEventCallback()
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
@@ -1139,10 +1146,10 @@
* @param Timeout Timeout duration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint8_t *pdata8bits;
- uint16_t *pdata16bits;
+ const uint8_t *pdata8bits;
+ const uint16_t *pdata16bits;
uint32_t tickstart;
/* Check that a Tx process is not already ongoing */
@@ -1168,7 +1175,7 @@
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
pdata8bits = NULL;
- pdata16bits = (uint16_t *) pData;
+ pdata16bits = (const uint16_t *) pData;
}
else
{
@@ -1314,7 +1321,7 @@
* @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
@@ -1351,7 +1358,7 @@
__HAL_UNLOCK(huart);
/* Enable the TX FIFO threshold interrupt */
- SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
}
else
{
@@ -1368,7 +1375,7 @@
__HAL_UNLOCK(huart);
/* Enable the Transmit Data Register Empty interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
}
#else
/* Set the Tx ISR function pointer according to the data word length */
@@ -1384,7 +1391,7 @@
__HAL_UNLOCK(huart);
/* Enable the Transmit Data Register Empty interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
#endif /* USART_CR1_FIFOEN */
return HAL_OK;
@@ -1423,14 +1430,14 @@
if (!(IS_LPUART_INSTANCE(huart->Instance)))
{
/* Check that USART RTOEN bit is set */
- if(READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
{
/* Enable the UART Receiver Timeout Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
}
}
- return(UART_Start_Receive_IT(huart, pData, Size));
+ return (UART_Start_Receive_IT(huart, pData, Size));
}
else
{
@@ -1448,7 +1455,7 @@
* @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
@@ -1502,7 +1509,7 @@
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the UART CR3 register */
- SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
return HAL_OK;
}
@@ -1542,14 +1549,14 @@
if (!(IS_LPUART_INSTANCE(huart->Instance)))
{
/* Check that USART RTOEN bit is set */
- if(READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
{
/* Enable the UART Receiver Timeout Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
}
}
- return(UART_Start_Receive_DMA(huart, pData, Size));
+ return (UART_Start_Receive_DMA(huart, pData, Size));
}
else
{
@@ -1573,17 +1580,17 @@
(gstate == HAL_UART_STATE_BUSY_TX))
{
/* Disable the UART DMA Tx request */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
}
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
(rxstate == HAL_UART_STATE_BUSY_RX))
{
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* Disable the UART DMA Rx request */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
}
__HAL_UNLOCK(huart);
@@ -1603,7 +1610,7 @@
if (huart->gState == HAL_UART_STATE_BUSY_TX)
{
/* Enable the UART DMA Tx request */
- SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
}
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
{
@@ -1611,11 +1618,14 @@
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
/* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ if (huart->Init.Parity != UART_PARITY_NONE)
+ {
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ }
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* Enable the UART DMA Rx request */
- SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
}
__HAL_UNLOCK(huart);
@@ -1644,7 +1654,7 @@
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
(gstate == HAL_UART_STATE_BUSY_TX))
{
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel */
if (huart->hdmatx != NULL)
@@ -1668,7 +1678,7 @@
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
(rxstate == HAL_UART_STATE_BUSY_RX))
{
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel */
if (huart->hdmarx != NULL)
@@ -1707,25 +1717,26 @@
{
#if defined(USART_CR1_FIFOEN)
/* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
- USART_CR1_TCIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
+ USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
#else
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
#endif /* USART_CR1_FIFOEN */
/* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
}
- /* Disable the UART DMA Tx request if enabled */
+ /* Abort the UART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ /* Disable the UART DMA Tx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
if (huart->hdmatx != NULL)
@@ -1747,10 +1758,11 @@
}
}
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ /* Disable the UART DMA Rx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
if (huart->hdmarx != NULL)
@@ -1816,17 +1828,18 @@
{
#if defined(USART_CR1_FIFOEN)
/* Disable TCIE, TXEIE and TXFTIE interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
#else
/* Disable TXEIE and TCIE interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
#endif /* USART_CR1_FIFOEN */
- /* Disable the UART DMA Tx request if enabled */
+ /* Abort the UART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ /* Disable the UART DMA Tx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
if (huart->hdmatx != NULL)
@@ -1881,24 +1894,25 @@
{
#if defined(USART_CR1_FIFOEN)
/* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
#else
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
#endif /* USART_CR1_FIFOEN */
/* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
}
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ /* Disable the UART DMA Rx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
if (huart->hdmarx != NULL)
@@ -1956,18 +1970,18 @@
/* Disable interrupts */
#if defined(USART_CR1_FIFOEN)
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE |
- USART_CR1_TXEIE_TXFNFIE));
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE |
+ USART_CR1_TXEIE_TXFNFIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
#else
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
#endif /* USART_CR1_FIFOEN */
/* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
}
/* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
@@ -2001,11 +2015,11 @@
}
}
- /* Disable the UART DMA Tx request if enabled */
+ /* Abort the UART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at UART level */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
if (huart->hdmatx != NULL)
@@ -2025,10 +2039,11 @@
}
}
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ /* Disable the UART DMA Rx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
if (huart->hdmarx != NULL)
@@ -2113,16 +2128,17 @@
{
/* Disable interrupts */
#if defined(USART_CR1_FIFOEN)
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
#else
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
#endif /* USART_CR1_FIFOEN */
- /* Disable the UART DMA Tx request if enabled */
+ /* Abort the UART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ /* Disable the UART DMA Tx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
if (huart->hdmatx != NULL)
@@ -2209,23 +2225,24 @@
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
#if defined(USART_CR1_FIFOEN)
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
#else
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
#endif /* USART_CR1_FIFOEN */
/* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
}
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ /* Disable the UART DMA Rx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
if (huart->hdmarx != NULL)
@@ -2425,10 +2442,11 @@
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
UART_EndRxTransfer(huart);
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ /* Disable the UART DMA Rx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel */
if (huart->hdmarx != NULL)
@@ -2489,9 +2507,9 @@
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
- if ( (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
- &&((isrflags & USART_ISR_IDLE) != 0U)
- &&((cr1its & USART_ISR_IDLE) != 0U))
+ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ && ((isrflags & USART_ISR_IDLE) != 0U)
+ && ((cr1its & USART_ISR_IDLE) != 0U))
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
@@ -2503,8 +2521,8 @@
(DMA cplt callback will be called).
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
- if ( (nb_remaining_rx_data > 0U)
- &&(nb_remaining_rx_data < huart->RxXferSize))
+ if ((nb_remaining_rx_data > 0U)
+ && (nb_remaining_rx_data < huart->RxXferSize))
{
/* Reception is not complete */
huart->RxXferCount = nb_remaining_rx_data;
@@ -2513,18 +2531,18 @@
if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
{
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
in the UART CR3 register */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
/* Last bytes received, so no need as the abort is immediate */
(void)HAL_DMA_Abort(huart->hdmarx);
@@ -2535,7 +2553,7 @@
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
-#endif
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
return;
}
@@ -2545,21 +2563,21 @@
/* Check received length : If all expected data are received, do nothing.
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
- if ( (huart->RxXferCount > 0U)
- &&(nb_rx_data > 0U) )
+ if ((huart->RxXferCount > 0U)
+ && (nb_rx_data > 0U))
{
#if defined(USART_CR1_FIFOEN)
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
#else
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
#endif
/* Rx process is completed, restore huart->RxState to Ready */
@@ -2569,14 +2587,14 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxEventCallback(huart, nb_rx_data);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
-#endif
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
return;
}
@@ -2926,7 +2944,7 @@
huart->gState = HAL_UART_STATE_BUSY;
/* Enable USART mute mode by setting the MME bit in the CR1 register */
- SET_BIT(huart->Instance->CR1, USART_CR1_MME);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME);
huart->gState = HAL_UART_STATE_READY;
@@ -2946,7 +2964,7 @@
huart->gState = HAL_UART_STATE_BUSY;
/* Disable USART mute mode by clearing the MME bit in the CR1 register */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
huart->gState = HAL_UART_STATE_READY;
@@ -2975,10 +2993,10 @@
huart->gState = HAL_UART_STATE_BUSY;
/* Clear TE and RE bits */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
/* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
- SET_BIT(huart->Instance->CR1, USART_CR1_TE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE);
huart->gState = HAL_UART_STATE_READY;
@@ -2998,10 +3016,10 @@
huart->gState = HAL_UART_STATE_BUSY;
/* Clear TE and RE bits */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
/* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
- SET_BIT(huart->Instance->CR1, USART_CR1_RE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE);
huart->gState = HAL_UART_STATE_READY;
@@ -3302,9 +3320,9 @@
if (pclk != 0U)
{
#if defined(USART_PRESC_PRESCALER)
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
#else
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
+ usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
#endif /* USART_PRESC_PRESCALER */
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
{
@@ -3347,13 +3365,13 @@
{
/* USARTDIV must be greater than or equal to 0d16 */
#if defined(USART_PRESC_PRESCALER)
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
#else
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
+ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
#endif /* USART_PRESC_PRESCALER */
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
{
- huart->Instance->BRR = usartdiv;
+ huart->Instance->BRR = (uint16_t)usartdiv;
}
else
{
@@ -3497,10 +3515,11 @@
}
/**
- * @brief Handle UART Communication Timeout.
+ * @brief This function handles UART Communication Timeout. It waits
+ * until a flag is no longer in the specified status.
* @param huart UART handle.
* @param Flag Specifies the UART flag to check
- * @param Status Flag status (SET or RESET)
+ * @param Status The actual Flag status (SET or RESET)
* @param Tickstart Tick start value
* @param Timeout Timeout duration
* @retval HAL status
@@ -3519,11 +3538,12 @@
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
#if defined(USART_CR1_FIFOEN)
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
+ USART_CR1_TXEIE_TXFNFIE));
#else
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
#endif /* USART_CR1_FIFOEN */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
@@ -3543,11 +3563,12 @@
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
#if defined(USART_CR1_FIFOEN)
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
+ USART_CR1_TXEIE_TXFNFIE));
#else
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
#endif
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
@@ -3589,7 +3610,7 @@
huart->RxState = HAL_UART_STATE_BUSY_RX;
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
#if defined(USART_CR1_FIFOEN)
/* Configure Rx interrupt processing */
@@ -3608,8 +3629,11 @@
__HAL_UNLOCK(huart);
/* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+ if (huart->Init.Parity != UART_PARITY_NONE)
+ {
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ }
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
}
else
{
@@ -3626,7 +3650,14 @@
__HAL_UNLOCK(huart);
/* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ if (huart->Init.Parity != UART_PARITY_NONE)
+ {
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ }
+ else
+ {
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ }
}
#else
/* Set the Rx ISR function pointer according to the data word length */
@@ -3642,7 +3673,14 @@
__HAL_UNLOCK(huart);
/* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
+ if (huart->Init.Parity != UART_PARITY_NONE)
+ {
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
+ }
+ else
+ {
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE);
+ }
#endif /* USART_CR1_FIFOEN */
return HAL_OK;
}
@@ -3688,8 +3726,8 @@
__HAL_UNLOCK(huart);
- /* Restore huart->gState to ready */
- huart->gState = HAL_UART_STATE_READY;
+ /* Restore huart->RxState to ready */
+ huart->RxState = HAL_UART_STATE_READY;
return HAL_ERROR;
}
@@ -3697,14 +3735,17 @@
__HAL_UNLOCK(huart);
/* Enable the UART Parity Error Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ if (huart->Init.Parity != UART_PARITY_NONE)
+ {
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ }
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* Enable the DMA transfer for the receiver request by setting the DMAR bit
in the UART CR3 register */
- SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
return HAL_OK;
}
@@ -3719,11 +3760,11 @@
{
#if defined(USART_CR1_FIFOEN)
/* Disable TXEIE, TCIE, TXFT interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
#else
/* Disable TXEIE and TCIE interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
#endif /* USART_CR1_FIFOEN */
/* At end of Tx process, restore huart->gState to Ready */
@@ -3740,17 +3781,17 @@
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
#if defined(USART_CR1_FIFOEN)
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
#else
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
#endif /* USART_CR1_FIFOEN */
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
}
/* At end of Rx process, restore huart->RxState to Ready */
@@ -3778,10 +3819,10 @@
/* Disable the DMA transfer for transmit request by resetting the DMAT bit
in the UART CR3 register */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Enable the UART Transmit Complete Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
}
/* DMA Circular mode */
else
@@ -3829,12 +3870,12 @@
huart->RxXferCount = 0U;
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
in the UART CR3 register */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
@@ -3842,7 +3883,7 @@
/* If Reception till IDLE event has been selected, Disable IDLE Interrupt */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
}
}
@@ -3886,10 +3927,10 @@
{
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
- huart->RxEventCallback(huart, huart->RxXferSize/2U);
+ huart->RxEventCallback(huart, huart->RxXferSize / 2U);
#else
/*Call legacy weak Rx Event callback*/
- HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize/2U);
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
else
@@ -4159,13 +4200,13 @@
{
/* Disable the UART Transmit Data Register Empty Interrupt */
#if defined(USART_CR1_FIFOEN)
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
#else
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
#endif /* USART_CR1_FIFOEN */
/* Enable the UART Transmit Complete Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
}
else
{
@@ -4185,7 +4226,7 @@
*/
static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
{
- uint16_t *tmp;
+ const uint16_t *tmp;
/* Check that a Tx process is ongoing */
if (huart->gState == HAL_UART_STATE_BUSY_TX)
@@ -4194,17 +4235,17 @@
{
/* Disable the UART Transmit Data Register Empty Interrupt */
#if defined(USART_CR1_FIFOEN)
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
#else
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
#endif /* USART_CR1_FIFOEN */
/* Enable the UART Transmit Complete Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
}
else
{
- tmp = (uint16_t *) huart->pTxBuffPtr;
+ tmp = (const uint16_t *) huart->pTxBuffPtr;
huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
huart->pTxBuffPtr += 2U;
huart->TxXferCount--;
@@ -4232,10 +4273,10 @@
if (huart->TxXferCount == 0U)
{
/* Disable the TX FIFO threshold interrupt */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
/* Enable the UART Transmit Complete Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
break; /* force exit loop */
}
@@ -4262,7 +4303,7 @@
*/
static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
{
- uint16_t *tmp;
+ const uint16_t *tmp;
uint16_t nb_tx_data;
/* Check that a Tx process is ongoing */
@@ -4273,16 +4314,16 @@
if (huart->TxXferCount == 0U)
{
/* Disable the TX FIFO threshold interrupt */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
/* Enable the UART Transmit Complete Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
break; /* force exit loop */
}
else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
{
- tmp = (uint16_t *) huart->pTxBuffPtr;
+ tmp = (const uint16_t *) huart->pTxBuffPtr;
huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
huart->pTxBuffPtr += 2U;
huart->TxXferCount--;
@@ -4305,7 +4346,7 @@
static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
{
/* Disable the UART Transmit Complete Interrupt */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
/* Tx process is ended, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
@@ -4344,13 +4385,13 @@
{
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
#if defined(USART_CR1_FIFOEN)
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
#else
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
#endif /* USART_CR1_FIFOEN */
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
@@ -4362,16 +4403,24 @@
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
- /* Disable IDLE interrupt */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ /* Set reception type to Standard */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ /* Disable IDLE interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+ {
+ /* Clear IDLE Flag */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ }
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
-#endif
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
else
{
@@ -4384,7 +4433,6 @@
HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
- huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
}
}
else
@@ -4420,13 +4468,13 @@
{
/* Disable the UART Parity Error Interrupt and RXNE interrupt*/
#if defined(USART_CR1_FIFOEN)
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
#else
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
#endif /* USART_CR1_FIFOEN */
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
@@ -4438,16 +4486,24 @@
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
- /* Disable IDLE interrupt */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ /* Set reception type to Standard */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ /* Disable IDLE interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+ {
+ /* Clear IDLE Flag */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ }
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
-#endif
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
else
{
@@ -4460,7 +4516,6 @@
HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
- huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
}
}
else
@@ -4546,11 +4601,11 @@
if (huart->RxXferCount == 0U)
{
/* Disable the UART Parity Error Interrupt and RXFT interrupt*/
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
and RX FIFO Threshold interrupt */
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
@@ -4562,16 +4617,24 @@
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
- /* Disable IDLE interrupt */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ /* Set reception type to Standard */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ /* Disable IDLE interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+ {
+ /* Clear IDLE Flag */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ }
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
-#endif
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
else
{
@@ -4584,7 +4647,6 @@
HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
- huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
}
}
@@ -4596,13 +4658,13 @@
if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
{
/* Disable the UART RXFT interrupt*/
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
/* Update the RxISR function pointer */
huart->RxISR = UART_RxISR_8BIT;
/* Enable the UART Data Register Not Empty interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
}
}
else
@@ -4689,11 +4751,11 @@
if (huart->RxXferCount == 0U)
{
/* Disable the UART Parity Error Interrupt and RXFT interrupt*/
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
and RX FIFO Threshold interrupt */
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
@@ -4705,16 +4767,24 @@
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
- /* Disable IDLE interrupt */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ /* Set reception type to Standard */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ /* Disable IDLE interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+ {
+ /* Clear IDLE Flag */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ }
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
-#endif
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
else
{
@@ -4727,7 +4797,6 @@
HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
- huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
}
}
@@ -4739,13 +4808,13 @@
if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
{
/* Disable the UART RXFT interrupt*/
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
/* Update the RxISR function pointer */
huart->RxISR = UART_RxISR_16BIT;
/* Enable the UART Data Register Not Empty interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
}
}
else
@@ -4769,4 +4838,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_uart_ex.c b/Src/stm32l4xx_hal_uart_ex.c
index b375d29..a2b94b0 100644
--- a/Src/stm32l4xx_hal_uart_ex.c
+++ b/Src/stm32l4xx_hal_uart_ex.c
@@ -9,6 +9,17 @@
* + Peripheral Control functions
*
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### UART peripheral extended features #####
@@ -27,17 +38,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -395,7 +395,7 @@
__HAL_LOCK(huart);
/* Set UCESM bit */
- SET_BIT(huart->Instance->CR3, USART_CR3_UCESM);
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_UCESM);
/* Process Unlocked */
__HAL_UNLOCK(huart);
@@ -414,7 +414,7 @@
__HAL_LOCK(huart);
/* Clear UCESM bit */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_UCESM);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_UCESM);
/* Process Unlocked */
__HAL_UNLOCK(huart);
@@ -535,7 +535,7 @@
__HAL_LOCK(huart);
/* Set UESM bit */
- SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
/* Process Unlocked */
__HAL_UNLOCK(huart);
@@ -554,7 +554,7 @@
__HAL_LOCK(huart);
/* Clear UESM bit */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
/* Process Unlocked */
__HAL_UNLOCK(huart);
@@ -742,13 +742,14 @@
#endif /* USART_CR1_FIFOEN */
/**
- * @brief Receive an amount of data in blocking mode till either the expected number of data is received or an IDLE event occurs.
- * @note HAL_OK is returned if reception is completed (expected number of data has been received)
- * or if reception is stopped after IDLE event (less than the expected number of data has been received)
- * In this case, RxLen output parameter indicates number of data available in reception buffer.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
- * the received data is handled as a set of uint16_t. In this case, Size must indicate the number
- * of uint16_t available through pData.
+ * @brief Receive an amount of data in blocking mode till either the expected number of data
+ * is received or an IDLE event occurs.
+ * @note HAL_OK is returned if reception is completed (expected number of data has been received)
+ * or if reception is stopped after IDLE event (less than the expected number of data has been received)
+ * In this case, RxLen output parameter indicates number of data available in reception buffer.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+ * of uint16_t available through pData.
* @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
* is not empty. Read operations from the RDR register are performed when
* RXFNE flag is set. From hardware perspective, RXFNE flag and
@@ -756,11 +757,13 @@
* @param huart UART handle.
* @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
* @param Size Amount of data elements (uint8_t or uint16_t) to be received.
- * @param RxLen Number of data elements finally received (could be lower than Size, in case reception ends on IDLE event)
+ * @param RxLen Number of data elements finally received
+ * (could be lower than Size, in case reception ends on IDLE event)
* @param Timeout Timeout duration expressed in ms (covers the whole reception sequence).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout)
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
+ uint32_t Timeout)
{
uint8_t *pdata8bits;
uint16_t *pdata16bits;
@@ -871,13 +874,14 @@
}
/**
- * @brief Receive an amount of data in interrupt mode till either the expected number of data is received or an IDLE event occurs.
- * @note Reception is initiated by this function call. Further progress of reception is achieved thanks
- * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating
- * number of received data elements.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
- * the received data is handled as a set of uint16_t. In this case, Size must indicate the number
- * of uint16_t available through pData.
+ * @brief Receive an amount of data in interrupt mode till either the expected number of data
+ * is received or an IDLE event occurs.
+ * @note Reception is initiated by this function call. Further progress of reception is achieved thanks
+ * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating
+ * number of received data elements.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+ * of uint16_t available through pData.
* @param huart UART handle.
* @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
* @param Size Amount of data elements (uint8_t or uint16_t) to be received.
@@ -908,7 +912,7 @@
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
- SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
}
else
{
@@ -929,16 +933,17 @@
}
/**
- * @brief Receive an amount of data in DMA mode till either the expected number of data is received or an IDLE event occurs.
- * @note Reception is initiated by this function call. Further progress of reception is achieved thanks
- * to DMA services, transferring automatically received data elements in user reception buffer and
- * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider
- * reception phase as ended. In all cases, callback execution will indicate number of received data elements.
- * @note When the UART parity is enabled (PCE = 1), the received data contain
- * the parity bit (MSB position).
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
- * the received data is handled as a set of uint16_t. In this case, Size must indicate the number
- * of uint16_t available through pData.
+ * @brief Receive an amount of data in DMA mode till either the expected number
+ * of data is received or an IDLE event occurs.
+ * @note Reception is initiated by this function call. Further progress of reception is achieved thanks
+ * to DMA services, transferring automatically received data elements in user reception buffer and
+ * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider
+ * reception phase as ended. In all cases, callback execution will indicate number of received data elements.
+ * @note When the UART parity is enabled (PCE = 1), the received data contain
+ * the parity bit (MSB position).
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+ * of uint16_t available through pData.
* @param huart UART handle.
* @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
* @param Size Amount of data elements (uint8_t or uint16_t) to be received.
@@ -969,7 +974,7 @@
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
- SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
}
else
{
@@ -1067,4 +1072,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_usart.c b/Src/stm32l4xx_hal_usart.c
index 0600e3b..9e522e8 100644
--- a/Src/stm32l4xx_hal_usart.c
+++ b/Src/stm32l4xx_hal_usart.c
@@ -11,6 +11,17 @@
* + Peripheral Control functions
* + Peripheral State and Error functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
@@ -62,8 +73,8 @@
allows the user to configure dynamically the driver callbacks.
[..]
- Use Function @ref HAL_USART_RegisterCallback() to register a user callback.
- Function @ref HAL_USART_RegisterCallback() allows to register following callbacks:
+ Use Function HAL_USART_RegisterCallback() to register a user callback.
+ Function HAL_USART_RegisterCallback() allows to register following callbacks:
(+) TxHalfCpltCallback : Tx Half Complete Callback.
(+) TxCpltCallback : Tx Complete Callback.
(+) RxHalfCpltCallback : Rx Half Complete Callback.
@@ -79,9 +90,9 @@
and a pointer to the user callback function.
[..]
- Use function @ref HAL_USART_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_USART_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
- @ref HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TxHalfCpltCallback : Tx Half Complete Callback.
@@ -97,13 +108,13 @@
(+) MspDeInitCallback : USART MspDeInit.
[..]
- By default, after the @ref HAL_USART_Init() and when the state is HAL_USART_STATE_RESET
+ By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_RESET
all callbacks are set to the corresponding weak (surcharged) functions:
- examples @ref HAL_USART_TxCpltCallback(), @ref HAL_USART_RxHalfCpltCallback().
+ examples HAL_USART_TxCpltCallback(), HAL_USART_RxHalfCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_USART_Init()
- and @ref HAL_USART_DeInit() only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_USART_Init() and @ref HAL_USART_DeInit()
+ reset to the legacy weak (surcharged) functions in the HAL_USART_Init()
+ and HAL_USART_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_USART_Init() and HAL_USART_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
@@ -112,8 +123,8 @@
in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user)
MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_USART_RegisterCallback() before calling @ref HAL_USART_DeInit()
- or @ref HAL_USART_Init() function.
+ using HAL_USART_RegisterCallback() before calling HAL_USART_DeInit()
+ or HAL_USART_Init() function.
[..]
When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or
@@ -123,17 +134,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -329,7 +329,8 @@
/* In Synchronous mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register
- - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
+ - HDSEL, SCEN and IREN bits in the USART_CR3 register.
+ */
husart->Instance->CR2 &= ~USART_CR2_LINEN;
husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
@@ -762,10 +763,10 @@
* @param Timeout Timeout duration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
{
- uint8_t *ptxdata8bits;
- uint16_t *ptxdata16bits;
+ const uint8_t *ptxdata8bits;
+ const uint16_t *ptxdata16bits;
uint32_t tickstart;
if (husart->State == HAL_USART_STATE_READY)
@@ -791,7 +792,7 @@
if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
ptxdata8bits = NULL;
- ptxdata16bits = (uint16_t *) pTxData;
+ ptxdata16bits = (const uint16_t *) pTxData;
}
else
{
@@ -975,13 +976,13 @@
* @param Timeout Timeout duration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size, uint32_t Timeout)
{
uint8_t *prxdata8bits;
uint16_t *prxdata16bits;
- uint8_t *ptxdata8bits;
- uint16_t *ptxdata16bits;
+ const uint8_t *ptxdata8bits;
+ const uint16_t *ptxdata16bits;
uint16_t uhMask;
uint16_t rxdatacount;
uint32_t tickstart;
@@ -1016,7 +1017,7 @@
{
prxdata8bits = NULL;
ptxdata8bits = NULL;
- ptxdata16bits = (uint16_t *) pTxData;
+ ptxdata16bits = (const uint16_t *) pTxData;
prxdata16bits = (uint16_t *) pRxData;
}
else
@@ -1126,7 +1127,7 @@
* @param Size amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size)
{
if (husart->State == HAL_USART_STATE_READY)
{
@@ -1258,7 +1259,10 @@
__HAL_UNLOCK(husart);
/* Enable the USART Parity Error interrupt and RX FIFO Threshold interrupt */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ if (husart->Init.Parity != USART_PARITY_NONE)
+ {
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ }
SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);
}
else
@@ -1279,9 +1283,23 @@
/* Enable the USART Parity Error and Data Register not empty Interrupts */
#if defined(USART_CR1_FIFOEN)
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ if (husart->Init.Parity != USART_PARITY_NONE)
+ {
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ }
+ else
+ {
+ SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ }
#else
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
+ if (husart->Init.Parity != USART_PARITY_NONE)
+ {
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
+ }
+ else
+ {
+ SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
+ }
#endif /* USART_CR1_FIFOEN */
}
@@ -1327,7 +1345,7 @@
* @param Size amount of data elements (u8 or u16) to be sent (same amount to be received).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size)
{
@@ -1376,8 +1394,11 @@
/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
- /* Enable the USART Parity Error interrupt */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ if (husart->Init.Parity != USART_PARITY_NONE)
+ {
+ /* Enable the USART Parity Error interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ }
/* Enable the TX and RX FIFO Threshold interrupts */
SET_BIT(husart->Instance->CR3, (USART_CR3_TXFTIE | USART_CR3_RXFTIE));
@@ -1404,9 +1425,23 @@
/* Enable the USART Parity Error and USART Data Register not empty Interrupts */
#if defined(USART_CR1_FIFOEN)
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ if (husart->Init.Parity != USART_PARITY_NONE)
+ {
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ }
+ else
+ {
+ SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ }
#else
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
+ if (husart->Init.Parity != USART_PARITY_NONE)
+ {
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
+ }
+ else
+ {
+ SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
+ }
#endif /* USART_CR1_FIFOEN */
/* Enable the USART Transmit Data Register Empty Interrupt */
@@ -1435,10 +1470,10 @@
* @param Size amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size)
{
HAL_StatusTypeDef status = HAL_OK;
- uint32_t *tmp;
+ const uint32_t *tmp;
if (husart->State == HAL_USART_STATE_READY)
{
@@ -1469,8 +1504,8 @@
husart->hdmatx->XferErrorCallback = USART_DMAError;
/* Enable the USART transmit DMA channel */
- tmp = (uint32_t *)&pTxData;
- status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
+ tmp = (const uint32_t *)&pTxData;
+ status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
}
if (status == HAL_OK)
@@ -1583,8 +1618,11 @@
/* Process Unlocked */
__HAL_UNLOCK(husart);
- /* Enable the USART Parity Error Interrupt */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ if (husart->Init.Parity != USART_PARITY_NONE)
+ {
+ /* Enable the USART Parity Error Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ }
/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
@@ -1639,11 +1677,11 @@
* @param Size amount of data elements (u8 or u16) to be received/sent.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size)
{
HAL_StatusTypeDef status;
- uint32_t *tmp;
+ const uint32_t *tmp;
if (husart->State == HAL_USART_STATE_READY)
{
@@ -1685,13 +1723,13 @@
/* Enable the USART receive DMA channel */
tmp = (uint32_t *)&pRxData;
- status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size);
+ status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(const uint32_t *)tmp, Size);
/* Enable the USART transmit DMA channel */
if (status == HAL_OK)
{
- tmp = (uint32_t *)&pTxData;
- status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
+ tmp = (const uint32_t *)&pTxData;
+ status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
}
}
else
@@ -1704,8 +1742,11 @@
/* Process Unlocked */
__HAL_UNLOCK(husart);
- /* Enable the USART Parity Error Interrupt */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ if (husart->Init.Parity != USART_PARITY_NONE)
+ {
+ /* Enable the USART Parity Error Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ }
/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
@@ -1822,7 +1863,10 @@
__HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
/* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ if (husart->Init.Parity != USART_PARITY_NONE)
+ {
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ }
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
/* Enable the USART DMA Rx request before the DMA Tx request */
@@ -1919,9 +1963,10 @@
CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
#endif /* USART_CR1_FIFOEN */
- /* Disable the USART DMA Tx request if enabled */
+ /* Abort the USART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
{
+ /* Disable the USART DMA Tx request if enabled */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
/* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
@@ -1944,9 +1989,10 @@
}
}
- /* Disable the USART DMA Rx request if enabled */
+ /* Abort the USART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the USART DMA Rx request if enabled */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
@@ -2055,7 +2101,7 @@
}
}
- /* Disable the USART DMA Tx request if enabled */
+ /* Abort the USART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at USART level */
@@ -2079,9 +2125,10 @@
}
}
- /* Disable the USART DMA Rx request if enabled */
+ /* Abort the USART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the USART DMA Rx request if enabled */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
@@ -2159,9 +2206,10 @@
/* If no error occurs */
#if defined(USART_CR2_SLVEN)
- errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_UDR));
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF |
+ USART_ISR_UDR));
#else
- errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
#endif /* USART_CR2_SLVEN */
if (errorflags == 0U)
{
@@ -2234,6 +2282,14 @@
husart->ErrorCode |= HAL_USART_ERROR_ORE;
}
+ /* USART Receiver Timeout interrupt occurred ---------------------------------*/
+ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_RTOF);
+
+ husart->ErrorCode |= HAL_USART_ERROR_RTO;
+ }
+
#if defined(USART_CR2_SLVEN)
/* USART SPI slave underrun error interrupt occurred -------------------------*/
if (((isrflags & USART_ISR_UDR) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
@@ -2282,9 +2338,10 @@
Disable Interrupts, and disable DMA requests, if ongoing */
USART_EndTransfer(husart);
- /* Disable the USART DMA Rx request if enabled */
+ /* Abort the USART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the USART DMA Rx request if enabled */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR);
/* Abort the USART DMA Tx channel */
@@ -2906,10 +2963,11 @@
/**
- * @brief Handle USART Communication Timeout.
+ * @brief Handle USART Communication Timeout. It waits
+ * until a flag is no longer in the specified status.
* @param husart USART handle.
* @param Flag Specifies the USART flag to check.
- * @param Status the Flag status (SET or RESET).
+ * @param Status the actual Flag status (SET or RESET).
* @param Tickstart Tick start value
* @param Timeout timeout duration.
* @retval HAL status
@@ -3160,7 +3218,7 @@
static void USART_TxISR_16BIT(USART_HandleTypeDef *husart)
{
const HAL_USART_StateTypeDef state = husart->State;
- uint16_t *tmp;
+ const uint16_t *tmp;
if ((state == HAL_USART_STATE_BUSY_TX) ||
(state == HAL_USART_STATE_BUSY_TX_RX))
@@ -3175,7 +3233,7 @@
}
else
{
- tmp = (uint16_t *) husart->pTxBuffPtr;
+ tmp = (const uint16_t *) husart->pTxBuffPtr;
husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
husart->pTxBuffPtr += 2U;
husart->TxXferCount--;
@@ -3242,7 +3300,7 @@
static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart)
{
const HAL_USART_StateTypeDef state = husart->State;
- uint16_t *tmp;
+ const uint16_t *tmp;
uint16_t nb_tx_data;
/* Check that a Tx process is ongoing */
@@ -3263,7 +3321,7 @@
}
else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET)
{
- tmp = (uint16_t *) husart->pTxBuffPtr;
+ tmp = (const uint16_t *) husart->pTxBuffPtr;
husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
husart->pTxBuffPtr += 2U;
husart->TxXferCount--;
@@ -3862,4 +3920,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_usart_ex.c b/Src/stm32l4xx_hal_usart_ex.c
index ed49a77..647c80e 100644
--- a/Src/stm32l4xx_hal_usart_ex.c
+++ b/Src/stm32l4xx_hal_usart_ex.c
@@ -8,6 +8,17 @@
* + Peripheral Control functions
*
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### USART peripheral extended features #####
@@ -26,17 +37,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -58,10 +58,10 @@
/** @defgroup USARTEx_Private_Constants USARTEx Private Constants
* @{
*/
-/* UART RX FIFO depth */
+/* USART RX FIFO depth */
#define RX_FIFO_DEPTH 8U
-/* UART TX FIFO depth */
+/* USART TX FIFO depth */
#define TX_FIFO_DEPTH 8U
/**
* @}
@@ -485,8 +485,8 @@
return HAL_OK;
}
-#endif /* USART_CR1_FIFOEN */
+#endif /* USART_CR1_FIFOEN */
/**
* @}
*/
@@ -526,10 +526,14 @@
{
rx_fifo_depth = RX_FIFO_DEPTH;
tx_fifo_depth = TX_FIFO_DEPTH;
- rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU);
- tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU);
- husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];
- husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];
+ rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3,
+ USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU);
+ tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3,
+ USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU);
+ husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+ (uint16_t)denominator[tx_fifo_threshold];
+ husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
+ (uint16_t)denominator[rx_fifo_threshold];
}
}
#endif /* USART_CR1_FIFOEN */
@@ -547,4 +551,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_hal_wwdg.c b/Src/stm32l4xx_hal_wwdg.c
index 1d61948..c15d4de 100644
--- a/Src/stm32l4xx_hal_wwdg.c
+++ b/Src/stm32l4xx_hal_wwdg.c
@@ -7,6 +7,17 @@
* functionalities of the Window Watchdog (WWDG) peripheral:
* + Initialization and Configuration functions
* + IO operation functions
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### WWDG Specific features #####
@@ -39,11 +50,11 @@
(++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
(++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
(+) Typical values:
- (++) Counter min (T[5;0] = 0x00) at 80MHz (PCLK1) with zero prescaler:
- max timeout before reset: approximately 51.2us
- (++) Counter max (T[5;0] = 0x3F) at 80MHz (PCLK1) with prescaler
+ (++) Counter min (T[5;0] = 0x00) at 56MHz (PCLK1) with zero prescaler:
+ max timeout before reset: approximately 73.14us
+ (++) Counter max (T[5;0] = 0x3F) at 56MHz (PCLK1) with prescaler
dividing by 8:
- max timeout before reset: approximately 26.21ms
+ max timeout before reset: approximately 599.18ms
##### How to use this driver #####
==============================================================================
@@ -55,7 +66,7 @@
(+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
(+) Configure the WWDG prescaler, refresh window value, counter value and early
interrupt status using HAL_WWDG_Init() function. This will automatically
- enable WWDG and start its downcounter. Time reference can be taken from
+ enable WWDG and start its downcounter. Time reference can be taken from
function exit. Care must be taken to provide a counter value
greater than 0x40 to prevent generation of immediate reset.
(+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is
@@ -112,17 +123,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -418,5 +418,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_ll_adc.c b/Src/stm32l4xx_ll_adc.c
index f82eeb3..693f613 100644
--- a/Src/stm32l4xx_ll_adc.c
+++ b/Src/stm32l4xx_ll_adc.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -312,6 +311,9 @@
/* Check the parameters */
assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+ /* Prevent unused argument compilation warning */
+ (void)(ADCxy_COMMON);
+
/* Force reset of ADC clock (core clock) */
LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC);
@@ -1058,5 +1060,3 @@
*/
#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_ll_comp.c b/Src/stm32l4xx_ll_comp.c
index bada110..33a574c 100644
--- a/Src/stm32l4xx_ll_comp.c
+++ b/Src/stm32l4xx_ll_comp.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -25,7 +24,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32L4xx_LL_Driver
* @{
@@ -337,5 +336,3 @@
*/
#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_ll_crc.c b/Src/stm32l4xx_ll_crc.c
index cc55e02..fbb3807 100644
--- a/Src/stm32l4xx_ll_crc.c
+++ b/Src/stm32l4xx_ll_crc.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -26,7 +25,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32L4xx_LL_Driver
* @{
@@ -102,6 +101,3 @@
*/
#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Src/stm32l4xx_ll_crs.c b/Src/stm32l4xx_ll_crs.c
index 557ec9a..d547dde 100644
--- a/Src/stm32l4xx_ll_crs.c
+++ b/Src/stm32l4xx_ll_crs.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -82,5 +81,3 @@
*/
#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_ll_dac.c b/Src/stm32l4xx_ll_dac.c
index c0d5a15..3fb52fe 100644
--- a/Src/stm32l4xx_ll_dac.c
+++ b/Src/stm32l4xx_ll_dac.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -319,4 +318,3 @@
#endif /* USE_FULL_LL_DRIVER */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_ll_dma.c b/Src/stm32l4xx_ll_dma.c
index 2d80835..5d18638 100644
--- a/Src/stm32l4xx_ll_dma.c
+++ b/Src/stm32l4xx_ll_dma.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -399,5 +398,3 @@
*/
#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_ll_dma2d.c b/Src/stm32l4xx_ll_dma2d.c
index d7aebdd..3790c24 100644
--- a/Src/stm32l4xx_ll_dma2d.c
+++ b/Src/stm32l4xx_ll_dma2d.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -25,7 +24,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32L4xx_LL_Driver
* @{
@@ -182,9 +181,12 @@
ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct)
{
ErrorStatus status = ERROR;
- LL_DMA2D_ColorTypeDef DMA2D_ColorStruct;
- uint32_t tmp, tmp1, tmp2;
- uint32_t regMask, regValue;
+ LL_DMA2D_ColorTypeDef dma2d_colorstruct;
+ uint32_t tmp;
+ uint32_t tmp1;
+ uint32_t tmp2;
+ uint32_t regMask;
+ uint32_t regValue;
/* Check the parameters */
assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
@@ -245,12 +247,12 @@
LL_DMA2D_SetOutputMemAddr(DMA2Dx, DMA2D_InitStruct->OutputMemoryAddress);
/* DMA2D OCOLR register configuration ------------------------------------------*/
- DMA2D_ColorStruct.ColorMode = DMA2D_InitStruct->ColorMode;
- DMA2D_ColorStruct.OutputBlue = DMA2D_InitStruct->OutputBlue;
- DMA2D_ColorStruct.OutputGreen = DMA2D_InitStruct->OutputGreen;
- DMA2D_ColorStruct.OutputRed = DMA2D_InitStruct->OutputRed;
- DMA2D_ColorStruct.OutputAlpha = DMA2D_InitStruct->OutputAlpha;
- LL_DMA2D_ConfigOutputColor(DMA2Dx, &DMA2D_ColorStruct);
+ dma2d_colorstruct.ColorMode = DMA2D_InitStruct->ColorMode;
+ dma2d_colorstruct.OutputBlue = DMA2D_InitStruct->OutputBlue;
+ dma2d_colorstruct.OutputGreen = DMA2D_InitStruct->OutputGreen;
+ dma2d_colorstruct.OutputRed = DMA2D_InitStruct->OutputRed;
+ dma2d_colorstruct.OutputAlpha = DMA2D_InitStruct->OutputAlpha;
+ LL_DMA2D_ConfigOutputColor(DMA2Dx, &dma2d_colorstruct);
status = SUCCESS;
}
@@ -649,6 +651,3 @@
*/
#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Src/stm32l4xx_ll_exti.c b/Src/stm32l4xx_ll_exti.c
index 5c52247..8d28066 100644
--- a/Src/stm32l4xx_ll_exti.c
+++ b/Src/stm32l4xx_ll_exti.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -117,7 +116,7 @@
* @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
* @retval An ErrorStatus enumeration value:
* - 0x00: EXTI registers are initialized
- * - any other calue : wrong configuration
+ * - any other value : wrong configuration
*/
uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
{
@@ -287,4 +286,3 @@
#endif /* USE_FULL_LL_DRIVER */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_ll_fmc.c b/Src/stm32l4xx_ll_fmc.c
index a246372..b1c1c77 100644
--- a/Src/stm32l4xx_ll_fmc.c
+++ b/Src/stm32l4xx_ll_fmc.c
@@ -10,6 +10,17 @@
* + Peripheral Control functions
* + Peripheral State functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### FMC peripheral features #####
@@ -39,17 +50,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -858,5 +858,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_ll_gpio.c b/Src/stm32l4xx_ll_gpio.c
index 2fdf8be..c3dd30c 100644
--- a/Src/stm32l4xx_ll_gpio.c
+++ b/Src/stm32l4xx_ll_gpio.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -292,4 +291,3 @@
#endif /* USE_FULL_LL_DRIVER */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_ll_i2c.c b/Src/stm32l4xx_ll_i2c.c
index 2dbdc97..1aee15b 100644
--- a/Src/stm32l4xx_ll_i2c.c
+++ b/Src/stm32l4xx_ll_i2c.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -25,7 +24,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32L4xx_LL_Driver
* @{
@@ -109,7 +108,7 @@
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
}
-#endif
+#endif /* I2C2 */
else if (I2Cx == I2C3)
{
/* Force reset of I2C clock */
@@ -127,7 +126,7 @@
/* Release reset of I2C clock */
LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_I2C4);
}
-#endif
+#endif /* I2C4 */
else
{
status = ERROR;
@@ -243,5 +242,3 @@
*/
#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_ll_lptim.c b/Src/stm32l4xx_ll_lptim.c
index cf00698..4a800cb 100644
--- a/Src/stm32l4xx_ll_lptim.c
+++ b/Src/stm32l4xx_ll_lptim.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -28,7 +27,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32L4xx_LL_Driver
* @{
@@ -196,6 +195,7 @@
uint32_t tmpCFGR;
uint32_t tmpCMP;
uint32_t tmpARR;
+ uint32_t primask_bit;
uint32_t tmpOR;
#if defined(LPTIM_RCR_REP)
uint32_t tmpRCR;
@@ -204,7 +204,9 @@
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(LPTIMx));
- __disable_irq();
+ /* Enter critical section */
+ primask_bit = __get_PRIMASK();
+ __set_PRIMASK(1) ;
/********** Save LPTIM Config *********/
/* Save LPTIM source clock */
@@ -317,7 +319,8 @@
LPTIMx->CFGR = tmpCFGR;
LPTIMx->OR = tmpOR;
- __enable_irq();
+ /* Exit critical section: restore previous priority mask */
+ __set_PRIMASK(primask_bit);
}
/**
@@ -339,5 +342,3 @@
*/
#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_ll_lpuart.c b/Src/stm32l4xx_ll_lpuart.c
index b1f6882..c0e7561 100644
--- a/Src/stm32l4xx_ll_lpuart.c
+++ b/Src/stm32l4xx_ll_lpuart.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -293,6 +292,3 @@
*/
#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Src/stm32l4xx_ll_opamp.c b/Src/stm32l4xx_ll_opamp.c
index 685a080..2ba49e8 100644
--- a/Src/stm32l4xx_ll_opamp.c
+++ b/Src/stm32l4xx_ll_opamp.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -50,7 +49,7 @@
/* OPAMP instance. */
#define IS_LL_OPAMP_POWER_MODE(__POWER_MODE__) \
- ( ((__POWER_MODE__) == LL_OPAMP_POWERMODE_NORMAL) \
+ ( ((__POWER_MODE__) == LL_OPAMP_POWERMODE_NORMALPOWER) \
|| ((__POWER_MODE__) == LL_OPAMP_POWERMODE_LOWPOWER))
#define IS_LL_OPAMP_FUNCTIONAL_MODE(__FUNCTIONAL_MODE__) \
@@ -196,7 +195,7 @@
void LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
{
/* Set OPAMP_InitStruct fields to default values */
- OPAMP_InitStruct->PowerMode = LL_OPAMP_POWERMODE_NORMAL;
+ OPAMP_InitStruct->PowerMode = LL_OPAMP_POWERMODE_NORMALPOWER;
OPAMP_InitStruct->FunctionalMode = LL_OPAMP_MODE_FOLLOWER;
OPAMP_InitStruct->InputNonInverting = LL_OPAMP_INPUT_NONINVERT_IO0;
/* Note: Parameter discarded if OPAMP in functional mode follower, */
@@ -223,5 +222,3 @@
*/
#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_ll_pka.c b/Src/stm32l4xx_ll_pka.c
index 4feba62..910a620 100644
--- a/Src/stm32l4xx_ll_pka.c
+++ b/Src/stm32l4xx_ll_pka.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -26,7 +25,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32L4xx_LL_Driver
* @{
@@ -46,23 +45,23 @@
* @{
*/
#define IS_LL_PKA_MODE(__VALUE__) (((__VALUE__) == LL_PKA_MODE_MONTGOMERY_PARAM_MOD_EXP) ||\
- ((__VALUE__) == LL_PKA_MODE_MONTGOMERY_PARAM) ||\
- ((__VALUE__) == LL_PKA_MODE_MODULAR_EXP) ||\
- ((__VALUE__) == LL_PKA_MODE_MONTGOMERY_PARAM_ECC) ||\
- ((__VALUE__) == LL_PKA_MODE_ECC_KP_PRIMITIVE) ||\
- ((__VALUE__) == LL_PKA_MODE_ECDSA_SIGNATURE) ||\
- ((__VALUE__) == LL_PKA_MODE_ECDSA_VERIFICATION) ||\
- ((__VALUE__) == LL_PKA_MODE_POINT_CHECK) ||\
- ((__VALUE__) == LL_PKA_MODE_RSA_CRT_EXP) ||\
- ((__VALUE__) == LL_PKA_MODE_MODULAR_INV) ||\
- ((__VALUE__) == LL_PKA_MODE_ARITHMETIC_ADD) ||\
- ((__VALUE__) == LL_PKA_MODE_ARITHMETIC_SUB) ||\
- ((__VALUE__) == LL_PKA_MODE_ARITHMETIC_MUL) ||\
- ((__VALUE__) == LL_PKA_MODE_COMPARISON) ||\
- ((__VALUE__) == LL_PKA_MODE_MODULAR_REDUC) ||\
- ((__VALUE__) == LL_PKA_MODE_MODULAR_ADD) ||\
- ((__VALUE__) == LL_PKA_MODE_MODULAR_SUB) ||\
- ((__VALUE__) == LL_PKA_MODE_MONTGOMERY_MUL))
+ ((__VALUE__) == LL_PKA_MODE_MONTGOMERY_PARAM) ||\
+ ((__VALUE__) == LL_PKA_MODE_MODULAR_EXP) ||\
+ ((__VALUE__) == LL_PKA_MODE_MONTGOMERY_PARAM_ECC) ||\
+ ((__VALUE__) == LL_PKA_MODE_ECC_KP_PRIMITIVE) ||\
+ ((__VALUE__) == LL_PKA_MODE_ECDSA_SIGNATURE) ||\
+ ((__VALUE__) == LL_PKA_MODE_ECDSA_VERIFICATION) ||\
+ ((__VALUE__) == LL_PKA_MODE_POINT_CHECK) ||\
+ ((__VALUE__) == LL_PKA_MODE_RSA_CRT_EXP) ||\
+ ((__VALUE__) == LL_PKA_MODE_MODULAR_INV) ||\
+ ((__VALUE__) == LL_PKA_MODE_ARITHMETIC_ADD) ||\
+ ((__VALUE__) == LL_PKA_MODE_ARITHMETIC_SUB) ||\
+ ((__VALUE__) == LL_PKA_MODE_ARITHMETIC_MUL) ||\
+ ((__VALUE__) == LL_PKA_MODE_COMPARISON) ||\
+ ((__VALUE__) == LL_PKA_MODE_MODULAR_REDUC) ||\
+ ((__VALUE__) == LL_PKA_MODE_MODULAR_ADD) ||\
+ ((__VALUE__) == LL_PKA_MODE_MODULAR_SUB) ||\
+ ((__VALUE__) == LL_PKA_MODE_MONTGOMERY_MUL))
/**
* @}
*/
@@ -159,6 +158,3 @@
*/
#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Src/stm32l4xx_ll_pwr.c b/Src/stm32l4xx_ll_pwr.c
index 7b12da7..8907e5d 100644
--- a/Src/stm32l4xx_ll_pwr.c
+++ b/Src/stm32l4xx_ll_pwr.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -81,5 +80,3 @@
*/
#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_ll_rcc.c b/Src/stm32l4xx_ll_rcc.c
index a55f4f4..f7f6d08 100644
--- a/Src/stm32l4xx_ll_rcc.c
+++ b/Src/stm32l4xx_ll_rcc.c
@@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
@@ -865,7 +863,10 @@
case LL_RCC_SAI1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI1 clock source */
if (LL_RCC_PLLSAI1_IsReady() != 0U)
{
- sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI();
+ if (LL_RCC_PLLSAI1_IsEnabledDomain_SAI() != 0U)
+ {
+ sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI();
+ }
}
break;
@@ -873,7 +874,10 @@
case LL_RCC_SAI1_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as SAI1 clock source */
if (LL_RCC_PLLSAI2_IsReady() != 0U)
{
- sai_frequency = RCC_PLLSAI2_GetFreqDomain_SAI();
+ if (LL_RCC_PLLSAI2_IsEnabledDomain_SAI() != 0U)
+ {
+ sai_frequency = RCC_PLLSAI2_GetFreqDomain_SAI();
+ }
}
break;
@@ -881,7 +885,10 @@
case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */
if (LL_RCC_PLL_IsReady() != 0U)
{
- sai_frequency = RCC_PLL_GetFreqDomain_SAI();
+ if (LL_RCC_PLL_IsEnabledDomain_SAI() != 0U)
+ {
+ sai_frequency = RCC_PLL_GetFreqDomain_SAI();
+ }
}
break;
@@ -904,7 +911,10 @@
case LL_RCC_SAI2_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI2 clock source */
if (LL_RCC_PLLSAI1_IsReady() != 0U)
{
- sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI();
+ if (LL_RCC_PLLSAI1_IsEnabledDomain_SAI() != 0U)
+ {
+ sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI();
+ }
}
break;
@@ -912,7 +922,10 @@
case LL_RCC_SAI2_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as SAI2 clock source */
if (LL_RCC_PLLSAI2_IsReady() != 0U)
{
- sai_frequency = RCC_PLLSAI2_GetFreqDomain_SAI();
+ if (LL_RCC_PLLSAI2_IsEnabledDomain_SAI() != 0U)
+ {
+ sai_frequency = RCC_PLLSAI2_GetFreqDomain_SAI();
+ }
}
break;
@@ -920,7 +933,10 @@
case LL_RCC_SAI2_CLKSOURCE_PLL: /* PLL clock used as SAI2 clock source */
if (LL_RCC_PLL_IsReady() != 0U)
{
- sai_frequency = RCC_PLL_GetFreqDomain_SAI();
+ if (LL_RCC_PLL_IsEnabledDomain_SAI() != 0U)
+ {
+ sai_frequency = RCC_PLL_GetFreqDomain_SAI();
+ }
}
break;
@@ -966,7 +982,10 @@
case LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP: /* PLL "P" output (PLLSAI3CLK) clock used as SDMMC1 clock source */
if (LL_RCC_PLL_IsReady() != 0U)
{
- sdmmc_frequency = RCC_PLL_GetFreqDomain_SAI();
+ if (LL_RCC_PLL_IsEnabledDomain_SAI() != 0U)
+ {
+ sdmmc_frequency = RCC_PLL_GetFreqDomain_SAI();
+ }
}
break;
@@ -1001,7 +1020,10 @@
case LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SDMMC1 clock source */
if (LL_RCC_PLLSAI1_IsReady() != 0U)
{
- sdmmc_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
+ if (LL_RCC_PLLSAI1_IsEnabledDomain_48M() != 0U)
+ {
+ sdmmc_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
+ }
}
break;
#endif
@@ -1009,7 +1031,10 @@
case LL_RCC_SDMMC1_CLKSOURCE_PLL: /* PLL clock used as SDMMC1 clock source */
if (LL_RCC_PLL_IsReady() != 0U)
{
- sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();
+ if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
+ {
+ sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();
+ }
}
break;
@@ -1066,7 +1091,10 @@
case LL_RCC_RNG_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as RNG clock source */
if (LL_RCC_PLLSAI1_IsReady() != 0U)
{
- rng_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
+ if (LL_RCC_PLLSAI1_IsEnabledDomain_48M() !=0U)
+ {
+ rng_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
+ }
}
break;
#endif /* RCC_PLLSAI1_SUPPORT */
@@ -1074,7 +1102,10 @@
case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */
if (LL_RCC_PLL_IsReady() != 0U)
{
- rng_frequency = RCC_PLL_GetFreqDomain_48M();
+ if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
+ {
+ rng_frequency = RCC_PLL_GetFreqDomain_48M();
+ }
}
break;
@@ -1132,7 +1163,10 @@
case LL_RCC_USB_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as USB clock source */
if (LL_RCC_PLLSAI1_IsReady() != 0U)
{
- usb_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
+ if (LL_RCC_PLLSAI1_IsEnabledDomain_48M() != 0U)
+ {
+ usb_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
+ }
}
break;
#endif /* RCC_PLLSAI1_SUPPORT */
@@ -1140,7 +1174,10 @@
case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
if (LL_RCC_PLL_IsReady() != 0U)
{
- usb_frequency = RCC_PLL_GetFreqDomain_48M();
+ if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
+ {
+ usb_frequency = RCC_PLL_GetFreqDomain_48M();
+ }
}
break;
@@ -1195,7 +1232,10 @@
case LL_RCC_ADC_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as ADC clock source */
if (LL_RCC_PLLSAI1_IsReady() != 0U)
{
- adc_frequency = RCC_PLLSAI1_GetFreqDomain_ADC();
+ if (LL_RCC_PLLSAI1_IsEnabledDomain_ADC() != 0U)
+ {
+ adc_frequency = RCC_PLLSAI1_GetFreqDomain_ADC();
+ }
}
break;
#endif /* RCC_PLLSAI1_SUPPORT */
@@ -1204,7 +1244,10 @@
case LL_RCC_ADC_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as ADC clock source */
if (LL_RCC_PLLSAI2_IsReady() != 0U)
{
- adc_frequency = RCC_PLLSAI2_GetFreqDomain_ADC();
+ if (LL_RCC_PLLSAI2_IsEnabledDomain_ADC() != 0U)
+ {
+ adc_frequency = RCC_PLLSAI2_GetFreqDomain_ADC();
+ }
}
break;
#endif /* RCC_PLLSAI2_SUPPORT && LL_RCC_ADC_CLKSOURCE_PLLSAI2 */
@@ -1359,7 +1402,10 @@
case LL_RCC_DSI_CLKSOURCE_PLL: /* DSI Clock is PLLSAI2 Osc. */
if (LL_RCC_PLLSAI2_IsReady() != 0U)
{
- dsi_frequency = RCC_PLLSAI2_GetFreqDomain_DSI();
+ if (LL_RCC_PLLSAI2_IsEnabledDomain_DSI() != 0U)
+ {
+ dsi_frequency = RCC_PLLSAI2_GetFreqDomain_DSI();
+ }
}
break;
@@ -1390,7 +1436,10 @@
if (LL_RCC_PLLSAI2_IsReady() != 0U)
{
- ltdc_frequency = RCC_PLLSAI2_GetFreqDomain_LTDC();
+ if (LL_RCC_PLLSAI2_IsEnabledDomain_LTDC() != 0U)
+ {
+ ltdc_frequency = RCC_PLLSAI2_GetFreqDomain_LTDC();
+ }
}
return ltdc_frequency;
@@ -1432,7 +1481,10 @@
case LL_RCC_OCTOSPI_CLKSOURCE_PLL: /* PLL clock used as OCTOSPI source */
if (LL_RCC_PLL_IsReady() != 0U)
{
- octospi_frequency = RCC_PLL_GetFreqDomain_48M();
+ if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
+ {
+ octospi_frequency = RCC_PLL_GetFreqDomain_48M();
+ }
}
break;
@@ -1985,4 +2037,3 @@
#endif /* USE_FULL_LL_DRIVER */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_ll_rng.c b/Src/stm32l4xx_ll_rng.c
index 40b27b1..2d7dabf 100644
--- a/Src/stm32l4xx_ll_rng.c
+++ b/Src/stm32l4xx_ll_rng.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -157,6 +156,3 @@
*/
#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Src/stm32l4xx_ll_rtc.c b/Src/stm32l4xx_ll_rtc.c
index ee462ab..956e1a5 100644
--- a/Src/stm32l4xx_ll_rtc.c
+++ b/Src/stm32l4xx_ll_rtc.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -147,7 +146,7 @@
/* Set Initialization mode */
status = LL_RTC_EnterInitMode(RTCx);
- if(status != ERROR)
+ if (status != ERROR)
{
/* Reset TR, DR and CR registers */
LL_RTC_WriteReg(RTCx, TR, 0x00000000U);
@@ -314,7 +313,7 @@
}
/* Exit Initialization mode */
- LL_RTC_DisableInitMode(RTC);
+ LL_RTC_DisableInitMode(RTCx);
/* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
@@ -403,7 +402,7 @@
}
/* Exit Initialization mode */
- LL_RTC_DisableInitMode(RTC);
+ LL_RTC_DisableInitMode(RTCx);
/* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
@@ -862,5 +861,3 @@
*/
#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_ll_sdmmc.c b/Src/stm32l4xx_ll_sdmmc.c
index 0e1cad2..feedcdf 100644
--- a/Src/stm32l4xx_ll_sdmmc.c
+++ b/Src/stm32l4xx_ll_sdmmc.c
@@ -11,6 +11,17 @@
* + Peripheral Control functions
* + Peripheral State functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### SDMMC peripheral features #####
@@ -150,17 +161,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -541,7 +541,7 @@
*/
/**
- * @brief Send the Data Block Lenght command and check the response
+ * @brief Send the Data Block Length command and check the response
* @param SDMMCx Pointer to SDMMC register base
* @retval HAL status
*/
@@ -1097,6 +1097,31 @@
}
/**
+ * @brief Send the Sleep command to MMC card (not SD card).
+ * @param SDMMCx Pointer to SDMMC register base
+ * @param Argument Argument of the command (RCA and Sleep/Awake)
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSleepMmc(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ /* Send CMD5 SDMMC_CMD_MMC_SLEEP_AWAKE */
+ sdmmc_cmdinit.Argument = Argument;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_MMC_SLEEP_AWAKE;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_MMC_SLEEP_AWAKE, SDMMC_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
* @brief Send the Status command and check the response.
* @param SDMMCx Pointer to SDMMC register base
* @param Argument Command Argument
@@ -1169,7 +1194,7 @@
}
/**
- * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand
+ * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH command
* @param SDMMCx Pointer to SDMMC register base
* @parame Argument: Argument used for the command
* @retval HAL status
@@ -1661,5 +1686,3 @@
*/
#endif /* SDMMC1 */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_ll_spi.c b/Src/stm32l4xx_ll_spi.c
index cb9db11..89cc53f 100644
--- a/Src/stm32l4xx_ll_spi.c
+++ b/Src/stm32l4xx_ll_spi.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -26,7 +25,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32L4xx_LL_Driver
* @{
@@ -294,4 +293,3 @@
#endif /* USE_FULL_LL_DRIVER */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_ll_swpmi.c b/Src/stm32l4xx_ll_swpmi.c
index 458b7a5..8bafe84 100644
--- a/Src/stm32l4xx_ll_swpmi.c
+++ b/Src/stm32l4xx_ll_swpmi.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -100,8 +99,9 @@
/**
* @brief Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitStruct.
- * @note As some bits in SWPMI configuration registers can only be written when the SWPMI is deactivated (SWPMI_CR_SWPACT bit = 0),
- * SWPMI IP should be in deactivated state prior calling this function. Otherwise, ERROR result will be returned.
+ * @note As some bits in SWPMI configuration registers can only be written when the SWPMI is deactivated
+ * (SWPMI_CR_SWPACT bit = 0), the SWPMI peripheral should be in deactivated state prior calling
+ * this function. Otherwise, ERROR result will be returned.
* @param SWPMIx SWPMI Instance
* @param SWPMI_InitStruct pointer to a @ref LL_SWPMI_InitTypeDef structure that contains
* the configuration information for the SWPMI peripheral.
@@ -131,8 +131,8 @@
/* Set the new configuration of the SWPMI peripheral */
MODIFY_REG(SWPMIx->CR,
- (SWPMI_CR_RXMODE | SWPMI_CR_TXMODE),
- (SWPMI_InitStruct->TxBufferingMode | SWPMI_InitStruct->RxBufferingMode));
+ (SWPMI_CR_RXMODE | SWPMI_CR_TXMODE),
+ (SWPMI_InitStruct->TxBufferingMode | SWPMI_InitStruct->RxBufferingMode));
}
/* Else (SWPMI not in deactivated state => return ERROR) */
else
@@ -177,5 +177,3 @@
*/
#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_ll_tim.c b/Src/stm32l4xx_ll_tim.c
index 80ceebe..eb87565 100644
--- a/Src/stm32l4xx_ll_tim.c
+++ b/Src/stm32l4xx_ll_tim.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -237,21 +236,21 @@
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
}
-#endif
+#endif /* TIM3 */
#if defined(TIM4)
else if (TIMx == TIM4)
{
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
}
-#endif
+#endif /* TIM4 */
#if defined(TIM5)
else if (TIMx == TIM5)
{
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
}
-#endif
+#endif /* TIM5 */
else if (TIMx == TIM6)
{
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
@@ -263,14 +262,14 @@
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
}
-#endif
+#endif /* TIM7 */
#if defined(TIM8)
else if (TIMx == TIM8)
{
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
}
-#endif
+#endif /* TIM8 */
else if (TIMx == TIM15)
{
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
@@ -287,7 +286,7 @@
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
}
-#endif
+#endif /* TIM17 */
else
{
result = ERROR;
@@ -315,7 +314,8 @@
/**
* @brief Configure the TIMx time base unit.
* @param TIMx Timer Instance
- * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
+ * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
+ * (TIMx time base unit configuration data structure)
* @retval An ErrorStatus enumeration value:
* - SUCCESS: TIMx registers are de-initialized
* - ERROR: not applicable
@@ -368,7 +368,8 @@
/**
* @brief Set the fields of the TIMx output channel configuration data
* structure to their default values.
- * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
+ * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
+ * (the output channel configuration data structure)
* @retval None
*/
void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
@@ -394,7 +395,8 @@
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
- * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
+ * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
+ * data structure)
* @retval An ErrorStatus enumeration value:
* - SUCCESS: TIMx output channel is initialized
* - ERROR: TIMx output channel is not initialized
@@ -433,7 +435,8 @@
/**
* @brief Set the fields of the TIMx input channel configuration data
* structure to their default values.
- * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
+ * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
+ * data structure)
* @retval None
*/
void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
@@ -453,7 +456,8 @@
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
- * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
+ * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
+ * structure)
* @retval An ErrorStatus enumeration value:
* - SUCCESS: TIMx output channel is initialized
* - ERROR: TIMx output channel is not initialized
@@ -485,7 +489,8 @@
/**
* @brief Fills each TIM_EncoderInitStruct field with its default value
- * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
+ * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
+ * configuration data structure)
* @retval None
*/
void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
@@ -505,7 +510,8 @@
/**
* @brief Configure the encoder interface of the timer instance.
* @param TIMx Timer Instance
- * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
+ * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
+ * configuration data structure)
* @retval An ErrorStatus enumeration value:
* - SUCCESS: TIMx registers are de-initialized
* - ERROR: not applicable
@@ -569,7 +575,8 @@
/**
* @brief Set the fields of the TIMx Hall sensor interface configuration data
* structure to their default values.
- * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
+ * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
+ * configuration data structure)
* @retval None
*/
void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
@@ -596,7 +603,8 @@
* @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
* when TIMx operates in Hall sensor interface mode.
* @param TIMx Timer Instance
- * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
+ * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
+ * interface configuration data structure)
* @retval An ErrorStatus enumeration value:
* - SUCCESS: TIMx registers are de-initialized
* - ERROR: not applicable
@@ -676,7 +684,8 @@
/**
* @brief Set the fields of the Break and Dead Time configuration data structure
* to their default values.
- * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
+ * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
+ * data structure)
* @retval None
*/
void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
@@ -706,7 +715,8 @@
* @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a second break input.
* @param TIMx Timer Instance
- * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
+ * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
+ * data structure)
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Break and Dead Time is initialized
* - ERROR: not applicable
@@ -1348,4 +1358,3 @@
#endif /* USE_FULL_LL_DRIVER */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_ll_usart.c b/Src/stm32l4xx_ll_usart.c
index 69278d3..90f603f 100644
--- a/Src/stm32l4xx_ll_usart.c
+++ b/Src/stm32l4xx_ll_usart.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -196,8 +195,9 @@
/**
* @brief Initialize USART registers according to the specified
* parameters in USART_InitStruct.
- * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
- * USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @note As some bits in USART configuration registers can only be written when
+ * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
+ * this function. Otherwise, ERROR result will be returned.
* @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
* @param USARTx USART Instance
* @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
@@ -250,7 +250,8 @@
/*---------------------------- USART CR3 Configuration ---------------------
* Configure USARTx CR3 (Hardware Flow Control) with parameters:
- * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
+ * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to
+ * USART_InitStruct->HardwareFlowControl value.
*/
LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
@@ -289,9 +290,9 @@
}
/* Configure the USART Baud Rate :
- #if defined(USART_PRESC_PRESCALER)
+#if defined(USART_PRESC_PRESCALER)
- prescaler value is required
- #endif
+#endif
- valid baud rate value (different from 0) is required
- Peripheral clock as returned by RCC service, should be valid (different from 0).
*/
@@ -349,13 +350,15 @@
/**
* @brief Initialize USART Clock related settings according to the
* specified parameters in the USART_ClockInitStruct.
- * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
- * USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @note As some bits in USART configuration registers can only be written when
+ * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
+ * this function. Otherwise, ERROR result will be returned.
* @param USARTx USART Instance
* @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
* that contains the Clock configuration information for the specified USART peripheral.
* @retval An ErrorStatus enumeration value:
- * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
+ * - SUCCESS: USART registers related to Clock settings are initialized according
+ * to USART_ClockInitStruct content
* - ERROR: Problem occurred during USART Registers initialization
*/
ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
@@ -442,9 +445,12 @@
{
/* Set LL_USART_ClockInitStruct fields with default values */
USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
- USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
- USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
- USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
+ USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput =
+ LL_USART_CLOCK_DISABLE */
+ USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput =
+ LL_USART_CLOCK_DISABLE */
+ USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput =
+ LL_USART_CLOCK_DISABLE */
}
/**
@@ -467,5 +473,4 @@
#endif /* USE_FULL_LL_DRIVER */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_ll_usb.c b/Src/stm32l4xx_ll_usb.c
index 59ab984..cb1ec13 100644
--- a/Src/stm32l4xx_ll_usb.c
+++ b/Src/stm32l4xx_ll_usb.c
@@ -11,6 +11,17 @@
* + Peripheral Control functions
* + Peripheral State functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -23,17 +34,7 @@
(#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+
******************************************************************************
*/
@@ -83,7 +84,6 @@
{
HAL_StatusTypeDef ret;
-
/* Select FS Embedded PHY */
USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
@@ -219,21 +219,39 @@
*/
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode)
{
+ uint32_t ms = 0U;
+
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
if (mode == USB_HOST_MODE)
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
+
+ do
+ {
+ HAL_Delay(1U);
+ ms++;
+ } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < 50U));
}
else if (mode == USB_DEVICE_MODE)
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
+
+ do
+ {
+ HAL_Delay(1U);
+ ms++;
+ } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < 50U));
}
else
{
return HAL_ERROR;
}
- HAL_Delay(50U);
+
+ if (ms == 50U)
+ {
+ return HAL_ERROR;
+ }
return HAL_OK;
}
@@ -375,7 +393,7 @@
}
/**
- * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO
+ * @brief USB_FlushTxFifo Flush a Tx FIFO
* @param USBx Selected device
* @param num FIFO number
* This parameter can be a value from 1 to 15
@@ -384,8 +402,19 @@
*/
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
{
- uint32_t count = 0U;
+ __IO uint32_t count = 0U;
+ /* Wait for AHB master IDLE state. */
+ do
+ {
+ if (++count > 200000U)
+ {
+ return HAL_TIMEOUT;
+ }
+ } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
+
+ /* Flush TX Fifo */
+ count = 0U;
USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
do
@@ -400,14 +429,25 @@
}
/**
- * @brief USB_FlushRxFifo : Flush Rx FIFO
+ * @brief USB_FlushRxFifo Flush Rx FIFO
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
{
- uint32_t count = 0;
+ __IO uint32_t count = 0U;
+ /* Wait for AHB master IDLE state. */
+ do
+ {
+ if (++count > 200000U)
+ {
+ return HAL_TIMEOUT;
+ }
+ } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
+
+ /* Flush RX Fifo */
+ count = 0U;
USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
do
@@ -657,7 +697,9 @@
*/
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
- USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19));
+ USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT &
+ (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19));
+
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
if (ep->type == EP_TYPE_ISOC)
@@ -802,6 +844,60 @@
return HAL_OK;
}
+
+/**
+ * @brief USB_EPStoptXfer Stop transfer on an EP
+ * @param USBx usb device instance
+ * @param ep pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+ __IO uint32_t count = 0U;
+ HAL_StatusTypeDef ret = HAL_OK;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+
+ /* IN endpoint */
+ if (ep->is_in == 1U)
+ {
+ /* EP enable, IN data in FIFO */
+ if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
+ {
+ USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK);
+ USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS);
+
+ do
+ {
+ if (++count > 10000U)
+ {
+ ret = HAL_ERROR;
+ break;
+ }
+ } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA);
+ }
+ }
+ else /* OUT endpoint */
+ {
+ if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+ {
+ USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK);
+ USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS);
+
+ do
+ {
+ if (++count > 10000U)
+ {
+ ret = HAL_ERROR;
+ break;
+ }
+ } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA);
+ }
+ }
+
+ return ret;
+}
+
+
/**
* @brief USB_WritePacket : Writes a packet into the Tx FIFO associated
* with the EP/channel
@@ -815,14 +911,18 @@
uint8_t ch_ep_num, uint16_t len)
{
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t *pSrc = (uint32_t *)src;
- uint32_t count32b, i;
+ uint8_t *pSrc = src;
+ uint32_t count32b;
+ uint32_t i;
count32b = ((uint32_t)len + 3U) / 4U;
for (i = 0U; i < count32b; i++)
{
USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);
pSrc++;
+ pSrc++;
+ pSrc++;
+ pSrc++;
}
return HAL_OK;
@@ -838,14 +938,34 @@
void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
{
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t *pDest = (uint32_t *)dest;
+ uint8_t *pDest = dest;
+ uint32_t pData;
uint32_t i;
- uint32_t count32b = ((uint32_t)len + 3U) / 4U;
+ uint32_t count32b = (uint32_t)len >> 2U;
+ uint16_t remaining_bytes = len % 4U;
for (i = 0U; i < count32b; i++)
{
__UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));
pDest++;
+ pDest++;
+ pDest++;
+ pDest++;
+ }
+
+ /* When Number of data is not word aligned, read the remaining byte */
+ if (remaining_bytes != 0U)
+ {
+ i = 0U;
+ __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U));
+
+ do
+ {
+ *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i)));
+ i++;
+ pDest++;
+ remaining_bytes--;
+ } while (remaining_bytes != 0U);
}
return ((void *)pDest);
@@ -1077,7 +1197,9 @@
uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
{
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t tmpreg, msk, emp;
+ uint32_t tmpreg;
+ uint32_t msk;
+ uint32_t emp;
msk = USBx_DEVICE->DIEPMSK;
emp = USBx_DEVICE->DIEPEMPMSK;
@@ -1136,9 +1258,9 @@
*/
HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup)
{
- UNUSED(psetup);
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+ UNUSED(psetup);
if (gSNPSiD > USB_OTG_CORE_ID_300A)
{
@@ -1163,7 +1285,7 @@
*/
static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
{
- uint32_t count = 0U;
+ __IO uint32_t count = 0U;
/* Wait for AHB master IDLE state. */
do
@@ -1199,6 +1321,7 @@
*/
HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
{
+ HAL_StatusTypeDef ret = HAL_OK;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t i;
@@ -1215,8 +1338,15 @@
USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
/* Make sure the FIFOs are flushed. */
- (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */
- (void)USB_FlushRxFifo(USBx);
+ if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
+ {
+ ret = HAL_ERROR;
+ }
+
+ if (USB_FlushRxFifo(USBx) != HAL_OK)
+ {
+ ret = HAL_ERROR;
+ }
/* Clear all pending HC Interrupts */
for (i = 0U; i < cfg.Host_channels; i++)
@@ -1225,11 +1355,6 @@
USBx_HC(i)->HCINTMSK = 0U;
}
- /* Enable VBUS driving */
- (void)USB_DriveVbus(USBx, 1U);
-
- HAL_Delay(200U);
-
/* Disable all interrupts. */
USBx->GINTMSK = 0U;
@@ -1248,7 +1373,7 @@
USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \
USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
- return HAL_OK;
+ return ret;
}
/**
@@ -1397,7 +1522,8 @@
{
HAL_StatusTypeDef ret = HAL_OK;
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t HCcharEpDir, HCcharLowSpeed;
+ uint32_t HCcharEpDir;
+ uint32_t HCcharLowSpeed;
uint32_t HostCoreSpeed;
/* Clear old interrupt conditions for this host channel. */
@@ -1454,6 +1580,9 @@
break;
}
+ /* Enable host channel Halt interrupt */
+ USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM;
+
/* Enable the top level host channel interrupt. */
USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU);
@@ -1629,7 +1758,7 @@
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t hcnum = (uint32_t)hc_num;
- uint32_t count = 0U;
+ __IO uint32_t count = 0U;
uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18;
uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31;
@@ -1650,7 +1779,6 @@
{
USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
do
{
if (++count > 1000U)
@@ -1673,7 +1801,6 @@
{
USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
do
{
if (++count > 1000U)
@@ -1724,16 +1851,24 @@
*/
HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
{
+ HAL_StatusTypeDef ret = HAL_OK;
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t count = 0U;
+ __IO uint32_t count = 0U;
uint32_t value;
uint32_t i;
(void)USB_DisableGlobalInt(USBx);
- /* Flush FIFO */
- (void)USB_FlushTxFifo(USBx, 0x10U);
- (void)USB_FlushRxFifo(USBx);
+ /* Flush USB FIFO */
+ if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
+ {
+ ret = HAL_ERROR;
+ }
+
+ if (USB_FlushRxFifo(USBx) != HAL_OK)
+ {
+ ret = HAL_ERROR;
+ }
/* Flush out any leftover queued requests. */
for (i = 0U; i <= 15U; i++)
@@ -1769,7 +1904,7 @@
(void)USB_EnableGlobalInt(USBx);
- return HAL_OK;
+ return ret;
}
/**
@@ -2028,22 +2163,31 @@
}
else
{
- /*Set the endpoint Receive buffer address */
+ /* Set the endpoint Receive buffer address */
PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);
- /*Set the endpoint Receive buffer counter*/
+ /* Set the endpoint Receive buffer counter */
PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
PCD_CLEAR_RX_DTOG(USBx, ep->num);
- /* Configure VALID status for the Endpoint*/
+ /* Configure VALID status for the Endpoint */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
}
}
- /*Double Buffer*/
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+ /* Double Buffer */
else
{
- /* Set the endpoint as double buffered */
- PCD_SET_EP_DBUF(USBx, ep->num);
+ if (ep->type == EP_TYPE_BULK)
+ {
+ /* Set bulk endpoint as double buffered */
+ PCD_SET_BULK_EP_DBUF(USBx, ep->num);
+ }
+ else
+ {
+ /* Set the ISOC endpoint in double buffer mode */
+ PCD_CLEAR_EP_KIND(USBx, ep->num);
+ }
/* Set buffer address for double buffered mode */
PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1);
@@ -2077,6 +2221,7 @@
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
}
}
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
return ret;
}
@@ -2095,18 +2240,20 @@
{
PCD_CLEAR_TX_DTOG(USBx, ep->num);
- /* Configure DISABLE status for the Endpoint*/
+ /* Configure DISABLE status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
}
+
else
{
PCD_CLEAR_RX_DTOG(USBx, ep->num);
- /* Configure DISABLE status for the Endpoint*/
+ /* Configure DISABLE status for the Endpoint */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
}
}
- /*Double Buffer*/
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+ /* Double Buffer */
else
{
if (ep->is_in == 0U)
@@ -2133,6 +2280,7 @@
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
}
}
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
return HAL_OK;
}
@@ -2146,8 +2294,10 @@
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
uint32_t len;
+#if (USE_USB_DOUBLE_BUFFER == 1U)
uint16_t pmabuffer;
uint16_t wEPVal;
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
/* IN endpoint */
if (ep->is_in == 1U)
@@ -2168,6 +2318,7 @@
USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len);
PCD_SET_EP_TX_CNT(USBx, ep->num, len);
}
+#if (USE_USB_DOUBLE_BUFFER == 1U)
else
{
/* double buffer bulk management */
@@ -2176,7 +2327,7 @@
if (ep->xfer_len_db > ep->maxpacket)
{
/* enable double buffer */
- PCD_SET_EP_DBUF(USBx, ep->num);
+ PCD_SET_BULK_EP_DBUF(USBx, ep->num);
/* each Time to write in PMA xfer_len_db will */
ep->xfer_len_db -= len;
@@ -2242,8 +2393,8 @@
{
len = ep->xfer_len_db;
- /* disable double buffer mode */
- PCD_CLEAR_EP_DBUF(USBx, ep->num);
+ /* disable double buffer mode for Bulk endpoint */
+ PCD_CLEAR_BULK_EP_DBUF(USBx, ep->num);
/* Set Tx count with nbre of byte to be transmitted */
PCD_SET_EP_TX_CNT(USBx, ep->num, len);
@@ -2252,14 +2403,9 @@
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
}
- }/* end if bulk double buffer */
-
- /* manage isochronous double buffer IN mode */
- else
+ }
+ else /* manage isochronous double buffer IN mode */
{
- /* enable double buffer */
- PCD_SET_EP_DBUF(USBx, ep->num);
-
/* each Time to write in PMA xfer_len_db will */
ep->xfer_len_db -= len;
@@ -2272,27 +2418,6 @@
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
- ep->xfer_buff += len;
-
- if (ep->xfer_len_db > ep->maxpacket)
- {
- ep->xfer_len_db -= len;
- }
- else
- {
- len = ep->xfer_len_db;
- ep->xfer_len_db = 0U;
- }
-
- if (len > 0U)
- {
- /* Set the Double buffer counter for pmabuffer0 */
- PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
- pmabuffer = ep->pmaaddr0;
-
- /* Write the user buffer to USB PMA */
- USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
- }
}
else
{
@@ -2302,30 +2427,10 @@
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
- ep->xfer_buff += len;
-
- if (ep->xfer_len_db > ep->maxpacket)
- {
- ep->xfer_len_db -= len;
- }
- else
- {
- len = ep->xfer_len_db;
- ep->xfer_len_db = 0U;
- }
-
- if (len > 0U)
- {
- /* Set the Double buffer counter for pmabuffer1 */
- PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
- pmabuffer = ep->pmaaddr1;
-
- /* Write the user buffer to USB PMA */
- USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
- }
}
}
}
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
}
@@ -2347,6 +2452,7 @@
/* configure and validate Rx endpoint */
PCD_SET_EP_RX_CNT(USBx, ep->num, len);
}
+#if (USE_USB_DOUBLE_BUFFER == 1U)
else
{
/* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */
@@ -2365,7 +2471,7 @@
if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
(((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
{
- PCD_FreeUserBuffer(USBx, ep->num, 0U);
+ PCD_FREE_USER_BUFFER(USBx, ep->num, 0U);
}
}
}
@@ -2390,6 +2496,7 @@
return HAL_ERROR;
}
}
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
}
@@ -2449,7 +2556,52 @@
return HAL_OK;
}
-#endif
+
+/**
+ * @brief USB_EPStoptXfer Stop transfer on an EP
+ * @param USBx usb device instance
+ * @param ep pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EPStopXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
+{
+ /* IN endpoint */
+ if (ep->is_in == 1U)
+ {
+ if (ep->doublebuffer == 0U)
+ {
+ if (ep->type != EP_TYPE_ISOC)
+ {
+ /* Configure NAK status for the Endpoint */
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
+ }
+ else
+ {
+ /* Configure TX Endpoint to disabled state */
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ }
+ }
+ }
+ else /* OUT endpoint */
+ {
+ if (ep->doublebuffer == 0U)
+ {
+ if (ep->type != EP_TYPE_ISOC)
+ {
+ /* Configure NAK status for the Endpoint */
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK);
+ }
+ else
+ {
+ /* Configure RX Endpoint to disabled state */
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+#endif /* defined (HAL_PCD_MODULE_ENABLED) */
/**
* @brief USB_StopDevice Stop the usb device mode
@@ -2668,7 +2820,9 @@
{
uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
uint32_t BaseAddr = (uint32_t)USBx;
- uint32_t i, temp1, temp2;
+ uint32_t i;
+ uint32_t temp1;
+ uint32_t temp2;
__IO uint16_t *pdwVal;
uint8_t *pBuf = pbUsrBuf;
@@ -2684,7 +2838,7 @@
#if PMA_ACCESS > 1U
pdwVal++;
-#endif
+#endif /* PMA_ACCESS */
pBuf++;
}
@@ -2702,7 +2856,8 @@
{
uint32_t n = (uint32_t)wNBytes >> 1;
uint32_t BaseAddr = (uint32_t)USBx;
- uint32_t i, temp;
+ uint32_t i;
+ uint32_t temp;
__IO uint16_t *pdwVal;
uint8_t *pBuf = pbUsrBuf;
@@ -2719,7 +2874,7 @@
#if PMA_ACCESS > 1U
pdwVal++;
-#endif
+#endif /* PMA_ACCESS */
}
if ((wNBytes % 2U) != 0U)
@@ -2743,5 +2898,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l4xx_ll_utils.c b/Src/stm32l4xx_ll_utils.c
index b1dd002..5375be8 100644
--- a/Src/stm32l4xx_ll_utils.c
+++ b/Src/stm32l4xx_ll_utils.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -912,5 +911,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
