Merge pull request #11 from schilkp/master
[HAL][GPIO] Fix documentation errors.
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index 82fe0e9..f11d8c4 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -4215,6 +4215,9 @@
#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
+
+#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1
+#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2
/**
* @}
*/
diff --git a/Inc/stm32l4xx_hal_tim.h b/Inc/stm32l4xx_hal_tim.h
index 6cbfe7a..5f958c4 100644
--- a/Inc/stm32l4xx_hal_tim.h
+++ b/Inc/stm32l4xx_hal_tim.h
@@ -1001,8 +1001,8 @@
#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */
#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */
#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */
-#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
-#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
+#define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
+#define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
/**
* @}
*/
@@ -1955,8 +1955,8 @@
((__MODE__) == TIM_OCMODE_PWM2) || \
((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
- ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
- ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
+ ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \
+ ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2))
#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
((__MODE__) == TIM_OCMODE_ACTIVE) || \
diff --git a/Inc/stm32l4xx_ll_tim.h b/Inc/stm32l4xx_ll_tim.h
index fb8110f..a98c585 100644
--- a/Inc/stm32l4xx_ll_tim.h
+++ b/Inc/stm32l4xx_ll_tim.h
@@ -737,6 +737,15 @@
*/
#endif /* USE_FULL_LL_DRIVER */
+/** Legacy definitions for compatibility purpose
+@cond 0
+ */
+#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
+#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
+/**
+@endcond
+ */
+
/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
* @{
*/
@@ -752,8 +761,8 @@
#define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
#define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
#define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
-#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
-#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
+#define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
+#define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
/**
* @}
*/
@@ -2143,8 +2152,8 @@
* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
- * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
- * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
+ * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
+ * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
@@ -2183,8 +2192,8 @@
* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
- * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
- * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
+ * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
+ * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
{
diff --git a/Inc/stm32l4xx_ll_usb.h b/Inc/stm32l4xx_ll_usb.h
index 38f9d47..244c04b 100644
--- a/Inc/stm32l4xx_ll_usb.h
+++ b/Inc/stm32l4xx_ll_usb.h
@@ -38,6 +38,10 @@
/* Exported types ------------------------------------------------------------*/
+#ifndef HAL_USB_CURRENT_MODE_MAX_DELAY_MS
+#define HAL_USB_CURRENT_MODE_MAX_DELAY_MS 200U
+#endif /* define HAL_USB_CURRENT_MODE_MAX_DELAY_MS */
+
/**
* @brief USB Mode definition
*/
diff --git a/Inc/stm32l4xx_ll_utils.h b/Inc/stm32l4xx_ll_utils.h
index d465c0d..8c2d542 100644
--- a/Inc/stm32l4xx_ll_utils.h
+++ b/Inc/stm32l4xx_ll_utils.h
@@ -274,7 +274,7 @@
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
* configuration by calling this function, for a delay use rather osDelay RTOS service.
- * @param Ticks Number of ticks
+ * @param Ticks Frequency of Ticks (Hz)
* @retval None
*/
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
diff --git a/Src/stm32l4xx_hal_can.c b/Src/stm32l4xx_hal_can.c
index 9c51e6f..c0d18e4 100644
--- a/Src/stm32l4xx_hal_can.c
+++ b/Src/stm32l4xx_hal_can.c
@@ -33,7 +33,7 @@
(++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE()
(++) Configure CAN pins
(+++) Enable the clock for the CAN GPIOs
- (+++) Configure CAN pins as alternate function open-drain
+ (+++) Configure CAN pins as alternate function
(++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification())
(+++) Configure the CAN interrupt priority using
HAL_NVIC_SetPriority()
@@ -235,6 +235,7 @@
* @{
*/
#define CAN_TIMEOUT_VALUE 10U
+#define CAN_WAKEUP_TIMEOUT_COUNTER 1000000U
/**
* @}
*/
@@ -248,8 +249,8 @@
*/
/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
@@ -328,7 +329,7 @@
/* Init the low level hardware: CLOCK, NVIC */
HAL_CAN_MspInit(hcan);
}
-#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/* Request initialisation */
SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
@@ -482,7 +483,7 @@
#else
/* DeInit the low level hardware: CLOCK, NVIC */
HAL_CAN_MspDeInit(hcan);
-#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/* Reset the CAN peripheral */
SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET);
@@ -814,8 +815,8 @@
*/
/** @defgroup CAN_Exported_Functions_Group2 Configuration functions
- * @brief Configuration functions.
- *
+ * @brief Configuration functions.
+ *
@verbatim
==============================================================================
##### Configuration functions #####
@@ -868,7 +869,7 @@
/* Check the parameters */
assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
-#endif
+#endif /* CAN3 */
/* Initialisation mode for the filter */
SET_BIT(can_ip->FMR, CAN_FMR_FINIT);
@@ -878,7 +879,7 @@
CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);
SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
-#endif
+#endif /* CAN3 */
/* Convert filter number into bit position */
filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU);
@@ -970,8 +971,8 @@
*/
/** @defgroup CAN_Exported_Functions_Group3 Control functions
- * @brief Control functions
- *
+ * @brief Control functions
+ *
@verbatim
==============================================================================
##### Control functions #####
@@ -1143,7 +1144,6 @@
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
{
__IO uint32_t count = 0;
- uint32_t timeout = 1000000U;
HAL_CAN_StateTypeDef state = hcan->State;
if ((state == HAL_CAN_STATE_READY) ||
@@ -1159,15 +1159,14 @@
count++;
/* Check if timeout is reached */
- if (count > timeout)
+ if (count > CAN_WAKEUP_TIMEOUT_COUNTER)
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
return HAL_ERROR;
}
- }
- while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
+ } while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
/* Return function status */
return HAL_OK;
@@ -1608,8 +1607,8 @@
*/
/** @defgroup CAN_Exported_Functions_Group4 Interrupts management
- * @brief Interrupts management
- *
+ * @brief Interrupts management
+ *
@verbatim
==============================================================================
##### Interrupts management #####
@@ -2074,8 +2073,8 @@
*/
/** @defgroup CAN_Exported_Functions_Group5 Callback functions
- * @brief CAN Callback functions
- *
+ * @brief CAN Callback functions
+ *
@verbatim
==============================================================================
##### Callback functions #####
@@ -2324,8 +2323,8 @@
*/
/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
- * @brief CAN Peripheral State functions
- *
+ * @brief CAN Peripheral State functions
+ *
@verbatim
==============================================================================
##### Peripheral State and Error functions #####
diff --git a/Src/stm32l4xx_hal_hash.c b/Src/stm32l4xx_hal_hash.c
index 8eede13..50fb51b 100644
--- a/Src/stm32l4xx_hal_hash.c
+++ b/Src/stm32l4xx_hal_hash.c
@@ -123,7 +123,7 @@
(#) HAL in interruption mode (interruptions driven)
(##)Due to HASH peripheral hardware design, the peripheral interruption is triggered every 64 bytes.
- This is why, for driver implementation simplicity’s sake, user is requested to enter a message the
+ This is why, for driver implementation simplicity s sake, user is requested to enter a message the
length of which is a multiple of 4 bytes.
(##) When the message length (in bytes) is not a multiple of words, a specific field exists in HASH_STR
@@ -1825,8 +1825,9 @@
{
uint32_t buffercounter;
__IO uint32_t inputaddr = (uint32_t) pInBuffer;
+ uint32_t tmp;
- for (buffercounter = 0U; buffercounter < Size; buffercounter += 4U)
+ for (buffercounter = 0U; buffercounter < Size / 4U; buffercounter++)
{
/* Write input data 4 bytes at a time */
HASH->DIN = *(uint32_t *)inputaddr;
@@ -1834,8 +1835,16 @@
/* If the suspension flag has been raised and if the processing is not about
to end, suspend processing */
- if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter + 4U) < Size))
+ if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter * 4 + 4U) < Size))
{
+ /* wait for flag BUSY not set before Wait for DINIS = 1*/
+ if (buffercounter * 4 >= 64U)
+ {
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
/* Wait for DINIS = 1, which occurs when 16 32-bit locations are free
in the input buffer */
if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
@@ -1850,14 +1859,14 @@
/* Save current reading and writing locations of Input and Output buffers */
hhash->pHashInBuffPtr = (uint8_t *)inputaddr;
/* Save the number of bytes that remain to be processed at this point */
- hhash->HashInCount = Size - (buffercounter + 4U);
+ hhash->HashInCount = Size - (buffercounter * 4 + 4U);
}
else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
{
/* Save current reading and writing locations of Input and Output buffers */
hhash->pHashKeyBuffPtr = (uint8_t *)inputaddr;
/* Save the number of bytes that remain to be processed at this point */
- hhash->HashKeyCount = Size - (buffercounter + 4U);
+ hhash->HashKeyCount = Size - (buffercounter * 4 + 4U);
}
else
{
@@ -1876,6 +1885,52 @@
} /* for(buffercounter = 0; buffercounter < Size; buffercounter+=4) */
/* At this point, all the data have been entered to the Peripheral: exit */
+
+ if (Size % 4U != 0U)
+ {
+ if (hhash->Init.DataType == HASH_DATATYPE_16B)
+ {
+ /* Write remaining input data */
+
+ if (Size % 4U <= 2)
+ {
+ HASH->DIN = (uint32_t) * (uint16_t *)inputaddr;
+ }
+ if (Size % 4U == 3)
+ {
+ HASH->DIN = *(uint32_t *)inputaddr;
+ }
+
+ }
+ else if ((hhash->Init.DataType == HASH_DATATYPE_8B)
+ || (hhash->Init.DataType == HASH_DATATYPE_1B)) /* byte swap or bit swap or */
+ {
+ /* Write remaining input data */
+ if (Size % 4U == 1)
+ {
+ HASH->DIN = (uint32_t) * (uint8_t *)inputaddr;
+ }
+ if (Size % 4U == 2)
+ {
+ HASH->DIN = (uint32_t) * (uint16_t *)inputaddr;
+ }
+ if (Size % 4U == 3)
+ {
+ tmp = *(uint8_t *)inputaddr;
+ tmp |= *(uint8_t *)(inputaddr + 1U) << 8U ;
+ tmp |= *(uint8_t *)(inputaddr + 2U) << 16U;
+ HASH->DIN = tmp;
+ }
+
+ }
+ else
+ {
+ HASH->DIN = *(uint32_t *)inputaddr;
+ }
+ /*hhash->HashInCount += 4U;*/
+ }
+
+
return HAL_OK;
}
@@ -2963,11 +3018,11 @@
HAL_StatusTypeDef status ;
HAL_HASH_StateTypeDef State_tmp = hhash->State;
-#if defined (HASH_CR_MDMAT)
+ #if defined (HASH_CR_MDMAT)
/* Make sure the input buffer size (in bytes) is a multiple of 4 when MDMAT bit is set
(case of multi-buffer HASH processing) */
assert_param(IS_HASH_DMA_MULTIBUFFER_SIZE(Size));
-#endif /* MDMA defined*/
+ #endif /* MDMA defined*/
/* If State is ready or suspended, start or resume polling-based HASH processing */
if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
@@ -3446,7 +3501,7 @@
/* Enable the DMA In DMA channel */
status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \
(((inputSize % 4U) != 0U) ? ((inputSize + (4U - (inputSize % 4U))) / 4U) \
- : (inputSize / 4U)));
+ : (inputSize / 4U)));
/* Enable DMA requests */
SET_BIT(HASH->CR, HASH_CR_DMAE);
diff --git a/Src/stm32l4xx_hal_hcd.c b/Src/stm32l4xx_hal_hcd.c
index b5dda20..9ba9c4f 100644
--- a/Src/stm32l4xx_hal_hcd.c
+++ b/Src/stm32l4xx_hal_hcd.c
@@ -163,13 +163,25 @@
__HAL_HCD_DISABLE(hhcd);
/* Init the Core (common init.) */
- (void)USB_CoreInit(hhcd->Instance, hhcd->Init);
+ if (USB_CoreInit(hhcd->Instance, hhcd->Init) != HAL_OK)
+ {
+ hhcd->State = HAL_HCD_STATE_ERROR;
+ return HAL_ERROR;
+ }
- /* Force Host Mode*/
- (void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE);
+ /* Force Host Mode */
+ if (USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE) != HAL_OK)
+ {
+ hhcd->State = HAL_HCD_STATE_ERROR;
+ return HAL_ERROR;
+ }
/* Init Host */
- (void)USB_HostInit(hhcd->Instance, hhcd->Init);
+ if (USB_HostInit(hhcd->Instance, hhcd->Init) != HAL_OK)
+ {
+ hhcd->State = HAL_HCD_STATE_ERROR;
+ return HAL_ERROR;
+ }
hhcd->State = HAL_HCD_STATE_READY;
diff --git a/Src/stm32l4xx_hal_i2c.c b/Src/stm32l4xx_hal_i2c.c
index 447c645..88cc084 100644
--- a/Src/stm32l4xx_hal_i2c.c
+++ b/Src/stm32l4xx_hal_i2c.c
@@ -1288,7 +1288,7 @@
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
+ hi2c->XferSize = 1U;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
I2C_GENERATE_START_READ);
}
@@ -1778,7 +1778,7 @@
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
+ hi2c->XferSize = 1U;
xfermode = I2C_RELOAD_MODE;
}
else
@@ -2127,7 +2127,7 @@
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
+ hi2c->XferSize = 1U;
xfermode = I2C_RELOAD_MODE;
}
else
@@ -2674,7 +2674,7 @@
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
+ hi2c->XferSize = 1U;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
I2C_GENERATE_START_READ);
}
@@ -2712,7 +2712,7 @@
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
+ hi2c->XferSize = 1U;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
I2C_NO_STARTSTOP);
}
@@ -4983,7 +4983,15 @@
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
+ /* Errata workaround 170323 */
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ {
+ hi2c->XferSize = 1U;
+ }
+ else
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ }
I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
@@ -5138,7 +5146,15 @@
{
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
+ /* Errata workaround 170323 */
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ {
+ hi2c->XferSize = 1U;
+ }
+ else
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ }
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
@@ -5172,7 +5188,15 @@
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
+ /* Errata workaround 170323 */
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ {
+ hi2c->XferSize = 1U;
+ }
+ else
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ }
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
@@ -5393,7 +5417,15 @@
/* Prepare the new XferSize to transfer */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
+ /* Errata workaround 170323 */
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ {
+ hi2c->XferSize = 1U;
+ }
+ else
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ }
xfermode = I2C_RELOAD_MODE;
}
else
@@ -5541,7 +5573,15 @@
/* Prepare the new XferSize to transfer */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
+ /* Errata workaround 170323 */
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ {
+ hi2c->XferSize = 1U;
+ }
+ else
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ }
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
@@ -5588,7 +5628,15 @@
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
+ /* Errata workaround 170323 */
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ {
+ hi2c->XferSize = 1U;
+ }
+ else
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ }
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
@@ -6814,7 +6862,15 @@
/* Set the XferSize to transfer */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
+ /* Errata workaround 170323 */
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ {
+ hi2c->XferSize = 1U;
+ }
+ else
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ }
}
else
{
diff --git a/Src/stm32l4xx_hal_pcd.c b/Src/stm32l4xx_hal_pcd.c
index 49707ac..d66eee0 100644
--- a/Src/stm32l4xx_hal_pcd.c
+++ b/Src/stm32l4xx_hal_pcd.c
@@ -201,8 +201,12 @@
return HAL_ERROR;
}
- /* Force Device Mode*/
- (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE);
+ /* Force Device Mode */
+ if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
+ {
+ hpcd->State = HAL_PCD_STATE_ERROR;
+ return HAL_ERROR;
+ }
/* Init endpoints structures */
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
diff --git a/Src/stm32l4xx_ll_tim.c b/Src/stm32l4xx_ll_tim.c
index 1ce1776..ef0badb 100644
--- a/Src/stm32l4xx_ll_tim.c
+++ b/Src/stm32l4xx_ll_tim.c
@@ -66,8 +66,8 @@
|| ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
|| ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
|| ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
- || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
- || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
+ || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2))
#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
|| ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
diff --git a/Src/stm32l4xx_ll_usb.c b/Src/stm32l4xx_ll_usb.c
index e50e787..5277d97 100644
--- a/Src/stm32l4xx_ll_usb.c
+++ b/Src/stm32l4xx_ll_usb.c
@@ -229,9 +229,9 @@
do
{
- HAL_Delay(1U);
- ms++;
- } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < 50U));
+ HAL_Delay(10U);
+ ms += 10U;
+ } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
}
else if (mode == USB_DEVICE_MODE)
{
@@ -239,16 +239,16 @@
do
{
- HAL_Delay(1U);
- ms++;
- } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < 50U));
+ HAL_Delay(10U);
+ ms += 10U;
+ } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
}
else
{
return HAL_ERROR;
}
- if (ms == 50U)
+ if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS)
{
return HAL_ERROR;
}
