Release v1.11.1
diff --git a/Inc/stm32l4xx_hal_cortex.h b/Inc/stm32l4xx_hal_cortex.h
index d33e71d..64f140b 100644
--- a/Inc/stm32l4xx_hal_cortex.h
+++ b/Inc/stm32l4xx_hal_cortex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/Inc/stm32l4xx_hal_rtc_ex.h b/Inc/stm32l4xx_hal_rtc_ex.h
index 67032c1..171a4bf 100644
--- a/Inc/stm32l4xx_hal_rtc_ex.h
+++ b/Inc/stm32l4xx_hal_rtc_ex.h
@@ -417,7 +417,7 @@
#define RTC_IT_TAMP2 TAMP_IER_TAMP2IE /*!< Tamper 2 Interrupt */
#define RTC_IT_TAMP3 TAMP_IER_TAMP3IE /*!< Tamper 3 Interrupt */
#define RTC_IT_TAMP (TAMP_IER_TAMP1IE | TAMP_IER_TAMP2IE | TAMP_IER_TAMP3IE) /*!< Enable all Tamper Interrupt */
-#else
+#else
#define RTC_IT_TAMP RTC_TAMPCR_TAMPIE /*!< Enable all Tamper Interrupt */
#define RTC_IT_TAMP1 RTC_TAMPCR_TAMP1IE /*!< Enable Tamper 1 Interrupt */
#define RTC_IT_TAMP2 RTC_TAMPCR_TAMP2IE /*!< Enable Tamper 2 Interrupt */
@@ -440,7 +440,7 @@
#define RTC_FLAG_TAMP2F TAMP_SR_TAMP2F
#define RTC_FLAG_TAMP3F TAMP_SR_TAMP3F
#define RTC_FLAG_TAMPALL (RTC_FLAG_TAMP1F | RTC_FLAG_TAMP2F | RTC_FLAG_TAMP3F)
-#else
+#else
#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F
#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F
#define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F
@@ -1594,7 +1594,6 @@
/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
* @{
*/
-//#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR1_IM18 /*!< External interrupt line 18 Connected to the RTC Alarm event */
#if defined (STM32L4P5xx) || defined (STM32L4Q5xx)
#define RTC_EXTI_LINE_SSRU_EVENT EXTI_IMR1_IM18 /*!< External interrupt line 18 Connected to the RTC SSR Underflow event */
#endif
diff --git a/Inc/stm32l4xx_hal_smbus.h b/Inc/stm32l4xx_hal_smbus.h
index 9871c85..66fad3a 100644
--- a/Inc/stm32l4xx_hal_smbus.h
+++ b/Inc/stm32l4xx_hal_smbus.h
@@ -132,7 +132,11 @@
* @brief SMBUS handle Structure definition
* @{
*/
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
typedef struct __SMBUS_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
{
I2C_TypeDef *Instance; /*!< SMBUS registers base address */
@@ -326,6 +330,7 @@
#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
+#define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE))
#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
@@ -582,11 +587,12 @@
((REQUEST) == SMBUS_NO_STARTSTOP))
-#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
+#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
((REQUEST) == SMBUS_FIRST_FRAME) || \
((REQUEST) == SMBUS_NEXT_FRAME) || \
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
diff --git a/Inc/stm32l4xx_ll_cortex.h b/Inc/stm32l4xx_ll_cortex.h
index 0a84990..2cb0a88 100644
--- a/Inc/stm32l4xx_ll_cortex.h
+++ b/Inc/stm32l4xx_ll_cortex.h
@@ -21,29 +21,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/Inc/stm32l4xx_ll_utils.h b/Inc/stm32l4xx_ll_utils.h
index 5db2e3a..bb0f3b8 100644
--- a/Inc/stm32l4xx_ll_utils.h
+++ b/Inc/stm32l4xx_ll_utils.h
@@ -297,6 +297,7 @@
*/
void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
+ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency);
ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
diff --git a/README.md b/README.md
index 7ed073b..32815d9 100644
--- a/README.md
+++ b/README.md
@@ -36,6 +36,9 @@
------------- | --------------- | ---------- | -------------------------------------
Tag v1.10.0 | Tag v1.5.1 | Tag v5.4.0_cm4 | Tag v1.14.0 (and following, if any, till next new tag)
Tag v1.11.0 | Tag v1.6.0 | Tag v5.4.0_cm4 | Tag v1.15.0 (and following, if any, till next new tag)
+Tag v1.11.1 | Tag v1.6.1 | Tag v5.4.0_cm4 | Tag v1.15.1 (and following, if any, till next new tag)
+
+Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/stm32l4xx_hal_driver/blob/master/Release_Notes.html).
The full **STM32CubeL4** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeL4).
diff --git a/Release_Notes.html b/Release_Notes.html
index 31e2183..bc56f54 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -46,10 +46,57 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section26" checked aria-hidden="true"> <label for="collapse-section26" aria-hidden="true">V1.11.0 / 22-November-2019</label>
+<input type="checkbox" id="collapse-section27" checked aria-hidden="true"> <label for="collapse-section27" aria-hidden="true">V1.11.1 / 07-February-2020</label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
+<li>Patch release of <strong>HAL and Low Layer</strong> drivers to include latest corrections</li>
+</ul>
+<h2 id="contents">Contents</h2>
+<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
+<ul>
+<li><strong>HAL GPIO</strong> driver
+<ul>
+<li>Update <em>HAL_GPIO_Init()</em> initialization sequence to modify the order of GPIO registers update</li>
+</ul></li>
+<li><strong>HAL I2C</strong> driver
+<ul>
+<li>Update <em>I2C_Enable_IRQ()</em> function to remove incorrect interrupts enable when InterruptRequest = I2C_XFER_CPLT_IT</li>
+<li>Update <em>I2C_DMAXferCplt()</em>, <em>I2C_DMAError()</em> and <em>I2C_DMAAbort()</em> functions to avoid null pointer exceptions</li>
+<li>Update <em>HAL_I2C_Master_Seq_Transmit/Receive_IT/DMA()</em> functions to set correct condition range</li>
+<li>Update <em>I2C_ITMasterCplt()</em> to remove C++ compilation warning due to unused variable</li>
+</ul></li>
+<li><strong>HAL RTC</strong> driver
+<ul>
+<li>Correct MISRA C:2012-Rule-3.1 warning in RTC driver</li>
+</ul></li>
+<li><strong>HAL SDMMC</strong> driver
+<ul>
+<li>Update <em>MMC_InitCard()</em> function to add missing correction for eMMC card size computation issue</li>
+<li>Update <em>SD_UltraHighSpeed()</em> and <em>SD_DDR_Mode()</em> functions to remove useless assignment</li>
+<li>Correct MISRA C:2012 warnings in SDMMC driver (rules 10.4_a, 10.7, 13.5, 15.7, 2.2_c)</li>
+</ul></li>
+<li><strong>HAL SMBUS</strong> driver
+<ul>
+<li>Update IS_SMBUS_TRANSFER_OPTIONS_REQUEST macro definition to include transfers with PEC</li>
+<li>Correct MISRA C:2012-Rule-2.4 warning in structure __SMBUS_HandleTypeDef definition</li>
+</ul></li>
+</ul>
+<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">LL drivers changes</span></span></strong></p>
+<ul>
+<li><strong>LL UTILS</strong> driver
+<ul>
+<li>Change private <em>UTILS_SetFlashLatency()</em> function into <em>LL_SetFlashLatency()</em> public function</li>
+<li>Update <em>LL_PLL_ConfigSystemClock_MSI/HSI/HSE()</em> functions to set expected AHB prescaler value</li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section26" aria-hidden="true"> <label for="collapse-section26" aria-hidden="true">V1.11.0 / 22-November-2019</label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
<li>Release of <strong>HAL and Low Layer</strong> drivers to add support of <strong>STM32L4P5xx/STM32L4Q5xx</strong> devices
<ul>
<li>New <strong>PKA</strong> and <strong>PSSI</strong> peripherals supported in <strong>new HAL/LL PKA</strong> and <strong>HAL PSSI</strong> drivers</li>
@@ -58,6 +105,7 @@
</li>
<li>Correction of several issues applicable to other devices</li>
</ul>
+<h2 id="contents-1">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<ul>
<li><strong>HAL</strong> driver
@@ -397,10 +445,11 @@
<div class="collapse">
<input type="checkbox" id="collapse-section22" aria-hidden="true"> <label for="collapse-section22" aria-hidden="true">V1.10.0 / 03-April-2019</label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
<ul>
<li>Delivery of the new HAL MMC driver</li>
</ul>
+<h2 id="contents-2">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<ul>
<li><strong>HAL ADC</strong> driver
@@ -688,12 +737,13 @@
<div class="collapse">
<input type="checkbox" id="collapse-section21" aria-hidden="true"> <label for="collapse-section21" aria-hidden="true">V1.9.0 / 27-July-2018</label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
<ul>
<li>Release of <strong>HAL and Low Layer drivers</strong> to add support of <strong>STM32L412xx/STM32L422xx</strong></li>
<li>Superset features device STM32L422xx API User Manual available (STM32L422xx_User_Manual.chm) </li>
<li>MISRA C:2012 corrections</li>
</ul>
+<h2 id="contents-3">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<p>MISRA C:2012 corrections listed hereafter are applicable to LL driver as well.</p>
<ul>
@@ -879,7 +929,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section19" aria-hidden="true"> <label for="collapse-section19" aria-hidden="true">V1.8.3 / 22-May-2018</label>
<div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
<p>Maintenance Release of <strong>HAL and Low Layer drivers</strong></p>
<p><strong>Add support of HAL callback registration feature</strong></p>
<ul>
@@ -889,6 +939,7 @@
<li><p>Once enabled, the user application may resort to HAL_PPP_RegisterCallback() to register specific callback function(s) and unregister it(them) with HAL_PPP_UnRegisterCallback().</p></li>
</ul>
<p>MISRAC-2012 corrections</p>
+<h2 id="contents-4">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<ul>
<li><p><strong>HAL generic</strong> driver</p>
@@ -1236,10 +1287,11 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.8.2 / 22-December-2017</label>
<div>
-<h2 id="main-changes-4">Main Changes</h2>
+<h2 id="main-changes-5">Main Changes</h2>
<ul>
<li>Maintenance Release of <strong>HAL and Low Layer drivers</strong></li>
</ul>
+<h2 id="contents-5">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<ul>
<li><strong>HAL CAN</strong> driver</li>
@@ -1317,10 +1369,11 @@
<div class="collapse">
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">V1.8.1 / 13-October-2017</label>
<div>
-<h2 id="main-changes-5">Main Changes</h2>
+<h2 id="main-changes-6">Main Changes</h2>
<ul>
<li>Maintenance Release of <strong>HAL and Low Layer drivers</strong></li>
</ul>
+<h2 id="contents-6">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<ul>
<li><p><strong>HAL generic</strong> driver</p>
@@ -1398,13 +1451,14 @@
<div class="collapse">
<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">V1.8.0 / 25-August-2017</label>
<div>
-<h2 id="main-changes-6">Main Changes</h2>
+<h2 id="main-changes-7">Main Changes</h2>
<ul>
<li><p>Release of <strong>HAL and Low Layer drivers</strong> to add support of <strong>STM32L4R5xx/STM32L4R7xx/STM32L4R9xx/STM32L4S5xx/STM32L4S7xx/STM32L4S9xx</strong> devices</p></li>
<li><p>New OctoSPI, DSI, LTDC, GFXMMU peripherals supported in <strong>new HAL OSPI, HAL DSI, HAL LTDC</strong> and <strong>HAL GFXMMU</strong> drivers</p></li>
<li><p>Superset features device STM32L4S9xx API User Manual available (STM32L4S9xx_User_Manual.chm) </p></li>
</ul>
-<p> <strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
+<p> ## Contents</p>
+<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<ul>
<li><strong>HAL DSI</strong> driver <strong>(NEW)</strong>: stm32l4xx_hal_dsi.h/.c files</li>
<li><strong>HAL GFXMMU</strong> driver <strong>(NEW)</strong>:stm32l4xx_hal_gfxmmu.h/.c files</li>
@@ -1654,10 +1708,11 @@
<div class="collapse">
<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">V1.7.2 / 16-June-2017</label>
<div>
-<h2 id="main-changes-7">Main Changes</h2>
+<h2 id="main-changes-8">Main Changes</h2>
<ul>
<li>Maintenance Release of <strong>HAL and Low Layer drivers</strong></li>
</ul>
+<h2 id="contents-7">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<ul>
<li><p><strong>HAL CAN</strong> driver</p>
@@ -1709,10 +1764,11 @@
<div class="collapse">
<input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true">V1.7.1 / 21-April-2017</label>
<div>
-<h2 id="main-changes-8">Main Changes</h2>
+<h2 id="main-changes-9">Main Changes</h2>
<ul>
<li>Maintenance Release of <strong>HAL and Low Layer drivers</strong></li>
</ul>
+<h2 id="contents-8">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<ul>
<li><p><strong>HAL generic</strong> driver</p>
@@ -1752,7 +1808,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true">V1.7.0 / 17-February-2017</label>
<div>
-<h2 id="main-changes-9">Main Changes</h2>
+<h2 id="main-changes-10">Main Changes</h2>
<ul>
<li>Release of <strong>HAL and Low Layer drivers</strong> to add support of <strong>STM32L496xx/STM32L4A6xx</strong> devices</li>
<li>New DCMI, DMA2D, HASH peripherals supported in <strong>new HAL DCMI, HAL & LL DMA2D and HAL HASH</strong> drivers</li>
@@ -1761,6 +1817,7 @@
<li>Superset features device STM32L4A6xx API User Manual available (STM32L4A6xx_User_Manual.chm) <br />
</li>
</ul>
+<h2 id="contents-9">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<ul>
<li><strong>HAL DCMI</strong> driver <strong>(NEW)</strong>: stm32l4xx_hal_dcmi.h/.c files</li>
@@ -1860,11 +1917,12 @@
<div class="collapse">
<input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true">V1.6.0 / 28-October-2016</label>
<div>
-<h2 id="main-changes-10">Main Changes</h2>
+<h2 id="main-changes-11">Main Changes</h2>
<ul>
<li>Release of <strong>HAL and Low Layer drivers</strong> to add support of <strong>STM32L451xx/STM32L452xx/STM32L462xx</strong> devices</li>
<li>Superset features device STM32L462xx API User Manual available (STM32L462xx_User_Manual.chm)</li>
</ul>
+<h2 id="contents-10">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<ul>
<li><p><strong>HAL CRYP</strong> driver</p>
@@ -1924,6 +1982,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true">V1.5.2 / 12-September-2016</label>
<div>
+<h2 id="contents-11">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<ul>
<li><p><strong>HAL ADC</strong> driver</p>
@@ -2015,6 +2074,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true">V1.5.1 / 31-May-2016</label>
<div>
+<h2 id="contents-12">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<ul>
<li><p><strong>HAL ADC</strong> driver</p>
@@ -2042,10 +2102,11 @@
<div class="collapse">
<input type="checkbox" id="collapse-section13" aria-hidden="true"> <label for="collapse-section13" aria-hidden="true">V1.5.0 / 29-April-2016</label>
<div>
-<h2 id="main-changes-11">Main Changes</h2>
+<h2 id="main-changes-12">Main Changes</h2>
<ul>
<li>Maintenance Release of <strong>HAL and Low Layer drivers</strong></li>
</ul>
+<h2 id="contents-13">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<p>Enhance HAL delay and timebase implementation</p>
<ul>
@@ -2225,7 +2286,7 @@
<li>Update initialization sequence in voltage class B</li>
</ul></li>
</ul>
-<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
+<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">LL drivers changes</span></span></strong></p>
<ul>
<li><strong>LL ADC</strong> driver
<ul>
@@ -2291,7 +2352,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section14" aria-hidden="true"> <label for="collapse-section14" aria-hidden="true">V1.4.0 / 26-February-2016</label>
<div>
-<h2 id="main-changes-12">Main Changes</h2>
+<h2 id="main-changes-13">Main Changes</h2>
<ul>
<li>Release of <strong>HAL and Low Layer drivers</strong> to add support of <strong>STM32L431xx/STM32L432xx/STM32L433xx/STM32L442xx/STM32L443xx</strong> devices</li>
<li><strong>Low Layer driver initialization/de-initialization APIs</strong> applicable to all STM32L4xx devices</li>
@@ -2299,6 +2360,7 @@
<li>Superset features device STM32L443xx API User Manual available (STM32L443xx_User_Manual.chm) <br />
</li>
</ul>
+<h2 id="contents-14">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<ul>
<li><p><strong>HAL</strong> generic update</p>
@@ -2315,9 +2377,11 @@
</ul></li>
</ul>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">LL drivers changes</span></span></strong></p>
-<p>New C files requiring to use USE_FULL_LL_DRIVER compilation switch in user project to benefit from new APIs</p>
<ul>
-<li><p>stm32l4xx_ll_crs.c</p></li>
+<li>New C files requiring to use USE_FULL_LL_DRIVER compilation switch in user project to benefit from new APIs
+<ul>
+<li>stm32l4xx_ll_crs.c</li>
+</ul></li>
<li><strong>LL BUS</strong> update
<ul>
<li>Add read-back register on clock enable functions to take into account any delay on bus</li>
@@ -2360,15 +2424,20 @@
<div class="collapse">
<input type="checkbox" id="collapse-section15" aria-hidden="true"> <label for="collapse-section15" aria-hidden="true">V1.3.0 / 29-January-2016</label>
<div>
-<h2 id="main-changes-13">Main Changes</h2>
-<p><strong>New Low Layer driver initialization/de-initialization APIs</strong></p>
-<p>Naming rule is LL_PPP_Init(), LL_PPP_StructInit(), LL_PPP_DeInit() and more initialization APIs when applicable for peripheral PPP: ADC, COMP, CRC, DAC, DMA, EXTI, GPIO, I2C, LPTIM, LPUART, OPAMP, PWR, RCC, RNG, RTC, SPI, SWPMI, TIM and USART. </p>
-<p>New C files requiring to use USE_FULL_LL_DRIVER compilation switch in user project to benefit from new APIs</p>
+<h2 id="main-changes-14">Main Changes</h2>
+<ul>
+<li><strong>New Low Layer driver initialization/de-initialization APIs</strong>
+<ul>
+<li>Naming rule is LL_PPP_Init(), LL_PPP_StructInit(), LL_PPP_DeInit() and more initialization APIs when applicable for peripheral PPP: ADC, COMP, CRC, DAC, DMA, EXTI, GPIO, I2C, LPTIM, LPUART, OPAMP, PWR, RCC, RNG, RTC, SPI, SWPMI, TIM and USART. </li>
+</ul></li>
+<li>New C files requiring to use USE_FULL_LL_DRIVER compilation switch in user project to benefit from new APIs
<ul>
<li>stm32l4xx_ll_adc.c, stm32l4xx_ll_comp.c, stm32l4xx_ll_crc.c, stm32l4xx_ll_dac.c, stm32l4xx_ll_dma.c, stm32l4xx_ll_exti.c, stm32l4xx_ll_gpio.c, stm32l4xx_ll_i2c.c, stm32l4xx_ll_lptim.c, stm32l4xx_ll_lpuart.c, stm32l4xx_ll_opamp.c, stm32l4xx_ll_pwr.c, stm32l4xx_ll_rcc.c, stm32l4xx_ll_rng.c, stm32l4xx_ll_rtc.c, stm32l4xx_ll_spi.c, stm32l4xx_ll_swpmi.c, stm32l4xx_ll_tim.c and stm32l4xx_ll_usart.c</li>
<li>stm32l4xx_ll_utils.c contains some Low Layer utilities for SysTick, Flash latency and clock configuration. </li>
+</ul></li>
+<li>Fix "parameter unused" GCC compilation warnings on __weak functions</li>
</ul>
-<p>Fix "parameter unused" GCC compilation warnings on __weak functions</p>
+<h2 id="contents-15">Contents</h2>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL drivers changes</span></span></strong></p>
<ul>
<li><p><strong>HAL generic</strong> update</p>
@@ -2516,7 +2585,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section16" aria-hidden="true"> <label for="collapse-section16" aria-hidden="true">V1.2.0 / 25-November-2015</label>
<div>
-<h2 id="main-changes-14">Main Changes</h2>
+<h2 id="main-changes-15">Main Changes</h2>
<ul>
<li><strong>HAL generic</strong> update
<ul>
@@ -2573,7 +2642,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section17" aria-hidden="true"> <label for="collapse-section17" aria-hidden="true">V1.1.1 / 16-October-2015</label>
<div>
-<h2 id="main-changes-15">Main Changes</h2>
+<h2 id="main-changes-16">Main Changes</h2>
<ul>
<li><p><strong>HAL generic</strong> update</p>
<ul>
@@ -2603,13 +2672,16 @@
<div class="collapse">
<input type="checkbox" id="collapse-section20" aria-hidden="true"> <label for="collapse-section20" aria-hidden="true">V1.1.0 / 26-September-2015</label>
<div>
-<h2 id="main-changes-16">Main Changes</h2>
+<h2 id="main-changes-17">Main Changes</h2>
<p><strong>Add Low Layer drivers allowing performance and footprint optimization</strong></p>
<ul>
<li>Low Layer drivers APIs provide register level programming: they require deep knowledge of peripherals described in STM32L4x6 Reference Manual</li>
<li><p>Low Layer drivers are available for: ADC, COMP, Cortex, CRC, DAC, DMA, EXTI, GPIO, I2C, IWDG, LPYIM, LPUART, OPAMP, PWR, RCC, RNG, RTC, SPI, SWPMI, TIM, USART, WWDG peripherals and additionnal Low Level Bus, System and Utilities APIs.<br />
</p></li>
<li><p>Low Layer drivers APIs are implemented as static inline function in new Inc/stm32l4xx_ll_ppp.h files for PPP peripherals, there is no configuration file and each stm32l4xx_ll_ppp.h file must be included in user code.</p></li>
+</ul>
+<h2 id="contents-16">Contents</h2>
+<ul>
<li><p><strong>HAL ADC</strong> update</p>
<ul>
<li>Channel 5 is not usable for ADC3</li>
@@ -2673,7 +2745,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section18" aria-hidden="true"> <label for="collapse-section18" aria-hidden="true">V1.0.0 / 26-June-2015</label>
<div>
-<h2 id="main-changes-17">Main Changes</h2>
+<h2 id="main-changes-18">Main Changes</h2>
<ul>
<li>First official release of <strong>STM32L4xx HAL Drivers</strong> for <strong>STM32L471xx/STM32L475xx/STM32L476xx/STM32L485xx</strong> and <strong>STM32L486xx</strong> devices</li>
</ul>
diff --git a/Src/stm32l4xx_hal.c b/Src/stm32l4xx_hal.c
index 5ff687d..e9e30ae 100644
--- a/Src/stm32l4xx_hal.c
+++ b/Src/stm32l4xx_hal.c
@@ -53,7 +53,7 @@
*/
#define STM32L4XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define STM32L4XX_HAL_VERSION_SUB1 (0x0BU) /*!< [23:16] sub1 version */
-#define STM32L4XX_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
+#define STM32L4XX_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define STM32L4XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define STM32L4XX_HAL_VERSION ((STM32L4XX_HAL_VERSION_MAIN << 24U)\
|(STM32L4XX_HAL_VERSION_SUB1 << 16U)\
diff --git a/Src/stm32l4xx_hal_cortex.c b/Src/stm32l4xx_hal_cortex.c
index c9e8780..149d4ba 100644
--- a/Src/stm32l4xx_hal_cortex.c
+++ b/Src/stm32l4xx_hal_cortex.c
@@ -90,29 +90,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -161,7 +145,7 @@
/**
* @brief Set the priority grouping field (pre-emption priority and subpriority)
* using the required unlock sequence.
- * @param PriorityGroup The priority grouping bits length.
+ * @param PriorityGroup: The priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
* 4 bits for subpriority
@@ -188,13 +172,13 @@
/**
* @brief Set the priority of an interrupt.
- * @param IRQn External interrupt number.
+ * @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
- * @param PreemptPriority The pre-emption priority for the IRQn channel.
+ * @param PreemptPriority: The pre-emption priority for the IRQn channel.
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority
- * @param SubPriority the subpriority level for the IRQ channel.
+ * @param SubPriority: the subpriority level for the IRQ channel.
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
@@ -259,7 +243,7 @@
/**
* @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
* Counter is in free running mode to generate periodic interrupts.
- * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
+ * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
@@ -299,7 +283,7 @@
/**
* @brief Get the priority of an interrupt.
- * @param IRQn External interrupt number.
+ * @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
* @param PriorityGroup: the priority grouping bits length.
@@ -314,8 +298,8 @@
* 1 bit for subpriority
* @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
* 0 bit for subpriority
- * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
- * @param pSubPriority Pointer on the Subpriority value (starting from 0).
+ * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
+ * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
* @retval None
*/
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
@@ -392,7 +376,7 @@
/**
* @brief Configure the SysTick clock source.
- * @param CLKSource specifies the SysTick clock source.
+ * @param CLKSource: specifies the SysTick clock source.
* This parameter can be one of the following values:
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
@@ -435,7 +419,7 @@
#if (__MPU_PRESENT == 1)
/**
* @brief Enable the MPU.
- * @param MPU_Control Specifies the control mode of the MPU during hard fault,
+ * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
* NMI, FAULTMASK and privileged accessto the default memory
* This parameter can be one of the following values:
* @arg MPU_HFNMI_PRIVDEF_NONE
@@ -471,7 +455,7 @@
/**
* @brief Initialize and configure the Region and the memory to be protected.
- * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
+ * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
* the initialization and configuration information.
* @retval None
*/
diff --git a/Src/stm32l4xx_hal_gpio.c b/Src/stm32l4xx_hal_gpio.c
index 412be3d..7454bec 100644
--- a/Src/stm32l4xx_hal_gpio.c
+++ b/Src/stm32l4xx_hal_gpio.c
@@ -190,26 +190,6 @@
if (iocurrent != 0x00u)
{
/*--------------------- GPIO Mode Configuration ------------------------*/
- /* In case of Alternate function mode selection */
- if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- {
- /* Check the Alternate function parameters */
- assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
- assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
-
- /* Configure Alternate function mapped with the current IO */
- temp = GPIOx->AFR[position >> 3u];
- temp &= ~(0xFu << ((position & 0x07u) * 4u));
- temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
- GPIOx->AFR[position >> 3u] = temp;
- }
-
- /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
- temp = GPIOx->MODER;
- temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
- temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
- GPIOx->MODER = temp;
-
/* In case of Output or Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
@@ -249,6 +229,26 @@
temp |= ((GPIO_Init->Pull) << (position * 2u));
GPIOx->PUPDR = temp;
+ /* In case of Alternate function mode selection */
+ if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ {
+ /* Check the Alternate function parameters */
+ assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
+ /* Configure Alternate function mapped with the current IO */
+ temp = GPIOx->AFR[position >> 3u];
+ temp &= ~(0xFu << ((position & 0x07u) * 4u));
+ temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
+ GPIOx->AFR[position >> 3u] = temp;
+ }
+
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+ temp = GPIOx->MODER;
+ temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
+ temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
+ GPIOx->MODER = temp;
+
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
diff --git a/Src/stm32l4xx_hal_i2c.c b/Src/stm32l4xx_hal_i2c.c
index 40afa7f..5ea8fd3 100644
--- a/Src/stm32l4xx_hal_i2c.c
+++ b/Src/stm32l4xx_hal_i2c.c
@@ -351,13 +351,13 @@
/* Private define to centralize the enable/disable of Interrupts */
-#define I2C_XFER_TX_IT (0x00000001U)
-#define I2C_XFER_RX_IT (0x00000002U)
-#define I2C_XFER_LISTEN_IT (0x00000004U)
+#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */
-#define I2C_XFER_ERROR_IT (0x00000011U)
-#define I2C_XFER_CPLT_IT (0x00000012U)
-#define I2C_XFER_RELOAD_IT (0x00000012U)
+#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error and NACK treatment */
+#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */
+#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */
/* Private define Sequential Transfer Options default/reset value */
#define I2C_NO_OPTION_FRAME (0xFFFF0000U)
@@ -410,6 +410,9 @@
static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+/* Private function to treat different error callback */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
+
/* Private function to flush TXDR register */
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
@@ -3200,7 +3203,7 @@
I2C_ConvertOtherXferOptions(hi2c);
/* Update xfermode accordingly if no reload is necessary */
- if (hi2c->XferCount < MAX_NBYTE_SIZE)
+ if (hi2c->XferCount <= MAX_NBYTE_SIZE)
{
xfermode = hi2c->XferOptions;
}
@@ -3285,7 +3288,7 @@
I2C_ConvertOtherXferOptions(hi2c);
/* Update xfermode accordingly if no reload is necessary */
- if (hi2c->XferCount < MAX_NBYTE_SIZE)
+ if (hi2c->XferCount <= MAX_NBYTE_SIZE)
{
xfermode = hi2c->XferOptions;
}
@@ -3446,7 +3449,7 @@
I2C_ConvertOtherXferOptions(hi2c);
/* Update xfermode accordingly if no reload is necessary */
- if (hi2c->XferCount < MAX_NBYTE_SIZE)
+ if (hi2c->XferCount <= MAX_NBYTE_SIZE)
{
xfermode = hi2c->XferOptions;
}
@@ -3531,7 +3534,7 @@
I2C_ConvertOtherXferOptions(hi2c);
/* Update xfermode accordingly if no reload is necessary */
- if (hi2c->XferCount < MAX_NBYTE_SIZE)
+ if (hi2c->XferCount <= MAX_NBYTE_SIZE)
{
xfermode = hi2c->XferOptions;
}
@@ -4251,9 +4254,21 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Disable Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
- I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+ /* Disable Interrupts and Store Previous state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ }
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
/* Set State at HAL_I2C_STATE_ABORT */
hi2c->State = HAL_I2C_STATE_ABORT;
@@ -5001,6 +5016,7 @@
{
uint32_t tmpoptions = hi2c->XferOptions;
uint32_t treatdmanack = 0U;
+ HAL_I2C_StateTypeDef tmpstate;
/* Process locked */
__HAL_LOCK(hi2c);
@@ -5079,8 +5095,24 @@
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
+ tmpstate = hi2c->State;
+
if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
{
+ if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+ {
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+ }
+ else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ {
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
}
@@ -5369,9 +5401,27 @@
*/
static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
{
+ uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+
/* Reset I2C handle mode */
hi2c->Mode = HAL_I2C_MODE_NONE;
+ /* If a DMA is ongoing, Update handle size context */
+ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+ {
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+ }
+ else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+ {
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
{
/* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
@@ -5426,19 +5476,36 @@
static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
uint32_t tmperror;
+ uint32_t tmpITFlags = ITFlags;
+ __IO uint32_t tmpreg;
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ /* Disable Interrupts and Store Previous state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ }
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
/* Reset handle parameters */
- hi2c->PreviousState = I2C_STATE_NONE;
hi2c->XferISR = NULL;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET)
+ if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -5447,12 +5514,17 @@
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
+ /* Fetch Last receive data if any */
+ if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
+ {
+ /* Read data from RXDR */
+ tmpreg = (uint8_t)hi2c->Instance->RXDR;
+ UNUSED(tmpreg);
+ }
+
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
- /* Disable Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT);
-
/* Store current volatile hi2c->ErrorCode, misra rule */
tmperror = hi2c->ErrorCode;
@@ -5466,6 +5538,7 @@
else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
{
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
@@ -5500,6 +5573,7 @@
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
@@ -5546,12 +5620,26 @@
{
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
uint32_t tmpITFlags = ITFlags;
+ HAL_I2C_StateTypeDef tmpstate = hi2c->State;
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- /* Disable all interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
+ /* Disable Interrupts and Store Previous state */
+ if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+ }
+ else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -5565,6 +5653,9 @@
/* If a DMA is ongoing, Update handle size context */
if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
{
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
if (hi2c->hdmatx != NULL)
{
hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx);
@@ -5572,6 +5663,9 @@
}
else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
{
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
if (hi2c->hdmarx != NULL)
{
hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx);
@@ -5608,7 +5702,6 @@
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
- hi2c->PreviousState = I2C_STATE_NONE;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->XferISR = NULL;
@@ -5631,6 +5724,7 @@
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -5646,6 +5740,7 @@
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -5660,6 +5755,7 @@
else
{
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -5733,6 +5829,7 @@
static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
{
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+ uint32_t tmppreviousstate;
/* Reset handle parameters */
hi2c->Mode = HAL_I2C_MODE_NONE;
@@ -5752,7 +5849,6 @@
/* keep HAL_I2C_STATE_LISTEN if set */
hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->PreviousState = I2C_STATE_NONE;
hi2c->XferISR = I2C_Slave_ISR_IT;
}
else
@@ -5767,16 +5863,19 @@
/* Set HAL_I2C_STATE_READY */
hi2c->State = HAL_I2C_STATE_READY;
}
- hi2c->PreviousState = I2C_STATE_NONE;
hi2c->XferISR = NULL;
}
/* Abort DMA TX transfer if any */
- if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ tmppreviousstate = hi2c->PreviousState;
+ if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
{
- hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+ if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+ }
- if (hi2c->hdmatx != NULL)
+ if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
{
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
@@ -5792,13 +5891,20 @@
hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
}
}
+ else
+ {
+ I2C_TreatErrorCallback(hi2c);
+ }
}
/* Abort DMA RX transfer if any */
- else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+ else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
{
- hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+ if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+ }
- if (hi2c->hdmarx != NULL)
+ if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
{
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
@@ -5814,10 +5920,28 @@
hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
}
}
+ else
+ {
+ I2C_TreatErrorCallback(hi2c);
+ }
}
- else if (hi2c->State == HAL_I2C_STATE_ABORT)
+ else
+ {
+ I2C_TreatErrorCallback(hi2c);
+ }
+}
+
+/**
+ * @brief I2C Error callback treatment.
+ * @param hi2c I2C handle.
+ * @retval None
+ */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+ if (hi2c->State == HAL_I2C_STATE_ABORT)
{
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -5831,6 +5955,8 @@
}
else
{
+ hi2c->PreviousState = I2C_STATE_NONE;
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -6041,30 +6167,16 @@
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
/* Reset AbortCpltCallback */
- hi2c->hdmatx->XferAbortCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
-
- /* Check if come from abort from user */
- if (hi2c->State == HAL_I2C_STATE_ABORT)
+ if (hi2c->hdmatx != NULL)
{
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- hi2c->AbortCpltCallback(hi2c);
-#else
- HAL_I2C_AbortCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ hi2c->hdmatx->XferAbortCallback = NULL;
}
- else
+ if (hi2c->hdmarx != NULL)
{
- /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- hi2c->ErrorCallback(hi2c);
-#else
- HAL_I2C_ErrorCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ hi2c->hdmarx->XferAbortCallback = NULL;
}
+
+ I2C_TreatErrorCallback(hi2c);
}
/**
@@ -6341,19 +6453,19 @@
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
- if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
+ if (InterruptRequest == I2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
}
- if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+ if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
- tmpisr |= I2C_IT_STOPI;
+ tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
}
- if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
+ if (InterruptRequest == I2C_XFER_RELOAD_IT)
{
/* Enable TC interrupts */
tmpisr |= I2C_IT_TCI;
@@ -6379,7 +6491,7 @@
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
}
- if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+ if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
@@ -6433,19 +6545,19 @@
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
- if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
+ if (InterruptRequest == I2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
}
- if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+ if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
}
- if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
+ if (InterruptRequest == I2C_XFER_RELOAD_IT)
{
/* Enable TC interrupts */
tmpisr |= I2C_IT_TCI;
diff --git a/Src/stm32l4xx_hal_mmc.c b/Src/stm32l4xx_hal_mmc.c
index f26f893..1d0e057 100644
--- a/Src/stm32l4xx_hal_mmc.c
+++ b/Src/stm32l4xx_hal_mmc.c
@@ -2532,7 +2532,7 @@
{
case SDMMC_SPEED_MODE_AUTO:
{
- if (((device_type & 0x04U) != 0U) && ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS) != 0U))
+ if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS) != 0U) && ((device_type & 0x04U) != 0U))
{
/* High Speed DDR mode allowed */
errorstate = MMC_HighSpeed(hmmc, ENABLE);
@@ -2558,11 +2558,15 @@
hmmc->ErrorCode |= errorstate;
}
}
+ else
+ {
+ /* Nothing to do : keep current speed */
+ }
break;
}
case SDMMC_SPEED_MODE_DDR:
{
- if (((device_type & 0x04U) != 0U) && ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS) != 0U))
+ if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS) != 0U) && ((device_type & 0x04U) != 0U))
{
/* High Speed DDR mode allowed */
errorstate = MMC_HighSpeed(hmmc, ENABLE);
@@ -3022,9 +3026,7 @@
HAL_MMC_CardCSDTypeDef CSD;
uint32_t errorstate;
uint16_t mmc_rca = 1U;
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
MMC_InitTypeDef Init;
-#endif
/* Check the power State */
if(SDMMC_GetPowerState(hmmc->Instance) == 0U)
@@ -3077,23 +3079,6 @@
/* Get the Card Class */
hmmc->MmcCard.Class = (SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2) >> 20U);
-#if !defined(STM32L4P5xx) && !defined(STM32L4Q5xx) && !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
- /* Get CSD parameters */
- if (HAL_MMC_GetCardCSD(hmmc, &CSD) != HAL_OK)
- {
- return hmmc->ErrorCode;
- }
-
- /* Select the Card */
- errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- return errorstate;
- }
-
- /* Configure SDMMC peripheral interface */
- (void)SDMMC_Init(hmmc->Instance, hmmc->Init);
-#else
/* Select the Card */
errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if(errorstate != HAL_MMC_ERROR_NONE)
@@ -3121,7 +3106,6 @@
Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl;
Init.ClockDiv = hmmc->Init.ClockDiv;
(void)SDMMC_Init(hmmc->Instance, Init);
-#endif
/* All cards are initialized */
return HAL_MMC_ERROR_NONE;
@@ -3274,7 +3258,7 @@
tmp_data = SDMMC_ReadFIFO(hmmc->Instance);
/* eg : SEC_COUNT : FieldIndex = 212 => i+count = 53 */
/* DEVICE_TYPE : FieldIndex = 196 => i+count = 49 */
- if ((i + count) == (FieldIndex/4))
+ if ((i + count) == ((uint32_t)FieldIndex/4U))
{
*pFieldData = tmp_data;
}
@@ -3395,16 +3379,16 @@
static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state)
{
uint32_t errorstate = HAL_MMC_ERROR_NONE;
- uint32_t response = 0U, count = 0U;
+ uint32_t response, count;
SDMMC_InitTypeDef Init;
- if ((state == DISABLE) && ((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U))
+ if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U) && (state == DISABLE))
{
/* Index : 185 - Value : 0 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90000U);
}
- if ((state != DISABLE) && ((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) == 0U))
+ if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) == 0U) && (state != DISABLE))
{
/* Index : 185 - Value : 1 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90100U);
@@ -3479,9 +3463,9 @@
static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state)
{
uint32_t errorstate = HAL_MMC_ERROR_NONE;
- uint32_t response = 0U, count = 0U;
+ uint32_t response, count;
- if ((state == DISABLE) && ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U))
+ if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U) && (state == DISABLE))
{
if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U)
{
@@ -3495,7 +3479,7 @@
}
}
- if ((state != DISABLE) && ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U))
+ if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U) && (state != DISABLE))
{
if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U)
{
diff --git a/Src/stm32l4xx_hal_sd.c b/Src/stm32l4xx_hal_sd.c
index ffd204a..80e416e 100644
--- a/Src/stm32l4xx_hal_sd.c
+++ b/Src/stm32l4xx_hal_sd.c
@@ -3556,8 +3556,6 @@
/* Clean Status flags */
hsd->Instance->ICR = 0xFFFFFFFFU;
}
-
- hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED;
}
}
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
@@ -3732,7 +3730,7 @@
*/
static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)
{
- uint32_t scr[2U] = {0U, 0U};
+ uint32_t scr[2U] = {0UL, 0UL};
uint32_t errorstate;
if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
@@ -3779,7 +3777,7 @@
*/
static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)
{
- uint32_t scr[2U] = {0U, 0U};
+ uint32_t scr[2U] = {0UL, 0UL};
uint32_t errorstate;
if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
@@ -3832,7 +3830,7 @@
uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
uint32_t index = 0U;
- uint32_t tempscr[2U] = {0U, 0U};
+ uint32_t tempscr[2U] = {0UL, 0UL};
uint32_t *scr = pSCR;
/* Set Block Size To 8 Bytes */
@@ -4086,8 +4084,6 @@
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
- errorstate = 0;
-
return errorstate;
}
else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
@@ -4201,8 +4197,6 @@
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
- errorstate = 0;
-
return errorstate;
}
else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
@@ -4332,8 +4326,6 @@
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
- errorstate = 0;
-
return errorstate;
}
else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
diff --git a/Src/stm32l4xx_hal_smbus.c b/Src/stm32l4xx_hal_smbus.c
index 29618a0..fa269e9 100644
--- a/Src/stm32l4xx_hal_smbus.c
+++ b/Src/stm32l4xx_hal_smbus.c
@@ -203,18 +203,18 @@
/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
* @{
*/
-static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
-static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
-static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
-static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
+static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
+static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
+static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
+static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
-static void SMBUS_ConvertOtherXferOptions(struct __SMBUS_HandleTypeDef *hsmbus);
+static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
-static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus);
+static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus);
-static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
/**
* @}
*/
@@ -1801,7 +1801,7 @@
* @param StatusFlags Value of Interrupt Flags.
* @retval HAL status
*/
-static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
+static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
{
uint16_t DevAddress;
@@ -2085,7 +2085,7 @@
* @param StatusFlags Value of Interrupt Flags.
* @retval HAL status
*/
-static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
+static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
{
uint8_t TransferDirection;
uint16_t SlaveAddrCode;
@@ -2341,7 +2341,7 @@
* @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
* @retval HAL status
*/
-static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
+static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
{
uint32_t tmpisr = 0UL;
@@ -2381,7 +2381,7 @@
* @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
* @retval HAL status
*/
-static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
+static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
{
uint32_t tmpisr = 0UL;
uint32_t tmpstate = hsmbus->State;
@@ -2453,7 +2453,7 @@
* @param hsmbus SMBUS handle.
* @retval None
*/
-static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus)
+static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
{
uint32_t itflags = READ_REG(hsmbus->Instance->ISR);
uint32_t itsources = READ_REG(hsmbus->Instance->CR1);
@@ -2554,7 +2554,7 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
{
uint32_t tickstart = HAL_GetTick();
@@ -2603,7 +2603,7 @@
* @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request.
* @retval None
*/
-static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
{
/* Check the parameters */
assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
@@ -2620,7 +2620,7 @@
* @param hsmbus SMBUS handle.
* @retval None
*/
-static void SMBUS_ConvertOtherXferOptions(struct __SMBUS_HandleTypeDef *hsmbus)
+static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus)
{
/* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */
/* it request implicitly to generate a restart condition */
diff --git a/Src/stm32l4xx_ll_utils.c b/Src/stm32l4xx_ll_utils.c
index 0f1999b..b1dd002 100644
--- a/Src/stm32l4xx_ll_utils.c
+++ b/Src/stm32l4xx_ll_utils.c
@@ -41,7 +41,8 @@
/** @addtogroup UTILS_LL_Private_Constants
* @{
*/
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define UTILS_MAX_FREQUENCY_SCALE1 120000000U /*!< Maximum frequency for system clock at power scale1, in Hz */
#define UTILS_MAX_FREQUENCY_SCALE2 26000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
#else
@@ -60,7 +61,8 @@
#define UTILS_HSE_FREQUENCY_MAX 48000000U /*!< Frequency max for HSE frequency, in Hz */
/* Defines used for FLASH latency according to HCLK Frequency */
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define UTILS_SCALE1_LATENCY1_FREQ 20000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
#define UTILS_SCALE1_LATENCY2_FREQ 40000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
#define UTILS_SCALE1_LATENCY3_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
@@ -143,7 +145,6 @@
*/
static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
-static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency);
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
static ErrorStatus UTILS_PLL_IsBusy(void);
/**
@@ -227,7 +228,7 @@
Depending on the device voltage range, the maximum frequency should be
adapted accordingly:
- (++) Table 1. HCLK clock frequency for STM32L4Rx/STM32L4Sx devices
+ (++) Table 1. HCLK clock frequency for STM32L4+ Series devices
(++) +--------------------------------------------------------+
(++) | Latency | HCLK clock frequency (MHz) |
(++) | |--------------------------------------|
@@ -247,7 +248,7 @@
(++) |5WS(6 CPU cycles)| 100 < HCLK <= 120 | 16 < HCLK <= 26 |
(++) +--------------------------------------------------------+
- (++) Table 2. HCLK clock frequency for other STM32L4 devices
+ (++) Table 2. HCLK clock frequency for STM32L4 Series devices
(++) +-------------------------------------------------------+
(++) | Latency | HCLK clock frequency (MHz) |
(++) | |-------------------------------------|
@@ -282,6 +283,150 @@
}
/**
+ * @brief Update number of Flash wait states in line with new frequency and current
+ voltage range.
+ * @param HCLKFrequency HCLK frequency
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Latency has been modified
+ * - ERROR: Latency cannot be modified
+ */
+ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency)
+{
+ ErrorStatus status = SUCCESS;
+
+ uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
+
+ /* Frequency cannot be equal to 0 or greater than max clock */
+ if ((HCLKFrequency == 0U) || (HCLKFrequency > UTILS_MAX_FREQUENCY_SCALE1))
+ {
+ status = ERROR;
+ }
+ else
+ {
+ if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
+ {
+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+ if(HCLKFrequency > UTILS_SCALE1_LATENCY5_FREQ)
+ {
+ /* 100 < HCLK <= 120 => 5WS (6 CPU cycles) */
+ latency = LL_FLASH_LATENCY_5;
+ }
+ else if(HCLKFrequency > UTILS_SCALE1_LATENCY4_FREQ)
+ {
+ /* 80 < HCLK <= 100 => 4WS (5 CPU cycles) */
+ latency = LL_FLASH_LATENCY_4;
+ }
+ else if(HCLKFrequency > UTILS_SCALE1_LATENCY3_FREQ)
+ {
+ /* 60 < HCLK <= 80 => 3WS (4 CPU cycles) */
+ latency = LL_FLASH_LATENCY_3;
+ }
+ else if(HCLKFrequency > UTILS_SCALE1_LATENCY2_FREQ)
+ {
+ /* 40 < HCLK <= 20 => 2WS (3 CPU cycles) */
+ latency = LL_FLASH_LATENCY_2;
+ }
+ else
+ {
+ if(HCLKFrequency > UTILS_SCALE1_LATENCY1_FREQ)
+ {
+ /* 20 < HCLK <= 40 => 1WS (2 CPU cycles) */
+ latency = LL_FLASH_LATENCY_1;
+ }
+ /* else HCLKFrequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */
+ }
+#else
+ if(HCLKFrequency > UTILS_SCALE1_LATENCY4_FREQ)
+ {
+ /* 64 < HCLK <= 80 => 4WS (5 CPU cycles) */
+ latency = LL_FLASH_LATENCY_4;
+ }
+ else if(HCLKFrequency > UTILS_SCALE1_LATENCY3_FREQ)
+ {
+ /* 48 < HCLK <= 64 => 3WS (4 CPU cycles) */
+ latency = LL_FLASH_LATENCY_3;
+ }
+ else if(HCLKFrequency > UTILS_SCALE1_LATENCY2_FREQ)
+ {
+ /* 32 < HCLK <= 48 => 2WS (3 CPU cycles) */
+ latency = LL_FLASH_LATENCY_2;
+ }
+ else
+ {
+ if(HCLKFrequency > UTILS_SCALE1_LATENCY1_FREQ)
+ {
+ /* 16 < HCLK <= 32 => 1WS (2 CPU cycles) */
+ latency = LL_FLASH_LATENCY_1;
+ }
+ /* else HCLKFrequency <= 16MHz default LL_FLASH_LATENCY_0 0WS */
+ }
+#endif
+ }
+ else /* SCALE2 */
+ {
+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+ if(HCLKFrequency > UTILS_MAX_FREQUENCY_SCALE2)
+ {
+ /* Unexpected HCLK > 26 */
+ status = ERROR;
+ }
+ else if(HCLKFrequency > UTILS_SCALE2_LATENCY2_FREQ)
+ {
+ /* 16 < HCLK <= 26 => 2WS (3 CPU cycles) */
+ latency = LL_FLASH_LATENCY_2;
+ }
+ else
+ {
+ if(HCLKFrequency > UTILS_SCALE2_LATENCY1_FREQ)
+ {
+ /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */
+ latency = LL_FLASH_LATENCY_1;
+ }
+ /* else HCLKFrequency <= 8MHz default LL_FLASH_LATENCY_0 0WS */
+ }
+#else
+ if(HCLKFrequency > UTILS_MAX_FREQUENCY_SCALE2)
+ {
+ /* Unexpected HCLK > 26 */
+ status = ERROR;
+ }
+ else if(HCLKFrequency > UTILS_SCALE2_LATENCY3_FREQ)
+ {
+ /* 18 < HCLK <= 26 => 3WS (4 CPU cycles) */
+ latency = LL_FLASH_LATENCY_3;
+ }
+ else if(HCLKFrequency > UTILS_SCALE2_LATENCY2_FREQ)
+ {
+ /* 12 < HCLK <= 18 => 2WS (3 CPU cycles) */
+ latency = LL_FLASH_LATENCY_2;
+ }
+ else
+ {
+ if(HCLKFrequency > UTILS_SCALE2_LATENCY1_FREQ)
+ {
+ /* 6 < HCLK <= 12 => 1WS (2 CPU cycles) */
+ latency = LL_FLASH_LATENCY_1;
+ }
+ /* else HCLKFrequency <= 6MHz default LL_FLASH_LATENCY_0 0WS */
+ }
+#endif
+ }
+
+ LL_FLASH_SetLatency(latency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if(LL_FLASH_GetLatency() != latency)
+ {
+ status = ERROR;
+ }
+ }
+ return status;
+}
+
+/**
* @brief This function configures system clock with MSI as clock source of the PLL
* @note The application needs to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.
* @note Function is based on the following formula:
@@ -302,7 +447,8 @@
{
ErrorStatus status = SUCCESS;
uint32_t pllfreq, msi_range;
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
uint32_t hpre = 0U; /* Set default value */
#endif
@@ -374,26 +520,34 @@
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
UTILS_PLLInitStruct->PLLR);
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
/* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */
if(pllfreq > 80000000U)
{
- hpre = UTILS_ClkInitStruct->AHBCLKDivider;
- if(hpre == LL_RCC_SYSCLK_DIV_1)
+ if(UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1)
{
UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2;
+ hpre = LL_RCC_SYSCLK_DIV_2;
}
}
#endif
/* Enable PLL and switch system clock to PLL */
status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
/* Apply definitive AHB prescaler value if necessary */
- if((status == SUCCESS) && (hpre != 0U))
+ if((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1))
{
- UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
- LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+ /* Set FLASH latency to highest latency */
+ status = LL_SetFlashLatency(pllfreq);
+ if(status == SUCCESS)
+ {
+ UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
+ LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+ LL_SetSystemCoreClock(pllfreq);
+ }
}
#endif
}
@@ -428,8 +582,9 @@
{
ErrorStatus status;
uint32_t pllfreq;
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
- uint32_t hpre = 0U; /* Set default value */
+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+ uint32_t hpre = LL_RCC_SYSCLK_DIV_1; /* Set default value */
#endif
/* Check if one of the PLL is enabled */
@@ -452,26 +607,34 @@
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
UTILS_PLLInitStruct->PLLR);
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
/* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */
if(pllfreq > 80000000U)
{
- hpre = UTILS_ClkInitStruct->AHBCLKDivider;
- if(hpre == LL_RCC_SYSCLK_DIV_1)
+ if(UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1)
{
UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2;
+ hpre = LL_RCC_SYSCLK_DIV_2;
}
}
#endif
/* Enable PLL and switch system clock to PLL */
status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
/* Apply definitive AHB prescaler value if necessary */
- if((status == SUCCESS) && (hpre != 0U))
+ if((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1))
{
- UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
- LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+ /* Set FLASH latency to highest latency */
+ status = LL_SetFlashLatency(pllfreq);
+ if(status == SUCCESS)
+ {
+ UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
+ LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+ LL_SetSystemCoreClock(pllfreq);
+ }
}
#endif
}
@@ -509,7 +672,8 @@
{
ErrorStatus status;
uint32_t pllfreq;
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
uint32_t hpre = 0U; /* Set default value */
#endif
@@ -548,26 +712,34 @@
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
UTILS_PLLInitStruct->PLLR);
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
/* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */
if(pllfreq > 80000000U)
{
- hpre = UTILS_ClkInitStruct->AHBCLKDivider;
- if(hpre == LL_RCC_SYSCLK_DIV_1)
+ if(UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1)
{
UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2;
+ hpre = LL_RCC_SYSCLK_DIV_2;
}
}
#endif
/* Enable PLL and switch system clock to PLL */
status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
/* Apply definitive AHB prescaler value if necessary */
- if((status == SUCCESS) && (hpre != 0U))
+ if((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1))
{
- UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
- LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+ /* Set FLASH latency to highest latency */
+ status = LL_SetFlashLatency(pllfreq);
+ if(status == SUCCESS)
+ {
+ UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
+ LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+ LL_SetSystemCoreClock(pllfreq);
+ }
}
#endif
}
@@ -592,138 +764,6 @@
* @{
*/
/**
- * @brief Update number of Flash wait states in line with new frequency and current
- voltage range.
- * @param HCLK_Frequency HCLK frequency
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Latency has been modified
- * - ERROR: Latency cannot be modified
- */
-static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency)
-{
- ErrorStatus status = SUCCESS;
-
- uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
-
- /* Frequency cannot be equal to 0 */
- if(HCLK_Frequency == 0U)
- {
- status = ERROR;
- }
- else
- {
- if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
- {
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
- if(HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ)
- {
- /* 100 < HCLK <= 120 => 5WS (6 CPU cycles) */
- latency = LL_FLASH_LATENCY_5;
- }
- else if(HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ)
- {
- /* 80 < HCLK <= 100 => 4WS (5 CPU cycles) */
- latency = LL_FLASH_LATENCY_4;
- }
- else if(HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ)
- {
- /* 60 < HCLK <= 80 => 3WS (4 CPU cycles) */
- latency = LL_FLASH_LATENCY_3;
- }
- else if(HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)
- {
- /* 40 < HCLK <= 20 => 2WS (3 CPU cycles) */
- latency = LL_FLASH_LATENCY_2;
- }
- else
- {
- if(HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)
- {
- /* 20 < HCLK <= 40 => 1WS (2 CPU cycles) */
- latency = LL_FLASH_LATENCY_1;
- }
- /* else HCLK_Frequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */
- }
-#else
- if(HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ)
- {
- /* 64 < HCLK <= 80 => 4WS (5 CPU cycles) */
- latency = LL_FLASH_LATENCY_4;
- }
- else if(HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ)
- {
- /* 48 < HCLK <= 64 => 3WS (4 CPU cycles) */
- latency = LL_FLASH_LATENCY_3;
- }
- else if(HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)
- {
- /* 32 < HCLK <= 48 => 2WS (3 CPU cycles) */
- latency = LL_FLASH_LATENCY_2;
- }
- else
- {
- if(HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)
- {
- /* 16 < HCLK <= 32 => 1WS (2 CPU cycles) */
- latency = LL_FLASH_LATENCY_1;
- }
- /* else HCLK_Frequency <= 16MHz default LL_FLASH_LATENCY_0 0WS */
- }
-#endif
- }
- else /* SCALE2 */
- {
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
- if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)
- {
- /* 16 < HCLK <= 26 => 2WS (3 CPU cycles) */
- latency = LL_FLASH_LATENCY_2;
- }
- else
- {
- if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)
- {
- /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */
- latency = LL_FLASH_LATENCY_1;
- }
- /* else HCLK_Frequency <= 8MHz default LL_FLASH_LATENCY_0 0WS */
- }
-#else
- if(HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)
- {
- /* 18 < HCLK <= 26 => 3WS (4 CPU cycles) */
- latency = LL_FLASH_LATENCY_3;
- }
- else if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)
- {
- /* 12 < HCLK <= 18 => 2WS (3 CPU cycles) */
- latency = LL_FLASH_LATENCY_2;
- }
- else
- {
- if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)
- {
- /* 6 < HCLK <= 12 => 1WS (2 CPU cycles) */
- latency = LL_FLASH_LATENCY_1;
- }
- /* else HCLK_Frequency <= 6MHz default LL_FLASH_LATENCY_0 0WS */
- }
-#endif
- }
-
- LL_FLASH_SetLatency(latency);
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if(LL_FLASH_GetLatency() != latency)
- {
- status = ERROR;
- }
- }
- return status;
-}
-
-/**
* @brief Function to check that PLL can be modified
* @param PLL_InputFrequency PLL input frequency (in Hz)
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
@@ -818,7 +858,7 @@
if(SystemCoreClock < hclk_frequency)
{
/* Set FLASH latency to highest latency */
- status = UTILS_SetFlashLatency(hclk_frequency);
+ status = LL_SetFlashLatency(hclk_frequency);
}
/* Update system clock configuration */
@@ -849,7 +889,7 @@
if(SystemCoreClock > hclk_frequency)
{
/* Set FLASH latency to lowest latency */
- status = UTILS_SetFlashLatency(hclk_frequency);
+ status = LL_SetFlashLatency(hclk_frequency);
}
/* Update SystemCoreClock variable */
