commit c421105c147127e8452c493937e848ddcf757a65
author Ali Labbene <ali.labbene@st.com> Thu Mar 03 17:52:43 2022 +0100
committer Ali Labbene <ali.labbene@st.com> Thu Mar 03 19:02:33 2022 +0100
tree 6beb6973ae1983fcc00a465b1fa561332a41e460
parent 4294fb822c0e580cab7b53560bfa2f59149b1f61

[HAL][LL][LPTIM] Add check on PRIMASK register to prevent from enabling unwanted global interrupts within LPTIM_Disable() and LL_LPTIM_Disable()

Src/stm32l5xx_hal_lptim.c

diff --git a/Src/stm32l5xx_hal_lptim.c b/Src/stm32l5xx_hal_lptim.c
index 8a0d78f..516f96b 100644
--- a/Src/stm32l5xx_hal_lptim.c
+++ b/Src/stm32l5xx_hal_lptim.c
@@ -2524,10 +2524,13 @@
   uint32_t tmpCFGR;
   uint32_t tmpCMP;
   uint32_t tmpARR;
+  uint32_t primask_bit;
   uint32_t tmpOR;
   uint32_t tmpRCR;
 
-  __disable_irq();
+   /* Enter critical section */  
+   primask_bit = __get_PRIMASK();
+  __set_PRIMASK(1) ;
 
   /*********** Save LPTIM Config ***********/
   /* Save LPTIM source clock */
@@ -2658,7 +2661,8 @@
   hlptim->Instance->CFGR = tmpCFGR;
   hlptim->Instance->OR = tmpOR;
 
-  __enable_irq();
+  /* Exit critical section: restore previous priority mask */
+  __set_PRIMASK(primask_bit);
 }
 /**
   * @}

Src/stm32l5xx_ll_lptim.c

diff --git a/Src/stm32l5xx_ll_lptim.c b/Src/stm32l5xx_ll_lptim.c
index a31326f..a9041d2 100644
--- a/Src/stm32l5xx_ll_lptim.c
+++ b/Src/stm32l5xx_ll_lptim.c
@@ -198,13 +198,16 @@
   uint32_t tmpCFGR;
   uint32_t tmpCMP;
   uint32_t tmpARR;
+  uint32_t primask_bit;
   uint32_t tmpOR;
   uint32_t tmpRCR;
 
   /* Check the parameters */
   assert_param(IS_LPTIM_INSTANCE(LPTIMx));
 
-  __disable_irq();
+  /* Enter critical section */  
+  primask_bit = __get_PRIMASK();
+  __set_PRIMASK(1) ;
 
   /********** Save LPTIM Config *********/
   /* Save LPTIM source clock */
@@ -311,7 +314,8 @@
   LPTIMx->CFGR = tmpCFGR;
   LPTIMx->OR = tmpOR;
 
-  __enable_irq();
+  /* Exit critical section: restore previous priority mask */
+  __set_PRIMASK(primask_bit);
 }
 
 /**