[HAL][CORTEX] Align MPU Enable/Disable APIs with ARM's last recommendations in the usage of Data Memory and Data/Instruction Synchronization barriers
diff --git a/Inc/stm32l5xx_ll_cortex.h b/Inc/stm32l5xx_ll_cortex.h
index 4260a3e..1c40cde 100644
--- a/Inc/stm32l5xx_ll_cortex.h
+++ b/Inc/stm32l5xx_ll_cortex.h
@@ -501,14 +501,15 @@
*/
__STATIC_INLINE void LL_MPU_Enable(uint32_t MPU_Control)
{
+ __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
+
/* Enable the MPU*/
MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
- /* Ensure MPU settings take effects */
- __DSB();
-
- /* Sequence instruction fetches using update settings */
- __ISB();
+ /* Follow ARM recommendation with */
+ /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
+ __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
+ __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
}
/**
@@ -520,10 +521,15 @@
*/
__STATIC_INLINE void LL_MPU_Disable(void)
{
- /* Make sure outstanding transfers are done */
- __DMB();
+ __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before disabling the MPU */
+
/* Disable MPU */
WRITE_REG(MPU->CTRL, 0U);
+
+ /* Follow ARM recommendation with */
+ /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
+ __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
+ __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
}
/**
@@ -899,14 +905,15 @@
*/
__STATIC_INLINE void LL_MPU_Enable_NS(uint32_t MPU_Control)
{
+ __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
+
/* Enable the MPU*/
MPU_NS->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
- /* Ensure MPU settings take effects */
- __DSB();
-
- /* Sequence instruction fetches using update settings */
- __ISB();
+ /* Follow ARM recommendation with */
+ /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
+ __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
+ __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
}
/**
@@ -918,10 +925,15 @@
*/
__STATIC_INLINE void LL_MPU_Disable_NS(void)
{
- /* Make sure outstanding transfers are done */
- __DMB();
+ __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before disabling the MPU */
+
/* Disable MPU*/
WRITE_REG(MPU_NS->CTRL, 0U);
+
+ /* Follow ARM recommendation with */
+ /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
+ __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
+ __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
}
/**
diff --git a/Src/stm32l5xx_hal_cortex.c b/Src/stm32l5xx_hal_cortex.c
index b17dd74..24e5df1 100644
--- a/Src/stm32l5xx_hal_cortex.c
+++ b/Src/stm32l5xx_hal_cortex.c
@@ -426,6 +426,8 @@
*/
void HAL_MPU_Enable(uint32_t MPU_Control)
{
+ __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
+
/* Enable the MPU */
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
@@ -433,9 +435,9 @@
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
/* Follow ARM recommendation with */
- /* - Data Memory Barrier and Instruction Synchronization to insure MPU usage */
- __DMB(); /* Force memory writes before continuing */
- __ISB(); /* Flush and refill pipeline with updated permissions */
+ /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
+ __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
+ __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
}
/**
@@ -446,8 +448,16 @@
{
__DMB(); /* Force any outstanding transfers to complete before disabling MPU */
+ /* Disable fault exceptions */
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+
/* Disable the MPU */
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+
+ /* Follow ARM recommendation with */
+ /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
+ __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
+ __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
}
/**
@@ -486,6 +496,8 @@
*/
void HAL_MPU_Enable_NS(uint32_t MPU_Control)
{
+ __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
+
/* Enable the MPU */
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
@@ -493,9 +505,9 @@
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
/* Follow ARM recommendation with */
- /* - Data Memory Barrier and Instruction Synchronization to insure MPU usage */
- __DMB(); /* Force memory writes before continuing */
- __ISB(); /* Flush and refill pipeline with updated permissions */
+ /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
+ __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
+ __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
}
/**
@@ -506,8 +518,16 @@
{
__DMB(); /* Force any outstanding transfers to complete before disabling MPU */
+ /* Disable fault exceptions */
+ SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+
/* Disable the MPU */
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+
+ /* Follow ARM recommendation with */
+ /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
+ __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
+ __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
}
/**
