commit e14da877c60d4b3449d8be12690d00f94c6c5105
author karim <karim.rabhi-ext@st.com> Fri Oct 18 11:19:59 2024 +0100
committer karim <karim.rabhi-ext@st.com> Fri Oct 18 11:19:59 2024 +0100
tree 0e766497d48df4f61f2902a717d0b21fae721d7c
parent d6f29230f89f61adfb69ee7029cbe4d561cf160f

[HAL][USART] Align prescaler value used by default in USART_GET_DIV_FACTOR macro with RM

Inc/stm32l5xx_hal_usart.h

diff --git a/Inc/stm32l5xx_hal_usart.h b/Inc/stm32l5xx_hal_usart.h
index e614c81..e62a674 100644
--- a/Inc/stm32l5xx_hal_usart.h
+++ b/Inc/stm32l5xx_hal_usart.h
@@ -704,8 +704,7 @@
    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16)  ? 16U :      \
    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32)  ? 32U :      \
    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64)  ? 64U :      \
-   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U :     \
-   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U)
+   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : 256U)
 
 /** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.
   * @param  __PCLK__ USART clock.