Release v1.3.0
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index e643dfd..7e4d458 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -460,7 +460,9 @@
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
-#endif
+#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
+#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
+#endif /* STM32H7 */
/**
* @}
@@ -735,6 +737,33 @@
#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
#endif /* STM32H7 */
+
+#if defined(STM32F3)
+#define HRTIM_OUTPUTSET_TIMEV_1 HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1
+#define HRTIM_OUTPUTSET_TIMEV_2 HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2
+#define HRTIM_OUTPUTSET_TIMEV_3 HRTIM_OUTPUTSET_TIMAEV3_TIMBCMP4
+#define HRTIM_OUTPUTSET_TIMEV_4 HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP2
+#define HRTIM_OUTPUTSET_TIMEV_5 HRTIM_OUTPUTSET_TIMAEV5_TIMCCMP3
+#define HRTIM_OUTPUTSET_TIMEV_6 HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP1
+#define HRTIM_OUTPUTSET_TIMEV_7 HRTIM_OUTPUTSET_TIMAEV7_TIMDCMP2
+#define HRTIM_OUTPUTSET_TIMEV_8 HRTIM_OUTPUTSET_TIMAEV8_TIMECMP3
+#define HRTIM_OUTPUTSET_TIMEV_9 HRTIM_OUTPUTSET_TIMAEV9_TIMECMP4
+
+#define HRTIM_OUTPUTRESET_TIMEV_1 HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1
+#define HRTIM_OUTPUTRESET_TIMEV_2 HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2
+#define HRTIM_OUTPUTRESET_TIMEV_3 HRTIM_OUTPUTRESET_TIMAEV3_TIMBCMP4
+#define HRTIM_OUTPUTRESET_TIMEV_4 HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP2
+#define HRTIM_OUTPUTRESET_TIMEV_5 HRTIM_OUTPUTRESET_TIMAEV5_TIMCCMP3
+#define HRTIM_OUTPUTRESET_TIMEV_6 HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP1
+#define HRTIM_OUTPUTRESET_TIMEV_7 HRTIM_OUTPUTRESET_TIMAEV7_TIMDCMP2
+#define HRTIM_OUTPUTRESET_TIMEV_8 HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP3
+#define HRTIM_OUTPUTRESET_TIMEV_9 HRTIM_OUTPUTRESET_TIMAEV9_TIMECMP4
+
+#define HRTIM_EVENTSRC_1 HRTIM_EEV1SRC_GPIO
+#define HRTIM_EVENTSRC_2 HRTIM_EEV2SRC_GPIO
+#define HRTIM_EVENTSRC_3 HRTIM_EEV3SRC_GPIO
+#define HRTIM_EVENTSRC_4 HRTIM_EEV4SRC_GPIO
+#endif /* STM32F3 */
/**
* @}
*/
@@ -1380,6 +1409,13 @@
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ)
+#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
+#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
+#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
+#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
+#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7A3xxQ || STM32H7B3xxQ */
+
/**
* @}
*/
@@ -3242,7 +3278,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined STM32G4
+#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3606,12 +3642,12 @@
* @{
*/
#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
-#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
-#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
-#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
-#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
-#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
-#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
+#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
+#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
+#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
+#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
+#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
+#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
#endif
/**
* @}
diff --git a/Inc/stm32wbxx_hal_cryp.h b/Inc/stm32wbxx_hal_cryp.h
index 391636f..55fe059 100644
--- a/Inc/stm32wbxx_hal_cryp.h
+++ b/Inc/stm32wbxx_hal_cryp.h
@@ -182,7 +182,7 @@
uint32_t Key_saved[8]; /*!< copy of key registers */
- uint32_t Size_saved; /*!< copy of input buffer size */
+ uint16_t Size_saved; /*!< copy of input buffer size */
uint16_t CrypHeaderCount_saved; /*!< copy of CRYP header data counter when processing is suspended */
@@ -565,6 +565,12 @@
#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
+#define IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE) \
+ (((((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC) || ((ALGO) == CRYP_AES_CTR)) && \
+ ((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U)) || \
+ (((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U)))) || \
+ (((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM)))
+
/**
* @}
*/
diff --git a/Inc/stm32wbxx_hal_dma.h b/Inc/stm32wbxx_hal_dma.h
index 9467354..e575d61 100644
--- a/Inc/stm32wbxx_hal_dma.h
+++ b/Inc/stm32wbxx_hal_dma.h
@@ -204,8 +204,10 @@
#define DMA_REQUEST_LPUART1_RX LL_DMAMUX_REQ_LPUART1_RX /*!< DMAMUX LP_UART1_RX request */
#define DMA_REQUEST_LPUART1_TX LL_DMAMUX_REQ_LPUART1_TX /*!< DMAMUX LP_UART1_RX request */
+#if defined (SAI1)
#define DMA_REQUEST_SAI1_A LL_DMAMUX_REQ_SAI1_A /*!< DMAMUX SAI1 A request */
#define DMA_REQUEST_SAI1_B LL_DMAMUX_REQ_SAI1_B /*!< DMAMUX SAI1 B request */
+#endif /* SAI1 */
#define DMA_REQUEST_QUADSPI LL_DMAMUX_REQ_QUADSPI /*!< DMAMUX QUADSPI request */
diff --git a/Inc/stm32wbxx_hal_flash.h b/Inc/stm32wbxx_hal_flash.h
index e0def21..548518f 100644
--- a/Inc/stm32wbxx_hal_flash.h
+++ b/Inc/stm32wbxx_hal_flash.h
@@ -150,10 +150,10 @@
/** @defgroup FLASH_LATENCY FLASH Latency
* @{
*/
-#define FLASH_LATENCY_0 0x00000000UL /*!< FLASH Zero wait state */
-#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One wait state */
-#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */
-#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_2 /*!< FLASH Three wait states */
+#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
+#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
+#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
+#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
/**
* @}
*/
@@ -179,12 +179,14 @@
#define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */
#define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */
-#define FLASH_FLAG_SR_ERROR (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
+#define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \
FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \
FLASH_FLAG_OPTVERR) /*!< All SR error flags */
-#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERROR | FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)
+#define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)
+
+#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS)
/** @defgroup FLASH_INTERRUPT_DEFINITION FLASH Interrupts Definition
* @brief FLASH Interrupt definition
@@ -212,7 +214,6 @@
#define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR
#define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR
#define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR
-#define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD
/**
* @}
*/
@@ -480,39 +481,39 @@
* @{
*/
-#define SRAM2A_START_SECURE_ADDR_0 0x20030000U /* When in secure mode 0x20030000 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_1 0x20030400U /* When in secure mode 0x20030400 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_2 0x20030800U /* When in secure mode 0x20030800 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_3 0x20030C00U /* When in secure mode 0x20030C00 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_4 0x20031000U /* When in secure mode 0x20031000 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_5 0x20031400U /* When in secure mode 0x20031400 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_6 0x20031800U /* When in secure mode 0x20031800 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_7 0x20031C00U /* When in secure mode 0x20031C00 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_8 0x20032000U /* When in secure mode 0x20032000 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_9 0x20032400U /* When in secure mode 0x20032400 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_10 0x20032800U /* When in secure mode 0x20032800 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_11 0x20032C00U /* When in secure mode 0x20032C00 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_12 0x20033000U /* When in secure mode 0x20033000 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_13 0x20033400U /* When in secure mode 0x20033400 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_14 0x20033800U /* When in secure mode 0x20033800 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_15 0x20033C00U /* When in secure mode 0x20033C00 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_16 0x20034000U /* When in secure mode 0x20034000 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_17 0x20034400U /* When in secure mode 0x20034400 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_18 0x20034800U /* When in secure mode 0x20034800 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_19 0x20034C00U /* When in secure mode 0x20034C00 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_20 0x20035000U /* When in secure mode 0x20035000 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_21 0x20035400U /* When in secure mode 0x20035400 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_22 0x20035800U /* When in secure mode 0x20035800 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_23 0x20035C00U /* When in secure mode 0x20035C00 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_24 0x20036000U /* When in secure mode 0x20036000 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_25 0x20036400U /* When in secure mode 0x20036400 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_26 0x20036800U /* When in secure mode 0x20036800 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_27 0x20036C00U /* When in secure mode 0x20036C00 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_28 0x20037000U /* When in secure mode 0x20037000 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_29 0x20037400U /* When in secure mode 0x20037400 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_30 0x20037800U /* When in secure mode 0x20037800 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_START_SECURE_ADDR_31 0x20037C00U /* When in secure mode 0x20037C00 - 0x20037FFF is accessible only by M0 Plus */
-#define SRAM2A_FULL_UNSECURE 0x20040000U /* The RAM2A is accessible to M0 Plus and M4 */
+#define SRAM2A_START_SECURE_ADDR_0 (SRAM2A_BASE + 0x0000U) /* When in secure mode (SRAM2A_BASE + 0x0000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_1 (SRAM2A_BASE + 0x0400U) /* When in secure mode (SRAM2A_BASE + 0x0400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_2 (SRAM2A_BASE + 0x0800U) /* When in secure mode (SRAM2A_BASE + 0x0800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_3 (SRAM2A_BASE + 0x0C00U) /* When in secure mode (SRAM2A_BASE + 0x0C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_4 (SRAM2A_BASE + 0x1000U) /* When in secure mode (SRAM2A_BASE + 0x1000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_5 (SRAM2A_BASE + 0x1400U) /* When in secure mode (SRAM2A_BASE + 0x1400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_6 (SRAM2A_BASE + 0x1800U) /* When in secure mode (SRAM2A_BASE + 0x1800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_7 (SRAM2A_BASE + 0x1C00U) /* When in secure mode (SRAM2A_BASE + 0x1C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_8 (SRAM2A_BASE + 0x2000U) /* When in secure mode (SRAM2A_BASE + 0x2000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_9 (SRAM2A_BASE + 0x2400U) /* When in secure mode (SRAM2A_BASE + 0x2400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_10 (SRAM2A_BASE + 0x2800U) /* When in secure mode (SRAM2A_BASE + 0x2800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_11 (SRAM2A_BASE + 0x2C00U) /* When in secure mode (SRAM2A_BASE + 0x2C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_12 (SRAM2A_BASE + 0x3000U) /* When in secure mode (SRAM2A_BASE + 0x3000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_13 (SRAM2A_BASE + 0x3400U) /* When in secure mode (SRAM2A_BASE + 0x3400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_14 (SRAM2A_BASE + 0x3800U) /* When in secure mode (SRAM2A_BASE + 0x3800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_15 (SRAM2A_BASE + 0x3C00U) /* When in secure mode (SRAM2A_BASE + 0x3C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_16 (SRAM2A_BASE + 0x4000U) /* When in secure mode (SRAM2A_BASE + 0x4000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_17 (SRAM2A_BASE + 0x4400U) /* When in secure mode (SRAM2A_BASE + 0x4400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_18 (SRAM2A_BASE + 0x4800U) /* When in secure mode (SRAM2A_BASE + 0x4800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_19 (SRAM2A_BASE + 0x4C00U) /* When in secure mode (SRAM2A_BASE + 0x4C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_20 (SRAM2A_BASE + 0x5000U) /* When in secure mode (SRAM2A_BASE + 0x5000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_21 (SRAM2A_BASE + 0x5400U) /* When in secure mode (SRAM2A_BASE + 0x5400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_22 (SRAM2A_BASE + 0x5800U) /* When in secure mode (SRAM2A_BASE + 0x5800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_23 (SRAM2A_BASE + 0x5C00U) /* When in secure mode (SRAM2A_BASE + 0x5C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_24 (SRAM2A_BASE + 0x6000U) /* When in secure mode (SRAM2A_BASE + 0x6000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_25 (SRAM2A_BASE + 0x6400U) /* When in secure mode (SRAM2A_BASE + 0x6400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_26 (SRAM2A_BASE + 0x6800U) /* When in secure mode (SRAM2A_BASE + 0x6800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_27 (SRAM2A_BASE + 0x6C00U) /* When in secure mode (SRAM2A_BASE + 0x6C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_28 (SRAM2A_BASE + 0x7000U) /* When in secure mode (SRAM2A_BASE + 0x7000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_29 (SRAM2A_BASE + 0x7400U) /* When in secure mode (SRAM2A_BASE + 0x7400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_30 (SRAM2A_BASE + 0x7800U) /* When in secure mode (SRAM2A_BASE + 0x7800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_START_SECURE_ADDR_31 (SRAM2A_BASE + 0x7C00U) /* When in secure mode (SRAM2A_BASE + 0x7C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2A_FULL_UNSECURE (SRAM2A_BASE + 0x8000U) /* The RAM2A is accessible to M0 Plus and M4 */
/**
* @}
@@ -522,39 +523,39 @@
* @{
*/
-#define SRAM2B_START_SECURE_ADDR_0 0x20038000U /* When in secure mode 0x20038000 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_1 0x20038400U /* When in secure mode 0x20038400 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_2 0x20038800U /* When in secure mode 0x20038800 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_3 0x20038C00U /* When in secure mode 0x20038C00 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_4 0x20039000U /* When in secure mode 0x20039000 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_5 0x20039400U /* When in secure mode 0x20039400 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_6 0x20039800U /* When in secure mode 0x20039800 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_7 0x20039C00U /* When in secure mode 0x20039C00 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_8 0x2003A000U /* When in secure mode 0x2003A000 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_9 0x2003A400U /* When in secure mode 0x2003A400 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_10 0x2003A800U /* When in secure mode 0x2003A800 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_11 0x2003AC00U /* When in secure mode 0x2003AC00 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_12 0x2003B000U /* When in secure mode 0x2003B000 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_13 0x2003B400U /* When in secure mode 0x2003B400 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_14 0x2003B800U /* When in secure mode 0x2003B800 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_15 0x2003BC00U /* When in secure mode 0x2003BC00 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_16 0x2003C000U /* When in secure mode 0x2003C000 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_17 0x2003C400U /* When in secure mode 0x2003C400 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_18 0x2003C800U /* When in secure mode 0x2003C800 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_19 0x2003CC00U /* When in secure mode 0x2003CC00 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_20 0x2003D000U /* When in secure mode 0x2003D000 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_21 0x2003D400U /* When in secure mode 0x2003D400 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_22 0x2003D800U /* When in secure mode 0x2003D800 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_23 0x2003DC00U /* When in secure mode 0x2003DC00 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_24 0x2003E000U /* When in secure mode 0x2003E000 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_25 0x2003E400U /* When in secure mode 0x2003E400 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_26 0x2003E800U /* When in secure mode 0x2003E800 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_27 0x2003EC00U /* When in secure mode 0x2003EC00 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_28 0x2003F000U /* When in secure mode 0x2003F000 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_29 0x2003F400U /* When in secure mode 0x2003F400 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_30 0x2003F800U /* When in secure mode 0x2003F800 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_START_SECURE_ADDR_31 0x2003FC00U /* When in secure mode 0x2003FC00 - 0x2003FFFF is accessible only by M0 Plus */
-#define SRAM2B_FULL_UNSECURE 0x2003FF00U /* The RAM2B is accessible to M0 Plus and M4 */
+#define SRAM2B_START_SECURE_ADDR_0 (SRAM2B_BASE + 0x0000U) /* When in secure mode (SRAM2B_BASE + 0x0000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_1 (SRAM2B_BASE + 0x0400U) /* When in secure mode (SRAM2B_BASE + 0x0400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_2 (SRAM2B_BASE + 0x0800U) /* When in secure mode (SRAM2B_BASE + 0x0800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_3 (SRAM2B_BASE + 0x0C00U) /* When in secure mode (SRAM2B_BASE + 0x0C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_4 (SRAM2B_BASE + 0x1000U) /* When in secure mode (SRAM2B_BASE + 0x1000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_5 (SRAM2B_BASE + 0x1400U) /* When in secure mode (SRAM2B_BASE + 0x1400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_6 (SRAM2B_BASE + 0x1800U) /* When in secure mode (SRAM2B_BASE + 0x1800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_7 (SRAM2B_BASE + 0x1C00U) /* When in secure mode (SRAM2B_BASE + 0x1C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_8 (SRAM2B_BASE + 0x2000U) /* When in secure mode (SRAM2B_BASE + 0x2000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_9 (SRAM2B_BASE + 0x2400U) /* When in secure mode (SRAM2B_BASE + 0x2400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_10 (SRAM2B_BASE + 0x2800U) /* When in secure mode (SRAM2B_BASE + 0x2800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_11 (SRAM2B_BASE + 0x2C00U) /* When in secure mode (SRAM2B_BASE + 0x2C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_12 (SRAM2B_BASE + 0x3000U) /* When in secure mode (SRAM2B_BASE + 0x3000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_13 (SRAM2B_BASE + 0x3400U) /* When in secure mode (SRAM2B_BASE + 0x3400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_14 (SRAM2B_BASE + 0x3800U) /* When in secure mode (SRAM2B_BASE + 0x3800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_15 (SRAM2B_BASE + 0x3C00U) /* When in secure mode (SRAM2B_BASE + 0x3C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_16 (SRAM2B_BASE + 0x4000U) /* When in secure mode (SRAM2B_BASE + 0x4000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_17 (SRAM2B_BASE + 0x4400U) /* When in secure mode (SRAM2B_BASE + 0x4400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_18 (SRAM2B_BASE + 0x4800U) /* When in secure mode (SRAM2B_BASE + 0x4800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_19 (SRAM2B_BASE + 0x4C00U) /* When in secure mode (SRAM2B_BASE + 0x4C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_20 (SRAM2B_BASE + 0x5000U) /* When in secure mode (SRAM2B_BASE + 0x5000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_21 (SRAM2B_BASE + 0x5400U) /* When in secure mode (SRAM2B_BASE + 0x5400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_22 (SRAM2B_BASE + 0x5800U) /* When in secure mode (SRAM2B_BASE + 0x5800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_23 (SRAM2B_BASE + 0x5C00U) /* When in secure mode (SRAM2B_BASE + 0x5C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_24 (SRAM2B_BASE + 0x6000U) /* When in secure mode (SRAM2B_BASE + 0x6000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_25 (SRAM2B_BASE + 0x6400U) /* When in secure mode (SRAM2B_BASE + 0x6400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_26 (SRAM2B_BASE + 0x6800U) /* When in secure mode (SRAM2B_BASE + 0x6800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_27 (SRAM2B_BASE + 0x6C00U) /* When in secure mode (SRAM2B_BASE + 0x6C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_28 (SRAM2B_BASE + 0x7000U) /* When in secure mode (SRAM2B_BASE + 0x7000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_29 (SRAM2B_BASE + 0x7400U) /* When in secure mode (SRAM2B_BASE + 0x7400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_30 (SRAM2B_BASE + 0x7800U) /* When in secure mode (SRAM2B_BASE + 0x7800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_START_SECURE_ADDR_31 (SRAM2B_BASE + 0x7C00U) /* When in secure mode (SRAM2B_BASE + 0x7C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
+#define SRAM2B_FULL_UNSECURE (SRAM2B_BASE + 0x8000U) /* The RAM2B is accessible to M0 Plus and M4 */
/**
* @}
@@ -707,7 +708,7 @@
* @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected
* @retval The new state of FLASH_FLAG (SET or RESET).
*/
-#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) ? \
+#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS)) != 0U) ? \
(READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \
(READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__)))
/**
@@ -727,11 +728,13 @@
* @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag
* @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected
* @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected
+ * @arg @ref FLASH_FLAG_SR_ERRORS FLASH All SR errors flags
+ * @arg @ref FLASH_FLAG_ECCR_ERRORS FLASH All ECCR errors flags
* @arg @ref FLASH_FLAG_ALL_ERRORS FLASH All errors flags
* @retval None
*/
-#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\
- if(((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS)) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS))); }\
+ if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\
} while(0)
/**
* @}
@@ -808,12 +811,11 @@
/** @defgroup FLASH_Private_Constants FLASH Private Constants
* @{
*/
-#define FLASH_SIZE (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0x07FFUL)) << 10U)
#define FLASH_END_ADDR (FLASH_BASE + FLASH_SIZE - 1U)
#define FLASH_BANK_SIZE FLASH_SIZE /*!< FLASH Bank Size */
#define FLASH_PAGE_SIZE 0x00001000U /*!< FLASH Page Size, 4 KBytes */
-#define FLASH_PAGE_NB 128U
+#define FLASH_PAGE_NB (FLASH_SIZE / FLASH_PAGE_SIZE)
#define FLASH_TIMEOUT_VALUE 1000U /*!< FLASH Execution Timeout, 1 s */
#define FLASH_PCROP_GRANULARITY_OFFSET 11U /*!< FLASH Code Readout Protection granularity offset */
diff --git a/Inc/stm32wbxx_hal_gpio_ex.h b/Inc/stm32wbxx_hal_gpio_ex.h
index e3c3fd3..fc10f8e 100644
--- a/Inc/stm32wbxx_hal_gpio_ex.h
+++ b/Inc/stm32wbxx_hal_gpio_ex.h
@@ -53,7 +53,9 @@
*
*/
- /* | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 |
+#if defined (STM32WB55xx) || defined (STM32WB50xx)
+
+ /* | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 |
*_____________________________________________________________________________________________
* |SYS_AF |TIM |TIM |SPI/SAI/TI|I2C | I2C | RF | USART |
*_____________________________________________________________________________________________
@@ -358,6 +360,9 @@
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0f)
+#endif
+
+
/**
* @}
diff --git a/Inc/stm32wbxx_hal_rcc.h b/Inc/stm32wbxx_hal_rcc.h
index ba03291..36c647b 100644
--- a/Inc/stm32wbxx_hal_rcc.h
+++ b/Inc/stm32wbxx_hal_rcc.h
@@ -110,7 +110,7 @@
((__VALUE__) == RCC_PLLM_DIV7) || \
((__VALUE__) == RCC_PLLM_DIV8))
-#define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
+#define IS_RCC_PLLN_VALUE(__VALUE__) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U))
#define IS_RCC_PLLP_VALUE(__VALUE__) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32))
@@ -220,7 +220,7 @@
This parameter must be a value of @ref RCC_PLLM_Clock_Divider */
uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
- This parameter must be a number between Min_Data = 8 and Max_Data = 86 */
+ This parameter must be a number between Min_Data = 6 and Max_Data = 127 */
uint32_t PLLP; /*!< PLLP: Division factor for SAI & ADC clock.
This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
@@ -2861,13 +2861,13 @@
* @param __PLLM__ specifies the division factor for PLL VCO input clock.
* This parameter must be a value of @ref RCC_PLLM_Clock_Divider.
* @note You have to set the PLLM parameter correctly to ensure that the VCO input
- * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
+ * frequency ranges from 2.66 to 16 MHz. It is recommended to select a frequency
* of 16 MHz to limit PLL jitter.
*
* @param __PLLN__ specifies the multiplication factor for PLL VCO output clock.
- * This parameter must be a number between 8 and 86.
+ * This parameter must be a number between 6 and 127.
* @note You have to set the PLLN parameter correctly to ensure that the VCO
- * output frequency is between 64 and 344 MHz.
+ * output frequency is between 96 and 344 MHz.
*
* @param __PLLP__ specifies the division factor for ADC and SAI1 clock.
* This parameter must be a value of @ref RCC_PLLP_Clock_Divider.
diff --git a/Inc/stm32wbxx_hal_rcc_ex.h b/Inc/stm32wbxx_hal_rcc_ex.h
index 68fe89f..230929e 100644
--- a/Inc/stm32wbxx_hal_rcc_ex.h
+++ b/Inc/stm32wbxx_hal_rcc_ex.h
@@ -191,7 +191,7 @@
#endif
#if defined(SAI1)
-#define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
+#define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U))
#define IS_RCC_PLLSAI1P_VALUE(__VALUE__) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32))
@@ -242,7 +242,7 @@
{
uint32_t PLLN; /*!< PLLN: specifies the multiplication factor for PLLSAI1 VCO output clock.
- This parameter must be a number between Min_Data=8 and Max_Data=86. */
+ This parameter must be a number between Min_Data=6 and Max_Data=127. */
uint32_t PLLP; /*!< PLLP: specifies the division factor for SAI clock.
This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
@@ -757,9 +757,9 @@
* @ref __HAL_RCC_PLL_CONFIG() macro)
*
* @param __PLLN__ specifies the multiplication factor for PLLSAI1 VCO output clock.
- * This parameter must be a number between 4 and 86.
+ * This parameter must be a number between 6 and 127.
* @note You have to set the PLLN parameter correctly to ensure that the VCO
- * output frequency is between 64 and 344 MHz.
+ * output frequency is between 96 and 344 MHz.
* PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLN
*
* @param __PLLP__ specifies the division factor for SAI clock.
@@ -789,9 +789,9 @@
* @ref __HAL_RCC_PLL_CONFIG() macro)
*
* @param __PLLN__ specifies the multiplication factor for PLLSAI1 VCO output clock.
- * This parameter must be a number between Min_Data=4 and Max_Data=86.
+ * This parameter must be a number between Min_Data=6 and Max_Data=127.
* @note You have to set the PLLN parameter correctly to ensure that the VCO
- * output frequency is between 64 and 344 MHz.
+ * output frequency is between 96 and 344 MHz.
* Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLN
*
* @retval None
diff --git a/Inc/stm32wbxx_hal_tim.h b/Inc/stm32wbxx_hal_tim.h
index 3c12713..ce4b09e 100644
--- a/Inc/stm32wbxx_hal_tim.h
+++ b/Inc/stm32wbxx_hal_tim.h
@@ -167,7 +167,7 @@
This parameter can be a value of @ref TIM_Encoder_Mode */
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+ This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
uint32_t IC1Selection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
@@ -179,7 +179,7 @@
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+ This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
uint32_t IC2Selection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
@@ -616,6 +616,15 @@
* @}
*/
+/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
+ * @{
+ */
+#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */
+#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */
+/**
+ * @}
+ */
+
/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
* @{
*/
@@ -1686,6 +1695,9 @@
#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
((__STATE__) == TIM_OCNIDLESTATE_RESET))
+#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
+ ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
+
#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
diff --git a/Inc/stm32wbxx_hal_wwdg.h b/Inc/stm32wbxx_hal_wwdg.h
index f20ee87..8d69784 100644
--- a/Inc/stm32wbxx_hal_wwdg.h
+++ b/Inc/stm32wbxx_hal_wwdg.h
@@ -22,7 +22,7 @@
#define STM32WBxx_HAL_WWDG_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -89,12 +89,12 @@
{
HAL_WWDG_EWI_CB_ID = 0x00u, /*!< WWDG EWI callback ID */
HAL_WWDG_MSPINIT_CB_ID = 0x01u, /*!< WWDG MspInit callback ID */
-}HAL_WWDG_CallbackIDTypeDef;
+} HAL_WWDG_CallbackIDTypeDef;
/**
* @brief HAL WWDG Callback pointer definition
*/
-typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer to a WWDG common callback functions */
+typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */
#endif
/**
@@ -247,7 +247,8 @@
* @arg WWDG_IT_EWI: Early Wakeup Interrupt
* @retval state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\
+ & (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @}
diff --git a/Inc/stm32wbxx_ll_pwr.h b/Inc/stm32wbxx_ll_pwr.h
index 5e7a297..d1a9b76 100644
--- a/Inc/stm32wbxx_ll_pwr.h
+++ b/Inc/stm32wbxx_ll_pwr.h
@@ -1062,7 +1062,7 @@
*/
__STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
{
- SET_BIT(*((uint32_t *)GPIO), GPIONumber);
+ SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
}
/**
@@ -1103,7 +1103,7 @@
*/
__STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
{
- CLEAR_BIT(*((uint32_t *)GPIO), GPIONumber);
+ CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
}
/**
@@ -1142,7 +1142,7 @@
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
{
- return ((READ_BIT(*((uint32_t *)(GPIO)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
+ return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
}
/**
@@ -1183,8 +1183,7 @@
*/
__STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
{
- register __IO uint32_t temp = (uint32_t)(GPIO) + 4UL;
- SET_BIT(*((uint32_t *)(temp)), GPIONumber);
+ SET_BIT(*((__IO uint32_t *)(GPIO + 4UL)), GPIONumber);
}
/**
@@ -1225,8 +1224,7 @@
*/
__STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
{
- register __IO uint32_t temp = (uint32_t)(GPIO) + 4UL;
- CLEAR_BIT(*((uint32_t *)(temp)), GPIONumber);
+ CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4UL)), GPIONumber);
}
/**
@@ -1265,8 +1263,7 @@
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
{
- register __IO uint32_t temp = (uint32_t)(GPIO) + 4UL;
- return ((READ_BIT(*((uint32_t *)(temp)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
+ return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4UL)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
}
#if defined(PWR_CR5_SMPSEN)
@@ -1573,12 +1570,12 @@
{
OutputVoltageLevelTrimmed = (int32_t)LL_PWR_SMPS_OUTPUT_VOLTAGE_1V20;
}
- else if(OutputVoltageLevelTrimmed > (int32_t)PWR_CR5_SMPSVOS)
- {
- OutputVoltageLevelTrimmed = (int32_t)LL_PWR_SMPS_OUTPUT_VOLTAGE_1V90;
- }
else
{
+ if(OutputVoltageLevelTrimmed > (int32_t)PWR_CR5_SMPSVOS)
+ {
+ OutputVoltageLevelTrimmed = (int32_t)LL_PWR_SMPS_OUTPUT_VOLTAGE_1V90;
+ }
}
return (uint32_t)OutputVoltageLevelTrimmed;
diff --git a/Inc/stm32wbxx_ll_rcc.h b/Inc/stm32wbxx_ll_rcc.h
index 5a3b92b..37cf247 100644
--- a/Inc/stm32wbxx_ll_rcc.h
+++ b/Inc/stm32wbxx_ll_rcc.h
@@ -849,7 +849,7 @@
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
- * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86
+ * @param __PLLN__ Between Min_Data = 6 and Max_Data = 127
* @param __PLLR__ This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLR_DIV_2
* @arg @ref LL_RCC_PLLR_DIV_3
@@ -878,7 +878,7 @@
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
- * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86
+ * @param __PLLN__ Between Min_Data = 6 and Max_Data = 127
* @param __PLLP__ This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLP_DIV_2
* @arg @ref LL_RCC_PLLP_DIV_3
@@ -930,7 +930,7 @@
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
- * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86
+ * @param __PLLN__ Between Min_Data = 6 and Max_Data = 127
* @param __PLLP__ This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLP_DIV_2
* @arg @ref LL_RCC_PLLP_DIV_3
@@ -982,7 +982,7 @@
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
- * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86
+ * @param __PLLN__ Between Min_Data = 6 and Max_Data = 127
* @param __PLLQ__ This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLQ_DIV_2
* @arg @ref LL_RCC_PLLQ_DIV_3
@@ -1011,7 +1011,7 @@
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
- * @param __PLLSAI1N__ Between 8 and 86
+ * @param __PLLSAI1N__ Between 6 and 127
* @param __PLLSAI1P__ This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLSAI1P_DIV_2
* @arg @ref LL_RCC_PLLSAI1P_DIV_3
@@ -1064,7 +1064,7 @@
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
- * @param __PLLSAI1N__ Between 8 and 86
+ * @param __PLLSAI1N__ Between 6 and 127
* @param __PLLSAI1Q__ This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLSAI1Q_DIV_2
* @arg @ref LL_RCC_PLLSAI1Q_DIV_3
@@ -1093,7 +1093,7 @@
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
- * @param __PLLSAI1N__ Between 8 and 86
+ * @param __PLLSAI1N__ Between 6 and 127
* @param __PLLSAI1R__ This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLSAI1R_DIV_2
* @arg @ref LL_RCC_PLLSAI1R_DIV_3
@@ -2956,7 +2956,7 @@
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
- * @param PLLN Between 8 and 86
+ * @param PLLN Between 6 and 127
* @param PLLR This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLR_DIV_2
* @arg @ref LL_RCC_PLLR_DIV_4
@@ -2994,7 +2994,7 @@
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
- * @param PLLN Between 8 and 86
+ * @param PLLN Between 6 and 127
* @param PLLP This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLP_DIV_2
* @arg @ref LL_RCC_PLLP_DIV_3
@@ -3059,7 +3059,7 @@
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
- * @param PLLN Between 8 and 86
+ * @param PLLN Between 6 and 127
* @param PLLP This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLP_DIV_2
* @arg @ref LL_RCC_PLLP_DIV_3
@@ -3124,7 +3124,7 @@
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
- * @param PLLN Between 8 and 86
+ * @param PLLN Between 6 and 127
* @param PLLQ This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLQ_DIV_2
* @arg @ref LL_RCC_PLLQ_DIV_3
@@ -3144,7 +3144,7 @@
/**
* @brief Get Main PLL multiplication factor for VCO
* @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
- * @retval Between 8 and 86
+ * @retval Between 6 and 127
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
{
@@ -3402,7 +3402,7 @@
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
- * @param PLLN Between 8 and 86
+ * @param PLLN Between 6 and 127
* @param PLLQ This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLSAI1Q_DIV_2
* @arg @ref LL_RCC_PLLSAI1Q_DIV_3
@@ -3443,7 +3443,7 @@
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
- * @param PLLN Between 8 and 86
+ * @param PLLN Between 6 and 127
* @param PLLP This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLSAI1P_DIV_2
* @arg @ref LL_RCC_PLLSAI1P_DIV_3
@@ -3509,7 +3509,7 @@
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
- * @param PLLN Between 8 and 86
+ * @param PLLN Between 6 and 127
* @param PLLR This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLSAI1R_DIV_2
* @arg @ref LL_RCC_PLLSAI1R_DIV_3
@@ -3529,7 +3529,7 @@
/**
* @brief Get SAI1PLL multiplication factor for VCO
* @rmtoll PLLSAI1CFGR PLLN LL_RCC_PLLSAI1_GetN
- * @retval Between 8 and 86
+ * @retval Between 6 and 127
*/
__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void)
{
diff --git a/Inc/stm32wbxx_ll_system.h b/Inc/stm32wbxx_ll_system.h
index 2a313c8..89bacd0 100644
--- a/Inc/stm32wbxx_ll_system.h
+++ b/Inc/stm32wbxx_ll_system.h
@@ -2182,8 +2182,8 @@
* @brief Return the Device ID
* @note The 64-bit UID64 may be used by Firmware to derive BLE 48-bit Device Address EUI-48 or
* 802.15.4 64-bit Device Address EUI-64.
- * For STM32WBxxxx devices, the device ID is 0x05
- * @retval Values between Min_Data=0x00 and Max_Data=0xFF (ex: Device ID is 0x05)
+ * For STM32WBxxxx devices, the device ID is 0x26
+ * @retval Values between Min_Data=0x00 and Max_Data=0xFF (ex: Device ID is 0x26 fo STM32WB55x)
*/
__STATIC_INLINE uint32_t LL_FLASH_GetDeviceID(void)
{
diff --git a/Inc/stm32wbxx_ll_tim.h b/Inc/stm32wbxx_ll_tim.h
index 5231a67..f7d2fc5 100644
--- a/Inc/stm32wbxx_ll_tim.h
+++ b/Inc/stm32wbxx_ll_tim.h
@@ -924,14 +924,15 @@
/** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source
* @{
*/
-#define LL_TIM_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
+#define LL_TIM_ETRSOURCE_LEGACY 0x00000000U /*!< ETR legacy mode */
#if defined(COMP1) && defined(COMP2)
#define LL_TIM_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
#define LL_TIM_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
#endif /* COMP1 && COMP2 */
-#define LL_TIM_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC1 analog watchdog 1 */
-#define LL_TIM_ETRSOURCE_ADC1_AWD2 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to ADC1 analog watchdog 2 */
-#define LL_TIM_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC1 analog watchdog 3 */
+#define LL_TIM_ETRSOURCE_GPIO LL_TIM_ETRSOURCE_LEGACY /*!< ETR input is connected to GPIO through TIMx ETR remapping capability */
+#define LL_TIM_ETRSOURCE_ADC1_AWD1 LL_TIM_ETRSOURCE_LEGACY /*!< ETR input is connected to ADC1 analog watchdog 1 through TIMx ETR remapping capability */
+#define LL_TIM_ETRSOURCE_ADC1_AWD2 LL_TIM_ETRSOURCE_LEGACY /*!< ETR input is connected to ADC1 analog watchdog 2 through TIMx ETR remapping capability */
+#define LL_TIM_ETRSOURCE_ADC1_AWD3 LL_TIM_ETRSOURCE_LEGACY /*!< ETR input is connected to ADC1 analog watchdog 3 through TIMx ETR remapping capability */
/**
* @}
*/
@@ -1129,7 +1130,7 @@
/** @defgroup TIM_LL_EC_TIM2_ITR1_RMP TIM2 Internal Trigger1 Remap
* @{
*/
-#define LL_TIM_TIM2_ITR1_RMP_NONE 0x00000000U /* !< No internal trigger on TIM2_ITR1 */
+#define LL_TIM_TIM2_ITR1_RMP_NONE TIM2_OR_RMP_MASK /* !< No internal trigger on TIM2_ITR1 */
#if defined(USB)
#define LL_TIM_TIM2_ITR1_RMP_USB_SOF (TIM2_OR_ITR1_RMP) /* !< TIM2_ITR1 is connected to USB SOF */
#endif /* USB */
@@ -3294,15 +3295,19 @@
* @brief Select the external trigger (ETR) input source.
* @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
* not a timer instance supports ETR source selection.
+ * @note When this function is called with LL_TIM_ETRSOURCE_GPIO,
+ * LL_TIM_ETRSOURCE_ADC1_AWD1, LL_TIM_ETRSOURCE_ADC1_AWD2 or
+ * LL_TIM_ETRSOURCE_ADC1_AWD3, ETR source relies on TIMx ETR remapping
+ * capability configured through the function @ref LL_TIM_SetRemap().
* @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
* @param TIMx Timer instance
* @param ETRSource This parameter can be one of the following values:
* @arg @ref LL_TIM_ETRSOURCE_GPIO
- * @arg @ref LL_TIM_ETRSOURCE_COMP1
- * @arg @ref LL_TIM_ETRSOURCE_COMP2
* @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD1
* @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD2
* @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD3
+ * @arg @ref LL_TIM_ETRSOURCE_COMP1
+ * @arg @ref LL_TIM_ETRSOURCE_COMP2
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
diff --git a/Inc/stm32wbxx_ll_utils.h b/Inc/stm32wbxx_ll_utils.h
index 733cc15..e7c1722 100644
--- a/Inc/stm32wbxx_ll_utils.h
+++ b/Inc/stm32wbxx_ll_utils.h
@@ -18,11 +18,11 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
+ * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
@@ -101,7 +101,7 @@
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
- This parameter must be a number between Min_Data = 8 and Max_Data = 86
+ This parameter must be a number between Min_Data = 6 and Max_Data = 127
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
@@ -195,59 +195,59 @@
/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
* @{
*/
- /**
- * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
- * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
- */
- __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
- {
- return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
- }
+/**
+ * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
+ * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
+ */
+__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
+}
- /**
- * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
- * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
- */
- __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
- {
- return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
- }
+/**
+ * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
+ * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
+ */
+__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
+}
- /**
- * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
- * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
- */
- __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
- {
- return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
- }
+/**
+ * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
+ * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
+ */
+__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
+}
- /**
- * @brief Get Flash memory size
- * @note This bitfield indicates the size of the device Flash memory expressed in
- * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
- * @retval FLASH_SIZE[15:0]: Flash memory size
- */
- __STATIC_INLINE uint32_t LL_GetFlashSize(void)
- {
- return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0x0000FFFFUL);
- }
+/**
+ * @brief Get Flash memory size
+ * @note This bitfield indicates the size of the device Flash memory expressed in
+ * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
+ * @retval FLASH_SIZE[15:0]: Flash memory size
+ */
+__STATIC_INLINE uint32_t LL_GetFlashSize(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0x0000FFFFUL);
+}
- /**
- * @brief Get Package type
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_UTILS_PACKAGETYPE_CSP100
- * @arg @ref LL_UTILS_PACKAGETYPE_CSP100_C
- * @arg @ref LL_UTILS_PACKAGETYPE_QFN68
- * @arg @ref LL_UTILS_PACKAGETYPE_QFN68_C
- * @arg @ref LL_UTILS_PACKAGETYPE_QFN48
- * @arg @ref LL_UTILS_PACKAGETYPE_QFN48_C
- *
- */
- __STATIC_INLINE uint32_t LL_GetPackageType(void)
- {
- return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);
- }
+/**
+ * @brief Get Package type
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_UTILS_PACKAGETYPE_CSP100
+ * @arg @ref LL_UTILS_PACKAGETYPE_CSP100_C
+ * @arg @ref LL_UTILS_PACKAGETYPE_QFN68
+ * @arg @ref LL_UTILS_PACKAGETYPE_QFN68_C
+ * @arg @ref LL_UTILS_PACKAGETYPE_QFN48
+ * @arg @ref LL_UTILS_PACKAGETYPE_QFN48_C
+ *
+ */
+__STATIC_INLINE uint32_t LL_GetPackageType(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);
+}
/**
* @}
diff --git a/Inc/stm32wbxx_ll_wwdg.h b/Inc/stm32wbxx_ll_wwdg.h
index cb6c74b..5bc7d87 100644
--- a/Inc/stm32wbxx_ll_wwdg.h
+++ b/Inc/stm32wbxx_ll_wwdg.h
@@ -58,8 +58,8 @@
*/
/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
-* @{
-*/
+ * @{
+ */
#define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
@@ -183,7 +183,7 @@
* @arg @ref LL_WWDG_PRESCALER_32
* @arg @ref LL_WWDG_PRESCALER_64
* @arg @ref LL_WWDG_PRESCALER_128
-* @retval None
+ * @retval None
*/
__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
{
diff --git a/README.md b/README.md
index da7e715..e9bf315 100644
--- a/README.md
+++ b/README.md
@@ -36,6 +36,7 @@
------------- | --------------- | ---------- | -------------------------------------
Tag v1.1.0 | Tag v1.1.0 | Tag v4.5_cm4 | Tag v1.1.0 (and following, if any, till next new tag)
Tag v1.2.0 | Tag v1.2.0 | Tag v5.4.0_cm4 | Tag v1.2.0 (and following, if any, till next new tag)
+Tag v1.3.0 | Tag v1.3.0 | Tag v5.4.0_cm4 | Tag v1.3.0 (and following, if any, till next new tag)
The full **STM32CubeWB** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeWB).
diff --git a/Release_Notes.html b/Release_Notes.html
index 3613db7..9eb79c7 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -46,9 +46,91 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section3" checked aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.2.0 / 26-June-2019</label>
+<input type="checkbox" id="collapse-section4" checked aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">v1.3.0 / 11-September-2019</label>
<div>
<h2 id="main-changes">Main Changes</h2>
+<h3 id="maitenance-release">Maitenance release</h3>
+<table>
+<thead>
+<tr class="header">
+<th>Peripheral</th>
+<th style="text-align: left;">Headline</th>
+</tr>
+</thead>
+<tbody>
+<tr class="odd">
+<td>CRYP</td>
+<td style="text-align: left;">Document a restriction regarding size field on HAL_CRYP_Encrypt_DMA, HAL_CRYP_Decrypt_DMA API.</td>
+</tr>
+<tr class="even">
+<td>CRYP</td>
+<td style="text-align: left;">Correct several MISRA C:2012 and Code Sonar compliancy improvements.</td>
+</tr>
+<tr class="odd">
+<td>FLASH</td>
+<td style="text-align: left;">Move FLASH_SIZE define from hal flash. h to cmsis device file</td>
+</tr>
+<tr class="even">
+<td>FLASH</td>
+<td style="text-align: left;">Correct ECC management in HAL FLASH driver</td>
+</tr>
+<tr class="odd">
+<td>FLASH</td>
+<td style="text-align: left;">Correct #define in stm32wbxx_hal_flash.h - FLASH_PAGE_NB</td>
+</tr>
+<tr class="even">
+<td>RCC</td>
+<td style="text-align: left;">Correct PLL characteristics</td>
+</tr>
+<tr class="odd">
+<td>TIMER</td>
+<td style="text-align: left;">Add assertion check inside HAL_TIMEx_MasterConfigSynchronization</td>
+</tr>
+<tr class="even">
+<td>TIMER</td>
+<td style="text-align: left;">Make LL_TIM_SetETRSource in line with RM0434</td>
+</tr>
+<tr class="odd">
+<td>WWDG</td>
+<td style="text-align: left;">Correct typical frequency computation description inside the header file</td>
+</tr>
+<tr class="even">
+<td>IRDA</td>
+<td style="text-align: left;">Improve the description of the APIs</td>
+</tr>
+<tr class="odd">
+<td>SMARTCARD</td>
+<td style="text-align: left;">Fix GCC compilation warning</td>
+</tr>
+<tr class="even">
+<td>UART</td>
+<td style="text-align: left;">Correct possible overflow with wordlength = 9bits and NO parity in HAL_UART_Transmit() and HAL_IRDA_Transmit()</td>
+</tr>
+<tr class="odd">
+<td>UART</td>
+<td style="text-align: left;">Fix GCC compilation warning</td>
+</tr>
+<tr class="even">
+<td>USART</td>
+<td style="text-align: left;">Correct possible overflow with wordlength = 9bits and NO parity in HAL_UART_Transmit() and HAL_IRDA_Transmit()</td>
+</tr>
+<tr class="odd">
+<td>USART</td>
+<td style="text-align: left;">Fix GCC compilation warning</td>
+</tr>
+</tbody>
+</table>
+<h2 id="backward-compatibility">Backward Compatibility</h2>
+<p>This release is compatible with the previous versions.</p>
+<h2 id="dependencies">Dependencies</h2>
+<p>This software release is compatible with:</p>
+<p>STM32CubeMX V5.4.0</p>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.2.0 / 26-June-2019</label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
<h3 id="stm32wb50xx-introduction-and-maintenance-release">STM32WB50xx introduction and maintenance release</h3>
<p>First release for STM32WBxx HAL drivers introducing <strong>stm32wb50xx</strong> devices.</p>
<table>
@@ -117,9 +199,9 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility">Backward Compatibility</h2>
+<h2 id="backward-compatibility-1">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
-<h2 id="dependencies">Dependencies</h2>
+<h2 id="dependencies-1">Dependencies</h2>
<p>This software release is compatible with:</p>
<p>STM32CubeMX V5.3.0</p>
</div>
@@ -127,7 +209,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 05-April-2019</label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
<h3 id="maintenance-release">Maintenance release</h3>
<p>Maintenance release of HAL and Low layers drivers supporting STM32WB55xx devices.</p>
<table>
@@ -181,9 +263,9 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-1">Backward Compatibility</h2>
+<h2 id="backward-compatibility-2">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
-<h2 id="dependencies-1">Dependencies</h2>
+<h2 id="dependencies-2">Dependencies</h2>
<p>This software release is compatible with:</p>
<p>STM32CubeMX V5.2.0</p>
</div>
@@ -191,7 +273,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 06-February-2019</label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
<h3 id="first-release">First release</h3>
<p>First official release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32WB55xx.</p>
</div>
diff --git a/Src/stm32wbxx_hal.c b/Src/stm32wbxx_hal.c
index 3d4ce01..8513cb7 100644
--- a/Src/stm32wbxx_hal.c
+++ b/Src/stm32wbxx_hal.c
@@ -56,7 +56,7 @@
* @brief STM32WBxx HAL Driver version number
*/
#define __STM32WBxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
-#define __STM32WBxx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */
+#define __STM32WBxx_HAL_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */
#define __STM32WBxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32WBxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32WBxx_HAL_VERSION ((__STM32WBxx_HAL_VERSION_MAIN << 24U)\
@@ -64,7 +64,9 @@
|(__STM32WBxx_HAL_VERSION_SUB2 << 8U )\
|(__STM32WBxx_HAL_VERSION_RC))
+#if defined(VREFBUF)
#define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms */
+#endif
/**
* @}
@@ -700,7 +702,7 @@
{
LL_VREFBUF_Disable();
}
-#endif
+#endif /* VREFBUF */
/**
* @brief Enable the I/O analog switch voltage booster
diff --git a/Src/stm32wbxx_hal_cryp.c b/Src/stm32wbxx_hal_cryp.c
index 0aa1b00..fab75d4 100644
--- a/Src/stm32wbxx_hal_cryp.c
+++ b/Src/stm32wbxx_hal_cryp.c
@@ -161,18 +161,18 @@
GCM standard specifies that ciphertext has same bit length as the plaintext.
(##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext
(on 64 bits)
-
- [..] A more detailed description of the GCM message structure is available below.
+
+ [..] A more detailed description of the GCM message structure is available below.
[..] This section describe The AES Counter with Cipher Block Chaining-Message
Authentication Code (CCM) supported by both CRYP1 and TinyAES peripheral:
(#) Specific parameters for CCM :
(##) B0 block : follows NIST Special Publication 800-38C,
- (##) B1 block (header)
+ (##) B1 block (header)
(##) CTRx block : control blocks
-
- [..] A detailed description of the CCM message structure is available below.
+
+ [..] A detailed description of the CCM message structure is available below.
(#) Four phases are performed in CCM for CRYP1 peripheral:
(##) Init phase: peripheral prepares the GCM hash subkey (H) and do the IV processing
@@ -189,13 +189,15 @@
(##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.
*** Callback registration ***
- =============================================
+ =============================
+ [..]
The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
to register an interrupt callback.
+ [..]
Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks:
(+) InCpltCallback : Input FIFO transfer completed callback.
(+) OutCpltCallback : Output FIFO transfer completed callback.
@@ -205,6 +207,7 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
+ [..]
Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default
weak function.
@ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
@@ -216,6 +219,7 @@
(+) MspInitCallback : CRYP MspInit.
(+) MspDeInitCallback : CRYP MspDeInit.
+ [..]
By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
all callbacks are set to the corresponding weak functions :
examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback().
@@ -225,6 +229,7 @@
if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit()
keep and use the user MspInit/MspDeInit functions (registered beforehand)
+ [..]
Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only.
Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
@@ -233,14 +238,16 @@
using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit()
or @ref HAL_CRYP_Init() function.
+ [..]
When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
*** Suspend/Resume feature ***
- =============================================
+ ==============================
+ [..]
The compilation define USE_HAL_CRYP_SUSPEND_RESUME when set to 1
allows the user to resort to the suspend/resume feature.
A low priority block processing can be suspended to process a high priority block
@@ -915,11 +922,15 @@
*/
HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp)
{
+ HAL_CRYP_STATETypeDef state;
+
/* Request suspension */
HAL_CRYP_ProcessSuspend(hcryp);
- while ((HAL_CRYP_GetState(hcryp) != HAL_CRYP_STATE_SUSPENDED) && \
- (HAL_CRYP_GetState(hcryp) != HAL_CRYP_STATE_READY));
+ do
+ {
+ state = HAL_CRYP_GetState(hcryp);
+ } while ((state != HAL_CRYP_STATE_SUSPENDED) && (state != HAL_CRYP_STATE_READY));
if (HAL_CRYP_GetState(hcryp) == HAL_CRYP_STATE_READY)
{
@@ -953,7 +964,7 @@
hcryp->CrypOutCount_saved = hcryp->CrypOutCount;
hcryp->Phase_saved = hcryp->Phase;
hcryp->State_saved = hcryp->State;
- hcryp->Size_saved = ( (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) ? hcryp->Size /4 : hcryp->Size);
+ hcryp->Size_saved = ( (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) ? (hcryp->Size /4U) : hcryp->Size);
hcryp->AutoKeyDerivation_saved = hcryp->AutoKeyDerivation;
hcryp->CrypHeaderCount_saved = hcryp->CrypHeaderCount;
hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
@@ -983,6 +994,12 @@
*/
HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp)
{
+ /* Check the CRYP handle allocation */
+ if (hcryp == NULL)
+ {
+ return HAL_ERROR;
+ }
+
if (hcryp->State_saved != HAL_CRYP_STATE_SUSPENDED)
{
/* CRYP was not suspended */
@@ -1009,10 +1026,7 @@
hcryp->Init.pInitVect = hcryp->IV_saved;
}
__HAL_CRYP_DISABLE(hcryp);
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
+ (void) HAL_CRYP_Init(hcryp);
}
else /* Authentication algorithms case */
{
@@ -1180,6 +1194,12 @@
{
uint32_t algo;
HAL_StatusTypeDef status;
+#ifdef USE_FULL_ASSERT
+ uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
+
+ /* Check input buffer size */
+ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
+#endif
if (hcryp->State == HAL_CRYP_STATE_READY)
{
@@ -1274,6 +1294,12 @@
{
HAL_StatusTypeDef status;
uint32_t algo;
+#ifdef USE_FULL_ASSERT
+ uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
+
+ /* Check input buffer size */
+ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
+#endif
if (hcryp->State == HAL_CRYP_STATE_READY)
{
@@ -1367,6 +1393,12 @@
{
HAL_StatusTypeDef status;
uint32_t algo;
+#ifdef USE_FULL_ASSERT
+ uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
+
+ /* Check input buffer size */
+ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
+#endif
if (hcryp->State == HAL_CRYP_STATE_READY)
{
@@ -1383,8 +1415,8 @@
hcryp->ResumingFlag = 0U;
if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED)
{
- hcryp->CrypInCount = hcryp->CrypInCount_saved;
- hcryp->CrypOutCount = hcryp->CrypOutCount_saved;
+ hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved;
+ hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved;
}
else
{
@@ -1471,6 +1503,12 @@
{
HAL_StatusTypeDef status;
uint32_t algo;
+#ifdef USE_FULL_ASSERT
+ uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
+
+ /* Check input buffer size */
+ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
+#endif
if (hcryp->State == HAL_CRYP_STATE_READY)
{
@@ -1487,8 +1525,8 @@
hcryp->ResumingFlag = 0U;
if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED)
{
- hcryp->CrypInCount = hcryp->CrypInCount_saved;
- hcryp->CrypOutCount = hcryp->CrypOutCount_saved;
+ hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved;
+ hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved;
}
else
{
@@ -1575,6 +1613,12 @@
HAL_StatusTypeDef status;
uint32_t algo;
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+#ifdef USE_FULL_ASSERT
+ uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
+
+ /* Check input buffer size */
+ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
+#endif
if (hcryp->State == HAL_CRYP_STATE_READY)
{
@@ -1695,6 +1739,12 @@
{
HAL_StatusTypeDef status;
uint32_t algo;
+#ifdef USE_FULL_ASSERT
+ uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
+
+ /* Check input buffer size */
+ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
+#endif
if (hcryp->State == HAL_CRYP_STATE_READY)
{
@@ -5015,7 +5065,7 @@
__IO uint32_t count = 0U;
/* In case of GCM payload phase encryption, check that suspension can be carried out */
- if (READ_BIT(hcryp->Instance->CR, (AES_CR_CHMOD|AES_CR_GCMPH|AES_CR_MODE)) == (CRYP_AES_GCM_GMAC|AES_CR_GCMPH_1|0x0))
+ if (READ_BIT(hcryp->Instance->CR, (AES_CR_CHMOD|AES_CR_GCMPH|AES_CR_MODE)) == (CRYP_AES_GCM_GMAC|AES_CR_GCMPH_1|0x0U))
{
/* Wait for BUSY flag to be cleared */
@@ -5153,21 +5203,21 @@
if (KeySize == CRYP_KEYSIZE_256B)
{
hcryp->Instance->KEYR7 = *(uint32_t*)(keyaddr);
- keyaddr+=4;
+ keyaddr+=4U;
hcryp->Instance->KEYR6 = *(uint32_t*)(keyaddr);
- keyaddr+=4;
+ keyaddr+=4U;
hcryp->Instance->KEYR5 = *(uint32_t*)(keyaddr);
- keyaddr+=4;
+ keyaddr+=4U;
hcryp->Instance->KEYR4 = *(uint32_t*)(keyaddr);
- keyaddr+=4;
+ keyaddr+=4U;
}
hcryp->Instance->KEYR3 = *(uint32_t*)(keyaddr);
- keyaddr+=4;
+ keyaddr+=4U;
hcryp->Instance->KEYR2 = *(uint32_t*)(keyaddr);
- keyaddr+=4;
+ keyaddr+=4U;
hcryp->Instance->KEYR1 = *(uint32_t*)(keyaddr);
- keyaddr+=4;
+ keyaddr+=4U;
hcryp->Instance->KEYR0 = *(uint32_t*)(keyaddr);
}
@@ -5179,9 +5229,10 @@
*/
static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp)
{
- uint32_t loopcounter = 0U;
- uint32_t lastwordsize =0;
- uint32_t npblb = 0U ;
+ uint32_t loopcounter;
+ uint16_t lastwordsize;
+ uint16_t npblb;
+ uint32_t cr_temp;
/* Case of header phase resumption =================================================*/
if (hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED)
@@ -5192,7 +5243,7 @@
/* Select header phase */
CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
- if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount) >= 4U))
+ if ((((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U))
{
/* Write the input block in the IN FIFO */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
@@ -5221,73 +5272,77 @@
}
}
/* Case of payload phase resumption =================================================*/
- else if (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)
+ else
{
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Select payload phase once the header phase is performed */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
-
- /* Set to 0 the number of non-valid bytes using NPBLB register*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
-
- if ((hcryp->Size/4) - (hcryp->CrypInCount) >= 4U)
+ if (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)
{
- /* Write the input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- if((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC))
- {
- /* Call output transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
- /*Call registered Input complete callback*/
- hcryp->InCpltCallback(hcryp);
-#else
- /*Call legacy weak Input complete callback*/
- HAL_CRYP_InCpltCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
- }
- else /* Last block of payload < 128bit*/
- {
- /* Compute the number of padding bytes in last block of payload */
- npblb = ((hcryp->Size/16U)+1U)*16U- (hcryp->Size);
- if((((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
- (((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
- {
- /* Specify the number of non-valid bytes using NPBLB register*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb<< 20U);
- }
- /* Number of valid words (lastwordsize) in last block */
- if (npblb % 4U ==0U)
- {
- lastwordsize = (16U-npblb)/4U;
- }
- else
- {
- lastwordsize = (16U-npblb)/4U +1U;
- }
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
- /* Last block optionally pad the data with zeros*/
- for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+ /* Select payload phase once the header phase is performed */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
+
+ /* Set to 0 the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
+
+ if (((hcryp->Size/4U) - (hcryp->CrypInCount)) >= 4U)
{
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ if((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC))
+ {
+ /* Call output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
}
- while(loopcounter < 4U )
+ else /* Last block of payload < 128bit*/
{
- /* pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0x0U;
- loopcounter++;
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = (((hcryp->Size/16U)+1U)*16U) - (hcryp->Size);
+ cr_temp = hcryp->Instance->CR;
+ if((((cr_temp & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
+ (((cr_temp& AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
+ {
+ /* Specify the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, ((uint32_t)npblb)<< 20U);
+ }
+
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) ==0U)
+ {
+ lastwordsize = (16U-npblb)/4U;
+ }
+ else
+ {
+ lastwordsize = ((16U-npblb)/4U) +1U;
+ }
+
+ /* Last block optionally pad the data with zeros*/
+ for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ }
+ while(loopcounter < 4U )
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
}
}
}
diff --git a/Src/stm32wbxx_hal_flash.c b/Src/stm32wbxx_hal_flash.c
index 237ce6b..ab3de96 100644
--- a/Src/stm32wbxx_hal_flash.c
+++ b/Src/stm32wbxx_hal_flash.c
@@ -269,7 +269,7 @@
pFlash.Address = Address;
/* Enable End of Operation and Error interrupts */
- __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR | FLASH_IT_ECCC);
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
{
@@ -302,13 +302,11 @@
uint32_t param = 0xFFFFFFFFU;
uint32_t error;
- /* Save flash errors. Only ECC detection can be checked here as ECCC
- generates NMI */
- error = (FLASH->SR & FLASH_FLAG_SR_ERROR);
+ /* Check FLASH operation error flags */
+ error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);
/* Clear Current operation */
CLEAR_BIT(FLASH->CR, pFlash.ProcedureOnGoing);
- error |= (FLASH->ECCR & FLASH_FLAG_ECCC);
/* A] Set parameter for user or error callbacks */
/* check operation was a program or erase */
@@ -381,7 +379,7 @@
if (pFlash.ProcedureOnGoing == FLASH_TYPENONE)
{
/* Disable End of Operation and Error interrupts */
- __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR | FLASH_IT_ECCC);
+ __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
@@ -581,7 +579,6 @@
* @arg @ref HAL_FLASH_ERROR_FAST FLASH Fast programming error
* @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error (PCROP)
* @arg @ref HAL_FLASH_ERROR_OPTV FLASH Option validity error
- * @arg @ref HAL_FLASH_ERROR_ECCD FLASH two ECC errors have been detected
*/
uint32_t HAL_FLASH_GetError(void)
{
@@ -623,8 +620,7 @@
}
}
- /* check flash errors. Only ECC correction can be checked here as ECCD
- generates NMI */
+ /* Check FLASH operation error flags */
error = FLASH->SR;
/* Check FLASH End of Operation flag */
@@ -635,10 +631,7 @@
}
/* Now update error variable to only error value */
- error &= FLASH_FLAG_SR_ERROR;
-
- /* Update error with ECC error value */
- error |= (FLASH->ECCR & FLASH_FLAG_ECCC);
+ error &= FLASH_FLAG_SR_ERRORS;
/* clear error flags */
__HAL_FLASH_CLEAR_FLAG(error);
diff --git a/Src/stm32wbxx_hal_irda.c b/Src/stm32wbxx_hal_irda.c
index b931497..6768dcf 100644
--- a/Src/stm32wbxx_hal_irda.c
+++ b/Src/stm32wbxx_hal_irda.c
@@ -782,10 +782,13 @@
/**
* @brief Send an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be sent.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
* @param Timeout Specify timeout value.
* @retval HAL status
*/
@@ -868,10 +871,13 @@
/**
* @brief Receive an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @param Timeout Specify timeout value.
* @retval HAL status
*/
@@ -956,10 +962,13 @@
/**
* @brief Send an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be sent.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@@ -998,10 +1007,13 @@
/**
* @brief Receive an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@@ -1047,10 +1059,13 @@
/**
* @brief Send an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be sent.
+ * @param pData pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@@ -1122,12 +1137,15 @@
/**
* @brief Receive an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
* @note When the IRDA parity is enabled (PCE = 1), the received data contains
* the parity bit (MSB position).
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
diff --git a/Src/stm32wbxx_hal_pwr.c b/Src/stm32wbxx_hal_pwr.c
index 4aec8eb..af8a039 100644
--- a/Src/stm32wbxx_hal_pwr.c
+++ b/Src/stm32wbxx_hal_pwr.c
@@ -560,6 +560,8 @@
* startup delay is incurred when waking up.
* By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
* is higher although the startup time is reduced.
+ * @note Case of Stop0 mode with SMPS: Before entering Stop 0 mode with SMPS Step Down converter enabled,
+ * the HSI16 must be kept on by enabling HSI kernel clock (set HSIKERON register bit).
* @note According to system power policy, system entering in Stop mode
* is depending on other CPU power mode.
* @param Regulator Specifies the regulator state in Stop mode.
diff --git a/Src/stm32wbxx_hal_pwr_ex.c b/Src/stm32wbxx_hal_pwr_ex.c
index 93554f6..3b394c6 100644
--- a/Src/stm32wbxx_hal_pwr_ex.c
+++ b/Src/stm32wbxx_hal_pwr_ex.c
@@ -1089,6 +1089,8 @@
* is set; the MSI oscillator is selected if STOPWUCK is cleared.
* @note By keeping the internal regulator ON during Stop 0 mode, the consumption
* is higher although the startup time is reduced.
+ * @note Case of Stop0 mode with SMPS: Before entering Stop 0 mode with SMPS Step Down converter enabled,
+ * the HSI16 must be kept on by enabling HSI kernel clock (set HSIKERON register bit).
* @note According to system power policy, system entering in Stop mode
* is depending on other CPU power mode.
* @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
@@ -1197,6 +1199,15 @@
* @note When exiting Stop 2 mode by issuing an interrupt or a wakeup event,
* the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
* is set; the MSI oscillator is selected if STOPWUCK is cleared.
+ * @note Case of Stop2 mode and debugger probe attached: a workaround should be applied.
+ * Issue specified in "ES0394 - STM32WB55Cx/Rx/Vx device errata":
+ * 2.2.9 Incomplete Stop 2 mode entry after a wakeup from debug upon EXTI line 48 event
+ * "With the JTAG debugger enabled on GPIO pins and after a wakeup from debug triggered by an event on EXTI
+ * line 48 (CDBGPWRUPREQ), the device may enter in a state in which attempts to enter Stop 2 mode are not fully
+ * effective ..."
+ * Workaround implementation example using LL driver:
+ * LL_EXTI_DisableIT_32_63(LL_EXTI_LINE_48);
+ * LL_C2_EXTI_DisableIT_32_63(LL_EXTI_LINE_48);
* @note According to system power policy, system entering in Stop mode
* is depending on other CPU power mode.
* @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
diff --git a/Src/stm32wbxx_hal_smartcard.c b/Src/stm32wbxx_hal_smartcard.c
index 954da87..a24a035 100644
--- a/Src/stm32wbxx_hal_smartcard.c
+++ b/Src/stm32wbxx_hal_smartcard.c
@@ -917,7 +917,7 @@
return HAL_TIMEOUT;
}
*ptmpdata = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF);
- *ptmpdata++;
+ ptmpdata++;
}
/* At end of Rx process, restore hsmartcard->RxState to Ready */
diff --git a/Src/stm32wbxx_hal_tim.c b/Src/stm32wbxx_hal_tim.c
index 9ebfa33..eeec812 100644
--- a/Src/stm32wbxx_hal_tim.c
+++ b/Src/stm32wbxx_hal_tim.c
@@ -2632,8 +2632,8 @@
assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
- assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
- assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
+ assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
+ assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
diff --git a/Src/stm32wbxx_hal_tim_ex.c b/Src/stm32wbxx_hal_tim_ex.c
index 2504060..503cb0c 100644
--- a/Src/stm32wbxx_hal_tim_ex.c
+++ b/Src/stm32wbxx_hal_tim_ex.c
@@ -1647,7 +1647,7 @@
uint32_t tmpsmcr;
/* Check the parameters */
- assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
@@ -1680,16 +1680,19 @@
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
- /* Reset the MSM Bit */
- tmpsmcr &= ~TIM_SMCR_MSM;
- /* Set master mode */
- tmpsmcr |= sMasterConfig->MasterSlaveMode;
-
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
- /* Update TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ /* Reset the MSM Bit */
+ tmpsmcr &= ~TIM_SMCR_MSM;
+ /* Set master mode */
+ tmpsmcr |= sMasterConfig->MasterSlaveMode;
+
+ /* Update TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+ }
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
diff --git a/Src/stm32wbxx_hal_uart.c b/Src/stm32wbxx_hal_uart.c
index de225f7..22e88e6 100644
--- a/Src/stm32wbxx_hal_uart.c
+++ b/Src/stm32wbxx_hal_uart.c
@@ -1075,6 +1075,8 @@
pdata16bits = NULL;
}
+ __HAL_UNLOCK(huart);
+
while (huart->TxXferCount > 0U)
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
@@ -1102,8 +1104,6 @@
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
- __HAL_UNLOCK(huart);
-
return HAL_OK;
}
else
@@ -1169,6 +1169,8 @@
pdata16bits = NULL;
}
+ __HAL_UNLOCK(huart);
+
/* as long as data have to be received */
while (huart->RxXferCount > 0U)
{
@@ -1192,8 +1194,6 @@
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
- __HAL_UNLOCK(huart);
-
return HAL_OK;
}
else
diff --git a/Src/stm32wbxx_hal_usart.c b/Src/stm32wbxx_hal_usart.c
index a17bd51..e6c7363 100644
--- a/Src/stm32wbxx_hal_usart.c
+++ b/Src/stm32wbxx_hal_usart.c
@@ -732,9 +732,12 @@
/**
* @brief Simplex send an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pTxData.
* @param husart USART handle.
- * @param pTxData Pointer to data buffer.
- * @param Size Amount of data to be sent.
+ * @param pTxData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
* @param Timeout Timeout duration.
* @retval HAL status
*/
@@ -826,10 +829,13 @@
/**
* @brief Receive an amount of data in blocking mode.
- * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pRxData.
* @param husart USART handle.
- * @param pRxData Pointer to data buffer.
- * @param Size Amount of data to be received.
+ * @param pRxData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @param Timeout Timeout duration.
* @retval HAL status
*/
@@ -936,10 +942,13 @@
/**
* @brief Full-Duplex Send and Receive an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+ * of u16 available through pTxData and through pRxData.
* @param husart USART handle.
- * @param pTxData pointer to TX data buffer.
- * @param pRxData pointer to RX data buffer.
- * @param Size amount of data to be sent (same amount to be received).
+ * @param pTxData pointer to TX data buffer (u8 or u16 data elements).
+ * @param pRxData pointer to RX data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received).
* @param Timeout Timeout duration.
* @retval HAL status
*/
@@ -1082,9 +1091,12 @@
/**
* @brief Send an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pTxData.
* @param husart USART handle.
- * @param pTxData pointer to data buffer.
- * @param Size amount of data to be sent.
+ * @param pTxData pointer to data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
@@ -1162,10 +1174,13 @@
/**
* @brief Receive an amount of data in interrupt mode.
- * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pRxData.
* @param husart USART handle.
- * @param pRxData pointer to data buffer.
- * @param Size amount of data to be received.
+ * @param pRxData pointer to data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
@@ -1264,10 +1279,13 @@
/**
* @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+ * of u16 available through pTxData and through pRxData.
* @param husart USART handle.
- * @param pTxData pointer to TX data buffer.
- * @param pRxData pointer to RX data buffer.
- * @param Size amount of data to be sent (same amount to be received).
+ * @param pTxData pointer to TX data buffer (u8 or u16 data elements).
+ * @param pRxData pointer to RX data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
@@ -1359,9 +1377,12 @@
/**
* @brief Send an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pTxData.
* @param husart USART handle.
- * @param pTxData pointer to data buffer.
- * @param Size amount of data to be sent.
+ * @param pTxData pointer to data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
@@ -1441,10 +1462,13 @@
* @brief Receive an amount of data in DMA mode.
* @note When the USART parity is enabled (PCE = 1), the received data contain
* the parity bit (MSB position).
- * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
+ * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pRxData.
* @param husart USART handle.
- * @param pRxData pointer to data buffer.
- * @param Size amount of data to be received.
+ * @param pRxData pointer to data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
@@ -1556,10 +1580,13 @@
/**
* @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
* @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+ * of u16 available through pTxData and through pRxData.
* @param husart USART handle.
- * @param pTxData pointer to TX data buffer.
- * @param pRxData pointer to RX data buffer.
- * @param Size amount of data to be received/sent.
+ * @param pTxData pointer to TX data buffer (u8 or u16 data elements).
+ * @param pRxData pointer to RX data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be received/sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
@@ -3061,7 +3088,7 @@
else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET)
{
husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF);
- *husart->pTxBuffPtr++;
+ husart->pTxBuffPtr++;
husart->TxXferCount--;
}
else
diff --git a/Src/stm32wbxx_hal_wwdg.c b/Src/stm32wbxx_hal_wwdg.c
index a4d72de..1195476 100644
--- a/Src/stm32wbxx_hal_wwdg.c
+++ b/Src/stm32wbxx_hal_wwdg.c
@@ -32,10 +32,10 @@
(++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
(++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
(+) Typical values:
- (++) Counter min (T[5;0] = 0x00) @56 MHz(PCLK1) with zero prescaler:
- max timeout before reset: approximately 73.14 microseconds
- (++) Counter max (T[5;0] = 0x3F) @56 MHz(PCLK1) with prescaler dividing by 128:
- max timeout before reset: approximately 599.18 milliseconds
+ (++) Counter min (T[5;0] = 0x00) @64 MHz (PCLK1) with zero prescaler:
+ max timeout before reset: approximately 64µs
+ (++) Counter max (T[5;0] = 0x3F) @64 MHz (PCLK1) with prescaler dividing by 128:
+ max timeout before reset: approximately 524.28ms
==============================================================================
##### How to use this driver #####
@@ -85,13 +85,13 @@
[..]
When calling @ref HAL_WWDG_Init function, callbacks are reset to the
- corresponding legacy weak (surcharged) functions:
+ corresponding legacy weak (surcharged) functions:
@ref HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
not been registered before.
[..]
When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registering feature is not available
+ not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
*** WWDG HAL driver macros list ***
@@ -143,8 +143,8 @@
*/
/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions.
- *
+ * @brief Initialization and Configuration functions.
+ *
@verbatim
==============================================================================
##### Initialization and Configuration functions #####
@@ -183,12 +183,12 @@
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
/* Reset Callback pointers */
- if(hwwdg->EwiCallback == NULL)
+ if (hwwdg->EwiCallback == NULL)
{
hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
}
- if(hwwdg->MspInitCallback == NULL)
+ if (hwwdg->MspInitCallback == NULL)
{
hwwdg->MspInitCallback = HAL_WWDG_MspInit;
}
@@ -247,13 +247,13 @@
{
HAL_StatusTypeDef status = HAL_OK;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
status = HAL_ERROR;
}
else
{
- switch(CallbackID)
+ switch (CallbackID)
{
case HAL_WWDG_EWI_CB_ID:
hwwdg->EwiCallback = pCallback;
@@ -275,7 +275,7 @@
/**
* @brief Unregister a WWDG Callback
- * WWDG Callback is redirected to the weak (surcharged) predefined callback
+ * WWDG Callback is redirected to the weak (surcharged) predefined callback
* @param hwwdg WWDG handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -287,7 +287,7 @@
{
HAL_StatusTypeDef status = HAL_OK;
- switch(CallbackID)
+ switch (CallbackID)
{
case HAL_WWDG_EWI_CB_ID:
hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
@@ -311,8 +311,8 @@
*/
/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
- *
+ * @brief IO operation functions
+ *
@verbatim
==============================================================================
##### IO operation functions #####
diff --git a/Src/stm32wbxx_ll_utils.c b/Src/stm32wbxx_ll_utils.c
index ec56897..ce9cbc1 100644
--- a/Src/stm32wbxx_ll_utils.c
+++ b/Src/stm32wbxx_ll_utils.c
@@ -6,11 +6,11 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
+ * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
@@ -47,9 +47,9 @@
#endif
/* Defines used for PLL range */
-#define UTILS_PLLVCO_INPUT_MIN 4000000U /*!< Frequency min for PLLVCO input, in Hz */
-#define UTILS_PLLVCO_INPUT_MAX 16000000U /*!< Frequency max for PLLVCO input, in Hz */
-#define UTILS_PLLVCO_OUTPUT_MIN 64000000U /*!< Frequency min for PLLVCO output, in Hz */
+#define UTILS_PLLVCO_INPUT_MIN 2660000U /*!< Frequency min for PLLVCO input, in Hz */
+#define UTILS_PLLVCO_INPUT_MAX 16000000U /*!< Frequency max for PLLVCO input, in Hz */
+#define UTILS_PLLVCO_OUTPUT_MIN 96000000U /*!< Frequency min for PLLVCO output, in Hz */
#define UTILS_PLLVCO_OUTPUT_MAX 344000000U /*!< Frequency max for PLLVCO output, in Hz */
/* Defines used for HCLK2 frequency check */
@@ -99,7 +99,7 @@
|| ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_8))
-#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
+#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U))
#define IS_LL_UTILS_PLLR_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLR_DIV_2) \
|| ((__VALUE__) == LL_RCC_PLLR_DIV_3) \
@@ -131,10 +131,10 @@
/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
* @{
*/
- static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
- static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK4_Frequency);
- static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
- static ErrorStatus UTILS_PLL_IsBusy(void);
+static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
+static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK4_Frequency);
+static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+static ErrorStatus UTILS_PLL_IsBusy(void);
/**
* @}
@@ -210,10 +210,10 @@
[..]
System, HCLK1, HCLK2, AHBS, AHBRF and APB buses clocks configuration
- (+) The maximum frequency of the SYSCLK, HCLK1, HCLK4, PCLK1 and PCLK2
+ (+) The maximum frequency of the SYSCLK, HCLK1, HCLK4, PCLK1 and PCLK2
is 640000000 Hz.
....... (+) The maximum frequency of the HCLK2 is 320000000 Hz.
-
+
@endverbatim
@internal
Depending on the device voltage range, the maximum frequency should be
@@ -236,7 +236,7 @@
@endinternal
* @{
*/
-
+
/**
* @brief This function sets directly SystemCoreClock CMSIS variable.
* @note Variable can be calculated also through SystemCoreClockUpdate function.
@@ -257,8 +257,8 @@
* @note The application needs to ensure that BUS prescalers are valid
* @note Function is based on the following formula:
* - PLL output frequency = (((MSI frequency / PLLM) * PLLN) / PLLR)
- * - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = MSI frequency / PLLM)
- * - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
+ * - PLLM: ensure that the VCO input frequency ranges from 2.66 to 16 MHz (PLLVCO_input = MSI frequency / PLLM)
+ * - PLLN: ensure that the VCO output frequency is between 96 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
* - PLLR: ensure that max frequency at 64000000 Hz is reached (PLLVCO_output / PLLR)
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
* the configuration information for the PLL.
@@ -275,7 +275,7 @@
uint32_t pllrfreq, hclk2freq, msi_range;
/* Check if one of the PLL is enabled */
- if(UTILS_PLL_IsBusy() == SUCCESS)
+ if (UTILS_PLL_IsBusy() == SUCCESS)
{
/* Get the current MSI range & check coherency */
msi_range = LL_RCC_MSI_GetRange();
@@ -287,7 +287,7 @@
case LL_RCC_MSIRANGE_3: /* MSI = 800 KHz */
case LL_RCC_MSIRANGE_4: /* MSI = 1 MHz */
case LL_RCC_MSIRANGE_5: /* MSI = 2 MHz */
- /* PLLVCO input frequency can not in the range from 4 to 16 MHz*/
+ /* PLLVCO input frequency can not in the range from 2.66 to 16 MHz*/
status = ERROR;
break;
@@ -304,9 +304,9 @@
/* PLL is ready, MSI range is valid and HCLK2 frequency is coherent
Main PLL configuration and activation */
- if(status != ERROR)
+ if (status != ERROR)
{
- /* Calculate the new PLL output frequency & verify all PLL stages are correct (VCO input ranges,
+ /* Calculate the new PLL output frequency & verify all PLL stages are correct (VCO input ranges,
VCO output ranges & SYSCLK max) when assert activated */
pllrfreq = UTILS_GetPLLOutputFrequency(__LL_RCC_CALC_MSI_FREQ(msi_range), UTILS_PLLInitStruct);
hclk2freq = __LL_RCC_CALC_HCLK2_FREQ(pllrfreq, UTILS_ClkInitStruct->CPU2CLKDivider);
@@ -321,7 +321,7 @@
{
/* Enable MSI if not enabled */
- if(LL_RCC_MSI_IsReady() != 1U)
+ if (LL_RCC_MSI_IsReady() != 1U)
{
LL_RCC_MSI_Enable();
while ((LL_RCC_MSI_IsReady() != 1U))
@@ -355,8 +355,8 @@
* @note The application needs to ensure that BUS prescalers are valid
* @note Function is based on the following formula:
* - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLR)
- * - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)
- * - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
+ * - PLLM: ensure that the VCO input frequency ranges from 2.66 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)
+ * - PLLN: ensure that the VCO output frequency is between 96 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
* - PLLR: ensure that max frequency at 64000000 Hz is reach (PLLVCO_output / PLLR)
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
* the configuration information for the PLL.
@@ -373,7 +373,7 @@
uint32_t pllrfreq, hclk2freq;
/* Check if one of the PLL is enabled */
- if(UTILS_PLL_IsBusy() == SUCCESS)
+ if (UTILS_PLL_IsBusy() == SUCCESS)
{
/* Calculate the new PLL output frequency */
pllrfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
@@ -388,7 +388,7 @@
else
{
/* Enable HSI if not enabled */
- if(LL_RCC_HSI_IsReady() != 1U)
+ if (LL_RCC_HSI_IsReady() != 1U)
{
LL_RCC_HSI_Enable();
while (LL_RCC_HSI_IsReady() != 1U)
@@ -400,7 +400,7 @@
/* Configure PLL */
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
UTILS_PLLInitStruct->PLLR);
-
+
/* Enable PLL and switch system clock to PLL */
status = UTILS_EnablePLLAndSwitchSystem(pllrfreq, UTILS_ClkInitStruct);
}
@@ -421,8 +421,8 @@
* @note The application needs to ensure that BUS prescalers are valid
* @note Function is based on the following formula:
* - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLR)
- * - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSE frequency / PLLM)
- * - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
+ * - PLLM: ensure that the VCO input frequency ranges from 2.66 to 16 MHz (PLLVCO_input = HSE frequency / PLLM)
+ * - PLLN: ensure that the VCO output frequency is between 96 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
* - PLLR: ensure that max frequency at 64000000 Hz is reached (PLLVCO_output / PLLR)
* @param HSEBypass This parameter can be one of the following values:
* @arg @ref LL_UTILS_HSEBYPASS_ON
@@ -435,7 +435,7 @@
* - SUCCESS: Max frequency configuration done
* - ERROR: Max frequency configuration not done
*/
-ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEBypass,LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
ErrorStatus status;
uint32_t pllrfreq, hclk2freq;
@@ -444,7 +444,7 @@
assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
/* Check if one of the PLL is enabled */
- if(UTILS_PLL_IsBusy() == SUCCESS)
+ if (UTILS_PLL_IsBusy() == SUCCESS)
{
/* Calculate the new PLL output frequency */
pllrfreq = UTILS_GetPLLOutputFrequency(HSE_VALUE, UTILS_PLLInitStruct);
@@ -460,10 +460,10 @@
{
/* Enable HSE if not enabled */
- if(LL_RCC_HSE_IsReady() != 1U)
+ if (LL_RCC_HSE_IsReady() != 1U)
{
/* Check if need to enable HSE bypass feature or not */
- if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
+ if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
{
LL_RCC_HSE_EnableBypass();
}
@@ -528,27 +528,27 @@
/* Flash Clock source (HCLK4) range in MHz with a VCORE is range1 */
const uint32_t UTILS_CLK_SRC_RANGE_VOS1[] = {18000000U, 36000000U, 54000000U, UTILS_MAX_FREQUENCY_SCALE1};
- #if defined(PWR_CR1_VOS)
+#if defined(PWR_CR1_VOS)
/* Flash Clock source (HCLK4) range in MHz with a VCORE is range2 */
const uint32_t UTILS_CLK_SRC_RANGE_VOS2[] = {6000000U, 12000000U, UTILS_MAX_FREQUENCY_SCALE2};
- #endif
-
+#endif
+
/* Flash Latency range */
const uint32_t UTILS_LATENCY_RANGE[] = {LL_FLASH_LATENCY_0, LL_FLASH_LATENCY_1, LL_FLASH_LATENCY_2, LL_FLASH_LATENCY_3};
/* Frequency cannot be equal to 0 */
- if(HCLK4_Frequency == 0U)
+ if (HCLK4_Frequency == 0U)
{
status = ERROR;
}
else
{
- #if defined(PWR_CR1_VOS)
- if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
+#if defined(PWR_CR1_VOS)
+ if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
{
- for(index = 0; index < countof(UTILS_CLK_SRC_RANGE_VOS1); index++)
+ for (index = 0; index < countof(UTILS_CLK_SRC_RANGE_VOS1); index++)
{
- if(HCLK4_Frequency <= UTILS_CLK_SRC_RANGE_VOS1[index])
+ if (HCLK4_Frequency <= UTILS_CLK_SRC_RANGE_VOS1[index])
{
latency = UTILS_LATENCY_RANGE[index];
break;
@@ -557,25 +557,25 @@
}
else /* SCALE2 */
{
- for(index = 0; index < countof(UTILS_CLK_SRC_RANGE_VOS2); index++)
+ for (index = 0; index < countof(UTILS_CLK_SRC_RANGE_VOS2); index++)
{
- if(HCLK4_Frequency <= UTILS_CLK_SRC_RANGE_VOS2[index])
+ if (HCLK4_Frequency <= UTILS_CLK_SRC_RANGE_VOS2[index])
{
latency = UTILS_LATENCY_RANGE[index];
break;
}
}
}
- #else
- for(index = 0; index < countof(UTILS_CLK_SRC_RANGE_VOS1); index++)
+#else
+ for (index = 0; index < countof(UTILS_CLK_SRC_RANGE_VOS1); index++)
{
- if(HCLK4_Frequency <= UTILS_CLK_SRC_RANGE_VOS1[index])
+ if (HCLK4_Frequency <= UTILS_CLK_SRC_RANGE_VOS1[index])
{
latency = UTILS_LATENCY_RANGE[index];
break;
}
}
- #endif
+#endif
LL_FLASH_SetLatency(latency);
@@ -605,11 +605,11 @@
assert_param(IS_LL_UTILS_PLLR_VALUE(UTILS_PLLInitStruct->PLLR));
/* Check different PLL parameters according to RM */
- /* - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz. */
+ /* - PLLM: ensure that the VCO input frequency ranges from 2.66 to 16 MHz. */
pllfreq = PLL_InputFrequency / (((UTILS_PLLInitStruct->PLLM >> RCC_PLLCFGR_PLLM_Pos) + 1U));
assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
- /* - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz.*/
+ /* - PLLN: ensure that the VCO output frequency is between 96 and 344 MHz.*/
pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
@@ -631,14 +631,14 @@
ErrorStatus status = SUCCESS;
/* Check if PLL is busy*/
- if(LL_RCC_PLL_IsReady() != 0U)
+ if (LL_RCC_PLL_IsReady() != 0U)
{
/* PLL configuration cannot be modified */
status = ERROR;
}
#if defined(SAI1)
/* Check if PLLSAI1 is busy*/
- if(LL_RCC_PLLSAI1_IsReady() != 0U)
+ if (LL_RCC_PLLSAI1_IsReady() != 0U)
{
/* PLLSAI1 configuration cannot be modified */
status = ERROR;
@@ -676,14 +676,14 @@
hclks_frequency_current = __LL_RCC_CALC_HCLK4_FREQ(sysclk_current, LL_RCC_GetAHB4Prescaler());
/* Increasing the number of wait states because of higher CPU frequency */
- if(hclks_frequency_current < hclks_frequency_target)
+ if (hclks_frequency_current < hclks_frequency_target)
{
/* Set FLASH latency to highest latency */
status = UTILS_SetFlashLatency(hclks_frequency_target);
}
/* Update system clock configuration */
- if(status == SUCCESS)
+ if (status == SUCCESS)
{
/* Enable PLL */
LL_RCC_PLL_Enable();
@@ -707,16 +707,16 @@
LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
}
-
+
/* Decreasing the number of wait states because of lower CPU frequency */
- if(hclks_frequency_current > hclks_frequency_target)
+ if (hclks_frequency_current > hclks_frequency_target)
{
/* Set FLASH latency to lowest latency */
status = UTILS_SetFlashLatency(hclks_frequency_target);
}
/* Update SystemCoreClock variable */
- if(status == SUCCESS)
+ if (status == SUCCESS)
{
LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK1_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->CPU1CLKDivider));
}
