Release v1.14.0
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h index 011fbcf..5a2c67e 100644 --- a/Inc/Legacy/stm32_hal_legacy.h +++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -37,16 +37,12 @@ #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR -#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1) +#if defined(STM32H7) || defined(STM32MP1) #define CRYP_DATATYPE_32B CRYP_NO_SWAP #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP #define CRYP_DATATYPE_1B CRYP_BIT_SWAP -#if defined(STM32U5) -#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF -#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF -#endif /* STM32U5 */ -#endif /* STM32U5 || STM32H7 || STM32MP1 */ +#endif /* STM32H7 || STM32MP1 */ /** * @} */ @@ -279,7 +275,7 @@ #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE -#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5) +#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif @@ -3931,6 +3927,12 @@ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) #endif /* STM32F1 */ +#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ + defined (STM32H7) || \ + defined (STM32L0) || defined (STM32L1) +#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG +#endif + #define IS_ALARM IS_RTC_ALARM #define IS_ALARM_MASK IS_RTC_ALARM_MASK #define IS_TAMPER IS_RTC_TAMPER
diff --git a/Inc/stm32wbxx_hal_comp.h b/Inc/stm32wbxx_hal_comp.h index a6676b2..a45165d 100644 --- a/Inc/stm32wbxx_hal_comp.h +++ b/Inc/stm32wbxx_hal_comp.h
@@ -51,7 +51,8 @@ #if defined(COMP2) uint32_t WindowMode; /*!< Set window mode of a pair of comparators instances (2 consecutive instances odd and even COMP<x> and COMP<x+1>). - Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode. + Note: HAL COMP driver allows to set window mode from any COMP + instance of the pair of COMP instances composing window mode. This parameter can be a value of @ref COMP_WindowMode */ #endif /* COMP2 */ @@ -153,17 +154,25 @@ * @} */ + #if defined(COMP2) /** @defgroup COMP_WindowMode COMP Window Mode * @{ */ -#define COMP_WINDOWMODE_DISABLE (0x00000000UL) /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */ -#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */ +#define COMP_WINDOWMODE_DISABLE (0x00000000UL) /*!< Window mode disable: Comparators instances + pair COMP1 and COMP2 are independent */ +#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances + pair COMP1 and COMP2 have their input plus + connected together. The common input is + COMP1 input plus + (COMP2 input plus is no more accessible). */ /** * @} */ #endif /* COMP2 */ + + /** @defgroup COMP_PowerMode COMP power mode * @{ */ @@ -198,7 +207,7 @@ #define COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 1/2 VrefInt */ #define COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 3/4 VrefInt */ #define COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN ) /*!< Comparator input minus connected to VrefInt */ -#define COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2) */ +#define COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2) */ #if defined(STM32WB15xx) || defined(STM32WB10xx) || defined(STM32WB1Mxx) /* COMP_INPUT_MINUS_IO2 not available on this device */ #else @@ -312,14 +321,14 @@ * @param __HANDLE__ COMP handle * @retval None */ -#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN) +#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN) /** * @brief Disable the specified comparator. * @param __HANDLE__ COMP handle * @retval None */ -#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN) +#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN) /** * @brief Lock the specified comparator configuration. @@ -330,14 +339,14 @@ * @param __HANDLE__ COMP handle * @retval None */ -#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) +#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) /** * @brief Check whether the specified comparator is locked. * @param __HANDLE__ COMP handle * @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked */ -#define __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK) +#define __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK) /** * @} @@ -346,7 +355,6 @@ /** @defgroup COMP_Exti_Management COMP external interrupt line management * @{ */ - /** * @brief Enable the COMP1 EXTI line rising edge trigger. * @retval None @@ -375,19 +383,19 @@ * @brief Enable the COMP1 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ - LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \ - } while(0) +#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1);\ + } while(0) /** * @brief Disable the COMP1 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ - LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \ - } while(0) +#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ + LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1);\ + } while(0) /** * @brief Enable the COMP1 EXTI line in interrupt mode. @@ -460,19 +468,19 @@ * @brief Enable the COMP2 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \ - LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \ - } while(0) +#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \ + } while(0) /** * @brief Disable the COMP2 EXTI line rising & falling edge trigger. * @retval None - */ -#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \ - LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \ - } while(0) + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \ + LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2);\ + } while(0) /** * @brief Enable the COMP2 EXTI line in interrupt mode. @@ -607,23 +615,23 @@ /* However, comparator instance kept as macro parameter for */ /* compatibility with other STM32 families. */ #if defined(COMP_INPUT_MINUS_IO2) -#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO4) || \ +#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO4) ||\ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO5)) #else -#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3) || \ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO4) || \ +#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO4) ||\ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO5)) #endif @@ -637,14 +645,14 @@ #define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__) \ ( ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3) \ ) /* Note: Output blanking source common to all COMP instances */ /* Macro kept for compatibility with other STM32 series */ #define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ - (IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__)) + (IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__)) #define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \
diff --git a/Inc/stm32wbxx_hal_crc.h b/Inc/stm32wbxx_hal_crc.h index 347969f..7265ebe 100644 --- a/Inc/stm32wbxx_hal_crc.h +++ b/Inc/stm32wbxx_hal_crc.h
@@ -318,7 +318,7 @@ /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions * @{ */ -HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc); +HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc); /** * @} */
diff --git a/Inc/stm32wbxx_hal_cryp.h b/Inc/stm32wbxx_hal_cryp.h index 7dd6865..8dc0f14 100644 --- a/Inc/stm32wbxx_hal_cryp.h +++ b/Inc/stm32wbxx_hal_cryp.h
@@ -96,7 +96,7 @@ { HAL_CRYP_SUSPEND_NONE = 0x00U, /*!< CRYP processing suspension not requested */ HAL_CRYP_SUSPEND = 0x01U /*!< CRYP processing suspension requested */ -}HAL_SuspendTypeDef; +} HAL_SuspendTypeDef; #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ /** @@ -407,7 +407,7 @@ * @arg CRYP_FLAG_OFNE: Output FIFO is not empty * @arg CRYP_FLAG_OFFU: Output FIFO is full * @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending - * @retval The state of __FLAG__ (TRUE or FALSE). + * @retval The state of __FLAG__ (TRUE or FALSE). */ #define CRYP_FLAG_MASK 0x0000001FU @@ -434,7 +434,8 @@ * @retval State of interruption (TRUE or FALSE). */ -#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR &\ + (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Check whether the specified CRYP interrupt is set or not. * @param __HANDLE__ specifies the CRYP handle. @@ -503,7 +504,8 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf); HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf); #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) -HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, + pCRYP_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) @@ -520,8 +522,10 @@ */ /* encryption/decryption ***********************************/ -HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout); -HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, + uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, + uint32_t Timeout); HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); @@ -579,11 +583,11 @@ ((CONFIG) == CRYP_KEYIVCONFIG_ONCE)) #define IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE) \ - (((((ALGO) == CRYP_AES_CTR)) && \ - ((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U)) || \ - (((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U)))) || \ - (((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC) || \ - ((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM))) + (((((ALGO) == CRYP_AES_CTR)) && \ + ((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U)) || \ + (((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U)))) || \ + (((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC) || \ + ((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM))) /** * @}
diff --git a/Inc/stm32wbxx_hal_cryp_ex.h b/Inc/stm32wbxx_hal_cryp_ex.h index fd8b0b2..0673d7c 100644 --- a/Inc/stm32wbxx_hal_cryp_ex.h +++ b/Inc/stm32wbxx_hal_cryp_ex.h
@@ -73,8 +73,8 @@ */ /** - * @} - */ + * @} + */ /* Private functions ---------------------------------------------------------*/ /** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
diff --git a/Inc/stm32wbxx_hal_i2c.h b/Inc/stm32wbxx_hal_i2c.h index 3ebbcec..c862c65 100644 --- a/Inc/stm32wbxx_hal_i2c.h +++ b/Inc/stm32wbxx_hal_i2c.h
@@ -809,8 +809,8 @@ (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ (~I2C_CR2_RD_WRN)) : \ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ - (I2C_CR2_ADD10) | (I2C_CR2_START)) & \ - (~I2C_CR2_RD_WRN))) + (I2C_CR2_ADD10) | (I2C_CR2_START) | \ + (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN))) #define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
diff --git a/Inc/stm32wbxx_hal_irda.h b/Inc/stm32wbxx_hal_irda.h index 1820911..86a81e7 100644 --- a/Inc/stm32wbxx_hal_irda.h +++ b/Inc/stm32wbxx_hal_irda.h
@@ -51,7 +51,7 @@ where usart_ker_ckpres is the IRDA input clock divided by a prescaler */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref IRDA_Word_Length */ + This parameter can be a value of @ref IRDAEx_Word_Length */ uint32_t Parity; /*!< Specifies the parity mode. This parameter can be a value of @ref IRDA_Parity @@ -169,7 +169,7 @@ __IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations. This parameter can be a value of @ref HAL_IRDA_StateTypeDef */ - uint32_t ErrorCode; /*!< IRDA Error code */ + __IO uint32_t ErrorCode; /*!< IRDA Error code */ #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Half Complete Callback */ @@ -247,7 +247,8 @@ Value is allowed for RxState only */ #define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ + Value is result of combination (Or) between + gState and RxState values */ #define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state Value is allowed for gState only */ #define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error @@ -259,30 +260,20 @@ /** @defgroup IRDA_Error_Definition IRDA Error Code Definition * @{ */ -#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ -#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ -#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */ -#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ -#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ -#define HAL_IRDA_ERROR_BUSY ((uint32_t)0x00000020U) /*!< Busy Error */ +#define HAL_IRDA_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_IRDA_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */ +#define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */ #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) -#define HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#define HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ /** * @} */ -/** @defgroup IRDA_Word_Length IRDA Word Length - * @{ - */ -#define IRDA_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long frame */ -#define IRDA_WORDLENGTH_8B 0x00000000U /*!< 8-bit long frame */ -#define IRDA_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long frame */ -/** - * @} - */ - /** @defgroup IRDA_Parity IRDA Parity * @{ */ @@ -312,7 +303,7 @@ * @} */ -/** @defgroup IRDA_ClockPrescaler Clock Prescaler +/** @defgroup IRDA_ClockPrescaler IRDA Clock Prescaler * @{ */ #define IRDA_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ @@ -340,7 +331,7 @@ * @} */ -/** @defgroup IRDA_Mode IRDA Mode +/** @defgroup IRDA_Mode IRDA Mode * @{ */ #define IRDA_MODE_DISABLE 0x00000000U /*!< Associated UART disabled in IRDA mode */ @@ -349,7 +340,7 @@ * @} */ -/** @defgroup IRDA_One_Bit IRDA One Bit Sampling +/** @defgroup IRDA_One_Bit IRDA One Bit Sampling * @{ */ #define IRDA_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disabled */ @@ -367,7 +358,7 @@ * @} */ -/** @defgroup IRDA_DMA_Rx IRDA DMA Rx +/** @defgroup IRDA_DMA_Rx IRDA DMA Rx * @{ */ #define IRDA_DMA_RX_DISABLE 0x00000000U /*!< IRDA DMA RX disabled */ @@ -440,7 +431,7 @@ * @} */ -/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags +/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags * @{ */ #define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ @@ -453,7 +444,7 @@ * @} */ -/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask +/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask * @{ */ #define IRDA_IT_MASK 0x001FU /*!< IRDA Interruptions flags mask */ @@ -466,9 +457,8 @@ */ /** - * @} - */ - + * @} + */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup IRDA_Exported_Macros IRDA Exported Macros @@ -485,12 +475,12 @@ (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \ (__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) + } while(0U) #else #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \ (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \ (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \ - } while(0) + } while(0U) #endif /*USE_HAL_IRDA_REGISTER_CALLBACKS */ /** @brief Flush the IRDA DR register. @@ -498,10 +488,10 @@ * @retval None */ #define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \ - SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \ - } while(0) + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \ + } while(0U) /** @brief Clear the specified IRDA pending flag. * @param __HANDLE__ specifies the IRDA Handle. @@ -581,9 +571,14 @@ * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) +#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \ + ((__HANDLE__)->Instance->CR1 |= (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))):\ + ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \ + ((__HANDLE__)->Instance->CR2 |= (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))):\ + ((__HANDLE__)->Instance->CR3 |= (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Disable the specified IRDA interrupt. * @param __HANDLE__ specifies the IRDA Handle. @@ -597,10 +592,14 @@ * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) - +#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \ + ((__HANDLE__)->Instance->CR1 &= ~ (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \ + ((__HANDLE__)->Instance->CR2 &= ~ (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Check whether the specified IRDA interrupt has occurred or not. * @param __HANDLE__ specifies the IRDA Handle. @@ -616,7 +615,8 @@ * @arg @ref IRDA_IT_PE Parity Error interrupt * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET) +#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) \ + ((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified IRDA interrupt source is enabled or not. * @param __HANDLE__ specifies the IRDA Handle. @@ -630,9 +630,10 @@ * @arg @ref IRDA_IT_PE Parity Error interrupt * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ - (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET) +#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + ((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__) \ + & IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3)) \ + & (0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the IRDA Handle. @@ -656,7 +657,6 @@ * @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request * @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request * @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request - * * @retval None */ #define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) @@ -671,7 +671,8 @@ * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ -#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) +#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\ + &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) /** @brief Enable UART/USART associated to IRDA Handle. * @param __HANDLE__ specifies the IRDA Handle. @@ -694,52 +695,6 @@ * @{ */ -/** @brief Compute the mask to apply to retrieve the received data - * according to the word length and to the parity bits activation. - * @param __HANDLE__ specifies the IRDA Handle. - * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field. - */ -#define IRDA_MASK_COMPUTATION(__HANDLE__) \ - do { \ - if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \ - { \ - if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x01FF ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x00FF ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \ - { \ - if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x00FF ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x007F ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \ - { \ - if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x007F ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x003F ; \ - } \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x0000U; \ - } \ -} while(0) - /** @brief Ensure that IRDA Baud rate is less or equal to maximum value. * @param __BAUDRATE__ specifies the IRDA Baudrate set by the user. * @retval True or False @@ -752,17 +707,7 @@ */ #define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U) -/** - * @brief Ensure that IRDA frame length is valid. - * @param __LENGTH__ IRDA frame length. - * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) - */ -#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \ - ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \ - ((__LENGTH__) == IRDA_WORDLENGTH_9B)) - -/** - * @brief Ensure that IRDA frame parity is valid. +/** @brief Ensure that IRDA frame parity is valid. * @param __PARITY__ IRDA frame parity. * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) */ @@ -770,81 +715,73 @@ ((__PARITY__) == IRDA_PARITY_EVEN) || \ ((__PARITY__) == IRDA_PARITY_ODD)) -/** - * @brief Ensure that IRDA communication mode is valid. +/** @brief Ensure that IRDA communication mode is valid. * @param __MODE__ IRDA communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ -#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) +#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\ + & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) -/** - * @brief Ensure that IRDA power mode is valid. +/** @brief Ensure that IRDA power mode is valid. * @param __MODE__ IRDA power mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \ ((__MODE__) == IRDA_POWERMODE_NORMAL)) -/** - * @brief Ensure that IRDA clock Prescaler is valid. +/** @brief Ensure that IRDA clock Prescaler is valid. * @param __CLOCKPRESCALER__ IRDA clock Prescaler value. * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) */ #define IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256)) + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256)) -/** - * @brief Ensure that IRDA state is valid. +/** @brief Ensure that IRDA state is valid. * @param __STATE__ IRDA state mode. * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) */ #define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \ ((__STATE__) == IRDA_STATE_ENABLE)) -/** - * @brief Ensure that IRDA associated UART/USART mode is valid. +/** @brief Ensure that IRDA associated UART/USART mode is valid. * @param __MODE__ IRDA associated UART/USART mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \ ((__MODE__) == IRDA_MODE_ENABLE)) -/** - * @brief Ensure that IRDA sampling rate is valid. +/** @brief Ensure that IRDA sampling rate is valid. * @param __ONEBIT__ IRDA sampling rate. * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) */ #define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \ ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE)) -/** - * @brief Ensure that IRDA DMA TX mode is valid. +/** @brief Ensure that IRDA DMA TX mode is valid. * @param __DMATX__ IRDA DMA TX mode. * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) */ #define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \ ((__DMATX__) == IRDA_DMA_TX_ENABLE)) -/** - * @brief Ensure that IRDA DMA RX mode is valid. +/** @brief Ensure that IRDA DMA RX mode is valid. * @param __DMARX__ IRDA DMA RX mode. * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) */ #define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \ ((__DMARX__) == IRDA_DMA_RX_ENABLE)) -/** - * @brief Ensure that IRDA request is valid. +/** @brief Ensure that IRDA request is valid. * @param __PARAM__ IRDA request. * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) */ @@ -852,8 +789,8 @@ ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \ ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST)) /** - * @} - */ + * @} + */ /* Include IRDA HAL Extended module */ #include "stm32wbxx_hal_irda_ex.h" @@ -875,7 +812,8 @@ #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) /* Callbacks Register/UnRegister functions ***********************************/ -HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, + pIRDA_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
diff --git a/Inc/stm32wbxx_hal_irda_ex.h b/Inc/stm32wbxx_hal_irda_ex.h index 870664c..694a1c5 100644 --- a/Inc/stm32wbxx_hal_irda_ex.h +++ b/Inc/stm32wbxx_hal_irda_ex.h
@@ -32,13 +32,31 @@ */ /** @defgroup IRDAEx IRDAEx + * @brief IRDA Extended HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ +/** @defgroup IRDAEx_Extended_Exported_Constants IRDAEx Extended Exported Constants + * @{ + */ + +/** @defgroup IRDAEx_Word_Length IRDAEx Word Length + * @{ + */ +#define IRDA_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long frame */ +#define IRDA_WORDLENGTH_8B 0x00000000U /*!< 8-bit long frame */ +#define IRDA_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long frame */ +/** + * @} + */ + +/** + * @} + */ + /* Exported macros -----------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ @@ -55,8 +73,8 @@ do { \ if((__HANDLE__)->Instance == USART1) \ { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ case RCC_USART1CLKSOURCE_PCLK2: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \ break; \ @@ -72,7 +90,7 @@ default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else \ { \ @@ -80,6 +98,59 @@ } \ } while(0U) +/** @brief Compute the mask to apply to retrieve the received data + * according to the word length and to the parity bits activation. + * @param __HANDLE__ specifies the IRDA Handle. + * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field. + */ +#define IRDA_MASK_COMPUTATION(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x003FU ; \ + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) + +/** @brief Ensure that IRDA frame length is valid. + * @param __LENGTH__ IRDA frame length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \ + ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \ + ((__LENGTH__) == IRDA_WORDLENGTH_9B)) /** * @} */
diff --git a/Inc/stm32wbxx_hal_lptim.h b/Inc/stm32wbxx_hal_lptim.h index f6712fc..7ca18f3 100644 --- a/Inc/stm32wbxx_hal_lptim.h +++ b/Inc/stm32wbxx_hal_lptim.h
@@ -657,11 +657,9 @@ /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, - HAL_LPTIM_CallbackIDTypeDef CallbackID, - pLPTIM_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, - HAL_LPTIM_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, + pLPTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ /** * @} @@ -672,7 +670,7 @@ * @{ */ /* Peripheral State functions ************************************************/ -HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); +HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim); /** * @} */
diff --git a/Inc/stm32wbxx_hal_pcd.h b/Inc/stm32wbxx_hal_pcd.h index 71778ab..b14b38d 100644 --- a/Inc/stm32wbxx_hal_pcd.h +++ b/Inc/stm32wbxx_hal_pcd.h
@@ -339,7 +339,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); -uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr); /** * @} */ @@ -348,7 +348,7 @@ /** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions * @{ */ -PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); /** * @} */
diff --git a/Inc/stm32wbxx_hal_rng.h b/Inc/stm32wbxx_hal_rng.h index fb07ec2..7842e26 100644 --- a/Inc/stm32wbxx_hal_rng.h +++ b/Inc/stm32wbxx_hal_rng.h
@@ -80,7 +80,7 @@ typedef struct __RNG_HandleTypeDef #else typedef struct -#endif /* (USE_HAL_RNG_REGISTER_CALLBACKS) */ +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ { RNG_TypeDef *Instance; /*!< Register base address */ @@ -90,7 +90,7 @@ __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */ - __IO uint32_t ErrorCode; /*!< RNG Error code */ + __IO uint32_t ErrorCode; /*!< RNG Error code */ uint32_t RandomNumber; /*!< Last Generated RNG Data */ @@ -170,14 +170,14 @@ /** @defgroup RNG_Error_Definition RNG Error Definition * @{ */ -#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */ #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) #define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U /*!< Invalid Callback error */ #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ -#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */ +#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */ #define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */ #define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */ -#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ +#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ /** * @} */ @@ -203,7 +203,7 @@ } while(0U) #else #define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET) -#endif /*USE_HAL_RNG_REGISTER_CALLBACKS */ +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ /** * @brief Enables the RNG peripheral. @@ -298,7 +298,8 @@ /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, + pRNG_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback); @@ -314,7 +315,7 @@ */ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit); HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng); -uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng); +uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng); void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng); void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng); @@ -327,8 +328,8 @@ /** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions * @{ */ -HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng); -uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng); +HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng); +uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng); /** * @} */ @@ -345,8 +346,8 @@ ((IT) == RNG_IT_SEI)) #define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \ - ((FLAG) == RNG_FLAG_CECS) || \ - ((FLAG) == RNG_FLAG_SECS)) + ((FLAG) == RNG_FLAG_CECS) || \ + ((FLAG) == RNG_FLAG_SECS)) /** * @brief Verify the RNG Clock Error Detection mode. @@ -375,3 +376,4 @@ #endif /* STM32WBxx_HAL_RNG_H */ +
diff --git a/Inc/stm32wbxx_hal_smartcard.h b/Inc/stm32wbxx_hal_smartcard.h index 4d4d967..1cd40b2 100644 --- a/Inc/stm32wbxx_hal_smartcard.h +++ b/Inc/stm32wbxx_hal_smartcard.h
@@ -51,7 +51,8 @@ where usart_ker_ckpres is the USART input clock divided by a prescaler */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */ + This parameter @ref SMARTCARD_Word_Length can only be + set to 9 (8 data + 1 parity bits). */ uint32_t StopBits; /*!< Specifies the number of stop bits. This parameter can be a value of @ref SMARTCARD_Stop_Bits. */ @@ -75,13 +76,14 @@ data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of @ref SMARTCARD_Last_Bit */ - uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. - Selecting the single sample method increases the receiver tolerance to clock - deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */ + uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote + is selected. Selecting the single sample method increases + the receiver tolerance to clock deviations. This parameter can be a value + of @ref SMARTCARD_OneBit_Sampling. */ uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler. - This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied - by 2 to give the division factor of the source clock frequency */ + This parameter can be any value from 0x01 to 0x1F. Prescaler value is + multiplied by 2 to give the division factor of the source clock frequency */ uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */ @@ -140,14 +142,16 @@ uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. This parameter can be a value of @ref SMARTCARD_MSB_First */ - uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when - relevant flag is available) or once guard time period has elapsed. - This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */ + uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when + relevant flag is available) or once guard time period has elapsed. + This parameter can be a value + of @ref SMARTCARDEx_Transmission_Completion_Indication. */ } SMARTCARD_AdvFeatureInitTypeDef; /** * @brief HAL SMARTCARD State definition - * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState (see @ref SMARTCARD_State_Definition). + * @note HAL SMARTCARD State value is a combination of 2 different substates: + * gState and RxState (see @ref SMARTCARD_State_Definition). * - gState contains SMARTCARD state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : @@ -214,7 +218,8 @@ uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. - This parameter can be a value of @ref SMARTCARDEx_FIFO_mode. */ + This parameter can be a value of + @ref SMARTCARDEx_FIFO_mode. */ void (*RxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ @@ -226,12 +231,14 @@ HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management - and also related to Tx operations. - This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ + __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global + Handle management and also related to Tx operations. + This parameter can be a value + of @ref HAL_SMARTCARD_StateTypeDef */ __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations. - This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ + This parameter can be a value + of @ref HAL_SMARTCARD_StateTypeDef */ __IO uint32_t ErrorCode; /*!< SmartCard Error code */ @@ -310,23 +317,26 @@ /** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition * @{ */ -#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized - Value is allowed for gState and RxState */ -#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use - Value is allowed for gState and RxState */ +#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized. Value + is allowed for gState and RxState */ +#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for + use. Value is allowed for gState + and RxState */ #define HAL_SMARTCARD_STATE_BUSY 0x00000024U /*!< an internal process is ongoing - Value is allowed for gState only */ + Value is allowed for gState only */ #define HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing - Value is allowed for gState only */ + Value is allowed for gState only */ #define HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing Value is allowed for RxState only */ -#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing - Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ +#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception + process is ongoing Not to be used for + neither gState nor RxState. + Value is result of combination (Or) + between gState and RxState values */ #define HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U /*!< Timeout state - Value is allowed for gState only */ + Value is allowed for gState only */ #define HAL_SMARTCARD_STATE_ERROR 0x000000E0U /*!< Error - Value is allowed for gState only */ + Value is allowed for gState only */ /** * @} */ @@ -334,15 +344,15 @@ /** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition * @{ */ -#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ -#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ -#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */ -#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ -#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ -#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver TimeOut error */ +#define HAL_SMARTCARD_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_SMARTCARD_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_SMARTCARD_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_SMARTCARD_ERROR_FE (0x00000004U) /*!< frame error */ +#define HAL_SMARTCARD_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_SMARTCARD_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_SMARTCARD_ERROR_RTO (0x00000020U) /*!< Receiver TimeOut error */ #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) -#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ /** * @} @@ -662,7 +672,8 @@ * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before + * guard time interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt @@ -675,9 +686,16 @@ * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval None */ -#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) +#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1UL <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))):\ + ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1UL <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1UL <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Disable the specified SmartCard interrupt. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -687,7 +705,8 @@ * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard + * time interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt @@ -700,9 +719,16 @@ * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval None */ -#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) +#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Check whether the specified SmartCard interrupt has occurred or not. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -712,7 +738,8 @@ * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time + * interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt @@ -725,8 +752,10 @@ * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ - & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET) +#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) (\ + (((__HANDLE__)->Instance->ISR & (0x01UL << (((__INTERRUPT__)\ + & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS)))!= 0U)\ + ? SET : RESET) /** @brief Check whether the specified SmartCard interrupt source is enabled or not. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -736,7 +765,8 @@ * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time + * interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt @@ -749,9 +779,16 @@ * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ - (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET) +#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 0x01U)?\ + (__HANDLE__)->Instance->CR1 : \ + (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 0x02U)?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) &\ + (0x01UL << (((uint16_t)(__INTERRUPT__))\ + & SMARTCARD_IT_MASK))) != 0U)\ + ? SET : RESET) /** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -1057,7 +1094,8 @@ #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) /* Callbacks Register/UnRegister functions ***********************************/ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, - HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback); + HAL_SMARTCARD_CallbackIDTypeDef CallbackID, + pSMARTCARD_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
diff --git a/Inc/stm32wbxx_hal_tim.h b/Inc/stm32wbxx_hal_tim.h index 5a23994..95f1188 100644 --- a/Inc/stm32wbxx_hal_tim.h +++ b/Inc/stm32wbxx_hal_tim.h
@@ -1842,6 +1842,10 @@ ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ ((__PRESCALER__) == TIM_ICPSC_DIV8)) +#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \ + ((__CHANNEL__) != (TIM_CHANNEL_5)) && \ + ((__CHANNEL__) != (TIM_CHANNEL_6))) + #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ ((__MODE__) == TIM_OPMODE_REPETITIVE)) @@ -2264,7 +2268,7 @@ * @{ */ /* Timer Encoder functions ****************************************************/ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
diff --git a/Inc/stm32wbxx_hal_tim_ex.h b/Inc/stm32wbxx_hal_tim_ex.h index 194bc42..81f4725 100644 --- a/Inc/stm32wbxx_hal_tim_ex.h +++ b/Inc/stm32wbxx_hal_tim_ex.h
@@ -364,7 +364,7 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); -HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput); /** * @} */
diff --git a/Inc/stm32wbxx_hal_tsc.h b/Inc/stm32wbxx_hal_tsc.h index 8f8273d..af6915d 100644 --- a/Inc/stm32wbxx_hal_tsc.h +++ b/Inc/stm32wbxx_hal_tsc.h
@@ -671,7 +671,8 @@ ((__VALUE__) == TSC_PG_PRESC_DIV128)) #define IS_TSC_PG_PRESC_VS_CTPL(__PGPSC__, __CTPL__) ((((__PGPSC__) == TSC_PG_PRESC_DIV1) && \ - ((__CTPL__) > TSC_CTPL_2CYCLES)) || \ + (((__CTPL__) == TSC_CTPL_1CYCLE) || \ + ((__CTPL__) > TSC_CTPL_2CYCLES))) || \ (((__PGPSC__) == TSC_PG_PRESC_DIV2) && \ ((__CTPL__) > TSC_CTPL_1CYCLE)) || \ (((__PGPSC__) > TSC_PG_PRESC_DIV2) && \
diff --git a/Inc/stm32wbxx_hal_uart.h b/Inc/stm32wbxx_hal_uart.h index a4b25fe..d37c25d 100644 --- a/Inc/stm32wbxx_hal_uart.h +++ b/Inc/stm32wbxx_hal_uart.h
@@ -45,56 +45,56 @@ */ typedef struct { - uint32_t BaudRate; /*!< This member configures the UART communication baud rate. - The baud rate register is computed using the following formula: + uint32_t BaudRate; /*!< This member configures the UART communication baud rate. + The baud rate register is computed using the following formula: #if defined(LPUART1) - LPUART: - ======= - Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) - where lpuart_ker_ck_pres is the UART input clock divided by a prescaler - UART: - ===== + LPUART: + ======= + Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) + where lpuart_ker_ck_pres is the UART input clock divided by a prescaler + UART: + ===== #endif - - If oversampling is 16 or in LIN mode, - Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) - - If oversampling is 8, - Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / - ((huart->Init.BaudRate)))[15:4] - Baud Rate Register[3] = 0 - Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / - ((huart->Init.BaudRate)))[3:0]) >> 1 - where uart_ker_ck_pres is the UART input clock divided by a prescaler */ + - If oversampling is 16 or in LIN mode, + Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) + - If oversampling is 8, + Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[3:0]) >> 1 + where uart_ker_ck_pres is the UART input clock divided by a prescaler */ - uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref UARTEx_Word_Length. */ + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref UARTEx_Word_Length. */ - uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref UART_Stop_Bits. */ + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref UART_Stop_Bits. */ - uint32_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref UART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref UART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ - uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref UART_Mode. */ + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref UART_Mode. */ - uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref UART_Hardware_Flow_Control. */ + uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref UART_Hardware_Flow_Control. */ - uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, - to achieve higher speed (up to f_PCLK/8). - This parameter can be a value of @ref UART_Over_Sampling. */ + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, + to achieve higher speed (up to f_PCLK/8). + This parameter can be a value of @ref UART_Over_Sampling. */ - uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. - Selecting the single sample method increases the receiver tolerance to clock - deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ + uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. + Selecting the single sample method increases the receiver tolerance to clock + deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ - uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source. - This parameter can be a value of @ref UART_ClockPrescaler. */ + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source. + This parameter can be a value of @ref UART_ClockPrescaler. */ } UART_InitTypeDef; @@ -316,8 +316,9 @@ /** * @brief HAL UART Callback pointer definition */ -typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ -typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ +typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ +typedef void (*pUART_RxEventCallbackTypeDef) +(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ @@ -1601,12 +1602,6 @@ /* Include UART HAL Extended module */ #include "stm32wbxx_hal_uart_ex.h" - -/* Prescaler Table used in BRR computation macros. - Declared as extern here to allow use of private UART macros, outside of HAL UART functions */ -extern const uint16_t UARTPrescTable[12]; - - /* Exported functions --------------------------------------------------------*/ /** @addtogroup UART_Exported_Functions UART Exported Functions * @{ @@ -1732,6 +1727,17 @@ * @} */ +/* Private variables -----------------------------------------------------------*/ +/** @defgroup UART_Private_variables UART Private variables + * @{ + */ +/* Prescaler Table used in BRR computation macros. + Declared as extern here to allow use of private UART macros, outside of HAL UART functions */ +extern const uint16_t UARTPrescTable[12]; +/** + * @} + */ + /** * @} */
diff --git a/Inc/stm32wbxx_hal_uart_ex.h b/Inc/stm32wbxx_hal_uart_ex.h index e80ffe8..c3ab804 100644 --- a/Inc/stm32wbxx_hal_uart_ex.h +++ b/Inc/stm32wbxx_hal_uart_ex.h
@@ -98,12 +98,12 @@ * @brief UART TXFIFO threshold level * @{ */ -#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ -#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */ -#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */ -#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */ -#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */ -#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */ +#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */ +#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */ /** * @} */ @@ -112,12 +112,12 @@ * @brief UART RXFIFO threshold level * @{ */ -#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ -#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */ -#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */ -#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */ -#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */ -#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */ +#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */ +#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */ /** * @} */ @@ -173,11 +173,12 @@ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout); HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart); +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart); /**
diff --git a/Inc/stm32wbxx_hal_usart.h b/Inc/stm32wbxx_hal_usart.h index 37514d6..b989f72 100644 --- a/Inc/stm32wbxx_hal_usart.h +++ b/Inc/stm32wbxx_hal_usart.h
@@ -224,6 +224,7 @@ #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) #define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +#define HAL_USART_ERROR_RTO ((uint32_t)0x00000080U) /*!< Receiver Timeout error */ /** * @} */ @@ -259,15 +260,6 @@ * @} */ -/** @defgroup USART_Over_Sampling USART Over Sampling - * @{ - */ -#define USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ -#define USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ -/** - * @} - */ - /** @defgroup USART_Clock USART Clock * @{ */ @@ -348,6 +340,7 @@ #define USART_FLAG_UDR USART_ISR_UDR /*!< SPI slave underrun error flag */ #define USART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< USART transmit data register empty */ #define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< USART TXFIFO not full */ +#define USART_FLAG_RTOF USART_ISR_RTOF /*!< USART receiver timeout flag */ #define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */ #define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< USART read data register not empty */ #define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< USART RXFIFO not empty */ @@ -402,6 +395,7 @@ #define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ #define USART_CLEAR_UDRF USART_ICR_UDRCF /*!< SPI slave underrun error Clear Flag */ #define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO Empty Clear Flag */ +#define USART_CLEAR_RTOF USART_ICR_RTOCF /*!< USART receiver timeout clear flag */ /** * @} */ @@ -412,6 +406,8 @@ #define USART_IT_MASK 0x001FU /*!< USART interruptions flags mask */ #define USART_CR_MASK 0x00E0U /*!< USART control register mask */ #define USART_CR_POS 5U /*!< USART control register position */ +#define USART_ISR_MASK 0x1F00U /*!< USART ISR register mask */ +#define USART_ISR_POS 8U /*!< USART ISR register position */ /** * @} */ @@ -456,6 +452,7 @@ * @arg @ref USART_FLAG_TC Transmission Complete flag * @arg @ref USART_FLAG_RXNE Receive data register not empty flag * @arg @ref USART_FLAG_RXFNE RXFIFO not empty flag + * @arg @ref USART_FLAG_RTOF Receiver Timeout flag * @arg @ref USART_FLAG_IDLE Idle Line detection flag * @arg @ref USART_FLAG_ORE OverRun Error flag * @arg @ref USART_FLAG_NE Noise Error flag @@ -476,6 +473,7 @@ * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref USART_CLEAR_RTOF Receiver Timeout clear flag * @arg @ref USART_CLEAR_UDRF SPI slave underrun error Clear Flag * @retval None */ @@ -588,7 +586,7 @@ * @arg @ref USART_IT_PE Parity Error interrupt * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__INTERRUPT__)>> 0x08))) != RESET) ? SET : RESET) +#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified USART interrupt source is enabled or not. * @param __HANDLE__ specifies the USART Handle. @@ -625,6 +623,7 @@ * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref USART_CLEAR_RTOF Receiver timeout clear flag * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag * @retval None @@ -769,14 +768,6 @@ #define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U)) /** - * @brief Ensure that USART oversampling is valid. - * @param __SAMPLING__ USART oversampling. - * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) - */ -#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ - ((__SAMPLING__) == USART_OVERSAMPLING_8)) - -/** * @brief Ensure that USART clock state is valid. * @param __CLOCK__ USART clock state. * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
diff --git a/Inc/stm32wbxx_ll_comp.h b/Inc/stm32wbxx_ll_comp.h index f15795e..2b3514a 100644 --- a/Inc/stm32wbxx_ll_comp.h +++ b/Inc/stm32wbxx_ll_comp.h
@@ -73,33 +73,33 @@ { uint32_t PowerMode; /*!< Set comparator operating mode to adjust power and speed. This parameter can be a value of @ref COMP_LL_EC_POWERMODE - - This feature can be modified afterwards using unitary function @ref LL_COMP_SetPowerMode(). */ + This feature can be modified afterwards using unitary + function @ref LL_COMP_SetPowerMode(). */ uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input). This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS - - This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */ + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetInputPlus(). */ uint32_t InputMinus; /*!< Set comparator input minus (inverting input). This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS - - This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */ + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetInputMinus(). */ uint32_t InputHysteresis; /*!< Set comparator hysteresis mode of the input minus. This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS - - This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputHysteresis(). */ + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetInputHysteresis(). */ uint32_t OutputPolarity; /*!< Set comparator output polarity. This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY - - This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputPolarity(). */ + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetOutputPolarity(). */ uint32_t OutputBlankingSource; /*!< Set comparator blanking source. This parameter can be a value of @ref COMP_LL_EC_OUTPUT_BLANKING_SOURCE - - This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputBlankingSource(). */ + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetOutputBlankingSource(). */ } LL_COMP_InitTypeDef; @@ -113,6 +113,7 @@ * @{ */ + /** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode * @{ */ @@ -124,6 +125,8 @@ * @} */ + + /** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode * @{ */ @@ -280,8 +283,7 @@ * @param __COMPx__ COMP instance * @retval COMP common instance or value "0" if there is no COMP common instance. */ -#define __LL_COMP_COMMON_INSTANCE(__COMPx__) \ - (COMP12_COMMON) +#define __LL_COMP_COMMON_INSTANCE(__COMPx__) (COMP12_COMMON) /** * @} @@ -297,7 +299,8 @@ */ #if defined(COMP2) -/** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: common to several COMP instances +/** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: + * common to several COMP instances * @{ */
diff --git a/Inc/stm32wbxx_ll_crc.h b/Inc/stm32wbxx_ll_crc.h index 2811746..570c46e 100644 --- a/Inc/stm32wbxx_ll_crc.h +++ b/Inc/stm32wbxx_ll_crc.h
@@ -184,7 +184,7 @@ * @arg @ref LL_CRC_POLYLENGTH_8B * @arg @ref LL_CRC_POLYLENGTH_7B */ -__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE)); } @@ -215,7 +215,7 @@ * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD * @arg @ref LL_CRC_INDATA_REVERSE_WORD */ -__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN)); } @@ -242,7 +242,7 @@ * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT */ -__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT)); } @@ -270,7 +270,7 @@ * @param CRCx CRC Instance * @retval Value programmed in Programmable initial CRC value register */ -__STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_GetInitialData(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_REG(CRCx->INIT)); } @@ -301,7 +301,7 @@ * @param CRCx CRC Instance * @retval Value programmed in Programmable Polynomial value register */ -__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_REG(CRCx->POL)); } @@ -359,7 +359,7 @@ * @param CRCx CRC Instance * @retval Current CRC calculation result as stored in CRC_DR register (32 bits). */ -__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_ReadData32(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_REG(CRCx->DR)); } @@ -371,7 +371,7 @@ * @param CRCx CRC Instance * @retval Current CRC calculation result as stored in CRC_DR register (16 bits). */ -__STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx) +__STATIC_INLINE uint16_t LL_CRC_ReadData16(const CRC_TypeDef *CRCx) { return (uint16_t)READ_REG(CRCx->DR); } @@ -383,7 +383,7 @@ * @param CRCx CRC Instance * @retval Current CRC calculation result as stored in CRC_DR register (8 bits). */ -__STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx) +__STATIC_INLINE uint8_t LL_CRC_ReadData8(const CRC_TypeDef *CRCx) { return (uint8_t)READ_REG(CRCx->DR); } @@ -395,7 +395,7 @@ * @param CRCx CRC Instance * @retval Current CRC calculation result as stored in CRC_DR register (7 bits). */ -__STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx) +__STATIC_INLINE uint8_t LL_CRC_ReadData7(const CRC_TypeDef *CRCx) { return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU); } @@ -407,7 +407,7 @@ * @param CRCx CRC Instance * @retval Value stored in CRC_IDR register (General-purpose 32-bit data register). */ -__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_Read_IDR(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_REG(CRCx->IDR)); } @@ -433,7 +433,7 @@ * @{ */ -ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx); +ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx); /** * @}
diff --git a/Inc/stm32wbxx_ll_lptim.h b/Inc/stm32wbxx_ll_lptim.h index 75cccc5..19ecf87 100644 --- a/Inc/stm32wbxx_ll_lptim.h +++ b/Inc/stm32wbxx_ll_lptim.h
@@ -362,7 +362,7 @@ * @{ */ -ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx); +ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx); void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct); ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct); void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);
diff --git a/Inc/stm32wbxx_ll_lpuart.h b/Inc/stm32wbxx_ll_lpuart.h index 62fab4a..bfb37a9 100644 --- a/Inc/stm32wbxx_ll_lpuart.h +++ b/Inc/stm32wbxx_ll_lpuart.h
@@ -1398,7 +1398,8 @@ * @arg @ref LL_LPUART_PRESCALER_DIV256 * @retval Baud Rate */ -__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue) +__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk, + uint32_t PrescalerValue) { uint32_t lpuartdiv; uint32_t brrresult; @@ -1636,8 +1637,7 @@ return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE +#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not @@ -1661,8 +1661,7 @@ return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF +#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not @@ -1936,8 +1935,7 @@ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); } -/* Legacy define */ -#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE +#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt @@ -1961,8 +1959,7 @@ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE); } -/* Legacy define */ -#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF +#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Enable TX Empty and TX FIFO Not Full Interrupt @@ -2089,8 +2086,7 @@ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); } -/* Legacy define */ -#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE +#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt @@ -2114,8 +2110,7 @@ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE); } -/* Legacy define */ -#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF +#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Disable TX Empty and TX FIFO Not Full Interrupt @@ -2242,8 +2237,7 @@ return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE +#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled. @@ -2267,8 +2261,7 @@ return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF +#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled
diff --git a/Inc/stm32wbxx_ll_rng.h b/Inc/stm32wbxx_ll_rng.h index 2b8e20a..709dca0 100644 --- a/Inc/stm32wbxx_ll_rng.h +++ b/Inc/stm32wbxx_ll_rng.h
@@ -38,6 +38,7 @@ */ /* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ @@ -56,8 +57,8 @@ { uint32_t ClockErrorDetection; /*!< Clock error detection. This parameter can be one value of @ref RNG_LL_CED. - - This parameter can be modified using unitary functions @ref LL_RNG_EnableClkErrorDetect(). */ + This parameter can be modified using unitary + functions @ref LL_RNG_EnableClkErrorDetect(). */ } LL_RNG_InitTypeDef; /** @@ -174,7 +175,7 @@ * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL); } @@ -207,7 +208,7 @@ * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL); } @@ -226,7 +227,7 @@ * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL); } @@ -237,7 +238,7 @@ * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL); } @@ -248,7 +249,7 @@ * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL); } @@ -259,7 +260,7 @@ * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL); } @@ -270,7 +271,7 @@ * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL); } @@ -336,7 +337,7 @@ * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL); } @@ -355,7 +356,7 @@ * @param RNGx RNG Instance * @retval Generated 32-bit random value */ -__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx) { return (uint32_t)(READ_REG(RNGx->DR)); } @@ -370,7 +371,7 @@ */ ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct); void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct); -ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx); +ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx); /** * @} @@ -396,3 +397,4 @@ #endif #endif /* __STM32WBxx_LL_RNG_H */ +
diff --git a/Inc/stm32wbxx_ll_tim.h b/Inc/stm32wbxx_ll_tim.h index 1a4ff44..a7249de 100644 --- a/Inc/stm32wbxx_ll_tim.h +++ b/Inc/stm32wbxx_ll_tim.h
@@ -126,11 +126,7 @@ #define TIMx_OR_RMP_SHIFT 16U #define TIMx_OR_RMP_MASK 0x0000FFFFU #define TIM1_OR_RMP_MASK ((TIM1_OR_ETR_ADC1_RMP | TIM1_OR_TI1_RMP) << TIMx_OR_RMP_SHIFT) -#if defined(USB) -#define TIM2_OR_RMP_MASK ((TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP | TIM2_OR_ITR1_RMP) << TIMx_OR_RMP_SHIFT) -#else #define TIM2_OR_RMP_MASK ((TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP) << TIMx_OR_RMP_SHIFT) -#endif #if defined(TIM16) #define TIM16_OR_RMP_MASK (TIM16_OR_TI1_RMP << TIMx_OR_RMP_SHIFT) #endif /* TIM16 */ @@ -972,11 +968,11 @@ #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */ #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */ #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */ -#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */ -#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */ -#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */ -#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */ -#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */ +#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */ +#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */ +#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */ +#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */ +#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */ #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */ #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */ #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */ @@ -1295,6 +1291,7 @@ /** @endcond */ + /** * @} */ @@ -1429,11 +1426,6 @@ * @} */ - -/** - * @} - */ - /* Exported functions --------------------------------------------------------*/ /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions * @{ @@ -2030,7 +2022,7 @@ * @arg @ref LL_TIM_CHANNEL_CH6 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels) { return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); } @@ -2371,7 +2363,7 @@ * @arg @ref LL_TIM_CHANNEL_CH6 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2447,7 +2439,7 @@ * @arg @ref LL_TIM_CHANNEL_CH6 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2532,7 +2524,7 @@ * @arg @ref LL_TIM_CHANNEL_CH6 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -3081,7 +3073,7 @@ * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); } @@ -4993,7 +4985,7 @@ * @{ */ -ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx); +ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx); void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct); void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
diff --git a/Inc/stm32wbxx_ll_usart.h b/Inc/stm32wbxx_ll_usart.h index 1e187d0..e22bd40 100644 --- a/Inc/stm32wbxx_ll_usart.h +++ b/Inc/stm32wbxx_ll_usart.h
@@ -1567,7 +1567,7 @@ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME */ -__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE)); } @@ -2985,8 +2985,7 @@ return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE +#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not @@ -3012,8 +3011,7 @@ return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF +#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not @@ -3468,8 +3466,7 @@ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); } -/* Legacy define */ -#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE +#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt @@ -3495,8 +3492,7 @@ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); } -/* Legacy define */ -#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF +#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Enable TX Empty and TX FIFO Not Full Interrupt @@ -3685,8 +3681,7 @@ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); } -/* Legacy define */ -#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE +#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt @@ -3712,8 +3707,7 @@ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); } -/* Legacy define */ -#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF +#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Disable TX Empty and TX FIFO Not Full Interrupt @@ -3904,8 +3898,7 @@ return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE +#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled. @@ -3931,8 +3924,7 @@ return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF +#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled
diff --git a/Inc/stm32wbxx_ll_usb.h b/Inc/stm32wbxx_ll_usb.h index 34afb78..11211ff 100644 --- a/Inc/stm32wbxx_ll_usb.h +++ b/Inc/stm32wbxx_ll_usb.h
@@ -192,6 +192,9 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx); HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode); +HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef const *USBx); +HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef const *USBx, uint32_t num); + #if defined (HAL_PCD_MODULE_ENABLED) HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep); HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep); @@ -205,14 +208,14 @@ HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx); HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx); HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx); -uint32_t USB_ReadInterrupts(USB_TypeDef *USBx); +uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx); HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx); HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx); -void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, +void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); -void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, +void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); /**
diff --git a/Release_Notes.html b/Release_Notes.html index c141efc..9b27cea 100644 --- a/Release_Notes.html +++ b/Release_Notes.html
@@ -40,7 +40,7 @@ <div class="col-sm-12 col-lg-8"> <h1 id="update-history">Update History</h1> <div class="collapse"> -<input type="checkbox" id="collapse-section15" checked aria-hidden="true"> <label for="collapse-section15" aria-hidden="true">V1.13.0 / 8-February-2023</label> +<input type="checkbox" id="collapse-section16" checked aria-hidden="true"> <label for="collapse-section16" aria-hidden="true">V1.14.0 / 07-June-2023</label> <div> <h2 id="main-changes">Main Changes</h2> <ul> @@ -50,6 +50,67 @@ <h2 id="contents">Contents</h2> <h3 id="hal-drivers-updates"><strong>HAL Drivers</strong> updates</h3> <ul> +<li><strong>HAL CRYP</strong> driver +<ul> +<li>Update Crypt/Decrypt IT processes to avoid Computation Completed IRQ fires before the DINR pointer increment</li> +</ul></li> +<li><strong>HAL Generic</strong> driver +<ul> +<li>Update of HAL_GetTickFreq() brief</li> +</ul></li> +<li><strong>HAL I2C</strong> driver +<ul> +<li>Change HAL_I2C_IsDeviceReady to support 10 bit addressing mode</li> +<li>Update HAL I2C driver to prefetch data before starting the transmission: implementation of errata sheet workaround I2C2-190208 : Transmission stalled after first byte</li> +<li>Update HAL I2C driver to disable all interrupts after end of transaction</li> +<li>Update HAL_I2C_Init API to clear ADD10 bit in 7 bit addressing mode</li> +<li>Update HAL_I2C_Mem_Write_IT API to initialize XferSize at 0</li> +</ul></li> +<li><strong>HAL SMBUS</strong> driver +<ul> +<li>Update HAL I2C driver to prefetch data before starting the transmission: implementation of errata sheet workaround I2C2-190208 : Transmission stalled after first byte</li> +</ul></li> +<li><strong>HAL SPI</strong> driver +<ul> +<li>Fix driver to don’t update state in case of error. (HAL_SPI_STATE_READY will be set only in case of HAL_TIMEOUT)</li> +<li>Update HAL_SPI_TransmitReceive API to set the bit CRCNEXT in case of one byte transaction</li> +<li>Update IT API to enable interrupts after process unlock</li> +</ul></li> +<li><strong>HAL TSC</strong> driver +<ul> +<li>Add parameter assertion depends on Duration time restriction link to product</li> +</ul></li> +<li><strong>HAL UART</strong> driver +<ul> +<li>Update initialisation sequence for TXINV, RXINV and TXRXSWAP settings</li> +</ul></li> +</ul> +<p><br /> +</p> +<h3 id="ll-drivers-updates"><strong>LL Drivers</strong> updates</h3> +<ul> +<li><strong>LL USB</strong> driver +<ul> +<li>Add USB_EPStopXfer() function</li> +</ul></li> +</ul> +<p><br /> +</p> +<h2 id="backward-compatibility">Backward Compatibility</h2> +<p>This release is compatible with the previous versions.</p> +</div> +</div> +<div class="collapse"> +<input type="checkbox" id="collapse-section15" aria-hidden="true"> <label for="collapse-section15" aria-hidden="true">V1.13.0 / 8-February-2023</label> +<div> +<h2 id="main-changes-1">Main Changes</h2> +<ul> +<li>Maintenance release of HAL and Low Layer drivers to include latest corrections</li> +<li>HAL/LL code quality enhancement</li> +</ul> +<h2 id="contents-1">Contents</h2> +<h3 id="hal-drivers-updates-1"><strong>HAL Drivers</strong> updates</h3> +<ul> <li><strong>HAL FLASH</strong> driver <ul> <li>Fix missing STM32WB10xx preprocessor checks for several constants (FLASH_PCROP_GRANULARITY_OFFSET,SRAM2B_START_SECURE_ADDR_4,FLASH_PAGE_SIZE..)</li> @@ -79,20 +140,20 @@ </ul> <p><br /> </p> -<h2 id="backward-compatibility">Backward Compatibility</h2> +<h2 id="backward-compatibility-1">Backward Compatibility</h2> <p>This release is compatible with the previous versions.</p> </div> </div> <div class="collapse"> <input type="checkbox" id="collapse-section14" aria-hidden="true"> <label for="collapse-section14" aria-hidden="true">V1.12.0 / 09-November-2022</label> <div> -<h2 id="main-changes-1">Main Changes</h2> +<h2 id="main-changes-2">Main Changes</h2> <ul> <li>Maintenance release of HAL and Low Layer drivers to include latest corrections</li> <li>Remove HAL_LOCK/HAL_UNLOCK calls in HAL_xxxx_RegisterCallback & HAL_xxxx_UnregisterCallback for IPs (IRDA, LPTIM, SMARTCARD, TIM, UART, USART)</li> </ul> -<h2 id="contents-1">Contents</h2> -<h3 id="hal-drivers-updates-1"><strong>HAL Drivers</strong> updates</h3> +<h2 id="contents-2">Contents</h2> +<h3 id="hal-drivers-updates-2"><strong>HAL Drivers</strong> updates</h3> <ul> <li><strong>HAL ADC</strong> driver <ul> @@ -139,7 +200,7 @@ </ul> <p><br /> </p> -<h3 id="ll-drivers-updates"><strong>LL Drivers</strong> updates</h3> +<h3 id="ll-drivers-updates-1"><strong>LL Drivers</strong> updates</h3> <ul> <li><strong>LL ADC</strong> driver <ul> @@ -160,20 +221,20 @@ </ul> <p><br /> </p> -<h2 id="backward-compatibility-1">Backward Compatibility</h2> +<h2 id="backward-compatibility-2">Backward Compatibility</h2> <p>This release is compatible with the previous versions.</p> </div> </div> <div class="collapse"> <input type="checkbox" id="collapse-section13" aria-hidden="true"> <label for="collapse-section13" aria-hidden="true">V1.11.0 / 01-June-2022</label> <div> -<h2 id="main-changes-2">Main Changes</h2> +<h2 id="main-changes-3">Main Changes</h2> <ul> <li>Maintenance release of HAL and Low Layer drivers to include latest corrections</li> <li>Correct English spelling errors and typos</li> </ul> -<h2 id="contents-2">Contents</h2> -<h3 id="hal-drivers-updates-2"><strong>HAL Drivers</strong> updates</h3> +<h2 id="contents-3">Contents</h2> +<h3 id="hal-drivers-updates-3"><strong>HAL Drivers</strong> updates</h3> <ul> <li><strong>HAL EXTI</strong> driver <ul> @@ -249,7 +310,7 @@ </ul> <p><br /> </p> -<h3 id="ll-drivers-updates-1"><strong>LL Drivers</strong> updates</h3> +<h3 id="ll-drivers-updates-2"><strong>LL Drivers</strong> updates</h3> <ul> <li><strong>LL I2C</strong> driver <ul> @@ -285,19 +346,19 @@ </ul> <p><br /> </p> -<h2 id="backward-compatibility-2">Backward Compatibility</h2> +<h2 id="backward-compatibility-3">Backward Compatibility</h2> <p>This release is compatible with the previous versions.</p> </div> </div> <div class="collapse"> <input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true">V1.10.1 / 27-March-2022</label> <div> -<h2 id="main-changes-3">Main Changes</h2> +<h2 id="main-changes-4">Main Changes</h2> <ul> <li>Patch release of <strong>HAL and Low Layer</strong> drivers</li> </ul> -<h2 id="contents-3">Contents</h2> -<h3 id="hal-drivers-updates-3"><strong>HAL Drivers</strong> updates</h3> +<h2 id="contents-4">Contents</h2> +<h3 id="hal-drivers-updates-4"><strong>HAL Drivers</strong> updates</h3> <ul> <li><strong>HAL COMP</strong> driver <ul> @@ -306,7 +367,7 @@ </ul> <p><br /> </p> -<h3 id="ll-drivers-updates-2"><strong>LL Drivers</strong> updates</h3> +<h3 id="ll-drivers-updates-3"><strong>LL Drivers</strong> updates</h3> <ul> <li><strong>LL COMP</strong> driver <ul> @@ -315,21 +376,21 @@ </ul> <p><br /> </p> -<h2 id="backward-compatibility-3">Backward Compatibility</h2> +<h2 id="backward-compatibility-4">Backward Compatibility</h2> <p>This release is compatible with the previous versions.</p> </div> </div> <div class="collapse"> <input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true">V1.10.0 / 12-November-2021</label> <div> -<h2 id="main-changes-4">Main Changes</h2> +<h2 id="main-changes-5">Main Changes</h2> <ul> <li>Maintenance release of <strong>HAL and Low Layer</strong> drivers to include latest corrections</li> <li>All source files: update disclaimer to add reference to the new license agreement</li> <li>Correct English spelling errors and typos</li> </ul> -<h2 id="contents-4">Contents</h2> -<h3 id="hal-drivers-updates-4"><strong>HAL Drivers</strong> updates</h3> +<h2 id="contents-5">Contents</h2> +<h3 id="hal-drivers-updates-5"><strong>HAL Drivers</strong> updates</h3> <ul> <li><strong>HAL ADC</strong> driver <ul> @@ -400,7 +461,7 @@ </ul> <p><br /> </p> -<h3 id="ll-drivers-updates-3"><strong>LL Drivers</strong> updates</h3> +<h3 id="ll-drivers-updates-4"><strong>LL Drivers</strong> updates</h3> <ul> <li><strong>LL ADC</strong> driver <ul> @@ -415,14 +476,14 @@ </ul> <p><br /> </p> -<h2 id="backward-compatibility-4">Backward Compatibility</h2> +<h2 id="backward-compatibility-5">Backward Compatibility</h2> <p>This release is compatible with the previous versions.</p> </div> </div> <div class="collapse"> <input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true">V1.9.0 / 24-June-2021</label> <div> -<h2 id="main-changes-5">Main Changes</h2> +<h2 id="main-changes-6">Main Changes</h2> <ul> <li>Maintenance release of <strong>HAL and Low Layer</strong> drivers to include latest corrections</li> <li>Update of HAL SMBUS driver to introduce fast mode and fast mode plus @@ -436,8 +497,8 @@ </ul> <p><br /> </p> -<h2 id="contents-5">Contents</h2> -<h3 id="hal-drivers-updates-5"><strong>HAL Drivers</strong> updates</h3> +<h2 id="contents-6">Contents</h2> +<h3 id="hal-drivers-updates-6"><strong>HAL Drivers</strong> updates</h3> <ul> <li><strong>HAL CORTEX</strong> driver <ul> @@ -513,7 +574,7 @@ </ul> <p><br /> </p> -<h3 id="ll-drivers-updates-4"><strong>LL Drivers</strong> updates</h3> +<h3 id="ll-drivers-updates-5"><strong>LL Drivers</strong> updates</h3> <ul> <li><strong>LL DMA</strong> driver <ul> @@ -540,14 +601,14 @@ </ul> <p><br /> </p> -<h2 id="backward-compatibility-5">Backward Compatibility</h2> +<h2 id="backward-compatibility-6">Backward Compatibility</h2> <p>This release is compatible with the previous versions.</p> </div> </div> <div class="collapse"> <input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true">v1.8.0 / 12-February-2021</label> <div> -<h2 id="main-changes-6">Main Changes</h2> +<h2 id="main-changes-7">Main Changes</h2> <h3 id="add-support-for-stm32wb15xx-and-stm32wb10xx">Add support for STM32WB15xx and STM32WB10xx</h3> <table> <thead> @@ -683,14 +744,14 @@ </tr> </tbody> </table> -<h2 id="backward-compatibility-6">Backward Compatibility</h2> +<h2 id="backward-compatibility-7">Backward Compatibility</h2> <p>This release is compatible with the previous versions.</p> </div> </div> <div class="collapse"> <input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true">v1.7.0 / 30-October-2020</label> <div> -<h2 id="main-changes-7">Main Changes</h2> +<h2 id="main-changes-8">Main Changes</h2> <h3 id="maitenance-release">Maitenance release</h3> <p>All peripheral</p> <table> @@ -763,14 +824,14 @@ </tr> </tbody> </table> -<h2 id="backward-compatibility-7">Backward Compatibility</h2> +<h2 id="backward-compatibility-8">Backward Compatibility</h2> <p>This release is compatible with the previous versions.</p> </div> </div> <div class="collapse"> <input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">v1.6.0 / 05-June-2020</label> <div> -<h2 id="main-changes-8">Main Changes</h2> +<h2 id="main-changes-9">Main Changes</h2> <h3 id="maitenance-release-1">Maitenance release</h3> <p>All peripheral</p> <table> @@ -875,14 +936,14 @@ </tr> </tbody> </table> -<h2 id="backward-compatibility-8">Backward Compatibility</h2> +<h2 id="backward-compatibility-9">Backward Compatibility</h2> <p>This release is compatible with the previous versions.</p> </div> </div> <div class="collapse"> <input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">v1.5.0 / 12-February-2020</label> <div> -<h2 id="main-changes-9">Main Changes</h2> +<h2 id="main-changes-10">Main Changes</h2> <h3 id="introduction-of-stm32wb5m-stm32wb35xx-and-stm32wb30xx-product">Introduction of STM32WB5M, STM32WB35xx and STM32WB30xx product</h3> <p>This release introduce the support of STM32WB5Mxx, STM32WB35xx product and its value line STM32WB30xx.</p> <p>Added features:</p> @@ -927,14 +988,14 @@ </tr> </tbody> </table> -<h2 id="backward-compatibility-9">Backward Compatibility</h2> +<h2 id="backward-compatibility-10">Backward Compatibility</h2> <p>This release is compatible with the previous versions.</p> </div> </div> <div class="collapse"> <input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">v1.4.0 / 15-December-2019</label> <div> -<h2 id="main-changes-10">Main Changes</h2> +<h2 id="main-changes-11">Main Changes</h2> <h3 id="maitenance-release-2">Maitenance release</h3> <table> <thead> @@ -978,7 +1039,7 @@ </tr> </tbody> </table> -<h2 id="backward-compatibility-10">Backward Compatibility</h2> +<h2 id="backward-compatibility-11">Backward Compatibility</h2> <p>This release is compatible with the previous versions.</p> <h2 id="dependencies">Dependencies</h2> <p>This software release is compatible with:</p> @@ -988,7 +1049,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">v1.3.0 / 11-September-2019</label> <div> -<h2 id="main-changes-11">Main Changes</h2> +<h2 id="main-changes-12">Main Changes</h2> <h3 id="maitenance-release-3">Maitenance release</h3> <table> <thead> @@ -1060,7 +1121,7 @@ </tr> </tbody> </table> -<h2 id="backward-compatibility-11">Backward Compatibility</h2> +<h2 id="backward-compatibility-12">Backward Compatibility</h2> <p>This release is compatible with the previous versions.</p> <h2 id="dependencies-1">Dependencies</h2> <p>This software release is compatible with:</p> @@ -1070,7 +1131,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.2.0 / 26-June-2019</label> <div> -<h2 id="main-changes-12">Main Changes</h2> +<h2 id="main-changes-13">Main Changes</h2> <h3 id="stm32wb50xx-introduction-and-maintenance-release">STM32WB50xx introduction and maintenance release</h3> <p>First release for STM32WBxx HAL drivers introducing <strong>stm32wb50xx</strong> devices.</p> <table> @@ -1139,7 +1200,7 @@ </tr> </tbody> </table> -<h2 id="backward-compatibility-12">Backward Compatibility</h2> +<h2 id="backward-compatibility-13">Backward Compatibility</h2> <p>This release is compatible with the previous versions.</p> <h2 id="dependencies-2">Dependencies</h2> <p>This software release is compatible with:</p> @@ -1149,7 +1210,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 05-April-2019</label> <div> -<h2 id="main-changes-13">Main Changes</h2> +<h2 id="main-changes-14">Main Changes</h2> <h3 id="maintenance-release">Maintenance release</h3> <p>Maintenance release of HAL and Low layers drivers supporting STM32WB55xx devices.</p> <table> @@ -1203,7 +1264,7 @@ </tr> </tbody> </table> -<h2 id="backward-compatibility-13">Backward Compatibility</h2> +<h2 id="backward-compatibility-14">Backward Compatibility</h2> <p>This release is compatible with the previous versions.</p> <h2 id="dependencies-3">Dependencies</h2> <p>This software release is compatible with:</p> @@ -1213,7 +1274,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 06-February-2019</label> <div> -<h2 id="main-changes-14">Main Changes</h2> +<h2 id="main-changes-15">Main Changes</h2> <h3 id="first-release">First release</h3> <p>First official release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32WB55xx.</p> </div>
diff --git a/Src/stm32wbxx_hal.c b/Src/stm32wbxx_hal.c index 31abf2b..7c01352 100644 --- a/Src/stm32wbxx_hal.c +++ b/Src/stm32wbxx_hal.c
@@ -55,7 +55,7 @@ * @brief STM32WBxx HAL Driver version number */ #define __STM32WBxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WBxx_HAL_VERSION_SUB1 (0x0DU) /*!< [23:16] sub1 version */ +#define __STM32WBxx_HAL_VERSION_SUB1 (0x0EU) /*!< [23:16] sub1 version */ #define __STM32WBxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WBxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WBxx_HAL_VERSION ((__STM32WBxx_HAL_VERSION_MAIN << 24U)\ @@ -375,7 +375,8 @@ /** * @brief Return tick frequency. - * @retval tick period in Hz + * @retval Tick frequency. + * Value of @ref HAL_TickFreqTypeDef. */ HAL_TickFreqTypeDef HAL_GetTickFreq(void) {
diff --git a/Src/stm32wbxx_hal_comp.c b/Src/stm32wbxx_hal_comp.c index d344a07..3da9a71 100644 --- a/Src/stm32wbxx_hal_comp.c +++ b/Src/stm32wbxx_hal_comp.c
@@ -21,9 +21,9 @@ * ****************************************************************************** @verbatim -================================================================================ + ============================================================================== ##### COMP Peripheral features ##### -================================================================================ + ============================================================================== [..] The STM32WBxx device family integrates two analog comparators instances: @@ -50,7 +50,7 @@ using macro __HAL_COMP_COMPx_EXTI_GET_FLAG(). ##### How to use this driver ##### -================================================================================ + ============================================================================== [..] This driver provides functions to configure and program the comparator instances of STM32WBxx devices. @@ -156,7 +156,6 @@ @endverbatim ****************************************************************************** - */ /* Includes ------------------------------------------------------------------*/ @@ -186,7 +185,7 @@ /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSTART"). */ /* Unit: us */ -#define COMP_DELAY_STARTUP_US (80UL) /*!< Delay for COMP startup time */ +#define COMP_DELAY_STARTUP_US (80UL) /*!< Delay for COMP startup time */ /* Delay for COMP voltage scaler stabilization time. */ /* Literal set to maximum value (refer to device datasheet, */ @@ -239,11 +238,11 @@ HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if(hcomp == NULL) + if (hcomp == NULL) { status = HAL_ERROR; } - else if(__HAL_COMP_IS_LOCKED(hcomp)) + else if (__HAL_COMP_IS_LOCKED(hcomp)) { status = HAL_ERROR; } @@ -258,11 +257,13 @@ assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis)); assert_param(IS_COMP_BLANKINGSRC_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce)); assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode)); + #if defined(COMP2) assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode)); #endif - if(hcomp->State == HAL_COMP_STATE_RESET) + + if (hcomp->State == HAL_COMP_STATE_RESET) { /* Allocate lock resource and initialize it */ hcomp->Lock = HAL_UNLOCKED; @@ -270,7 +271,6 @@ /* Set COMP error code to none */ COMP_CLEAR_ERRORCODE(hcomp); - #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) /* Init the COMP Callback settings */ hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */ @@ -298,7 +298,7 @@ comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN); /* Set COMP parameters */ - tmp_csr = ( hcomp->Init.InputMinus + tmp_csr = (hcomp->Init.InputMinus | hcomp->Init.InputPlus | hcomp->Init.BlankingSrce | hcomp->Init.Hysteresis @@ -318,18 +318,19 @@ #else MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_PWRMODE | COMP_CSR_INMSEL | COMP_CSR_INPSEL | - COMP_CSR_POLARITY | COMP_CSR_HYST | + COMP_CSR_POLARITY | COMP_CSR_HYST | COMP_CSR_BLANKING | COMP_CSR_BRGEN | COMP_CSR_SCALEN | COMP_CSR_INMESEL, tmp_csr ); #endif /* COMP_CSR_WINMODE */ + #if defined(COMP2) /* Set window mode */ /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */ /* instances. Therefore, this function can update another COMP */ /* instance that the one currently selected. */ - if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) + if (hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) { SET_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE); } @@ -339,17 +340,18 @@ } #endif /* COMP2 */ + /* Delay for COMP scaler bridge voltage stabilization */ /* Apply the delay if voltage scaler bridge is required and not already enabled */ if ((READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN) != 0UL) && - (comp_voltage_scaler_initialized == 0UL) ) + (comp_voltage_scaler_initialized == 0UL)) { /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); - while(wait_loop_index != 0UL) + while (wait_loop_index != 0UL) { wait_loop_index--; } @@ -359,10 +361,10 @@ exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); /* Manage EXTI settings */ - if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL) + if ((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL) { /* Configure EXTI rising edge */ - if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL) + if ((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL) { LL_EXTI_EnableRisingTrig_0_31(exti_line); } @@ -372,7 +374,7 @@ } /* Configure EXTI falling edge */ - if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL) + if ((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL) { LL_EXTI_EnableFallingTrig_0_31(exti_line); } @@ -385,7 +387,7 @@ LL_EXTI_ClearFlag_0_31(exti_line); /* Configure EXTI event mode */ - if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL) + if ((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL) { LL_EXTI_EnableEvent_0_31(exti_line); } @@ -395,7 +397,7 @@ } /* Configure EXTI interrupt mode */ - if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL) + if ((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL) { LL_EXTI_EnableIT_0_31(exti_line); } @@ -437,11 +439,11 @@ HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if(hcomp == NULL) + if (hcomp == NULL) { status = HAL_ERROR; } - else if(__HAL_COMP_IS_LOCKED(hcomp)) + else if (__HAL_COMP_IS_LOCKED(hcomp)) { status = HAL_ERROR; } @@ -520,7 +522,8 @@ * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, + pCOMP_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -696,11 +699,11 @@ HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if(hcomp == NULL) + if (hcomp == NULL) { status = HAL_ERROR; } - else if(__HAL_COMP_IS_LOCKED(hcomp)) + else if (__HAL_COMP_IS_LOCKED(hcomp)) { status = HAL_ERROR; } @@ -709,7 +712,7 @@ /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - if(hcomp->State == HAL_COMP_STATE_READY) + if (hcomp->State == HAL_COMP_STATE_READY) { /* Enable the selected comparator */ SET_BIT(hcomp->Instance->CSR, COMP_CSR_EN); @@ -723,7 +726,7 @@ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); - while(wait_loop_index != 0UL) + while (wait_loop_index != 0UL) { wait_loop_index--; } @@ -747,11 +750,11 @@ HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if(hcomp == NULL) + if (hcomp == NULL) { status = HAL_ERROR; } - else if(__HAL_COMP_IS_LOCKED(hcomp)) + else if (__HAL_COMP_IS_LOCKED(hcomp)) { status = HAL_ERROR; } @@ -762,7 +765,7 @@ /* Check compliant states: HAL_COMP_STATE_READY or HAL_COMP_STATE_BUSY */ /* (all states except HAL_COMP_STATE_RESET and except locked status. */ - if(hcomp->State != HAL_COMP_STATE_RESET) + if (hcomp->State != HAL_COMP_STATE_RESET) { /* Disable the selected comparator */ CLEAR_BIT(hcomp->Instance->CSR, COMP_CSR_EN); @@ -790,11 +793,11 @@ uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); /* Check COMP EXTI flag */ - if(LL_EXTI_IsActiveFlag_0_31(exti_line) != 0UL) + if (LL_EXTI_IsActiveFlag_0_31(exti_line) != 0UL) { #if defined(COMP2) /* Check whether comparator is in independent or window mode */ - if(READ_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE) != 0UL) + if (READ_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE) != 0UL) { /* Clear COMP EXTI line pending bit of the pair of comparators */ /* in window mode. */ @@ -852,11 +855,11 @@ HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if(hcomp == NULL) + if (hcomp == NULL) { status = HAL_ERROR; } - else if(__HAL_COMP_IS_LOCKED(hcomp)) + else if (__HAL_COMP_IS_LOCKED(hcomp)) { status = HAL_ERROR; } @@ -866,7 +869,7 @@ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); /* Set HAL COMP handle state */ - switch(hcomp->State) + switch (hcomp->State) { case HAL_COMP_STATE_RESET: hcomp->State = HAL_COMP_STATE_RESET_LOCKED; @@ -878,10 +881,7 @@ hcomp->State = HAL_COMP_STATE_BUSY_LOCKED; break; } - } - if(status == HAL_OK) - { /* Set the lock bit corresponding to selected comparator */ __HAL_COMP_LOCK(hcomp); } @@ -959,7 +959,7 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp) { /* Check the COMP handle allocation */ - if(hcomp == NULL) + if (hcomp == NULL) { return HAL_COMP_STATE_RESET; }
diff --git a/Src/stm32wbxx_hal_crc.c b/Src/stm32wbxx_hal_crc.c index 9d229d0..d1b1b63 100644 --- a/Src/stm32wbxx_hal_crc.c +++ b/Src/stm32wbxx_hal_crc.c
@@ -403,7 +403,7 @@ * @param hcrc CRC handle * @retval HAL state */ -HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) +HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc) { /* Return CRC handle state */ return hcrc->State;
diff --git a/Src/stm32wbxx_hal_crc_ex.c b/Src/stm32wbxx_hal_crc_ex.c index 25a4c13..3cd8e96 100644 --- a/Src/stm32wbxx_hal_crc_ex.c +++ b/Src/stm32wbxx_hal_crc_ex.c
@@ -94,7 +94,7 @@ /* Check the parameters */ assert_param(IS_CRC_POL_LENGTH(PolyLength)); - /* Ensure that the generating polynomial is odd */ + /* Ensure that the generating polynomial is odd */ if ((Pol & (uint32_t)(0x1U)) == 0U) { status = HAL_ERROR; @@ -114,7 +114,7 @@ switch (PolyLength) { - + case CRC_POLYLENGTH_7B: if (msb >= HAL_CRC_LENGTH_7B) { @@ -133,7 +133,7 @@ status = HAL_ERROR; } break; - + case CRC_POLYLENGTH_32B: /* no polynomial definition vs. polynomial length issue possible */ break;
diff --git a/Src/stm32wbxx_hal_cryp.c b/Src/stm32wbxx_hal_cryp.c index d3467f6..e668b5f 100644 --- a/Src/stm32wbxx_hal_cryp.c +++ b/Src/stm32wbxx_hal_cryp.c
@@ -59,7 +59,7 @@ algorithms) is in words or bytes. (##) The Header used only in AES GCM and CCM Algorithm for authentication. (##) The HeaderSize providing the size of the header buffer in words or bytes, depending upon HeaderWidthUnit field. - (##) The HeaderWidthUnit field. It specifies whether the header length (for authentication algorithms) is in words or bytes. + (##) The HeaderWidthUnit field. It specifies whether the header length (for authentication algorithms) is in words or bytes. (##) The B0 block is the first authentication block used only in AES CCM mode. (##) The KeyIVConfigSkip used to process several messages in a row (please see more information below). @@ -78,7 +78,7 @@ the CRYP peripheral is configured and processes the buffer in input. At second call, no need to Initialize the CRYP, user have to get current configuration via HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set - new parametres, finally user can start encryption/decryption. + new parameters, finally user can start encryption/decryption. (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral. @@ -200,7 +200,7 @@ (##) To perform message payload encryption or decryption AES is configured in CTR mode. (##) For authentication two phases are performed : - Header phase: peripheral processes the Additional Authenticated Data (AAD) first, then the cleartext message - only cleartext payload (not the ciphertext payload) is used and no outpout. + only cleartext payload (not the ciphertext payload) is used and no output. (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data. *** Callback registration *** @@ -390,12 +390,12 @@ static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) -static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output); -static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input); -static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output); -static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input); -static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output, uint32_t KeySize); -static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input, uint32_t KeySize); +static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output); +static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input); +static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output); +static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input); +static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output, uint32_t KeySize); +static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t KeySize); static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp); #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ @@ -488,7 +488,8 @@ #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ /* Set the key size (This bit field is do not care in the DES or TDES modes), data type and Algorithm */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, + hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); /* Reset Error Code field */ hcryp->ErrorCode = HAL_CRYP_ERROR_NONE; @@ -511,7 +512,7 @@ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) { /* Check the CRYP handle allocation */ @@ -600,7 +601,8 @@ hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip; /* Set the key size (This bit field is do not care in the DES or TDES modes), data type and operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, + hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); /*clear error flags*/ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR); @@ -733,7 +735,8 @@ * @param pCallback pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, + pCRYP_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -954,14 +957,14 @@ /* If authentication algorithms on-going, carry out first saving steps before disable the peripheral */ if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || \ - (hcryp->Init.Algorithm == CRYP_AES_CCM)) + (hcryp->Init.Algorithm == CRYP_AES_CCM)) { - /* Save Suspension registers */ - CRYP_Read_SuspendRegisters(hcryp, hcryp->SUSPxR_saved); - /* Save Key */ - CRYP_Read_KeyRegisters(hcryp, hcryp->Key_saved, hcryp->Init.KeySize); - /* Save IV */ - CRYP_Read_IVRegisters(hcryp, hcryp->IV_saved); + /* Save Suspension registers */ + CRYP_Read_SuspendRegisters(hcryp, hcryp->SUSPxR_saved); + /* Save Key */ + CRYP_Read_KeyRegisters(hcryp, hcryp->Key_saved, hcryp->Init.KeySize); + /* Save IV */ + CRYP_Read_IVRegisters(hcryp, hcryp->IV_saved); } /* Disable AES */ __HAL_CRYP_DISABLE(hcryp); @@ -974,7 +977,7 @@ hcryp->CrypOutCount_saved = hcryp->CrypOutCount; hcryp->Phase_saved = hcryp->Phase; hcryp->State_saved = hcryp->State; - hcryp->Size_saved = ( (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) ? (hcryp->Size /4U) : hcryp->Size); + hcryp->Size_saved = ((hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) ? (hcryp->Size / 4U) : hcryp->Size); hcryp->SizesSum_saved = hcryp->SizesSum; hcryp->AutoKeyDerivation_saved = hcryp->AutoKeyDerivation; hcryp->CrypHeaderCount_saved = hcryp->CrypHeaderCount; @@ -1032,7 +1035,7 @@ hcryp->AutoKeyDerivation = hcryp->AutoKeyDerivation_saved; if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \ - (hcryp->Init.Algorithm == CRYP_AES_CTR)) + (hcryp->Init.Algorithm == CRYP_AES_CTR)) { hcryp->Init.pInitVect = hcryp->IV_saved; } @@ -1200,7 +1203,8 @@ * @param Timeout Specify Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout) +HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, + uint32_t Timeout) { uint32_t algo; HAL_StatusTypeDef status; @@ -1300,7 +1304,8 @@ * @param Timeout Specify Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout) +HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, + uint32_t Timeout) { HAL_StatusTypeDef status; uint32_t algo; @@ -1420,26 +1425,26 @@ /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/ #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) - if (hcryp->ResumingFlag == 1U) - { - hcryp->ResumingFlag = 0U; - if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED) - { - hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved; - hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved; - } - else - { - hcryp->CrypInCount = 0U; - hcryp->CrypOutCount = 0U; - } - } - else + if (hcryp->ResumingFlag == 1U) + { + hcryp->ResumingFlag = 0U; + if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED) + { + hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved; + hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved; + } + else + { + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + } + } + else #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ - { - hcryp->CrypInCount = 0U; - hcryp->CrypOutCount = 0U; - } + { + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + } hcryp->pCrypInBuffPtr = Input; hcryp->pCrypOutBuffPtr = Output; @@ -1530,26 +1535,26 @@ /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/ #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) - if (hcryp->ResumingFlag == 1U) - { - hcryp->ResumingFlag = 0U; - if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED) - { - hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved; - hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved; - } - else - { - hcryp->CrypInCount = 0U; - hcryp->CrypOutCount = 0U; - } - } - else + if (hcryp->ResumingFlag == 1U) + { + hcryp->ResumingFlag = 0U; + if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED) + { + hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved; + hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved; + } + else + { + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + } + } + else #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ - { - hcryp->CrypInCount = 0U; - hcryp->CrypOutCount = 0U; - } + { + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + } hcryp->pCrypInBuffPtr = Input; hcryp->pCrypOutBuffPtr = Output; @@ -1858,15 +1863,15 @@ { /* Check if error occurred */ - if (__HAL_CRYP_GET_IT_SOURCE(hcryp,CRYP_IT_ERRIE) != RESET) + if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_ERRIE) != RESET) { /* If write Error occurred */ - if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_WRERR) != RESET) + if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_WRERR) != RESET) { hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE; } /* If read Error occurred */ - if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_RDERR) != RESET) + if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_RDERR) != RESET) { hcryp->ErrorCode |= HAL_CRYP_ERROR_READ; } @@ -1874,31 +1879,31 @@ if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_CCF) != RESET) { - if(__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET) - { - /* Clear computation complete flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - - if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || (hcryp->Init.Algorithm == CRYP_AES_CCM)) + if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET) { + /* Clear computation complete flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - /* if header phase */ - if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER) + if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || (hcryp->Init.Algorithm == CRYP_AES_CCM)) { - CRYP_GCMCCM_SetHeaderPhase_IT(hcryp); + + /* if header phase */ + if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER) + { + CRYP_GCMCCM_SetHeaderPhase_IT(hcryp); + } + else /* if payload phase */ + { + CRYP_GCMCCM_SetPayloadPhase_IT(hcryp); + } } - else /* if payload phase */ + else /* AES Algorithm ECB,CBC or CTR*/ { - CRYP_GCMCCM_SetPayloadPhase_IT(hcryp); + CRYP_AES_IT(hcryp); } } - else /* AES Algorithm ECB,CBC or CTR*/ - { - CRYP_AES_IT(hcryp); - } } } -} /** * @brief Return the CRYP error code. @@ -2106,15 +2111,17 @@ /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); - /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + /* Increment the pointer before writing the input block in the IN FIFO to make sure that + when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value + and it is ready for the next operation. */ hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); } else { @@ -2134,7 +2141,7 @@ * @param hcryp pointer to a CRYP_HandleTypeDef structure * @param Timeout Specify Timeout value * @retval HAL status -*/ + */ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { uint16_t incount; /* Temporary CrypInCount Value */ @@ -2307,8 +2314,7 @@ __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -2352,15 +2358,17 @@ /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); - /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + /* Increment the pointer before writing the input block in the IN FIFO to make sure that + when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value + and it is ready for the next operation. */ hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); } else { @@ -2436,8 +2444,7 @@ __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -2503,9 +2510,10 @@ uint32_t loopcounter; uint32_t headersize_in_bytes; uint32_t tmp; - uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ + static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ /* Stop the DMA transfers to the IN FIFO by clearing to "0" the DMAINEN */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); @@ -2577,17 +2585,17 @@ else { uint32_t algo; - /* ECB, CBC or CTR end of input data feeding + /* ECB, CBC or CTR end of input data feeding or end of GCM/CCM payload data feeding through DMA */ algo = hcryp->Instance->CR & AES_CR_CHMOD; - /* Don't call input data transfer complete callback only if + /* Don't call input data transfer complete callback only if it remains some input data to write to the peripheral. This case can only occur for GCM and CCM with a payload length not a multiple of 16 bytes */ if (!(((algo == CRYP_AES_GCM_GMAC) || (algo == CRYP_AES_CCM)) && \ - (((hcryp->Size) % 16U) != 0U))) + (((hcryp->Size) % 16U) != 0U))) { /* Call input data transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -2669,7 +2677,7 @@ #else /*Call legacy weak Input complete callback*/ HAL_CRYP_InCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ /*Wait on CCF flag*/ CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE); @@ -2682,7 +2690,7 @@ } count = 0U; - while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (count<4U)) + while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (count < 4U)) { *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[count]; hcryp->CrypOutCount++; @@ -2690,7 +2698,8 @@ } } - if (((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC) && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM)) + if (((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC) + && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM)) { /* Disable CRYP (not allowed in GCM)*/ __HAL_CRYP_DISABLE(hcryp); @@ -2892,8 +2901,8 @@ { temp[i] = hcryp->Instance->DOUTR; } - i= 0U; - while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (i<4U)) + i = 0U; + while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) { *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; hcryp->CrypOutCount++; @@ -2921,14 +2930,14 @@ { temp[i] = hcryp->Instance->DOUTR; } - i= 0U; - while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (i<4U)) + i = 0U; + while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) { *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; hcryp->CrypOutCount++; i++; } - if (hcryp->CrypOutCount == (hcryp->Size / 4U)) + if (hcryp->CrypOutCount == (hcryp->Size / 4U)) { /* Disable Computation Complete flag and errors interrupts */ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); @@ -2964,13 +2973,13 @@ /* reset SuspendRequest */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; /* Disable Computation Complete Flag and Errors Interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_SUSPENDED; /* Mark that the payload phase is suspended */ hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); } else @@ -2986,7 +2995,7 @@ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if (hcryp->CrypInCount == (hcryp->Size / 4U)) + if (hcryp->CrypInCount == (hcryp->Size / 4U)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -3271,9 +3280,10 @@ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ uint32_t headersize_in_bytes; uint32_t tmp; - uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ + static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) @@ -3358,8 +3368,7 @@ __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -3408,7 +3417,7 @@ hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -3466,7 +3475,7 @@ #else /*Call legacy weak Input complete callback*/ HAL_CRYP_InCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } /* Enter header data */ @@ -3499,10 +3508,10 @@ loopcounter++; hcryp->CrypHeaderCount++ ; /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DINR = 0x0U; - loopcounter++; + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; hcryp->CrypHeaderCount++; } } @@ -3555,7 +3564,7 @@ hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -3613,7 +3622,7 @@ #else /*Call legacy weak Input complete callback*/ HAL_CRYP_InCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } @@ -3696,8 +3705,7 @@ __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -3842,7 +3850,7 @@ /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if (((HAL_GetTick() - tickstart) > Timeout) ||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -3913,7 +3921,7 @@ /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ temp[loopcounter] = hcryp->Instance->DOUTR; } - for (loopcounter = 0U; loopcounter<lastwordsize; loopcounter++) + for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) { *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[loopcounter]; hcryp->CrypOutCount++; @@ -3941,9 +3949,10 @@ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ uint32_t headersize_in_bytes; uint32_t tmp; - uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ + static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)) @@ -4016,8 +4025,7 @@ __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -4079,7 +4087,7 @@ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -4133,7 +4141,7 @@ #else /*Call legacy weak Input complete callback*/ HAL_CRYP_InCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } /* Enter header data */ @@ -4164,12 +4172,12 @@ hcryp->CrypHeaderCount++; loopcounter++; /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DINR = 0x0U; - loopcounter++; + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } } - } /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) /*Call registered Input complete callback*/ @@ -4220,7 +4228,7 @@ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -4274,7 +4282,7 @@ #else /*Call legacy weak Input complete callback*/ HAL_CRYP_InCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } @@ -4358,8 +4366,7 @@ __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -4410,8 +4417,8 @@ { temp[i] = hcryp->Instance->DOUTR; } - i= 0U; - while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (i<4U)) + i = 0U; + while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) { *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; hcryp->CrypOutCount++; @@ -4419,15 +4426,15 @@ } incount = hcryp->CrypInCount; outcount = hcryp->CrypOutCount; - if ((outcount >= (hcryp->Size / 4U)) && ((incount * 4U) >= hcryp->Size)) + if ((outcount >= (hcryp->Size / 4U)) && ((incount * 4U) >= hcryp->Size)) { - /* When in CCM with Key and IV configuration skipped, don't disable interruptions */ - if (!((hcryp->Init.Algorithm == CRYP_AES_CCM) && (hcryp->KeyIVConfig == 1U))) - { + /* When in CCM with Key and IV configuration skipped, don't disable interruptions */ + if (!((hcryp->Init.Algorithm == CRYP_AES_CCM) && (hcryp->KeyIVConfig == 1U))) + { /* Disable computation complete flag and errors interrupts */ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); - } + } /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_READY; @@ -4459,40 +4466,40 @@ /* reset SuspendRequest */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; /* Disable Computation Complete Flag and Errors Interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_SUSPENDED; /* Mark that the payload phase is suspended */ hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); } else #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ { - /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) - { - /* Call input transfer complete callback */ + /* Write the input block in the IN FIFO */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + { + /* Call input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); #else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } } } - } else /* Last block of payload < 128bit*/ { /* Compute the number of padding bytes in last block of payload */ @@ -4528,14 +4535,14 @@ hcryp->Instance->DINR = 0x0U; loopcounter++; } - /* Call input transfer complete callback */ + /* Call input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); #else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } @@ -4579,9 +4586,9 @@ npblb = 16U - (uint32_t)hcryp->Size; /* Set Npblb in case of AES GCM payload encryption or AES CCM payload decryption to get right tag*/ - reg = hcryp->Instance->CR & (AES_CR_CHMOD|AES_CR_MODE); - if ((reg == (CRYP_AES_GCM_GMAC|CRYP_OPERATINGMODE_ENCRYPT)) ||\ - (reg == (CRYP_AES_CCM|CRYP_OPERATINGMODE_DECRYPT))) + reg = hcryp->Instance->CR & (AES_CR_CHMOD | AES_CR_MODE); + if ((reg == (CRYP_AES_GCM_GMAC | CRYP_OPERATINGMODE_ENCRYPT)) || \ + (reg == (CRYP_AES_CCM | CRYP_OPERATINGMODE_DECRYPT))) { /* Specify the number of non-valid bytes using NPBLB register*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U); @@ -4617,7 +4624,7 @@ #else /*Call legacy weak Input complete callback*/ HAL_CRYP_InCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ /* Wait for CCF flag to be raised */ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; do @@ -4636,8 +4643,7 @@ __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -4660,14 +4666,14 @@ /* Process unlocked */ __HAL_UNLOCK(hcryp); - /* Call Output transfer complete callback */ + /* Call Output transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered Output complete callback*/ - hcryp->OutCpltCallback(hcryp); + /*Call registered Output complete callback*/ + hcryp->OutCpltCallback(hcryp); #else - /*Call legacy weak Output complete callback*/ - HAL_CRYP_OutCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + /*Call legacy weak Output complete callback*/ + HAL_CRYP_OutCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } return HAL_OK; @@ -4685,9 +4691,10 @@ uint32_t loopcounter; uint32_t size_in_bytes; uint32_t tmp; - uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ + static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ /***************************** Header phase for GCM/GMAC or CCM *********************************/ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) @@ -4789,17 +4796,17 @@ } else { - /* Enter last bytes, padded with zeros */ - tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)]; - hcryp->Instance->DINR = tmp; - loopcounter++; - /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DINR = 0x0U; - loopcounter++; - } + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; + loopcounter++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } } if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) @@ -4845,9 +4852,10 @@ uint32_t loopcounter; uint32_t headersize_in_bytes; uint32_t tmp; - uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ + static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ /***************************** Header phase for GCM/GMAC or CCM *********************************/ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) @@ -4874,7 +4882,8 @@ if (headersize_in_bytes >= 16U) { /* Initiate header DMA transfer */ - if (CRYP_SetHeaderDMAConfig(hcryp, (uint32_t)(hcryp->Init.Header), (uint16_t)((headersize_in_bytes / 16U) * 4U)) != HAL_OK) + if (CRYP_SetHeaderDMAConfig(hcryp, (uint32_t)(hcryp->Init.Header), + (uint16_t)((headersize_in_bytes / 16U) * 4U)) != HAL_OK) { return HAL_ERROR; } @@ -4966,9 +4975,10 @@ uint32_t mode; uint32_t headersize_in_bytes; uint32_t tmp; - uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ + static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) { @@ -5019,7 +5029,7 @@ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call the input data transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -5072,7 +5082,7 @@ #else /*Call legacy weak Input complete callback*/ HAL_CRYP_InCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } else if ((((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U)) @@ -5089,28 +5099,28 @@ /* reset SuspendRequest */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; /* Disable Computation Complete Flag and Errors Interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_SUSPENDED; /* Mark that the payload phase is suspended */ hcryp->Phase = CRYP_PHASE_HEADER_SUSPENDED; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hcryp); } else #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ { - /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++; - } + /* Write the input block in the IN FIFO */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + } } else /* Write last header block (4 words), padded with zeros if needed */ { @@ -5140,10 +5150,10 @@ loopcounter++; hcryp->CrypHeaderCount++; /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DINR = 0x0U; - loopcounter++; + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; hcryp->CrypHeaderCount++; } } @@ -5207,15 +5217,14 @@ hcryp->State = HAL_CRYP_STATE_READY; #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); #else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); + /*Call legacy weak error callback*/ + HAL_CRYP_ErrorCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -5231,17 +5240,17 @@ * as soon as the suspended processing has to be resumed. * @retval None */ -static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output) +static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output) { uint32_t outputaddr = (uint32_t)Output; - *(uint32_t*)(outputaddr) = hcryp->Instance->IVR3; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->IVR2; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->IVR1; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->IVR0; + *(uint32_t *)(outputaddr) = hcryp->Instance->IVR3; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->IVR2; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->IVR1; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->IVR0; } /** @@ -5254,17 +5263,17 @@ * @note AES must be disabled when reconfiguring the IV values. * @retval None */ -static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input) +static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input) { uint32_t ivaddr = (uint32_t)Input; - hcryp->Instance->IVR3 = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->IVR2 = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->IVR1 = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->IVR0 = *(uint32_t*)(ivaddr); + hcryp->Instance->IVR3 = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->IVR2 = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->IVR1 = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->IVR0 = *(uint32_t *)(ivaddr); } /** @@ -5277,52 +5286,52 @@ * as soon as the suspended processing has to be resumed. * @retval None */ -static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output) +static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output) { uint32_t outputaddr = (uint32_t)Output; __IO uint32_t count = 0U; /* In case of GCM payload phase encryption, check that suspension can be carried out */ - if (READ_BIT(hcryp->Instance->CR, (AES_CR_CHMOD|AES_CR_GCMPH|AES_CR_MODE)) == (CRYP_AES_GCM_GMAC|AES_CR_GCMPH_1|0x0U)) + if (READ_BIT(hcryp->Instance->CR, + (AES_CR_CHMOD | AES_CR_GCMPH | AES_CR_MODE)) == (CRYP_AES_GCM_GMAC | AES_CR_GCMPH_1 | 0x0U)) { - /* Wait for BUSY flag to be cleared */ - count = 0xFFF; - do + /* Wait for BUSY flag to be cleared */ + count = 0xFFF; + do + { + count-- ; + if (count == 0U) { - count-- ; - if(count == 0U) - { - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - HAL_CRYP_ErrorCallback(hcryp); - return; - } + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + HAL_CRYP_ErrorCallback(hcryp); + return; } - while(HAL_IS_BIT_SET(hcryp->Instance->SR, AES_SR_BUSY)); + } while (HAL_IS_BIT_SET(hcryp->Instance->SR, AES_SR_BUSY)); } - *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP7R; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP6R; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP5R; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP4R; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP3R; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP2R; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP1R; - outputaddr+=4U; - *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP0R; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP7R; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP6R; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP5R; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP4R; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP3R; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP2R; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP1R; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP0R; } /** @@ -5335,25 +5344,25 @@ * @note AES must be disabled when reconfiguring the suspend registers. * @retval None */ -static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input) +static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input) { uint32_t ivaddr = (uint32_t)Input; - hcryp->Instance->SUSP7R = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->SUSP6R = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->SUSP5R = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->SUSP4R = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->SUSP3R = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->SUSP2R = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->SUSP1R = *(uint32_t*)(ivaddr); - ivaddr+=4U; - hcryp->Instance->SUSP0R = *(uint32_t*)(ivaddr); + hcryp->Instance->SUSP7R = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->SUSP6R = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->SUSP5R = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->SUSP4R = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->SUSP3R = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->SUSP2R = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->SUSP1R = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->SUSP0R = *(uint32_t *)(ivaddr); } /** @@ -5366,37 +5375,37 @@ * as soon as the suspended processing has to be resumed. * @retval None */ -static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output, uint32_t KeySize) +static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output, uint32_t KeySize) { uint32_t keyaddr = (uint32_t)Output; switch (KeySize) { case CRYP_KEYSIZE_256B: - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 1U); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 2U); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 3U); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 4U); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 5U); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 6U); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 7U); + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 1U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 2U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 3U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 4U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 5U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 6U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 7U); break; case CRYP_KEYSIZE_128B: - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 1U); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 2U); - keyaddr+=4U; - *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 3U); + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 1U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 2U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 3U); break; default: break; @@ -5414,29 +5423,29 @@ * @note AES must be disabled when reconfiguring the Key registers. * @retval None */ -static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input, uint32_t KeySize) +static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t KeySize) { uint32_t keyaddr = (uint32_t)Input; if (KeySize == CRYP_KEYSIZE_256B) { - hcryp->Instance->KEYR7 = *(uint32_t*)(keyaddr); - keyaddr+=4U; - hcryp->Instance->KEYR6 = *(uint32_t*)(keyaddr); - keyaddr+=4U; - hcryp->Instance->KEYR5 = *(uint32_t*)(keyaddr); - keyaddr+=4U; - hcryp->Instance->KEYR4 = *(uint32_t*)(keyaddr); - keyaddr+=4U; + hcryp->Instance->KEYR7 = *(uint32_t *)(keyaddr); + keyaddr += 4U; + hcryp->Instance->KEYR6 = *(uint32_t *)(keyaddr); + keyaddr += 4U; + hcryp->Instance->KEYR5 = *(uint32_t *)(keyaddr); + keyaddr += 4U; + hcryp->Instance->KEYR4 = *(uint32_t *)(keyaddr); + keyaddr += 4U; } - hcryp->Instance->KEYR3 = *(uint32_t*)(keyaddr); - keyaddr+=4U; - hcryp->Instance->KEYR2 = *(uint32_t*)(keyaddr); - keyaddr+=4U; - hcryp->Instance->KEYR1 = *(uint32_t*)(keyaddr); - keyaddr+=4U; - hcryp->Instance->KEYR0 = *(uint32_t*)(keyaddr); + hcryp->Instance->KEYR3 = *(uint32_t *)(keyaddr); + keyaddr += 4U; + hcryp->Instance->KEYR2 = *(uint32_t *)(keyaddr); + keyaddr += 4U; + hcryp->Instance->KEYR1 = *(uint32_t *)(keyaddr); + keyaddr += 4U; + hcryp->Instance->KEYR0 = *(uint32_t *)(keyaddr); } /** @@ -5464,7 +5473,7 @@ /* Case of header phase resumption =================================================*/ if (hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) { - /* Set the phase */ + /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; /* Select header phase */ @@ -5473,24 +5482,24 @@ if ((((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)) { /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; } else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/ { /* Last block optionally pad the data with zeros*/ - for(loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize %4U ); loopcounter++) + for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++) { - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } - while(loopcounter <4U ) + while (loopcounter < 4U) { /* pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0x0U; @@ -5513,18 +5522,18 @@ /* Set to 0 the number of non-valid bytes using NPBLB register*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); - if (((hcryp->Size/4U) - (hcryp->CrypInCount)) >= 4U) + if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U) { /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) @@ -5539,32 +5548,32 @@ else /* Last block of payload < 128bit*/ { /* Compute the number of padding bytes in last block of payload */ - npblb = (((hcryp->Size/16U)+1U)*16U) - (hcryp->Size); + npblb = (((hcryp->Size / 16U) + 1U) * 16U) - (hcryp->Size); cr_temp = hcryp->Instance->CR; - if((((cr_temp & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) || - (((cr_temp& AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM))) + if ((((cr_temp & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) || + (((cr_temp & AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM))) { /* Specify the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, ((uint32_t)npblb)<< 20U); + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, ((uint32_t)npblb) << 20U); } /* Number of valid words (lastwordsize) in last block */ - if ((npblb % 4U) ==0U) + if ((npblb % 4U) == 0U) { - lastwordsize = (16U-npblb)/4U; + lastwordsize = (16U - npblb) / 4U; } else { - lastwordsize = ((16U-npblb)/4U) +1U; + lastwordsize = ((16U - npblb) / 4U) + 1U; } /* Last block optionally pad the data with zeros*/ - for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) + for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; } - while(loopcounter < 4U ) + while (loopcounter < 4U) { /* pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0x0U; @@ -5588,5 +5597,5 @@ */ /** - * @} - */ + * @} + */
diff --git a/Src/stm32wbxx_hal_cryp_ex.c b/Src/stm32wbxx_hal_cryp_ex.c index b41b478..16ec979 100644 --- a/Src/stm32wbxx_hal_cryp_ex.c +++ b/Src/stm32wbxx_hal_cryp_ex.c
@@ -71,8 +71,8 @@ */ /** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions - * @brief Extended processing functions. - * + * @brief Extended processing functions. + * @verbatim ============================================================================== ##### Extended AES processing functions ##### @@ -161,7 +161,7 @@ /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if (((HAL_GetTick() - tickstart) > Timeout)||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -267,7 +267,7 @@ /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if (((HAL_GetTick() - tickstart) > Timeout) ||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Disable the CRYP peripheral Clock */ __HAL_CRYP_DISABLE(hcryp);
diff --git a/Src/stm32wbxx_hal_i2c.c b/Src/stm32wbxx_hal_i2c.c index d7acf1c..e221553 100644 --- a/Src/stm32wbxx_hal_i2c.c +++ b/Src/stm32wbxx_hal_i2c.c
@@ -614,7 +614,12 @@ /* Configure I2Cx: Addressing Master mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { - hi2c->Instance->CR2 = (I2C_CR2_ADD10); + SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); + } + else + { + /* Clear the I2C ADD10 bit */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); } /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); @@ -1121,6 +1126,7 @@ uint16_t Size, uint32_t Timeout) { uint32_t tickstart; + uint32_t xfermode; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -1144,18 +1150,39 @@ hi2c->XferCount = Size; hi2c->XferISR = NULL; - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, - I2C_GENERATE_START_WRITE); + xfermode = I2C_RELOAD_MODE; } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode, + I2C_GENERATE_START_WRITE); + } + else + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); } @@ -1678,7 +1705,26 @@ /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + if (hi2c->XferSize > 0U) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode, + I2C_GENERATE_START_WRITE); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, + I2C_GENERATE_START_WRITE); + } /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1902,6 +1948,7 @@ { uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; + uint32_t sizetoxfer = 0U; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -1936,6 +1983,20 @@ if (hi2c->XferSize > 0U) { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + sizetoxfer = hi2c->XferSize; + hi2c->XferCount--; + hi2c->XferSize--; + } + + if (hi2c->XferSize > 0U) + { if (hi2c->hdmatx != NULL) { /* Set the I2C DMA transfer complete callback */ @@ -1949,8 +2010,8 @@ hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, - hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, + (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); } else { @@ -1971,7 +2032,8 @@ { /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), + xfermode, I2C_GENERATE_START_WRITE); /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; @@ -2010,7 +2072,7 @@ /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ @@ -2166,11 +2228,11 @@ /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); } return HAL_OK; @@ -2736,6 +2798,7 @@ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ + hi2c->XferSize = 0U; hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; @@ -2857,11 +2920,11 @@ to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT)); + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); return HAL_OK; } @@ -3323,6 +3386,7 @@ { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_WRITE; + uint32_t sizetoxfer = 0U; /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -3354,6 +3418,21 @@ xfermode = hi2c->XferOptions; } + if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \ + (XferOptions == I2C_FIRST_AND_LAST_FRAME))) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + sizetoxfer = hi2c->XferSize; + hi2c->XferCount--; + hi2c->XferSize--; + } + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ /* Mean Previous state is same as current state */ @@ -3375,7 +3454,14 @@ } /* Send Slave Address and set NBYTES to write */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)) + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + } /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3416,6 +3502,7 @@ uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_WRITE; HAL_StatusTypeDef dmaxferstatus; + uint32_t sizetoxfer = 0U; /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -3447,6 +3534,21 @@ xfermode = hi2c->XferOptions; } + if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \ + (XferOptions == I2C_FIRST_AND_LAST_FRAME))) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + sizetoxfer = hi2c->XferSize; + hi2c->XferCount--; + hi2c->XferSize--; + } + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ /* Mean Previous state is same as current state */ @@ -3482,8 +3584,8 @@ hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, - hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, + (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); } else { @@ -3503,7 +3605,14 @@ if (dmaxferstatus == HAL_OK) { /* Send Slave Address and set NBYTES to write */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)) + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + } /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; @@ -3542,8 +3651,14 @@ /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, - I2C_GENERATE_START_WRITE); + if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)) + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + } /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3808,11 +3923,11 @@ /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); } return HAL_OK; @@ -4864,17 +4979,22 @@ hi2c->XferSize--; hi2c->XferCount--; } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) == RESET) && \ + ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))) { /* Write data to TXDR */ - hi2c->Instance->TXDR = *hi2c->pBuffPtr; + if (hi2c->XferCount != 0U) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; - hi2c->XferSize--; - hi2c->XferCount--; + hi2c->XferSize--; + hi2c->XferCount--; + } } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) @@ -5061,6 +5181,12 @@ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { direction = I2C_GENERATE_START_READ; @@ -5428,6 +5554,9 @@ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + /* Enable only Error interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); @@ -5470,6 +5599,12 @@ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable only Error and NACK interrupt for data transfer */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { direction = I2C_GENERATE_START_READ; @@ -6157,7 +6292,8 @@ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Disable Interrupts and Store Previous state */ - if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || + (tmpstate == HAL_I2C_STATE_LISTEN)) { I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; @@ -7139,13 +7275,13 @@ if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) { - /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; } if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) { - /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } @@ -7173,13 +7309,13 @@ if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) { - /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; } if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) { - /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } @@ -7195,7 +7331,7 @@ tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); } - if ((hi2c->XferISR != I2C_Mem_ISR_DMA) && (InterruptRequest == I2C_XFER_RELOAD_IT)) + if (InterruptRequest == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI;
diff --git a/Src/stm32wbxx_hal_irda.c b/Src/stm32wbxx_hal_irda.c index a638cdf..bda4aaf 100644 --- a/Src/stm32wbxx_hal_irda.c +++ b/Src/stm32wbxx_hal_irda.c
@@ -142,7 +142,7 @@ [..] Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -159,10 +159,10 @@ [..] By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak functions: examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_IRDA_Init() + reset to the legacy weak functions in the HAL_IRDA_Init() and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -179,7 +179,7 @@ [..] When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim ****************************************************************************** @@ -462,7 +462,7 @@ #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) /** * @brief Register a User IRDA Callback - * To be used instead of the weak predefined callback + * To be used to override the weak predefined callback * @note The HAL_IRDA_RegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET * to register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID * @param hirda irda handle @@ -1292,7 +1292,7 @@ /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ if (hirda->Init.Parity != IRDA_PARITY_NONE) - { + { SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); } SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); @@ -2422,7 +2422,6 @@ hirda->gState = HAL_IRDA_STATE_READY; } - /** * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
diff --git a/Src/stm32wbxx_hal_lptim.c b/Src/stm32wbxx_hal_lptim.c index 2372f9f..28e14a8 100644 --- a/Src/stm32wbxx_hal_lptim.c +++ b/Src/stm32wbxx_hal_lptim.c
@@ -43,6 +43,9 @@ (++) Clock: the counter clock. (+++) Source : it can be either the ULPTIM input (IN1) or one of the internal clock; (APB, LSE, LSI or MSI). + CAUTION: if LSI2 is selected as LPTIM cock source, LSI1 has + to be enabled as well (for further information please + refer to errata sheet ES0394). (+++) Prescaler: select the clock divider. (++) UltraLowPowerClock : To be used only if the ULPTIM is selected as counter clock source. @@ -206,7 +209,7 @@ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim); #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ -static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag); +static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag); /* Exported functions --------------------------------------------------------*/ @@ -368,10 +371,10 @@ } else { - /* Check LPTIM2 Input1 source */ + /* Check LPTIM Input1 source */ assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source)); - /* Configure LPTIM2 Input1 source */ + /* Configure LPTIM Input1 source */ hlptim->Instance->OR = hlptim->Init.Input1Source; } #endif /* LPTIM_OR_OR */ @@ -2311,7 +2314,7 @@ * @param hlptim LPTIM handle * @retval HAL state */ -HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim) +HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim) { /* Return LPTIM handle state */ return hlptim->State; @@ -2358,7 +2361,7 @@ * @param flag The lptim flag * @retval HAL status */ -static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag) +static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag) { HAL_StatusTypeDef result = HAL_OK; uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);
diff --git a/Src/stm32wbxx_hal_pcd.c b/Src/stm32wbxx_hal_pcd.c index 8eba857..f247475 100644 --- a/Src/stm32wbxx_hal_pcd.c +++ b/Src/stm32wbxx_hal_pcd.c
@@ -1481,7 +1481,7 @@ * @param ep_addr endpoint address * @retval Data Size */ -uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr) { return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count; } @@ -1621,9 +1621,18 @@ */ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(ep_addr); + __HAL_LOCK(hpcd); + + if ((ep_addr & 0x80U) == 0x80U) + { + (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK); + } + else + { + (void)USB_FlushRxFifo(hpcd->Instance); + } + + __HAL_UNLOCK(hpcd); return HAL_OK; } @@ -1672,7 +1681,7 @@ * @param hpcd PCD handle * @retval HAL state */ -PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd) { return hpcd->State; }
diff --git a/Src/stm32wbxx_hal_qspi.c b/Src/stm32wbxx_hal_qspi.c index fdddf2d..58c87ae 100644 --- a/Src/stm32wbxx_hal_qspi.c +++ b/Src/stm32wbxx_hal_qspi.c
@@ -161,7 +161,7 @@ and a pointer to the user callback function. Use function HAL_QSPI_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) ErrorCallback : callback when error occurs. (+) AbortCpltCallback : callback when abort is completed. (+) FifoThresholdCallback : callback when the fifo threshold is reached. @@ -177,9 +177,9 @@ This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_QSPI_Init + reset to the legacy weak (overridden) functions in the HAL_QSPI_Init and HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_QSPI_Init and HAL_QSPI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -194,7 +194,7 @@ When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. *** Workarounds linked to Silicon Limitation *** ==================================================== @@ -1973,7 +1973,7 @@ #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) /** * @brief Register a User QSPI Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used to override the weak predefined callback * @param hqspi QSPI handle * @param CallbackId ID of the callback to be registered * This parameter can be one of the following values: @@ -2087,7 +2087,7 @@ /** * @brief Unregister a User QSPI Callback - * QSPI Callback is redirected to the weak (surcharged) predefined callback + * QSPI Callback is redirected to the weak predefined callback * @param hqspi QSPI handle * @param CallbackId ID of the callback to be unregistered * This parameter can be one of the following values: @@ -2264,25 +2264,33 @@ } } - /* Configure QSPI: CR register with Abort request */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); - - /* Wait until TC flag is set to go back in idle state */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); - - if (status == HAL_OK) + if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET) { - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + /* Configure QSPI: CR register with Abort request */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); + + /* Wait until TC flag is set to go back in idle state */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); + + if (status == HAL_OK) + { + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + + /* Wait until BUSY flag is reset */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); + } - /* Wait until BUSY flag is reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); + if (status == HAL_OK) + { + /* Reset functional mode configuration to indirect write mode by default */ + CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); + + /* Update state */ + hqspi->State = HAL_QSPI_STATE_READY; + } } - - if (status == HAL_OK) + else { - /* Reset functional mode configuration to indirect write mode by default */ - CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); - /* Update state */ hqspi->State = HAL_QSPI_STATE_READY; } @@ -2334,14 +2342,22 @@ } else { - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - - /* Enable the QSPI Transfer Complete Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); - - /* Configure QSPI: CR register with Abort request */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); + if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET) + { + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + + /* Enable the QSPI Transfer Complete Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); + + /* Configure QSPI: CR register with Abort request */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); + } + else + { + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; + } } } return status;
diff --git a/Src/stm32wbxx_hal_rng.c b/Src/stm32wbxx_hal_rng.c index 582a2f7..276f8fc 100644 --- a/Src/stm32wbxx_hal_rng.c +++ b/Src/stm32wbxx_hal_rng.c
@@ -52,7 +52,7 @@ [..] Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak (overridden) function. HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -66,10 +66,10 @@ [..] By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak (overridden) functions: example HAL_RNG_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_RNG_Init() + reset to the legacy weak (overridden) functions in the HAL_RNG_Init() and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -86,7 +86,7 @@ [..] When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -129,7 +129,7 @@ */ /** @addtogroup RNG_Exported_Functions_Group1 - * @brief Initialization and configuration functions + * @brief Initialization and configuration functions * @verbatim =============================================================================== @@ -301,7 +301,8 @@ * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, + pRNG_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -311,8 +312,6 @@ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hrng); if (HAL_RNG_STATE_READY == hrng->State) { @@ -366,8 +365,6 @@ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hrng); return status; } @@ -386,8 +383,6 @@ { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hrng); if (HAL_RNG_STATE_READY == hrng->State) { @@ -441,8 +436,6 @@ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hrng); return status; } @@ -520,7 +513,7 @@ */ /** @addtogroup RNG_Exported_Functions_Group2 - * @brief Peripheral Control functions + * @brief Peripheral Control functions * @verbatim =============================================================================== @@ -663,15 +656,16 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) { uint32_t rngclockerror = 0U; + uint32_t itflag = hrng->Instance->SR; /* RNG clock error interrupt occurred */ - if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) + if ((itflag & RNG_IT_CEI) == RNG_IT_CEI) { /* Update the error code */ hrng->ErrorCode = HAL_RNG_ERROR_CLOCK; rngclockerror = 1U; } - else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) + else if ((itflag & RNG_IT_SEI) == RNG_IT_SEI) { /* Update the error code */ hrng->ErrorCode = HAL_RNG_ERROR_SEED; @@ -697,10 +691,12 @@ /* Clear the clock error flag */ __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI | RNG_IT_SEI); + + return; } /* Check RNG data ready interrupt occurred */ - if (__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET) + if ((itflag & RNG_IT_DRDY) == RNG_IT_DRDY) { /* Generate random number once, so disable the IT */ __HAL_RNG_DISABLE_IT(hrng); @@ -732,7 +728,7 @@ * the configuration information for RNG. * @retval random value */ -uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng) +uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng) { return (hrng->RandomNumber); } @@ -779,7 +775,7 @@ /** @addtogroup RNG_Exported_Functions_Group3 - * @brief Peripheral State functions + * @brief Peripheral State functions * @verbatim =============================================================================== @@ -799,7 +795,7 @@ * the configuration information for RNG. * @retval HAL state */ -HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) +HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng) { return hrng->State; } @@ -809,7 +805,7 @@ * @param hrng: pointer to a RNG_HandleTypeDef structure. * @retval RNG Error Code */ -uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng) +uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng) { /* Return RNG Error Code */ return hrng->ErrorCode; @@ -833,3 +829,4 @@ /** * @} */ +
diff --git a/Src/stm32wbxx_hal_smartcard.c b/Src/stm32wbxx_hal_smartcard.c index 58b5e49..6f5cd70 100644 --- a/Src/stm32wbxx_hal_smartcard.c +++ b/Src/stm32wbxx_hal_smartcard.c
@@ -136,7 +136,7 @@ [..] Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -153,10 +153,10 @@ [..] By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak functions: examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init() + reset to the legacy weak functions in the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -173,7 +173,7 @@ [..] When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim @@ -467,7 +467,7 @@ #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) /** * @brief Register a User SMARTCARD Callback - * To be used instead of the weak predefined callback + * To be used to override the weak predefined callback * @note The HAL_SMARTCARD_RegisterCallback() may be called before HAL_SMARTCARD_Init() * in HAL_SMARTCARD_STATE_RESET to register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID * and HAL_SMARTCARD_MSPDEINIT_CB_ID
diff --git a/Src/stm32wbxx_hal_smartcard_ex.c b/Src/stm32wbxx_hal_smartcard_ex.c index 1351cb4..fad1756 100644 --- a/Src/stm32wbxx_hal_smartcard_ex.c +++ b/Src/stm32wbxx_hal_smartcard_ex.c
@@ -472,8 +472,10 @@ tx_fifo_depth = TX_FIFO_DEPTH; rx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); tx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); - hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; - hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; + hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / \ + (uint16_t)denominator[tx_fifo_threshold]; + hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / \ + (uint16_t)denominator[rx_fifo_threshold]; } }
diff --git a/Src/stm32wbxx_hal_smbus.c b/Src/stm32wbxx_hal_smbus.c index 2f4f9b7..bb0cfb1 100644 --- a/Src/stm32wbxx_hal_smbus.c +++ b/Src/stm32wbxx_hal_smbus.c
@@ -926,6 +926,7 @@ uint8_t *pData, uint16_t Size, uint32_t XferOptions) { uint32_t tmp; + uint32_t sizetoxfer = 0U; /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -958,11 +959,35 @@ hsmbus->XferSize = Size; } + sizetoxfer = hsmbus->XferSize; + if ((hsmbus->XferSize > 0U) && ((XferOptions == SMBUS_FIRST_FRAME) || + (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || + (XferOptions == SMBUS_FIRST_FRAME_WITH_PEC) || + (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC))) + { + if (hsmbus->pBuffPtr != NULL) + { + /* Preload TX register */ + /* Write data to TXDR */ + hsmbus->Instance->TXDR = *hsmbus->pBuffPtr; + + /* Increment Buffer pointer */ + hsmbus->pBuffPtr++; + + hsmbus->XferCount--; + hsmbus->XferSize--; + } + else + { + return HAL_ERROR; + } + } + /* Send Slave Address */ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) + if ((sizetoxfer < hsmbus->XferCount) && (sizetoxfer == MAX_NBYTE_SIZE)) { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)sizetoxfer, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); } @@ -977,7 +1002,7 @@ if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && \ (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)sizetoxfer, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ @@ -987,7 +1012,7 @@ SMBUS_ConvertOtherXferOptions(hsmbus); /* Handle Transfer */ - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)sizetoxfer, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE); } @@ -996,8 +1021,15 @@ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) { - hsmbus->XferSize--; - hsmbus->XferCount--; + if (hsmbus->XferSize > 0U) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + else + { + return HAL_ERROR; + } } }
diff --git a/Src/stm32wbxx_hal_spi.c b/Src/stm32wbxx_hal_spi.c index 51c9a90..ddec922 100644 --- a/Src/stm32wbxx_hal_spi.c +++ b/Src/stm32wbxx_hal_spi.c
@@ -908,6 +908,7 @@ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -957,6 +958,7 @@ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -986,9 +988,12 @@ { errorcode = HAL_ERROR; } + else + { + hspi->State = HAL_SPI_STATE_READY; + } error: - hspi->State = HAL_SPI_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspi); return errorcode; @@ -1013,6 +1018,12 @@ uint32_t tickstart; HAL_StatusTypeDef errorcode = HAL_OK; + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1026,12 +1037,6 @@ /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if (hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } - if ((pData == NULL) || (Size == 0U)) { errorcode = HAL_ERROR; @@ -1109,6 +1114,7 @@ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -1132,6 +1138,7 @@ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -1226,9 +1233,12 @@ { errorcode = HAL_ERROR; } + else + { + hspi->State = HAL_SPI_STATE_READY; + } error : - hspi->State = HAL_SPI_STATE_READY; __HAL_UNLOCK(hspi); return errorcode; } @@ -1349,6 +1359,20 @@ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ + if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); + } + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) { @@ -1387,6 +1411,7 @@ if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -1407,6 +1432,19 @@ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ + if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); + } + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ } } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) @@ -1469,6 +1507,7 @@ if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -1538,8 +1577,16 @@ hspi->ErrorCode = HAL_SPI_ERROR_FLAG; } + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + errorcode = HAL_ERROR; + } + else + { + hspi->State = HAL_SPI_STATE_READY; + } + error : - hspi->State = HAL_SPI_STATE_READY; __HAL_UNLOCK(hspi); return errorcode; } @@ -1559,8 +1606,6 @@ /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); if ((pData == NULL) || (Size == 0U)) { @@ -1574,6 +1619,9 @@ goto error; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1613,10 +1661,6 @@ } #endif /* USE_SPI_CRC */ - /* Enable TXE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); - - /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { @@ -1624,8 +1668,12 @@ __HAL_SPI_ENABLE(hspi); } -error : + /* Process Unlocked */ __HAL_UNLOCK(hspi); + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + +error : return errorcode; } @@ -1641,15 +1689,6 @@ { HAL_StatusTypeDef errorcode = HAL_OK; - if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) - { - hspi->State = HAL_SPI_STATE_BUSY_RX; - /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ - return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); - } - - /* Process Locked */ - __HAL_LOCK(hspi); if (hspi->State != HAL_SPI_STATE_READY) { @@ -1657,12 +1696,23 @@ goto error; } + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + hspi->State = HAL_SPI_STATE_BUSY_RX; + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); + } + + if ((pData == NULL) || (Size == 0U)) { errorcode = HAL_ERROR; goto error; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1715,9 +1765,6 @@ } #endif /* USE_SPI_CRC */ - /* Enable TXE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - /* Note : The SPI must be enabled after unlocking current process to avoid the risk of SPI interrupt handle execution before current process unlock */ @@ -1729,9 +1776,12 @@ __HAL_SPI_ENABLE(hspi); } -error : /* Process Unlocked */ __HAL_UNLOCK(hspi); + /* Enable RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + +error : return errorcode; } @@ -1753,9 +1803,6 @@ /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process locked */ - __HAL_LOCK(hspi); - /* Init temporary variables */ tmp_state = hspi->State; tmp_mode = hspi->Init.Mode; @@ -1773,6 +1820,9 @@ goto error; } + /* Process locked */ + __HAL_LOCK(hspi); + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) { @@ -1829,8 +1879,6 @@ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } - /* Enable TXE, RXNE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) @@ -1839,9 +1887,12 @@ __HAL_SPI_ENABLE(hspi); } -error : /* Process Unlocked */ __HAL_UNLOCK(hspi); + /* Enable TXE, RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + +error : return errorcode; } @@ -1945,7 +1996,6 @@ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); errorcode = HAL_ERROR; - hspi->State = HAL_SPI_STATE_READY; goto error; } @@ -1985,6 +2035,12 @@ /* Check rx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1999,12 +2055,6 @@ /* Process Locked */ __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } - if ((pData == NULL) || (Size == 0U)) { errorcode = HAL_ERROR; @@ -2090,7 +2140,6 @@ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); errorcode = HAL_ERROR; - hspi->State = HAL_SPI_STATE_READY; goto error; } @@ -2258,7 +2307,6 @@ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); errorcode = HAL_ERROR; - hspi->State = HAL_SPI_STATE_READY; goto error; } @@ -2280,7 +2328,6 @@ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); errorcode = HAL_ERROR; - hspi->State = HAL_SPI_STATE_READY; goto error; }
diff --git a/Src/stm32wbxx_hal_tim.c b/Src/stm32wbxx_hal_tim.c index 3309aa9..ddbb0cb 100644 --- a/Src/stm32wbxx_hal_tim.c +++ b/Src/stm32wbxx_hal_tim.c
@@ -896,7 +896,7 @@ uint32_t tmpsmcr; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) @@ -988,7 +988,7 @@ HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); switch (Channel) { @@ -1067,7 +1067,7 @@ uint32_t tmpsmcr; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Set the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) @@ -1229,7 +1229,7 @@ HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); switch (Channel) { @@ -1565,7 +1565,7 @@ uint32_t tmpsmcr; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) @@ -1657,7 +1657,7 @@ HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); switch (Channel) { @@ -1736,7 +1736,7 @@ uint32_t tmpsmcr; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Set the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) @@ -1897,7 +1897,7 @@ HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); switch (Channel) { @@ -2141,7 +2141,7 @@ HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Check the TIM channel state */ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) @@ -2189,7 +2189,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Disable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); @@ -2225,7 +2225,7 @@ HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Check the TIM channel state */ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) @@ -2313,7 +2313,7 @@ HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); switch (Channel) { @@ -2389,7 +2389,7 @@ HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); /* Set the TIM channel state */ @@ -2544,7 +2544,7 @@ HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); /* Disable the Input Capture channel */ @@ -3035,7 +3035,7 @@ * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) { uint32_t tmpsmcr; uint32_t tmpccmr1; @@ -3841,10 +3841,13 @@ */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { + uint32_t itsource = htim->Instance->DIER; + uint32_t itflag = htim->Instance->SR; + /* Capture compare 1 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) + if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) { { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); @@ -3875,9 +3878,9 @@ } } /* Capture compare 2 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) + if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; @@ -3905,9 +3908,9 @@ } } /* Capture compare 3 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) + if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; @@ -3935,9 +3938,9 @@ } } /* Capture compare 4 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) + if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; @@ -3965,9 +3968,9 @@ } } /* TIM Update event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) + if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) @@ -3978,9 +3981,9 @@ } } /* TIM Break input event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) @@ -3991,9 +3994,9 @@ } } /* TIM Break2 input event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) + if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) @@ -4004,9 +4007,9 @@ } } /* TIM Trigger detection event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) + if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) @@ -4017,9 +4020,9 @@ } } /* TIM commutation event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) + if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) @@ -6999,11 +7002,12 @@ uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -7074,11 +7078,12 @@ uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -7150,11 +7155,12 @@ uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -7224,11 +7230,12 @@ uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -7285,11 +7292,12 @@ uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC5E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ @@ -7338,11 +7346,12 @@ uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC6E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ @@ -7526,9 +7535,9 @@ uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC1E; tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; /* Select the Input */ if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) @@ -7616,9 +7625,9 @@ uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr1 &= ~TIM_CCMR1_CC2S; @@ -7655,9 +7664,9 @@ uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; @@ -7699,9 +7708,9 @@ uint32_t tmpccer; /* Disable the Channel 3: Reset the CC3E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC3E; tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC3S; @@ -7747,9 +7756,9 @@ uint32_t tmpccer; /* Disable the Channel 4: Reset the CC4E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC4E; tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC4S;
diff --git a/Src/stm32wbxx_hal_tim_ex.c b/Src/stm32wbxx_hal_tim_ex.c index 3f6dcd6..5e90810 100644 --- a/Src/stm32wbxx_hal_tim_ex.c +++ b/Src/stm32wbxx_hal_tim_ex.c
@@ -2463,7 +2463,7 @@ * @note Break input is automatically armed as soon as MOE bit is set. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput) +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput) { HAL_StatusTypeDef status = HAL_OK; uint32_t tickstart; @@ -2820,13 +2820,13 @@ { uint32_t tmp; - tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */ /* Reset the CCxNE Bit */ TIMx->CCER &= ~tmp; /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */ } /** * @}
diff --git a/Src/stm32wbxx_hal_timebase_rtc_alarm_template.c b/Src/stm32wbxx_hal_timebase_rtc_alarm_template.c index bf0f90f..aa7f2ec 100644 --- a/Src/stm32wbxx_hal_timebase_rtc_alarm_template.c +++ b/Src/stm32wbxx_hal_timebase_rtc_alarm_template.c
@@ -158,19 +158,19 @@ else { #ifdef RTC_CLOCK_SOURCE_LSE - /* Configue LSE as RTC clock source */ + /* Configure LSE as RTC clock source */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; RCC_OscInitStruct.LSEState = RCC_LSE_ON; PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; #elif defined (RTC_CLOCK_SOURCE_LSI) - /* Configue LSI as RTC clock source */ + /* Configure LSI as RTC clock source */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; RCC_OscInitStruct.LSIState = RCC_LSI_ON; PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; #elif defined (RTC_CLOCK_SOURCE_HSE) - /* Configue HSE as RTC clock source */ + /* Configure HSE as RTC clock source */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; RCC_OscInitStruct.HSEState = RCC_HSE_ON;
diff --git a/Src/stm32wbxx_hal_timebase_rtc_wakeup_template.c b/Src/stm32wbxx_hal_timebase_rtc_wakeup_template.c index 5865e3a..fcda1d3 100644 --- a/Src/stm32wbxx_hal_timebase_rtc_wakeup_template.c +++ b/Src/stm32wbxx_hal_timebase_rtc_wakeup_template.c
@@ -153,19 +153,19 @@ else { #ifdef RTC_CLOCK_SOURCE_LSE - /* Configue LSE as RTC clock source */ + /* Configure LSE as RTC clock source */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; RCC_OscInitStruct.LSEState = RCC_LSE_ON; PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; #elif defined (RTC_CLOCK_SOURCE_LSI) - /* Configue LSI as RTC clock source */ + /* Configure LSI as RTC clock source */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; RCC_OscInitStruct.LSIState = RCC_LSI_ON; PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; #elif defined (RTC_CLOCK_SOURCE_HSE) - /* Configue HSE as RTC clock source */ + /* Configure HSE as RTC clock source */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; RCC_OscInitStruct.HSEState = RCC_HSE_ON;
diff --git a/Src/stm32wbxx_hal_uart.c b/Src/stm32wbxx_hal_uart.c index 23c7ce0..57cd74c 100644 --- a/Src/stm32wbxx_hal_uart.c +++ b/Src/stm32wbxx_hal_uart.c
@@ -107,7 +107,7 @@ [..] Use function HAL_UART_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -131,10 +131,10 @@ [..] By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak functions: examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_UART_Init() + reset to the legacy weak functions in the HAL_UART_Init() and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -151,7 +151,7 @@ [..] When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim @@ -199,8 +199,8 @@ /** @addtogroup UART_Private_Functions * @{ */ -static void UART_EndTxTransfer(UART_HandleTypeDef *huart); static void UART_EndRxTransfer(UART_HandleTypeDef *huart); +static void UART_EndTxTransfer(UART_HandleTypeDef *huart); static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); @@ -354,17 +354,19 @@ __HAL_UART_DISABLE(huart); + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ @@ -419,17 +421,19 @@ __HAL_UART_DISABLE(huart); + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - /* In half-duplex mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN and IREN bits in the USART_CR3 register.*/ @@ -505,17 +509,19 @@ __HAL_UART_DISABLE(huart); + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - /* In LIN mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN and IREN bits in the USART_CR3 register.*/ @@ -589,17 +595,19 @@ __HAL_UART_DISABLE(huart); + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - /* In multiprocessor mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ @@ -706,7 +714,7 @@ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /** * @brief Register a User UART Callback - * To be used instead of the weak predefined callback + * To be used to override the weak predefined callback * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID @@ -3316,6 +3324,13 @@ /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + } + /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) { @@ -3337,13 +3352,6 @@ MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); } - /* if required, configure RX/TX pins swap */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) - { - assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); - } - /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) { @@ -3473,20 +3481,20 @@ { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) { - /* Clear Overrun Error flag*/ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + /* Clear Overrun Error flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - /* Blocking error : transfer is aborted - Set the UART state ready to be able to start again the process, - Disable Rx Interrupts if ongoing */ - UART_EndRxTransfer(huart); + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); - huart->ErrorCode = HAL_UART_ERROR_ORE; + huart->ErrorCode = HAL_UART_ERROR_ORE; - /* Process Unlocked */ - __HAL_UNLOCK(huart); + /* Process Unlocked */ + __HAL_UNLOCK(huart); - return HAL_ERROR; + return HAL_ERROR; } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) {
diff --git a/Src/stm32wbxx_hal_uart_ex.c b/Src/stm32wbxx_hal_uart_ex.c index 020bc8f..12740d6 100644 --- a/Src/stm32wbxx_hal_uart_ex.c +++ b/Src/stm32wbxx_hal_uart_ex.c
@@ -211,17 +211,19 @@ /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_DEM); @@ -688,30 +690,28 @@ } /** - * @brief Receive an amount of data in blocking mode till either the expected number of data is received or an IDLE event occurs. - * @note HAL_OK is returned if reception is completed (expected number of data has been received) - * or if reception is stopped after IDLE event (less than the expected number of data has been received) - * In this case, RxLen output parameter indicates number of data available in reception buffer. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of uint16_t. In this case, Size must indicate the number - * of uint16_t available through pData. + * @brief Receive an amount of data in blocking mode till either the expected number of data + * is received or an IDLE event occurs. + * @note HAL_OK is returned if reception is completed (expected number of data has been received) + * or if reception is stopped after IDLE event (less than the expected number of data has been received) + * In this case, RxLen output parameter indicates number of data available in reception buffer. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO * is not empty. Read operations from the RDR register are performed when * RXFNE flag is set. From hardware perspective, RXFNE flag and * RXNE are mapped on the same bit-field. - * @note Dual core specific: there is no support for unaligned accesses on the Cortex-M0+ processor. - * When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) - * (as received data will be handled using uint16_t pointer cast). Depending on compilation chain, - * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. * @param huart UART handle. * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. - * @param RxLen Number of data elements finally received (could be lower than Size, in case reception ends on IDLE event) + * @param RxLen Number of data elements finally received + * (could be lower than Size, in case reception ends on IDLE event) * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence). * @retval HAL status */ -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout) +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout) { uint8_t *pdata8bits; uint16_t *pdata16bits; @@ -820,18 +820,14 @@ } /** - * @brief Receive an amount of data in interrupt mode till either the expected number of data is received or an IDLE event occurs. - * @note Reception is initiated by this function call. Further progress of reception is achieved thanks - * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating - * number of received data elements. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of uint16_t. In this case, Size must indicate the number - * of uint16_t available through pData. - * @note Dual core specific: there is no support for unaligned accesses on the Cortex-M0+ processor. - * When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) - * (as received data will be handled using uint16_t pointer cast). Depending on compilation chain, - * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. + * @brief Receive an amount of data in interrupt mode till either the expected number of data + * is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating + * number of received data elements. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. * @param huart UART handle. * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. @@ -839,7 +835,7 @@ */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef status; + HAL_StatusTypeDef status = HAL_OK; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) @@ -853,24 +849,20 @@ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; huart->RxEventType = HAL_UART_RXEVENT_TC; - status = UART_Start_Receive_IT(huart, pData, Size); + (void)UART_Start_Receive_IT(huart, pData, Size); - /* Check Rx process has been successfully started */ - if (status == HAL_OK) + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - } - else - { - /* In case of errors already pending when reception is started, - Interrupts may have already been raised and lead to reception abortion. - (Overrun error for instance). - In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ - status = HAL_ERROR; - } + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; } return status; @@ -882,21 +874,17 @@ } /** - * @brief Receive an amount of data in DMA mode till either the expected number of data is received or an IDLE event occurs. - * @note Reception is initiated by this function call. Further progress of reception is achieved thanks - * to DMA services, transferring automatically received data elements in user reception buffer and - * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider - * reception phase as ended. In all cases, callback execution will indicate number of received data elements. - * @note When the UART parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position). - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of uint16_t. In this case, Size must indicate the number - * of uint16_t available through pData. - * @note Dual core specific: there is no support for unaligned accesses on the Cortex-M0+ processor. - * When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) - * (as received data will be handled by DMA from halfword frontier). Depending on compilation chain, - * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. + * @brief Receive an amount of data in DMA mode till either the expected number + * of data is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to DMA services, transferring automatically received data elements in user reception buffer and + * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider + * reception phase as ended. In all cases, callback execution will indicate number of received data elements. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. * @param huart UART handle. * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. @@ -970,7 +958,7 @@ * @param huart UART handle. * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values) */ -HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart) +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart) { /* Return Rx Event type value, as stored in UART handle */ return (huart->RxEventType);
diff --git a/Src/stm32wbxx_hal_usart.c b/Src/stm32wbxx_hal_usart.c index 1133d89..0c371f7 100644 --- a/Src/stm32wbxx_hal_usart.c +++ b/Src/stm32wbxx_hal_usart.c
@@ -91,7 +91,7 @@ [..] Use function HAL_USART_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -109,10 +109,10 @@ [..] By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak functions: examples HAL_USART_TxCpltCallback(), HAL_USART_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_USART_Init() + reset to the legacy weak functions in the HAL_USART_Init() and HAL_USART_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_USART_Init() and HAL_USART_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -129,7 +129,7 @@ [..] When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim @@ -404,7 +404,7 @@ #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) /** * @brief Register a User USART Callback - * To be used instead of the weak predefined callback + * To be used to override the weak predefined callback * @note The HAL_USART_RegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET * to register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID * @param husart usart handle @@ -1850,9 +1850,6 @@ /* Set error code to DMA */ husart->ErrorCode = HAL_USART_ERROR_DMA; - /* Process Unlocked */ - __HAL_UNLOCK(husart); - return HAL_TIMEOUT; } } @@ -1867,9 +1864,6 @@ /* Set error code to DMA */ husart->ErrorCode = HAL_USART_ERROR_DMA; - /* Process Unlocked */ - __HAL_UNLOCK(husart); - return HAL_TIMEOUT; } } @@ -1919,9 +1913,6 @@ /* Set error code to DMA */ husart->ErrorCode = HAL_USART_ERROR_DMA; - /* Process Unlocked */ - __HAL_UNLOCK(husart); - return HAL_TIMEOUT; } } @@ -1947,9 +1938,6 @@ /* Set error code to DMA */ husart->ErrorCode = HAL_USART_ERROR_DMA; - /* Process Unlocked */ - __HAL_UNLOCK(husart); - return HAL_TIMEOUT; } } @@ -2136,7 +2124,7 @@ uint32_t errorcode; /* If no error occurs */ - errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_UDR)); + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF | USART_ISR_UDR)); if (errorflags == 0U) { /* USART in mode Receiver ---------------------------------------------------*/ @@ -2191,6 +2179,14 @@ husart->ErrorCode |= HAL_USART_ERROR_ORE; } + /* USART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(husart, UART_CLEAR_RTOF); + + husart->ErrorCode |= HAL_USART_ERROR_RTO; + } + /* USART SPI slave underrun error interrupt occurred -------------------------*/ if (((isrflags & USART_ISR_UDR) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) { @@ -3248,6 +3244,7 @@ const HAL_USART_StateTypeDef state = husart->State; uint16_t txdatacount; uint16_t uhMask = husart->Mask; + uint32_t txftie; if ((state == HAL_USART_STATE_BUSY_RX) || (state == HAL_USART_STATE_BUSY_TX_RX)) @@ -3267,7 +3264,8 @@ /* Clear RxISR function pointer */ husart->RxISR = NULL; - /* txdatacount is a temporary variable for MISRAC2012-Rule-13.5 */ + /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */ + txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE); txdatacount = husart->TxXferCount; if (state == HAL_USART_STATE_BUSY_RX) @@ -3291,6 +3289,7 @@ #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txftie != USART_CR3_TXFTIE) && (txdatacount == 0U)) { /* TxRx process is completed, restore husart->State to Ready */ @@ -3337,6 +3336,7 @@ uint16_t txdatacount; uint16_t *tmp; uint16_t uhMask = husart->Mask; + uint32_t txftie; if ((state == HAL_USART_STATE_BUSY_RX) || (state == HAL_USART_STATE_BUSY_TX_RX)) @@ -3357,7 +3357,8 @@ /* Clear RxISR function pointer */ husart->RxISR = NULL; - /* txdatacount is a temporary variable for MISRAC2012-Rule-13.5 */ + /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */ + txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE); txdatacount = husart->TxXferCount; if (state == HAL_USART_STATE_BUSY_RX) @@ -3381,6 +3382,7 @@ #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txftie != USART_CR3_TXFTIE) && (txdatacount == 0U)) { /* TxRx process is completed, restore husart->State to Ready */ @@ -3428,6 +3430,7 @@ uint16_t rxdatacount; uint16_t uhMask = husart->Mask; uint16_t nb_rx_data; + uint32_t txftie; /* Check that a Rx process is ongoing */ if ((state == HAL_USART_STATE_BUSY_RX) || @@ -3453,7 +3456,8 @@ /* Clear RxISR function pointer */ husart->RxISR = NULL; - /* txdatacount is a temporary variable for MISRAC2012-Rule-13.5 */ + /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */ + txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE); txdatacount = husart->TxXferCount; if (state == HAL_USART_STATE_BUSY_RX) @@ -3478,6 +3482,7 @@ #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txftie != USART_CR3_TXFTIE) && (txdatacount == 0U)) { /* TxRx process is completed, restore husart->State to Ready */ @@ -3559,6 +3564,7 @@ uint16_t *tmp; uint16_t uhMask = husart->Mask; uint16_t nb_rx_data; + uint32_t txftie; /* Check that a Tx process is ongoing */ if ((state == HAL_USART_STATE_BUSY_RX) || @@ -3585,7 +3591,8 @@ /* Clear RxISR function pointer */ husart->RxISR = NULL; - /* txdatacount is a temporary variable for MISRAC2012-Rule-13.5 */ + /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */ + txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE); txdatacount = husart->TxXferCount; if (state == HAL_USART_STATE_BUSY_RX) @@ -3610,6 +3617,7 @@ #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txftie != USART_CR3_TXFTIE) && (txdatacount == 0U)) { /* TxRx process is completed, restore husart->State to Ready */
diff --git a/Src/stm32wbxx_ll_comp.c b/Src/stm32wbxx_ll_comp.c index dc16d54..85961c1 100644 --- a/Src/stm32wbxx_ll_comp.c +++ b/Src/stm32wbxx_ll_comp.c
@@ -15,6 +15,7 @@ * ****************************************************************************** */ + #if defined(USE_FULL_LL_DRIVER) /* Includes ------------------------------------------------------------------*/ @@ -49,7 +50,7 @@ /* COMP instance. */ #define IS_LL_COMP_POWER_MODE(__POWER_MODE__) \ - ( ((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED) \ + (((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED) \ || ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED) \ || ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER) \ ) @@ -60,13 +61,13 @@ /* compatibility with other STM32 families. */ #if defined(LL_COMP_INPUT_PLUS_IO1) #define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \ - ( ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \ + (((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2) \ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO3) \ ) #else #define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \ - ( ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2) \ + (((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2) \ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO3) \ ) #endif @@ -77,7 +78,7 @@ /* compatibility with other STM32 families. */ #if defined(LL_COMP_INPUT_MINUS_IO2) #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ - ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \ + (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \ @@ -89,7 +90,7 @@ ) #else #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ - ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \ + (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \ @@ -101,19 +102,19 @@ #endif #define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__) \ - ( ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE) \ + (((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE) \ || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_LOW) \ || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_MEDIUM) \ || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_HIGH) \ ) #define IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__) \ - ( ((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED) \ + (((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED) \ || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED) \ ) #define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__OUTPUT_BLANKING_SOURCE__) \ - ( ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) \ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5) \ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3) \ )
diff --git a/Src/stm32wbxx_ll_crc.c b/Src/stm32wbxx_ll_crc.c index 51ac55c..ca8e87a 100644 --- a/Src/stm32wbxx_ll_crc.c +++ b/Src/stm32wbxx_ll_crc.c
@@ -59,7 +59,7 @@ * - SUCCESS: CRC registers are de-initialized * - ERROR: CRC registers are not de-initialized */ -ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx) +ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx) { ErrorStatus status = SUCCESS;
diff --git a/Src/stm32wbxx_ll_lptim.c b/Src/stm32wbxx_ll_lptim.c index d7003f5..4318ad9 100644 --- a/Src/stm32wbxx_ll_lptim.c +++ b/Src/stm32wbxx_ll_lptim.c
@@ -92,7 +92,7 @@ * - SUCCESS: LPTIMx registers are de-initialized * - ERROR: invalid LPTIMx instance */ -ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx) +ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx) { ErrorStatus result = SUCCESS;
diff --git a/Src/stm32wbxx_ll_lpuart.c b/Src/stm32wbxx_ll_lpuart.c index 7512fbd..f51da58 100644 --- a/Src/stm32wbxx_ll_lpuart.c +++ b/Src/stm32wbxx_ll_lpuart.c
@@ -44,6 +44,9 @@ * @{ */ +/* Definition of default baudrate value used for LPUART initialisation */ +#define LPUART_DEFAULT_BAUDRATE (9600U) + /** * @} */ @@ -253,7 +256,7 @@ { /* Set LPUART_InitStruct fields to default values */ LPUART_InitStruct->PrescalerValue = LL_LPUART_PRESCALER_DIV1; - LPUART_InitStruct->BaudRate = 9600U; + LPUART_InitStruct->BaudRate = LPUART_DEFAULT_BAUDRATE; LPUART_InitStruct->DataWidth = LL_LPUART_DATAWIDTH_8B; LPUART_InitStruct->StopBits = LL_LPUART_STOPBITS_1; LPUART_InitStruct->Parity = LL_LPUART_PARITY_NONE ; @@ -273,7 +276,7 @@ * @} */ -#endif /* defined (LPUART1) */ +#endif /* LPUART1 */ /** * @}
diff --git a/Src/stm32wbxx_ll_rng.c b/Src/stm32wbxx_ll_rng.c index 463d4e8..3d6dab3 100644 --- a/Src/stm32wbxx_ll_rng.c +++ b/Src/stm32wbxx_ll_rng.c
@@ -25,7 +25,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32WBxx_LL_Driver * @{ @@ -68,16 +68,26 @@ * - SUCCESS: RNG registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx) +ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx) { + ErrorStatus status = SUCCESS; + /* Check the parameters */ assert_param(IS_RNG_ALL_INSTANCE(RNGx)); - /* Enable RNG reset state */ - LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_RNG); + if (RNGx == RNG) + { + /* Enable RNG reset state */ + LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_RNG); - /* Release RNG from reset state */ - LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_RNG); - return (SUCCESS); + /* Release RNG from reset state */ + LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_RNG); + } + else + { + status = ERROR; + } + + return status; } /**
diff --git a/Src/stm32wbxx_ll_tim.c b/Src/stm32wbxx_ll_tim.c index bd7713c..e59f9c2 100644 --- a/Src/stm32wbxx_ll_tim.c +++ b/Src/stm32wbxx_ll_tim.c
@@ -219,7 +219,7 @@ * - SUCCESS: TIMx registers are de-initialized * - ERROR: invalid TIMx instance */ -ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) +ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx) { ErrorStatus result = SUCCESS; @@ -710,7 +710,6 @@ MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); - MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
diff --git a/Src/stm32wbxx_ll_usart.c b/Src/stm32wbxx_ll_usart.c index 1f8b816..f99e5db 100644 --- a/Src/stm32wbxx_ll_usart.c +++ b/Src/stm32wbxx_ll_usart.c
@@ -21,11 +21,11 @@ #include "stm32wbxx_ll_usart.h" #include "stm32wbxx_ll_rcc.h" #include "stm32wbxx_ll_bus.h" -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32WBxx_LL_Driver * @{ @@ -44,28 +44,30 @@ * @{ */ +/* Definition of default baudrate value used for USART initialisation */ +#define USART_DEFAULT_BAUDRATE (9600U) + /** * @} */ - /* Private macros ------------------------------------------------------------*/ /** @addtogroup USART_LL_Private_Macros * @{ */ #define IS_LL_USART_PRESCALER(__VALUE__) (((__VALUE__) == LL_USART_PRESCALER_DIV1) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV256)) + || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV256)) /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available * divided by the smallest oversampling used on the USART (i.e. 8) */ @@ -75,42 +77,42 @@ #define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U) #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ - || ((__VALUE__) == LL_USART_DIRECTION_RX) \ - || ((__VALUE__) == LL_USART_DIRECTION_TX) \ - || ((__VALUE__) == LL_USART_DIRECTION_TX_RX)) + || ((__VALUE__) == LL_USART_DIRECTION_RX) \ + || ((__VALUE__) == LL_USART_DIRECTION_TX) \ + || ((__VALUE__) == LL_USART_DIRECTION_TX_RX)) #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \ - || ((__VALUE__) == LL_USART_PARITY_EVEN) \ - || ((__VALUE__) == LL_USART_PARITY_ODD)) + || ((__VALUE__) == LL_USART_PARITY_EVEN) \ + || ((__VALUE__) == LL_USART_PARITY_ODD)) #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \ - || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \ - || ((__VALUE__) == LL_USART_DATAWIDTH_9B)) + || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \ + || ((__VALUE__) == LL_USART_DATAWIDTH_9B)) #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \ - || ((__VALUE__) == LL_USART_OVERSAMPLING_8)) + || ((__VALUE__) == LL_USART_OVERSAMPLING_8)) #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \ - || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT)) + || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT)) #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \ - || ((__VALUE__) == LL_USART_PHASE_2EDGE)) + || ((__VALUE__) == LL_USART_PHASE_2EDGE)) #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \ - || ((__VALUE__) == LL_USART_POLARITY_HIGH)) + || ((__VALUE__) == LL_USART_POLARITY_HIGH)) #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \ - || ((__VALUE__) == LL_USART_CLOCK_ENABLE)) + || ((__VALUE__) == LL_USART_CLOCK_ENABLE)) #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \ - || ((__VALUE__) == LL_USART_STOPBITS_1) \ - || ((__VALUE__) == LL_USART_STOPBITS_1_5) \ - || ((__VALUE__) == LL_USART_STOPBITS_2)) + || ((__VALUE__) == LL_USART_STOPBITS_1) \ + || ((__VALUE__) == LL_USART_STOPBITS_1_5) \ + || ((__VALUE__) == LL_USART_STOPBITS_2)) #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \ - || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \ - || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \ - || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS)) + || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \ + || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \ + || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS)) /** * @} @@ -160,8 +162,9 @@ /** * @brief Initialize USART registers according to the specified * parameters in USART_InitStruct. - * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), - * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @note As some bits in USART configuration registers can only be written when + * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling + * this function. Otherwise, ERROR result will be returned. * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0). * @param USARTx USART Instance * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure @@ -212,7 +215,8 @@ /*---------------------------- USART CR3 Configuration --------------------- * Configure USARTx CR3 (Hardware Flow Control) with parameters: - * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value. + * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to + * USART_InitStruct->HardwareFlowControl value. */ LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl); @@ -269,7 +273,7 @@ { /* Set USART_InitStruct fields to default values */ USART_InitStruct->PrescalerValue = LL_USART_PRESCALER_DIV1; - USART_InitStruct->BaudRate = 9600U; + USART_InitStruct->BaudRate = USART_DEFAULT_BAUDRATE; USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B; USART_InitStruct->StopBits = LL_USART_STOPBITS_1; USART_InitStruct->Parity = LL_USART_PARITY_NONE ; @@ -281,13 +285,15 @@ /** * @brief Initialize USART Clock related settings according to the * specified parameters in the USART_ClockInitStruct. - * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), - * USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @note As some bits in USART configuration registers can only be written when + * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling + * this function. Otherwise, ERROR result will be returned. * @param USARTx USART Instance * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure * that contains the Clock configuration information for the specified USART peripheral. * @retval An ErrorStatus enumeration value: - * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content + * - SUCCESS: USART registers related to Clock settings are initialized according + * to USART_ClockInitStruct content * - ERROR: Problem occurred during USART Registers initialization */ ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct) @@ -341,9 +347,12 @@ { /* Set LL_USART_ClockInitStruct fields with default values */ USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE; - USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ - USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ - USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ + USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = + LL_USART_CLOCK_DISABLE */ + USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = + LL_USART_CLOCK_DISABLE */ + USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = + LL_USART_CLOCK_DISABLE */ } /**
diff --git a/Src/stm32wbxx_ll_usb.c b/Src/stm32wbxx_ll_usb.c index 1cd629c..f3a23b9 100644 --- a/Src/stm32wbxx_ll_usb.c +++ b/Src/stm32wbxx_ll_usb.c
@@ -172,6 +172,47 @@ return HAL_OK; } +/** + * @brief USB_FlushTxFifo : Flush a Tx FIFO + * @param USBx : Selected device + * @param num : FIFO number + * This parameter can be a value from 1 to 15 + 15 means Flush all Tx FIFOs + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef const *USBx, uint32_t num) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(num); + + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + + return HAL_OK; +} + +/** + * @brief USB_FlushRxFifo : Flush Rx FIFO + * @param USBx : Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef const *USBx) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + + return HAL_OK; +} + + #if defined (HAL_PCD_MODULE_ENABLED) /** * @brief Activate and configure an endpoint @@ -751,7 +792,7 @@ * @param USBx Selected device * @retval USB Global Interrupt status */ -uint32_t USB_ReadInterrupts(USB_TypeDef *USBx) +uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx) { uint32_t tmpreg; @@ -791,7 +832,7 @@ * @param wNBytes no. of bytes to be copied. * @retval None */ -void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { uint32_t n = ((uint32_t)wNBytes + 1U) >> 1; uint32_t BaseAddr = (uint32_t)USBx; @@ -826,7 +867,7 @@ * @param wNBytes no. of bytes to be copied. * @retval None */ -void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { uint32_t n = (uint32_t)wNBytes >> 1; uint32_t BaseAddr = (uint32_t)USBx;