Release v1.2.0
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h index fecbdf4..e643dfd 100644 --- a/Inc/Legacy/stm32_hal_legacy.h +++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * <h2><center>© Copyright (c) 2018 STMicroelectronics. + * <h2><center>© Copyright (c) 2019 STMicroelectronics. * All rights reserved.</center></h2> * * This software component is licensed by ST under BSD 3-Clause license, @@ -623,6 +623,118 @@ #define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable #define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset #endif /* STM32G4 */ + +#if defined(STM32H7) +#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 + +#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 +#endif /* STM32H7 */ /** * @} */ @@ -1297,7 +1409,7 @@ #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT @@ -1397,7 +1509,7 @@ #define HAL_TIM_DMAError TIM_DMAError #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt -#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4) #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback @@ -3130,7 +3242,7 @@ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32G4) +#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined STM32G4 #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3246,7 +3358,7 @@ #define SDIO_IRQHandler SDMMC1_IRQHandler #endif -#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
diff --git a/Inc/stm32wbxx_hal.h b/Inc/stm32wbxx_hal.h index 68c02ed..b69544f 100644 --- a/Inc/stm32wbxx_hal.h +++ b/Inc/stm32wbxx_hal.h
@@ -65,7 +65,9 @@ #define SYSCFG_BOOT_MAINFLASH LL_SYSCFG_REMAP_FLASH /*!< Main Flash memory mapped at 0x00000000 */ #define SYSCFG_BOOT_SYSTEMFLASH LL_SYSCFG_REMAP_SYSTEMFLASH /*!< System Flash memory mapped at 0x00000000 */ #define SYSCFG_BOOT_SRAM LL_SYSCFG_REMAP_SRAM /*!< SRAM1 mapped at 0x00000000 */ +#if defined(LL_SYSCFG_REMAP_QUADSPI) #define SYSCFG_BOOT_QUADSPI LL_SYSCFG_REMAP_QUADSPI /*!< QUADSPI memory mapped at 0x00000000 */ +#endif /** * @} */ @@ -215,7 +217,9 @@ /** @defgroup Secure_IP_Write_Access Secure IP Write Access * @{ */ +#if defined(LL_SYSCFG_SECURE_ACCESS_AES1) #define HAL_SYSCFG_SECURE_ACCESS_AES1 LL_SYSCFG_SECURE_ACCESS_AES1 /*!< Enabling the security access of Advanced Encryption Standard 1 KEY[7:0] */ +#endif #define HAL_SYSCFG_SECURE_ACCESS_AES2 LL_SYSCFG_SECURE_ACCESS_AES2 /*!< Enabling the security access of Advanced Encryption Standard 2 */ #define HAL_SYSCFG_SECURE_ACCESS_PKA LL_SYSCFG_SECURE_ACCESS_PKA /*!< Enabling the security access of Public Key Accelerator */ #define HAL_SYSCFG_SECURE_ACCESS_RNG LL_SYSCFG_SECURE_ACCESS_RNG /*!< Enabling the security access of Random Number Generator */ @@ -382,9 +386,11 @@ */ #define __HAL_SYSCFG_REMAPMEMORY_SRAM() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SRAM) +#if defined(LL_SYSCFG_REMAP_QUADSPI) /** @brief QUADSPI mapped at 0x00000000. */ #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_QUADSPI) +#endif /** * @brief Return the boot mode as configured by user. @@ -393,7 +399,9 @@ * @arg @ref SYSCFG_BOOT_MAINFLASH * @arg @ref SYSCFG_BOOT_SYSTEMFLASH * @arg @ref SYSCFG_BOOT_SRAM +#if defined(LL_SYSCFG_REMAP_QUADSPI) * @arg @ref SYSCFG_BOOT_QUADSPI +#endif */ #define __HAL_SYSCFG_GET_BOOT_MODE() LL_SYSCFG_GetRemapMemory() @@ -510,6 +518,7 @@ #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU)) +#if defined(VREFBUF) #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1)) @@ -517,16 +526,23 @@ ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) +#endif #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) +#if defined(LL_SYSCFG_SECURE_ACCESS_AES1) #define IS_SYSCFG_SECURITY_ACCESS(__VALUE__) ((((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES1) == HAL_SYSCFG_SECURE_ACCESS_AES1) || \ (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES2) == HAL_SYSCFG_SECURE_ACCESS_AES2) || \ (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_PKA) == HAL_SYSCFG_SECURE_ACCESS_PKA) || \ (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_RNG) == HAL_SYSCFG_SECURE_ACCESS_RNG)) +#else +#define IS_SYSCFG_SECURITY_ACCESS(__VALUE__) ((((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES2) == HAL_SYSCFG_SECURE_ACCESS_AES2) || \ + (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_PKA) == HAL_SYSCFG_SECURE_ACCESS_PKA) || \ + (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_RNG) == HAL_SYSCFG_SECURE_ACCESS_RNG)) +#endif /** * @} @@ -628,11 +644,13 @@ void HAL_SYSCFG_DisableSRAMFetch(void); uint32_t HAL_SYSCFG_IsEnabledSRAMFetch(void); +#if defined(VREFBUF) void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); void HAL_SYSCFG_DisableVREFBUF(void); +#endif void HAL_SYSCFG_EnableIOBooster(void); void HAL_SYSCFG_DisableIOBooster(void);
diff --git a/Inc/stm32wbxx_hal_adc.h b/Inc/stm32wbxx_hal_adc.h index 2f6b1f8..51790fc 100644 --- a/Inc/stm32wbxx_hal_adc.h +++ b/Inc/stm32wbxx_hal_adc.h
@@ -22,7 +22,7 @@ #define STM32WBxx_HAL_ADC_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -44,7 +44,7 @@ * @{ */ -/** +/** * @brief ADC group regular oversampling structure definition */ typedef struct @@ -66,7 +66,7 @@ (the oversampling buffer is zeroed during injection sequence). This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */ -}ADC_OversamplingTypeDef; +} ADC_OversamplingTypeDef; /** * @brief Structure definition of ADC instance and ADC group regular. @@ -89,15 +89,19 @@ uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler. This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. Note: The ADC clock configuration is common to all ADC instances. - Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, + Note: ADC clock source and prescaler must be selected in function of system clock to not exceed ADC maximum frequency, depending on devices. + Example: STM32WB55xx ADC maximum frequency is 64MHz (corresponding to 4.27Msmp/s maximum) + Example: STM32WB50xx ADC maximum frequency is 32MHz (corresponding to 2.13Msmp/s maximum) + For ADC maximum frequency, refer to datasheet of the selected device. + Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only - if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC + if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level. Note: This parameter can be modified only if all ADC instances are disabled. */ - uint32_t Resolution; /*!< Configure the ADC resolution. + uint32_t Resolution; /*!< Configure the ADC resolution. This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). @@ -134,7 +138,7 @@ uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer. To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 16. - Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without + Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence @@ -151,7 +155,7 @@ If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. This parameter can be a value of @ref ADC_regular_external_trigger_source. Caution: external trigger source is common to all ADC instances. */ - + uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start. If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. This parameter can be a value of @ref ADC_regular_external_trigger_edge */ @@ -164,11 +168,11 @@ uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). This parameter applies to ADC group regular only. This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. - Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear - end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function + Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear + end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). Note: Error reporting with respect to the conversion mode: - - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data + - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case. - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */ @@ -179,7 +183,7 @@ ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */ -}ADC_InitTypeDef; +} ADC_InitTypeDef; /** * @brief Structure definition of ADC channel for regular group @@ -232,12 +236,12 @@ uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data. Offset value must be a positive number. - Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, + Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. - Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled + Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ -}ADC_ChannelConfTypeDef; +} ADC_ChannelConfTypeDef; /** * @brief Structure definition of ADC analog watchdog @@ -268,7 +272,7 @@ uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. - Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits + Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: the comparison of analog watchdog thresholds is done on @@ -284,7 +288,7 @@ impacted: the comparison of analog watchdog thresholds is done on oversampling final computation (after ratio and shift application): ADC data register bitfield [15:4] (12 most significant bits). */ -}ADC_AnalogWDGConfTypeDef; +} ADC_AnalogWDGConfTypeDef; /** * @brief ADC group injected contexts queue configuration @@ -292,12 +296,12 @@ */ typedef struct { - uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each + uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each HAL_ADCEx_InjectedConfigChannel() call to finally initialize JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ - + uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ -}ADC_InjectionConfigTypeDef; +} ADC_InjectionConfigTypeDef; /** @defgroup ADC_States ADC States * @{ @@ -307,7 +311,7 @@ * @brief HAL ADC state machine: ADC states definition (bitfields) * @note ADC state machine is managed by bitfields, state must be compared * with bit by bit. - * For example: + * For example: * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */ @@ -377,7 +381,7 @@ void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ -}ADC_HandleTypeDef; +} ADC_HandleTypeDef; #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /** @@ -752,7 +756,7 @@ * @param __HANDLE__ ADC handle * @retval None */ -#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) +#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) /** * @brief Simultaneously clear and set specific bits of the handle State. @@ -766,7 +770,7 @@ /** * @brief Verify that a given value is aligned with the ADC resolution range. * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). - * @param __ADC_VALUE__ value checked against the resolution. + * @param __ADC_VALUE__ value checked against the resolution. * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) */ #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ @@ -774,7 +778,7 @@ /** * @brief Verify the length of the scheduled regular conversions group. - * @param __LENGTH__ number of programmed conversions. + * @param __LENGTH__ number of programmed conversions. * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large) */ #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL))) @@ -782,7 +786,7 @@ /** * @brief Verify the number of scheduled regular conversions in discontinuous mode. - * @param NUMBER number of scheduled regular conversions in discontinuous mode. + * @param NUMBER number of scheduled regular conversions in discontinuous mode. * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large) */ #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL))) @@ -807,7 +811,7 @@ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \ - ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) + ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) /** * @brief Verify the ADC resolution setting. @@ -818,18 +822,18 @@ ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) - -/** + +/** * @brief Verify the ADC resolution setting when limited to 6 or 8 bits. - * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits. + * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits. * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) - */ + */ #define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) /** * @brief Verify the ADC converted data alignment. - * @param __ALIGN__ programmed ADC converted data alignment. + * @param __ALIGN__ programmed ADC converted data alignment. * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid) */ #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \ @@ -939,7 +943,7 @@ /* Minimum ADC Clock frequency is 0.14 MHz */ /* Maximum conversion time is */ /* 653 / 0.14 MHz = 4.66 ms */ -#define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */ +#define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */ /* Delay for temperature sensor stabilization time. */ /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */ @@ -969,10 +973,10 @@ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ do{ \ - (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) + (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ ((__HANDLE__)->State = HAL_ADC_STATE_RESET) @@ -993,7 +997,7 @@ * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. + * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. * @retval None */ #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ @@ -1014,7 +1018,7 @@ * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. + * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. * @retval None */ #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ @@ -1034,28 +1038,28 @@ * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. + * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. * @retval State of interruption (SET or RESET) */ #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) - + /** * @brief Check whether the specified ADC flag is set or not. * @param __HANDLE__ ADC handle * @param __FLAG__ ADC flag * This parameter can be one of the following values: - * @arg @ref ADC_FLAG_RDY ADC Ready flag - * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag - * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag - * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag - * @arg @ref ADC_FLAG_OVR ADC overrun flag - * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag - * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag + * @arg @ref ADC_FLAG_RDY ADC Ready flag + * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag + * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag + * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag + * @arg @ref ADC_FLAG_OVR ADC overrun flag + * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag + * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) - * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. + * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. * @retval State of flag (TRUE or FALSE). */ #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ @@ -1066,17 +1070,17 @@ * @param __HANDLE__ ADC handle * @param __FLAG__ ADC flag * This parameter can be one of the following values: - * @arg @ref ADC_FLAG_RDY ADC Ready flag - * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag - * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag - * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag - * @arg @ref ADC_FLAG_OVR ADC overrun flag - * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag - * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag + * @arg @ref ADC_FLAG_RDY ADC Ready flag + * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag + * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag + * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag + * @arg @ref ADC_FLAG_OVR ADC overrun flag + * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag + * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) - * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. + * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. * @retval None */ /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ @@ -1129,7 +1133,7 @@ * @retval Value between Min_Data=0 and Max_Data=18 */ #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ - __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) + __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) /** * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x @@ -1169,7 +1173,7 @@ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ - __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) + __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) /** * @brief Helper macro to determine whether the selected channel @@ -1218,7 +1222,7 @@ * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. */ #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ - __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) + __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) /** * @brief Helper macro to convert a channel defined from parameter @@ -1281,7 +1285,7 @@ * @arg @ref ADC_CHANNEL_18 */ #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ - __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) + __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) /** * @brief Helper macro to determine whether the internal channel @@ -1305,7 +1309,7 @@ * Value "1" if the internal channel selected is available on the ADC instance selected. */ #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ - __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) + __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) /** * @brief Helper macro to select the ADC common instance @@ -1318,7 +1322,7 @@ * @retval ADC common register instance */ #define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ - __LL_ADC_COMMON_INSTANCE((__ADCx__)) + __LL_ADC_COMMON_INSTANCE((__ADCx__)) /** * @brief Helper macro to check if all ADC instances sharing the same @@ -1338,7 +1342,7 @@ * is enabled. */ #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ - __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) + __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) /** * @brief Helper macro to define the ADC conversion data full-scale digital @@ -1354,12 +1358,12 @@ * @retval ADC conversion data full-scale digital value */ #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ - __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) + __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) /** * @brief Helper macro to convert the ADC conversion data from * a resolution to another resolution. - * @param __DATA__ ADC conversion data to be converted + * @param __DATA__ ADC conversion data to be converted * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted * This parameter can be one of the following values: * @arg @ref ADC_RESOLUTION_12B @@ -1377,9 +1381,9 @@ #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ __ADC_RESOLUTION_CURRENT__,\ __ADC_RESOLUTION_TARGET__) \ - __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ - (__ADC_RESOLUTION_CURRENT__),\ - (__ADC_RESOLUTION_TARGET__)) + __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__), \ + (__ADC_RESOLUTION_CURRENT__), \ + (__ADC_RESOLUTION_TARGET__)) /** * @brief Helper macro to calculate the voltage (unit: mVolt) @@ -1400,9 +1404,9 @@ #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ __ADC_DATA__,\ __ADC_RESOLUTION__) \ - __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ - (__ADC_DATA__),\ - (__ADC_RESOLUTION__)) + __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__), \ + (__ADC_DATA__), \ + (__ADC_RESOLUTION__)) /** * @brief Helper macro to calculate analog reference voltage (Vref+) @@ -1431,8 +1435,8 @@ */ #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ __ADC_RESOLUTION__) \ - __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ - (__ADC_RESOLUTION__)) + __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__), \ + (__ADC_RESOLUTION__)) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) @@ -1482,9 +1486,9 @@ #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ __ADC_RESOLUTION__) \ - __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ - (__TEMPSENSOR_ADC_DATA__),\ - (__ADC_RESOLUTION__)) + __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__), \ + (__TEMPSENSOR_ADC_DATA__), \ + (__ADC_RESOLUTION__)) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) @@ -1536,12 +1540,12 @@ __VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ __ADC_RESOLUTION__) \ - __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ - (__TEMPSENSOR_TYP_CALX_V__),\ - (__TEMPSENSOR_CALX_TEMP__),\ - (__VREFANALOG_VOLTAGE__),\ - (__TEMPSENSOR_ADC_DATA__),\ - (__ADC_RESOLUTION__)) + __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__), \ + (__TEMPSENSOR_TYP_CALX_V__), \ + (__TEMPSENSOR_CALX_TEMP__), \ + (__VREFANALOG_VOLTAGE__), \ + (__TEMPSENSOR_ADC_DATA__), \ + (__ADC_RESOLUTION__)) /** * @} @@ -1564,14 +1568,15 @@ * @{ */ /* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); -void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); -void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); +void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); +void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /* Callbacks Register/UnRegister functions ***********************************/ -HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, + pADC_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** @@ -1585,39 +1590,39 @@ /* IO operation functions *****************************************************/ /* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); -HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); /* Non-blocking mode: Interruption */ -HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); /* Non-blocking mode: DMA */ -HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); -HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); /* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ -void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); -void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); -void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); -void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); +void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); +void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); /** * @} */ /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * @{ - */ + * @brief Peripheral Control functions + * @{ + */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); /** * @} @@ -1627,7 +1632,7 @@ /** @addtogroup ADC_Exported_Functions_Group4 * @{ */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** @@ -1642,9 +1647,9 @@ /** @addtogroup ADC_Private_Functions ADC Private Functions * @{ */ -HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup); -HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup); +HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); void ADC_DMAError(DMA_HandleTypeDef *hdma);
diff --git a/Inc/stm32wbxx_hal_adc_ex.h b/Inc/stm32wbxx_hal_adc_ex.h index 223c437..2bf99de 100644 --- a/Inc/stm32wbxx_hal_adc_ex.h +++ b/Inc/stm32wbxx_hal_adc_ex.h
@@ -22,7 +22,7 @@ #define STM32WBxx_HAL_ADC_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -48,12 +48,12 @@ { uint32_t Ratio; /*!< Configures the oversampling ratio. This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ - + uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ -}ADC_InjOversamplingTypeDef; +} ADC_InjOversamplingTypeDef; -/** +/** * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected * @note Parameters of this structure are shared within 2 scopes: * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset @@ -64,7 +64,7 @@ * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff') * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group. * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups. - * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going + * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going * on ADC groups regular and injected. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). @@ -77,7 +77,7 @@ uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. This parameter must be a value of @ref ADC_INJ_SEQ_RANKS. - Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by + Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions adjusted) */ uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. @@ -100,7 +100,7 @@ Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). - If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case + If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case of another parameter update on the fly) */ uint32_t InjectedOffsetNumber; /*!< Selects the offset number. @@ -111,27 +111,27 @@ Offset value must be a positive number. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. - Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled + Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer. To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 4. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. - Discontinuous mode can be enabled only if continuous mode is disabled. + Discontinuous mode can be enabled only if continuous mode is disabled. This parameter can be set to ENABLE or DISABLE. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank). - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one - This parameter can be set to ENABLE or DISABLE. + This parameter can be set to ENABLE or DISABLE. Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START) Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. @@ -142,11 +142,11 @@ FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. This parameter can be set to ENABLE or DISABLE. If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a - new injected context is set when queue is full, error is triggered by interruption and through function + new injected context is set when queue is full, error is triggered by interruption and through function 'HAL_ADCEx_InjectedQueueOverflowCallback'. Caution: This feature request that the sequence is fully configured before injected conversion start. Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */ @@ -159,7 +159,7 @@ uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. This parameter can be a value of @ref ADC_injected_external_trigger_edge. If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. @@ -167,9 +167,9 @@ Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. - Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. + Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ -}ADC_InjectionConfTypeDef; +} ADC_InjectionConfTypeDef; /** * @} @@ -199,10 +199,10 @@ /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) * @{ */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ /** * @} */ @@ -261,7 +261,7 @@ /** * @} */ - + /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields * @{ */ @@ -273,7 +273,7 @@ * @} */ -/** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields +/** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields * @{ */ /* ADC_CFGR fields of parameters that can be updated when no conversion @@ -310,7 +310,7 @@ /** * @brief Check whether or not ADC is independent. * @param __HANDLE__ ADC handle. - * @note When multimode feature is not available, the macro always returns SET. + * @note When multimode feature is not available, the macro always returns SET. * @retval SET (ADC is independent) or RESET (ADC is not). */ #define ADC_IS_INDEPENDENT(__HANDLE__) (SET) @@ -374,7 +374,7 @@ /** - * @brief Shift the offset with respect to the selected ADC resolution. + * @brief Shift the offset with respect to the selected ADC resolution. * @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0. * If resolution 12 bits, no shift. * If resolution 10 bits, shift of 2 ranks on the left. @@ -386,7 +386,7 @@ * @retval None */ #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ - ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) + ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) /** * @brief Shift the AWD1 threshold with respect to the selected ADC resolution. @@ -401,7 +401,7 @@ * @retval None */ #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ - ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) + ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) /** * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution. @@ -416,8 +416,8 @@ */ #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) ? \ - ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \ - ((__THRESHOLD__) << 2UL) \ + ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \ + ((__THRESHOLD__) << 2UL) \ ) /** @@ -455,7 +455,7 @@ /** * @brief Verify the length of scheduled injected conversions group. - * @param __LENGTH__ number of programmed conversions. + * @param __LENGTH__ number of programmed conversions. * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large) */ #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) @@ -471,7 +471,7 @@ /** * @brief Verify the ADC channel setting. * @param __HANDLE__ ADC handle. - * @param __CHANNEL__ programmed ADC channel. + * @param __CHANNEL__ programmed ADC channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) */ #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1) && \ @@ -501,7 +501,7 @@ /** * @brief Verify the ADC channel setting in differential mode. * @param __HANDLE__ ADC handle. - * @param __CHANNEL__ programmed ADC channel. + * @param __CHANNEL__ programmed ADC channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) */ #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ @@ -522,7 +522,7 @@ /** * @brief Verify the ADC single-ended input or differential mode setting. - * @param __SING_DIFF__ programmed channel setting. + * @param __SING_DIFF__ programmed channel setting. * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid) */ #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \ @@ -530,24 +530,24 @@ /** * @brief Verify the ADC offset management setting. - * @param __OFFSET_NUMBER__ ADC offset management. + * @param __OFFSET_NUMBER__ ADC offset management. * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid) */ #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \ ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \ ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \ ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \ - ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) + ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) /** * @brief Verify the ADC injected channel setting. - * @param __CHANNEL__ programmed ADC injected channel. + * @param __CHANNEL__ programmed ADC injected channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) */ #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \ ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \ ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \ - ((__CHANNEL__) == ADC_INJECTED_RANK_4) ) + ((__CHANNEL__) == ADC_INJECTED_RANK_4) ) /** * @brief Verify the ADC injected conversions external trigger. @@ -567,11 +567,11 @@ * @brief Verify the ADC edge trigger setting for injected group. * @param __EDGE__ programmed ADC edge trigger setting. * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) - */ -#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ - ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ - ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ - ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) + */ +#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ + ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ + ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ + ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) /** * @brief Verify the ADC analog watchdog setting. @@ -580,7 +580,7 @@ */ #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \ ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \ - ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) + ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) /** * @brief Verify the ADC analog watchdog mode setting. @@ -593,31 +593,31 @@ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ - ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) + ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) /** * @brief Verify the ADC conversion (regular or injected or both). * @param __CONVERSION__ ADC conversion group. * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid) */ -#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ - ((__CONVERSION__) == ADC_INJECTED_GROUP) || \ - ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) ) +#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ + ((__CONVERSION__) == ADC_INJECTED_GROUP) || \ + ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) ) /** * @brief Verify the ADC event type. * @param __EVENT__ ADC event. * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid) */ -#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ - ((__EVENT__) == ADC_AWD_EVENT) || \ - ((__EVENT__) == ADC_AWD2_EVENT) || \ - ((__EVENT__) == ADC_AWD3_EVENT) || \ - ((__EVENT__) == ADC_OVR_EVENT) || \ - ((__EVENT__) == ADC_JQOVF_EVENT) ) +#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ + ((__EVENT__) == ADC_AWD_EVENT) || \ + ((__EVENT__) == ADC_AWD2_EVENT) || \ + ((__EVENT__) == ADC_AWD3_EVENT) || \ + ((__EVENT__) == ADC_OVR_EVENT) || \ + ((__EVENT__) == ADC_JQOVF_EVENT) ) /** - * @brief Verify the ADC oversampling ratio. + * @brief Verify the ADC oversampling ratio. * @param __RATIO__ programmed ADC oversampling ratio. * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid) */ @@ -631,7 +631,7 @@ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 )) /** - * @brief Verify the ADC oversampling shift. + * @brief Verify the ADC oversampling shift. * @param __SHIFT__ programmed ADC oversampling shift. * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) */ @@ -646,37 +646,37 @@ ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 )) /** - * @brief Verify the ADC oversampling triggered mode. - * @param __MODE__ programmed ADC oversampling triggered mode. + * @brief Verify the ADC oversampling triggered mode. + * @param __MODE__ programmed ADC oversampling triggered mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ - ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) + ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) /** - * @brief Verify the ADC oversampling regular conversion resumed or continued mode. - * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. + * @brief Verify the ADC oversampling regular conversion resumed or continued mode. + * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \ - ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) + ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) /** - * @brief Verify the DFSDM mode configuration. - * @param __HANDLE__ ADC handle. + * @brief Verify the DFSDM mode configuration. + * @param __HANDLE__ ADC handle. * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For * this reason, the input parameter is the ADC handle and not the configuration parameter - * directly. + * directly. * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid) */ #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET) /** * @brief Return the DFSDM configuration mode. - * @param __HANDLE__ ADC handle. - * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). + * @param __HANDLE__ ADC handle. + * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). * For this reason, the input parameter is the ADC handle and not the configuration parameter - * directly. + * directly. * @retval DFSDM configuration mode */ #define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL) @@ -697,33 +697,34 @@ /* IO operation functions *****************************************************/ /* ADC calibration */ -HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff); +HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); -HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor); +HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, + uint32_t CalibrationFactor); /* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); /* Non-blocking mode: Interruption */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); /* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); +uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ -void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); -void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc); -void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc); -void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc); -void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc); +void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); +void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc); +void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc); +void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc); +void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc); /* ADC group regular conversions stop */ -HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc); /** * @} */ @@ -732,11 +733,11 @@ * @{ */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); -HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,ADC_InjectionConfTypeDef* sConfigInjected); +HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc); /** * @}
diff --git a/Inc/stm32wbxx_hal_comp.h b/Inc/stm32wbxx_hal_comp.h index 82d73fc..59edc5d 100644 --- a/Inc/stm32wbxx_hal_comp.h +++ b/Inc/stm32wbxx_hal_comp.h
@@ -32,7 +32,7 @@ /** @addtogroup STM32WBxx_HAL_Driver * @{ */ - +#if defined (COMP1) || defined (COMP2) /** @addtogroup COMP * @{ @@ -697,7 +697,7 @@ /** * @} */ - +#endif /* COMP1 || COMP2 */ /** * @} */
diff --git a/Inc/stm32wbxx_hal_cortex.h b/Inc/stm32wbxx_hal_cortex.h index 5d56b08..bc0e0ac 100644 --- a/Inc/stm32wbxx_hal_cortex.h +++ b/Inc/stm32wbxx_hal_cortex.h
@@ -27,7 +27,6 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32wbxx_hal_def.h" -#include "stm32wb55xx.h" /** @addtogroup STM32WBxx_HAL_Driver * @{
diff --git a/Inc/stm32wbxx_hal_dma.h b/Inc/stm32wbxx_hal_dma.h index f8c1169..9467354 100644 --- a/Inc/stm32wbxx_hal_dma.h +++ b/Inc/stm32wbxx_hal_dma.h
@@ -361,7 +361,7 @@ * @{ */ -/** @brief Reset DMA handle state +/** @brief Reset DMA handle state. * @param __HANDLE__ DMA handle * @retval None */ @@ -385,11 +385,12 @@ /* Interrupt & Flag management */ /** - * @brief Returns the current DMA Channel transfer complete flag. + * @brief Return the current DMA Channel transfer complete flag. * @param __HANDLE__ DMA handle * @retval The specified transfer complete flag index. */ +#if defined(DMA2) #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ @@ -404,12 +405,23 @@ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\ DMA_FLAG_TC7) +#else +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + DMA_FLAG_TC7) +#endif /** - * @brief Returns the current DMA Channel half transfer complete flag. + * @brief Return the current DMA Channel half transfer complete flag. * @param __HANDLE__ DMA handle * @retval The specified half transfer complete flag index. */ +#if defined(DMA2) #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ @@ -424,12 +436,23 @@ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\ DMA_FLAG_HT7) +#else +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + DMA_FLAG_HT7) +#endif /** - * @brief Returns the current DMA Channel transfer error flag. + * @brief Return the current DMA Channel transfer error flag. * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ +#if defined(DMA2) #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ @@ -444,12 +467,23 @@ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\ DMA_FLAG_TE7) +#else +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + DMA_FLAG_TE7) +#endif /** - * @brief Returns the current DMA Channel Global interrupt flag. + * @brief Return the current DMA Channel Global interrupt flag. * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ +#if defined(DMA2) #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\ @@ -464,6 +498,16 @@ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\ DMA_ISR_GIF7) +#else +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ + DMA_ISR_GIF7) +#endif /** * @brief Get the DMA Channel pending flags. @@ -477,8 +521,12 @@ * Where x can be from 1 to 7 to select the DMA Channel x flag. * @retval The state of FLAG (SET or RESET). */ +#if defined(DMA2) #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) +#else +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) +#endif /** * @brief Clear the DMA Channel pending flags. @@ -492,8 +540,12 @@ * Where x can be from 1 to 7 to select the DMA Channel x flag. * @retval None */ +#if defined(DMA2) #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) +#else +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) +#endif /** * @brief Enable the specified DMA Channel interrupts. @@ -532,7 +584,7 @@ #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) /** - * @brief Returns the number of remaining data units in the current DMA Channel transfer. + * @brief Return the number of remaining data units in the current DMA Channel transfer. * @param __HANDLE__ DMA handle * @retval The number of remaining data units in the current DMA Channel transfer. */
diff --git a/Inc/stm32wbxx_hal_exti.h b/Inc/stm32wbxx_hal_exti.h index 8bd410d..e169796 100644 --- a/Inc/stm32wbxx_hal_exti.h +++ b/Inc/stm32wbxx_hal_exti.h
@@ -128,7 +128,11 @@ #define EXTI_LINE_40 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | 0x08u) #define EXTI_LINE_41 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | 0x09u) #define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0Au) +#if defined (STM32WB55xx) #define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu) +#else +#define EXTI_LINE_43 (EXTI_RESERVED | EXTI_REG2 | 0x0Bu) +#endif #define EXTI_LINE_44 (EXTI_DIRECT | EXTI_REG2 | 0x0Cu) #define EXTI_LINE_45 (EXTI_DIRECT | EXTI_REG2 | 0x0Du) #define EXTI_LINE_46 (EXTI_DIRECT | EXTI_REG2 | 0x0Eu) @@ -166,7 +170,9 @@ #define EXTI_GPIOA 0x00000000u #define EXTI_GPIOB 0x00000001u #define EXTI_GPIOC 0x00000002u +#if defined (STM32WB55xx) #define EXTI_GPIOD 0x00000003u +#endif #define EXTI_GPIOE 0x00000004u #define EXTI_GPIOH 0x00000007u /** @@ -255,12 +261,20 @@ #define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u) +#if defined (STM32WB55xx) #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ ((__PORT__) == EXTI_GPIOB) || \ ((__PORT__) == EXTI_GPIOC) || \ ((__PORT__) == EXTI_GPIOD) || \ ((__PORT__) == EXTI_GPIOE) || \ ((__PORT__) == EXTI_GPIOH)) +#else +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOH)) +#endif #define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
diff --git a/Inc/stm32wbxx_hal_gpio_ex.h b/Inc/stm32wbxx_hal_gpio_ex.h index 5c43d9c..e3c3fd3 100644 --- a/Inc/stm32wbxx_hal_gpio_ex.h +++ b/Inc/stm32wbxx_hal_gpio_ex.h
@@ -375,13 +375,18 @@ /** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index * @{ */ - +#if defined (STM32WB55xx) #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ ((__GPIOx__) == (GPIOB))? 1uL :\ ((__GPIOx__) == (GPIOC))? 2uL :\ ((__GPIOx__) == (GPIOD))? 3uL :\ ((__GPIOx__) == (GPIOE))? 4uL : 7uL) - +#else +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ + ((__GPIOx__) == (GPIOB))? 1uL :\ + ((__GPIOx__) == (GPIOC))? 2uL :\ + ((__GPIOx__) == (GPIOE))? 4uL : 7uL) +#endif /** * @} */
diff --git a/Inc/stm32wbxx_hal_i2c_ex.h b/Inc/stm32wbxx_hal_i2c_ex.h index 94d3011..4b6975d 100644 --- a/Inc/stm32wbxx_hal_i2c_ex.h +++ b/Inc/stm32wbxx_hal_i2c_ex.h
@@ -55,12 +55,17 @@ /** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus * @{ */ +#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ #define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ #define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ #define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ #define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ #define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ +#if defined(SYSCFG_CFGR1_I2C3_FMP) #define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ +#else +#define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */ +#endif /** * @} */
diff --git a/Inc/stm32wbxx_hal_iwdg.h b/Inc/stm32wbxx_hal_iwdg.h index 4dd0579..a206d19 100644 --- a/Inc/stm32wbxx_hal_iwdg.h +++ b/Inc/stm32wbxx_hal_iwdg.h
@@ -119,7 +119,7 @@ /** * @brief Reload IWDG counter with value defined in the reload register - * (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled). + * (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled). * @param __HANDLE__ IWDG handle * @retval None */ @@ -219,6 +219,7 @@ */ #define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN) + /** * @} */
diff --git a/Inc/stm32wbxx_hal_lcd.h b/Inc/stm32wbxx_hal_lcd.h index 5d77cde..86e55f8 100644 --- a/Inc/stm32wbxx_hal_lcd.h +++ b/Inc/stm32wbxx_hal_lcd.h
@@ -33,6 +33,8 @@ * @{ */ +#if defined (LCD) + /** @addtogroup LCD * @{ */ @@ -755,6 +757,8 @@ * @} */ +#endif /* LCD */ + /** * @} */
diff --git a/Inc/stm32wbxx_hal_lptim.h b/Inc/stm32wbxx_hal_lptim.h index b3f3416..8db7416 100644 --- a/Inc/stm32wbxx_hal_lptim.h +++ b/Inc/stm32wbxx_hal_lptim.h
@@ -42,6 +42,8 @@ /** @defgroup LPTIM_Exported_Types LPTIM Exported Types * @{ */ +#define LPTIM_EXTI_LINE_LPTIM1 EXTI_IMR1_IM29 /*!< External interrupt line 29 Connected to the LPTIM1 EXTI Line */ +#define LPTIM_EXTI_LINE_LPTIM2 EXTI_IMR1_IM30 /*!< External interrupt line 30 Connected to the LPTIM2 EXTI Line */ /** * @brief LPTIM Clock configuration definition @@ -397,6 +399,8 @@ * @note The following sequence is required to solve LPTIM disable HW limitation. * Please check Errata Sheet ES0335 for more details under "MCU may remain * stuck in LPTIM interrupt when entering Stop mode" section. + * @note Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to + * check for TIMEOUT. * @retval None */ #define __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__) @@ -433,6 +437,7 @@ * @param __HANDLE__ LPTIM handle * @param __VALUE__ Autoreload value * @retval None + * @note The ARR register can only be modified when the LPTIM instance is enabled. */ #define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__)) @@ -441,6 +446,7 @@ * @param __HANDLE__ LPTIM handle * @param __VALUE__ Compare value * @retval None + * @note The CMP register can only be modified when the LPTIM instance is enabled. */ #define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__)) @@ -489,6 +495,7 @@ * @arg LPTIM_IT_ARRM : Autoreload match Interrupt. * @arg LPTIM_IT_CMPM : Compare match Interrupt. * @retval None. + * @note The LPTIM interrupts can only be enabled when the LPTIM instance is disabled. */ #define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) @@ -505,6 +512,7 @@ * @arg LPTIM_IT_ARRM : Autoreload match Interrupt. * @arg LPTIM_IT_CMPM : Compare match Interrupt. * @retval None. + * @note The LPTIM interrupts can only be disabled when the LPTIM instance is disabled. */ #define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) @@ -526,6 +534,56 @@ #define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** + * @brief Enable the LPTIM1 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM1) + +/** + * @brief Disable the LPTIM1 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(LPTIM_EXTI_LINE_LPTIM1)) + + +/** + * @brief Enable the LPTIM1 EXTI line in event mode. + * @retval None + */ +#define __HAL_LPTIM_LPTIM1_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= LPTIM_EXTI_LINE_LPTIM1) + +/** + * @brief Disable the LPTIM1 EXTI line in event mode. + * @retval None + */ +#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(LPTIM_EXTI_LINE_LPTIM1)) + +/** + * @brief Enable the LPTIM2 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT() (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM2) + +/** + * @brief Disable the LPTIM2 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(LPTIM_EXTI_LINE_LPTIM2)) + + +/** + * @brief Enable the LPTIM2 EXTI line in event mode. + * @retval None + */ +#define __HAL_LPTIM_LPTIM2_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= LPTIM_EXTI_LINE_LPTIM2) + +/** + * @brief Disable the LPTIM2 EXTI line in event mode. + * @retval None + */ +#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(LPTIM_EXTI_LINE_LPTIM2)) + +/** * @} */ @@ -737,7 +795,7 @@ /** @defgroup LPTIM_Private_Functions LPTIM Private Functions * @{ */ -void LPTIM_Disable(LPTIM_HandleTypeDef *lptim); +void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim); /** * @} */
diff --git a/Inc/stm32wbxx_hal_pcd.h b/Inc/stm32wbxx_hal_pcd.h index ea7f10f..c076705 100644 --- a/Inc/stm32wbxx_hal_pcd.h +++ b/Inc/stm32wbxx_hal_pcd.h
@@ -155,7 +155,7 @@ /** @defgroup PCD_Speed PCD Speed * @{ */ -#define PCD_SPEED_FULL 2U +#define PCD_SPEED_FULL USBD_FS_SPEED /** * @} */
diff --git a/Inc/stm32wbxx_hal_pwr_ex.h b/Inc/stm32wbxx_hal_pwr_ex.h index 9b91984..b7367f4 100644 --- a/Inc/stm32wbxx_hal_pwr_ex.h +++ b/Inc/stm32wbxx_hal_pwr_ex.h
@@ -61,6 +61,7 @@ This parameter can be a value of @ref PWREx_WakeUpTarget_Definition */ }PWR_PVMTypeDef; +#if defined(PWR_CR5_SMPSEN) /** * @brief PWR SMPS step down configuration structure definition */ @@ -72,6 +73,7 @@ uint32_t OutputVoltage; /*!< SMPS step down converter output voltage scaling voltage level. This parameter can be a value of @ref PWREx_SMPS_OUTPUT_VOLTAGE_LEVEL */ }PWR_SMPSTypeDef; +#endif /** * @} @@ -96,26 +98,44 @@ * @{ */ #define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ +#if defined(PWR_CR3_EWUP2) #define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ +#endif +#if defined(PWR_CR3_EWUP3) #define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ +#endif #define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ +#if defined(PWR_CR3_EWUP5) #define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ +#endif #define PWR_WAKEUP_PIN1_LOW ((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */ +#if defined(PWR_CR3_EWUP2) #define PWR_WAKEUP_PIN2_LOW ((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */ +#endif +#if defined(PWR_CR3_EWUP3) #define PWR_WAKEUP_PIN3_LOW ((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */ +#endif #define PWR_WAKEUP_PIN4_LOW ((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */ +#if defined(PWR_CR3_EWUP5) #define PWR_WAKEUP_PIN5_LOW ((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */ +#endif /** * @} */ /* Literals kept for legacy purpose */ #define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ +#if defined(PWR_CR3_EWUP2) #define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ +#endif +#if defined(PWR_CR3_EWUP3) #define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ +#endif #define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ +#if defined(PWR_CR3_EWUP5) #define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ +#endif /** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration * @{ @@ -129,7 +149,9 @@ /** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type * @{ */ +#if defined(PWR_CR2_PVME1) #define PWR_PVM_1 PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */ +#endif #define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */ /** * @} @@ -163,8 +185,12 @@ /** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale * @{ */ +#if defined(PWR_CR1_VOS) #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz */ #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Regulator voltage output range 2 mode, typical output voltage at 1.0 V, system frequency up to 16 MHz */ +#else +#define PWR_REGULATOR_VOLTAGE_SCALE1 (0x00000200UL) /*!< Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz */ +#endif /** * @} */ @@ -191,20 +217,20 @@ /** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode * @{ */ -#define PWR_GPIO_BIT_0 PWR_PUCRC_PC0 /*!< GPIO port I/O pin 0 */ -#define PWR_GPIO_BIT_1 PWR_PUCRC_PC1 /*!< GPIO port I/O pin 1 */ -#define PWR_GPIO_BIT_2 PWR_PUCRC_PC2 /*!< GPIO port I/O pin 2 */ -#define PWR_GPIO_BIT_3 PWR_PUCRC_PC3 /*!< GPIO port I/O pin 3 */ -#define PWR_GPIO_BIT_4 PWR_PUCRC_PC4 /*!< GPIO port I/O pin 4 */ -#define PWR_GPIO_BIT_5 PWR_PUCRC_PC5 /*!< GPIO port I/O pin 5 */ -#define PWR_GPIO_BIT_6 PWR_PUCRC_PC6 /*!< GPIO port I/O pin 6 */ -#define PWR_GPIO_BIT_7 PWR_PUCRC_PC7 /*!< GPIO port I/O pin 7 */ -#define PWR_GPIO_BIT_8 PWR_PUCRC_PC8 /*!< GPIO port I/O pin 8 */ -#define PWR_GPIO_BIT_9 PWR_PUCRC_PC9 /*!< GPIO port I/O pin 9 */ -#define PWR_GPIO_BIT_10 PWR_PUCRC_PC10 /*!< GPIO port I/O pin 10 */ -#define PWR_GPIO_BIT_11 PWR_PUCRC_PC11 /*!< GPIO port I/O pin 11 */ -#define PWR_GPIO_BIT_12 PWR_PUCRC_PC12 /*!< GPIO port I/O pin 12 */ -#define PWR_GPIO_BIT_13 PWR_PUCRC_PC13 /*!< GPIO port I/O pin 14 */ +#define PWR_GPIO_BIT_0 PWR_PUCRA_PA0 /*!< GPIO port I/O pin 0 */ +#define PWR_GPIO_BIT_1 PWR_PUCRA_PA1 /*!< GPIO port I/O pin 1 */ +#define PWR_GPIO_BIT_2 PWR_PUCRA_PA2 /*!< GPIO port I/O pin 2 */ +#define PWR_GPIO_BIT_3 PWR_PUCRA_PA3 /*!< GPIO port I/O pin 3 */ +#define PWR_GPIO_BIT_4 PWR_PUCRA_PA4 /*!< GPIO port I/O pin 4 */ +#define PWR_GPIO_BIT_5 PWR_PUCRA_PA5 /*!< GPIO port I/O pin 5 */ +#define PWR_GPIO_BIT_6 PWR_PUCRA_PA6 /*!< GPIO port I/O pin 6 */ +#define PWR_GPIO_BIT_7 PWR_PUCRA_PA7 /*!< GPIO port I/O pin 7 */ +#define PWR_GPIO_BIT_8 PWR_PUCRA_PA8 /*!< GPIO port I/O pin 8 */ +#define PWR_GPIO_BIT_9 PWR_PUCRA_PA9 /*!< GPIO port I/O pin 9 */ +#define PWR_GPIO_BIT_10 PWR_PUCRA_PA10 /*!< GPIO port I/O pin 10 */ +#define PWR_GPIO_BIT_11 PWR_PUCRA_PA11 /*!< GPIO port I/O pin 11 */ +#define PWR_GPIO_BIT_12 PWR_PUCRA_PA12 /*!< GPIO port I/O pin 12 */ +#define PWR_GPIO_BIT_13 PWR_PUCRA_PA13 /*!< GPIO port I/O pin 14 */ #define PWR_GPIO_BIT_14 PWR_PDCRC_PC14 /*!< GPIO port I/O pin 14 */ #define PWR_GPIO_BIT_15 PWR_PUCRC_PC15 /*!< GPIO port I/O pin 15 */ /** @@ -217,13 +243,16 @@ #define PWR_GPIO_A 0x00000000U /*!< GPIO port A */ #define PWR_GPIO_B 0x00000001U /*!< GPIO port B */ #define PWR_GPIO_C 0x00000002U /*!< GPIO port C */ +#if defined(GPIOD) #define PWR_GPIO_D 0x00000003U /*!< GPIO port D */ +#endif #define PWR_GPIO_E 0x00000004U /*!< GPIO port E */ #define PWR_GPIO_H 0x00000007U /*!< GPIO port H */ /** * @} */ +#if defined(PWR_CR5_SMPSEN) /** @defgroup PWREx_BOR_CONFIGURATION BOR configuration * @{ */ @@ -286,6 +315,7 @@ /** * @} */ +#endif /** @defgroup PWREx_Flag PWR Status Flags * Elements values convention: 0000 0000 0XXY YYYYb @@ -300,15 +330,22 @@ */ /*--------------------------------SR1-------------------------------*/ #define PWR_FLAG_WUF1 (0x0020U) /*!< Wakeup event on wakeup pin 1 */ +#if defined(PWR_CR3_EWUP2) #define PWR_FLAG_WUF2 (0x0021U) /*!< Wakeup event on wakeup pin 2 */ +#endif +#if defined(PWR_CR3_EWUP3) #define PWR_FLAG_WUF3 (0x0022U) /*!< Wakeup event on wakeup pin 3 */ +#endif #define PWR_FLAG_WUF4 (0x0023U) /*!< Wakeup event on wakeup pin 4 */ +#if defined(PWR_CR3_EWUP5) #define PWR_FLAG_WUF5 (0x0024U) /*!< Wakeup event on wakeup pin 5 */ +#endif #define PWR_FLAG_WU PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */ -#define PWR_FLAG_BHWF (0x0028U) /*!< BLE_Host WakeUp Flag */ -#define PWR_FLAG_FRCBYPI (0x0029U) /*!< SMPS Forced in Bypass Interrupt Flag */ - +#if defined(PWR_CR5_SMPSEN) +#define PWR_FLAG_FRCBYPI (0x0027U) /*!< SMPS Forced in Bypass Interrupt Flag */ +#endif +#define PWR_FLAG_BHWF (0x0029U) /*!< BLE_Host WakeUp Flag */ #define PWR_FLAG_RFPHASEI (0x002BU) /*!< Radio Phase Interrupt Flag */ #define PWR_FLAG_BLEACTI (0x002CU) /*!< BLE Activity Interrupt Flag */ #define PWR_FLAG_802ACTI (0x002DU) /*!< 802.15.4 Activity Interrupt Flag */ @@ -316,13 +353,17 @@ #define PWR_FLAG_WUFI (0x002FU) /*!< Wakeup on internal wakeup line */ /*--------------------------------SR2-------------------------------*/ +#if defined(PWR_CR5_SMPSEN) #define PWR_FLAG_SMPSRDYF (0x0040U) /*!< SMPS Ready Flag */ #define PWR_FLAG_SMPSBYPF (0x0041U) /*!< SMPS Bypass Flag */ +#endif #define PWR_FLAG_REGLPS (0x0048U) /*!< Low-power regulator start flag */ #define PWR_FLAG_REGLPF (0x0049U) /*!< Low-power regulator flag */ +#if defined(PWR_CR1_VOS) #define PWR_FLAG_VOSF (0x004AU) /*!< Voltage scaling flag */ +#endif #define PWR_FLAG_PVDO (0x004BU) /*!< Power Voltage Detector output flag */ #define PWR_FLAG_PVMO1 (0x004CU) /*!< Power Voltage Monitoring 1 output flag */ @@ -373,7 +414,9 @@ /** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines * @{ */ +#if defined(PWR_CR2_PVME1) #define PWR_EXTI_LINE_PVM1 (LL_EXTI_LINE_31) /*!< External interrupt line 31 Connected to PVM1 */ +#endif #define PWR_EXTI_LINE_PVM3 (LL_EXTI_LINE_33) /*!< External interrupt line 33 Connected to PVM3 */ /** * @} @@ -402,6 +445,7 @@ * @{ */ +#if defined(PWR_CR2_PVME1) /** * @brief Enable the PVM1 Extended Interrupt C1 Line. * @retval None @@ -521,6 +565,7 @@ */ #define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(PWR_EXTI_LINE_PVM1) +#endif /** * @brief Enable the PVM3 Extended Interrupt C1 Line. @@ -641,7 +686,7 @@ */ #define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_32_63(PWR_EXTI_LINE_PVM3) - +#if defined(PWR_CR1_VOS) /** * @brief Configure the main internal regulator output voltage. * @param __REGULATOR__ specifies the regulator output voltage to achieve @@ -665,6 +710,7 @@ tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \ UNUSED(tmpreg); \ } while(0) +#endif /** * @brief Wakeup BLE controller from its sleep mode @@ -690,7 +736,7 @@ /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros * @{ */ - +#if defined(PWR_CR3_EWUP2) #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1_HIGH) || \ ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \ ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \ @@ -701,13 +747,22 @@ ((PIN) == PWR_WAKEUP_PIN3_LOW) || \ ((PIN) == PWR_WAKEUP_PIN4_LOW) || \ ((PIN) == PWR_WAKEUP_PIN5_LOW)) +#else +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1_HIGH) || \ + ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \ + ((PIN) == PWR_WAKEUP_PIN1_LOW) || \ + ((PIN) == PWR_WAKEUP_PIN4_LOW)) +#endif #define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) || \ ((POLARITY) == PWR_PIN_POLARITY_LOW)) - +#if defined(PWR_CR2_PVME1) #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ ((TYPE) == PWR_PVM_3)) +#else +#define IS_PWR_PVM_TYPE(TYPE) ((TYPE) == PWR_PVM_3) +#endif #define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\ ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ @@ -720,9 +775,10 @@ #define IS_PWR_FLASH_POWERDOWN(__MODE__) ((((__MODE__) & (PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP)) != 0x00u) && \ (((__MODE__) & ~(PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP)) == 0x00u)) +#if defined(PWR_CR1_VOS) #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) - +#endif #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) @@ -732,14 +788,23 @@ #define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00) - + +#if defined(GPIOD) #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ ((GPIO) == PWR_GPIO_B) ||\ ((GPIO) == PWR_GPIO_C) ||\ ((GPIO) == PWR_GPIO_D) ||\ ((GPIO) == PWR_GPIO_E) ||\ ((GPIO) == PWR_GPIO_H)) +#else +#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ + ((GPIO) == PWR_GPIO_B) ||\ + ((GPIO) == PWR_GPIO_C) ||\ + ((GPIO) == PWR_GPIO_E) ||\ + ((GPIO) == PWR_GPIO_H)) +#endif +#if defined(PWR_CR5_SMPSEN) #define IS_PWR_SMPS_MODE(SMPS_MODE) (((SMPS_MODE) == PWR_SMPS_BYPASS) ||\ ((SMPS_MODE) == PWR_SMPS_STEP_DOWN)) @@ -767,6 +832,7 @@ ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V80) ||\ ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V85) ||\ ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V90)) +#endif #define IS_PWR_CORE(CPU) (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2)) @@ -785,7 +851,6 @@ * @{ */ - /* Peripheral Control functions **********************************************/ uint32_t HAL_PWREx_GetVoltageRange(void); HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); @@ -799,8 +864,10 @@ void HAL_PWREx_EnableInternalWakeUpLine(void); void HAL_PWREx_DisableInternalWakeUpLine(void); +#if defined(PWR_CR5_SMPSEN) void HAL_PWREx_EnableBORH_SMPSBypassIT(void); void HAL_PWREx_DisableBORH_SMPSBypassIT(void); +#endif void HAL_PWREx_EnableRFPhaseIT(void); void HAL_PWREx_DisableRFPhaseIT(void); void HAL_PWREx_EnableBLEActivityIT(void); @@ -820,8 +887,10 @@ void HAL_PWREx_EnablePullUpPullDownConfig(void); void HAL_PWREx_DisablePullUpPullDownConfig(void); +#if defined(PWR_CR5_SMPSEN) void HAL_PWREx_SetBORConfig(uint32_t BORConfiguration); uint32_t HAL_PWREx_GetBORConfig(void); +#endif void HAL_PWREx_EnableSRAMRetention(void); void HAL_PWREx_DisableSRAMRetention(void); @@ -829,17 +898,21 @@ void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode); void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode); +#if defined(PWR_CR2_PVME1) void HAL_PWREx_EnablePVM1(void); void HAL_PWREx_DisablePVM1(void); +#endif void HAL_PWREx_EnablePVM3(void); void HAL_PWREx_DisablePVM3(void); HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); +#if defined(PWR_CR5_SMPSEN) HAL_StatusTypeDef HAL_PWREx_ConfigSMPS(PWR_SMPSTypeDef *sConfigSMPS); void HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode); uint32_t HAL_PWREx_SMPS_GetEffectiveMode(void); +#endif /* WakeUp pins configuration functions ****************************************/ void HAL_PWREx_EnableWakeUpPin(uint32_t WakeUpPinPolarity, uint32_t wakeupTarget); @@ -857,7 +930,9 @@ void HAL_PWREx_PVD_PVM_IRQHandler(void); +#if defined(PWR_CR2_PVME1) void HAL_PWREx_PVM1Callback(void); +#endif void HAL_PWREx_PVM3Callback(void); /**
diff --git a/Inc/stm32wbxx_hal_qspi.h b/Inc/stm32wbxx_hal_qspi.h index e74bd61..01ef0e0 100644 --- a/Inc/stm32wbxx_hal_qspi.h +++ b/Inc/stm32wbxx_hal_qspi.h
@@ -27,7 +27,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32wbxx_hal_def.h" -#if defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) +#if defined(QUADSPI) /** @addtogroup STM32WBxx_HAL_Driver * @{ @@ -408,7 +408,7 @@ * @brief QSPI Timeout definition * @{ */ -#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */ +#define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */ /** * @} */
diff --git a/Inc/stm32wbxx_hal_rcc.h b/Inc/stm32wbxx_hal_rcc.h index ad0da9f..ba03291 100644 --- a/Inc/stm32wbxx_hal_rcc.h +++ b/Inc/stm32wbxx_hal_rcc.h
@@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - * <h2><center>© Copyright (c) 2019 STMicroelectronics. + * <h2><center>© Copyright (c) 2019 STMicroelectronics. * All rights reserved.</center></h2> * * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -101,7 +101,14 @@ ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ ((__SOURCE__) == RCC_PLLSOURCE_HSE)) -#define IS_RCC_PLLM_VALUE(__VALUE__) ((__VALUE__) <= RCC_PLLM_DIV8) +#define IS_RCC_PLLM_VALUE(__VALUE__) (((__VALUE__) == RCC_PLLM_DIV1) || \ + ((__VALUE__) == RCC_PLLM_DIV2) || \ + ((__VALUE__) == RCC_PLLM_DIV3) || \ + ((__VALUE__) == RCC_PLLM_DIV4) || \ + ((__VALUE__) == RCC_PLLM_DIV5) || \ + ((__VALUE__) == RCC_PLLM_DIV6) || \ + ((__VALUE__) == RCC_PLLM_DIV7) || \ + ((__VALUE__) == RCC_PLLM_DIV8)) #define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) @@ -111,12 +118,12 @@ #define IS_RCC_PLLR_VALUE(__VALUE__) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8)) +#if defined(SAI1) #define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_ADCCLK) == RCC_PLLSAI1_ADCCLK) || \ (((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \ - (((__VALUE__) & RCC_PLLSAI1_USBCLK) == RCC_PLLSAI1_USBCLK) || \ - (((__VALUE__) & RCC_PLLSAI1_RNGCLK) == RCC_PLLSAI1_RNGCLK)) && \ - (((__VALUE__) & ~(RCC_PLLSAI1_ADCCLK|RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_USBCLK|RCC_PLLSAI1_RNGCLK)) == 0U)) - + (((__VALUE__) & RCC_PLLSAI1_USBCLK) == RCC_PLLSAI1_USBCLK)) && \ + (((__VALUE__) & ~(RCC_PLLSAI1_ADCCLK|RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_USBCLK)) == 0U)) +#endif #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ ((__RANGE__) == RCC_MSIRANGE_1) || \ ((__RANGE__) == RCC_MSIRANGE_2) || \ @@ -204,7 +211,7 @@ typedef struct { uint32_t PLLState; /*!< The new state of the PLL. - This parameter can be a value of @ref RCC_PLL_Config */ + This parameter must be a value of @ref RCC_PLL_Config */ uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. This parameter must be a value of @ref RCC_PLL_Clock_Source */ @@ -233,7 +240,7 @@ typedef struct { uint32_t OscillatorType; /*!< The oscillators to be configured. - This parameter can be a value of @ref RCC_Oscillator_Type */ + This parameter can be a combination of @ref RCC_Oscillator_Type */ uint32_t HSEState; /*!< The new state of the HSE. This parameter can be a value of @ref RCC_HSE_Config */ @@ -269,7 +276,7 @@ } RCC_OscInitTypeDef; /** - * @brief RCC System, AHB and APB busses clock configuration structure definition + * @brief RCC System, AHB and APB buses clock configuration structure definition */ typedef struct { @@ -499,22 +506,25 @@ #define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */ #define RCC_PLL_USBCLK RCC_PLLCFGR_PLLQEN /*!< PLLUSBCLK selection from main PLL */ #define RCC_PLL_RNGCLK RCC_PLLCFGR_PLLQEN /*!< PLLRNGCLK selection from main PLL */ +#if defined(SAI1) #define RCC_PLL_SAI1CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI1CLK selection from main PLL */ +#endif #define RCC_PLL_ADCCLK RCC_PLLCFGR_PLLPEN /*!< PLLADCCLK selection from main PLL */ /** * @} */ +#if defined(SAI1) /** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output * @{ */ #define RCC_PLLSAI1_ADCCLK RCC_PLLSAI1CFGR_PLLREN /*!< PLLADCCLK selection from PLLSAI1 */ #define RCC_PLLSAI1_USBCLK RCC_PLLSAI1CFGR_PLLQEN /*!< USBCLK selection from PLLSAI1 */ -#define RCC_PLLSAI1_RNGCLK RCC_PLLSAI1CFGR_PLLQEN /*!< RNGCLK selection from PLLSAI1 */ #define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLPEN /*!< PLLSAI1CLK selection from PLLSAI1 */ /** * @} */ +#endif /** @defgroup RCC_MSI_Clock_Range MSI Clock Range * @{ @@ -693,7 +703,9 @@ #define RCC_IT_HSIRDY LL_RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ #define RCC_IT_HSERDY LL_RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ #define RCC_IT_PLLRDY LL_RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ +#if defined(SAI1) #define RCC_IT_PLLSAI1RDY LL_RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */ +#endif #define RCC_IT_HSECSS LL_RCC_CIFR_CSSF /*!< HSE Clock Security System Interrupt flag */ #define RCC_IT_LSECSS LL_RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ #define RCC_IT_HSI48RDY LL_RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ @@ -780,13 +792,17 @@ */ #define __HAL_RCC_DMA1_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1) +#if defined(DMA2) #define __HAL_RCC_DMA2_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA2) +#endif #define __HAL_RCC_DMAMUX1_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1) #define __HAL_RCC_CRC_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC) #define __HAL_RCC_TSC_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_TSC) #define __HAL_RCC_DMA1_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMA1) +#if defined(DMA2) #define __HAL_RCC_DMA2_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMA2) +#endif #define __HAL_RCC_DMAMUX1_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1) #define __HAL_RCC_CRC_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_CRC) #define __HAL_RCC_TSC_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_TSC) @@ -806,22 +822,31 @@ #define __HAL_RCC_GPIOA_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA) #define __HAL_RCC_GPIOB_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB) #define __HAL_RCC_GPIOC_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC) + +#if defined(GPIOD) #define __HAL_RCC_GPIOD_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOD) +#endif #define __HAL_RCC_GPIOE_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOE) #define __HAL_RCC_GPIOH_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOH) #define __HAL_RCC_ADC_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADC) +#if defined(AES1) #define __HAL_RCC_AES1_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_AES1) - +#endif #define __HAL_RCC_GPIOA_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOA) #define __HAL_RCC_GPIOB_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOB) #define __HAL_RCC_GPIOC_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOC) +#if defined(GPIOD) #define __HAL_RCC_GPIOD_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOD) +#endif #define __HAL_RCC_GPIOE_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOE) #define __HAL_RCC_GPIOH_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOH) #define __HAL_RCC_ADC_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_ADC) + +#if defined(AES1) #define __HAL_RCC_AES1_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_AES1) +#endif /** * @} @@ -835,7 +860,9 @@ * @{ */ +#if defined(QUADSPI) #define __HAL_RCC_QUADSPI_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_QUADSPI) +#endif #define __HAL_RCC_PKA_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PKA) #define __HAL_RCC_AES2_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_AES2) #define __HAL_RCC_RNG_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_RNG) @@ -843,7 +870,9 @@ #define __HAL_RCC_IPCC_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC) #define __HAL_RCC_FLASH_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_FLASH) +#if defined(QUADSPI) #define __HAL_RCC_QUADSPI_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_QUADSPI) +#endif #define __HAL_RCC_PKA_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_PKA) #define __HAL_RCC_AES2_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_AES2) #define __HAL_RCC_RNG_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_RNG) @@ -866,29 +895,52 @@ #define __HAL_RCC_RTCAPB_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_RTCAPB) #define __HAL_RCC_WWDG_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_WWDG) #define __HAL_RCC_TIM2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2) +#if defined(LCD) #define __HAL_RCC_LCD_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LCD) +#endif +#if defined(SPI2) #define __HAL_RCC_SPI2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2) +#endif #define __HAL_RCC_I2C1_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C1) +#if defined(I2C3) #define __HAL_RCC_I2C3_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C3) +#endif +#if defined(CRS) #define __HAL_RCC_CRS_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_CRS) +#endif +#if defined(USB) #define __HAL_RCC_USB_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USB) +#endif #define __HAL_RCC_LPTIM1_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPTIM1) #define __HAL_RCC_LPTIM2_CLK_ENABLE() LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPTIM2) +#if defined(LPUART1) #define __HAL_RCC_LPUART1_CLK_ENABLE() LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPUART1) +#endif #define __HAL_RCC_RTCAPB_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_RTCAPB) #define __HAL_RCC_TIM2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM2) +#if defined(LCD) #define __HAL_RCC_LCD_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_LCD) +#endif +#if defined(SPI2) #define __HAL_RCC_SPI2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_SPI2) +#endif #define __HAL_RCC_I2C1_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C1) +#if defined(I2C3) #define __HAL_RCC_I2C3_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C3) +#endif +#if defined(CRS) #define __HAL_RCC_CRS_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_CRS) +#endif +#if defined(USB) #define __HAL_RCC_USB_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_USB) +#endif #define __HAL_RCC_LPTIM1_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_LPTIM1) #define __HAL_RCC_LPTIM2_CLK_DISABLE() LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_LPTIM2) +#if defined(LPUART1) #define __HAL_RCC_LPUART1_CLK_DISABLE() LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_LPUART1) - +#endif /** * @} @@ -907,14 +959,18 @@ #define __HAL_RCC_USART1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1) #define __HAL_RCC_TIM16_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM16) #define __HAL_RCC_TIM17_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM17) +#if defined(SAI1) #define __HAL_RCC_SAI1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SAI1) +#endif #define __HAL_RCC_TIM1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM1) #define __HAL_RCC_SPI1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SPI1) #define __HAL_RCC_USART1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_USART1) #define __HAL_RCC_TIM16_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM16) #define __HAL_RCC_TIM17_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM17) +#if defined(SAI1) #define __HAL_RCC_SAI1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SAI1) +#endif /** * @} @@ -929,13 +985,17 @@ */ #define __HAL_RCC_DMA1_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA1) +#if defined(DMA2) #define __HAL_RCC_DMA2_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA2) +#endif #define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMAMUX1) #define __HAL_RCC_CRC_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_CRC) #define __HAL_RCC_TSC_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_TSC) #define __HAL_RCC_DMA1_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA1)) +#if defined(DMA2) #define __HAL_RCC_DMA2_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA2)) +#endif #define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMAMUX1)) #define __HAL_RCC_CRC_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_CRC)) #define __HAL_RCC_TSC_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_TSC)) @@ -955,22 +1015,28 @@ #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOA) #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOB) #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOC) +#if defined(GPIOD) #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOD) +#endif #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOE) #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOH) #define __HAL_RCC_ADC_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADC) +#if defined(AES1) #define __HAL_RCC_AES1_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_AES1) +#endif #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOA)) #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOB)) #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOC)) +#if defined(GPIOD) #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOD)) +#endif #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOE)) #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOH)) #define __HAL_RCC_ADC_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADC)) +#if defined(AES1) #define __HAL_RCC_AES1_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_AES1)) - - +#endif /** * @} @@ -984,7 +1050,9 @@ * @{ */ +#if defined(QUADSPI) #define __HAL_RCC_QUADSPI_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_QUADSPI) +#endif #define __HAL_RCC_PKA_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PKA) #define __HAL_RCC_AES2_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_AES2) #define __HAL_RCC_RNG_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_RNG) @@ -992,7 +1060,9 @@ #define __HAL_RCC_IPCC_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_IPCC) #define __HAL_RCC_FLASH_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_FLASH) +#if defined(QUADSPI) #define __HAL_RCC_QUADSPI_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_QUADSPI)) +#endif #define __HAL_RCC_PKA_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PKA)) #define __HAL_RCC_AES2_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_AES2)) #define __HAL_RCC_RNG_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_RNG)) @@ -1015,30 +1085,54 @@ #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_RTCAPB) #define __HAL_RCC_WWDG_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_WWDG) #define __HAL_RCC_TIM2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM2) +#if defined(LCD) #define __HAL_RCC_LCD_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LCD) +#endif +#if defined(SPI2) #define __HAL_RCC_SPI2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI2) +#endif #define __HAL_RCC_I2C1_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C1) +#if defined(I2C3) #define __HAL_RCC_I2C3_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C3) +#endif +#if defined(CRS) #define __HAL_RCC_CRS_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_CRS) +#endif +#if defined(USB) #define __HAL_RCC_USB_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USB) +#endif #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LPTIM1) #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPTIM2) +#if defined(LPUART1) #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPUART1) +#endif #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_RTCAPB)) #define __HAL_RCC_WWDG_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_WWDG)) #define __HAL_RCC_TIM2_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM2)) +#if defined(LCD) #define __HAL_RCC_LCD_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LCD)) +#endif +#if defined(SPI2) #define __HAL_RCC_SPI2_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI2)) +#endif #define __HAL_RCC_I2C1_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C1)) +#if defined(I2C3) #define __HAL_RCC_I2C3_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C3)) +#endif +#if defined(CRS) #define __HAL_RCC_CRS_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_CRS)) +#endif +#if defined(USB) #define __HAL_RCC_USB_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USB)) +#endif #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LPTIM1)) #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() !(LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPTIM2)) +#if defined(LPUART1) #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() !(LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPUART1)) +#endif /** * @} @@ -1057,7 +1151,9 @@ #define __HAL_RCC_USART1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1) #define __HAL_RCC_TIM16_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM16) #define __HAL_RCC_TIM17_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM17) +#if defined(SAI1) #define __HAL_RCC_SAI1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SAI1) +#endif #define __HAL_RCC_TIM1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM1)) @@ -1065,7 +1161,9 @@ #define __HAL_RCC_USART1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1)) #define __HAL_RCC_TIM16_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM16)) #define __HAL_RCC_TIM17_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM17)) +#if defined(SAI1) #define __HAL_RCC_SAI1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SAI1)) +#endif /** * @} @@ -1080,14 +1178,18 @@ */ #define __HAL_RCC_C2DMA1_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1) +#if defined(DMA2) #define __HAL_RCC_C2DMA2_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMA2) +#endif #define __HAL_RCC_C2DMAMUX1_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) #define __HAL_RCC_C2SRAM1_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1) #define __HAL_RCC_C2CRC_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_CRC) #define __HAL_RCC_C2TSC_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_TSC) #define __HAL_RCC_C2DMA1_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1) +#if defined(DMA2) #define __HAL_RCC_C2DMA2_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMA2) +#endif #define __HAL_RCC_C2DMAMUX1_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) #define __HAL_RCC_C2SRAM1_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1) #define __HAL_RCC_C2CRC_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_CRC) @@ -1108,20 +1210,28 @@ #define __HAL_RCC_C2GPIOA_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA) #define __HAL_RCC_C2GPIOB_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB) #define __HAL_RCC_C2GPIOC_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC) +#if defined(GPIOD) #define __HAL_RCC_C2GPIOD_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD) +#endif #define __HAL_RCC_C2GPIOE_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE) #define __HAL_RCC_C2GPIOH_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH) #define __HAL_RCC_C2ADC_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_ADC) +#if defined(GPIOD) #define __HAL_RCC_C2AES1_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_AES1) +#endif #define __HAL_RCC_C2GPIOA_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA) #define __HAL_RCC_C2GPIOB_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB) #define __HAL_RCC_C2GPIOC_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC) +#if defined(GPIOD) #define __HAL_RCC_C2GPIOD_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD) +#endif #define __HAL_RCC_C2GPIOE_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE) #define __HAL_RCC_C2GPIOH_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH) #define __HAL_RCC_C2ADC_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_ADC) +#if defined(AES1) #define __HAL_RCC_C2AES1_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_AES1) +#endif /** * @} @@ -1163,29 +1273,53 @@ #define __HAL_RCC_C2RTCAPB_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB) #define __HAL_RCC_C2TIM2_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_TIM2) +#if defined(LCD) #define __HAL_RCC_C2LCD_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_LCD) +#endif +#if defined(SPI2) #define __HAL_RCC_C2SPI2_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_SPI2) +#endif #define __HAL_RCC_C2I2C1_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_I2C1) +#if defined(I2C3) #define __HAL_RCC_C2I2C3_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_I2C3) +#endif +#if defined(CRS) #define __HAL_RCC_C2CRS_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_CRS) +#endif +#if defined(USB) #define __HAL_RCC_C2USB_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_USB) +#endif #define __HAL_RCC_C2LPTIM1_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1) #define __HAL_RCC_C2LPTIM2_CLK_ENABLE() LL_C2_APB1_GRP2_EnableClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2) +#if defined(LPUART1) #define __HAL_RCC_C2LPUART1_CLK_ENABLE() LL_C2_APB1_GRP2_EnableClock(LL_C2_APB1_GRP2_PERIPH_LPUART1) +#endif #define __HAL_RCC_C2RTCAPB_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB) #define __HAL_RCC_C2TIM2_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_TIM2) +#if defined(LCD) #define __HAL_RCC_C2LCD_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_LCD) +#endif +#if defined(SPI2) #define __HAL_RCC_C2SPI2_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_SPI2) +#endif #define __HAL_RCC_C2I2C1_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_I2C1) +#if defined(I2C3) #define __HAL_RCC_C2I2C3_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_I2C3) +#endif +#if defined(CRS) #define __HAL_RCC_C2CRS_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_CRS) +#endif +#if defined(USB) #define __HAL_RCC_C2USB_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_USB) +#endif #define __HAL_RCC_C2LPTIM1_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1) #define __HAL_RCC_C2LPTIM2_CLK_DISABLE() LL_C2_APB1_GRP2_DisableClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2) +#if defined(LPUART1) #define __HAL_RCC_C2LPUART1_CLK_DISABLE() LL_C2_APB1_GRP2_DisableClock(LL_C2_APB1_GRP2_PERIPH_LPUART1) +#endif /** * @} @@ -1204,14 +1338,18 @@ #define __HAL_RCC_C2USART1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_USART1) #define __HAL_RCC_C2TIM16_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM16) #define __HAL_RCC_C2TIM17_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM17) +#if defined(SAI1) #define __HAL_RCC_C2SAI1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_SAI1) +#endif #define __HAL_RCC_C2TIM1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM1) #define __HAL_RCC_C2SPI1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_SPI1) #define __HAL_RCC_C2USART1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_USART1) #define __HAL_RCC_C2TIM16_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM16) #define __HAL_RCC_C2TIM17_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM17) +#if defined(SAI1) #define __HAL_RCC_C2SAI1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_SAI1) +#endif /** * @} @@ -1245,14 +1383,18 @@ */ #define __HAL_RCC_C2DMA1_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA1) +#if defined(DMA2) #define __HAL_RCC_C2DMA2_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA2) +#endif #define __HAL_RCC_C2DMAMUX1_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) #define __HAL_RCC_C2SRAM1_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1) #define __HAL_RCC_C2CRC_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_CRC) #define __HAL_RCC_C2TSC_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_TSC) #define __HAL_RCC_C2DMA1_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA1)) +#if defined(DMA2) #define __HAL_RCC_C2DMA2_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA2)) +#endif #define __HAL_RCC_C2DMAMUX1_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)) #define __HAL_RCC_C2SRAM1_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1)) #define __HAL_RCC_C2CRC_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_CRC)) @@ -1273,20 +1415,28 @@ #define __HAL_RCC_C2GPIOA_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA) #define __HAL_RCC_C2GPIOB_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB) #define __HAL_RCC_C2GPIOC_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC) +#if defined(GPIOD) #define __HAL_RCC_C2GPIOD_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD) +#endif #define __HAL_RCC_C2GPIOE_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE) #define __HAL_RCC_C2GPIOH_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH) #define __HAL_RCC_C2ADC_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_ADC) +#if defined(AES1) #define __HAL_RCC_C2AES1_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_AES1) +#endif #define __HAL_RCC_C2GPIOA_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA)) #define __HAL_RCC_C2GPIOB_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB)) #define __HAL_RCC_C2GPIOC_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC)) +#if defined(GPIOD) #define __HAL_RCC_C2GPIOD_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD)) +#endif #define __HAL_RCC_C2GPIOE_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE)) #define __HAL_RCC_C2GPIOH_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH)) #define __HAL_RCC_C2ADC_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_ADC)) +#if defined(AES1) #define __HAL_RCC_C2AES1_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_AES1)) +#endif /** * @} @@ -1328,29 +1478,53 @@ #define __HAL_RCC_C2RTCAPB_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB) #define __HAL_RCC_C2TIM2_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_TIM2) +#if defined(LCD) #define __HAL_RCC_C2LCD_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LCD) +#endif +#if defined(SPI2) #define __HAL_RCC_C2SPI2_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_SPI2) +#endif #define __HAL_RCC_C2I2C1_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C1) +#if defined(I2C3) #define __HAL_RCC_C2I2C3_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C3) +#endif +#if defined(CRS) #define __HAL_RCC_C2CRS_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_CRS) +#endif +#if defined(USB) #define __HAL_RCC_C2USB_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_USB) +#endif #define __HAL_RCC_C2LPTIM1_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1) #define __HAL_RCC_C2LPTIM2_IS_CLK_ENABLED() LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2) +#if defined(LPUART1) #define __HAL_RCC_C2LPUART1_IS_CLK_ENABLED() LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPUART1) +#endif #define __HAL_RCC_C2RTCAPB_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB)) #define __HAL_RCC_C2TIM2_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_TIM2)) +#if defined(LCD) #define __HAL_RCC_C2LCD_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LCD)) +#endif +#if defined(SPI2) #define __HAL_RCC_C2SPI2_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_SPI2)) +#endif #define __HAL_RCC_C2I2C1_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C1)) +#if defined(I2C3) #define __HAL_RCC_C2I2C3_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C3)) +#endif +#if defined(CRS) #define __HAL_RCC_C2CRS_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_CRS)) +#endif +#if defined(USB) #define __HAL_RCC_C2USB_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_USB)) +#endif #define __HAL_RCC_C2LPTIM1_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1)) #define __HAL_RCC_C2LPTIM2_IS_CLK_DISABLED() !(LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2)) +#if defined(LPUART1) #define __HAL_RCC_C2LPUART1_IS_CLK_DISABLED() !(LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1)) +#endif /** * @} @@ -1369,14 +1543,18 @@ #define __HAL_RCC_C2USART1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_USART1) #define __HAL_RCC_C2TIM16_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM16) #define __HAL_RCC_C2TIM17_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM17) +#if defined(SAI1) #define __HAL_RCC_C2SAI1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SAI1) +#endif #define __HAL_RCC_C2TIM1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM1)) #define __HAL_RCC_C2SPI1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SPI1)) #define __HAL_RCC_C2USART1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_USART1)) #define __HAL_RCC_C2TIM16_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM16)) #define __HAL_RCC_C2TIM17_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM17)) +#if defined(SAI1) #define __HAL_RCC_C2SAI1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SAI1)) +#endif /** * @} @@ -1408,7 +1586,9 @@ */ #define __HAL_RCC_AHB1_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_ALL) #define __HAL_RCC_DMA1_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1) +#if defined(DMA2) #define __HAL_RCC_DMA2_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2) +#endif #define __HAL_RCC_DMAMUX1_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMAMUX1) #define __HAL_RCC_CRC_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC) #define __HAL_RCC_TSC_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_TSC) @@ -1416,7 +1596,9 @@ #define __HAL_RCC_AHB1_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ALL) #define __HAL_RCC_DMA1_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1) +#if defined(DMA2) #define __HAL_RCC_DMA2_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2) +#endif #define __HAL_RCC_DMAMUX1_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMAMUX1) #define __HAL_RCC_CRC_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC) #define __HAL_RCC_TSC_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_TSC) @@ -1434,21 +1616,29 @@ #define __HAL_RCC_GPIOA_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOA) #define __HAL_RCC_GPIOB_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOB) #define __HAL_RCC_GPIOC_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOC) +#if defined(GPIOD) #define __HAL_RCC_GPIOD_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOD) +#endif #define __HAL_RCC_GPIOE_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOE) #define __HAL_RCC_GPIOH_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOH) #define __HAL_RCC_ADC_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC) +#if defined(AES1) #define __HAL_RCC_AES1_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_AES1) +#endif #define __HAL_RCC_AHB2_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ALL) #define __HAL_RCC_GPIOA_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOA) #define __HAL_RCC_GPIOB_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOB) #define __HAL_RCC_GPIOC_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOC) +#if defined(GPIOD) #define __HAL_RCC_GPIOD_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOD) +#endif #define __HAL_RCC_GPIOE_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOE) #define __HAL_RCC_GPIOH_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOH) #define __HAL_RCC_ADC_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC) +#if defined(AES1) #define __HAL_RCC_AES1_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_AES1) +#endif /** * @} @@ -1459,7 +1649,9 @@ * @{ */ #define __HAL_RCC_AHB3_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ALL) +#if defined(QUADSPI) #define __HAL_RCC_QUADSPI_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_QUADSPI) +#endif #define __HAL_RCC_PKA_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_PKA) #define __HAL_RCC_AES2_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_AES2) #define __HAL_RCC_RNG_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_RNG) @@ -1468,7 +1660,9 @@ #define __HAL_RCC_FLASH_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_FLASH) #define __HAL_RCC_AHB3_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ALL) +#if defined(QUADSPI) #define __HAL_RCC_QUADSPI_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_QUADSPI) +#endif #define __HAL_RCC_PKA_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_PKA) #define __HAL_RCC_AES2_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_AES2) #define __HAL_RCC_RNG_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_RNG) @@ -1486,16 +1680,28 @@ #define __HAL_RCC_APB1L_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_ALL) #define __HAL_RCC_TIM2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2) +#if defined(LCD) #define __HAL_RCC_LCD_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LCD) +#endif +#if defined(SPI2) #define __HAL_RCC_SPI2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2) +#endif #define __HAL_RCC_I2C1_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1) +#if defined(I2C3) #define __HAL_RCC_I2C3_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3) +#endif +#if defined(CRS) #define __HAL_RCC_CRS_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_CRS) +#endif +#if defined(USB) #define __HAL_RCC_USB_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USB) +#endif #define __HAL_RCC_LPTIM1_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1) #define __HAL_RCC_APB1H_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_ALL) +#if defined(LPUART1) #define __HAL_RCC_LPUART1_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPUART1) +#endif #define __HAL_RCC_LPTIM2_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2) #define __HAL_RCC_APB1_FORCE_RESET() do { \ @@ -1505,16 +1711,28 @@ #define __HAL_RCC_APB1L_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_ALL) #define __HAL_RCC_TIM2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2) +#if defined(LCD) #define __HAL_RCC_LCD_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LCD) +#endif +#if defined(SPI2) #define __HAL_RCC_SPI2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2) +#endif #define __HAL_RCC_I2C1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1) +#if defined(I2C3) #define __HAL_RCC_I2C3_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3) +#endif +#if defined(CRS) #define __HAL_RCC_CRS_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_CRS) +#endif +#if defined(USB) #define __HAL_RCC_USB_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USB) +#endif #define __HAL_RCC_LPTIM1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1) #define __HAL_RCC_APB1H_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_ALL) +#if defined(LPUART1) #define __HAL_RCC_LPUART1_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPUART1) +#endif #define __HAL_RCC_LPTIM2_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2) #define __HAL_RCC_APB1_RELEASE_RESET() do { \ @@ -1535,7 +1753,9 @@ #define __HAL_RCC_USART1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1) #define __HAL_RCC_TIM16_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16) #define __HAL_RCC_TIM17_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17) +#if defined(SAI1) #define __HAL_RCC_SAI1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SAI1) +#endif #define __HAL_RCC_APB2_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ALL) #define __HAL_RCC_TIM1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1) @@ -1543,7 +1763,9 @@ #define __HAL_RCC_USART1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1) #define __HAL_RCC_TIM16_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16) #define __HAL_RCC_TIM17_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17) +#if defined(SAI1) #define __HAL_RCC_SAI1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SAI1) +#endif /** * @} */ @@ -1571,28 +1793,36 @@ * @{ */ #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMA1) +#if defined(DMA2) #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMA2) +#endif #define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1) #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_SRAM1) #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_CRC) #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_TSC) #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMA1) +#if defined(DMA2) #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMA2) +#endif #define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1) #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_SRAM1) #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_CRC) #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_TSC) #define __HAL_RCC_C2DMA1_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA1) +#if defined(DMA2) #define __HAL_RCC_C2DMA2_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA2) +#endif #define __HAL_RCC_C2DMAMUX1_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) #define __HAL_RCC_C2SRAM1_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_SRAM1) #define __HAL_RCC_C2CRC_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_CRC) #define __HAL_RCC_C2TSC_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_TSC) #define __HAL_RCC_C2DMA1_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA1) +#if defined(DMA2) #define __HAL_RCC_C2DMA2_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA2) +#endif #define __HAL_RCC_C2DMAMUX1_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) #define __HAL_RCC_C2SRAM1_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_SRAM1) @@ -1614,38 +1844,54 @@ #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOA) #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOB) #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOC) +#if defined(GPIOD) #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOD) +#endif #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOE) #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH) #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_ADC) +#if defined(AES1) #define __HAL_RCC_AES1_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_AES1) +#endif #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOA) #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOB) #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOC) +#if defined(GPIOD) #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOD) +#endif #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOE) #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH) #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_ADC) +#if defined(AES1) #define __HAL_RCC_AES1_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_AES1) +#endif #define __HAL_RCC_C2GPIOA_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOA) #define __HAL_RCC_C2GPIOB_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOB) #define __HAL_RCC_C2GPIOC_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOC) +#if defined(GPIOD) #define __HAL_RCC_C2GPIOD_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOD) +#endif #define __HAL_RCC_C2GPIOE_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOE) #define __HAL_RCC_C2GPIOH_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH) #define __HAL_RCC_C2ADC_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_ADC) +#if defined(AES1) #define __HAL_RCC_C2AES1_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_AES1) +#endif #define __HAL_RCC_C2GPIOA_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOA) #define __HAL_RCC_C2GPIOB_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOB) #define __HAL_RCC_C2GPIOC_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOC) +#if defined(GPIOD) #define __HAL_RCC_C2GPIOD_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOD) +#endif #define __HAL_RCC_C2GPIOE_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOE) #define __HAL_RCC_C2GPIOH_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH) #define __HAL_RCC_C2ADC_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_ADC) +#if defined(AES1) #define __HAL_RCC_C2AES1_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_AES1) +#endif /** * @} @@ -1659,14 +1905,18 @@ * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ +#if defined(QUADSPI) #define __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_QUADSPI) +#endif #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_PKA) #define __HAL_RCC_AES2_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_AES2) #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_RNG) #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_SRAM2) #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_FLASH) +#if defined(QUADSPI) #define __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_QUADSPI) +#endif #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_PKA) #define __HAL_RCC_AES2_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_AES2) #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_RNG) @@ -1698,53 +1948,101 @@ * @{ */ #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_TIM2) +#if defined(LCD) #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_LCD) +#endif #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_RTCAPB) #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_WWDG) +#if defined(SPI2) #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_SPI2) +#endif #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_I2C1) +#if defined(I2C3) #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_I2C3) +#endif +#if defined(CRS) #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_CRS) +#endif +#if defined(USB) #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_USB) +#endif #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_LPTIM1) +#if defined(LPUART1) #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() LL_APB1_GRP2_EnableClockSleep(LL_APB1_GRP2_PERIPH_LPUART1) +#endif #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() LL_APB1_GRP2_EnableClockSleep(LL_APB1_GRP2_PERIPH_LPTIM2) #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_TIM2) +#if defined(LCD) #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_LCD) +#endif #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_RTCAPB) #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_WWDG) +#if defined(SPI2) #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_SPI2) +#endif #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_I2C1) +#if defined(I2C3) #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_I2C3) +#endif +#if defined(CRS) #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_CRS) +#endif +#if defined(USB) #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_USB) +#endif #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_LPTIM1) +#if defined(LPUART1) #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() LL_APB1_GRP2_DisableClockSleep(LL_APB1_GRP2_PERIPH_LPUART1) +#endif #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() LL_APB1_GRP2_DisableClockSleep(LL_APB1_GRP2_PERIPH_LPTIM2) #define __HAL_RCC_C2TIM2_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_TIM2) +#if defined(LCD) #define __HAL_RCC_C2LCD_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_LCD) +#endif #define __HAL_RCC_C2RTCAPB_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_RTCAPB) +#if defined(SPI2) #define __HAL_RCC_C2SPI2_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_SPI2) +#endif #define __HAL_RCC_C2I2C1_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C1) +#if defined(I2C3) #define __HAL_RCC_C2I2C3_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C3) +#endif +#if defined(CRS) #define __HAL_RCC_C2CRS_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_CRS) +#endif +#if defined(USB) #define __HAL_RCC_C2USB_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_USB) +#endif #define __HAL_RCC_C2LPTIM1_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_LPTIM1) +#if defined(LPUART1) #define __HAL_RCC_C2LPUART1_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP2_EnableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPUART1) +#endif #define __HAL_RCC_C2LPTIM2_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP2_EnableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM2) #define __HAL_RCC_C2TIM2_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_TIM2) +#if defined(LCD) #define __HAL_RCC_C2LCD_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_LCD) +#endif #define __HAL_RCC_C2RTCAPB_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_RTCAPB) +#if defined(SPI2) #define __HAL_RCC_C2SPI2_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_SPI2) +#endif #define __HAL_RCC_C2I2C1_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C1) +#if defined(I2C3) #define __HAL_RCC_C2I2C3_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C3) +#endif +#if defined(CRS) #define __HAL_RCC_C2CRS_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_CRS) +#endif +#if defined(USB) #define __HAL_RCC_C2USB_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_USB) +#endif #define __HAL_RCC_C2LPTIM1_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_LPTIM1) +#if defined(LPUART1) #define __HAL_RCC_C2LPUART1_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP2_DisableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPUART1) +#endif #define __HAL_RCC_C2LPTIM2_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP2_DisableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM2) /** @@ -1764,28 +2062,36 @@ #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_USART1) #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM16) #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM17) +#if defined(SAI1) #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_SAI1) +#endif #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM1) #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_SPI1) #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_USART1) #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM16) #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM17) +#if defined(SAI1) #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_SAI1) +#endif #define __HAL_RCC_C2TIM1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1) #define __HAL_RCC_C2SPI1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1) #define __HAL_RCC_C2USART1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1) #define __HAL_RCC_C2TIM16_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM16) #define __HAL_RCC_C2TIM17_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM17) +#if defined(SAI1) #define __HAL_RCC_C2SAI1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_SAI1) +#endif #define __HAL_RCC_C2TIM1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1) #define __HAL_RCC_C2SPI1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1) #define __HAL_RCC_C2USART1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1) #define __HAL_RCC_C2TIM16_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM16) #define __HAL_RCC_C2TIM17_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM17) +#if defined(SAI1) #define __HAL_RCC_C2SAI1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_SAI1) +#endif /** * @} */ @@ -1799,28 +2105,36 @@ * @{ */ #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET) +#if defined(DMA2) #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET) +#endif #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != RESET) #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET) #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET) #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET) #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET) +#if defined(DMA2) #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET) +#endif #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == RESET) #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET) #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET) #define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET) #define __HAL_RCC_C2DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA1SMEN) != RESET) +#if defined(DMA2) #define __HAL_RCC_C2DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA2SMEN) != RESET) +#endif #define __HAL_RCC_C2DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMAMUX1SMEN) != RESET) #define __HAL_RCC_C2SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_SRAM1SMEN) != RESET) #define __HAL_RCC_C2CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_CRCSMEN) != RESET) #define __HAL_RCC_C2TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_TSCSMEN) != RESET) #define __HAL_RCC_C2DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA1SMEN) == RESET) +#if defined(DMA2) #define __HAL_RCC_C2DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA2SMEN) == RESET) +#endif #define __HAL_RCC_C2DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMAMUX1SMEN) == RESET) #define __HAL_RCC_C2SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_SRAM1SMEN) == RESET) #define __HAL_RCC_C2CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_CRCSMEN) == RESET) @@ -1840,38 +2154,54 @@ #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET) #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET) #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET) +#if defined(GPIOD) #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET) +#endif #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET) #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET) #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET) +#if defined(AES1) #define __HAL_RCC_AES1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AES1SMEN) != RESET) +#endif #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET) #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET) #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET) +#if defined(GPIOD) #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET) +#endif #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET) #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET) #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET) +#if defined(AES1) #define __HAL_RCC_AES1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AES1SMEN) == RESET) +#endif #define __HAL_RCC_C2GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOASMEN) != RESET) #define __HAL_RCC_C2GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOBSMEN) != RESET) #define __HAL_RCC_C2GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOCSMEN) != RESET) +#if defined(GPIOD) #define __HAL_RCC_C2GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIODSMEN) != RESET) +#endif #define __HAL_RCC_C2GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOESMEN) != RESET) #define __HAL_RCC_C2GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOHSMEN) != RESET) #define __HAL_RCC_C2ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_ADCSMEN) != RESET) +#if defined(AES1) #define __HAL_RCC_C2AES1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_AES1SMEN) != RESET) +#endif #define __HAL_RCC_C2GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOASMEN) == RESET) #define __HAL_RCC_C2GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOBSMEN) == RESET) #define __HAL_RCC_C2GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOCSMEN) == RESET) +#if defined(GPIOD) #define __HAL_RCC_C2GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIODSMEN) == RESET) +#endif #define __HAL_RCC_C2GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOESMEN) == RESET) #define __HAL_RCC_C2GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOHSMEN) == RESET) #define __HAL_RCC_C2ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_ADCSMEN) == RESET) +#if defined(AES1) #define __HAL_RCC_C2AES1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_AES1SMEN) == RESET) +#endif /** * @} */ @@ -1884,14 +2214,18 @@ * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ +#if defined(QUADSPI) #define __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QUADSPISMEN) != RESET) +#endif #define __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PKASMEN) != RESET) #define __HAL_RCC_AES2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_AES2SMEN) != RESET) #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_RNGSMEN) != RESET) #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM2SMEN) != RESET) #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FLASHSMEN) != RESET) +#if defined(QUADSPI) #define __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QUADSPISMEN) == RESET) +#endif #define __HAL_RCC_PKA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PKASMEN) == RESET) #define __HAL_RCC_AES2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_AES2SMEN) == RESET) #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_RNGSMEN) == RESET) @@ -1923,57 +2257,101 @@ * @{ */ #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET) +#if defined(LCD) #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET) +#endif #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != RESET) #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET) +#if defined(SPI2) #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET) +#endif #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET) +#if defined(I2C3) #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET) +#endif #if defined(CRS) #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != RESET) -#endif /* CRS */ +#endif +#if defined(USB) #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) != RESET) +#endif #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET) +#if defined(LPUART1) #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET) +#endif #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET) #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET) +#if defined(LCD) #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET) +#endif #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == RESET) #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET) +#if defined(SPI2) #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET) +#endif #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET) +#if defined(I2C3) #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET) +#endif #if defined(CRS) #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == RESET) -#endif /* CRS */ +#endif +#if defined(USB) #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) == RESET) +#endif #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET) +#if defined(LPUART1) #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET) +#endif #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET) #define __HAL_RCC_C2TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_TIM2SMEN) != RESET) +#if defined(LCD) #define __HAL_RCC_C2LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LCDSMEN) != RESET) +#endif #define __HAL_RCC_C2RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_RTCAPBSMEN) != RESET) +#if defined(SPI2) #define __HAL_RCC_C2SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_SPI2SMEN) != RESET) +#endif #define __HAL_RCC_C2I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C1SMEN) != RESET) +#if defined(I2C3) #define __HAL_RCC_C2I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C3SMEN) != RESET) +#endif +#if defined(CRS) #define __HAL_RCC_C2CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_CRSSMEN) != RESET) +#endif +#if defined(USB) #define __HAL_RCC_C2USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_USBSMEN) != RESET) +#endif #define __HAL_RCC_C2LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LPTIM1SMEN) != RESET) +#if defined(LPUART1) #define __HAL_RCC_C2LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPUART1SMEN) != RESET) +#endif #define __HAL_RCC_C2LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPTIM2SMEN) != RESET) #define __HAL_RCC_C2TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_TIM2SMEN) == RESET) +#if defined(LCD) #define __HAL_RCC_C2LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LCDSMEN) == RESET) +#endif #define __HAL_RCC_C2RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_RTCAPBSMEN) == RESET) +#if defined(SPI2) #define __HAL_RCC_C2SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_SPI2SMEN) == RESET) +#endif #define __HAL_RCC_C2I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C1SMEN) == RESET) +#if defined(I2C3) #define __HAL_RCC_C2I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C3SMEN) == RESET) +#endif +#if defined(CRS) #define __HAL_RCC_C2CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_CRSSMEN) == RESET) +#endif +#if defined(USB) #define __HAL_RCC_C2USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_USBSMEN) == RESET) +#endif #define __HAL_RCC_C2LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LPTIM1SMEN) == RESET) +#if defined(LPUART1) #define __HAL_RCC_C2LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPUART1SMEN) == RESET) +#endif #define __HAL_RCC_C2LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPTIM2SMEN) == RESET) /** * @} @@ -1992,28 +2370,36 @@ #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET) #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET) #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET) +#if defined(SAI1) #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET) +#endif #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET) #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET) #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET) #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET) #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET) +#if defined(SAI1) #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET) +#endif #define __HAL_RCC_C2TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM1SMEN) != RESET) #define __HAL_RCC_C2SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SPI1SMEN) != RESET) #define __HAL_RCC_C2USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_USART1SMEN) != RESET) #define __HAL_RCC_C2TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM16SMEN) != RESET) #define __HAL_RCC_C2TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM17SMEN) != RESET) +#if defined(SAI1) #define __HAL_RCC_C2SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SAI1SMEN) != RESET) +#endif #define __HAL_RCC_C2TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM1SMEN) == RESET) #define __HAL_RCC_C2SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SPI1SMEN) == RESET) #define __HAL_RCC_C2USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_USART1SMEN) == RESET) #define __HAL_RCC_C2TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM16SMEN) == RESET) #define __HAL_RCC_C2TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM17SMEN) == RESET) +#if defined(SAI1) #define __HAL_RCC_C2SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SAI1SMEN) == RESET) +#endif /** * @} */ @@ -2090,18 +2476,17 @@ /** @brief Macros to enable the Internal High Speed oscillator (HSI). * @note The HSI is stopped by hardware when entering STOP, STANDBY or SHUTDOWN modes. - * It is enabled by hardware ato force the HSI oscillator ON when STOPWUCK=1 + * It is enabled by hardware to force the HSI oscillator ON when STOPWUCK=1 * or HSIASFS = 1 when leaving Stop modes, or in case of failure of the HSE * crystal oscillator and Security System CSS is enabled. * @note After enabling the HSI, the application software should wait on HSIRDY * flag to be set indicating that HSI clock is stable and can be used as * system clock source. - * This parameter can be: ENABLE or DISABLE. * @retval None */ #define __HAL_RCC_HSI_ENABLE() LL_RCC_HSI_Enable() -/** @brief Macros to disable the Internal High Speed oscillator (HSI). +/** @brief Macro to disable the Internal High Speed oscillator (HSI). * @note HSI can not be stopped if it is used as system clock source. In this case, * you have to select another source of the system clock then stop the HSI. * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator @@ -2136,7 +2521,6 @@ * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication * speed because of the HSI startup time. * @note The enable of this function has not effect on the HSION bit. - * This parameter can be: ENABLE or DISABLE. * @retval None */ #define __HAL_RCC_HSISTOP_ENABLE() LL_RCC_HSI_EnableInStopMode() @@ -2162,7 +2546,7 @@ #define __HAL_RCC_MSI_ENABLE() LL_RCC_MSI_Enable() #define __HAL_RCC_MSI_DISABLE() LL_RCC_MSI_Disable() -/** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value. +/** @brief Macro to adjust the Internal Multi Speed oscillator (MSI) calibration value. * @note The calibration is used to compensate for the variations in voltage * and temperature that influence the frequency of the internal MSI RC. * Refer to the Application Note AN3300 for more details on how to @@ -2452,7 +2836,7 @@ /** @brief Macro to configure the PLL multiplication factor. * @note This function must be used only when the main PLL is disabled. * @param __PLLM__ specifies the division factor for PLL VCO input clock - * This parameter must be a value of RCC_PLLM_Clock_Divider. + * This parameter must be a value of @ref RCC_PLLM_Clock_Divider. * @note You have to set the PLLM parameter correctly to ensure that the VCO input * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency * of 16 MHz to limit PLL jitter. @@ -2475,7 +2859,7 @@ * @note This clock source is common for the main PLL and audio PLL (PLL and PLLSAI1). * * @param __PLLM__ specifies the division factor for PLL VCO input clock. - * This parameter must be a value of RCC_PLLM_Clock_Divider. + * This parameter must be a value of @ref RCC_PLLM_Clock_Divider. * @note You have to set the PLLM parameter correctly to ensure that the VCO input * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency * of 16 MHz to limit PLL jitter. @@ -2496,8 +2880,8 @@ * correctly. * * @param __PLLR__ specifies the division factor for the main system clock. - * This parameter must be a value of RCC_PLLR_Clock_Divider - * @note You have to set the PLLR parameter correctly to not exceed 64MHZ. + * This parameter must be a value of @ref RCC_PLLR_Clock_Divider + * @note You have to set the PLLR parameter correctly to not exceed 48 MHZ. * @retval None */ #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
diff --git a/Inc/stm32wbxx_hal_rcc_ex.h b/Inc/stm32wbxx_hal_rcc_ex.h index db0f515..68fe89f 100644 --- a/Inc/stm32wbxx_hal_rcc_ex.h +++ b/Inc/stm32wbxx_hal_rcc_ex.h
@@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - * <h2><center>© Copyright (c) 2019 STMicroelectronics. + * <h2><center>© Copyright (c) 2019 STMicroelectronics. * All rights reserved.</center></h2> * * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -48,6 +48,8 @@ /* CRS Flag Error Mask */ #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) +/* RNG closk selection CLK48 clock mask */ +#define CLK48_MASK 0x10000000U /** * @} */ @@ -62,11 +64,11 @@ #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) - +#if defined(LPUART1) && defined(I2C3) && defined(SAI1) && defined(USB) && defined(RCC_SMPS_SUPPORT) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ @@ -77,6 +79,17 @@ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ (((__SELECTION__) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP)|| \ (((__SELECTION__) & RCC_PERIPHCLK_SMPS) == RCC_PERIPHCLK_SMPS)) +#else +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP)) +#endif #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ @@ -84,31 +97,33 @@ ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) - +#if defined(LPUART1) #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) - +#endif #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) +#if defined(I2C3) #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) +#endif - +#if defined(SAI1) #define IS_RCC_SAI1CLK(__SOURCE__) \ (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) - +#endif #define IS_RCC_LPTIM1CLK(__SOURCE__) \ (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ @@ -123,22 +138,38 @@ ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_RNGCLKSOURCE_CLK48) || \ - ((__SOURCE__) == RCC_RNGCLKSOURCE_LSI) || \ + (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_CLK48) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_LSI) || \ ((__SOURCE__) == RCC_RNGCLKSOURCE_LSE)) +#if defined(SAI1) #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \ ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) +#else +#define IS_RCC_USBCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ + ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) +#endif - +#if defined(SAI1) #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) +#else +#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) +#endif #define IS_RCC_RFWKPCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_RFWKPCLKSOURCE_NONE) || \ @@ -146,6 +177,7 @@ ((__SOURCE__) == RCC_RFWKPCLKSOURCE_LSI) || \ ((__SOURCE__) == RCC_RFWKPCLKSOURCE_HSE_DIV1024)) +#if defined(RCC_SMPS_SUPPORT) #define IS_RCC_SMPSCLKDIV(__DIV__) \ (((__DIV__) == RCC_SMPSCLKDIV_RANGE0) || \ ((__DIV__) == RCC_SMPSCLKDIV_RANGE1) || \ @@ -156,7 +188,9 @@ (((__SOURCE__) == RCC_SMPSCLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_SMPSCLKSOURCE_MSI) || \ ((__SOURCE__) == RCC_SMPSCLKSOURCE_HSE)) +#endif +#if defined(SAI1) #define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32)) @@ -164,9 +198,11 @@ #define IS_RCC_PLLSAI1Q_VALUE(__VALUE__) ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8)) #define IS_RCC_PLLSAI1R_VALUE(__VALUE__) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8)) +#endif #define IS_RCC_TRIMOSC(__VALUE__) ((__VALUE__) == RCC_OSCILLATORTYPE_LSI2) +#if defined(CRS) #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) @@ -187,7 +223,7 @@ #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) - +#endif /** * @} */ @@ -198,6 +234,7 @@ * @{ */ +#if defined(SAI1) /** * @brief PLLSAI1 Clock structure definition */ @@ -219,7 +256,7 @@ uint32_t PLLSAI1ClockOut; /*!< PLLSAI1ClockOut: specifies PLLSAI1 output clock to be enabled. This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */ } RCC_PLLSAI1InitTypeDef; - +#endif /** * @brief RCC extended clocks structure definition @@ -229,23 +266,27 @@ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - +#if defined(SAI1) RCC_PLLSAI1InitTypeDef PLLSAI1; /*!< PLLSAI1 structure parameters. This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI, USB/RNG or ADC */ +#endif uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ - +#if defined(LPUART1) uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ +#endif uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ +#if defined(I2C3) uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ +#endif uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ @@ -253,9 +294,10 @@ uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ +#if defined(SAI1) uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ - +#endif uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for RNG). This parameter can be a value of @ref RCCEx_USB_Clock_Source */ @@ -273,15 +315,17 @@ uint32_t RFWakeUpClockSelection; /*!< Specifies RF Wake-up clock source. This parameter can be a value of @ref RCCEx_RFWKP_Clock_Source */ +#if defined(RCC_SMPS_SUPPORT) uint32_t SmpsClockSelection; /*!< Specifies SMPS clock source. This parameter can be a value of @ref RCCEx_SMPS_Clock_Source */ uint32_t SmpsDivSelection; /*!< Specifies SMPS clock division factor. This parameter can be a value of @ref RCCEx_SMPS_Clock_Divider */ - +#endif } RCC_PeriphCLKInitTypeDef; +#if defined(CRS) /** * @brief RCC_CRS Init structure definition */ @@ -329,7 +373,7 @@ This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ } RCC_CRSSynchroInfoTypeDef; - +#endif /** * @} @@ -364,25 +408,31 @@ * @{ */ #define RCC_PERIPHCLK_USART1 0x00000001U /*!< USART1 Peripheral Clock Selection */ +#if defined(LPUART1) #define RCC_PERIPHCLK_LPUART1 0x00000002U /*!< LPUART1 Peripheral Clock Selection */ +#endif #define RCC_PERIPHCLK_I2C1 0x00000004U /*!< I2C1 Peripheral Clock Selection */ +#if defined(I2C3) #define RCC_PERIPHCLK_I2C3 0x00000008U /*!< I2C3 Peripheral Clock Selection */ +#endif #define RCC_PERIPHCLK_LPTIM1 0x00000010U /*!< LPTIM1 Peripheral Clock Selection */ #define RCC_PERIPHCLK_LPTIM2 0x00000020U /*!< LPTIM2 Peripheral Clock Selection */ +#if defined(SAI1) #define RCC_PERIPHCLK_SAI1 0x00000040U /*!< SAI1 Peripheral Clock Selection */ -#define RCC_PERIPHCLK_USB 0x00000100U /*!< USB Peripheral Clock Selection */ +#endif +#define RCC_PERIPHCLK_CLK48SEL 0x00000100U /*!< 48 MHz clock source selection */ +#define RCC_PERIPHCLK_USB RCC_PERIPHCLK_CLK48SEL /*!< USB Peripheral Clock Selection */ #define RCC_PERIPHCLK_RNG 0x00000200U /*!< RNG Peripheral Clock Selection */ #define RCC_PERIPHCLK_ADC 0x00000400U /*!< ADC Peripheral Clock Selection */ #define RCC_PERIPHCLK_RTC 0x00000800U /*!< RTC Peripheral Clock Selection */ #define RCC_PERIPHCLK_RFWAKEUP 0x00001000U /*!< RF Wakeup Peripheral Clock Selection */ -#define RCC_PERIPHCLK_SMPS 0x00002000U /*!< SMPSS Peripheral Clock Selection */ +#if defined(RCC_SMPS_SUPPORT) +#define RCC_PERIPHCLK_SMPS 0x00002000U /*!< SMPS Peripheral Clock Selection */ +#endif /** * @} */ - - - /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source * @{ */ @@ -394,7 +444,7 @@ * @} */ - +#if defined(LPUART1) /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source * @{ */ @@ -405,6 +455,7 @@ /** * @} */ +#endif /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source * @{ @@ -416,7 +467,7 @@ * @} */ - +#if defined(I2C3) /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source * @{ */ @@ -426,8 +477,9 @@ /** * @} */ +#endif - +#if defined(SAI1) /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source * @{ */ @@ -438,6 +490,7 @@ /** * @} */ +#endif /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source * @{ @@ -454,9 +507,9 @@ * @{ */ #define RCC_LPTIM2CLKSOURCE_PCLK1 LL_RCC_LPTIM2_CLKSOURCE_PCLK1 /*!< APB1 clock selected as LPTIM2 clock */ -#define RCC_LPTIM2CLKSOURCE_LSI LL_RCC_LPTIM2_CLKSOURCE_LSI /*!< LSI clock selected as LPTIM1 clock */ -#define RCC_LPTIM2CLKSOURCE_HSI LL_RCC_LPTIM2_CLKSOURCE_HSI /*!< HSI clock selected as LPTIM1 clock */ -#define RCC_LPTIM2CLKSOURCE_LSE LL_RCC_LPTIM2_CLKSOURCE_LSE /*!< LSE clock selected as LPTIM1 clock */ +#define RCC_LPTIM2CLKSOURCE_LSI LL_RCC_LPTIM2_CLKSOURCE_LSI /*!< LSI clock selected as LPTIM2 clock */ +#define RCC_LPTIM2CLKSOURCE_HSI LL_RCC_LPTIM2_CLKSOURCE_HSI /*!< HSI clock selected as LPTIM2 clock */ +#define RCC_LPTIM2CLKSOURCE_LSE LL_RCC_LPTIM2_CLKSOURCE_LSE /*!< LSE clock selected as LPTIM2 clock */ /** * @} */ @@ -464,9 +517,12 @@ /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source * @{ */ -#define RCC_RNGCLKSOURCE_CLK48 LL_RCC_RNG_CLKSOURCE_CLK48 /*!< CLK48 divided by 3 selected as RNG Clock */ -#define RCC_RNGCLKSOURCE_LSI LL_RCC_RNG_CLKSOURCE_LSI /*!< LSI selected as ADC clock*/ -#define RCC_RNGCLKSOURCE_LSE LL_RCC_RNG_CLKSOURCE_LSE /*!< LSE selected as ADC clock*/ +#define RCC_RNGCLKSOURCE_HSI48 (CLK48_MASK | LL_RCC_CLK48_CLKSOURCE_HSI48) /*!< HSI48 clock divided by 3 selected as RNG clock */ +#define RCC_RNGCLKSOURCE_PLL (CLK48_MASK | LL_RCC_CLK48_CLKSOURCE_PLL) /*!< PLL "Q" clock divided by 3 selected as RNG clock */ +#define RCC_RNGCLKSOURCE_MSI (CLK48_MASK | LL_RCC_CLK48_CLKSOURCE_MSI) /*!< MSI clock divided by 3 selected as RNG clock */ +#define RCC_RNGCLKSOURCE_CLK48 LL_RCC_RNG_CLKSOURCE_CLK48 /*!< CLK48 divided by 3 selected as RNG Clock */ +#define RCC_RNGCLKSOURCE_LSI LL_RCC_RNG_CLKSOURCE_LSI /*!< LSI clock selected as RNG clock */ +#define RCC_RNGCLKSOURCE_LSE LL_RCC_RNG_CLKSOURCE_LSE /*!< LSE clock selected as RNG clock */ /** * @} */ @@ -474,12 +530,10 @@ /** @defgroup RCCEx_USB_Clock_Source USB Clock Source * @{ */ - #define RCC_USBCLKSOURCE_HSI48 LL_RCC_USB_CLKSOURCE_HSI48 /*!< HSI48 clock selected as USB clock */ #define RCC_USBCLKSOURCE_PLLSAI1 LL_RCC_USB_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 "Q" clock selected as USB clock */ #define RCC_USBCLKSOURCE_PLL LL_RCC_USB_CLKSOURCE_PLL /*!< PLL "Q" clock selected as USB clock */ #define RCC_USBCLKSOURCE_MSI LL_RCC_USB_CLKSOURCE_MSI /*!< MSI clock selected as USB clock */ - /** * @} */ @@ -489,7 +543,9 @@ */ #define RCC_ADCCLKSOURCE_NONE LL_RCC_ADC_CLKSOURCE_NONE /*!< None clock selected as ADC clock */ +#if defined(SAI1) #define RCC_ADCCLKSOURCE_PLLSAI1 LL_RCC_ADC_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 "R" clock selected as ADC clock */ +#endif #define RCC_ADCCLKSOURCE_PLL LL_RCC_ADC_CLKSOURCE_PLL /*!< PLL "P" clock selected as ADC clock */ #define RCC_ADCCLKSOURCE_SYSCLK LL_RCC_ADC_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as ADC clock */ @@ -522,45 +578,38 @@ */ - +#if defined(RCC_SMPS_SUPPORT) /** @defgroup RCCEx_SMPS_Clock_Source SMPS Clock Source * @{ */ - #define RCC_SMPSCLKSOURCE_HSI LL_RCC_SMPS_CLKSOURCE_HSI /*!< HSI selection as smps clock */ #define RCC_SMPSCLKSOURCE_MSI LL_RCC_SMPS_CLKSOURCE_MSI /*!< MSI selection as smps clock */ #define RCC_SMPSCLKSOURCE_HSE LL_RCC_SMPS_CLKSOURCE_HSE /*!< HSE selection as smps clock */ - /** * @} */ - /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status * @{ */ #define RCC_SMPSCLKSOURCE_STATUS_HSI LL_RCC_SMPS_CLKSOURCE_STATUS_HSI /*!< HSI selection as smps clock */ #define RCC_SMPSCLKSOURCE_STATUS_MSI LL_RCC_SMPS_CLKSOURCE_STATUS_MSI /*!< MSI selection as smps clock */ #define RCC_SMPSCLKSOURCE_STATUS_HSE LL_RCC_SMPS_CLKSOURCE_STATUS_HSE /*!< HSE selection as smps clock */ - - /** * @} */ - /** @defgroup RCCEx_SMPS_Clock_Divider SMPS Clock Division Factor * @{ */ - #define RCC_SMPSCLKDIV_RANGE0 LL_RCC_SMPS_DIV_0 /*!< PLLM division factor = 0 */ #define RCC_SMPSCLKDIV_RANGE1 LL_RCC_SMPS_DIV_1 /*!< PLLM division factor = 1 */ #define RCC_SMPSCLKDIV_RANGE2 LL_RCC_SMPS_DIV_2 /*!< PLLM division factor = 2 */ #define RCC_SMPSCLKDIV_RANGE3 LL_RCC_SMPS_DIV_3 /*!< PLLM division factor = 3 */ - /** * @} */ +#endif /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line * @{ @@ -572,6 +621,7 @@ */ +#if defined(CRS) /** @defgroup RCCEx_CRS_Status RCCEx CRS Status * @{ */ @@ -685,6 +735,7 @@ /** * @} */ +#endif /** * @} @@ -697,6 +748,7 @@ /*================================================================================================================*/ +#if defined(SAI1) /** * @brief Macro to configure the PLLSAI1 clock multiplication and division factors. * @@ -817,7 +869,6 @@ * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface * @arg @ref RCC_PLLSAI1_ADCCLK Clock used to clock ADC peripheral * @arg @ref RCC_PLLSAI1_USBCLK This clock is used to generate the clock for the USB Device (48 MHz) - * @arg @ref RCC_PLLSAI1_RNGCLK same as RCC_PLLSAI1_USBCLK * * @retval None */ @@ -832,7 +883,6 @@ * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface * @arg @ref RCC_PLLSAI1_ADCCLK Clock used to clock ADC peripheral * @arg @ref RCC_PLLSAI1_USBCLK This clock is used to generate the clock for the USB Device (48 MHz) - * @arg @ref RCC_PLLSAI1_RNGCLK same as RCC_PLLSAI1_USBCLK * * @retval None */ @@ -845,7 +895,6 @@ * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface * @arg @ref RCC_PLLSAI1_ADCCLK Clock used to clock ADC peripheral * @arg @ref RCC_PLLSAI1_USBCLK This clock is used to generate the clock for the USB Device (48 MHz) - * @arg @ref RCC_PLLSAI1_RNGCLK same as RCC_PLLSAI1_USBCLK * @retval SET / RESET */ #define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) @@ -876,6 +925,7 @@ * @retval None */ #define __HAL_RCC_GET_SAI1_SOURCE() LL_RCC_GetSAIClockSource(LL_RCC_SAI1_CLKSOURCE) +#endif /** @brief Macro to configure the I2C1 clock (I2C1CLK). * @@ -896,6 +946,7 @@ */ #define __HAL_RCC_GET_I2C1_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C1_CLKSOURCE) +#if defined(I2C3) /** @brief Macro to configure the I2C3 clock (I2C3CLK). * * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. @@ -914,6 +965,7 @@ * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock */ #define __HAL_RCC_GET_I2C3_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C3_CLKSOURCE) +#endif /** @brief Macro to configure the USART1 clock (USART1CLK). * @@ -936,6 +988,7 @@ */ #define __HAL_RCC_GET_USART1_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_USART1_CLKSOURCE) +#if defined(LPUART1) /** @brief Macro to configure the LPUART clock (LPUARTCLK). * * @param __LPUART_CLKSOURCE__ specifies the LPUART clock source. @@ -956,6 +1009,7 @@ * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock */ #define __HAL_RCC_GET_LPUART1_SOURCE() LL_RCC_GetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE) +#endif /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). * @@ -1006,19 +1060,40 @@ * * @param __RNG_CLKSOURCE__ specifies the RNG clock source. * This parameter can be one of the following values: - * @arg @ref RCC_RNGCLKSOURCE_CLK48 CLK48 divided by 3 selected as RNG Clock - * @arg @ref RCC_RNGCLKSOURCE_LSI LSI selected as RNG clock - * @arg @ref RCC_RNGCLKSOURCE_LSE LSE selected as RNG clock + * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 clock divided by 3 selected as RNG clock + * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock divided by 3 selected as RNG clock + * @arg @ref RCC_RNGCLKSOURCE_MSI MSI clock divided by 3 selected as RNG clock + * @arg @ref RCC_RNGCLKSOURCE_CLK48 CLK48 divided by 3 selected as RNG Clock (default HSI48) + * @arg @ref RCC_RNGCLKSOURCE_LSI LSI clock selected as RNG clock + * @arg @ref RCC_RNGCLKSOURCE_LSE LSE clock selected as RNG clock * @retval None */ -#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) LL_RCC_SetRNGClockSource(__RNG_CLKSOURCE__) +#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ + do { \ + if (((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_LSI) \ + || ((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_LSE) \ + || ((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_CLK48)) \ + { \ + LL_RCC_SetRNGClockSource((__RNG_CLKSOURCE__)); \ + } \ + else \ + { \ + uint32_t tmp = (__RNG_CLKSOURCE__) &(~CLK48_MASK); \ + LL_RCC_SetRNGClockSource(RCC_RNGCLKSOURCE_CLK48); \ + LL_RCC_SetCLK48ClockSource(tmp); \ + } \ + } while(0U) -/** @brief Macro to get the RNG clock. * @retval The clock source can be one of the following values: +/** @brief Macro to get the direct RNG clock. + * @note @ref HAL_RCCEx_GetRngCLKSource can also be called to get direct + * of indirect (48 MHz clock source) RNG clock source. + * @retval The RNG clock source can be one of the following values: * @arg @ref RCC_RNGCLKSOURCE_CLK48 CLK48 divided by 3 selected as RNG Clock * @arg @ref RCC_RNGCLKSOURCE_LSI LSI selected as RNG clock * @arg @ref RCC_RNGCLKSOURCE_LSE LSE selected as RNG clock */ #define __HAL_RCC_GET_RNG_SOURCE() LL_RCC_GetRNGClockSource(LL_RCC_RNG_CLKSOURCE) + /** @brief Macro to configure the USB clock (USBCLK). * * @note USB and RNG peripherals share the same 48MHz clock source. @@ -1082,6 +1157,7 @@ */ #define __HAL_RCC_GET_RFWAKEUP_SOURCE() LL_RCC_GetRFWKPClockSource() +#if defined(RCC_SMPS_SUPPORT) /** @brief Macro to configure the SMPS clock division factor. * * @param __SMPSCLKDIV__ specifies the division factor for SMPS clock. @@ -1134,12 +1210,14 @@ * @arg @ref RCC_SMPSCLKSOURCE_STATUS_HSE HSE Clock selected as SMPS clock */ #define __HAL_RCC_GET_SMPS_SOURCE_STATUS() LL_RCC_GetSMPSClockSource() +#endif /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management * @brief macros to manage the specified RCC Flags and interrupts. * @{ */ +#if defined(SAI1) /** @brief Enable PLLSAI1RDY interrupt. * @retval None */ @@ -1164,6 +1242,7 @@ * @retval TRUE or FALSE. */ #define __HAL_RCC_PLLSAI1_GET_FLAG() LL_RCC_PLLSAI1_IsReady() +#endif /** * @brief Enable the RCC LSE CSS Extended Interrupt C1 Line. @@ -1275,6 +1354,7 @@ */ #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(RCC_EXTI_LINE_LSECSS) +#if defined(CRS) /** * @brief Enable the specified CRS interrupts. * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. @@ -1371,12 +1451,13 @@ WRITE_REG(CRS->ICR, (__FLAG__)); \ } \ } while(0) - +#endif /** * @} */ +#if defined(CRS) /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features * @{ */ @@ -1421,6 +1502,7 @@ /** * @} */ +#endif /** * @} @@ -1438,6 +1520,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); +uint32_t HAL_RCCEx_GetRngCLKSource(void); /** * @} @@ -1447,8 +1530,10 @@ * @{ */ +#if defined(SAI1) HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init); HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void); +#endif void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); @@ -1471,6 +1556,7 @@ * @} */ + #if defined(CRS) /** @addtogroup RCCEx_Exported_Functions_Group3 @@ -1491,8 +1577,7 @@ * @} */ -#endif /* CRS */ - +#endif /** * @} */
diff --git a/Inc/stm32wbxx_hal_rng.h b/Inc/stm32wbxx_hal_rng.h index dbc0a09..1c170b8 100644 --- a/Inc/stm32wbxx_hal_rng.h +++ b/Inc/stm32wbxx_hal_rng.h
@@ -176,7 +176,9 @@ #define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U /*!< Invalid Callback error */ #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ #define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */ - +#define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */ +#define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */ +#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ /** * @} */
diff --git a/Inc/stm32wbxx_hal_rtc.h b/Inc/stm32wbxx_hal_rtc.h index babb4c1..917560f 100644 --- a/Inc/stm32wbxx_hal_rtc.h +++ b/Inc/stm32wbxx_hal_rtc.h
@@ -213,9 +213,13 @@ HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01U, /*!< RTC Alarm B Event Callback ID */ HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02U, /*!< RTC TimeStamp Event Callback ID */ HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03U, /*!< RTC WakeUp Timer Event Callback ID */ +#if defined(RTC_TAMPER1_SUPPORT) HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04U, /*!< RTC Tamper 1 Callback ID */ +#endif HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, /*!< RTC Tamper 2 Callback ID */ +#if defined(RTC_TAMPER3_SUPPORT) HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06U, /*!< RTC Tamper 3 Callback ID */ +#endif HAL_RTC_MSPINIT_CB_ID = 0x0EU, /*!< RTC Msp Init callback ID */ HAL_RTC_MSPDEINIT_CB_ID = 0x0FU /*!< RTC Msp DeInit callback ID */ }HAL_RTC_CallbackIDTypeDef;
diff --git a/Inc/stm32wbxx_hal_rtc_ex.h b/Inc/stm32wbxx_hal_rtc_ex.h index adb0c2a..34aef5a 100644 --- a/Inc/stm32wbxx_hal_rtc_ex.h +++ b/Inc/stm32wbxx_hal_rtc_ex.h
@@ -731,17 +731,18 @@ /**************************************************************************************************/ -#if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT) - /** * @brief Enable the RTC Tamper interrupt. * @param __HANDLE__ specifies the RTC handle. * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg RTC_IT_TAMP: All tampers interrupts - * @arg RTC_IT_TAMP1: Tamper1 interrupt + * @arg RTC_IT_TAMP1: Tamper1 interrupt (*) * @arg RTC_IT_TAMP2: Tamper2 interrupt - * @arg RTC_IT_TAMP3: Tamper3 interrupt + * @arg RTC_IT_TAMP3: Tamper3 interrupt (*) + * + * (*) Value not defined in all devices. \n + * * @retval None */ #define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__)) @@ -751,131 +752,54 @@ * @param __HANDLE__ specifies the RTC handle. * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled. * This parameter can be any combination of the following values: - * @arg RTC_IT_TAMP: All tampers interrupts - * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt - * @arg RTC_IT_TAMP3: Tamper3 interrupt - * @retval None - */ -#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__)) - -#elif defined(RTC_TAMPER1_SUPPORT) - -/** - * @brief Enable the RTC Tamper interrupt. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled. - * This parameter can be any combination of the following values: * @arg RTC_IT_TAMP: All tampers interrupts - * @arg RTC_IT_TAMP1: Tamper1 interrupt + * @arg RTC_IT_TAMP1: Tamper1 interrupt (*) * @arg RTC_IT_TAMP2: Tamper2 interrupt - * @retval None - */ -#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__)) - -/** - * @brief Disable the RTC Tamper interrupt. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TAMP: All tampers interrupts - * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt + * @arg RTC_IT_TAMP3: Tamper3 interrupt (*) + * + * (*) Value not defined in all devices. \n + * * @retval None */ #define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__)) -#elif defined(RTC_TAMPER3_SUPPORT) - - -/** - * @brief Enable the RTC Tamper interrupt. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TAMP: All tampers interrupts - * @arg RTC_IT_TAMP2: Tamper2 interrupt - * @arg RTC_IT_TAMP3: Tamper3 interrupt - * @retval None - */ -#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__)) - -/** - * @brief Disable the RTC Tamper interrupt. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TAMP: All tampers interrupts - * @arg RTC_IT_TAMP2: Tamper2 interrupt - * @arg RTC_IT_TAMP3: Tamper3 interrupt - * @retval None - */ -#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__)) - -#endif - /**************************************************************************************************/ -#if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT) - /** * @brief Check whether the specified RTC Tamper interrupt has occurred or not. * @param __HANDLE__ specifies the RTC handle. * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check. * This parameter can be: - * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt - * @arg RTC_IT_TAMP3: Tamper3 interrupt + * @arg RTC_IT_TAMP1: Tamper1 interrupt (*) + * @arg RTC_IT_TAMP2: Tamper2 interrupt + * @arg RTC_IT_TAMP3: Tamper3 interrupt (*) + * + * (*) Value not defined in all devices. \n + * * @retval None */ +#if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT) #define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3U)) != 0U) ? 1U : 0U) : \ ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5U)) != 0U) ? 1U : 0U) : \ ((__INTERRUPT__) == RTC_IT_TAMP3) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7U)) != 0U) ? 1U : 0U)) - -#elif defined(RTC_TAMPER1_SUPPORT) - -/** - * @brief Check whether the specified RTC Tamper interrupt has occurred or not. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check. - * This parameter can be: - * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt - * @retval None - */ -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3U)) != 0U) ? 1U : 0U) : \ - ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5U)) != 0U) ? 1U : 0U)) - -#elif defined(RTC_TAMPER3_SUPPORT) - -/** - * @brief Check whether the specified RTC Tamper interrupt has occurred or not. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check. - * This parameter can be: - * @arg RTC_IT_TAMP2: Tamper2 interrupt - * @arg RTC_IT_TAMP3: Tamper3 interrupt - * @retval None - */ -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5U)) != 0U) ? 1U : 0U) : \ - ((__INTERRUPT__) == RTC_IT_TAMP3) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7U)) != 0U) ? 1U : 0U)) - - +#else +#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3U)) != 0U) ? 1U : 0U)) #endif - + /**************************************************************************************************/ -#if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT) - /** * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. * @param __HANDLE__ specifies the RTC handle. * @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check. * This parameter can be: * @arg RTC_IT_TAMP: All tampers interrupts - * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt - * @arg RTC_IT_TAMP3: Tamper3 interrupt + * @arg RTC_IT_TAMP1: Tamper1 interrupt (*) + * @arg RTC_IT_TAMP2: Tamper2 interrupt + * @arg RTC_IT_TAMP3: Tamper3 interrupt (*) + * + * (*) Value not defined in all devices. \n + * * @retval None */ #define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) @@ -886,9 +810,12 @@ * @param __HANDLE__ specifies the RTC handle. * @param __FLAG__ specifies the RTC Tamper Flag is pending or not. * This parameter can be: - * @arg RTC_FLAG_TAMP1F: Tamper1 flag + * @arg RTC_FLAG_TAMP1F: Tamper1 flag (*) * @arg RTC_FLAG_TAMP2F: Tamper2 flag - * @arg RTC_FLAG_TAMP3F: Tamper3 flag + * @arg RTC_FLAG_TAMP3F: Tamper3 flag (*) + * + * (*) Value not defined in all devices. \n + * * @retval None */ #define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U) @@ -898,90 +825,16 @@ * @param __HANDLE__ specifies the RTC handle. * @param __FLAG__ specifies the RTC Tamper Flag to clear. * This parameter can be: - * @arg RTC_FLAG_TAMP1F: Tamper1 flag + * @arg RTC_FLAG_TAMP1F: Tamper1 flag (*) * @arg RTC_FLAG_TAMP2F: Tamper2 flag - * @arg RTC_FLAG_TAMP3F: Tamper3 flag + * @arg RTC_FLAG_TAMP3F: Tamper3 flag (*) + * + * (*) Value not defined in all devices. \n + * * @retval None */ #define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) -#elif defined(RTC_TAMPER1_SUPPORT) - -/** - * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check. - * This parameter can be: - * @arg RTC_IT_TAMP: All tampers interrupts - * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt - * @retval None - */ -#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) - - -/** - * @brief Get the selected RTC Tamper's flag status. - * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC Tamper Flag is pending or not. - * This parameter can be: - * @arg RTC_FLAG_TAMP1F: Tamper1 flag - * @arg RTC_FLAG_TAMP2F: Tamper2 flag - * @retval None - */ -#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U) - -/** - * @brief Clear the RTC Tamper's pending flags. - * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC Tamper Flag to clear. - * This parameter can be: - * @arg RTC_FLAG_TAMP1F: Tamper1 flag - * @arg RTC_FLAG_TAMP2F: Tamper2 flag - * @retval None - */ -#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -#elif defined(RTC_TAMPER3_SUPPORT) - - -/** - * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check. - * This parameter can be: - * @arg RTC_IT_TAMP: All tampers interrupts - * @arg RTC_IT_TAMP2: Tamper2 interrupt - * @arg RTC_IT_TAMP3: Tamper3 interrupt - * @retval None - */ -#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) - - -/** - * @brief Get the selected RTC Tamper's flag status. - * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC Tamper Flag is pending or not. - * This parameter can be: - * @arg RTC_FLAG_TAMP2F: Tamper2 flag - * @arg RTC_FLAG_TAMP3F: Tamper3 flag - * @retval None - */ -#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U) - -/** - * @brief Clear the RTC Tamper's pending flags. - * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC Tamper Flag to clear. - * This parameter can be: - * @arg RTC_FLAG_TAMP2F: Tamper2 flag - * @arg RTC_FLAG_TAMP3F: Tamper3 flag - * @retval None - */ -#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -#endif - /**************************************************************************************************/ @@ -1332,31 +1185,18 @@ #define RTC_TAMPCR_TAMPXIE ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | \ RTC_TAMPER3_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT)) -#elif defined(RTC_TAMPER1_SUPPORT) +#else -#define RTC_FLAGS_MASK ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP2F | RTC_FLAG_TAMP1F| \ +#define RTC_FLAGS_MASK ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP2F | \ RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \ RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | \ RTC_FLAG_INITF | RTC_FLAG_RSF | RTC_FLAG_INITS | \ RTC_FLAG_SHPF | RTC_FLAG_WUTWF |RTC_FLAG_ALRBWF | \ RTC_FLAG_ALRAWF)) -#define RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E)) -#define RTC_TAMPCR_TAMPXIE ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | \ - RTC_ALL_TAMPER_INTERRUPT)) +#define RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP2E)) +#define RTC_TAMPCR_TAMPXIE ((uint32_t) (RTC_TAMPER2_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT)) -#elif defined(RTC_TAMPER3_SUPPORT) - -#define RTC_FLAGS_MASK ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP3F | RTC_FLAG_TAMP2F | \ - RTC_FLAG_TSOVF | RTC_FLAG_TSF | \ - RTC_FLAG_WUTF | RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | \ - RTC_FLAG_INITF | RTC_FLAG_RSF | \ - RTC_FLAG_INITS | RTC_FLAG_SHPF | RTC_FLAG_WUTWF | \ - RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF)) - -#define RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E)) -#define RTC_TAMPCR_TAMPXIE ((uint32_t) (RTC_TAMPER2_INTERRUPT | \ - RTC_TAMPER3_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT)) #endif #define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT (EXTI_IMR1_IM18) /*!< External interrupt line 18 Connected to the RTC Tamper and Time Stamp events */
diff --git a/Inc/stm32wbxx_hal_sai.h b/Inc/stm32wbxx_hal_sai.h index 831fd1f..bdcf604 100644 --- a/Inc/stm32wbxx_hal_sai.h +++ b/Inc/stm32wbxx_hal_sai.h
@@ -32,6 +32,8 @@ * @{ */ +#if defined (SAI1) + /** @addtogroup SAI * @{ */ @@ -153,6 +155,7 @@ /** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition * @brief SAI Frame Init structure definition + * @note For SPDIF and AC97 protocol, these parameters are not used (set by hardware). * @{ */ typedef struct @@ -185,6 +188,8 @@ /** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition * @brief SAI Block Slot Init Structure definition + * @note For SPDIF protocol, these parameters are not used (set by hardware). + * @note For AC97 protocol, only SlotActive parameter is used (the others are set by hardware). * @{ */ typedef struct @@ -948,6 +953,8 @@ * @} */ +#endif /* SAI1 */ + /** * @} */
diff --git a/Inc/stm32wbxx_hal_sai_ex.h b/Inc/stm32wbxx_hal_sai_ex.h index ac2871c..7a9d931 100644 --- a/Inc/stm32wbxx_hal_sai_ex.h +++ b/Inc/stm32wbxx_hal_sai_ex.h
@@ -32,6 +32,8 @@ * @{ */ +#if defined (SAI1) + /** @addtogroup SAIEx * @{ */ @@ -92,10 +94,11 @@ * @} */ +#endif /* SAI1 */ + /** * @} */ - #ifdef __cplusplus } #endif
diff --git a/Inc/stm32wbxx_hal_spi.h b/Inc/stm32wbxx_hal_spi.h index 5f14649..7b2a571 100644 --- a/Inc/stm32wbxx_hal_spi.h +++ b/Inc/stm32wbxx_hal_spi.h
@@ -383,7 +383,8 @@ #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ #define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */ #define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */ -#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL) +#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\ + | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL) /** * @} */ @@ -433,7 +434,7 @@ } while(0) #else #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) -#endif +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ /** @brief Enable the specified SPI interrupts. * @param __HANDLE__ specifies the SPI Handle. @@ -469,7 +470,8 @@ * @arg SPI_IT_ERR: Error interrupt enable * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified SPI flag is set or not. * @param __HANDLE__ specifies the SPI Handle. @@ -529,9 +531,9 @@ */ #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ do{ \ - __IO uint32_t tmpreg_fre = 0x00U; \ - tmpreg_fre = (__HANDLE__)->Instance->SR; \ - UNUSED(tmpreg_fre); \ + __IO uint32_t tmpreg_fre = 0x00U; \ + tmpreg_fre = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg_fre); \ }while(0U) /** @brief Enable the SPI peripheral.
diff --git a/Inc/stm32wbxx_hal_tim.h b/Inc/stm32wbxx_hal_tim.h index a25f79a..3c12713 100644 --- a/Inc/stm32wbxx_hal_tim.h +++ b/Inc/stm32wbxx_hal_tim.h
@@ -235,7 +235,12 @@ uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ uint32_t MasterSlaveMode; /*!< Master/slave mode selection - This parameter can be a value of @ref TIM_Master_Slave_Mode */ + This parameter can be a value of @ref TIM_Master_Slave_Mode + @note When the Master/slave mode is enabled, the effect of + an event on the trigger input (TRGI) is delayed to allow a + perfect synchronization between the current timer and its + slaves (through TRGO). It is not mandatory in case of timer + synchronization mode. */ } TIM_MasterConfigTypeDef; /** @@ -1498,12 +1503,62 @@ * @retval None */ #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\ - ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE)) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) + +/** + * @brief Enable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is enabled an active edge on the trigger input acts + * like a compare match on CCx output. Delay to sample the trigger + * input and to activate CCx output is reduced to 3 clock cycles. + * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) + +/** + * @brief Disable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is disabled CCx output behaves normally depending + * on counter and CCRx values even when the trigger is ON. The minimum + * delay to activate CCx output when an active edge occurs on the + * trigger input is 5 clock cycles. + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) /** * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. @@ -1855,10 +1910,10 @@ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ - ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ @@ -1867,10 +1922,10 @@ ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ - ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ + ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) /** * @}
diff --git a/Inc/stm32wbxx_hal_tim_ex.h b/Inc/stm32wbxx_hal_tim_ex.h index 1903cd1..0c53871 100644 --- a/Inc/stm32wbxx_hal_tim_ex.h +++ b/Inc/stm32wbxx_hal_tim_ex.h
@@ -91,24 +91,40 @@ #define TIM_TIM1_ETR_ADC1_AWD1 TIM1_OR_ETR_ADC1_RMP_0 /* !< TIM1_ETR is connected to ADC1 AWD1 */ #define TIM_TIM1_ETR_ADC1_AWD2 TIM1_OR_ETR_ADC1_RMP_1 /* !< TIM1_ETR is connected to ADC1 AWD2 */ #define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_OR_ETR_ADC1_RMP_0 | TIM1_OR_ETR_ADC1_RMP_1) /* !< TIM1_ETR is connected to ADC1 AWD3 */ +#if defined(COMP1) #define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 output */ +#endif /* COMP1 */ +#if defined(COMP2) #define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 output */ +#endif /* COMP2 */ #define TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1 Input capture 1 is connected to I/0 */ #define TIM_TIM1_TI1_COMP1 TIM1_OR_TI1_RMP /* !< TIM1 Input capture 1is connected to COMP1 OUT */ #define TIM_TIM2_ITR_NC 0x00000000U /* !< TIM2 Internal trigger ITR is not connected */ +#if defined(USB) #define TIM_TIM2_ITR_USB TIM2_OR_ITR1_RMP /* !< TIM2 Internal trigger ITR is connected to USBFS SOF */ +#endif /* USB */ #define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2 External trigger ETR is connected to I/O */ #define TIM_TIM2_ETR_LSE TIM2_OR_ETR_RMP /* !< TIM2 External trigger ETR is connected to LSE */ +#if defined(COMP1) #define TIM_TIM2_ETR_COMP1 TIM2_AF1_ETRSEL_0 /* !< TIM2_ETR is connected to COMP1 output */ +#endif /* COMP1 */ +#if defined(COMP2) #define TIM_TIM2_ETR_COMP2 TIM2_AF1_ETRSEL_1 /* !< TIM2_ETR is connected to COMP2 output */ +#endif /* COMP2 */ #define TIM_TIM2_TI4_GPIO 0x00000000U /* !< TIM2_TI4 is connected to I/O */ +#if defined(COMP1) #define TIM_TIM2_TI4_COMP1 TIM2_OR_TI4_RMP_0 /* !< TIM2_TI4 is connected to COMP1 OUT */ +#endif /* COMP1 */ +#if defined(COMP2) #define TIM_TIM2_TI4_COMP2 TIM2_OR_TI4_RMP_1 /* !< TIM2_TI4 is connected to COMP1 OUT */ +#endif /* COMP2 */ +#if defined(COMP1) && defined(COMP2) #define TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR_TI4_RMP_0 | TIM2_OR_TI4_RMP_1) /* !< TIM2_TI4 is connected to COMP1 and COMP2 OUT */ +#endif /* COMP1 && COMP2 */ #define TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16_TI1 is connected to I/O */ #define TIM_TIM16_TI1_LSI TIM16_OR_TI1_RMP_0 /* !< TIM16_TI1 is connected to LSI Clock */ @@ -136,8 +152,12 @@ * @{ */ #define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */ +#if defined(COMP1) #define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */ +#endif /* COMP1 */ +#if defined(COMP2) #define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */ +#endif /* COMP2 */ /** * @} */ @@ -189,10 +209,15 @@ (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) +#if defined(COMP1) && defined(COMP2) #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) \ (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2)) +#else +#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) \ + (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)) +#endif #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) \ (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
diff --git a/Inc/stm32wbxx_hal_tsc.h b/Inc/stm32wbxx_hal_tsc.h index 6150c7e..81bc24e 100644 --- a/Inc/stm32wbxx_hal_tsc.h +++ b/Inc/stm32wbxx_hal_tsc.h
@@ -28,6 +28,8 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32wbxx_hal_def.h" +#if defined(TSC) + /** @addtogroup STM32WBxx_HAL_Driver * @{ */ @@ -640,7 +642,8 @@ #define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS))) -#define IS_TSC_GROUP(__VALUE__) ((((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\ +#define IS_TSC_GROUP(__VALUE__) (((__VALUE__) == 0UL) ||\ + (((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\ (((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\ (((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\ (((__VALUE__) & TSC_GROUP1_IO4) == TSC_GROUP1_IO4) ||\ @@ -751,6 +754,7 @@ /** * @} */ +#endif /* TSC */ #ifdef __cplusplus }
diff --git a/Inc/stm32wbxx_hal_uart.h b/Inc/stm32wbxx_hal_uart.h index 2e2e2b4..47f158b 100644 --- a/Inc/stm32wbxx_hal_uart.h +++ b/Inc/stm32wbxx_hal_uart.h
@@ -48,12 +48,14 @@ { uint32_t BaudRate; /*!< This member configures the UART communication baud rate. The baud rate register is computed using the following formula: +#if defined(LPUART1) LPUART: ======= Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) where lpuart_ker_ck_pres is the UART input clock divided by a prescaler UART: ===== +#endif - If oversampling is 16 or in LIN mode, Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) - If oversampling is 8, @@ -104,10 +106,10 @@ This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */ uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. - This parameter can be a value of @ref UART_Tx_Inv. */ + This parameter can be a value of @ref UART_Tx_Inv. */ uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. - This parameter can be a value of @ref UART_Rx_Inv. */ + This parameter can be a value of @ref UART_Rx_Inv. */ uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic vs negative/inverted logic). @@ -133,8 +135,6 @@ This parameter can be a value of @ref UART_MSB_First. */ } UART_AdvFeatureInitTypeDef; - - /** * @brief HAL UART State definition * @note HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition). @@ -221,9 +221,9 @@ uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ - void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ - void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ + void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ @@ -331,8 +331,10 @@ #define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */ #define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ #define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ +#define HAL_UART_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver Timeout error */ + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */ +#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ /** * @} @@ -422,7 +424,6 @@ #define UART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ #define UART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ #define UART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ - /** * @} */ @@ -438,11 +439,11 @@ * @} */ -/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut +/** @defgroup UART_Receiver_Timeout UART Receiver Timeout * @{ */ -#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART receiver timeout disable */ -#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART receiver timeout enable */ +#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */ +#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */ /** * @} */ @@ -696,6 +697,7 @@ #define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */ #define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */ #define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */ +#define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */ #define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */ #define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */ #define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */ @@ -746,17 +748,10 @@ #define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */ #define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */ #define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */ +#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */ -/* Elements values convention: 000000000XXYYYYYb - - YYYYY : Interrupt source position in the XX register (5bits) - - XX : Interrupt source register (2bits) - - 01: CR1 register - - 10: CR2 register - - 11: CR3 register */ #define UART_IT_ERR 0x0060U /*!< UART error interruption */ -/* Elements values convention: 0000ZZZZ00000000b - - ZZZZ : Flag position in the ISR register(4bits) */ #define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ #define UART_IT_NE 0x0200U /*!< UART noise error interruption */ #define UART_IT_FE 0x0100U /*!< UART frame error interruption */ @@ -778,6 +773,7 @@ #define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ #define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ #define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ +#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */ /** * @} */ @@ -816,9 +812,9 @@ */ #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ do{ \ - SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ - SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ - } while(0U) + SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ + } while(0U) /** @brief Clear the specified UART pending flag. * @param __HANDLE__ specifies the UART Handle. @@ -831,6 +827,7 @@ * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag * @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag * @arg @ref UART_CLEAR_CMF Character Match Clear Flag @@ -899,6 +896,7 @@ * @arg @ref UART_FLAG_TC Transmission Complete flag * @arg @ref UART_FLAG_RXNE Receive data register not empty flag * @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag + * @arg @ref UART_FLAG_RTOF Receiver Timeout flag * @arg @ref UART_FLAG_IDLE Idle Line detection flag * @arg @ref UART_FLAG_ORE Overrun Error flag * @arg @ref UART_FLAG_NE Noise Error flag @@ -925,6 +923,7 @@ * @arg @ref UART_IT_TC Transmission complete interrupt * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error) @@ -952,6 +951,7 @@ * @arg @ref UART_IT_TC Transmission complete interrupt * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) @@ -978,12 +978,14 @@ * @arg @ref UART_IT_TC Transmission complete interrupt * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) +#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) /** @brief Check whether the specified UART interrupt source is enabled or not. * @param __HANDLE__ specifies the UART Handle. @@ -1002,14 +1004,15 @@ * @arg @ref UART_IT_TC Transmission complete interrupt * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET) + (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET) /** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the UART Handle. @@ -1021,6 +1024,7 @@ * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag * @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag @@ -1165,13 +1169,16 @@ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U) +#if defined(LPUART1) /** @brief BRR division operation to set BRR register with LPUART. * @param __PCLK__ LPUART clock. * @param __BAUD__ Baud rate set by the user. * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U) + (uint32_t)((__BAUD__)/2U)) / (__BAUD__))) +#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U)\ + + (uint32_t)((__BAUD__)/2U)) / (__BAUD__))) +#endif /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ UART clock. @@ -1179,7 +1186,8 @@ * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U) + ((__BAUD__)/2U)) / (__BAUD__)) +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U)\ + + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief BRR division operation to set BRR register in 16-bit oversampling mode. * @param __PCLK__ UART clock. @@ -1187,13 +1195,16 @@ * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__))) + ((__BAUD__)/2U)) / (__BAUD__)) +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))\ + + ((__BAUD__)/2U)) / (__BAUD__)) +#if defined(LPUART1) /** @brief Check whether or not UART instance is Low Power UART. * @param __HANDLE__ specifies the UART Handle. * @retval SET (instance is LPUART) or RESET (instance isn't LPUART) */ #define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance)) +#endif /** @brief Check UART Baud rate. * @param __BAUDRATE__ Baudrate specified by the user. @@ -1225,6 +1236,7 @@ ((__STOPBITS__) == UART_STOPBITS_1_5) || \ ((__STOPBITS__) == UART_STOPBITS_2)) +#if defined(LPUART1) /** * @brief Ensure that LPUART frame number of stop bits is valid. * @param __STOPBITS__ LPUART frame number of stop bits. @@ -1232,6 +1244,7 @@ */ #define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \ ((__STOPBITS__) == UART_STOPBITS_2)) +#endif /** * @brief Ensure that UART frame parity is valid. @@ -1248,10 +1261,10 @@ * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) */ #define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ - (((__CONTROL__) == UART_HWCONTROL_NONE) || \ - ((__CONTROL__) == UART_HWCONTROL_RTS) || \ - ((__CONTROL__) == UART_HWCONTROL_CTS) || \ - ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) + (((__CONTROL__) == UART_HWCONTROL_NONE) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS) || \ + ((__CONTROL__) == UART_HWCONTROL_CTS) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) /** * @brief Ensure that UART communication mode is valid. @@ -1299,8 +1312,15 @@ * @param __TIMEOUT__ UART receiver timeout setting. * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) */ -#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ - ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) +#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ + ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) + +/** @brief Check the receiver timeout value. + * @note The maximum UART receiver timeout value is 0xFFFFFF. + * @param __TIMEOUTVALUE__ receiver timeout value. + * @retval Test result (TRUE or FALSE) + */ +#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) /** * @brief Ensure that UART LIN state is valid. @@ -1519,7 +1539,8 @@ /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ @@ -1568,12 +1589,17 @@ */ /* Peripheral Control functions ************************************************/ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue); +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart); + HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); + /** * @} */ @@ -1598,13 +1624,13 @@ /** @addtogroup UART_Private_Functions UART Private Functions * @{ */ - #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); /**
diff --git a/Inc/stm32wbxx_hal_uart_ex.h b/Inc/stm32wbxx_hal_uart_ex.h index 0564ccb..1544e69 100644 --- a/Inc/stm32wbxx_hal_uart_ex.h +++ b/Inc/stm32wbxx_hal_uart_ex.h
@@ -69,9 +69,9 @@ /** @defgroup UARTEx_Word_Length UARTEx Word Length * @{ */ -#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ -#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ -#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ +#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ +#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ +#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ /** * @} */ @@ -79,8 +79,8 @@ /** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length * @{ */ -#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ -#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ +#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ +#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ /** * @} */ @@ -89,8 +89,8 @@ * @brief UART FIFO mode * @{ */ -#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ -#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ /** * @} */ @@ -138,7 +138,8 @@ */ /* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime); +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime); /** * @} @@ -165,7 +166,9 @@ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); + HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); + HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); @@ -189,12 +192,13 @@ * @param __CLOCKSOURCE__ output variable. * @retval UART clocking source, written in __CLOCKSOURCE__. */ +#if defined (LPUART1) #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ case RCC_USART1CLKSOURCE_PCLK2: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ break; \ @@ -210,12 +214,12 @@ default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == LPUART1) \ { \ - switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ + { \ case RCC_LPUART1CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ @@ -231,13 +235,43 @@ default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else \ { \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) +#else +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#endif /* LPUART1 */ /** @brief Report the UART mask to apply to retrieve the received data * according to the word length and to the parity bits activation. @@ -250,44 +284,44 @@ */ #define UART_MASK_COMPUTATION(__HANDLE__) \ do { \ - if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ + if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x01FFU ; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x00FFU ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x00FFU ; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x007FU ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x007FU ; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x003FU ; \ - } \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x0000U; \ - } \ -} while(0U) + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) /** * @brief Ensure that UART frame length is valid.
diff --git a/Inc/stm32wbxx_ll_adc.h b/Inc/stm32wbxx_ll_adc.h index cb82769..4ceebba 100644 --- a/Inc/stm32wbxx_ll_adc.h +++ b/Inc/stm32wbxx_ll_adc.h
@@ -145,10 +145,10 @@ /* Mask containing trigger source masks for each of possible */ /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ -#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \ - ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \ - ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \ - ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) ) +#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \ + ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \ + ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \ + ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) ) /* Mask containing trigger edge masks for each of possible */ /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ @@ -367,7 +367,7 @@ * @retval Pointer to register address */ #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ - ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) + ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) /** * @} @@ -397,7 +397,7 @@ @note On this STM32 serie, if ADC group injected is used, some clock ratio constraints between ADC clock and AHB clock must be respected. Refer to reference manual. - + This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */ } LL_ADC_CommonInitTypeDef; @@ -426,17 +426,17 @@ { uint32_t Resolution; /*!< Set ADC resolution. This parameter can be a value of @ref ADC_LL_EC_RESOLUTION - + This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */ uint32_t DataAlignment; /*!< Set ADC conversion data alignment. This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN - + This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */ uint32_t LowPowerMode; /*!< Set ADC low power mode. This parameter can be a value of @ref ADC_LL_EC_LP_MODE - + This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */ } LL_ADC_InitTypeDef; @@ -467,36 +467,36 @@ @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge(). - + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */ uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH - + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */ uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE @note This parameter has an effect only if group regular sequencer is enabled (scan length of 2 ranks or more). - + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */ uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode. - + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */ uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER - + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */ uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun: data preserved or overwritten. This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR - + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */ } LL_ADC_REG_InitTypeDef; @@ -527,25 +527,25 @@ @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge(). - + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */ uint32_t SequencerLength; /*!< Set ADC group injected sequencer length. This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH - + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */ uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE @note This parameter has an effect only if group injected sequencer is enabled (scan length of 2 ranks or more). - + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */ uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular. This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO - Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. - + Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */ } LL_ADC_INJ_InitTypeDef; @@ -762,8 +762,8 @@ */ /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode -* @{ -*/ + * @{ + */ #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */ #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ /** @@ -783,8 +783,8 @@ /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data -* @{ -*/ + * @{ + */ #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */ #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */ /** @@ -878,8 +878,8 @@ */ /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode -* @{ -*/ + * @{ + */ #define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */ /** @@ -1109,7 +1109,7 @@ * above each literal definition. * @{ */ - + /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */ /* not timeout values. */ /* Timeout values for ADC operations are dependent to device clock */ @@ -1229,20 +1229,20 @@ * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR * @arg @ref LL_ADC_CHANNEL_VBAT - * + * * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). * @retval Value between Min_Data=0 and Max_Data=18 */ #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \ - ? ( \ + ? ( \ ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \ - ) \ - : \ - ( \ + ) \ + : \ + ( \ (uint32_t)POSITION_VAL((__CHANNEL__)) \ - ) \ + ) \ ) /** @@ -1275,7 +1275,7 @@ * @arg @ref LL_ADC_CHANNEL_VREFINT (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) * @arg @ref LL_ADC_CHANNEL_VBAT (4) - * + * * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n * (4) For ADC channel read back from ADC register, @@ -1284,17 +1284,17 @@ */ #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ (((__DECIMAL_NB__) <= 9UL) \ - ? ( \ + ? ( \ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ - ) \ - : \ - ( \ + ) \ + : \ + ( \ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ - ) \ + ) \ ) /** @@ -1337,7 +1337,7 @@ * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR * @arg @ref LL_ADC_CHANNEL_VBAT - * + * * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). @@ -1382,7 +1382,7 @@ * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR * @arg @ref LL_ADC_CHANNEL_VBAT - * + * * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). * @retval Returned value can be one of the following values: @@ -1469,7 +1469,7 @@ * @arg @ref LL_ADC_CHANNEL_VREFINT (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) * @arg @ref LL_ADC_CHANNEL_VBAT (4) - * + * * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n * (4) For ADC channel read back from ADC register, @@ -1550,17 +1550,17 @@ * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0) * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0) * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ - * + * * (0) On STM32WB, parameter available only on analog watchdog number: AWD1. */ #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ (((__GROUP__) == LL_ADC_GROUP_REGULAR) \ - ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \ - : \ - ((__GROUP__) == LL_ADC_GROUP_INJECTED) \ - ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \ - : \ - (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \ + ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \ + : \ + ((__GROUP__) == LL_ADC_GROUP_INJECTED) \ + ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \ + : \ + (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \ ) /** @@ -1588,7 +1588,7 @@ /** * @brief Helper macro to get the value of ADC analog watchdog threshold high - * or low in function of ADC resolution, when ADC resolution is + * or low in function of ADC resolution, when ADC resolution is * different of 12 bits. * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). * Example, with a ADC resolution of 8 bits, to get the value of @@ -1710,7 +1710,7 @@ /** * @brief Helper macro to convert the ADC conversion data from * a resolution to another resolution. - * @param __DATA__ ADC conversion data to be converted + * @param __DATA__ ADC conversion data to be converted * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted * This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B @@ -1784,10 +1784,9 @@ #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ __ADC_RESOLUTION__) \ (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ - / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ - (__ADC_RESOLUTION__), \ - LL_ADC_RESOLUTION_12B) \ - ) + / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ + (__ADC_RESOLUTION__), \ + LL_ADC_RESOLUTION_12B)) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) @@ -1960,7 +1959,7 @@ { /* Prevent unused argument(s) compilation warning */ (void)(Register); - + /* Retrieve address of register DR */ return (uint32_t)&(ADCx->DR); } @@ -1975,6 +1974,10 @@ /** * @brief Set parameter common to several ADC: Clock source and prescaler. + * @note ADC clock source and prescaler must be selected in function of system clock to not exceed ADC maximum frequency, depending on devices. + * Example: STM32WB55xx ADC maximum frequency is 64MHz (corresponding to 4.27Msmp/s maximum) + * Example: STM32WB50xx ADC maximum frequency is 32MHz (corresponding to 2.13Msmp/s maximum) + * For ADC maximum frequency, refer to datasheet of the selected device. * @note On this STM32 serie, if ADC group injected is used, some * clock ratio constraints between ADC clock and AHB clock * must be respected. @@ -2410,7 +2413,7 @@ * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR * @arg @ref LL_ADC_CHANNEL_VBAT - * + * * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF @@ -2419,7 +2422,7 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel) { register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - + MODIFY_REG(*preg, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1, ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); @@ -2476,7 +2479,7 @@ * @arg @ref LL_ADC_CHANNEL_VREFINT (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) * @arg @ref LL_ADC_CHANNEL_VBAT (4) - * + * * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n * (4) For ADC channel read back from ADC register, @@ -2486,7 +2489,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety) { register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - + return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); } @@ -2512,7 +2515,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety) { register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - + return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1); } @@ -2545,7 +2548,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState) { register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - + MODIFY_REG(*preg, ADC_OFR1_OFFSET1_EN, OffsetState); @@ -2571,7 +2574,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety) { register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - + return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN); } @@ -2589,12 +2592,12 @@ * internal (SW start) or from external peripheral (timer event, * external interrupt line). * @note On this STM32 serie, setting trigger source to external trigger - * also set trigger polarity to rising edge + * also set trigger polarity to rising edge * (default setting for compatibility with some ADC on other * STM32 families having this setting set by HW default value). * In case of need to modify trigger edge, use * function @ref LL_ADC_REG_SetTriggerEdge(). - * @note Availability of parameters of trigger sources from timer + * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. * @note On this STM32 serie, setting of this feature is conditioned to * ADC state: @@ -2627,10 +2630,10 @@ * @note To determine whether group regular trigger source is * internal (SW start) or external, without detail * of which peripheral is selected as external trigger, - * (equivalent to + * (equivalent to * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. - * @note Availability of parameters of trigger sources from timer + * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n * CFGR EXTEN LL_ADC_REG_GetTriggerSource @@ -2649,11 +2652,11 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) { register __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN); - + /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */ register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); - + /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */ /* to match with triggers literals definition. */ return ((TriggerSource @@ -2830,7 +2833,7 @@ * @brief Set ADC group regular sequencer discontinuous mode: * sequence subdivided and scan conversions interrupted every selected * number of ranks. - * @note It is not possible to enable both ADC group regular + * @note It is not possible to enable both ADC group regular * continuous mode and sequencer discontinuous mode. * @note It is not possible to enable both ADC auto-injected mode * and ADC group regular sequencer discontinuous mode. @@ -2958,7 +2961,7 @@ * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR * @arg @ref LL_ADC_CHANNEL_VBAT - * + * * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). * @retval None @@ -2970,7 +2973,7 @@ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); - + MODIFY_REG(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); @@ -3053,7 +3056,7 @@ * @arg @ref LL_ADC_CHANNEL_VREFINT (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) * @arg @ref LL_ADC_CHANNEL_VBAT (4) - * + * * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n * (4) For ADC channel read back from ADC register, @@ -3063,11 +3066,11 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) { register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); - - return (uint32_t) ((READ_BIT(*preg, + + return (uint32_t)((READ_BIT(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - ); + ); } /** @@ -3076,7 +3079,7 @@ * - single mode: one conversion per trigger * - continuous mode: after the first trigger, following * conversions launched successively automatically. - * @note It is not possible to enable both ADC group regular + * @note It is not possible to enable both ADC group regular * continuous mode and sequencer discontinuous mode. * @note On this STM32 serie, setting of this feature is conditioned to * ADC state: @@ -3235,12 +3238,12 @@ * internal (SW start) or from external peripheral (timer event, * external interrupt line). * @note On this STM32 serie, setting trigger source to external trigger - * also set trigger polarity to rising edge + * also set trigger polarity to rising edge * (default setting for compatibility with some ADC on other * STM32 families having this setting set by HW default value). * In case of need to modify trigger edge, use * function @ref LL_ADC_INJ_SetTriggerEdge(). - * @note Availability of parameters of trigger sources from timer + * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. * @note On this STM32 serie, setting of this feature is conditioned to * ADC state: @@ -3271,10 +3274,10 @@ * @note To determine whether group injected trigger source is * internal (SW start) or external, without detail * of which peripheral is selected as external trigger, - * (equivalent to + * (equivalent to * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart. - * @note Availability of parameters of trigger sources from timer + * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource @@ -3291,11 +3294,11 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) { register __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); - + /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */ register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL)); - + /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */ /* to match with triggers literals definition. */ return ((TriggerSource @@ -3483,7 +3486,7 @@ * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR * @arg @ref LL_ADC_CHANNEL_VBAT - * + * * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). * @retval None @@ -3548,7 +3551,7 @@ * @arg @ref LL_ADC_CHANNEL_VREFINT (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) * @arg @ref LL_ADC_CHANNEL_VBAT (4) - * + * * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n * (4) For ADC channel read back from ADC register, @@ -3558,8 +3561,8 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) { return (uint32_t)((READ_BIT(ADCx->JSQR, - (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) - >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS + (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) + >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ); } @@ -3567,18 +3570,18 @@ * @brief Set ADC group injected conversion trigger: * independent or from ADC group regular. * @note This mode can be used to extend number of data registers - * updated after one ADC conversion trigger and with data + * updated after one ADC conversion trigger and with data * permanently kept (not erased by successive conversions of scan of * ADC sequencer ranks), up to 5 data registers: * 1 data register on ADC group regular, 4 data registers - * on ADC group injected. + * on ADC group injected. * @note If ADC group injected injected trigger source is set to an * external trigger, this feature must be must be set to * independent trigger. - * ADC group injected automatic trigger is compliant only with - * group injected trigger source set to SW start, without any - * further action on ADC group injected conversion start or stop: - * in this case, ADC group injected is controlled only + * ADC group injected automatic trigger is compliant only with + * group injected trigger source set to SW start, without any + * further action on ADC group injected conversion start or stop: + * in this case, ADC group injected is controlled only * from ADC group regular. * @note It is not possible to enable both ADC group injected * auto-injected mode and sequencer discontinuous mode. @@ -3751,7 +3754,7 @@ * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR * @arg @ref LL_ADC_CHANNEL_VBAT - * + * * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). * @param Rank2_Channel This parameter can be one of the following values: @@ -3777,7 +3780,7 @@ * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR * @arg @ref LL_ADC_CHANNEL_VBAT - * + * * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). * @param Rank3_Channel This parameter can be one of the following values: @@ -3803,7 +3806,7 @@ * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR * @arg @ref LL_ADC_CHANNEL_VBAT - * + * * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). * @param Rank4_Channel This parameter can be one of the following values: @@ -3829,7 +3832,7 @@ * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR * @arg @ref LL_ADC_CHANNEL_VBAT - * + * * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). * @retval None @@ -3850,15 +3853,15 @@ /* If parameter "TriggerSource" is set to SW start, then parameter */ /* "ExternalTriggerEdge" is discarded. */ register uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL); - MODIFY_REG(ADCx->JSQR , + MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 | - ADC_JSQR_JL , - TriggerSource | + ADC_JSQR_JL, + (TriggerSource & ADC_JSQR_JEXTSEL) | (ExternalTriggerEdge * (is_trigger_not_sw)) | (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) | (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) | @@ -3945,7 +3948,7 @@ * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR * @arg @ref LL_ADC_CHANNEL_VBAT - * + * * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). * @param SamplingTime This parameter can be one of the following values: @@ -3966,7 +3969,7 @@ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); - + MODIFY_REG(*preg, ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)); @@ -4026,7 +4029,7 @@ * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR * @arg @ref LL_ADC_CHANNEL_VBAT - * + * * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). * @retval Returned value can be one of the following values: @@ -4042,7 +4045,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) { register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); - + return (uint32_t)(READ_BIT(*preg, ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)) >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS) @@ -4276,7 +4279,7 @@ * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0) * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0) * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ - * + * * (0) On STM32WB, parameter available only on analog watchdog number: AWD1. * @retval None */ @@ -4287,8 +4290,8 @@ /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ /* containing other bits reserved for other purpose. */ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) - + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); - + + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); + MODIFY_REG(*preg, (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), AWDChannelGroup & AWDy); @@ -4345,7 +4348,7 @@ * @arg @ref LL_ADC_AWD1 * @arg @ref LL_ADC_AWD2 (1) * @arg @ref LL_ADC_AWD3 (1) - * + * * (1) On this AWD number, monitored channel can be retrieved * if only 1 channel is programmed (or none or all channels). * This function cannot retrieve monitored channel if @@ -4413,28 +4416,28 @@ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ - * + * * (0) On STM32WB, parameter available only on analog watchdog number: AWD1. */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) { register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) - + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); - + + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); + register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); - + /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */ /* (parameter value LL_ADC_AWD_DISABLE). */ /* Else, the selected AWD is enabled and is monitoring a group of channels */ /* or a single channel. */ - if(AnalogWDMonitChannels != 0UL) + if (AnalogWDMonitChannels != 0UL) { - if(AWDy == LL_ADC_AWD1) + if (AWDy == LL_ADC_AWD1) { - if((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL) + if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL) { /* AWD monitoring a group of channels */ - AnalogWDMonitChannels = (( AnalogWDMonitChannels + AnalogWDMonitChannels = ((AnalogWDMonitChannels | (ADC_AWD_CR23_CHANNEL_MASK) ) & (~(ADC_CFGR_AWD1CH)) @@ -4450,10 +4453,10 @@ } else { - if((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK) + if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK) { /* AWD monitoring a group of channels */ - AnalogWDMonitChannels = ( ADC_AWD_CR23_CHANNEL_MASK + AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN)) ); } @@ -4461,14 +4464,14 @@ { /* AWD monitoring a single channel */ /* AWD monitoring a group of channels */ - AnalogWDMonitChannels = ( AnalogWDMonitChannels + AnalogWDMonitChannels = (AnalogWDMonitChannels | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos) ); } } } - + return AnalogWDMonitChannels; } @@ -4524,7 +4527,8 @@ * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ -__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue) +__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, + uint32_t AWDThresholdLowValue) { /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */ /* position in register and register position depending on parameter */ @@ -4532,7 +4536,7 @@ /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */ /* containing other bits reserved for other purpose. */ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); - + MODIFY_REG(*preg, ADC_TR1_HT1 | ADC_TR1_LT1, (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue); @@ -4592,7 +4596,8 @@ * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ -__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) +__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, + uint32_t AWDThresholdValue) { /* Set bits with content of parameter "AWDThresholdValue" with bits */ /* position in register and register position depending on parameters */ @@ -4600,7 +4605,7 @@ /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ /* containing other bits reserved for other purpose. */ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); - + MODIFY_REG(*preg, AWDThresholdsHighLow, AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)); @@ -4633,11 +4638,11 @@ * @arg @ref LL_ADC_AWD_THRESHOLD_LOW * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW * @retval Value between Min_Data=0x000 and Max_Data=0xFFF -*/ + */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) { register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); - + return (uint32_t)(READ_BIT(*preg, (AWDThresholdsHighLow | ADC_TR1_LT1)) >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR1_LT1)) @@ -4719,8 +4724,8 @@ * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. - * @note On this STM32 serie, oversampling discontinuous mode - * (triggered mode) can be used only when oversampling is + * @note On this STM32 serie, oversampling discontinuous mode + * (triggered mode) can be used only when oversampling is * set on group regular only and in resumed mode. * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont * @param ADCx ADC instance @@ -4806,7 +4811,7 @@ * @arg @ref LL_ADC_OVS_RATIO_64 * @arg @ref LL_ADC_OVS_RATIO_128 * @arg @ref LL_ADC_OVS_RATIO_256 -*/ + */ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)); @@ -4827,7 +4832,7 @@ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 -*/ + */ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS)); @@ -4947,7 +4952,7 @@ /** * @brief Enable the selected ADC instance. - * @note On this STM32 serie, after ADC enable, a delay for + * @note On this STM32 serie, after ADC enable, a delay for * ADC internal analog stabilization is required before performing a * ADC conversion start. * Refer to device datasheet, parameter tSTAB. @@ -5070,7 +5075,7 @@ /** * @brief Start ADC group regular conversion. - * @note On this STM32 serie, this function is relevant for both + * @note On this STM32 serie, this function is relevant for both * internal trigger (SW start) and external trigger: * - If ADC trigger has been set to software start, ADC conversion * starts immediately. @@ -5222,7 +5227,7 @@ /** * @brief Start ADC group injected conversion. - * @note On this STM32 serie, this function is relevant for both + * @note On this STM32 serie, this function is relevant for both * internal trigger (SW start) and external trigger: * - If ADC trigger has been set to software start, ADC conversion * starts immediately. @@ -5291,7 +5296,7 @@ } /** - * @brief Get ADC group regular conversion data, range fit for + * @brief Get ADC group injected conversion data, range fit for * all ADC configurations: all ADC resolutions and * all oversampling increased data width (for devices * with feature oversampling). @@ -5310,7 +5315,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) { register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); - + return (uint32_t)(READ_BIT(*preg, ADC_JDR1_JDATA) ); @@ -5337,7 +5342,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) { register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); - + return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) ); @@ -5364,7 +5369,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) { register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); - + return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) ); @@ -5391,7 +5396,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) { register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); - + return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) ); @@ -5418,7 +5423,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank) { register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); - + return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) );
diff --git a/Inc/stm32wbxx_ll_bus.h b/Inc/stm32wbxx_ll_bus.h index 047a3f0..825c83e 100644 --- a/Inc/stm32wbxx_ll_bus.h +++ b/Inc/stm32wbxx_ll_bus.h
@@ -23,11 +23,11 @@ ****************************************************************************** * @attention * - * <h2><center>© Copyright (c) 2019 STMicroelectronics. + * <h2><center>© Copyright (c) 2019 STMicroelectronics. * All rights reserved.</center></h2> * * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -73,8 +73,11 @@ * @{ */ #define LL_AHB1_GRP1_PERIPH_ALL (0xFFFFFFFFU) + #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN +#if defined(DMA2) #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN +#endif #define LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN @@ -87,14 +90,19 @@ * @{ */ #define LL_AHB2_GRP1_PERIPH_ALL (0xFFFFFFFFU) + #define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN #define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN #define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN +#if defined(GPIOD) #define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN +#endif #define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN #define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN #define LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN +#if defined(AES1) #define LL_AHB2_GRP1_PERIPH_AES1 RCC_AHB2ENR_AES1EN +#endif /** * @} */ @@ -103,7 +111,9 @@ * @{ */ #define LL_AHB3_GRP1_PERIPH_ALL (0xFFFFFFFFU) +#if defined(QUADSPI) #define LL_AHB3_GRP1_PERIPH_QUADSPI RCC_AHB3ENR_QUADSPIEN +#endif #define LL_AHB3_GRP1_PERIPH_PKA RCC_AHB3ENR_PKAEN #define LL_AHB3_GRP1_PERIPH_AES2 RCC_AHB3ENR_AES2EN #define LL_AHB3_GRP1_PERIPH_RNG RCC_AHB3ENR_RNGEN @@ -120,14 +130,24 @@ */ #define LL_APB1_GRP1_PERIPH_ALL (0xFFFFFFFFU) #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN +#if defined(LCD) #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR1_LCDEN +#endif #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN +#if defined(SPI2) #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN +#endif #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN +#if defined(I2C3) #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN +#endif +#if defined(CRS) #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN +#endif +#if defined(USB) #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBEN +#endif #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN /** * @} @@ -138,7 +158,10 @@ * @{ */ #define LL_APB1_GRP2_PERIPH_ALL (0xFFFFFFFFU) + +#if defined(LPUART1) #define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN +#endif #define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN /** * @} @@ -148,12 +171,15 @@ * @{ */ #define LL_APB2_GRP1_PERIPH_ALL (0xFFFFFFFFU) + #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN +#if defined(SAI1) #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN +#endif /** * @} */ @@ -172,7 +198,9 @@ * @{ */ #define LL_C2_AHB1_GRP1_PERIPH_DMA1 RCC_C2AHB1ENR_DMA1EN +#if defined(DMA2) #define LL_C2_AHB1_GRP1_PERIPH_DMA2 RCC_C2AHB1ENR_DMA2EN +#endif #define LL_C2_AHB1_GRP1_PERIPH_DMAMUX1 RCC_C2AHB1ENR_DMAMUX1EN #define LL_C2_AHB1_GRP1_PERIPH_SRAM1 RCC_C2AHB1ENR_SRAM1EN #define LL_C2_AHB1_GRP1_PERIPH_CRC RCC_C2AHB1ENR_CRCEN @@ -188,11 +216,15 @@ #define LL_C2_AHB2_GRP1_PERIPH_GPIOA RCC_C2AHB2ENR_GPIOAEN #define LL_C2_AHB2_GRP1_PERIPH_GPIOB RCC_C2AHB2ENR_GPIOBEN #define LL_C2_AHB2_GRP1_PERIPH_GPIOC RCC_C2AHB2ENR_GPIOCEN +#if defined(GPIOD) #define LL_C2_AHB2_GRP1_PERIPH_GPIOD RCC_C2AHB2ENR_GPIODEN +#endif #define LL_C2_AHB2_GRP1_PERIPH_GPIOE RCC_C2AHB2ENR_GPIOEEN #define LL_C2_AHB2_GRP1_PERIPH_GPIOH RCC_C2AHB2ENR_GPIOHEN #define LL_C2_AHB2_GRP1_PERIPH_ADC RCC_C2AHB2ENR_ADCEN +#if defined(AES1) #define LL_C2_AHB2_GRP1_PERIPH_AES1 RCC_C2AHB2ENR_AES1EN +#endif /** * @} */ @@ -217,13 +249,19 @@ * @{ */ #define LL_C2_APB1_GRP1_PERIPH_TIM2 RCC_C2APB1ENR1_TIM2EN +#if defined(LCD) #define LL_C2_APB1_GRP1_PERIPH_LCD RCC_C2APB1ENR1_LCDEN +#endif #define LL_C2_APB1_GRP1_PERIPH_RTCAPB RCC_C2APB1ENR1_RTCAPBEN +#if defined(SPI2) #define LL_C2_APB1_GRP1_PERIPH_SPI2 RCC_C2APB1ENR1_SPI2EN +#endif #define LL_C2_APB1_GRP1_PERIPH_I2C1 RCC_C2APB1ENR1_I2C1EN +#if defined(I2C3) #define LL_C2_APB1_GRP1_PERIPH_I2C3 RCC_C2APB1ENR1_I2C3EN #define LL_C2_APB1_GRP1_PERIPH_CRS RCC_C2APB1ENR1_CRSEN #define LL_C2_APB1_GRP1_PERIPH_USB RCC_C2APB1ENR1_USBEN +#endif #define LL_C2_APB1_GRP1_PERIPH_LPTIM1 RCC_C2APB1ENR1_LPTIM1EN /** * @} @@ -233,7 +271,9 @@ /** @defgroup BUS_LL_EC_C2_APB1_GRP2_PERIPH C2 APB1 GRP2 PERIPH * @{ */ +#if defined(LPUART1) #define LL_C2_APB1_GRP2_PERIPH_LPUART1 RCC_C2APB1ENR2_LPUART1EN +#endif #define LL_C2_APB1_GRP2_PERIPH_LPTIM2 RCC_C2APB1ENR2_LPTIM2EN /** * @} @@ -248,7 +288,9 @@ #define LL_C2_APB2_GRP1_PERIPH_USART1 RCC_C2APB2ENR_USART1EN #define LL_C2_APB2_GRP1_PERIPH_TIM16 RCC_C2APB2ENR_TIM16EN #define LL_C2_APB2_GRP1_PERIPH_TIM17 RCC_C2APB2ENR_TIM17EN +#if defined(SAI1) #define LL_C2_APB2_GRP1_PERIPH_SAI1 RCC_C2APB2ENR_SAI1EN +#endif /** * @} */
diff --git a/Inc/stm32wbxx_ll_comp.h b/Inc/stm32wbxx_ll_comp.h index 98304e8..fd8320a 100644 --- a/Inc/stm32wbxx_ll_comp.h +++ b/Inc/stm32wbxx_ll_comp.h
@@ -32,7 +32,7 @@ * @{ */ - +#if defined (COMP1) || defined (COMP2) /** @defgroup COMP_LL COMP * @{ @@ -747,7 +747,7 @@ * @} */ - +#endif /* COMP1 || COMP2 */ /** * @}
diff --git a/Inc/stm32wbxx_ll_dma.h b/Inc/stm32wbxx_ll_dma.h index 4689d87..fbe97e4 100644 --- a/Inc/stm32wbxx_ll_dma.h +++ b/Inc/stm32wbxx_ll_dma.h
@@ -53,19 +53,31 @@ * @param __CHANNEL_INDEX__ 0 to 6 to map DMAx_Channel1 to DMAx_Channel7 * @retval Pointer to the DMA channel */ +#if defined (DMA2) #define __LL_DMA_INSTANCE_TO_CHANNEL(__DMA_INSTANCE__, __CHANNEL_INDEX__) \ (((__DMA_INSTANCE__) == DMA1) ? (DMA1_Channel1 + (__CHANNEL_INDEX__)) : (DMA2_Channel1 + (__CHANNEL_INDEX__))) +#else +#define __LL_DMA_INSTANCE_TO_CHANNEL(__DMA_INSTANCE__, __CHANNEL_INDEX__) \ +(DMA1_Channel1 + (__CHANNEL_INDEX__)) +#endif /** * @brief Helper macro to convert DMA Instance and index into DMAMUX channel * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. +#if defined (DMA2) * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. +#endif * @param __DMA_INSTANCE__ DMAx * @param __CHANNEL_INDEX__ 0 to 6 to map DMAx_Channel1 to DMAx_Channel7 * @retval Pointer to the DMA channel */ +#if defined (DMA2) #define __LL_DMA_INSTANCE_TO_DMAMUX_CCR(__DMA_INSTANCE__, __CHANNEL_INDEX__)\ (((__DMA_INSTANCE__) == DMA1) ? (DMAMUX1_Channel0 + (__CHANNEL_INDEX__)) : (DMAMUX1_Channel7 + (__CHANNEL_INDEX__))) +#else +#define __LL_DMA_INSTANCE_TO_DMAMUX_CCR(__DMA_INSTANCE__, __CHANNEL_INDEX__)\ +(DMAMUX1_Channel0 + (__CHANNEL_INDEX__)) +#endif /** * @} */ @@ -1157,7 +1169,9 @@ /** * @brief Set DMA request for DMA Channels on DMAMUX Channel x. * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. +#if defined(DMA2) * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. +#endif * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: @@ -1220,7 +1234,9 @@ /** * @brief Get DMA request for DMA Channels on DMAMUX Channel x. * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. +#if defined(DMA2) * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. +#endif * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values:
diff --git a/Inc/stm32wbxx_ll_dmamux.h b/Inc/stm32wbxx_ll_dmamux.h index a00a513..a08aded 100644 --- a/Inc/stm32wbxx_ll_dmamux.h +++ b/Inc/stm32wbxx_ll_dmamux.h
@@ -70,6 +70,7 @@ #define LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4 /*!< Synchronization Event Overrun Flag Channel 4 */ #define LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5 /*!< Synchronization Event Overrun Flag Channel 5 */ #define LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6 /*!< Synchronization Event Overrun Flag Channel 6 */ +#if defined(DMA2) #define LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7 /*!< Synchronization Event Overrun Flag Channel 7 */ #define LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8 /*!< Synchronization Event Overrun Flag Channel 8 */ #define LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9 /*!< Synchronization Event Overrun Flag Channel 9 */ @@ -77,6 +78,7 @@ #define LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11 /*!< Synchronization Event Overrun Flag Channel 11 */ #define LL_DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12 /*!< Synchronization Event Overrun Flag Channel 12 */ #define LL_DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13 /*!< Synchronization Event Overrun Flag Channel 13 */ +#endif #define LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0 /*!< Request Generator 0 Trigger Event Overrun Flag */ #define LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1 /*!< Request Generator 1 Trigger Event Overrun Flag */ #define LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2 /*!< Request Generator 2 Trigger Event Overrun Flag */ @@ -96,6 +98,7 @@ #define LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4 /*!< Synchronization Event Overrun Flag Channel 4 */ #define LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5 /*!< Synchronization Event Overrun Flag Channel 5 */ #define LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6 /*!< Synchronization Event Overrun Flag Channel 6 */ +#if defined(DMA2) #define LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7 /*!< Synchronization Event Overrun Flag Channel 7 */ #define LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8 /*!< Synchronization Event Overrun Flag Channel 8 */ #define LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9 /*!< Synchronization Event Overrun Flag Channel 9 */ @@ -103,6 +106,7 @@ #define LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11 /*!< Synchronization Event Overrun Flag Channel 11 */ #define LL_DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12 /*!< Synchronization Event Overrun Flag Channel 12 */ #define LL_DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13 /*!< Synchronization Event Overrun Flag Channel 13 */ +#endif #define LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0 /*!< Request Generator 0 Trigger Event Overrun Flag */ #define LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1 /*!< Request Generator 1 Trigger Event Overrun Flag */ #define LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2 /*!< Request Generator 2 Trigger Event Overrun Flag */ @@ -132,19 +136,29 @@ #define LL_DMAMUX_REQ_ADC1 0x00000005U /*!< DMAMUX ADC1 request */ #define LL_DMAMUX_REQ_SPI1_RX 0x00000006U /*!< DMAMUX SPI1 RX request */ #define LL_DMAMUX_REQ_SPI1_TX 0x00000007U /*!< DMAMUX SPI1 TX request */ +#if defined(SPI2) #define LL_DMAMUX_REQ_SPI2_RX 0x00000008U /*!< DMAMUX SPI2 RX request */ #define LL_DMAMUX_REQ_SPI2_TX 0x00000009U /*!< DMAMUX SPI2 TX request */ +#endif #define LL_DMAMUX_REQ_I2C1_RX 0x0000000AU /*!< DMAMUX I2C1 RX request */ #define LL_DMAMUX_REQ_I2C1_TX 0x0000000BU /*!< DMAMUX I2C1 TX request */ +#if defined(I2C3) #define LL_DMAMUX_REQ_I2C3_RX 0x0000000CU /*!< DMAMUX I2C3 RX request */ #define LL_DMAMUX_REQ_I2C3_TX 0x0000000DU /*!< DMAMUX I2C3 TX request */ +#endif #define LL_DMAMUX_REQ_USART1_RX 0x0000000EU /*!< DMAMUX USART1 RX request */ #define LL_DMAMUX_REQ_USART1_TX 0x0000000FU /*!< DMAMUX USART1 TX request */ +#if defined(LPUART1) #define LL_DMAMUX_REQ_LPUART1_RX 0x00000010U /*!< DMAMUX LPUART1 RX request */ #define LL_DMAMUX_REQ_LPUART1_TX 0x00000011U /*!< DMAMUX LPUART1 TX request */ +#endif +#if defined(SAI1) #define LL_DMAMUX_REQ_SAI1_A 0x00000012U /*!< DMAMUX SAI1 A request */ #define LL_DMAMUX_REQ_SAI1_B 0x00000013U /*!< DMAMUX SAI1 B request */ +#endif +#if defined(QUADSPI) #define LL_DMAMUX_REQ_QUADSPI 0x00000014U /*!< DMAMUX QUADSPI request */ +#endif #define LL_DMAMUX_REQ_TIM1_CH1 0x00000015U /*!< DMAMUX TIM1 CH1 request */ #define LL_DMAMUX_REQ_TIM1_CH2 0x00000016U /*!< DMAMUX TIM1 CH2 request */ #define LL_DMAMUX_REQ_TIM1_CH3 0x00000017U /*!< DMAMUX TIM1 CH3 request */ @@ -161,8 +175,10 @@ #define LL_DMAMUX_REQ_TIM16_UP 0x00000022U /*!< DMAMUX TIM16 UP request */ #define LL_DMAMUX_REQ_TIM17_CH1 0x00000023U /*!< DMAMUX TIM17 CH1 request */ #define LL_DMAMUX_REQ_TIM17_UP 0x00000024U /*!< DMAMUX TIM17 UP request */ +#if defined(AES1) #define LL_DMAMUX_REQ_AES1_IN 0x00000025U /*!< DMAMUX AES1_IN request */ #define LL_DMAMUX_REQ_AES1_OUT 0x00000026U /*!< DMAMUX AES1_OUT request */ +#endif #define LL_DMAMUX_REQ_AES2_IN 0x00000027U /*!< DMAMUX AES2_IN request */ #define LL_DMAMUX_REQ_AES2_OUT 0x00000028U /*!< DMAMUX AES2_OUT request */ /** @@ -179,6 +195,7 @@ #define LL_DMAMUX_CHANNEL_4 0x00000004U /*!< DMAMUX Channel 4 connected to DMA1 Channel 5 */ #define LL_DMAMUX_CHANNEL_5 0x00000005U /*!< DMAMUX Channel 5 connected to DMA1 Channel 6 */ #define LL_DMAMUX_CHANNEL_6 0x00000006U /*!< DMAMUX Channel 6 connected to DMA1 Channel 7 */ +#if defined(DMA2) #define LL_DMAMUX_CHANNEL_7 0x00000007U /*!< DMAMUX Channel 7 connected to DMA2 Channel 1 */ #define LL_DMAMUX_CHANNEL_8 0x00000008U /*!< DMAMUX Channel 8 connected to DMA2 Channel 2 */ #define LL_DMAMUX_CHANNEL_9 0x00000009U /*!< DMAMUX Channel 9 connected to DMA2 Channel 3 */ @@ -186,6 +203,7 @@ #define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX Channel 11 connected to DMA2 Channel 5 */ #define LL_DMAMUX_CHANNEL_12 0x0000000CU /*!< DMAMUX Channel 12 connected to DMA2 Channel 6 */ #define LL_DMAMUX_CHANNEL_13 0x0000000DU /*!< DMAMUX Channel 13 connected to DMA2 Channel 7 */ +#endif /** * @} */ @@ -324,7 +342,9 @@ /** * @brief Set DMAMUX request ID for DMAMUX Channel x. * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. +#if defined(DMA2) * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. +#endif * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_SetRequestID * @param DMAMUXx DMAMUXx Instance * @param Channel This parameter can be one of the following values: @@ -335,6 +355,7 @@ * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 +#if defined(DMA2) * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -342,6 +363,7 @@ * @arg @ref LL_DMAMUX_CHANNEL_11 * @arg @ref LL_DMAMUX_CHANNEL_12 * @arg @ref LL_DMAMUX_CHANNEL_13 +#endif * @param Request This parameter can be one of the following values: * @arg @ref LL_DMAMUX_REQ_MEM2MEM * @arg @ref LL_DMAMUX_REQ_GENERATOR0 @@ -395,7 +417,9 @@ /** * @brief Get DMAMUX request ID for DMAMUX Channel x. * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. +#if defined(DMA2) * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. +#endif * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID * @param DMAMUXx DMAMUXx Instance * @param Channel This parameter can be one of the following values: @@ -561,6 +585,7 @@ * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 +#if defined(DMA2) * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -568,6 +593,7 @@ * @arg @ref LL_DMAMUX_CHANNEL_11 * @arg @ref LL_DMAMUX_CHANNEL_12 * @arg @ref LL_DMAMUX_CHANNEL_13 +#endif * @retval Returned value can be one of the following values: * @arg @ref LL_DMAMUX_SYNC_NO_EVENT * @arg @ref LL_DMAMUX_SYNC_POL_RISING @@ -592,6 +618,7 @@ * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 +#if defined(DMA2) * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -599,6 +626,7 @@ * @arg @ref LL_DMAMUX_CHANNEL_11 * @arg @ref LL_DMAMUX_CHANNEL_12 * @arg @ref LL_DMAMUX_CHANNEL_13 +#endif * @retval None */ __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) @@ -619,6 +647,7 @@ * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 +#if defined(DMA2) * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -626,6 +655,7 @@ * @arg @ref LL_DMAMUX_CHANNEL_11 * @arg @ref LL_DMAMUX_CHANNEL_12 * @arg @ref LL_DMAMUX_CHANNEL_13 +#endif * @retval None */ __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) @@ -646,6 +676,7 @@ * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 +#if defined(DMA2) * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -653,6 +684,7 @@ * @arg @ref LL_DMAMUX_CHANNEL_11 * @arg @ref LL_DMAMUX_CHANNEL_12 * @arg @ref LL_DMAMUX_CHANNEL_13 +#endif * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) @@ -673,6 +705,7 @@ * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 +#if defined(DMA2) * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -680,6 +713,7 @@ * @arg @ref LL_DMAMUX_CHANNEL_11 * @arg @ref LL_DMAMUX_CHANNEL_12 * @arg @ref LL_DMAMUX_CHANNEL_13 +#endif * @retval None */ __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) @@ -700,6 +734,7 @@ * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 +#if defined(DMA2) * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -707,6 +742,7 @@ * @arg @ref LL_DMAMUX_CHANNEL_11 * @arg @ref LL_DMAMUX_CHANNEL_12 * @arg @ref LL_DMAMUX_CHANNEL_13 +#endif * @retval None */ __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) @@ -727,6 +763,7 @@ * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 +#if defined(DMA2) * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -734,6 +771,7 @@ * @arg @ref LL_DMAMUX_CHANNEL_11 * @arg @ref LL_DMAMUX_CHANNEL_12 * @arg @ref LL_DMAMUX_CHANNEL_13 +#endif * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) @@ -754,6 +792,7 @@ * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 +#if defined(DMA2) * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -761,6 +800,7 @@ * @arg @ref LL_DMAMUX_CHANNEL_11 * @arg @ref LL_DMAMUX_CHANNEL_12 * @arg @ref LL_DMAMUX_CHANNEL_13 +#endif * @param SyncID This parameter can be one of the following values: * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1 @@ -802,6 +842,7 @@ * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 +#if defined(DMA2) * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -809,6 +850,7 @@ * @arg @ref LL_DMAMUX_CHANNEL_11 * @arg @ref LL_DMAMUX_CHANNEL_12 * @arg @ref LL_DMAMUX_CHANNEL_13 +#endif * @retval Returned value can be one of the following values: * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1 @@ -1502,6 +1544,7 @@ * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 +#if defined(DMA2) * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -1509,6 +1552,7 @@ * @arg @ref LL_DMAMUX_CHANNEL_11 * @arg @ref LL_DMAMUX_CHANNEL_12 * @arg @ref LL_DMAMUX_CHANNEL_13 +#endif * @retval None */ __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) @@ -1529,6 +1573,7 @@ * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 +#if defined(DMA2) * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -1536,6 +1581,7 @@ * @arg @ref LL_DMAMUX_CHANNEL_11 * @arg @ref LL_DMAMUX_CHANNEL_12 * @arg @ref LL_DMAMUX_CHANNEL_13 +#endif * @retval None */ __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) @@ -1556,6 +1602,7 @@ * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 +#if defined(DMA2) * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -1563,6 +1610,7 @@ * @arg @ref LL_DMAMUX_CHANNEL_11 * @arg @ref LL_DMAMUX_CHANNEL_12 * @arg @ref LL_DMAMUX_CHANNEL_13 +#endif * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
diff --git a/Inc/stm32wbxx_ll_exti.h b/Inc/stm32wbxx_ll_exti.h index bc38c6a..d2ef804 100644 --- a/Inc/stm32wbxx_ll_exti.h +++ b/Inc/stm32wbxx_ll_exti.h
@@ -113,18 +113,22 @@ #define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */ #define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */ #define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */ -#define LL_EXTI_LINE_26 EXTI_IMR1_IM26 /*!< Extended line 26 */ -#define LL_EXTI_LINE_27 EXTI_IMR1_IM27 /*!< Extended line 27 */ #define LL_EXTI_LINE_28 EXTI_IMR1_IM28 /*!< Extended line 28 */ #define LL_EXTI_LINE_29 EXTI_IMR1_IM29 /*!< Extended line 29 */ #define LL_EXTI_LINE_30 EXTI_IMR1_IM30 /*!< Extended line 30 */ #define LL_EXTI_LINE_31 EXTI_IMR1_IM31 /*!< Extended line 31 */ -#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR1_IM /*!< All Extended line not reserved*/ - -#define LL_EXTI_LINE_32 EXTI_IMR2_IM32 /*!< Extended line 32 */ +#define LL_EXTI_LINE_ALL_0_31 (LL_EXTI_LINE_0 | LL_EXTI_LINE_1 | LL_EXTI_LINE_2 | \ + LL_EXTI_LINE_3 | LL_EXTI_LINE_4 | LL_EXTI_LINE_5 | \ + LL_EXTI_LINE_6 | LL_EXTI_LINE_7 | LL_EXTI_LINE_8 | \ + LL_EXTI_LINE_9 | LL_EXTI_LINE_10 | LL_EXTI_LINE_11 | \ + LL_EXTI_LINE_12 | LL_EXTI_LINE_13 | LL_EXTI_LINE_14 | \ + LL_EXTI_LINE_15 | LL_EXTI_LINE_16 | LL_EXTI_LINE_17 | \ + LL_EXTI_LINE_18 | LL_EXTI_LINE_19 | LL_EXTI_LINE_20 | \ + LL_EXTI_LINE_21 | LL_EXTI_LINE_22 | LL_EXTI_LINE_23 | \ + LL_EXTI_LINE_24 | LL_EXTI_LINE_25 | LL_EXTI_LINE_28 | \ + LL_EXTI_LINE_29 | LL_EXTI_LINE_30 | LL_EXTI_LINE_31) /*!< All Extended line not reserved*/ + #define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */ -#define LL_EXTI_LINE_34 EXTI_IMR2_IM34 /*!< Extended line 34 */ -#define LL_EXTI_LINE_35 EXTI_IMR2_IM35 /*!< Extended line 35 */ #define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */ #define LL_EXTI_LINE_37 EXTI_IMR2_IM37 /*!< Extended line 37 */ #define LL_EXTI_LINE_38 EXTI_IMR2_IM38 /*!< Extended line 38 */ @@ -132,13 +136,25 @@ #define LL_EXTI_LINE_40 EXTI_IMR2_IM40 /*!< Extended line 40 */ #define LL_EXTI_LINE_41 EXTI_IMR2_IM41 /*!< Extended line 41 */ #define LL_EXTI_LINE_42 EXTI_IMR2_IM42 /*!< Extended line 42 */ +#if defined (STM32WB55xx) #define LL_EXTI_LINE_43 EXTI_IMR2_IM43 /*!< Extended line 43 */ +#endif #define LL_EXTI_LINE_44 EXTI_IMR2_IM44 /*!< Extended line 44 */ #define LL_EXTI_LINE_45 EXTI_IMR2_IM45 /*!< Extended line 45 */ #define LL_EXTI_LINE_46 EXTI_IMR2_IM46 /*!< Extended line 46 */ -#define LL_EXTI_LINE_47 EXTI_IMR2_IM47 /*!< Extended line 47 */ #define LL_EXTI_LINE_48 EXTI_IMR2_IM48 /*!< Extended line 48 */ -#define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM /*!< All Extended line not reserved*/ +#if defined (STM32WB55xx) +#define LL_EXTI_LINE_ALL_32_63 (LL_EXTI_LINE_33 | LL_EXTI_LINE_36 | LL_EXTI_LINE_37 | \ + LL_EXTI_LINE_38 | LL_EXTI_LINE_39 | LL_EXTI_LINE_40 | \ + LL_EXTI_LINE_41 | LL_EXTI_LINE_42 | LL_EXTI_LINE_43 | \ + LL_EXTI_LINE_44 | LL_EXTI_LINE_45 | LL_EXTI_LINE_46 | \ + LL_EXTI_LINE_48) /*!< All Extended line not reserved*/ +#else +#define LL_EXTI_LINE_ALL_32_63 (LL_EXTI_LINE_33 | LL_EXTI_LINE_36 | LL_EXTI_LINE_37 | \ + LL_EXTI_LINE_38 | LL_EXTI_LINE_39 | LL_EXTI_LINE_40 | \ + LL_EXTI_LINE_41 | LL_EXTI_LINE_42 | LL_EXTI_LINE_44 | \ + LL_EXTI_LINE_45 | LL_EXTI_LINE_46 | LL_EXTI_LINE_48) /*!< All Extended line not reserved*/ +#endif #define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ @@ -254,8 +270,6 @@ * @arg @ref LL_EXTI_LINE_23 * @arg @ref LL_EXTI_LINE_24 * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_26 - * @arg @ref LL_EXTI_LINE_27 * @arg @ref LL_EXTI_LINE_28 * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 @@ -298,8 +312,6 @@ * @arg @ref LL_EXTI_LINE_23 * @arg @ref LL_EXTI_LINE_24 * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_26 - * @arg @ref LL_EXTI_LINE_27 * @arg @ref LL_EXTI_LINE_28 * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 @@ -316,10 +328,7 @@ * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63 * @rmtoll IMR2 IMx LL_EXTI_EnableIT_32_63 * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_32 * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 - * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 @@ -327,13 +336,13 @@ * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 * @arg @ref LL_EXTI_LINE_42 - * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_43 (*) * @arg @ref LL_EXTI_LINE_44 * @arg @ref LL_EXTI_LINE_45 * @arg @ref LL_EXTI_LINE_46 - * @arg @ref LL_EXTI_LINE_47 * @arg @ref LL_EXTI_LINE_48 * @arg @ref LL_EXTI_LINE_ALL_32_63 + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) @@ -345,10 +354,7 @@ * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2 * @rmtoll C2IMR2 IMx LL_C2_EXTI_EnableIT_32_63 * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_32 * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 - * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 @@ -356,13 +362,13 @@ * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 * @arg @ref LL_EXTI_LINE_42 - * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_43 (*) * @arg @ref LL_EXTI_LINE_44 * @arg @ref LL_EXTI_LINE_45 * @arg @ref LL_EXTI_LINE_46 - * @arg @ref LL_EXTI_LINE_47 * @arg @ref LL_EXTI_LINE_48 * @arg @ref LL_EXTI_LINE_ALL_32_63 + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_C2_EXTI_EnableIT_32_63(uint32_t ExtiLine) @@ -400,8 +406,6 @@ * @arg @ref LL_EXTI_LINE_23 * @arg @ref LL_EXTI_LINE_24 * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_26 - * @arg @ref LL_EXTI_LINE_27 * @arg @ref LL_EXTI_LINE_28 * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 @@ -444,8 +448,6 @@ * @arg @ref LL_EXTI_LINE_23 * @arg @ref LL_EXTI_LINE_24 * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_26 - * @arg @ref LL_EXTI_LINE_27 * @arg @ref LL_EXTI_LINE_28 * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 @@ -462,10 +464,7 @@ * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63 * @rmtoll IMR2 IMx LL_EXTI_DisableIT_32_63 * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_32 * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 - * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 @@ -473,13 +472,13 @@ * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 * @arg @ref LL_EXTI_LINE_42 - * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_43 (*) * @arg @ref LL_EXTI_LINE_44 * @arg @ref LL_EXTI_LINE_45 * @arg @ref LL_EXTI_LINE_46 - * @arg @ref LL_EXTI_LINE_47 * @arg @ref LL_EXTI_LINE_48 * @arg @ref LL_EXTI_LINE_ALL_32_63 + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine) @@ -491,10 +490,7 @@ * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2 * @rmtoll C2IMR2 IMx LL_C2_EXTI_DisableIT_32_63 * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_32 * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 - * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 @@ -502,13 +498,13 @@ * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 * @arg @ref LL_EXTI_LINE_42 - * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_43 (*) * @arg @ref LL_EXTI_LINE_44 * @arg @ref LL_EXTI_LINE_45 * @arg @ref LL_EXTI_LINE_46 - * @arg @ref LL_EXTI_LINE_47 * @arg @ref LL_EXTI_LINE_48 * @arg @ref LL_EXTI_LINE_ALL_32_63 + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_C2_EXTI_DisableIT_32_63(uint32_t ExtiLine) @@ -546,8 +542,6 @@ * @arg @ref LL_EXTI_LINE_23 * @arg @ref LL_EXTI_LINE_24 * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_26 - * @arg @ref LL_EXTI_LINE_27 * @arg @ref LL_EXTI_LINE_28 * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 @@ -590,8 +584,6 @@ * @arg @ref LL_EXTI_LINE_23 * @arg @ref LL_EXTI_LINE_24 * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_26 - * @arg @ref LL_EXTI_LINE_27 * @arg @ref LL_EXTI_LINE_28 * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 @@ -608,10 +600,7 @@ * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 * @rmtoll IMR2 IMx LL_EXTI_IsEnabledIT_32_63 * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_32 * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 - * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 @@ -619,13 +608,13 @@ * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 * @arg @ref LL_EXTI_LINE_42 - * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_43 (*) * @arg @ref LL_EXTI_LINE_44 * @arg @ref LL_EXTI_LINE_45 * @arg @ref LL_EXTI_LINE_46 - * @arg @ref LL_EXTI_LINE_47 * @arg @ref LL_EXTI_LINE_48 * @arg @ref LL_EXTI_LINE_ALL_32_63 + * (*) value not defined in all devices * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) @@ -637,10 +626,7 @@ * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 for cpu2 * @rmtoll C2IMR2 IMx LL_C2_EXTI_IsEnabledIT_32_63 * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_32 * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 - * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 @@ -648,13 +634,13 @@ * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 * @arg @ref LL_EXTI_LINE_42 - * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_43 (*) * @arg @ref LL_EXTI_LINE_44 * @arg @ref LL_EXTI_LINE_45 * @arg @ref LL_EXTI_LINE_46 - * @arg @ref LL_EXTI_LINE_47 * @arg @ref LL_EXTI_LINE_48 * @arg @ref LL_EXTI_LINE_ALL_32_63 + * (*) value not defined in all devices * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) @@ -1171,13 +1157,11 @@ * @arg @ref LL_EXTI_LINE_14 * @arg @ref LL_EXTI_LINE_15 * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 * @arg @ref LL_EXTI_LINE_31 * @note Please check each device line mapping for EXTI Line availability * @retval None @@ -1198,10 +1182,9 @@ * condition. * @rmtoll FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_35 - * @arg @ref LL_EXTI_LINE_36 - * @arg @ref LL_EXTI_LINE_37 - * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 * @retval None */ __STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine) @@ -1236,13 +1219,11 @@ * @arg @ref LL_EXTI_LINE_14 * @arg @ref LL_EXTI_LINE_15 * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 * @arg @ref LL_EXTI_LINE_31 * @note Please check each device line mapping for EXTI Line availability * @retval None @@ -1262,10 +1243,9 @@ * In this case, both generate a trigger condition. * @rmtoll FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_35 - * @arg @ref LL_EXTI_LINE_36 - * @arg @ref LL_EXTI_LINE_37 - * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 * @retval None */ __STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine) @@ -1294,13 +1274,11 @@ * @arg @ref LL_EXTI_LINE_14 * @arg @ref LL_EXTI_LINE_15 * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 * @arg @ref LL_EXTI_LINE_31 * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). @@ -1314,10 +1292,9 @@ * @brief Check if falling edge trigger is enabled for Lines in range 32 to 63 * @rmtoll FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_35 - * @arg @ref LL_EXTI_LINE_36 - * @arg @ref LL_EXTI_LINE_37 - * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine) @@ -1359,13 +1336,11 @@ * @arg @ref LL_EXTI_LINE_14 * @arg @ref LL_EXTI_LINE_15 * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 * @arg @ref LL_EXTI_LINE_31 * @note Please check each device line mapping for EXTI Line availability * @retval None @@ -1384,10 +1359,9 @@ * register (by writing a 1 into the bit) * @rmtoll SWIER2 SWIx LL_EXTI_GenerateSWI_32_63 * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_35 - * @arg @ref LL_EXTI_LINE_36 - * @arg @ref LL_EXTI_LINE_37 - * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 * @retval None */ __STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine) @@ -1426,6 +1400,7 @@ * @arg @ref LL_EXTI_LINE_14 * @arg @ref LL_EXTI_LINE_15 * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 * @arg @ref LL_EXTI_LINE_20 @@ -1477,6 +1452,7 @@ * @arg @ref LL_EXTI_LINE_14 * @arg @ref LL_EXTI_LINE_15 * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 * @arg @ref LL_EXTI_LINE_20 @@ -1528,6 +1504,7 @@ * @arg @ref LL_EXTI_LINE_14 * @arg @ref LL_EXTI_LINE_15 * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 * @arg @ref LL_EXTI_LINE_20
diff --git a/Inc/stm32wbxx_ll_lptim.h b/Inc/stm32wbxx_ll_lptim.h index 06a67cf..57ddd38 100644 --- a/Inc/stm32wbxx_ll_lptim.h +++ b/Inc/stm32wbxx_ll_lptim.h
@@ -191,11 +191,19 @@ #define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/ #define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/ #define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/ +#if defined(RTC_TAMPER1_SUPPORT) #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/ +#endif /* RTC_TAMPER1_SUPPORT */ #define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/ +#if defined(RTC_TAMPER3_SUPPORT) #define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 3*/ +#endif /* RTC_TAMPER3_SUPPORT */ +#if defined(COMP1) #define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/ +#endif /* COMP1 */ +#if defined(COMP2) #define LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL /*!<External input trigger is connected to COMP2 output*/ +#endif /* COMP2 */ /** * @} */ @@ -281,7 +289,6 @@ * @} */ - /** * @} */ @@ -302,7 +309,7 @@ * @param __VALUE__ Value to be written in the register * @retval None */ -#define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->(__REG__), (__VALUE__)) +#define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) /** * @brief Read a value in LPTIM register @@ -310,7 +317,7 @@ * @param __REG__ Register to be read * @retval Register value */ -#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->(__REG__)) +#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) /** * @} */ @@ -467,7 +474,7 @@ * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled * @note After a write to the LPTIMx_ARR register a new write operation to the * same register can only be performed when the previous write operation - * is completed. Any successive write before the ARROK flag be set, will + * is completed. Any successive write before the ARROK flag is set, will * lead to unpredictable results. * @note autoreload value be strictly greater than the compare value. * @rmtoll ARR ARR LL_LPTIM_SetAutoReload @@ -495,7 +502,7 @@ * @brief Set the compare value * @note After a write to the LPTIMx_CMP register a new write operation to the * same register can only be performed when the previous write operation - * is completed. Any successive write before the CMPOK flag be set, will + * is completed. Any successive write before the CMPOK flag is set, will * lead to unpredictable results. * @rmtoll CMP CMP LL_LPTIM_SetCompare * @param LPTIMx Low-Power Timer instance @@ -787,11 +794,14 @@ * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB - * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1 + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (*) * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2 - * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3 - * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1 - * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2 + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (*) + * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1 (*) + * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2 (*) + * + * (*) Value not defined in all devices. \n + * * @param Filter This parameter can be one of the following values: * @arg @ref LL_LPTIM_TRIG_FILTER_NONE * @arg @ref LL_LPTIM_TRIG_FILTER_2 @@ -816,11 +826,14 @@ * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB - * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1 + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (*) * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2 - * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3 - * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1 - * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2 + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (*) + * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1 (*) + * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2 (*) + * + * (*) Value not defined in all devices. \n + * */ __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx) {
diff --git a/Inc/stm32wbxx_ll_lpuart.h b/Inc/stm32wbxx_ll_lpuart.h index 2d37e8c..c141442 100644 --- a/Inc/stm32wbxx_ll_lpuart.h +++ b/Inc/stm32wbxx_ll_lpuart.h
@@ -442,7 +442,8 @@ * @param __BAUDRATE__ Baud Rate value to achieve * @retval LPUARTDIV value to be used for BRR register filling */ -#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)])) * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK) +#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)])) * LPUART_LPUARTDIV_FREQ_MUL)\ + + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK) /** * @} @@ -1341,9 +1342,10 @@ * @param BaudRate Baud Rate * @retval None */ -__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t BaudRate) +__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t BaudRate) { - LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, (uint16_t)PrescalerValue, BaudRate); + LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate); } /** @@ -2485,12 +2487,12 @@ if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT) { /* return address of TDR register */ - data_reg_addr = (uint32_t) & (LPUARTx->TDR); + data_reg_addr = (uint32_t) &(LPUARTx->TDR); } else { /* return address of RDR register */ - data_reg_addr = (uint32_t) & (LPUARTx->RDR); + data_reg_addr = (uint32_t) &(LPUARTx->RDR); } return data_reg_addr; @@ -2566,7 +2568,7 @@ */ __STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->RQR, USART_RQR_SBKRQ); + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ); } /** @@ -2577,7 +2579,7 @@ */ __STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->RQR, USART_RQR_MMRQ); + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ); } /** @@ -2590,7 +2592,7 @@ */ __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->RQR, USART_RQR_RXFRQ); + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ); } /**
diff --git a/Inc/stm32wbxx_ll_pwr.h b/Inc/stm32wbxx_ll_pwr.h index 15955bd..5e7a297 100644 --- a/Inc/stm32wbxx_ll_pwr.h +++ b/Inc/stm32wbxx_ll_pwr.h
@@ -45,6 +45,8 @@ /** @defgroup PWR_LL_Private_Constants PWR Private Constants * @{ */ + +#if defined(PWR_CR5_SMPSEN) /** @defgroup PWR_SMPS_Calibration PWR SMPS calibration * @{ */ @@ -57,6 +59,7 @@ /** * @} */ +#endif /** * @} @@ -75,10 +78,16 @@ * @{ */ #define LL_PWR_SCR_CWUF PWR_SCR_CWUF +#if defined(PWR_CR3_EWUP2) #define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5 +#endif #define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4 +#if defined(PWR_CR3_EWUP3) #define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3 +#endif +#if defined(PWR_CR3_EWUP2) #define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2 +#endif #define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1 #define LL_PWR_SCR_CC2HF PWR_SCR_CC2HF #define LL_PWR_SCR_C802AF PWR_SCR_C802AF @@ -86,8 +95,10 @@ #define LL_PWR_SCR_CCRPEF PWR_SCR_CCRPEF #define LL_PWR_SCR_C802WUF PWR_SCR_C802WUF #define LL_PWR_SCR_CBLEWUF PWR_SCR_CBLEWUF +#if defined(PWR_CR5_SMPSEN) #define LL_PWR_SCR_CBORHF PWR_SCR_CBORHF #define LL_PWR_SCR_CSMPSFBF PWR_SCR_CSMPSFBF +#endif #define LL_PWR_EXTSCR_CCRPF PWR_EXTSCR_CCRPF #define LL_PWR_EXTSCR_C2CSSF PWR_EXTSCR_C2CSSF #define LL_PWR_EXTSCR_C1CSSF PWR_EXTSCR_C1CSSF @@ -100,25 +111,37 @@ * @{ */ #define LL_PWR_SR1_WUFI PWR_SR1_WUFI +#if defined(PWR_CR3_EWUP5) #define LL_PWR_SR1_WUF5 PWR_SR1_WUF5 +#endif #define LL_PWR_SR1_WUF4 PWR_SR1_WUF4 +#if defined(PWR_CR3_EWUP3) #define LL_PWR_SR1_WUF3 PWR_SR1_WUF3 +#endif +#if defined(PWR_CR3_EWUP2) #define LL_PWR_SR1_WUF2 PWR_SR1_WUF2 +#endif #define LL_PWR_SR1_WUF1 PWR_SR1_WUF1 #define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3 +#if defined(PWR_CR2_PVME1) #define LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1 +#endif #define LL_PWR_SR2_PVDO PWR_SR2_PVDO +#if defined(PWR_CR1_VOS) #define LL_PWR_SR2_VOSF PWR_SR2_VOSF +#endif #define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF #define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS /* BOR flags */ #define LL_PWR_FLAG_BORH PWR_SR1_BORHF /* BORH interrupt flag */ +#if defined(PWR_CR5_SMPSEN) /* SMPS flags */ #define LL_PWR_FLAG_SMPS PWR_SR2_SMPSF /* SMPS step down converter ready flag */ #define LL_PWR_FLAG_SMPSB PWR_SR2_SMPSBF /* SMPS step down converter in bypass mode flag */ #define LL_PWR_FLAG_SMPSFB PWR_SR1_SMPSFB /* SMPS step down converter forced in bypass mode interrupt flag */ +#endif /* Radio (BLE or 802.15.4) flags */ #define LL_PWR_FLAG_BLEWU PWR_SR1_BLEWUF /* BLE wakeup interrupt flag */ @@ -140,6 +163,7 @@ * @} */ +#if defined(PWR_CR1_VOS) /** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE * @{ */ @@ -148,6 +172,7 @@ /** * @} */ +#endif /** @defgroup PWR_LL_EC_MODE_PWR MODE PWR * @{ @@ -179,10 +204,12 @@ * @} */ -/** @defgroup PWR_LL_EC_PVM_VDDUSB_1 Peripheral voltage monitoring +/** @defgroup PWR_LL_EC_PVM Peripheral voltage monitoring * @{ */ +#if defined(PWR_CR2_PVME1) #define LL_PWR_PVM_VDDUSB_1_2V (PWR_CR2_PVME1) /* Monitoring VDDUSB vs. 1.2V */ +#endif #define LL_PWR_PVM_VDDA_1_62V (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */ /** * @} @@ -207,10 +234,16 @@ * @{ */ #define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1) +#if defined(PWR_CR3_EWUP2) #define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2) +#endif +#if defined(PWR_CR3_EWUP3) #define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3) +#endif #define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4) +#if defined(PWR_CR3_EWUP5) #define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5) +#endif /** * @} */ @@ -240,6 +273,7 @@ /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT * @{ */ +#if defined(PWR_PUCRC_PC0) /* Note: LL_PWR_GPIO_BIT_x defined from port C because all pins are available */ /* for PWR pull-up and pull-down. */ #define LL_PWR_GPIO_BIT_0 (PWR_PUCRC_PC0) @@ -258,10 +292,29 @@ #define LL_PWR_GPIO_BIT_13 (PWR_PUCRC_PC13) #define LL_PWR_GPIO_BIT_14 (PWR_PUCRC_PC14) #define LL_PWR_GPIO_BIT_15 (PWR_PUCRC_PC15) +#else +#define LL_PWR_GPIO_BIT_0 (PWR_PUCRA_PA0) +#define LL_PWR_GPIO_BIT_1 (PWR_PUCRA_PA1) +#define LL_PWR_GPIO_BIT_2 (PWR_PUCRA_PA2) +#define LL_PWR_GPIO_BIT_3 (PWR_PUCRA_PA3) +#define LL_PWR_GPIO_BIT_4 (PWR_PUCRA_PA4) +#define LL_PWR_GPIO_BIT_5 (PWR_PUCRA_PA5) +#define LL_PWR_GPIO_BIT_6 (PWR_PUCRA_PA6) +#define LL_PWR_GPIO_BIT_7 (PWR_PUCRA_PA7) +#define LL_PWR_GPIO_BIT_8 (PWR_PUCRA_PA8) +#define LL_PWR_GPIO_BIT_9 (PWR_PUCRA_PA9) +#define LL_PWR_GPIO_BIT_10 (PWR_PUCRA_PA10) +#define LL_PWR_GPIO_BIT_11 (PWR_PUCRA_PA11) +#define LL_PWR_GPIO_BIT_12 (PWR_PUCRA_PA12) +#define LL_PWR_GPIO_BIT_13 (PWR_PUCRA_PA13) +#define LL_PWR_GPIO_BIT_14 (PWR_PUCRC_PC14) +#define LL_PWR_GPIO_BIT_15 (PWR_PUCRC_PC15) +#endif /** * @} */ +#if defined(PWR_CR5_SMPSEN) /** @defgroup PWR_LL_EC_BOR_CONFIGURATION BOR configuration * @{ */ @@ -324,6 +377,7 @@ /** * @} */ +#endif /** * @} @@ -400,6 +454,7 @@ return ((READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)) ? 1UL : 0UL); } +#if defined(PWR_CR1_VOS) /** * @brief Set the main internal regulator output voltage * @note A delay is required for the internal regulator to be ready @@ -428,6 +483,7 @@ { return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS)); } +#endif /** * @brief Enable access to the backup domain @@ -544,6 +600,7 @@ return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_FPDS)); } +#if defined(PWR_CR2_PVME1) /** * @brief Enable VDDUSB supply * @rmtoll CR2 USV LL_PWR_EnableVddUSB @@ -573,15 +630,17 @@ { return ((READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)) ? 1UL : 0UL); } - +#endif /** * @brief Enable the Power Voltage Monitoring on a peripheral * @rmtoll CR2 PVME1 LL_PWR_EnablePVM\n * CR2 PVME3 LL_PWR_EnablePVM * @param PeriphVoltage This parameter can be one of the following values: - * @arg @ref LL_PWR_PVM_VDDUSB_1_2V + * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) * @arg @ref LL_PWR_PVM_VDDA_1_62V + * + * (*) Not available on devices STM32WB50xx * @retval None */ __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage) @@ -594,8 +653,10 @@ * @rmtoll CR2 PVME1 LL_PWR_DisablePVM\n * CR2 PVME3 LL_PWR_DisablePVM * @param PeriphVoltage This parameter can be one of the following values: - * @arg @ref LL_PWR_PVM_VDDUSB_1_2V + * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) * @arg @ref LL_PWR_PVM_VDDA_1_62V + * + * (*) Not available on devices STM32WB50xx * @retval None */ __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage) @@ -608,8 +669,10 @@ * @rmtoll CR2 PVME1 LL_PWR_IsEnabledPVM\n * CR2 PVME3 LL_PWR_IsEnabledPVM * @param PeriphVoltage This parameter can be one of the following values: - * @arg @ref LL_PWR_PVM_VDDUSB_1_2V + * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) * @arg @ref LL_PWR_PVM_VDDA_1_62V + * + * (*) Not available on devices STM32WB50xx * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage) @@ -783,10 +846,12 @@ * CR3 EWUP5 LL_PWR_EnableWakeUpPin\n * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN2 (*) + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) * @arg @ref LL_PWR_WAKEUP_PIN4 - * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * + * (*) Not available on devices STM32WB50xx * @retval None */ __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) @@ -803,10 +868,12 @@ * CR3 EWUP5 LL_PWR_DisableWakeUpPin\n * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN2 (*) + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) * @arg @ref LL_PWR_WAKEUP_PIN4 - * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * + * (*) Not available on devices STM32WB50xx * @retval None */ __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) @@ -823,10 +890,12 @@ * CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin\n * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN2 (*) + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) * @arg @ref LL_PWR_WAKEUP_PIN4 - * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * + * (*) Not available on devices STM32WB50xx * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) @@ -898,10 +967,12 @@ * CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN2 (*) + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) * @arg @ref LL_PWR_WAKEUP_PIN4 - * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * + * (*) Not available on devices STM32WB50xx * @retval None */ __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) @@ -918,10 +989,12 @@ * CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN2 (*) + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) * @arg @ref LL_PWR_WAKEUP_PIN4 - * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * + * (*) Not available on devices STM32WB50xx * @retval None */ __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) @@ -938,10 +1011,12 @@ * CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN2 (*) + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) * @arg @ref LL_PWR_WAKEUP_PIN4 - * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * + * (*) Not available on devices STM32WB50xx * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) @@ -1194,6 +1269,7 @@ return ((READ_BIT(*((uint32_t *)(temp)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL); } +#if defined(PWR_CR5_SMPSEN) /** * @brief Set BOR configuration * @rmtoll CR5 BORHC LL_PWR_SetBORConfig @@ -1217,11 +1293,13 @@ { return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_BORHC)); } +#endif /** * @} */ +#if defined(PWR_CR5_SMPSEN) /** @defgroup PWR_LL_EF_Configuration_SMPS Configuration of SMPS * @{ */ @@ -1434,12 +1512,12 @@ { OutputVoltageLevelTrimmed = 0; } - else if(OutputVoltageLevelTrimmed > (int32_t)PWR_CR5_SMPSVOS) - { - OutputVoltageLevelTrimmed = (int32_t)PWR_CR5_SMPSVOS; - } else { + if(OutputVoltageLevelTrimmed > (int32_t)PWR_CR5_SMPSVOS) + { + OutputVoltageLevelTrimmed = (int32_t)PWR_CR5_SMPSVOS; + } } /* Update register */ @@ -1510,6 +1588,7 @@ /** * @} */ +#endif /** @defgroup PWR_LL_EF_Configuration_Multicore Configuration of multicore, intended to be executed by CPU1 * @{ @@ -1680,10 +1759,12 @@ * C2CR3 EWUP5 LL_C2_PWR_EnableWakeUpPin * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN2 (*) + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) * @arg @ref LL_PWR_WAKEUP_PIN4 - * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * + * (*) Not available on devices STM32WB50xx * @retval None */ __STATIC_INLINE void LL_C2_PWR_EnableWakeUpPin(uint32_t WakeUpPin) @@ -1700,10 +1781,12 @@ * C2CR3 EWUP5 LL_C2_PWR_DisableWakeUpPin * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN2 (*) + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) * @arg @ref LL_PWR_WAKEUP_PIN4 - * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * + * (*) Not available on devices STM32WB50xx * @retval None */ __STATIC_INLINE void LL_C2_PWR_DisableWakeUpPin(uint32_t WakeUpPin) @@ -1720,10 +1803,12 @@ * C2CR3 EWUP5 LL_C2_PWR_IsEnabledWakeUpPin * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN2 (*) + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) * @arg @ref LL_PWR_WAKEUP_PIN4 - * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * + * (*) Not available on devices STM32WB50xx * @retval None */ __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) @@ -1833,6 +1918,7 @@ return ((READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)) ? 1UL : 0UL); } +#if defined(PWR_CR3_EWUP5) /** * @brief Get Wake-up Flag 5 * @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5 @@ -1842,6 +1928,7 @@ { return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL); } +#endif /** * @brief Get Wake-up Flag 4 @@ -1853,6 +1940,7 @@ return ((READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)) ? 1UL : 0UL); } +#if defined(PWR_CR3_EWUP3) /** * @brief Get Wake-up Flag 3 * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3 @@ -1862,7 +1950,9 @@ { return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL); } +#endif +#if defined(PWR_CR3_EWUP2) /** * @brief Get Wake-up Flag 2 * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2 @@ -1872,6 +1962,7 @@ { return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL); } +#endif /** * @brief Get Wake-up Flag 1 @@ -1893,6 +1984,7 @@ WRITE_REG(PWR->SCR, PWR_SCR_CWUF); } +#if defined(PWR_CR3_EWUP5) /** * @brief Clear Wake-up Flag 5 * @rmtoll SCR CWUF5 LL_PWR_ClearFlag_WU5 @@ -1902,6 +1994,7 @@ { WRITE_REG(PWR->SCR, PWR_SCR_CWUF5); } +#endif /** * @brief Clear Wake-up Flag 4 @@ -1913,6 +2006,7 @@ WRITE_REG(PWR->SCR, PWR_SCR_CWUF4); } +#if defined(PWR_CR3_EWUP3) /** * @brief Clear Wake-up Flag 3 * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3 @@ -1922,7 +2016,9 @@ { WRITE_REG(PWR->SCR, PWR_SCR_CWUF3); } +#endif +#if defined(PWR_CR3_EWUP2) /** * @brief Clear Wake-up Flag 2 * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2 @@ -1932,6 +2028,7 @@ { WRITE_REG(PWR->SCR, PWR_SCR_CWUF2); } +#endif /** * @brief Clear Wake-up Flag 1 @@ -1954,7 +2051,7 @@ return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3)) ? 1UL : 0UL); } - +#if defined(PWR_CR2_PVME1) /** * @brief Indicate whether VDDUSB voltage is below or above PVM1 threshold * @rmtoll SR2 PVMO1 LL_PWR_IsActiveFlag_PVMO1 @@ -1964,6 +2061,7 @@ { return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1)) ? 1UL : 0UL); } +#endif /** * @brief Indicate whether VDD voltage is below or above the selected PVD threshold @@ -1975,6 +2073,7 @@ return ((READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)) ? 1UL : 0UL); } +#if defined(PWR_CR1_VOS) /** * @brief Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level * @rmtoll SR2 VOSF LL_PWR_IsActiveFlag_VOS @@ -1984,6 +2083,7 @@ { return ((READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)) ? 1UL : 0UL); } +#endif /** * @brief Indicate whether the regulator is ready in main mode or is in low-power mode @@ -2030,6 +2130,7 @@ * @} */ +#if defined(PWR_CR5_SMPSEN) /** @defgroup PWR_LL_EF_FLAG_Management_SMPS FLAG management for SMPS * @{ */ @@ -2065,6 +2166,7 @@ /** * @} */ +#endif /** @defgroup PWR_LL_EF_FLAG_Management_Radio FLAG management for radio (BLE or 802.15.4) * @{ @@ -2301,6 +2403,7 @@ * @} */ +#if defined(PWR_CR5_SMPSEN) /** @defgroup PWR_LL_EF_IT_Management_SMPS PWR IT management for SMPS * @{ */ @@ -2345,6 +2448,7 @@ /** * @} */ +#endif /** @defgroup PWR_LL_EF_IT_Management_Radio PWR IT management for radio (BLE or 802.15.4) * @{
diff --git a/Inc/stm32wbxx_ll_rcc.h b/Inc/stm32wbxx_ll_rcc.h index c7631df..5a3b92b 100644 --- a/Inc/stm32wbxx_ll_rcc.h +++ b/Inc/stm32wbxx_ll_rcc.h
@@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - * <h2><center>© Copyright (c) 2019 STMicroelectronics. + * <h2><center>© Copyright (c) 2019 STMicroelectronics. * All rights reserved.</center></h2> * * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -140,7 +140,9 @@ #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */ #define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */ #define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */ +#if defined(SAI1) #define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC /*!< PLLSAI1 Ready Interrupt Clear */ +#endif #define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */ #define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */ /** @@ -159,7 +161,9 @@ #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ #define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ #define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ +#if defined(SAI1) #define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */ +#endif #define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ #define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ @@ -185,7 +189,9 @@ #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */ #define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */ #define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */ +#if defined(SAI1) #define LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE /*!< PLLSAI1 Ready Interrupt Enable */ +#endif #define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */ /** * @} @@ -448,9 +454,11 @@ #define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (0x00000000U >> 4)) /*!< PCLK1 selected as I2C1 clock */ #define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_0 >> 4)) /*!< SYSCLK selected as I2C1 clock */ #define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_1 >> 4)) /*!< HSI selected as I2C1 clock */ +#if defined(I2C3) #define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (0x00000000U >> 4)) /*!< PCLK1 selected as I2C3 clock */ #define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_0 >> 4)) /*!< SYSCLK selected as I2C3 clock */ #define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_1 >> 4)) /*!< HSI selected as I2C3 clock */ +#endif /** * @} */ @@ -485,7 +493,9 @@ * @{ */ #define LL_RCC_CLK48_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 selected as CLK48 clock*/ +#if defined(SAI1) #define LL_RCC_CLK48_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 selected as CLK48 clock*/ +#endif #define LL_RCC_CLK48_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL selected as CLK48 clock*/ #define LL_RCC_CLK48_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI selected as CLK48 clock*/ /** @@ -496,7 +506,9 @@ * @{ */ #define LL_RCC_USB_CLKSOURCE_HSI48 LL_RCC_CLK48_CLKSOURCE_HSI48 /*!< HSI48 selected as USB clock*/ +#if defined(SAI1) #define LL_RCC_USB_CLKSOURCE_PLLSAI1 LL_RCC_CLK48_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 selected as USB clock*/ +#endif #define LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CLK48_CLKSOURCE_PLL /*!< PLL selected as USB clock*/ #define LL_RCC_USB_CLKSOURCE_MSI LL_RCC_CLK48_CLKSOURCE_MSI /*!< MSI selected as USB clock*/ /** @@ -507,7 +519,9 @@ * @{ */ #define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /*!< no Clock used as ADC clock*/ +#if defined(SAI1) #define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 /*!< PLLSAI1 selected as ADC clock*/ +#endif #define LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_1 /*!< PLL selected as ADC clock*/ #define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK selected as ADC clock*/ /** @@ -532,6 +546,7 @@ * @} */ +#if defined(LPUART1) /** @defgroup RCC_LL_EC_LPUART1 LPUART1 * @{ */ @@ -539,6 +554,7 @@ /** * @} */ +#endif /** @defgroup RCC_LL_EC_I2C1 I2C1 * @{ @@ -558,6 +574,7 @@ * @} */ +#if defined(SAI1) /** @defgroup RCC_LL_EC_SAI1 SAI1 * @{ */ @@ -565,6 +582,7 @@ /** * @} */ +#endif /** @defgroup RCC_LL_EC_CLK48 CLK48 * @{ @@ -574,7 +592,6 @@ * @} */ - /** @defgroup RCC_LL_EC_USB USB * @{ */ @@ -846,6 +863,7 @@ #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ (((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U)) +#if defined(SAI1) /** * @brief Helper macro to calculate the PLLPCLK frequency used on SAI domain * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), @@ -896,7 +914,7 @@ */ #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U))/ \ (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U)) - +#endif /** * @brief Helper macro to calculate the PLLPCLK frequency used on ADC domain @@ -978,6 +996,7 @@ #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)) +#if defined(SAI1) /** * @brief Helper macro to calculate the PLLSAI1PCLK frequency used for SAI domain * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), @@ -1088,6 +1107,7 @@ #define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__) \ ((__INPUTFREQ__) * (__PLLSAI1N__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ (((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLR_Pos) + 1U)) +#endif /** * @brief Helper macro to calculate the HCLK1 frequency @@ -1908,7 +1928,7 @@ __STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void) { uint32_t msiRange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE); - if(msiRange > LL_RCC_MSIRANGE_11) + if (msiRange > LL_RCC_MSIRANGE_11) { msiRange = LL_RCC_MSIRANGE_11; } @@ -2081,11 +2101,11 @@ return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RFWKPSEL)); } - /** - * @brief Check if Radio System is reset. - * @rmtoll CSR RFRSTS LL_RCC_IsRFUnderReset - * @retval State of bit (1 or 0). - */ +/** + * @brief Check if Radio System is reset. + * @rmtoll CSR RFRSTS LL_RCC_IsRFUnderReset + * @retval State of bit (1 or 0). + */ __STATIC_INLINE uint32_t LL_RCC_IsRFUnderReset(void) { return ((READ_BIT(RCC->CSR, RCC_CSR_RFRSTS) == (RCC_CSR_RFRSTS)) ? 1UL : 0UL); @@ -2329,6 +2349,7 @@ * @} */ +#if defined(RCC_SMPS_SUPPORT) /** @defgroup RCC_LL_EF_SMPS SMPS * @{ */ @@ -2411,7 +2432,7 @@ /** * @} */ - +#endif /** @defgroup RCC_LL_EF_MCO MCO * @{ @@ -2469,6 +2490,7 @@ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, USARTxSource); } +#if defined(LPUART1) /** * @brief Configure LPUART1x clock source * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource @@ -2483,6 +2505,7 @@ { MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource); } +#endif /** * @brief Configure I2Cx clock source @@ -2520,6 +2543,7 @@ MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16)); } +#if defined(SAI1) /** * @brief Configure SAIx clock source * @rmtoll CCIPR SAI1SEL LL_RCC_SetSAIClockSource @@ -2534,6 +2558,7 @@ { MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, SAIxSource); } +#endif /** * @brief Configure RNG clock source @@ -2565,7 +2590,6 @@ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, CLK48xSource); } - /** * @brief Configure USB clock source * @rmtoll CCIPR CLK48SEL LL_RCC_SetUSBClockSource @@ -2640,6 +2664,7 @@ return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx)); } +#if defined(LPUART1) /** * @brief Get LPUARTx clock source * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource @@ -2655,6 +2680,7 @@ { return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx)); } +#endif /** * @brief Get I2Cx clock source @@ -2696,6 +2722,7 @@ return (uint32_t)((READ_BIT(RCC->CCIPR, LPTIMx) >> 16) | LPTIMx); } +#if defined(SAI1) /** * @brief Get SAIx clock source * @rmtoll CCIPR SAI1SEL LL_RCC_GetSAIClockSource @@ -2711,6 +2738,7 @@ { return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx)); } +#endif /** * @brief Get RNGx clock source @@ -2743,7 +2771,6 @@ return (uint32_t)(READ_BIT(RCC->CCIPR, CLK48x)); } - /** * @brief Get USBx clock source * @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource @@ -2943,6 +2970,7 @@ Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR); } +#if defined(SAI1) /** * @brief Configure PLL used for SAI domain clock * @note PLL Source and PLLM Divider can be written only when PLL is disabled @@ -3006,6 +3034,7 @@ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP, Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP); } +#endif /** * @brief Configure PLL used for ADC domain clock @@ -3218,6 +3247,7 @@ return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); } +#if defined(SAI1) /** * @brief Enable PLL output mapped on SAI domain clock * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_SAI @@ -3239,6 +3269,7 @@ { CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN); } +#endif /** * @brief Enable PLL output mapped on ADC domain clock @@ -3312,6 +3343,7 @@ * @} */ +#if defined(SAI1) /** @defgroup RCC_LL_EF_PLLSAI1 PLLSAI1 * @{ */ @@ -3495,34 +3527,6 @@ } /** - * @brief Configure PLL clock source - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource - * @param PLLSource This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_MSI - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) -{ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource); -} - -/** - * @brief Get the oscillator used as PLL clock source. - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_NONE - * @arg @ref LL_RCC_PLLSOURCE_MSI - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); -} - -/** * @brief Get SAI1PLL multiplication factor for VCO * @rmtoll PLLSAI1CFGR PLLN LL_RCC_PLLSAI1_GetN * @retval Between 8 and 86 @@ -3676,6 +3680,7 @@ { CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLREN); } +#endif /** * @} @@ -3748,6 +3753,34 @@ } /** + * @brief Configure PLL clock source + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource + * @param PLLSource This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); +} + +/** * @brief Clear PLL ready interrupt flag * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY * @retval None @@ -3767,6 +3800,7 @@ SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC); } +#if defined(SAI1) /** * @brief Clear PLLSAI1 ready interrupt flag * @rmtoll CICR PLLSAI1RDYC LL_RCC_ClearFlag_PLLSAI1RDY @@ -3776,6 +3810,7 @@ { SET_BIT(RCC->CICR, RCC_CICR_PLLSAI1RDYC); } +#endif /** * @brief Clear Clock security system interrupt flag @@ -3877,6 +3912,7 @@ return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL); } +#if defined(SAI1) /** * @brief Check if PLLSAI1 ready interrupt occurred or not * @rmtoll CIFR PLLSAI1RDYF LL_RCC_IsActiveFlag_PLLSAI1RDY @@ -3886,6 +3922,7 @@ { return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == (RCC_CIFR_PLLSAI1RDYF)) ? 1UL : 0UL); } +#endif /** * @brief Check if Clock security system interrupt occurred or not @@ -4125,6 +4162,7 @@ SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); } +#if defined(SAI1) /** * @brief Enable PLLSAI1 ready interrupt * @rmtoll CIER PLLSAI1RDYIE LL_RCC_EnableIT_PLLSAI1RDY @@ -4134,6 +4172,7 @@ { SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE); } +#endif /** * @brief Enable LSE clock security system interrupt @@ -4224,6 +4263,7 @@ CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); } +#if defined(SAI1) /** * @brief Disable PLLSAI1 ready interrupt * @rmtoll CIER PLLSAI1RDYIE LL_RCC_DisableIT_PLLSAI1RDY @@ -4233,6 +4273,7 @@ { CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE); } +#endif /** * @brief Disable LSE clock security system interrupt @@ -4323,6 +4364,7 @@ return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE)) ? 1UL : 0UL); } +#if defined(SAI1) /** * @brief Checks if PLLSAI1 ready interrupt source is enabled or disabled. * @rmtoll CIER PLLSAI1RDYIE LL_RCC_IsEnabledIT_PLLSAI1RDY @@ -4332,6 +4374,7 @@ { return ((READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == (RCC_CIER_PLLSAI1RDYIE)) ? 1UL : 0UL); } +#endif /** * @brief Checks if LSECSS interrupt source is enabled or disabled. @@ -4363,9 +4406,13 @@ uint32_t LL_RCC_GetSMPSClockFreq(void); uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); +#if defined(LPUART1) uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource); +#endif uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); +#if defined(SAI1) uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); +#endif uint32_t LL_RCC_GetCLK48ClockFreq(uint32_t CLK48xSource); uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
diff --git a/Inc/stm32wbxx_ll_rtc.h b/Inc/stm32wbxx_ll_rtc.h index c37c081..d54fff6 100644 --- a/Inc/stm32wbxx_ll_rtc.h +++ b/Inc/stm32wbxx_ll_rtc.h
@@ -234,9 +234,15 @@ */ #define LL_RTC_ISR_ITSF RTC_ISR_ITSF #define LL_RTC_ISR_RECALPF RTC_ISR_RECALPF +#if defined(RTC_TAMPER3_SUPPORT) #define LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F +#endif +#if defined(RTC_TAMPER2_SUPPORT) #define LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F +#endif +#if defined(RTC_TAMPER1_SUPPORT) #define LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F +#endif #define LL_RTC_ISR_TSOVF RTC_ISR_TSOVF #define LL_RTC_ISR_TSF RTC_ISR_TSF #define LL_RTC_ISR_WUTF RTC_ISR_WUTF @@ -261,9 +267,15 @@ #define LL_RTC_CR_WUTIE RTC_CR_WUTIE #define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE #define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE +#if defined(RTC_TAMPER3_SUPPORT) #define LL_RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE +#endif +#if defined(RTC_TAMPER2_SUPPORT) #define LL_RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE +#endif +#if defined(RTC_TAMPER1_SUPPORT) #define LL_RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE +#endif #define LL_RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE /** * @} @@ -427,7 +439,9 @@ #define LL_RTC_TAMPER_1 RTC_TAMPCR_TAMP1E /*!< RTC_TAMP1 input detection */ #endif /* RTC_TAMPER1_SUPPORT */ #if defined(RTC_TAMPER2_SUPPORT) +#if defined(RTC_TAMPER2_SUPPORT) #define LL_RTC_TAMPER_2 RTC_TAMPCR_TAMP2E /*!< RTC_TAMP2 input detection */ +#endif #endif /* RTC_TAMPER2_SUPPORT */ #if defined(RTC_TAMPER3_SUPPORT) #define LL_RTC_TAMPER_3 RTC_TAMPCR_TAMP3E /*!< RTC_TAMP3 input detection */ @@ -2641,10 +2655,12 @@ * TAMPCR TAMP3E LL_RTC_TAMPER_Enable * @param RTCx RTC Instance * @param Tamper This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_1 + * @arg @ref LL_RTC_TAMPER_1 (*) * @arg @ref LL_RTC_TAMPER_2 - * @arg @ref LL_RTC_TAMPER_3 - * + * @arg @ref LL_RTC_TAMPER_3 (*) + * + * (*) Value not defined in all devices. \n + * * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper) @@ -2659,10 +2675,12 @@ * TAMPCR TAMP3E LL_RTC_TAMPER_Disable * @param RTCx RTC Instance * @param Tamper This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_1 + * @arg @ref LL_RTC_TAMPER_1 (*) * @arg @ref LL_RTC_TAMPER_2 - * @arg @ref LL_RTC_TAMPER_3 - * + * @arg @ref LL_RTC_TAMPER_3 (*) + * + * (*) Value not defined in all devices. \n + * * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper) @@ -2678,10 +2696,12 @@ * TAMPCR TAMP3MF LL_RTC_TAMPER_EnableMask * @param RTCx RTC Instance * @param Mask This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 (*) * @arg @ref LL_RTC_TAMPER_MASK_TAMPER2 - * @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 - * + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 (*) + * + * (*) Value not defined in all devices. \n + * * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask) @@ -2696,10 +2716,12 @@ * TAMPCR TAMP3MF LL_RTC_TAMPER_DisableMask * @param RTCx RTC Instance * @param Mask This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 (*) * @arg @ref LL_RTC_TAMPER_MASK_TAMPER2 - * @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 - * + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 (*) + * + * (*) Value not defined in all devices. \n + * * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask) @@ -2714,10 +2736,12 @@ * TAMPCR TAMP3NOERASE LL_RTC_TAMPER_EnableEraseBKP * @param RTCx RTC Instance * @param Tamper This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 (*) * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2 - * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 - * + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 (*) + * + * (*) Value not defined in all devices. \n + * * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper) @@ -2732,10 +2756,12 @@ * TAMPCR TAMP3NOERASE LL_RTC_TAMPER_DisableEraseBKP * @param RTCx RTC Instance * @param Tamper This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 (*) * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2 - * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 - * + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 (*) + * + * (*) Value not defined in all devices. \n + * * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper)
diff --git a/Inc/stm32wbxx_ll_spi.h b/Inc/stm32wbxx_ll_spi.h index b422ce3..65ddb0f 100644 --- a/Inc/stm32wbxx_ll_spi.h +++ b/Inc/stm32wbxx_ll_spi.h
@@ -1314,7 +1314,7 @@ */ __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) { - return (uint32_t) & (SPIx->DR); + return (uint32_t) &(SPIx->DR); } /** @@ -1361,7 +1361,7 @@ *spidr = TxData; #else *((__IO uint8_t *)&SPIx->DR) = TxData; -#endif +#endif /* __GNUC__ */ } /** @@ -1378,7 +1378,7 @@ *spidr = TxData; #else SPIx->DR = TxData; -#endif +#endif /* __GNUC__ */ } /**
diff --git a/Inc/stm32wbxx_ll_system.h b/Inc/stm32wbxx_ll_system.h index ca28496..2a313c8 100644 --- a/Inc/stm32wbxx_ll_system.h +++ b/Inc/stm32wbxx_ll_system.h
@@ -77,7 +77,9 @@ #define LL_SYSCFG_REMAP_FLASH 0x00000000U /*!< Main Flash memory mapped at 0x00000000 */ #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */ #define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */ +#if defined(QUADSPI) #define LL_SYSCFG_REMAP_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) /*!< QUADSPI memory mapped at 0x00000000 */ +#endif /** * @} */ @@ -90,7 +92,9 @@ #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ +#if defined(I2C3) #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ +#endif /** * @} */ @@ -238,7 +242,9 @@ #define LL_SYSCFG_GRP1_EXTI14 SYSCFG_IMR1_EXTI14IM /*!< Enabling of interrupt from External Interrupt Line 14 to CPU1 */ #define LL_SYSCFG_GRP1_EXTI15 SYSCFG_IMR1_EXTI15IM /*!< Enabling of interrupt from External Interrupt Line 15 to CPU1 */ +#if defined(SYSCFG_IMR2_PVM1IM) #define LL_SYSCFG_GRP2_PVM1 SYSCFG_IMR2_PVM1IM /*!< Enabling of interrupt from Power Voltage Monitoring 1 to CPU1 */ +#endif #define LL_SYSCFG_GRP2_PVM3 SYSCFG_IMR2_PVM3IM /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU1 */ #define LL_SYSCFG_GRP2_PVD SYSCFG_IMR2_PVDIM /*!< Enabling of interrupt from Power Voltage Detector to CPU1 */ /** @@ -256,8 +262,12 @@ #define LL_C2_SYSCFG_GRP1_FLASH SYSCFG_C2IMR1_FLASHIM /*!< Enabling of interrupt from FLASH to CPU2 */ #define LL_C2_SYSCFG_GRP1_PKA SYSCFG_C2IMR1_PKAIM /*!< Enabling of interrupt from Public Key Accelerator to CPU2 */ #define LL_C2_SYSCFG_GRP1_RNG SYSCFG_C2IMR1_RNGIM /*!< Enabling of interrupt from Random Number Generator to CPU2 */ +#if defined(AES1) #define LL_C2_SYSCFG_GRP1_AES1 SYSCFG_C2IMR1_AES1IM /*!< Enabling of interrupt from Advanced Encryption Standard 1 to CPU2 */ +#endif +#if defined(COMP1) #define LL_C2_SYSCFG_GRP1_COMP SYSCFG_C2IMR1_COMPIM /*!< Enabling of interrupt from Comparator to CPU2 */ +#endif #define LL_C2_SYSCFG_GRP1_ADC SYSCFG_C2IMR1_ADCIM /*!< Enabling of interrupt from Analog Digital Converter to CPU2 */ #define LL_C2_SYSCFG_GRP1_EXTI0 SYSCFG_C2IMR1_EXTI0IM /*!< Enabling of interrupt from External Interrupt Line 0 to CPU2 */ @@ -285,6 +295,7 @@ #define LL_C2_SYSCFG_GRP2_DMA1CH6 SYSCFG_C2IMR2_DMA1CH6IM /*!< Enabling of interrupt from DMA1 Channel 6 to CPU2 */ #define LL_C2_SYSCFG_GRP2_DMA1CH7 SYSCFG_C2IMR2_DMA1CH7IM /*!< Enabling of interrupt from DMA1 Channel 7 to CPU2 */ +#if defined(DMA2) #define LL_C2_SYSCFG_GRP2_DMA2CH1 SYSCFG_C2IMR2_DMA2CH1IM /*!< Enabling of interrupt from DMA2 Channel 1 to CPU2 */ #define LL_C2_SYSCFG_GRP2_DMA2CH2 SYSCFG_C2IMR2_DMA2CH2IM /*!< Enabling of interrupt from DMA2 Channel 2 to CPU2 */ #define LL_C2_SYSCFG_GRP2_DMA2CH3 SYSCFG_C2IMR2_DMA2CH3IM /*!< Enabling of interrupt from DMA2 Channel 3 to CPU2 */ @@ -292,13 +303,18 @@ #define LL_C2_SYSCFG_GRP2_DMA2CH5 SYSCFG_C2IMR2_DMA2CH5IM /*!< Enabling of interrupt from DMA2 Channel 5 to CPU2 */ #define LL_C2_SYSCFG_GRP2_DMA2CH6 SYSCFG_C2IMR2_DMA2CH6IM /*!< Enabling of interrupt from DMA2 Channel 6 to CPU2 */ #define LL_C2_SYSCFG_GRP2_DMA2CH7 SYSCFG_C2IMR2_DMA2CH7IM /*!< Enabling of interrupt from DMA2 Channel 7 to CPU2 */ +#endif #define LL_C2_SYSCFG_GRP2_DMAMUX1 SYSCFG_C2IMR2_DMAMUX1IM /*!< Enabling of interrupt from DMAMUX1 to CPU2 */ +#if defined(SYSCFG_C2IMR2_PVM1IM) #define LL_C2_SYSCFG_GRP2_PVM1 SYSCFG_C2IMR2_PVM1IM /*!< Enabling of interrupt from Power Voltage Monitoring 1 to CPU2 */ +#endif #define LL_C2_SYSCFG_GRP2_PVM3 SYSCFG_C2IMR2_PVM3IM /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU2 */ #define LL_C2_SYSCFG_GRP2_PVD SYSCFG_C2IMR2_PVDIM /*!< Enabling of interrupt from Power Voltage Detector to CPU2 */ #define LL_C2_SYSCFG_GRP2_TSC SYSCFG_C2IMR2_TSCIM /*!< Enabling of interrupt from Touch Sensing Controller to CPU2 */ +#if defined(LCD) #define LL_C2_SYSCFG_GRP2_LCD SYSCFG_C2IMR2_LCDIM /*!< Enabling of interrupt from Liquid Crystal Display to CPU2 */ +#endif /** * @} */ @@ -306,7 +322,9 @@ /** @defgroup SYSTEM_LL_EC_SECURE_IP_ACCESS SYSCFG SECURE IP ACCESS * @{ */ +#if defined(AES1) #define LL_SYSCFG_SECURE_ACCESS_AES1 SYSCFG_SIPCR_SAES1 /*!< Enabling the security access of Advanced Encryption Standard 1 KEY[7:0] */ +#endif #define LL_SYSCFG_SECURE_ACCESS_AES2 SYSCFG_SIPCR_SAES2 /*!< Enabling the security access of Advanced Encryption Standard 2 */ #define LL_SYSCFG_SECURE_ACCESS_PKA SYSCFG_SIPCR_SPKA /*!< Enabling the security access of Public Key Accelerator */ #define LL_SYSCFG_SECURE_ACCESS_RNG SYSCFG_SIPCR_SRNG /*!< Enabling the security access of Random Number Generator */ @@ -322,7 +340,9 @@ #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /*!< The window watchdog counter clock is stopped when the core is halted */ #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted */ #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen */ +#if defined(I2C3) #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP /*!< The I2C3 SMBus timeout is frozen */ +#endif #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted */ /** * @} @@ -335,7 +355,9 @@ #define LL_C2_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_C2APB1FZR1_DBG_RTC_STOP /*!< The clock of the RTC counter is stopped when the core is halted */ #define LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_C2APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted */ #define LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_C2APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen */ +#if defined(I2C3) #define LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_C2APB1FZR1_DBG_I2C3_STOP /*!< The I2C3 SMBus timeout is frozen */ +#endif #define LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted */ /** * @}
diff --git a/Inc/stm32wbxx_ll_tim.h b/Inc/stm32wbxx_ll_tim.h index 160b175..5231a67 100644 --- a/Inc/stm32wbxx_ll_tim.h +++ b/Inc/stm32wbxx_ll_tim.h
@@ -121,20 +121,28 @@ /* Generic bit definitions for TIMx_AF1 register */ #define TIMx_AF1_BKINE TIM1_AF1_BKINE /*!< BRK BKIN input enable */ +#if defined(COMP1) && defined(COMP2) #define TIMx_AF1_BKCOMP1E TIM1_AF1_BKCMP1E /*!< BRK COMP1 enable */ #define TIMx_AF1_BKCOMP2E TIM1_AF1_BKCMP2E /*!< BRK COMP2 enable */ +#endif /* COMP1 && COMP2 */ #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */ +#if defined(COMP1) && defined(COMP2) #define TIMx_AF1_BKCOMP1P TIM1_AF1_BKCMP1P /*!< BRK COMP1 input polarity */ #define TIMx_AF1_BKCOMP2P TIM1_AF1_BKCMP2P /*!< BRK COMP2 input polarity */ +#endif /* COMP1 && COMP2 */ #define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */ /* Generic bit definitions for TIMx_AF2 register */ #define TIMx_AF2_BK2INE TIM1_AF2_BK2INE /*!< BRK2 BKIN2 input enable */ +#if defined(COMP1) && defined(COMP2) #define TIMx_AF2_BK2COMP1E TIM1_AF2_BK2CMP1E /*!< BRK2 COMP1 enable */ #define TIMx_AF2_BK2COMP2E TIM1_AF2_BK2CMP2E /*!< BRK2 COMP2 enable */ +#endif /* COMP1 && COMP2 */ #define TIMx_AF2_BK2INP TIM1_AF2_BK2INP /*!< BRK2 BKIN2 input polarity */ +#if defined(COMP1) && defined(COMP2) #define TIMx_AF2_BK2COMP1P TIM1_AF2_BK2CMP1P /*!< BRK2 COMP1 input polarity */ #define TIMx_AF2_BK2COMP2P TIM1_AF2_BK2CMP2P /*!< BRK2 COMP2 input polarity */ +#endif /* COMP1 && COMP2 */ /* Remap mask definitions */ #define TIMx_OR_RMP_SHIFT 16U @@ -917,8 +925,10 @@ * @{ */ #define LL_TIM_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */ +#if defined(COMP1) && defined(COMP2) #define LL_TIM_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */ #define LL_TIM_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ +#endif /* COMP1 && COMP2 */ #define LL_TIM_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC1 analog watchdog 1 */ #define LL_TIM_ETRSOURCE_ADC1_AWD2 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to ADC1 analog watchdog 2 */ #define LL_TIM_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC1 analog watchdog 3 */ @@ -1109,7 +1119,9 @@ * @{ */ #define LL_TIM_TIM1_TI1_RMP_GPIO TIM1_OR_RMP_MASK /*!< TIM1 input capture 1 is connected to GPIO */ +#if defined(COMP1) #define LL_TIM_TIM1_TI1_RMP_COMP1 (TIM1_OR_TI1_RMP | TIM1_OR_RMP_MASK) /*!< TIM1 input capture 1 is connected to COMP1 output */ +#endif /* COMP1 */ /** * @} */ @@ -1118,7 +1130,9 @@ * @{ */ #define LL_TIM_TIM2_ITR1_RMP_NONE 0x00000000U /* !< No internal trigger on TIM2_ITR1 */ +#if defined(USB) #define LL_TIM_TIM2_ITR1_RMP_USB_SOF (TIM2_OR_ITR1_RMP) /* !< TIM2_ITR1 is connected to USB SOF */ +#endif /* USB */ /** * @} */ @@ -1136,9 +1150,11 @@ * @{ */ #define LL_TIM_TIM2_TI4_RMP_GPIO TIM2_OR_RMP_MASK /*!< TIM2 input capture 4 is connected to GPIO */ +#if defined(COMP1) && defined(COMP2) #define LL_TIM_TIM2_TI4_RMP_COMP1 (TIM2_OR_TI4_RMP_0 | TIM2_OR_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP1_OUT */ #define LL_TIM_TIM2_TI4_RMP_COMP2 (TIM2_OR_TI4_RMP_1 | TIM2_OR_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP2_OUT */ #define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR_TI4_RMP | TIM2_OR_RMP_MASK) /*!< TIM2 input capture 4 is connected to logical OR between COMP1_OUT and COMP2_OUT */ +#endif /* COMP1 && COMP2 */ /** * @} */ @@ -1451,7 +1467,7 @@ /** * @brief Set the timer counter counting mode. - * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to * check whether or not the counter mode selection feature is supported * by a timer instance. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) @@ -1475,7 +1491,7 @@ /** * @brief Get actual counter mode. - * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to * check whether or not the counter mode selection feature is supported * by a timer instance. * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n @@ -1528,7 +1544,7 @@ /** * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. - * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check * whether or not the clock division feature is supported by the timer * instance. * @rmtoll CR1 CKD LL_TIM_SetClockDivision @@ -1546,7 +1562,7 @@ /** * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. - * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check * whether or not the clock division feature is supported by the timer * instance. * @rmtoll CR1 CKD LL_TIM_GetClockDivision @@ -1563,7 +1579,7 @@ /** * @brief Set the counter value. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @rmtoll CNT CNT LL_TIM_SetCounter * @param TIMx Timer instance @@ -1577,7 +1593,7 @@ /** * @brief Get the counter value. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @rmtoll CNT CNT LL_TIM_GetCounter * @param TIMx Timer instance @@ -1631,7 +1647,7 @@ /** * @brief Set the auto-reload value. * @note The counter is blocked while the auto-reload value is null. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter * @rmtoll ARR ARR LL_TIM_SetAutoReload @@ -1647,7 +1663,7 @@ /** * @brief Get the auto-reload value. * @rmtoll ARR ARR LL_TIM_GetAutoReload - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @param TIMx Timer instance * @retval Auto-reload value @@ -1660,7 +1676,7 @@ /** * @brief Set the repetition counter value. * @note For advanced timer instances RepetitionCounter can be up to 65535. - * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a repetition counter. * @rmtoll RCR REP LL_TIM_SetRepetitionCounter * @param TIMx Timer instance @@ -1674,7 +1690,7 @@ /** * @brief Get the repetition counter value. - * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a repetition counter. * @rmtoll RCR REP LL_TIM_GetRepetitionCounter * @param TIMx Timer instance @@ -1720,7 +1736,7 @@ * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, * they are updated only when a commutation event (COM) occurs. * @note Only on channels that have a complementary output. - * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check * whether or not a timer instance is able to generate a commutation event. * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload * @param TIMx Timer instance @@ -1733,7 +1749,7 @@ /** * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. - * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check * whether or not a timer instance is able to generate a commutation event. * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload * @param TIMx Timer instance @@ -1746,7 +1762,7 @@ /** * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). - * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check * whether or not a timer instance is able to generate a commutation event. * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate * @param TIMx Timer instance @@ -1790,7 +1806,7 @@ /** * @brief Set the lock level to freeze the * configuration of several capture/compare parameters. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * the lock mechanism is supported by a timer instance. * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel * @param TIMx Timer instance @@ -2092,7 +2108,7 @@ /** * @brief Set the IDLE state of an output channel * @note This function is significant only for the timer instances - * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) + * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) * can be used to check whether or not a timer instance provides * a break input. * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n @@ -2316,7 +2332,7 @@ /** * @brief Enable clearing the output channel on an external event. * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. - * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether * or not a timer instance can clear the OCxREF signal on an external event. * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n * CCMR1 OC2CE LL_TIM_OC_EnableClear\n @@ -2343,7 +2359,7 @@ /** * @brief Disable clearing the output channel on an external event. - * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether * or not a timer instance can clear the OCxREF signal on an external event. * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n * CCMR1 OC2CE LL_TIM_OC_DisableClear\n @@ -2372,7 +2388,7 @@ * @brief Indicates clearing the output channel on an external event is enabled for the output channel. * @note This function enables clearing the output channel on an external event. * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. - * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether * or not a timer instance can clear the OCxREF signal on an external event. * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n @@ -2400,7 +2416,7 @@ /** * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals). - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * dead-time insertion feature is supported by a timer instance. * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime @@ -2416,9 +2432,9 @@ /** * @brief Set compare value for output channel 1 (TIMx_CCR1). * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not * output channel 1 is supported by a timer instance. * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 * @param TIMx Timer instance @@ -2433,9 +2449,9 @@ /** * @brief Set compare value for output channel 2 (TIMx_CCR2). * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not * output channel 2 is supported by a timer instance. * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 * @param TIMx Timer instance @@ -2450,9 +2466,9 @@ /** * @brief Set compare value for output channel 3 (TIMx_CCR3). * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not * output channel is supported by a timer instance. * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 * @param TIMx Timer instance @@ -2467,9 +2483,9 @@ /** * @brief Set compare value for output channel 4 (TIMx_CCR4). * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not * output channel 4 is supported by a timer instance. * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 * @param TIMx Timer instance @@ -2483,7 +2499,7 @@ /** * @brief Set compare value for output channel 5 (TIMx_CCR5). - * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not * output channel 5 is supported by a timer instance. * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 * @param TIMx Timer instance @@ -2497,7 +2513,7 @@ /** * @brief Set compare value for output channel 6 (TIMx_CCR6). - * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not * output channel 6 is supported by a timer instance. * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 * @param TIMx Timer instance @@ -2512,9 +2528,9 @@ /** * @brief Get compare value (TIMx_CCR1) set for output channel 1. * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not * output channel 1 is supported by a timer instance. * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 * @param TIMx Timer instance @@ -2528,9 +2544,9 @@ /** * @brief Get compare value (TIMx_CCR2) set for output channel 2. * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not * output channel 2 is supported by a timer instance. * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 * @param TIMx Timer instance @@ -2544,9 +2560,9 @@ /** * @brief Get compare value (TIMx_CCR3) set for output channel 3. * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not * output channel 3 is supported by a timer instance. * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 * @param TIMx Timer instance @@ -2560,9 +2576,9 @@ /** * @brief Get compare value (TIMx_CCR4) set for output channel 4. * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not * output channel 4 is supported by a timer instance. * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 * @param TIMx Timer instance @@ -2575,7 +2591,7 @@ /** * @brief Get compare value (TIMx_CCR5) set for output channel 5. - * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not * output channel 5 is supported by a timer instance. * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 * @param TIMx Timer instance @@ -2588,7 +2604,7 @@ /** * @brief Get compare value (TIMx_CCR6) set for output channel 6. - * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not * output channel 6 is supported by a timer instance. * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 * @param TIMx Timer instance @@ -2601,7 +2617,7 @@ /** * @brief Select on which reference signal the OC5REF is combined to. - * @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports the combined 3-phase PWM mode. * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n @@ -2905,7 +2921,7 @@ /** * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). - * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides an XOR input. * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination * @param TIMx Timer instance @@ -2918,7 +2934,7 @@ /** * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. - * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides an XOR input. * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination * @param TIMx Timer instance @@ -2931,7 +2947,7 @@ /** * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. - * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides an XOR input. * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination * @param TIMx Timer instance @@ -2945,9 +2961,9 @@ /** * @brief Get captured value for input channel 1. * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not * input channel 1 is supported by a timer instance. * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 * @param TIMx Timer instance @@ -2961,9 +2977,9 @@ /** * @brief Get captured value for input channel 2. * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not * input channel 2 is supported by a timer instance. * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 * @param TIMx Timer instance @@ -2977,9 +2993,9 @@ /** * @brief Get captured value for input channel 3. * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not * input channel 3 is supported by a timer instance. * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 * @param TIMx Timer instance @@ -2993,9 +3009,9 @@ /** * @brief Get captured value for input channel 4. * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not * input channel 4 is supported by a timer instance. * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 * @param TIMx Timer instance @@ -3016,7 +3032,7 @@ /** * @brief Enable external clock mode 2. * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. - * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports external clock mode2. * @rmtoll SMCR ECE LL_TIM_EnableExternalClock * @param TIMx Timer instance @@ -3029,7 +3045,7 @@ /** * @brief Disable external clock mode 2. - * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports external clock mode2. * @rmtoll SMCR ECE LL_TIM_DisableExternalClock * @param TIMx Timer instance @@ -3042,7 +3058,7 @@ /** * @brief Indicate whether external clock mode 2 is enabled. - * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports external clock mode2. * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock * @param TIMx Timer instance @@ -3059,9 +3075,9 @@ * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() * function. This timer input must be configured by calling * the @ref LL_TIM_IC_Config() function. - * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports external clock mode1. - * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports external clock mode2. * @rmtoll SMCR SMS LL_TIM_SetClockSource\n * SMCR ECE LL_TIM_SetClockSource @@ -3079,7 +3095,7 @@ /** * @brief Set the encoder interface mode. - * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports the encoder mode. * @rmtoll SMCR SMS LL_TIM_SetEncoderMode * @param TIMx Timer instance @@ -3103,7 +3119,7 @@ */ /** * @brief Set the trigger output (TRGO) used for timer synchronization . - * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance can operate as a master timer. * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput * @param TIMx Timer instance @@ -3125,7 +3141,7 @@ /** * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . - * @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check * whether or not a timer instance can be used for ADC synchronization. * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 * @param TIMx Timer Instance @@ -3155,7 +3171,7 @@ /** * @brief Set the synchronization mode of a slave timer. - * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not * a timer instance can operate as a slave timer. * @rmtoll SMCR SMS LL_TIM_SetSlaveMode * @param TIMx Timer instance @@ -3174,7 +3190,7 @@ /** * @brief Set the selects the trigger input to be used to synchronize the counter. - * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not * a timer instance can operate as a slave timer. * @rmtoll SMCR TS LL_TIM_SetTriggerInput * @param TIMx Timer instance @@ -3196,7 +3212,7 @@ /** * @brief Enable the Master/Slave mode. - * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not * a timer instance can operate as a slave timer. * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode * @param TIMx Timer instance @@ -3209,7 +3225,7 @@ /** * @brief Disable the Master/Slave mode. - * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not * a timer instance can operate as a slave timer. * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode * @param TIMx Timer instance @@ -3222,7 +3238,7 @@ /** * @brief Indicates whether the Master/Slave mode is enabled. - * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not * a timer instance can operate as a slave timer. * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode * @param TIMx Timer instance @@ -3235,7 +3251,7 @@ /** * @brief Configure the external trigger (ETR) input. - * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides an external trigger input. * @rmtoll SMCR ETP LL_TIM_ConfigETR\n * SMCR ETPS LL_TIM_ConfigETR\n @@ -3276,7 +3292,7 @@ /** * @brief Select the external trigger (ETR) input source. - * @note Macro @ref IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or + * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or * not a timer instance supports ETR source selection. * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource * @param TIMx Timer instance @@ -3304,7 +3320,7 @@ */ /** * @brief Enable the break function. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR BKE LL_TIM_EnableBRK * @param TIMx Timer instance @@ -3319,7 +3335,7 @@ * @brief Disable the break function. * @rmtoll BDTR BKE LL_TIM_DisableBRK * @param TIMx Timer instance - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @retval None */ @@ -3330,7 +3346,7 @@ /** * @brief Configure the break input. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n * BDTR BKF LL_TIM_ConfigBRK @@ -3365,7 +3381,7 @@ /** * @brief Enable the break 2 function. - * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a second break input. * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 * @param TIMx Timer instance @@ -3378,7 +3394,7 @@ /** * @brief Disable the break 2 function. - * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a second break input. * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 * @param TIMx Timer instance @@ -3391,7 +3407,7 @@ /** * @brief Configure the break 2 input. - * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a second break input. * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n * BDTR BK2F LL_TIM_ConfigBRK2 @@ -3425,7 +3441,7 @@ /** * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n * BDTR OSSR LL_TIM_SetOffStates @@ -3445,7 +3461,7 @@ /** * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput * @param TIMx Timer instance @@ -3458,7 +3474,7 @@ /** * @brief Disable automatic output (MOE can be set only by software). - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput * @param TIMx Timer instance @@ -3471,7 +3487,7 @@ /** * @brief Indicate whether automatic output is enabled. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput * @param TIMx Timer instance @@ -3486,7 +3502,7 @@ * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by * software and is reset in case of break or break2 event - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs * @param TIMx Timer instance @@ -3501,7 +3517,7 @@ * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by * software and is reset in case of break or break2 event. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs * @param TIMx Timer instance @@ -3514,7 +3530,7 @@ /** * @brief Indicates whether outputs are enabled. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs * @param TIMx Timer instance @@ -3527,22 +3543,24 @@ /** * @brief Enable the signals connected to the designated timer break input. - * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether * or not a timer instance allows for break input selection. * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n * AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n - * AF2 BKINE LL_TIM_EnableBreakInputSource\n - * AF2 BKCMP1E LL_TIM_EnableBreakInputSource\n - * AF2 BKCMP2E LL_TIM_EnableBreakInputSource\n + * AF2 BK2INE LL_TIM_EnableBreakInputSource\n + * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n + * AF2 BK2CMP2E LL_TIM_EnableBreakInputSource * @param TIMx Timer instance * @param BreakInput This parameter can be one of the following values: * @arg @ref LL_TIM_BREAK_INPUT_BKIN * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 * @param Source This parameter can be one of the following values: * @arg @ref LL_TIM_BKIN_SOURCE_BKIN - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*) + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*) + * + * (*) Value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) @@ -3553,22 +3571,24 @@ /** * @brief Disable the signals connected to the designated timer break input. - * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether * or not a timer instance allows for break input selection. * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n * AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n - * AF2 BKINE LL_TIM_DisableBreakInputSource\n - * AF2 BKCMP1E LL_TIM_DisableBreakInputSource\n - * AF2 BKCMP2E LL_TIM_DisableBreakInputSource\n + * AF2 BK2INE LL_TIM_DisableBreakInputSource\n + * AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n + * AF2 BK2CMP2E LL_TIM_DisableBreakInputSource * @param TIMx Timer instance * @param BreakInput This parameter can be one of the following values: * @arg @ref LL_TIM_BREAK_INPUT_BKIN * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 * @param Source This parameter can be one of the following values: * @arg @ref LL_TIM_BKIN_SOURCE_BKIN - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*) + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*) + * + * (*) Value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) @@ -3579,7 +3599,7 @@ /** * @brief Set the polarity of the break signal for the timer break input. - * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether * or not a timer instance allows for break input selection. * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n @@ -3593,11 +3613,13 @@ * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 * @param Source This parameter can be one of the following values: * @arg @ref LL_TIM_BKIN_SOURCE_BKIN - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*) + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*) * @param Polarity This parameter can be one of the following values: * @arg @ref LL_TIM_BKIN_POLARITY_LOW * @arg @ref LL_TIM_BKIN_POLARITY_HIGH + * + * (*) Value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, @@ -3615,7 +3637,7 @@ */ /** * @brief Configures the timer DMA burst feature. - * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or + * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or * not a timer instance supports the DMA burst mode. * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n * DCR DBA LL_TIM_ConfigDMABurst @@ -3680,7 +3702,7 @@ */ /** * @brief Remap TIM inputs (input channel, internal/external triggers). - * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not * a some timer inputs can be remapped. * @rmtoll TIM1_OR ETR_ADC1_RMP LL_TIM_SetRemap\n * TIM1_OR TI1_RMP LL_TIM_SetRemap\n @@ -3706,13 +3728,13 @@ * * . . TI1_RMP can be one of the following values * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO - * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1 + * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1 (*) * * TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where * * ITR1_RMP can be one of the following values * @arg @ref LL_TIM_TIM2_ITR1_RMP_NONE - * @arg @ref LL_TIM_TIM2_ITR1_RMP_USB_SOF + * @arg @ref LL_TIM_TIM2_ITR1_RMP_USB_SOF (*) * * . . ETR1_RMP can be one of the following values * @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO @@ -3720,9 +3742,9 @@ * * . . TI4_RMP can be one of the following values * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO - * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1 - * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2 - * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 + * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1 (*) + * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2 (*) + * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (*) * * TIM16: one of the following values * @@ -3737,6 +3759,8 @@ * @arg @ref LL_TIM_TIM17_TI1_RMP_MSI * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32 * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO + * + * (*) Value not defined in all devices. \n * @retval None */ __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
diff --git a/Inc/stm32wbxx_ll_usb.h b/Inc/stm32wbxx_ll_usb.h index 0a67470..ad2e901 100644 --- a/Inc/stm32wbxx_ll_usb.h +++ b/Inc/stm32wbxx_ll_usb.h
@@ -151,6 +151,14 @@ * @} */ +/** @defgroup USB_LL Device Speed + * @{ + */ +#define USBD_FS_SPEED 2U +/** + * @} + */ + #define BTABLE_ADDRESS 0x000U #define PMA_ACCESS 1U
diff --git a/License.md b/License.md index 618e114..37e1863 100644 --- a/License.md +++ b/License.md
@@ -1,3 +1,3 @@ # Copyright (c) 2019 STMicroelectronics -This software component is licensed by STMicroelectronics under the **BSD 3-Clause** license. You may not use this file except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/BSD-3-Clause). +This software component is licensed by STMicroelectronics under the **BSD-3-Clause** license. You may not use this software except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/BSD-3-Clause).
diff --git a/README.md b/README.md index d7b7264..da7e715 100644 --- a/README.md +++ b/README.md
@@ -23,7 +23,7 @@ Copyright (c) 2019 STMicroelectronics. -This software component is licensed by STMicroelectronics under BSD 3-Clause license. You may not use this file except in compliance with the License. +This software component is licensed by STMicroelectronics under BSD-3-Clause license. You may not use this software except in compliance with the License. You may obtain a copy of the License [here](https://opensource.org/licenses/BSD-3-Clause). ## Compatibility information @@ -35,11 +35,12 @@ HAL Driver WB | CMSIS Device WB | CMSIS Core | Was delivered in the full MCU package ------------- | --------------- | ---------- | ------------------------------------- Tag v1.1.0 | Tag v1.1.0 | Tag v4.5_cm4 | Tag v1.1.0 (and following, if any, till next new tag) +Tag v1.2.0 | Tag v1.2.0 | Tag v5.4.0_cm4 | Tag v1.2.0 (and following, if any, till next new tag) The full **STM32CubeWB** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeWB). ## Troubleshooting -If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/stm32wbxx_hal_driver/issues/new). +If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/stm32wbxx_hal_driver/issues/new/choose). For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
diff --git a/Release_Notes.html b/Release_Notes.html index 359e0f0..3613db7 100644 --- a/Release_Notes.html +++ b/Release_Notes.html
@@ -46,9 +46,88 @@ <div class="col-sm-12 col-lg-8"> <h1 id="update-history">Update History</h1> <div class="collapse"> -<input type="checkbox" id="collapse-section2" checked aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 05-April-2019</label> +<input type="checkbox" id="collapse-section3" checked aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.2.0 / 26-June-2019</label> <div> <h2 id="main-changes">Main Changes</h2> +<h3 id="stm32wb50xx-introduction-and-maintenance-release">STM32WB50xx introduction and maintenance release</h3> +<p>First release for STM32WBxx HAL drivers introducing <strong>stm32wb50xx</strong> devices.</p> +<table> +<thead> +<tr class="header"> +<th>Peripheral</th> +<th style="text-align: left;">Headline</th> +</tr> +</thead> +<tbody> +<tr class="odd"> +<td>RCC</td> +<td style="text-align: left;">Add capabilty to configure RNG clock in one step.</td> +</tr> +<tr class="even"> +<td></td> +<td style="text-align: left;">Before two steps were required: USB clock then RNG clock.</td> +</tr> +<tr class="odd"> +<td></td> +<td style="text-align: left;">Two step method is still supported and compatible.</td> +</tr> +<tr class="even"> +<td>IRDA</td> +<td style="text-align: left;">Avoid using macros with function calls as argument</td> +</tr> +<tr class="odd"> +<td>LPTIM</td> +<td style="text-align: left;">Add polling mechanims to check xxOK flags</td> +</tr> +<tr class="even"> +<td></td> +<td style="text-align: left;">Add new EXTI macros to manage LPTIM wakeup EXTI interrupts</td> +</tr> +<tr class="odd"> +<td>USB</td> +<td style="text-align: left;">Improve ep OUT interrupt handler</td> +</tr> +<tr class="even"> +<td></td> +<td style="text-align: left;">Ensure 16 bit access to USB PMA</td> +</tr> +<tr class="odd"> +<td></td> +<td style="text-align: left;">Enable BCD</td> +</tr> +<tr class="even"> +<td>RNG</td> +<td style="text-align: left;">Add new error definitions</td> +</tr> +<tr class="odd"> +<td>SAI</td> +<td style="text-align: left;">Correct SAI frequency calculation in case of SPDIF output</td> +</tr> +<tr class="even"> +<td>SMARTCARD</td> +<td style="text-align: left;">Avoid using macros with function calls as argument</td> +</tr> +<tr class="odd"> +<td>UART</td> +<td style="text-align: left;">Avoid using macros with function calls as argument</td> +</tr> +<tr class="even"> +<td>USART</td> +<td style="text-align: left;">Avoid using macros with function calls as argument</td> +</tr> +</tbody> +</table> +<h2 id="backward-compatibility">Backward Compatibility</h2> +<p>This release is compatible with the previous versions.</p> +<h2 id="dependencies">Dependencies</h2> +<p>This software release is compatible with:</p> +<p>STM32CubeMX V5.3.0</p> +</div> +</div> +<div class="collapse"> +<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 05-April-2019</label> +<div> +<h2 id="main-changes-1">Main Changes</h2> <h3 id="maintenance-release">Maintenance release</h3> <p>Maintenance release of HAL and Low layers drivers supporting STM32WB55xx devices.</p> <table> @@ -102,9 +181,9 @@ </tr> </tbody> </table> -<h2 id="backward-compatibility">Backward Compatibility</h2> +<h2 id="backward-compatibility-1">Backward Compatibility</h2> <p>This release is compatible with the previous versions.</p> -<h2 id="dependencies">Dependencies</h2> +<h2 id="dependencies-1">Dependencies</h2> <p>This software release is compatible with:</p> <p>STM32CubeMX V5.2.0</p> </div> @@ -112,7 +191,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 06-February-2019</label> <div> -<h2 id="main-changes-1">Main Changes</h2> +<h2 id="main-changes-2">Main Changes</h2> <h3 id="first-release">First release</h3> <p>First official release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32WB55xx.</p> </div>
diff --git a/Src/stm32wbxx_hal.c b/Src/stm32wbxx_hal.c index 597a959..3d4ce01 100644 --- a/Src/stm32wbxx_hal.c +++ b/Src/stm32wbxx_hal.c
@@ -56,7 +56,7 @@ * @brief STM32WBxx HAL Driver version number */ #define __STM32WBxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WBxx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ +#define __STM32WBxx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ #define __STM32WBxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WBxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WBxx_HAL_VERSION ((__STM32WBxx_HAL_VERSION_MAIN << 24U)\ @@ -575,6 +575,7 @@ (+) Enable/Disable the Voltage reference buffer (+) Enable/Disable the I/O analog switch voltage booster (+) Enable/Disable the access for security IP (AES1, AES2, PKA, RNG) + (+) Enable/Disable the access for security IP (AES2, PKA, RNG) @endverbatim * @{ @@ -614,6 +615,7 @@ return (LL_SYSCFG_IsEnabledSRAMFetch()); } +#if defined(VREFBUF) /** * @brief Configure the internal voltage reference buffer voltage scale. * @param VoltageScaling specifies the output voltage to achieve @@ -698,6 +700,7 @@ { LL_VREFBUF_Disable(); } +#endif /** * @brief Enable the I/O analog switch voltage booster
diff --git a/Src/stm32wbxx_hal_adc.c b/Src/stm32wbxx_hal_adc.c index ad6f1cf..ecf52d2 100644 --- a/Src/stm32wbxx_hal_adc.c +++ b/Src/stm32wbxx_hal_adc.c
@@ -2,7 +2,7 @@ ****************************************************************************** * @file stm32wbxx_hal_adc.c * @author MCD Application Team - * @brief This file provides firmware functions to manage the following + * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: * + Initialization and de-initialization functions @@ -16,7 +16,7 @@ * + State functions * ++ ADC state machine management * ++ Interrupts and flags management - * Other functions (extended functions) are available in file + * Other functions (extended functions) are available in file * "stm32wbxx_hal_adc_ex.c". * @verbatim @@ -26,31 +26,31 @@ [..] (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution. - (+) Interrupt generation at the end of regular conversion and in case of + (+) Interrupt generation at the end of regular conversion and in case of analog watchdog or overrun events. - + (+) Single and continuous conversion modes. - + (+) Scan mode for conversion of several channels sequentially. - + (+) Data alignment with in-built data coherency. - + (+) Programmable sampling time (channel wise) - + (+) External trigger (timer or EXTI) with configurable polarity - + (+) DMA request generation for transfer of conversions data of regular group. - + (+) ADC channels selectable single/differential input. - + (+) ADC offset shared on 4 offset instances. (+) ADC calibration - + (+) ADC conversion of regular group. - + (+) ADC supply requirements: 1.62 V to 3.6 V. - - (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to + + (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to Vdda or to an external voltage reference). @@ -65,12 +65,12 @@ (#) Enable the ADC interface (++) As prerequisite, ADC clock must be configured at RCC top level. - (++) Two clock settings are mandatory: + (++) Two clock settings are mandatory: (+++) ADC clock (core clock, also possibly conversion clock). (+++) ADC clock (conversions clock). Two possible clock sources: synchronous clock derived from AHB2 clock - or asynchronous clock derived from system clock, PLLSAI1 (output divider R) or the PLL system (output divider P) + or asynchronous clock derived from system clock, PLLSAI1 (output divider R) or the PLL system (output divider P) running up to 64MHz. (+++) Example: @@ -96,8 +96,8 @@ (#) Optionally, in case of usage of ADC with interruptions: (++) Configure the NVIC for ADC using function HAL_NVIC_EnableIRQ(ADCx_IRQn) - (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() - into the function of corresponding ADC interruption vector + (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() + into the function of corresponding ADC interruption vector ADCx_IRQHandler(). (#) Optionally, in case of usage of DMA: @@ -105,8 +105,8 @@ using function HAL_DMA_Init(). (++) Configure the NVIC for DMA using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) - (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() - into the function of corresponding DMA interruption vector + (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() + into the function of corresponding DMA interruption vector DMAx_Channelx_IRQHandler(). *** Configuration of ADC, group regular, channels parameters *** @@ -117,7 +117,7 @@ and regular group parameters (conversion trigger, sequencer, ...) using function HAL_ADC_Init(). - (#) Configure the channels for regular group parameters (channel number, + (#) Configure the channels for regular group parameters (channel number, channel rank into sequencer, ..., into regular group) using function HAL_ADC_ConfigChannel(). @@ -139,22 +139,22 @@ (++) ADC conversion by polling: (+++) Activate the ADC peripheral and start conversions using function HAL_ADC_Start() - (+++) Wait for ADC conversion completion + (+++) Wait for ADC conversion completion using function HAL_ADC_PollForConversion() - (+++) Retrieve conversion results + (+++) Retrieve conversion results using function HAL_ADC_GetValue() - (+++) Stop conversion and disable the ADC peripheral + (+++) Stop conversion and disable the ADC peripheral using function HAL_ADC_Stop() - (++) ADC conversion by interruption: + (++) ADC conversion by interruption: (+++) Activate the ADC peripheral and start conversions using function HAL_ADC_Start_IT() (+++) Wait for ADC conversion completion by call of function HAL_ADC_ConvCpltCallback() (this function must be implemented in user program) - (+++) Retrieve conversion results + (+++) Retrieve conversion results using function HAL_ADC_GetValue() - (+++) Stop conversion and disable the ADC peripheral + (+++) Stop conversion and disable the ADC peripheral using function HAL_ADC_Stop_IT() (++) ADC conversion with transfer by DMA: @@ -165,7 +165,7 @@ (these functions must be implemented in user program) (+++) Conversion results are automatically transferred by DMA into destination variable address. - (+++) Stop conversion and disable the ADC peripheral + (+++) Stop conversion and disable the ADC peripheral using function HAL_ADC_Stop_DMA() [..] @@ -208,7 +208,7 @@ using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) [..] - + *** Callback registration *** ============================================= [..] @@ -281,7 +281,7 @@ When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. - + @endverbatim ****************************************************************************** * @attention @@ -294,7 +294,7 @@ * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -321,16 +321,16 @@ #define ADC_CFGR_FIELDS_1 ((ADC_CFGR_RES | ADC_CFGR_ALIGN |\ ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\ - ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated + ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going */ - + /* Timeout values for ADC operations (enable settling time, */ /* disable settling time, ...). */ /* Values defined to be higher than worst cases: low clock frequency, */ /* maximum prescalers. */ #define ADC_ENABLE_TIMEOUT (2UL) /*!< ADC enable time-out value */ #define ADC_DISABLE_TIMEOUT (2UL) /*!< ADC disable time-out value */ - + /* Timeout to wait for current conversion on going to be completed. */ /* Timeout fixed to longest ADC conversion possible, for 1 channel: */ /* - maximum sampling time (640.5 adc_clk) */ @@ -358,19 +358,19 @@ /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions * @brief ADC Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Initialize and configure the ADC. + (+) Initialize and configure the ADC. (+) De-initialize the ADC. @endverbatim * @{ */ /** - * @brief Initialize the ADC peripheral and regular group according to + * @brief Initialize the ADC peripheral and regular group according to * parameters specified in structure "ADC_InitTypeDef". * @note As prerequisite, ADC clock must be configured at RCC top level * (refer to description of RCC configuration for ADC @@ -378,20 +378,20 @@ * @note Possibility to update parameters on the fly: * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when * coming from ADC state reset. Following calls to this function can - * be used to reconfigure some parameters of ADC_InitTypeDef - * structure on the fly, without modifying MSP configuration. If ADC + * be used to reconfigure some parameters of ADC_InitTypeDef + * structure on the fly, without modifying MSP configuration. If ADC * MSP has to be modified again, HAL_ADC_DeInit() must be called * before HAL_ADC_Init(). * The setting of these parameters is conditioned to ADC state. - * For parameters constraints, see comments of structure + * For parameters constraints, see comments of structure * "ADC_InitTypeDef". - * @note This function configures the ADC within 2 scopes: scope of entire - * ADC and scope of regular group. For parameters details, see comments + * @note This function configures the ADC within 2 scopes: scope of entire + * ADC and scope of regular group. For parameters details, see comments * of structure "ADC_InitTypeDef". * @param hadc ADC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpCFGR; @@ -399,13 +399,13 @@ __IO uint32_t wait_loop_index = 0UL; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; - + /* Check ADC handle */ - if(hadc == NULL) + if (hadc == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); @@ -420,24 +420,24 @@ assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); - - if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) + + if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) { assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); - - if(hadc->Init.DiscontinuousConvMode == ENABLE) + + if (hadc->Init.DiscontinuousConvMode == ENABLE) { assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); } } - + /* DISCEN and CONT bits cannot be set at the same time */ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); - + /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ - if(hadc->State == HAL_ADC_STATE_RESET) + if (hadc->State == HAL_ADC_STATE_RESET) { #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /* Init the ADC Callback settings */ @@ -450,83 +450,83 @@ hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */ hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */ hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */ - + if (hadc->MspInitCallback == NULL) { hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ } - + /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - + /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); - + /* Initialize Lock */ hadc->Lock = HAL_UNLOCKED; } - + /* - Exit from deep-power-down mode and ADC voltage regulator enable */ - if(LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) + if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) { - /* Disable ADC deep power down mode */ + /* Disable ADC deep power down mode */ LL_ADC_DisableDeepPowerDown(hadc->Instance); - + /* System was in deep power down mode, calibration must - be relaunched or a previously saved calibration factor - re-applied once the ADC voltage regulator is enabled */ + be relaunched or a previously saved calibration factor + re-applied once the ADC voltage regulator is enabled */ } - - if(LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) + + if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) { /* Enable ADC internal voltage regulator */ LL_ADC_EnableInternalRegulator(hadc->Instance); - + /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); - while(wait_loop_index != 0UL) + while (wait_loop_index != 0UL) { wait_loop_index--; } } - + /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ - if(LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) + if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - + tmp_hal_status = HAL_ERROR; } - - /* Configuration of ADC parameters if previous preliminary actions are */ + + /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); - - if( ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) - && (tmp_adc_reg_is_conversion_on_going == 0UL) - ) + + if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) + && (tmp_adc_reg_is_conversion_on_going == 0UL) + ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); - + /* Configuration of common ADC parameters */ - + /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - clock configuration */ @@ -554,7 +554,7 @@ LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); } } - + /* Configuration of ADC: */ /* - resolution Init.Resolution */ /* - data alignment Init.DataAlign */ @@ -568,13 +568,13 @@ hadc->Init.Overrun | hadc->Init.DataAlign | hadc->Init.Resolution | - ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode) ); - + ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); + if (hadc->Init.DiscontinuousConvMode == ENABLE) { tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion); } - + /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ @@ -582,14 +582,14 @@ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) { - tmpCFGR |= ( (hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) + tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) | hadc->Init.ExternalTrigConvEdge ); } - + /* Update Configuration Register CFGR */ - MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); - + MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); + /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular and injected groups: */ @@ -598,23 +598,23 @@ /* - Oversampling parameters Init.Oversampling */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - if ( (tmp_adc_is_conversion_on_going_regular == 0UL) + if ((tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) { - tmpCFGR = ( ADC_CFGR_DFSDM(hadc) | - ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | - ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) ); - + tmpCFGR = (ADC_CFGR_DFSDM(hadc) | + ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | + ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); + MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); - + if (hadc->Init.OversamplingMode == ENABLE) { assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio)); assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift)); assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode)); assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset)); - + /* Configuration of Oversampler: */ /* - Oversampling Ratio */ /* - Right bit shift */ @@ -637,9 +637,9 @@ /* Disable ADC oversampling scope on ADC group regular */ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); } - + } - + /* Configuration of regular group sequencer: */ /* - if scan mode is disabled, regular channels sequence length is set to */ /* 0x00: 1 channel converted (channel on regular rank 1) */ @@ -658,7 +658,7 @@ { CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); } - + /* Initialize the ADC state */ /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); @@ -667,10 +667,10 @@ { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - + tmp_hal_status = HAL_ERROR; } - + /* Return function status */ return tmp_hal_status; } @@ -678,40 +678,40 @@ /** * @brief Deinitialize the ADC peripheral registers to their default reset * values, with deinitialization of the ADC MSP. - * @note For devices with several ADCs: reset of ADC common registers is done + * @note For devices with several ADCs: reset of ADC common registers is done * only if all ADCs sharing the same common group are disabled. * (function "HAL_ADC_MspDeInit()" is also called under the same conditions: * all ADC instances use the same core clock at RCC level, disabling * the core clock reset all ADC instances). - * If this is not the case, reset of these common parameters reset is + * If this is not the case, reset of these common parameters reset is * bypassed without error reporting: it can be the intended behavior in - * case of reset of a single ADC while the other ADCs sharing the same + * case of reset of a single ADC while the other ADCs sharing the same * common group is still running. * @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down: - * this saves more power by reducing leakage currents + * this saves more power by reducing leakage currents * and is particularly interesting before entering MCU low-power modes. * @param hadc ADC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; - + /* Check ADC handle */ - if(hadc == NULL) + if (hadc == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); - + /* Stop potential conversion on going */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); - + /* Disable ADC peripheral if conversions are effectively stopped */ /* Flush register JSQR: reset the queue sequencer when injected */ /* queue sequencer is enabled and ADC disabled. */ @@ -719,13 +719,13 @@ /* internally disabled just after the completion of the last valid */ /* injected sequence. */ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM); - + /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); - + /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { @@ -733,115 +733,115 @@ hadc->State = HAL_ADC_STATE_READY; } } - + /* Note: HAL ADC deInit is done independently of ADC conversion stop */ /* and disable return status. In case of status fail, attempt to */ /* perform deinitialization anyway and it is up user code in */ /* in HAL_ADC_MspDeInit() to reset the ADC peripheral using */ /* system RCC hard reset. */ - + /* ========== Reset ADC registers ========== */ /* Reset register IER */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 | ADC_IT_JQOVF | ADC_IT_OVR | ADC_IT_JEOS | ADC_IT_JEOC | ADC_IT_EOS | ADC_IT_EOC | - ADC_IT_EOSMP | ADC_IT_RDY ) ); - + ADC_IT_EOSMP | ADC_IT_RDY)); + /* Reset register ISR */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 | ADC_FLAG_JQOVF | ADC_FLAG_OVR | ADC_FLAG_JEOS | ADC_FLAG_JEOC | ADC_FLAG_EOS | ADC_FLAG_EOC | - ADC_FLAG_EOSMP | ADC_FLAG_RDY ) ); - + ADC_FLAG_EOSMP | ADC_FLAG_RDY)); + /* Reset register CR */ - /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, - ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set": - no direct reset applicable. - Update CR register to reset value where doable by software */ + /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, + ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set": + no direct reset applicable. + Update CR register to reset value where doable by software */ CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF); - SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD); - + SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD); + /* Reset register CFGR */ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_FIELDS); - SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); - + SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); + /* Reset register CFGR2 */ - CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS | - ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE ); - + CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS | + ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE); + /* Reset register SMPR1 */ - CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS); - + CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS); + /* Reset register SMPR2 */ - CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 | - ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 | - ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10 ); - + CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 | + ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 | + ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10); + /* Reset register TR1 */ CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 | ADC_TR1_LT1); - + /* Reset register TR2 */ - CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2); - + CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2); + /* Reset register TR3 */ - CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3); - + CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3); + /* Reset register SQR1 */ - CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 | - ADC_SQR1_SQ1 | ADC_SQR1_L); - + CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 | + ADC_SQR1_SQ1 | ADC_SQR1_L); + /* Reset register SQR2 */ - CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 | - ADC_SQR2_SQ6 | ADC_SQR2_SQ5); - + CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 | + ADC_SQR2_SQ6 | ADC_SQR2_SQ5); + /* Reset register SQR3 */ - CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 | - ADC_SQR3_SQ11 | ADC_SQR3_SQ10); - + CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 | + ADC_SQR3_SQ11 | ADC_SQR3_SQ10); + /* Reset register SQR4 */ - CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15); - + CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15); + /* Register JSQR was reset when the ADC was disabled */ - + /* Reset register DR */ /* bits in access mode read only, no direct reset applicable*/ - + /* Reset register OFR1 */ - CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1); + CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1); /* Reset register OFR2 */ - CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2); + CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2); /* Reset register OFR3 */ - CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3); + CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3); /* Reset register OFR4 */ CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4); - + /* Reset registers JDR1, JDR2, JDR3, JDR4 */ /* bits in access mode read only, no direct reset applicable*/ - + /* Reset register AWD2CR */ CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH); - + /* Reset register AWD3CR */ CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH); - + /* Reset register DIFSEL */ CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL); - + /* Reset register CALFACT */ CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S); - - + + /* ========== Reset common ADC registers ========== */ - + /* Software is allowed to change common parameters only when all the other ADCs are disabled. */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) { /* Reset configuration of ADC common register CCR: - clock mode: CKMODE, PRESCEN - - multimode related parameters (when this feature is available): MDMA, + - multimode related parameters (when this feature is available): MDMA, DMACFG, DELAY, DUAL (set by HAL_ADCEx_MultiModeConfigChannel() API) - internal measurement paths: Vbat, temperature sensor, Vref (set into HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() ) @@ -849,43 +849,43 @@ ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc); } - /* DeInit the low level hardware. - + /* DeInit the low level hardware. + For example: __HAL_RCC_ADC_FORCE_RESET(); __HAL_RCC_ADC_RELEASE_RESET(); __HAL_RCC_ADC_CLK_DISABLE(); - + Keep in mind that all ADCs use the same clock: disabling - the clock will reset all ADCs. - + the clock will reset all ADCs. + */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) if (hadc->MspDeInitCallback == NULL) { hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ } - + /* DeInit the low level hardware: RCC clock, NVIC */ hadc->MspDeInitCallback(hadc); #else /* DeInit the low level hardware: RCC clock, NVIC */ HAL_ADC_MspDeInit(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - + /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); - + /* Reset injected channel configuration parameters */ hadc->InjectionConfig.ContextQueue = 0; - hadc->InjectionConfig.ChannelCount = 0; - + hadc->InjectionConfig.ChannelCount = 0; + /* Set ADC state */ hadc->State = HAL_ADC_STATE_RESET; - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -895,14 +895,14 @@ * @param hadc ADC handle * @retval None */ -__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_MspInit must be implemented in the user file. - */ + */ } /** @@ -912,14 +912,14 @@ * the core clock reset all ADC instances). * @retval None */ -__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_MspDeInit must be implemented in the user file. - */ + */ } #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) @@ -949,7 +949,7 @@ HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - + if (pCallback == NULL) { /* Update the error code */ @@ -957,7 +957,7 @@ return HAL_ERROR; } - + if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) { switch (CallbackID) @@ -965,47 +965,47 @@ case HAL_ADC_CONVERSION_COMPLETE_CB_ID : hadc->ConvCpltCallback = pCallback; break; - + case HAL_ADC_CONVERSION_HALF_CB_ID : hadc->ConvHalfCpltCallback = pCallback; break; - + case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : hadc->LevelOutOfWindowCallback = pCallback; break; - + case HAL_ADC_ERROR_CB_ID : hadc->ErrorCallback = pCallback; break; - + case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : hadc->InjectedConvCpltCallback = pCallback; break; - + case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID : hadc->InjectedQueueOverflowCallback = pCallback; break; - + case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : hadc->LevelOutOfWindow2Callback = pCallback; break; - + case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : hadc->LevelOutOfWindow3Callback = pCallback; break; - + case HAL_ADC_END_OF_SAMPLING_CB_ID : hadc->EndOfSamplingCallback = pCallback; break; - + case HAL_ADC_MSPINIT_CB_ID : hadc->MspInitCallback = pCallback; break; - + case HAL_ADC_MSPDEINIT_CB_ID : hadc->MspDeInitCallback = pCallback; break; - + default : /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; @@ -1022,15 +1022,15 @@ case HAL_ADC_MSPINIT_CB_ID : hadc->MspInitCallback = pCallback; break; - + case HAL_ADC_MSPDEINIT_CB_ID : hadc->MspDeInitCallback = pCallback; break; - + default : /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - + /* Return error status */ status = HAL_ERROR; break; @@ -1040,11 +1040,11 @@ { /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - + /* Return error status */ status = HAL_ERROR; } - + return status; } @@ -1073,7 +1073,7 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; - + if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) { switch (CallbackID) @@ -1081,51 +1081,51 @@ case HAL_ADC_CONVERSION_COMPLETE_CB_ID : hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; break; - + case HAL_ADC_CONVERSION_HALF_CB_ID : hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; break; - + case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; break; - + case HAL_ADC_ERROR_CB_ID : hadc->ErrorCallback = HAL_ADC_ErrorCallback; break; - + case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; break; - + case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID : hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; break; - + case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; break; - + case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; break; - + case HAL_ADC_END_OF_SAMPLING_CB_ID : hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; break; - + case HAL_ADC_MSPINIT_CB_ID : hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ break; - + case HAL_ADC_MSPDEINIT_CB_ID : hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ break; - + default : /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - + /* Return error status */ status = HAL_ERROR; break; @@ -1138,15 +1138,15 @@ case HAL_ADC_MSPINIT_CB_ID : hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ break; - + case HAL_ADC_MSPDEINIT_CB_ID : hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ break; - + default : /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - + /* Return error status */ status = HAL_ERROR; break; @@ -1156,11 +1156,11 @@ { /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - + /* Return error status */ status = HAL_ERROR; } - + return status; } @@ -1171,9 +1171,9 @@ */ /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions - * @brief ADC IO operation functions - * -@verbatim + * @brief ADC IO operation functions + * +@verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== @@ -1198,22 +1198,22 @@ * @param hadc ADC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* Process locked */ __HAL_LOCK(hadc); - + /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); - + /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { @@ -1223,29 +1223,29 @@ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); - + /* Set ADC error code */ /* Check if a conversion is on going on ADC group injected */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { /* Reset ADC error code fields related to regular conversions only */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else - { + { /* Reset all ADC error code fields */ - ADC_CLEAR_ERRORCODE(hadc); + ADC_CLEAR_ERRORCODE(hadc); } - + /* Clear ADC group regular conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - + /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); - + /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ @@ -1263,39 +1263,39 @@ { tmp_hal_status = HAL_BUSY; } - + /* Return function status */ return tmp_hal_status; } /** - * @brief Stop ADC conversion of regular group (and injected channels in + * @brief Stop ADC conversion of regular group (and injected channels in * case of auto_injection mode), disable ADC peripheral. - * @note: ADC peripheral disable is forcing stop of potential + * @note: ADC peripheral disable is forcing stop of potential * conversion on injected group. If injected group is under use, it * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @param hadc ADC handle * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* 1. Stop potential conversion on going, on ADC groups regular and injected */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); - + /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); - + /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { @@ -1305,10 +1305,10 @@ HAL_ADC_STATE_READY); } } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -1317,28 +1317,28 @@ * @brief Wait for regular group conversion to be completed. * @note ADC conversion flags EOS (end of sequence) and EOC (end of * conversion) are cleared by this function, with an exception: - * if low power feature "LowPowerAutoWait" is enabled, flags are + * if low power feature "LowPowerAutoWait" is enabled, flags are * not cleared to not interfere with this feature until data register * is read using function HAL_ADC_GetValue(). - * @note This function cannot be used in a particular setup: ADC configured + * @note This function cannot be used in a particular setup: ADC configured * in DMA mode and polling for end of each conversion (ADC init * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). * In this case, DMA resets the flag EOC and polling cannot be - * performed on each conversion. Nevertheless, polling can still + * performed on each conversion. Nevertheless, polling can still * be performed on the complete sequence (ADC init * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). * @param hadc ADC handle * @param Timeout Timeout value in millisecond. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) { uint32_t tickstart; uint32_t tmp_Flag_End; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* If end of conversion selected to end of sequence conversions */ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) { @@ -1357,7 +1357,7 @@ { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - + return HAL_ERROR; } else @@ -1365,55 +1365,55 @@ tmp_Flag_End = (ADC_FLAG_EOC); } } - + /* Get tick count */ tickstart = HAL_GetTick(); - + /* Wait until End of unitary conversion or sequence conversions flag is raised */ - while((hadc->Instance->ISR & tmp_Flag_End) == 0UL) + while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) { /* Check if timeout is disabled (set to infinite wait) */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + return HAL_TIMEOUT; } } } - + /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - + /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ - if( (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) - && (hadc->Init.ContinuousConvMode == DISABLE) - ) + if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) + && (hadc->Init.ContinuousConvMode == DISABLE) + ) { /* Check whether end of sequence is reached */ - if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - + if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } } - + /* Clear polled flag */ if (tmp_Flag_End == ADC_FLAG_EOS) { - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS); + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS); } else { @@ -1425,7 +1425,7 @@ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); } } - + /* Return function status */ return HAL_OK; } @@ -1443,131 +1443,131 @@ * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event * @param Timeout Timeout value in millisecond. * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR. - * Indeed, the latter is reset only if hadc->Init.Overrun field is set - * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten + * Indeed, the latter is reset only if hadc->Init.Overrun field is set + * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten * by a new converted data as soon as OVR is cleared. * To reset OVR flag once the preserved data is retrieved, the user can resort - * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout) { uint32_t tickstart; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_EVENT_TYPE(EventType)); - + /* Get tick count */ tickstart = HAL_GetTick(); - + /* Check selected event flag */ - while(__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) + while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) { /* Check if timeout is disabled (set to infinite wait) */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + return HAL_TIMEOUT; } } } - - switch(EventType) + + switch (EventType) { - /* End Of Sampling event */ - case ADC_EOSMP_EVENT: - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); - - /* Clear the End Of Sampling flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); - - break; - - /* Analog watchdog (level out of window) event */ - /* Note: In case of several analog watchdog enabled, if needed to know */ - /* which one triggered and on which ADCx, test ADC state of analog watchdog */ - /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */ - /* For example: */ - /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */ - /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */ - /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */ - - /* Check analog watchdog 1 flag */ - case ADC_AWD_EVENT: - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); - - /* Clear ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); - - break; - - /* Check analog watchdog 2 flag */ - case ADC_AWD2_EVENT: - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); - - /* Clear ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); - - break; - - /* Check analog watchdog 3 flag */ - case ADC_AWD3_EVENT: - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); - - /* Clear ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); - - break; - - /* Injected context queue overflow event */ - case ADC_JQOVF_EVENT: - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); - - /* Set ADC error code to Injected context queue overflow */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); - - /* Clear ADC Injected context queue overflow flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); - - break; - - /* Overrun event */ - default: /* Case ADC_OVR_EVENT */ - /* If overrun is set to overwrite previous data, overrun event is not */ - /* considered as an error. */ - /* (cf ref manual "Managing conversions without using the DMA and without */ - /* overrun ") */ - if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) - { + /* End Of Sampling event */ + case ADC_EOSMP_EVENT: /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); - - /* Set ADC error code to overrun */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); - } - else - { - /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN - otherwise, data register is potentially overwritten by new converted data as soon - as OVR is cleared. */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); - } - break; + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); + + /* Clear the End Of Sampling flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); + + break; + + /* Analog watchdog (level out of window) event */ + /* Note: In case of several analog watchdog enabled, if needed to know */ + /* which one triggered and on which ADCx, test ADC state of analog watchdog */ + /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */ + /* For example: */ + /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */ + /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */ + /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */ + + /* Check analog watchdog 1 flag */ + case ADC_AWD_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); + + break; + + /* Check analog watchdog 2 flag */ + case ADC_AWD2_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); + + break; + + /* Check analog watchdog 3 flag */ + case ADC_AWD3_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); + + break; + + /* Injected context queue overflow event */ + case ADC_JQOVF_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); + + /* Set ADC error code to Injected context queue overflow */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); + + /* Clear ADC Injected context queue overflow flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); + + break; + + /* Overrun event */ + default: /* Case ADC_OVR_EVENT */ + /* If overrun is set to overwrite previous data, overrun event is not */ + /* considered as an error. */ + /* (cf ref manual "Managing conversions without using the DMA and without */ + /* overrun ") */ + if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); + + /* Set ADC error code to overrun */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); + } + else + { + /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN + otherwise, data register is potentially overwritten by new converted data as soon + as OVR is cleared. */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + } + break; } - + /* Return function status */ return HAL_OK; } @@ -1575,37 +1575,37 @@ /** * @brief Enable ADC, start conversion of regular group with interruption. * @note Interruptions enabled in this function according to initialization - * setting : EOC (end of conversion), EOS (end of sequence), + * setting : EOC (end of conversion), EOS (end of sequence), * OVR overrun. * Each of these interruptions has its dedicated callback function. * @note To guarantee a proper reset of all interruptions once all the needed - * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure + * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure * a correct stop of the IT-based conversions. - * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling + * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling * interruption. If required (e.g. in case of oversampling with trigger * mode), the user must: - * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP) - * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP) + * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP) + * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP) * before calling HAL_ADC_Start_IT(). * @param hadc ADC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* Process locked */ __HAL_LOCK(hadc); - + /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); - + /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { @@ -1615,34 +1615,34 @@ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); - + /* Set ADC error code */ /* Check if a conversion is on going on ADC group injected */ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) { /* Reset ADC error code fields related to regular conversions only */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR|HAL_ADC_ERROR_DMA)); + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { /* Reset all ADC error code fields */ - ADC_CLEAR_ERRORCODE(hadc); + ADC_CLEAR_ERRORCODE(hadc); } - + /* Clear ADC group regular conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - + /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); - + /* Disable all interruptions before enabling the desired ones */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); - + /* Enable ADC end of conversion interrupt */ - switch(hadc->Init.EOCSelection) + switch (hadc->Init.EOCSelection) { case ADC_EOC_SEQ_CONV: __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS); @@ -1652,16 +1652,16 @@ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); break; } - + /* Enable ADC overrun interrupt */ /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is ADC_IT_OVR enabled; otherwise data overwrite is considered as normal behavior and no CPU time is lost for a non-processed interruption */ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) { - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); } - + /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ @@ -1674,47 +1674,47 @@ /* Process unlocked */ __HAL_UNLOCK(hadc); } - + } else { tmp_hal_status = HAL_BUSY; } - + /* Return function status */ return tmp_hal_status; } /** - * @brief Stop ADC conversion of regular group (and injected group in - * case of auto_injection mode), disable interrution of + * @brief Stop ADC conversion of regular group (and injected group in + * case of auto_injection mode), disable interrution of * end-of-conversion, disable ADC peripheral. * @param hadc ADC handle * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* 1. Stop potential conversion on going, on ADC groups regular and injected */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); - + /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* Disable ADC end of conversion interrupt for regular group */ /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); - + /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); - + /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { @@ -1724,10 +1724,10 @@ HAL_ADC_STATE_READY); } } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -1735,29 +1735,29 @@ /** * @brief Enable ADC, start conversion of regular group and transfer result through DMA. * @note Interruptions enabled in this function: - * overrun (if applicable), DMA half transfer, DMA transfer complete. + * overrun (if applicable), DMA half transfer, DMA transfer complete. * Each of these interruptions has its dedicated callback function. * @param hadc ADC handle * @param pData Destination Buffer address. * @param Length Number of data to be transferred from ADC peripheral to memory * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { HAL_StatusTypeDef tmp_hal_status; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* Process locked */ __HAL_LOCK(hadc); - + /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); - + /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { @@ -1767,53 +1767,53 @@ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); - + /* Check if a conversion is on going on ADC group injected */ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) { /* Reset ADC error code fields related to regular conversions only */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else - { + { /* Reset all ADC error code fields */ - ADC_CLEAR_ERRORCODE(hadc); + ADC_CLEAR_ERRORCODE(hadc); } - + /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; - + /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; - + /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; - - + + /* Manage ADC and DMA start: ADC overrun interruption, DMA start, */ /* ADC start (in case of SW start): */ - + /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - + /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); - - /* With DMA, overrun event is always considered as an error even if - hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore, + + /* With DMA, overrun event is always considered as an error even if + hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore, ADC_IT_OVR is enabled. */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - + /* Enable ADC DMA mode */ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); - + /* Start the DMA channel */ tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); - + /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ @@ -1831,14 +1831,14 @@ { tmp_hal_status = HAL_BUSY; } - + /* Return function status */ return tmp_hal_status; } /** - * @brief Stop ADC conversion of regular group (and injected group in - * case of auto_injection mode), disable ADC DMA transfer, disable + * @brief Stop ADC conversion of regular group (and injected group in + * case of auto_injection mode), disable ADC DMA transfer, disable * ADC peripheral. * @note: ADC peripheral disable is forcing stop of potential * conversion on ADC group injected. If ADC group injected is under use, it @@ -1846,31 +1846,31 @@ * @param hadc ADC handle * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* 1. Stop potential ADC group regular conversion on going */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); - + /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* Disable ADC DMA (ADC DMA configuration of continous requests is kept) */ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); - + /* Disable the DMA channel (in case of DMA in circular mode or stop */ /* while DMA transfer is on going) */ - if(hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) + if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) { tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - + /* Check if DMA channel effectively disabled */ if (tmp_hal_status != HAL_OK) { @@ -1878,10 +1878,10 @@ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } } - + /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); - + /* 2. Disable the ADC peripheral */ /* Update "tmp_hal_status" only if DMA channel disabling passed, */ /* to keep in memory a potential failing status. */ @@ -1902,12 +1902,12 @@ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } - + } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -1916,7 +1916,7 @@ * @brief Get ADC regular group conversion result. * @note Reading register DR automatically clears ADC flag EOC * (ADC group regular end of unitary conversion). - * @note This function does not clear ADC flag EOS + * @note This function does not clear ADC flag EOS * (ADC group regular end of sequence conversion). * Occurrence of flag EOS rising: * - If sequencer is composed of 1 rank, flag EOS is equivalent @@ -1931,15 +1931,15 @@ * @param hadc ADC handle * @retval ADC group regular conversion data */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ - - /* Return ADC converted value */ + + /* Return ADC converted value */ return hadc->Instance->DR; } @@ -1948,7 +1948,7 @@ * @param hadc ADC handle * @retval None */ -void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) +void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) { uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */ uint32_t tmp_isr = hadc->Instance->ISR; @@ -1956,13 +1956,13 @@ uint32_t tmp_adc_inj_is_trigger_source_sw_start; uint32_t tmp_adc_reg_is_trigger_source_sw_start; uint32_t tmp_cfgr; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); - + /* ========== Check End of Sampling flag for ADC group regular ========== */ - if(((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP)) + if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP)) { /* Update state machine on end of sampling status if not in error state */ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) @@ -1970,21 +1970,21 @@ /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); } - + /* End Of Sampling callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->EndOfSamplingCallback(hadc); #else HAL_ADCEx_EndOfSamplingCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - + /* Clear regular group conversion flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP ); + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); } - + /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */ - if((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) || - (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)) ) + if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) || + (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS))) { /* Update state machine on conversion status if not in error state */ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) @@ -1992,17 +1992,17 @@ /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); } - + /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going */ /* to disable interruption. */ - if(LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) + if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) { /* Carry on if continuous mode is disabled */ if (READ_BIT (hadc->Instance->CFGR, ADC_CFGR_CONT) != ADC_CFGR_CONT) { /* If End of Sequence is reached, disable interrupts */ - if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) { /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ /* ADSTART==0 (no conversion on going) */ @@ -2013,27 +2013,27 @@ /* HAL_Start_IT(), but is not disabled here because can be used */ /* by overrun IRQ process below. */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); - + /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - + if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } + } } else { /* Change ADC state to error state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } } } } - + /* Conversion complete callback */ /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */ /* to determine if conversion has been triggered from EOC or EOS, */ @@ -2044,18 +2044,18 @@ #else HAL_ADC_ConvCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - + /* Clear regular group conversion flag */ /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ /* conversion flags clear induces the release of the preserved data.*/ /* Therefore, if the preserved data value is needed, it must be */ /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) ); + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); } - + /* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */ - if( (((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) || - (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)) ) + if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) || + (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS))) { /* Update state machine on conversion status if not in error state */ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) @@ -2063,24 +2063,24 @@ /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); } - + /* Retrieve ADC configuration */ tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance); tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance); tmp_cfgr = READ_REG(hadc->Instance->CFGR); - + /* Disable interruption if no further conversion upcoming by injected */ /* external trigger or by automatic injected conversion with regular */ /* group having no further conversion upcoming (same conditions as */ /* regular group interruption disabling above), */ /* and if injected scan sequence is completed. */ - if((tmp_adc_inj_is_trigger_source_sw_start != 0UL) || - ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) && - ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && - (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == 0UL) ) ) ) + if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) || + ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) && + ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && + (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))) { /* If End of Sequence is reached, disable interrupts */ - if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) { /* Particular case if injected contexts queue is enabled: */ /* when the last context has been fully processed, JSQR is reset */ @@ -2088,7 +2088,7 @@ /* (queue empty, triggers are ignored), it can start again */ /* immediately after setting a new context (JADSTART is still set). */ /* Therefore, state of HAL ADC injected group is kept to busy. */ - if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM) == 0UL) + if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM) == 0UL) { /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ /* JADSTART==0 (no conversion on going) */ @@ -2096,12 +2096,12 @@ { /* Disable ADC end of sequence conversion interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); - + /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) - { + { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } @@ -2109,83 +2109,83 @@ { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } } } } - + /* Injected Conversion complete callback */ - /* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to + /* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether - interruption has been triggered by end of conversion or end of - sequence. */ + interruption has been triggered by end of conversion or end of + sequence. */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedConvCpltCallback(hadc); #else HAL_ADCEx_InjectedConvCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - + /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS); } - + /* ========== Check Analog watchdog 1 flag ========== */ - if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1)) + if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); - + /* Level out of window 1 callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindowCallback(hadc); #else HAL_ADC_LevelOutOfWindowCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Clear ADC analog watchdog flag */ + + /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); } - + /* ========== Check analog watchdog 2 flag ========== */ - if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2)) + if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); - + /* Level out of window 2 callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindow2Callback(hadc); #else HAL_ADCEx_LevelOutOfWindow2Callback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Clear ADC analog watchdog flag */ + + /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); } - + /* ========== Check analog watchdog 3 flag ========== */ - if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3)) + if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); - + /* Level out of window 3 callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindow3Callback(hadc); #else HAL_ADCEx_LevelOutOfWindow3Callback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Clear ADC analog watchdog flag */ + + /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); } - + /* ========== Check Overrun flag ========== */ - if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR)) + if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR)) { /* If overrun is set to overwrite previous data (default setting), */ /* overrun event is not considered as an error. */ @@ -2205,15 +2205,15 @@ overrun_error = 1UL; } } - + if (overrun_error == 1UL) { /* Change ADC state to error state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); - + /* Set ADC error code to overrun */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); - + /* Error callback */ /* Note: In case of overrun, ADC conversion data is preserved until */ /* flag OVR is reset. */ @@ -2225,23 +2225,23 @@ HAL_ADC_ErrorCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } - + /* Clear ADC overrun flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); } - + /* ========== Check Injected context queue overflow flag ========== */ - if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF)) + if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF)) { /* Change ADC state to overrun state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); - + /* Set ADC error code to Injected context queue overflow */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); - + /* Clear the Injected context queue overflow flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); - + /* Injected context queue overflow callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedQueueOverflowCallback(hadc); @@ -2249,7 +2249,7 @@ HAL_ADCEx_InjectedQueueOverflowCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } - + } /** @@ -2257,7 +2257,7 @@ * @param hadc ADC handle * @retval None */ -__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); @@ -2272,7 +2272,7 @@ * @param hadc ADC handle * @retval None */ -__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); @@ -2287,7 +2287,7 @@ * @param hadc ADC handle * @retval None */ -__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); @@ -2300,7 +2300,7 @@ /** * @brief ADC error callback in non-blocking mode * (ADC conversion with interruption or transfer by DMA). - * @note In case of error due to overrun when using ADC with DMA transfer + * @note In case of error due to overrun when using ADC with DMA transfer * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"): * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". * - If needed, restart a new ADC conversion using function @@ -2324,16 +2324,16 @@ */ /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim + * @brief Peripheral Control functions + * +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Configure channels on regular group (+) Configure the analog watchdog - + @endverbatim * @{ */ @@ -2342,7 +2342,7 @@ * @brief Configure a channel to be assigned to ADC group regular. * @note In case of usage of internal measurement channels: * Vbat/VrefInt/TempSensor. - * These internal paths can be disabled using function + * These internal paths can be disabled using function * HAL_ADC_DeInit(). * @note Possibility to update parameters on the fly: * This function initializes channel into ADC group regular, @@ -2355,7 +2355,7 @@ * @param sConfig Structure of ADC channel assigned to ADC group regular. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpOffsetShifted; @@ -2363,7 +2363,7 @@ __IO uint32_t wait_loop_index = 0; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); @@ -2371,24 +2371,24 @@ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff)); assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber)); assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset)); - - /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is + + /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is ignored (considered as reset) */ - assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE))); - + assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE))); + /* Verification of channel number */ if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) { - assert_param(IS_ADC_CHANNEL(hadc, sConfig->Channel)); + assert_param(IS_ADC_CHANNEL(hadc, sConfig->Channel)); } else { assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfig->Channel)); } - + /* Process locked */ __HAL_LOCK(hadc); - + /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ @@ -2398,7 +2398,7 @@ { /* Set ADC group regular sequence: channel on the selected scan sequence rank */ LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel); - + /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ @@ -2406,24 +2406,24 @@ /* - Channel offset */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - if ( (tmp_adc_is_conversion_on_going_regular == 0UL) + if ((tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); - + /* Configure the offset: offset enable/disable, channel, offset value */ /* Shift the offset with respect to the selected ADC resolution. */ /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); - - if(sConfig->OffsetNumber != ADC_OFFSET_NONE) + + if (sConfig->OffsetNumber != ADC_OFFSET_NONE) { /* Set ADC selected offset number */ LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted); - + } else { @@ -2447,7 +2447,7 @@ } } } - + /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ @@ -2456,27 +2456,29 @@ { /* Set mode single-ended or differential input of the selected ADC channel */ LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff); - + /* Configuration of differential mode */ if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) { /* Set sampling time of the selected ADC channel */ /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), sConfig->SamplingTime); + LL_ADC_SetChannelSamplingTime(hadc->Instance, + (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), + sConfig->SamplingTime); } - + /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */ /* If internal channel selected, enable dedicated internal buffers and */ /* paths. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ - + if(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) { /* Configuration of common ADC parameters */ - + tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); - + /* Software is allowed to change common parameters only when all ADCs */ /* of the common group are disabled. */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) @@ -2488,7 +2490,7 @@ if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); - + /* Delay for temperature sensor stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ @@ -2523,17 +2525,17 @@ /* If the requested internal measurement path has already been */ /* enabled and other ADC of the common group are enabled, internal */ /* measurement paths cannot be enabled. */ - else + else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - + tmp_hal_status = HAL_ERROR; } } } } - + /* If a conversion is on going on regular group, no update on regular */ /* channel could be done on neither of the channel configuration structure */ /* parameters. */ @@ -2541,13 +2543,13 @@ { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - + tmp_hal_status = HAL_ERROR; } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -2555,12 +2557,12 @@ /** * @brief Configure the analog watchdog. * @note Possibility to update parameters on the fly: - * This function initializes the selected analog watchdog, successive - * calls to this function can be used to reconfigure some parameters - * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting + * This function initializes the selected analog watchdog, successive + * calls to this function can be used to reconfigure some parameters + * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting * the ADC. * The setting of these parameters is conditioned to ADC state. - * For parameters constraints, see comments of structure + * For parameters constraints, see comments of structure * "ADC_AnalogWDGConfTypeDef". * @note On this STM32 serie, analog watchdog thresholds cannot be modified * while ADC conversion is on going. @@ -2568,27 +2570,27 @@ * @param AnalogWDGConfig Structure of ADC analog watchdog configuration * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpAWDHighThresholdShifted; uint32_t tmpAWDLowThresholdShifted; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber)); assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); - - if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || - (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || - (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) ) + + if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || + (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || + (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)) { assert_param(IS_ADC_CHANNEL(hadc, AnalogWDGConfig->Channel)); } - + /* Verify thresholds range */ if (hadc->Init.OversamplingMode == ENABLE) { @@ -2604,10 +2606,10 @@ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); } - + /* Process locked */ __HAL_LOCK(hadc); - + /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on ADC groups regular and injected: */ @@ -2615,67 +2617,70 @@ /* - Analog watchdog thresholds */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - if ( (tmp_adc_is_conversion_on_going_regular == 0UL) + if ((tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) { /* Analog watchdog configuration */ - if(AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) + if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) { /* Configuration of analog watchdog: */ /* - Set the analog watchdog enable mode: one or overall group of */ /* channels, on groups regular and-or injected. */ - switch(AnalogWDGConfig->WatchdogMode) + switch (AnalogWDGConfig->WatchdogMode) { case ADC_ANALOGWATCHDOG_SINGLE_REG: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR)); + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, + LL_ADC_GROUP_REGULAR)); break; - + case ADC_ANALOGWATCHDOG_SINGLE_INJEC: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_INJECTED)); + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, + LL_ADC_GROUP_INJECTED)); break; - + case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR_INJECTED)); + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, + LL_ADC_GROUP_REGULAR_INJECTED)); break; - + case ADC_ANALOGWATCHDOG_ALL_REG: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG); break; - + case ADC_ANALOGWATCHDOG_ALL_INJEC: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ); break; - + case ADC_ANALOGWATCHDOG_ALL_REGINJEC: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ); break; - + default: /* ADC_ANALOGWATCHDOG_NONE */ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE); break; } - + /* Shift the offset in function of the selected ADC resolution: */ /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */ - /* are set to 0 */ + /* are set to 0 */ tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); - + /* Set ADC analog watchdog thresholds value of both thresholds high and low */ LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted, tmpAWDLowThresholdShifted); - + /* Update state, clear previous result related to AWD1 */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1); - + /* Clear flag ADC analog watchdog */ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ /* (in case left enabled by previous ADC operations). */ LL_ADC_ClearFlag_AWD1(hadc->Instance); - + /* Configure ADC analog watchdog interrupt */ - if(AnalogWDGConfig->ITMode == ENABLE) + if (AnalogWDGConfig->ITMode == ENABLE) { LL_ADC_EnableIT_AWD1(hadc->Instance); } @@ -2687,7 +2692,7 @@ /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */ else { - switch(AnalogWDGConfig->WatchdogMode) + switch (AnalogWDGConfig->WatchdogMode) { case ADC_ANALOGWATCHDOG_SINGLE_REG: case ADC_ANALOGWATCHDOG_SINGLE_INJEC: @@ -2703,39 +2708,39 @@ SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL))); } break; - + case ADC_ANALOGWATCHDOG_ALL_REG: case ADC_ANALOGWATCHDOG_ALL_INJEC: case ADC_ANALOGWATCHDOG_ALL_REGINJEC: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ); break; - + default: /* ADC_ANALOGWATCHDOG_NONE */ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE); break; } - + /* Shift the thresholds in function of the selected ADC resolution */ /* have to be left-aligned on bit 7, the LSB (right bits) are set to 0 */ tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); - + /* Set ADC analog watchdog thresholds value of both thresholds high and low */ LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted, tmpAWDLowThresholdShifted); - + if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) { /* Update state, clear previous result related to AWD2 */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2); - + /* Clear flag ADC analog watchdog */ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ /* (in case left enabled by previous ADC operations). */ LL_ADC_ClearFlag_AWD2(hadc->Instance); - + /* Configure ADC analog watchdog interrupt */ - if(AnalogWDGConfig->ITMode == ENABLE) + if (AnalogWDGConfig->ITMode == ENABLE) { LL_ADC_EnableIT_AWD2(hadc->Instance); } @@ -2749,15 +2754,15 @@ { /* Update state, clear previous result related to AWD3 */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3); - + /* Clear flag ADC analog watchdog */ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ /* (in case left enabled by previous ADC operations). */ LL_ADC_ClearFlag_AWD3(hadc->Instance); - + /* Configure ADC analog watchdog interrupt */ - if(AnalogWDGConfig->ITMode == ENABLE) + if (AnalogWDGConfig->ITMode == ENABLE) { LL_ADC_EnableIT_AWD3(hadc->Instance); } @@ -2767,7 +2772,7 @@ } } } - + } /* If a conversion is on going on ADC group regular or injected, no update */ /* could be done on neither of the AWD configuration structure parameters. */ @@ -2775,12 +2780,12 @@ { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - + tmp_hal_status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -2791,14 +2796,14 @@ */ /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions - * @brief ADC Peripheral State functions - * + * @brief ADC Peripheral State functions + * @verbatim =============================================================================== ##### Peripheral state and errors functions ##### =============================================================================== [..] - This subsection provides functions to get in run-time the status of the + This subsection provides functions to get in run-time the status of the peripheral. (+) Check the ADC state (+) Check the ADC error code @@ -2809,19 +2814,19 @@ /** * @brief Return the ADC handle state. - * @note ADC state machine is managed by bitfields, ADC status must be + * @note ADC state machine is managed by bitfields, ADC status must be * compared with states bits. - * For example: + * For example: * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " * @param hadc ADC handle * @retval ADC handle state (bitfield on 32 bits) */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Return ADC handle state */ return hadc->State; } @@ -2835,7 +2840,7 @@ { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + return hadc->ErrorCode; } @@ -2861,7 +2866,7 @@ * @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type. * @retval HAL status. */ -HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup) +HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup) { uint32_t tickstart; uint32_t Conversion_Timeout_CPU_cycles = 0UL; @@ -2869,16 +2874,16 @@ uint32_t tmp_ADC_CR_ADSTART_JADSTART; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup)); - + /* Verification if ADC is not already stopped (on regular and injected */ /* groups) to bypass this function if not needed. */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - if ( (tmp_adc_is_conversion_on_going_regular != 0UL) + if ((tmp_adc_is_conversion_on_going_regular != 0UL) || (tmp_adc_is_conversion_on_going_injected != 0UL) ) { @@ -2888,34 +2893,34 @@ /* injected group stop ADC_CR_JADSTP). */ /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */ /* (see reference manual). */ - if ( ((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL) - && (hadc->Init.ContinuousConvMode == ENABLE) - && (hadc->Init.LowPowerAutoWait == ENABLE) + if (((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL) + && (hadc->Init.ContinuousConvMode == ENABLE) + && (hadc->Init.LowPowerAutoWait == ENABLE) ) { /* Use stop of regular group */ conversion_group_reassigned = ADC_REGULAR_GROUP; - + /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */ - while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL) + while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL) { if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL)) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - + return HAL_ERROR; } Conversion_Timeout_CPU_cycles ++; } - + /* Clear JEOS */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS); } - + /* Stop potential conversion on going on ADC group regular */ if (conversion_group_reassigned != ADC_INJECTED_GROUP) { @@ -2929,7 +2934,7 @@ } } } - + /* Stop potential conversion on going on ADC group injected */ if (conversion_group_reassigned != ADC_REGULAR_GROUP) { @@ -2943,41 +2948,41 @@ } } } - + /* Selection of start and stop bits with respect to the regular or injected group */ - switch(conversion_group_reassigned) + switch (conversion_group_reassigned) { - case ADC_REGULAR_INJECTED_GROUP: + case ADC_REGULAR_INJECTED_GROUP: tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART); break; - case ADC_INJECTED_GROUP: + case ADC_INJECTED_GROUP: tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART; break; - /* Case ADC_REGULAR_GROUP only*/ - default: + /* Case ADC_REGULAR_GROUP only*/ + default: tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART; break; } - + /* Wait for conversion effectively stopped */ tickstart = HAL_GetTick(); - - while((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) + + while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) { - if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT) + if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - + return HAL_ERROR; } } - + } - + /* Return HAL status */ return HAL_OK; } @@ -2991,10 +2996,10 @@ * @param hadc ADC handle * @retval HAL status. */ -HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) { uint32_t tickstart; - + /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ @@ -3006,47 +3011,47 @@ { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - + return HAL_ERROR; } - + /* Enable the ADC peripheral */ LL_ADC_Enable(hadc->Instance); - + /* Wait for ADC effectively enabled */ tickstart = HAL_GetTick(); - - while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) + + while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) { - /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit - has been cleared (after a calibration), ADEN bit is reset by the + /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit + has been cleared (after a calibration), ADEN bit is reset by the calibration logic. The workaround is to continue setting ADEN until ADRDY is becomes 1. Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this 4 ADC clock cycle duration */ /* Note: Test of ADC enabled required due to hardware constraint to */ /* not enable ADC if already enabled. */ - if(LL_ADC_IsEnabled(hadc->Instance) == 0UL) + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { LL_ADC_Enable(hadc->Instance); } - - if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) + + if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - + return HAL_ERROR; } } } - + /* Return HAL status */ return HAL_OK; } @@ -3058,20 +3063,20 @@ * @param hadc ADC handle * @retval HAL status. */ -HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) { uint32_t tickstart; const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance); - + /* Verification if ADC is not already disabled: */ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ /* disabled. */ - if ( (LL_ADC_IsEnabled(hadc->Instance) != 0UL) + if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) && (tmp_adc_is_disable_on_going == 0UL) ) { /* Check if conditions to disable the ADC are fulfilled */ - if((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) + if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) { /* Disable the ADC peripheral */ LL_ADC_Disable(hadc->Instance); @@ -3081,52 +3086,52 @@ { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - + return HAL_ERROR; } - + /* Wait for ADC effectively disabled */ /* Get tick count */ tickstart = HAL_GetTick(); - - while((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) + + while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) { - if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) + if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - + return HAL_ERROR; } } } - + /* Return HAL status */ return HAL_OK; } /** - * @brief DMA transfer complete callback. + * @brief DMA transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Update state machine on conversion status if not in error state */ - if((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) + if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - + /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going */ /* to disable interruption. */ @@ -3134,15 +3139,15 @@ if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL) { /* Are conversions software-triggered ? */ - if(LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) + if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) { /* Is CONT bit set ? */ - if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL) + if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL) { /* CONT bit is not set, no more conversions expected */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - if((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) - { + if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) + { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } @@ -3152,17 +3157,17 @@ { /* DMA End of Transfer interrupt was triggered but conversions sequence is not over. If DMACFG is set to 0, conversions are stopped. */ - if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == 0UL) + if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == 0UL) { /* DMACFG bit is not set, conversions are stopped. */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - if((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) - { + if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) + { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } } - + /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); @@ -3190,15 +3195,15 @@ } /** - * @brief DMA half transfer complete callback. + * @brief DMA half transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); @@ -3215,14 +3220,14 @@ void ADC_DMAError(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); - + /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); - + /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc);
diff --git a/Src/stm32wbxx_hal_adc_ex.c b/Src/stm32wbxx_hal_adc_ex.c index 38f08be..1327585 100644 --- a/Src/stm32wbxx_hal_adc_ex.c +++ b/Src/stm32wbxx_hal_adc_ex.c
@@ -19,7 +19,7 @@ * "stm32wbxx_hal_adc.c". * @verbatim - [..] + [..] (@) Sections "ADC peripheral features" and "How to use this driver" are available in file of generic functions "stm32wbxx_hal_adc.c". [..] @@ -63,7 +63,7 @@ ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\ ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime once the ADC is enabled */ - + /* Fixed timeout value for ADC calibration. */ /* Values defined to be higher than worst cases: maximum ratio between ADC */ /* and CPU clock frequencies. */ @@ -94,7 +94,7 @@ ##### IO operation functions ##### =============================================================================== [..] This section provides functions allowing to: - + (+) Perform the ADC self-calibration for single or differential ending. (+) Get calibration factors for single or differential ending. (+) Set calibration factors for single or differential ending. @@ -105,7 +105,7 @@ (+) Get result of ADC group injected channel conversion. (+) Start conversion of ADC group injected and enable interruptions. (+) Stop conversion of ADC group injected and disable interruptions. - + @endverbatim * @{ */ @@ -121,36 +121,36 @@ * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff) +HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff) { HAL_StatusTypeDef tmp_hal_status; __IO uint32_t wait_loop_index = 0UL; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* Calibration prerequisite: ADC must be disabled. */ - + /* Disable the ADC (if not already disabled) */ tmp_hal_status = ADC_Disable(hadc); - + /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); - + /* Start ADC calibration in mode single-ended or differential */ LL_ADC_StartCalibration(hadc->Instance, SingleDiff); - + /* Wait for calibration completion */ - while(LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) + while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) { wait_loop_index++; if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) @@ -159,14 +159,14 @@ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + return HAL_ERROR; } } - + /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, @@ -175,14 +175,14 @@ else { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - + /* Note: No need to update variable "tmp_hal_status" here: already set */ /* to state "HAL_ERROR" by function disabling the ADC. */ } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -195,14 +195,14 @@ * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @retval Calibration value. */ -uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff) +uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); - + assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); + /* Return the selected ADC calibration value */ - return LL_ADC_GetCalibrationFactor(hadc->Instance, SingleDiff); + return LL_ADC_GetCalibrationFactor(hadc->Instance, SingleDiff); } /** @@ -215,26 +215,26 @@ * @param CalibrationFactor Calibration factor (coded on 7 bits maximum) * @retval HAL state */ -HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor) +HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); assert_param(IS_ADC_CALFACT(CalibrationFactor)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* Verification of hardware constraints before modifying the calibration */ /* factors register: ADC must be enabled, no conversion on going. */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - - if ( (LL_ADC_IsEnabled(hadc->Instance) != 0UL) + + if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) && (tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) @@ -248,14 +248,14 @@ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Update ADC error code */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - + /* Update ADC state machine to error */ tmp_hal_status = HAL_ERROR; } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -266,43 +266,43 @@ * @param hadc ADC handle. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; uint32_t tmp_config_injected_queue; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) { return HAL_BUSY; } else { - /* In case of software trigger detection enabled, JQDIS must be set + /* In case of software trigger detection enabled, JQDIS must be set (which can be done only if ADSTART and JADSTART are both cleared). If JQDIS is not set at that point, returns an error - since software trigger detection is disabled. User needs to - resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS. - - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means + resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS. + - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means the queue is empty */ tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); - - if ( (READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL) + + if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL) && (tmp_config_injected_queue == 0UL) ) { - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); return HAL_ERROR; } - + /* Process locked */ __HAL_LOCK(hadc); - + /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); - + /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { @@ -317,23 +317,23 @@ /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); } - + /* Set ADC state */ /* - Clear state bitfield related to injected group conversion results */ /* - Set state bitfield related to injected operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - + /* Clear ADC group injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); - + /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); - + /* Enable conversion of injected group, if automatic injected conversion */ /* is disabled. */ /* If software start has been selected, conversion starts immediately. */ @@ -344,13 +344,13 @@ /* Start ADC group injected conversion */ LL_ADC_INJ_StartConversion(hadc->Instance); } - } + } else { /* Process unlocked */ - __HAL_UNLOCK(hadc); + __HAL_UNLOCK(hadc); } - + /* Return function status */ return tmp_hal_status; } @@ -359,7 +359,7 @@ /** * @brief Stop conversion of injected channels. Disable ADC peripheral if * no regular conversion is on going. - * @note If ADC must be disabled and if conversion is on going on + * @note If ADC must be disabled and if conversion is on going on * regular group, function HAL_ADC_Stop must be used to stop both * injected and regular groups, and disable the ADC. * @note If injected group mode auto-injection is enabled, @@ -367,19 +367,19 @@ * @param hadc ADC handle. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* 1. Stop potential conversion on going on injected group only. */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP); - + /* Disable ADC peripheral if injected conversions are effectively stopped */ /* and if no conversion on regular group is on-going */ if (tmp_hal_status == HAL_OK) @@ -388,7 +388,7 @@ { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); - + /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { @@ -406,10 +406,10 @@ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); } } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -422,14 +422,14 @@ * checked and cleared depending on AUTDLY bit status. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) +HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) { uint32_t tickstart; uint32_t tmp_Flag_End; uint32_t tmp_adc_inj_is_trigger_source_sw_start; uint32_t tmp_adc_reg_is_trigger_source_sw_start; uint32_t tmp_cfgr; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -442,47 +442,47 @@ { tmp_Flag_End = ADC_FLAG_JEOC; } - + /* Get timeout */ tickstart = HAL_GetTick(); - - /* Wait until End of Conversion or Sequence flag is raised */ - while((hadc->Instance->ISR & tmp_Flag_End) == 0UL) + + /* Wait until End of Conversion or Sequence flag is raised */ + while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) { /* Check if timeout is disabled (set to infinite wait) */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + return HAL_TIMEOUT; } } } - + /* Retrieve ADC configuration */ tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance); tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance); tmp_cfgr = READ_REG(hadc->Instance->CFGR); - + /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); - + /* Determine whether any further conversion upcoming on group injected */ /* by external trigger or by automatic injected conversion */ /* from group regular. */ - if((tmp_adc_inj_is_trigger_source_sw_start != 0UL) || - ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) && - ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && - (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == 0UL) ) ) ) + if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) || + ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) && + ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && + (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))) { /* Check whether end of sequence is reached */ - if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) ) + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) { /* Particular case if injected contexts queue is enabled: */ /* when the last context has been fully processed, JSQR is reset */ @@ -490,19 +490,19 @@ /* (queue empty, triggers are ignored), it can start again */ /* immediately after setting a new context (JADSTART is still set). */ /* Therefore, state of HAL ADC injected group is kept to busy. */ - if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM) == 0UL) + if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM) == 0UL) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - - if((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) + + if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } } } - + /* Clear polled flag */ if (tmp_Flag_End == ADC_FLAG_JEOS) { @@ -519,7 +519,7 @@ { __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); } - + /* Return API HAL status */ return HAL_OK; } @@ -527,47 +527,47 @@ /** * @brief Enable ADC, start conversion of injected group with interruption. * @note Interruptions enabled in this function according to initialization - * setting : JEOC (end of conversion) or JEOS (end of sequence) + * setting : JEOC (end of conversion) or JEOS (end of sequence) * @param hadc ADC handle. * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; uint32_t tmp_config_injected_queue; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) { return HAL_BUSY; } else { - /* In case of software trigger detection enabled, JQDIS must be set + /* In case of software trigger detection enabled, JQDIS must be set (which can be done only if ADSTART and JADSTART are both cleared). If JQDIS is not set at that point, returns an error - since software trigger detection is disabled. User needs to - resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS. - - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means + resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS. + - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means the queue is empty */ tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); - - if ( (READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL) + + if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL) && (tmp_config_injected_queue == 0UL) ) { - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); return HAL_ERROR; } /* Process locked */ __HAL_LOCK(hadc); - + /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); - + /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { @@ -575,51 +575,51 @@ if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL) { /* Reset ADC error code field related to injected conversions only */ - CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); + CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); } else { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); } - + /* Set ADC state */ /* - Clear state bitfield related to injected group conversion results */ /* - Set state bitfield related to injected operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - + /* Clear ADC group injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); - + /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); - + /* Enable ADC Injected context queue overflow interrupt if this feature */ /* is enabled. */ if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != 0UL) { __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF); } - + /* Enable ADC end of conversion interrupt */ - switch(hadc->Init.EOCSelection) + switch (hadc->Init.EOCSelection) { - case ADC_EOC_SEQ_CONV: + case ADC_EOC_SEQ_CONV: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); break; /* case ADC_EOC_SINGLE_CONV */ default: - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); break; } - + /* Enable conversion of injected group, if automatic injected conversion */ /* is disabled. */ /* If software start has been selected, conversion starts immediately. */ @@ -636,17 +636,17 @@ /* Process unlocked */ __HAL_UNLOCK(hadc); } - + /* Return function status */ return tmp_hal_status; } } /** - * @brief Stop conversion of injected channels, disable interruption of + * @brief Stop conversion of injected channels, disable interruption of * end-of-conversion. Disable ADC peripheral if no regular conversion * is on going. - * @note If ADC must be disabled and if conversion is on going on + * @note If ADC must be disabled and if conversion is on going on * regular group, function HAL_ADC_Stop must be used to stop both * injected and regular groups, and disable the ADC. * @note If injected group mode auto-injection is enabled, @@ -655,19 +655,19 @@ * @param hadc ADC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* 1. Stop potential conversion on going on injected group only. */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP); - + /* Disable ADC peripheral if injected conversions are effectively stopped */ /* and if no conversion on the other group (regular group) is intended to */ /* continue. */ @@ -675,12 +675,12 @@ { /* Disable ADC end of conversion interrupt for injected channels */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF)); - + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); - + /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { @@ -701,7 +701,7 @@ /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -710,7 +710,7 @@ * @brief Get ADC injected group conversion result. * @note Reading register JDRx automatically clears ADC flag JEOC * (ADC group injected end of unitary conversion). - * @note This function does not clear ADC flag JEOS + * @note This function does not clear ADC flag JEOS * (ADC group injected end of sequence conversion) * Occurrence of flag JEOS rising: * - If sequencer is composed of 1 rank, flag JEOS is equivalent @@ -721,9 +721,9 @@ * Flag JEOS must not be cleared by this function because * it would not be compliant with low power features * (feature low power auto-wait, not available on all STM32 families). - * To clear this flag, either use function: + * To clear this flag, either use function: * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming - * model polling: @ref HAL_ADCEx_InjectedPollForConversion() + * model polling: @ref HAL_ADCEx_InjectedPollForConversion() * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS). * @param hadc ADC handle * @param InjectedRank the converted ADC injected rank. @@ -734,24 +734,24 @@ * @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4 * @retval ADC group injected conversion data */ -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) +uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank) { uint32_t tmp_jdr; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); - + /* Get ADC converted value */ - switch(InjectedRank) - { + switch (InjectedRank) + { case ADC_INJECTED_RANK_4: tmp_jdr = hadc->Instance->JDR4; break; - case ADC_INJECTED_RANK_3: + case ADC_INJECTED_RANK_3: tmp_jdr = hadc->Instance->JDR3; break; - case ADC_INJECTED_RANK_2: + case ADC_INJECTED_RANK_2: tmp_jdr = hadc->Instance->JDR2; break; case ADC_INJECTED_RANK_1: @@ -759,8 +759,8 @@ tmp_jdr = hadc->Instance->JDR1; break; } - - /* Return ADC converted value */ + + /* Return ADC converted value */ return tmp_jdr; } @@ -769,11 +769,11 @@ * @param hadc ADC handle * @retval None */ -__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); - + /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file. */ @@ -788,11 +788,11 @@ * @param hadc ADC handle * @retval None */ -__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); - + /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file. */ @@ -803,11 +803,11 @@ * @param hadc ADC handle * @retval None */ -__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); - + /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file. */ @@ -818,11 +818,11 @@ * @param hadc ADC handle * @retval None */ -__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); - + /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file. */ @@ -834,48 +834,48 @@ * @param hadc ADC handle * @retval None */ -__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); - + /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file. */ } /** - * @brief Stop ADC conversion of regular group (and injected channels in - * case of auto_injection mode), disable ADC peripheral if no + * @brief Stop ADC conversion of regular group (and injected channels in + * case of auto_injection mode), disable ADC peripheral if no * conversion is on going on injected group. * @param hadc ADC handle * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* 1. Stop potential regular conversion on going */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); - - /* Disable ADC peripheral if regular conversions are effectively stopped + + /* Disable ADC peripheral if regular conversions are effectively stopped and if no injected conversions are on-going */ if (tmp_hal_status == HAL_OK) { - /* Clear HAL_ADC_STATE_REG_BUSY bit */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - + /* Clear HAL_ADC_STATE_REG_BUSY bit */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); - + /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { @@ -892,10 +892,10 @@ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); } } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -909,32 +909,32 @@ * @param hadc ADC handle * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* 1. Stop potential regular conversion on going */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); - + /* Disable ADC peripheral if conversions are effectively stopped and if no injected conversion is on-going */ if (tmp_hal_status == HAL_OK) { - /* Clear HAL_ADC_STATE_REG_BUSY bit */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - + /* Clear HAL_ADC_STATE_REG_BUSY bit */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + /* Disable all regular-related interrupts */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); - + /* 2. Disable ADC peripheral if no injected conversions are on-going */ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) - { + { tmp_hal_status = ADC_Disable(hadc); /* if no issue reported */ if (tmp_hal_status == HAL_OK) @@ -950,59 +950,59 @@ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); } } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } /** - * @brief Stop ADC conversion of regular group (and injected group in - * case of auto_injection mode), disable ADC DMA transfer, disable + * @brief Stop ADC conversion of regular group (and injected group in + * case of auto_injection mode), disable ADC DMA transfer, disable * ADC peripheral if no conversion is on going * on injected group. * @param hadc ADC handle * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* 1. Stop potential regular conversion on going */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); - - /* Disable ADC peripheral if conversions are effectively stopped + + /* Disable ADC peripheral if conversions are effectively stopped and if no injected conversion is on-going */ if (tmp_hal_status == HAL_OK) { /* Clear HAL_ADC_STATE_REG_BUSY bit */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - + /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */ - CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); - + CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); + /* Disable the DMA channel (in case of DMA in circular mode or stop while */ /* while DMA transfer is on going) */ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - + /* Check if DMA channel effectively disabled */ if (tmp_hal_status != HAL_OK) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } - + /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); - + /* 2. Disable the ADC peripheral */ /* Update "tmp_hal_status" only if DMA channel disabling passed, */ /* to keep in memory a potential failing status. */ @@ -1016,7 +1016,7 @@ { (void)ADC_Disable(hadc); } - + /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { @@ -1031,10 +1031,10 @@ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); } } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -1046,7 +1046,7 @@ /** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions * @brief ADC Extended Peripheral Control functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== @@ -1055,7 +1055,7 @@ (+) Enable or Disable Injected Queue (+) Disable ADC voltage regulator (+) Enter ADC deep-power-down mode - + @endverbatim * @{ */ @@ -1063,38 +1063,38 @@ /** * @brief Configure a channel to be assigned to ADC group injected. * @note Possibility to update parameters on the fly: - * This function initializes injected group, following calls to this + * This function initializes injected group, following calls to this * function can be used to reconfigure some parameters of structure * "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC. * The setting of these parameters is conditioned to ADC state: * Refer to comments of structure "ADC_InjectionConfTypeDef". * @note In case of usage of internal measurement channels: * Vbat/VrefInt/TempSensor. - * These internal paths can be disabled using function + * These internal paths can be disabled using function * HAL_ADC_DeInit(). - * @note Caution: For Injected Context Queue use, a context must be fully - * defined before start of injected conversion. All channels are configured - * consecutively for the same ADC instance. Therefore, the number of calls to - * HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter + * @note Caution: For Injected Context Queue use, a context must be fully + * defined before start of injected conversion. All channels are configured + * consecutively for the same ADC instance. Therefore, the number of calls to + * HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter * InjectedNbrOfConversion for each context. - * - Example 1: If 1 context is intended to be used (or if there is no use of the - * Injected Queue Context feature) and if the context contains 3 injected ranks - * (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be - * called once for each channel (i.e. 3 times) before starting a conversion. - * This function must not be called to configure a 4th injected channel: + * - Example 1: If 1 context is intended to be used (or if there is no use of the + * Injected Queue Context feature) and if the context contains 3 injected ranks + * (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be + * called once for each channel (i.e. 3 times) before starting a conversion. + * This function must not be called to configure a 4th injected channel: * it would start a new context into context queue. - * - Example 2: If 2 contexts are intended to be used and each of them contains - * 3 injected ranks (InjectedNbrOfConversion = 3), - * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and - * for each context (3 channels x 2 contexts = 6 calls). Conversion can - * start once the 1st context is set, that is after the first three + * - Example 2: If 2 contexts are intended to be used and each of them contains + * 3 injected ranks (InjectedNbrOfConversion = 3), + * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and + * for each context (3 channels x 2 contexts = 6 calls). Conversion can + * start once the 1st context is set, that is after the first three * HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly. * @param hadc ADC handle * @param sConfigInjected Structure of ADC injected group and ADC channel for * injected group. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpOffsetShifted; @@ -1102,9 +1102,9 @@ uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; __IO uint32_t wait_loop_index = 0; - + uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); @@ -1116,38 +1116,38 @@ assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber)); assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode)); - - if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) + + if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) { assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); } - - - /* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is + + + /* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is ignored (considered as reset) */ - assert_param(!((sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) && (sConfigInjected->InjecOversamplingMode == ENABLE))); - + assert_param(!((sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) && (sConfigInjected->InjecOversamplingMode == ENABLE))); + /* JDISCEN and JAUTO bits can't be set at the same time */ - assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE))); - + assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE))); + /* DISCEN and JAUTO bits can't be set at the same time */ - assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE))); - + assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE))); + /* Verification of channel number */ if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED) { - assert_param(IS_ADC_CHANNEL(hadc, sConfigInjected->InjectedChannel)); + assert_param(IS_ADC_CHANNEL(hadc, sConfigInjected->InjectedChannel)); } else { assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfigInjected->InjectedChannel)); } - + /* Process locked */ __HAL_LOCK(hadc); - + /* Configuration of injected group sequencer: */ /* Hardware constraint: Must fully define injected context register JSQR */ /* before make it entering into injected sequencer queue. */ @@ -1168,9 +1168,9 @@ /* injected ranks have been set. */ /* Note: Scan mode is not present by hardware on this device, but used */ /* by software for alignment over all STM32 devices. */ - + if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) || - (sConfigInjected->InjectedNbrOfConversion == 1U) ) + (sConfigInjected->InjectedNbrOfConversion == 1U)) { /* Configuration of context register JSQR: */ /* - number of ranks in injected group sequencer: fixed to 1st rank */ @@ -1178,7 +1178,7 @@ /* - external trigger to start conversion */ /* - external trigger polarity */ /* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */ - + if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) { /* Enable external trigger if trigger selection is different of */ @@ -1188,20 +1188,20 @@ /* software start. */ if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { - tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) - | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) - | sConfigInjected->ExternalTrigInjecConvEdge - ); + tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) + | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) + | sConfigInjected->ExternalTrigInjecConvEdge + ); } else { - tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) ); + tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)); } - - MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt); + + MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt); /* For debug and informative reasons, hadc handle saves JSQR setting */ hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt; - + } } else @@ -1213,10 +1213,10 @@ /* calls of this function, for each injected channel rank: */ /* 1. Start new context and set parameters related to all injected */ /* channels: injected sequence length and trigger. */ - + /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */ /* call of the context under setting */ - if (hadc->InjectionConfig.ChannelCount == 0U) + if (hadc->InjectionConfig.ChannelCount == 0U) { /* Initialize number of channels that will be configured on the context */ /* being built */ @@ -1224,13 +1224,13 @@ /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel() call, this context will be written in JSQR register at the last call. At this point, the context is merely reset */ - hadc->InjectionConfig.ContextQueue = 0x00000000U; - + hadc->InjectionConfig.ContextQueue = 0x00000000U; + /* Configuration of context register JSQR: */ /* - number of ranks in injected group sequencer */ /* - external trigger to start conversion */ /* - external trigger polarity */ - + /* Enable external trigger if trigger selection is different of */ /* software start. */ /* Note: This configuration keeps the hardware feature of parameter */ @@ -1238,39 +1238,39 @@ /* software start. */ if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { - tmp_JSQR_ContextQueueBeingBuilt = ( (sConfigInjected->InjectedNbrOfConversion - 1U) - | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) - | sConfigInjected->ExternalTrigInjecConvEdge - ); + tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U) + | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) + | sConfigInjected->ExternalTrigInjecConvEdge + ); } else { - tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U) ); + tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U)); } - + } - + /* 2. Continue setting of context under definition with parameter */ /* related to each channel: channel rank sequence */ /* Clear the old JSQx bits for the selected rank */ tmp_JSQR_ContextQueueBeingBuilt &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank); - + /* Set the JSQx bits for the selected rank */ tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank); - + /* Decrease channel count */ hadc->InjectionConfig.ChannelCount--; - + /* 3. tmp_JSQR_ContextQueueBeingBuilt is fully built for this HAL_ADCEx_InjectedConfigChannel() - call, aggregate the setting to those already built during the previous + call, aggregate the setting to those already built during the previous HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course) */ hadc->InjectionConfig.ContextQueue |= tmp_JSQR_ContextQueueBeingBuilt; - + /* 4. End of context setting: if this is the last channel set, then write context into register JSQR and make it enter into queue */ if (hadc->InjectionConfig.ChannelCount == 0U) { - MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue); + MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue); } } @@ -1285,23 +1285,23 @@ { /* If auto-injected mode is disabled: no constraint */ if (sConfigInjected->AutoInjectedConv == DISABLE) - { + { MODIFY_REG(hadc->Instance->CFGR, - ADC_CFGR_JQM | ADC_CFGR_JDISCEN, + ADC_CFGR_JQM | ADC_CFGR_JDISCEN, ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext) | - ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)sConfigInjected->InjectedDiscontinuousConvMode) ); + ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)sConfigInjected->InjectedDiscontinuousConvMode)); } /* If auto-injected mode is enabled: Injected discontinuous setting is */ /* discarded. */ else { MODIFY_REG(hadc->Instance->CFGR, - ADC_CFGR_JQM | ADC_CFGR_JDISCEN, - ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext) ); + ADC_CFGR_JQM | ADC_CFGR_JDISCEN, + ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext)); } } - + /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular and injected groups: */ @@ -1311,24 +1311,24 @@ /* - Channel offset */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - - if ( (tmp_adc_is_conversion_on_going_regular == 0UL) + + if ((tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) { /* If injected group external triggers are disabled (set to injected */ /* software start): no constraint */ if ((sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) - || (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)) + || (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)) { - if (sConfigInjected->AutoInjectedConv == ENABLE) - { - SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); - } - else - { - CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); - } + if (sConfigInjected->AutoInjectedConv == ENABLE) + { + SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); + } + else + { + CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); + } } /* If Automatic injected conversion was intended to be set and could not */ /* due to injected group external triggers enabled, error is reported. */ @@ -1338,57 +1338,58 @@ { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - + tmp_hal_status = HAL_ERROR; } else { - CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); + CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); } } - + if (sConfigInjected->InjecOversamplingMode == ENABLE) { assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio)); assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift)); - + /* JOVSE must be reset in case of triggered regular mode */ - assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE|ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE|ADC_CFGR2_TROVS))); - + assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS))); + /* Configuration of Injected Oversampler: */ /* - Oversampling Ratio */ /* - Right bit shift */ - + /* Enable OverSampling mode */ - MODIFY_REG(hadc->Instance->CFGR2, - ADC_CFGR2_JOVSE | - ADC_CFGR2_OVSR | - ADC_CFGR2_OVSS, - ADC_CFGR2_JOVSE | - sConfigInjected->InjecOversampling.Ratio | - sConfigInjected->InjecOversampling.RightBitShift - ); + MODIFY_REG(hadc->Instance->CFGR2, + ADC_CFGR2_JOVSE | + ADC_CFGR2_OVSR | + ADC_CFGR2_OVSS, + ADC_CFGR2_JOVSE | + sConfigInjected->InjecOversampling.Ratio | + sConfigInjected->InjecOversampling.RightBitShift + ); } else { /* Disable Regular OverSampling */ - CLEAR_BIT( hadc->Instance->CFGR2, ADC_CFGR2_JOVSE); + CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE); } - + /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime); - + /* Configure the offset: offset enable/disable, channel, offset value */ - + /* Shift the offset with respect to the selected ADC resolution. */ /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset); - - if(sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) + + if (sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) { /* Set ADC selected offset number */ - LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel, tmpOffsetShifted); - + LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel, + tmpOffsetShifted); + } else { @@ -1396,24 +1397,24 @@ /* If this is the case, the corresponding offset number is disabled. */ if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { - LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE); + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE); } if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { - LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE); + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE); } if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { - LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE); + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE); } if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { - LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE); + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE); } } - + } - + /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ @@ -1422,7 +1423,7 @@ { /* Set mode single-ended or differential input of the selected ADC channel */ LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSingleDiff); - + /* Configuration of differential mode */ /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED) @@ -1430,13 +1431,13 @@ /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel) + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime); } - + /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */ /* internal measurement paths enable: If internal channel selected, */ /* enable dedicated internal buffers and path. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ - + if(__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel)) { /* Configuration of common ADC parameters (continuation) */ @@ -1445,7 +1446,7 @@ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) { tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); - + /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) @@ -1453,7 +1454,7 @@ if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); - + /* Delay for temperature sensor stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ @@ -1467,14 +1468,14 @@ } } else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) - { + { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); } } else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) - { + { if (ADC_VREFINT_INSTANCE(hadc)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); @@ -1488,20 +1489,20 @@ /* If the requested internal measurement path has already been enabled */ /* and other ADC of the common group are enabled, internal */ /* measurement paths cannot be enabled. */ - else + else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - + tmp_hal_status = HAL_ERROR; } } - + } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -1510,40 +1511,40 @@ * @brief Enable Injected Queue * @note This function resets CFGR register JQDIS bit in order to enable the * Injected Queue. JQDIS can be written only when ADSTART and JDSTART - * are both equal to 0 to ensure that no regular nor injected - * conversion is ongoing. + * are both equal to 0 to ensure that no regular nor injected + * conversion is ongoing. * @param hadc ADC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - + /* Parameter can be set only if no conversion is on-going */ - if ( (tmp_adc_is_conversion_on_going_regular == 0UL) + if ((tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) { CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); - + /* Update state, clear previous result related to injected queue overflow */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); - + tmp_hal_status = HAL_OK; } else { tmp_hal_status = HAL_ERROR; } - + return tmp_hal_status; } @@ -1551,25 +1552,25 @@ * @brief Disable Injected Queue * @note This function sets CFGR register JQDIS bit in order to disable the * Injected Queue. JQDIS can be written only when ADSTART and JDSTART - * are both equal to 0 to ensure that no regular nor injected - * conversion is ongoing. + * are both equal to 0 to ensure that no regular nor injected + * conversion is ongoing. * @param hadc ADC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - + /* Parameter can be set only if no conversion is on-going */ - if ( (tmp_adc_is_conversion_on_going_regular == 0UL) + if ((tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) { @@ -1580,7 +1581,7 @@ { tmp_hal_status = HAL_ERROR; } - + return tmp_hal_status; } @@ -1588,18 +1589,18 @@ * @brief Disable ADC voltage regulator. * @note Disabling voltage regulator allows to save power. This operation can * be carried out only when ADC is disabled. - * @note To enable again the voltage regulator, the user is expected to + * @note To enable again the voltage regulator, the user is expected to * resort to HAL_ADC_Init() API. * @param hadc ADC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { @@ -1610,33 +1611,33 @@ { tmp_hal_status = HAL_ERROR; } - + return tmp_hal_status; } /** * @brief Enter ADC deep-power-down mode - * @note This mode is achieved in setting DEEPPWD bit and allows to save power - * in reducing leakage currents. It is particularly interesting before + * @note This mode is achieved in setting DEEPPWD bit and allows to save power + * in reducing leakage currents. It is particularly interesting before * entering stop modes. * @note Setting DEEPPWD automatically clears ADVREGEN bit and disables the * ADC voltage regulator. This means that this API encompasses * HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal * calibration is lost. - * @note To exit the ADC deep-power-down mode, the user is expected to + * @note To exit the ADC deep-power-down mode, the user is expected to * resort to HAL_ADC_Init() API as well as to relaunch a calibration * with HAL_ADCEx_Calibration_Start() API or to re-apply a previously * saved calibration factor. * @param hadc ADC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { @@ -1647,7 +1648,7 @@ { tmp_hal_status = HAL_ERROR; } - + return tmp_hal_status; }
diff --git a/Src/stm32wbxx_hal_comp.c b/Src/stm32wbxx_hal_comp.c index 03b4bd7..a113b0d 100644 --- a/Src/stm32wbxx_hal_comp.c +++ b/Src/stm32wbxx_hal_comp.c
@@ -168,7 +168,7 @@ #ifdef HAL_COMP_MODULE_ENABLED - +#if defined (COMP1) || defined (COMP2) /** @defgroup COMP COMP * @brief COMP HAL module driver @@ -981,7 +981,7 @@ * @} */ - +#endif /* COMP1 || COMP2 */ #endif /* HAL_COMP_MODULE_ENABLED */
diff --git a/Src/stm32wbxx_hal_dma.c b/Src/stm32wbxx_hal_dma.c index e394777..096128d 100644 --- a/Src/stm32wbxx_hal_dma.c +++ b/Src/stm32wbxx_hal_dma.c
@@ -18,17 +18,15 @@ necessary). Please refer to the Reference manual for connection between peripherals and DMA requests. - __HAL_RCC_DMAMUX1_CLK_ENABLE - (#) For a given Channel, program the required configuration through the following parameters: Channel request, Transfer Direction, Source and Destination data formats, Circular or Normal mode, Channel Priority level, Source and Destination Increment mode using HAL_DMA_Init() function. - Prior to HAL_DMA_Init the CLK shall be enabled for both DMA & DMAMUX + Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX thanks to: - DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE() ; - DMAMUX1: __HAL_RCC_DMAMUX1_CLK_ENABLE(); + (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE() ; + (##) DMAMUX1: __HAL_RCC_DMAMUX1_CLK_ENABLE(); (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error detection. @@ -36,6 +34,7 @@ (#) Use HAL_DMA_Abort() function to abort the current transfer -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + *** Polling mode IO operation *** ================================= [..] @@ -54,13 +53,12 @@ In this case the DMA interrupt is configured (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can - add his own function by customization of function pointer XferCpltCallback and - XferErrorCallback (i.e. a member of DMA handle structure). + add his own function to register callbacks with HAL_DMA_RegisterCallback(). *** DMA HAL driver macros list *** ============================================= [..] - Below the list of most used macros in DMA HAL driver. + Below the list of macros in DMA HAL driver. (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. @@ -68,7 +66,7 @@ (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. - (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not. [..] (@) You can refer to the DMA HAL driver header file for more useful macros @@ -172,19 +170,25 @@ assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request)); +#if defined(DMA2) /* Compute the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) { /* DMA1 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; hdma->DmaBaseAddress = DMA1; } else { /* DMA2 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; hdma->DmaBaseAddress = DMA2; } +#else + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA1; +#endif /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; @@ -263,6 +267,7 @@ */ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) { + /* Check the DMA handle allocation */ if (NULL == hdma) { @@ -275,19 +280,25 @@ /* Disable the selected DMA Channelx */ __HAL_DMA_DISABLE(hdma); +#if defined(DMA2) /* Compute the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) { /* DMA1 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; hdma->DmaBaseAddress = DMA1; } else { /* DMA2 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; hdma->DmaBaseAddress = DMA2; } +#else + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA1; +#endif /* Reset DMA Channel control register */ hdma->Instance->CCR = 0U; @@ -645,9 +656,9 @@ /* Get tick */ tickstart = HAL_GetTick(); - while (0U == (hdma->DmaBaseAddress->ISR & temp)) + while((hdma->DmaBaseAddress->ISR & temp) == 0U) { - if ((0U != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU))))) + if((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex& 0x1CU))) != 0U) { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ @@ -753,7 +764,7 @@ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); } /* Clear the half transfer complete flag */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1cU)); + hdma->DmaBaseAddress->IFCR = (DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU)); /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ @@ -766,7 +777,7 @@ } /* Transfer Complete Interrupt management ***********************************/ - else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TC))) + else if (((flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_TC) != 0U)) { if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { @@ -956,7 +967,7 @@ */ /** - * @brief Return the DMA hande state. + * @brief Return the DMA handle state. * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL state @@ -1016,7 +1027,7 @@ /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; - /* Peripheral to Memory */ + /* Memory to Peripheral */ if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) { /* Configure DMA Channel destination address */ @@ -1025,7 +1036,7 @@ /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; } - /* Memory to Peripheral */ + /* Peripheral to Memory */ else { /* Configure DMA Channel source address */ @@ -1037,9 +1048,9 @@ } /** - * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on stream number + * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on channel number * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. + * the configuration information for the specified DMA Channel. * @retval None */ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) @@ -1047,6 +1058,7 @@ uint32_t channel_number; /* check if instance is not outside the DMA channel range */ +#if defined(DMA2) if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) { /* DMA1 */ @@ -1057,6 +1069,10 @@ /* DMA2 */ hdma->DMAmuxChannel = (DMAMUX1_Channel7 + (hdma->ChannelIndex >> 2U)); } +#else + /* DMA1 */ + hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U)); +#endif channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1cU); @@ -1065,7 +1081,7 @@ /** * @brief Updates the DMA handle with the DMAMUX request generator params * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. + * the configuration information for the specified DMA Channel. * @retval None */ @@ -1078,7 +1094,7 @@ hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; - /* here "Request" is either DMA_REQUEST_GENERATOR0 to 4, i.e. <= 4*/ + /* here "Request" is either DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR3, i.e. <= 4*/ hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U); }
diff --git a/Src/stm32wbxx_hal_dma_ex.c b/Src/stm32wbxx_hal_dma_ex.c index 22a38c1..fe223c6 100644 --- a/Src/stm32wbxx_hal_dma_ex.c +++ b/Src/stm32wbxx_hal_dma_ex.c
@@ -76,8 +76,8 @@ =============================================================================== [..] This section provides functions allowing to: - (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. - (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. + (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. + (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used to respectively enable/disable the request generator.
diff --git a/Src/stm32wbxx_hal_irda.c b/Src/stm32wbxx_hal_irda.c index f2a3373..b931497 100644 --- a/Src/stm32wbxx_hal_irda.c +++ b/Src/stm32wbxx_hal_irda.c
@@ -2213,6 +2213,7 @@ IRDA_ClockSourceTypeDef clocksource; HAL_StatusTypeDef ret = HAL_OK; const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; + uint32_t pclk; /* Check the communication parameters */ assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate)); @@ -2241,7 +2242,7 @@ MODIFY_REG(hirda->Instance->PRESC, USART_PRESC_PRESCALER, hirda->Init.ClockPrescaler); /*-------------------------- USART GTPR Configuration ----------------------*/ - MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler); + MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)hirda->Init.Prescaler); /*-------------------------- USART BRR Configuration -----------------------*/ IRDA_GETCLOCKSOURCE(hirda, clocksource); @@ -2249,13 +2250,15 @@ switch (clocksource) { case IRDA_CLOCKSOURCE_PCLK2: - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK2Freq(); + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); break; case IRDA_CLOCKSOURCE_HSI: tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); break; case IRDA_CLOCKSOURCE_SYSCLK: - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + pclk = HAL_RCC_GetSysClockFreq(); + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); break; case IRDA_CLOCKSOURCE_LSE: tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
diff --git a/Src/stm32wbxx_hal_iwdg.c b/Src/stm32wbxx_hal_iwdg.c index e938601..b6db8e5 100644 --- a/Src/stm32wbxx_hal_iwdg.c +++ b/Src/stm32wbxx_hal_iwdg.c
@@ -36,7 +36,7 @@ (+) Debug mode : When the microcontroller enters debug mode (core halted), the IWDG counter either continues to work normally or stops, depending on DBG_IWDG_STOP configuration bit in DBG module, accessible through - __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros + __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros. [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s The IWDG timeout may vary due to LSI frequency dispersion. STM32WBxx @@ -49,17 +49,17 @@ [..] (#) Use IWDG using HAL_IWDG_Init() function to : (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI - clock is forced ON and IWDG counter starts downcounting. - (++) Enable write access to configuration register: IWDG_PR, IWDG_RLR & - IWDG_WINR. + clock is forced ON and IWDG counter starts counting down. + (++) Enable write access to configuration registers: + IWDG_PR, IWDG_RLR and IWDG_WINR. (++) Configure the IWDG prescaler and counter reload value. This reload value will be loaded in the IWDG counter each time the watchdog is reloaded, then the IWDG will start counting down from this value. - (++) wait for status flags to be reset + (++) Wait for status flags to be reset. (++) Depending on window parameter: (+++) If Window Init parameter is same as Window register value, nothing more is done but reload counter value in order to exit - function withy exact time base. + function with exact time base. (+++) Else modify Window register. This will automatically reload watchdog counter. @@ -167,7 +167,7 @@ assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window)); - /* Enable IWDG. LSI is turned on automaticaly */ + /* Enable IWDG. LSI is turned on automatically */ __HAL_IWDG_START(hiwdg); /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
diff --git a/Src/stm32wbxx_hal_lcd.c b/Src/stm32wbxx_hal_lcd.c index 41152ea..b2d55ed 100644 --- a/Src/stm32wbxx_hal_lcd.c +++ b/Src/stm32wbxx_hal_lcd.c
@@ -89,6 +89,8 @@ #ifdef HAL_LCD_MODULE_ENABLED +#if defined (LCD) + /** @defgroup LCD LCD * @brief LCD HAL module driver * @{ @@ -597,6 +599,8 @@ * @} */ +#endif /* LCD */ + #endif /* HAL_LCD_MODULE_ENABLED */ /**
diff --git a/Src/stm32wbxx_hal_lptim.c b/Src/stm32wbxx_hal_lptim.c index 7b9188a..2bd7242 100644 --- a/Src/stm32wbxx_hal_lptim.c +++ b/Src/stm32wbxx_hal_lptim.c
@@ -152,7 +152,8 @@ * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause - * ****************************************************************************** + * + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -180,6 +181,7 @@ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim); #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag); /* Exported functions --------------------------------------------------------*/ @@ -351,6 +353,11 @@ /* Disable the LPTIM Peripheral Clock */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) if (hlptim->MspDeInitCallback == NULL) { @@ -459,12 +466,30 @@ /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); @@ -491,6 +516,11 @@ /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Change the TIM state*/ hlptim->State = HAL_LPTIM_STATE_READY; @@ -520,6 +550,41 @@ /* Reset WAVE bit to set PWM mode */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + + /* Load the pulse value in the compare register */ + __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); + + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Enable Autoreload write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); @@ -542,12 +607,6 @@ /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Load the pulse value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); @@ -574,6 +633,11 @@ /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Disable Autoreload write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); @@ -625,12 +689,30 @@ /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); @@ -657,6 +739,11 @@ /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Change the TIM state*/ hlptim->State = HAL_LPTIM_STATE_READY; @@ -686,6 +773,41 @@ /* Reset WAVE bit to set one pulse mode */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + + /* Load the pulse value in the compare register */ + __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); + + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Enable Autoreload write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); @@ -708,12 +830,6 @@ /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Load the pulse value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); @@ -740,6 +856,11 @@ /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Disable Autoreload write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); @@ -791,12 +912,30 @@ /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); @@ -823,6 +962,11 @@ /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Change the TIM state*/ hlptim->State = HAL_LPTIM_STATE_READY; @@ -852,6 +996,41 @@ /* Set WAVE bit to enable the set once mode */ hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE; + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + + /* Load the pulse value in the compare register */ + __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); + + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Enable Autoreload write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); @@ -874,12 +1053,6 @@ /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Load the pulse value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); @@ -906,6 +1079,11 @@ /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Disable Autoreload write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); @@ -971,9 +1149,18 @@ /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); @@ -1000,6 +1187,11 @@ /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Reset ENC bit to disable the encoder interface */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; @@ -1047,6 +1239,29 @@ /* Set ENC bit to enable the encoder interface */ hlptim->Instance->CFGR |= LPTIM_CFGR_ENC; + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Enable "switch to down direction" interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN); @@ -1056,9 +1271,6 @@ /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); @@ -1085,6 +1297,11 @@ /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Reset ENC bit to disable the encoder interface */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; @@ -1128,12 +1345,30 @@ /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + /* Load the Timeout value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Timeout); + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); @@ -1160,6 +1395,11 @@ /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Reset TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; @@ -1194,18 +1434,47 @@ /* Set TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT; + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + + /* Load the Timeout value in the compare register */ + __HAL_LPTIM_COMPARE_SET(hlptim, Timeout); + + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Enable Compare match interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Load the Timeout value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Timeout); - /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); @@ -1232,6 +1501,11 @@ /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Reset TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; @@ -1273,9 +1547,18 @@ /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); @@ -1302,6 +1585,11 @@ /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Change the TIM state*/ hlptim->State = HAL_LPTIM_STATE_READY; @@ -1334,6 +1622,29 @@ hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC; } + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Enable Autoreload write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); @@ -1343,9 +1654,6 @@ /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); @@ -1372,12 +1680,16 @@ /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Disable Autoreload write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); /* Disable Autoreload match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); - /* Change the TIM state*/ hlptim->State = HAL_LPTIM_STATE_READY; @@ -1975,15 +2287,39 @@ #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ /** + * @brief LPTimer Wait for flag set + * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains + * the configuration information for LPTIM module. + * @param flag The lptim flag + * @retval HAL status + */ +static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag) +{ + HAL_StatusTypeDef result = HAL_OK; + uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL); + do + { + count--; + if (count == 0UL) + { + result = HAL_TIMEOUT; + } + } + while((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL)); + + return result; +} + +/** * @brief Disable LPTIM HW instance. - * @param lptim pointer to a LPTIM_HandleTypeDef structure that contains + * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains * the configuration information for LPTIM module. * @note The following sequence is required to solve LPTIM disable HW limitation. * Please check Errata Sheet ES0335 for more details under "MCU may remain * stuck in LPTIM interrupt when entering Stop mode" section. * @retval None */ -void LPTIM_Disable(LPTIM_HandleTypeDef *lptim) +void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) { uint32_t tmpclksource = 0; uint32_t tmpIER; @@ -1996,7 +2332,7 @@ /*********** Save LPTIM Config ***********/ /* Save LPTIM source clock */ - switch ((uint32_t)lptim->Instance) + switch ((uint32_t)hlptim->Instance) { case LPTIM1_BASE: tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE(); @@ -2011,14 +2347,14 @@ } /* Save LPTIM configuration registers */ - tmpIER = lptim->Instance->IER; - tmpCFGR = lptim->Instance->CFGR; - tmpCMP = lptim->Instance->CMP; - tmpARR = lptim->Instance->ARR; - tmpOR = lptim->Instance->OR; + tmpIER = hlptim->Instance->IER; + tmpCFGR = hlptim->Instance->CFGR; + tmpCMP = hlptim->Instance->CMP; + tmpARR = hlptim->Instance->ARR; + tmpOR = hlptim->Instance->OR; /*********** Reset LPTIM ***********/ - switch ((uint32_t)lptim->Instance) + switch ((uint32_t)hlptim->Instance) { case LPTIM1_BASE: __HAL_RCC_LPTIM1_FORCE_RESET(); @@ -2035,13 +2371,10 @@ } /*********** Restore LPTIM Config ***********/ - uint32_t Ref_Time; - uint32_t Time_Elapsed; - if ((tmpCMP != 0UL) || (tmpARR != 0UL)) { /* Force LPTIM source kernel clock from APB */ - switch ((uint32_t)lptim->Instance) + switch ((uint32_t)hlptim->Instance) { case LPTIM1_BASE: __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1); @@ -2058,35 +2391,34 @@ if (tmpCMP != 0UL) { /* Restore CMP register (LPTIM should be enabled first) */ - lptim->Instance->CR |= LPTIM_CR_ENABLE; - lptim->Instance->CMP = tmpCMP; - /* Polling on CMP write ok status after above restore operation */ - Ref_Time = HAL_GetTick(); - do - { - Time_Elapsed = HAL_GetTick() - Ref_Time; - } while ((!(__HAL_LPTIM_GET_FLAG(lptim, LPTIM_FLAG_CMPOK))) && (Time_Elapsed <= TIMEOUT)); + hlptim->Instance->CR |= LPTIM_CR_ENABLE; + hlptim->Instance->CMP = tmpCMP; - __HAL_LPTIM_CLEAR_FLAG(lptim, LPTIM_FLAG_CMPOK); + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + hlptim->State = HAL_LPTIM_STATE_TIMEOUT; + } + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); } if (tmpARR != 0UL) { /* Restore ARR register (LPTIM should be enabled first) */ - lptim->Instance->CR |= LPTIM_CR_ENABLE; - lptim->Instance->ARR = tmpARR; - /* Polling on ARR write ok status after above restore operation */ - Ref_Time = HAL_GetTick(); - do - { - Time_Elapsed = HAL_GetTick() - Ref_Time; - } while ((!(__HAL_LPTIM_GET_FLAG(lptim, LPTIM_FLAG_ARROK))) && (Time_Elapsed <= TIMEOUT)); + hlptim->Instance->CR |= LPTIM_CR_ENABLE; + hlptim->Instance->ARR = tmpARR; - __HAL_LPTIM_CLEAR_FLAG(lptim, LPTIM_FLAG_ARROK); + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + hlptim->State = HAL_LPTIM_STATE_TIMEOUT; + } + + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); } /* Restore LPTIM source kernel clock */ - switch ((uint32_t)lptim->Instance) + switch ((uint32_t)hlptim->Instance) { case LPTIM1_BASE: __HAL_RCC_LPTIM1_CONFIG(tmpclksource); @@ -2102,10 +2434,10 @@ } /* Restore configuration registers (LPTIM should be disabled first) */ - lptim->Instance->CR &= ~(LPTIM_CR_ENABLE); - lptim->Instance->IER = tmpIER; - lptim->Instance->CFGR = tmpCFGR; - lptim->Instance->OR = tmpOR; + hlptim->Instance->CR &= ~(LPTIM_CR_ENABLE); + hlptim->Instance->IER = tmpIER; + hlptim->Instance->CFGR = tmpCFGR; + hlptim->Instance->OR = tmpOR; __enable_irq(); }
diff --git a/Src/stm32wbxx_hal_pcd.c b/Src/stm32wbxx_hal_pcd.c index b3f16ae..1a13883 100644 --- a/Src/stm32wbxx_hal_pcd.c +++ b/Src/stm32wbxx_hal_pcd.c
@@ -1714,7 +1714,10 @@ { /* Get SETUP Packet*/ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, ep->pmaadress, (uint16_t)ep->xfer_count); + + USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, + ep->pmaadress, (uint16_t)ep->xfer_count); + /* SETUP bit kept frozen while CTR_RX = 1*/ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); @@ -1729,21 +1732,24 @@ else if ((wEPVal & USB_EP_CTR_RX) != 0U) { PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + /* Get Control Data OUT Packet*/ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0U) + if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U)) { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, (uint16_t)ep->xfer_count); - ep->xfer_buff += ep->xfer_count; - } + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, + ep->pmaadress, (uint16_t)ep->xfer_count); - /* Process Control Data OUT Packet*/ + ep->xfer_buff += ep->xfer_count; + + /* Process Control Data OUT Packet*/ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataOutStageCallback(hpcd, 0U); + hpcd->DataOutStageCallback(hpcd, 0U); #else - HAL_PCD_DataOutStageCallback(hpcd, 0U); + HAL_PCD_DataOutStageCallback(hpcd, 0U); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
diff --git a/Src/stm32wbxx_hal_pcd_ex.c b/Src/stm32wbxx_hal_pcd_ex.c index 086e6e7..77ba282 100644 --- a/Src/stm32wbxx_hal_pcd_ex.c +++ b/Src/stm32wbxx_hal_pcd_ex.c
@@ -125,6 +125,9 @@ USB_TypeDef *USBx = hpcd->Instance; hpcd->battery_charging_active = 1U; + /* Enable BCD feature */ + USBx->BCDR |= USB_BCDR_BCDEN; + /* Enable DCD : Data Contact Detect */ USBx->BCDR &= ~(USB_BCDR_PDEN); USBx->BCDR &= ~(USB_BCDR_SDEN); @@ -143,6 +146,7 @@ USB_TypeDef *USBx = hpcd->Instance; hpcd->battery_charging_active = 0U; + /* Disable BCD feature */ USBx->BCDR &= ~(USB_BCDR_BCDEN); return HAL_OK;
diff --git a/Src/stm32wbxx_hal_pwr.c b/Src/stm32wbxx_hal_pwr.c index 915ddca..4aec8eb 100644 --- a/Src/stm32wbxx_hal_pwr.c +++ b/Src/stm32wbxx_hal_pwr.c
@@ -114,8 +114,10 @@ LL_PWR_WriteReg(PDCRB, PWR_PDCRB_RESET_VALUE); LL_PWR_WriteReg(PUCRC, PWR_PUCRC_RESET_VALUE); LL_PWR_WriteReg(PDCRC, PWR_PDCRC_RESET_VALUE); +#if defined(GPIOD) LL_PWR_WriteReg(PUCRD, PWR_PUCRD_RESET_VALUE); LL_PWR_WriteReg(PDCRD, PWR_PDCRD_RESET_VALUE); +#endif LL_PWR_WriteReg(PUCRE, PWR_PUCRE_RESET_VALUE); LL_PWR_WriteReg(PDCRE, PWR_PDCRE_RESET_VALUE); LL_PWR_WriteReg(PUCRH, PWR_PUCRH_RESET_VALUE); @@ -131,8 +133,10 @@ | LL_PWR_SCR_CCRPEF | LL_PWR_SCR_C802WUF | LL_PWR_SCR_CBLEWUF +#if defined(PWR_CR5_SMPSEN) | LL_PWR_SCR_CBORHF | LL_PWR_SCR_CSMPSFBF +#endif | LL_PWR_SCR_CWUF );
diff --git a/Src/stm32wbxx_hal_pwr_ex.c b/Src/stm32wbxx_hal_pwr_ex.c index bb62eda..93554f6 100644 --- a/Src/stm32wbxx_hal_pwr_ex.c +++ b/Src/stm32wbxx_hal_pwr_ex.c
@@ -79,6 +79,7 @@ */ +#if defined(PWR_CR1_VOS) /** * @brief Return Voltage Scaling Range. * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2) @@ -145,7 +146,8 @@ } return HAL_OK; -} +} +#endif /****************************************************************************/ @@ -179,7 +181,7 @@ } /****************************************************************************/ - +#if defined(PWR_CR2_PVME1) /** * @brief Enable VDDUSB supply. * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present. @@ -198,6 +200,7 @@ { CLEAR_BIT(PWR->CR2, PWR_CR2_USV); } +#endif /****************************************************************************/ @@ -219,7 +222,7 @@ CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL); } - +#if defined(PWR_CR5_SMPSEN) /** * @brief Enable BORH and SMPS step down converter forced in bypass mode * interrupt for CPU1 @@ -239,7 +242,7 @@ { CLEAR_BIT(PWR->CR3, PWR_CR3_EBORHSMPSFB); } - +#endif /** * @brief Enable RF Phase interrupt. @@ -358,11 +361,13 @@ case PWR_GPIO_C: SET_BIT(PWR->PUCRC, GPIONumber); CLEAR_BIT(PWR->PDCRC, GPIONumber); - break; + break; +#if defined(GPIOD) case PWR_GPIO_D: SET_BIT(PWR->PUCRD, GPIONumber); CLEAR_BIT(PWR->PDCRD, GPIONumber); break; +#endif case PWR_GPIO_E: SET_BIT(PWR->PUCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS)); CLEAR_BIT(PWR->PDCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS)); @@ -411,10 +416,12 @@ break; case PWR_GPIO_C: CLEAR_BIT(PWR->PUCRC, GPIONumber); - break; + break; +#if defined(GPIOD) case PWR_GPIO_D: CLEAR_BIT(PWR->PUCRD, GPIONumber); break; +#endif case PWR_GPIO_E: CLEAR_BIT(PWR->PUCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS)); break; @@ -472,11 +479,13 @@ case PWR_GPIO_C: SET_BIT(PWR->PDCRC, GPIONumber); CLEAR_BIT(PWR->PUCRC, GPIONumber); - break; + break; +#if defined(GPIOD) case PWR_GPIO_D: SET_BIT(PWR->PDCRD, GPIONumber); CLEAR_BIT(PWR->PUCRD, GPIONumber); break; +#endif case PWR_GPIO_E: SET_BIT(PWR->PDCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS)); CLEAR_BIT(PWR->PUCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS)); @@ -526,9 +535,11 @@ case PWR_GPIO_C: CLEAR_BIT(PWR->PDCRC, GPIONumber); break; +#if defined(GPIOD) case PWR_GPIO_D: CLEAR_BIT(PWR->PDCRD, GPIONumber); break; +#endif case PWR_GPIO_E: CLEAR_BIT(PWR->PDCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS)); break; @@ -571,6 +582,7 @@ /****************************************************************************/ +#if defined(PWR_CR5_SMPSEN) /** * @brief Set BOR configuration * @param BORConfiguration This parameter can be one of the following values: @@ -592,6 +604,7 @@ { return LL_PWR_GetBORConfig(); } +#endif /****************************************************************************/ /** @@ -690,6 +703,7 @@ } /****************************************************************************/ +#if defined(PWR_CR2_PVME1) /** * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V. * @retval None @@ -707,6 +721,8 @@ { CLEAR_BIT(PWR->CR2, PWR_PVM_1); } +#endif + /** * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62V. * @retval None @@ -753,6 +769,7 @@ configure the corresponding EXTI line accordingly. */ switch (sConfigPVM->PVMType) { +#if defined(PWR_CR2_PVME1) case PWR_PVM_1: /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVM1_EXTI_DISABLE_EVENT(); @@ -782,7 +799,8 @@ { __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); } - break; + break; +#endif case PWR_PVM_3: /* Clear any previous config. Keep it clear if no event or IT mode is selected */ @@ -824,6 +842,7 @@ return status; } +#if defined(PWR_CR5_SMPSEN) /** * @brief Configure the SMPS step down converter. * @note SMPS output voltage is calibrated in production, @@ -867,13 +886,13 @@ OutputVoltageLevelTrimmed = 0; status = HAL_ERROR; } - else if(OutputVoltageLevelTrimmed > (int32_t)PWR_CR5_SMPSVOS) - { - OutputVoltageLevelTrimmed = (int32_t)PWR_CR5_SMPSVOS; - status = HAL_ERROR; - } else { + if(OutputVoltageLevelTrimmed > (int32_t)PWR_CR5_SMPSVOS) + { + OutputVoltageLevelTrimmed = (int32_t)PWR_CR5_SMPSVOS; + status = HAL_ERROR; + } } /* Update register */ @@ -923,6 +942,7 @@ { return (uint32_t)(READ_BIT(PWR->SR2, (PWR_SR2_SMPSF | PWR_SR2_SMPSBF))); } +#endif /****************************************************************************/ @@ -1270,7 +1290,7 @@ __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); } - +#if defined(PWR_CR2_PVME1) /* Next, successively check PVMx exti flags */ if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != 0U) { @@ -1280,6 +1300,7 @@ /* Clear PVM1 exti pending bit */ __HAL_PWR_PVM1_EXTI_CLEAR_FLAG(); } +#endif if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != 0U) { @@ -1291,7 +1312,7 @@ } } - +#if defined(PWR_CR2_PVME1) /** * @brief PWR PVM1 interrupt callback * @retval None @@ -1302,6 +1323,7 @@ HAL_PWREx_PVM1Callback() API can be implemented in the user file */ } +#endif /** * @brief PWR PVM3 interrupt callback
diff --git a/Src/stm32wbxx_hal_qspi.c b/Src/stm32wbxx_hal_qspi.c index d5108c3..ca9c65b 100644 --- a/Src/stm32wbxx_hal_qspi.c +++ b/Src/stm32wbxx_hal_qspi.c
@@ -208,7 +208,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32wbxx_hal.h" -#if defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) +#if defined(QUADSPI) /** @addtogroup STM32WBxx_HAL_Driver * @{ @@ -340,7 +340,7 @@ #endif /* Configure the default timeout for the QSPI memory access */ - HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE); + HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE); } /* Configure QSPI FIFO Threshold */
diff --git a/Src/stm32wbxx_hal_rcc.c b/Src/stm32wbxx_hal_rcc.c index 68e68e8..c6f2c02 100644 --- a/Src/stm32wbxx_hal_rcc.c +++ b/Src/stm32wbxx_hal_rcc.c
@@ -10,6 +10,7 @@ * @verbatim ============================================================================== + ##### RCC specific features ##### ============================================================================== [..] @@ -18,8 +19,8 @@ and I-Cache are disabled, and all peripherals are off except internal SRAM, Flash and JTAG. - (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) busses: - all peripherals mapped on these busses are running at MSI speed. + (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) buses: + all peripherals mapped on these buses are running at MSI speed. (+) The clock for all peripherals is switched off, except the SRAM and FLASH. (+) All GPIOs are in analog mode, except the JTAG pins which are assigned to be used for debug purpose. @@ -29,7 +30,7 @@ (+) Configure the clock source to be used to drive the System clock (if the application needs higher frequency/performance) (+) Configure the System clock frequency and Flash settings - (+) Configure the AHB and APB busses prescalers + (+) Configure the AHB and APB buses prescalers (+) Enable the clock for the peripheral(s) to be used (+) Configure the clock source(s) for peripherals which clocks are not derived from the System clock (SAI1, RTC, ADC, USB/RNG, USART1, LPUART1, LPTIMx, I2Cx, SMPS) @@ -38,11 +39,11 @@ ****************************************************************************** * @attention * - * <h2><center>© Copyright (c) 2019 STMicroelectronics. + * <h2><center>© Copyright (c) 2019 STMicroelectronics. * All rights reserved.</center></h2> * * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -145,7 +146,7 @@ =============================================================================== [..] This section provides functions allowing to configure the internal and external oscillators - (HSE, HSI, LSE, MSI, LSI1, LSI2, PLL, CSS and MCO) and the System busses clocks (SYSCLK, HCLK1, HCLK2, HCLK4, PCLK1 + (HSE, HSI, LSE, MSI, LSI1, LSI2, PLL, CSS and MCO) and the System buses clocks (SYSCLK, HCLK1, HCLK2, HCLK4, PCLK1 and PCLK2). [..] Internal/external clock and PLL configuration @@ -196,14 +197,14 @@ (+) MCO (microcontroller clock output): used to output MSI, LSI1, LSI2, HSI, LSE, HSE (before and after stabilization), SYSCLK, HSI48 or main PLL clock (through a configurable prescaler) on PA8, PB6 & PA15 pins. - [..] System, AHB and APB busses clocks configuration + [..] System, AHB and APB buses clocks configuration (+) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI, HSE and main PLL. The AHB clock (HCLK1) is derived from System clock through configurable prescaler and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through configurable prescalers and used to clock - the peripherals mapped on these busses. You can use + the peripherals mapped on these buses. You can use "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. The AHB4 clock (HCLK4) is derived from System clock through configurable prescaler and used to clock the FLASH @@ -308,13 +309,17 @@ } /* Reset HSION, HSIKERON, HSIASFS, HSEON, PLLON, PLLSAI11ON, HSEPRE bits */ +#if defined(SAI1) CLEAR_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSIASFS | RCC_CR_HSEON | RCC_CR_HSEPRE | RCC_CR_PLLON | RCC_CR_PLLSAI1ON); +#else + CLEAR_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSIASFS | RCC_CR_HSEON | RCC_CR_HSEPRE | RCC_CR_PLLON); +#endif /* Reset HSEBYP bit once HSE is OFF */ LL_RCC_HSE_DisableBypass(); /* Get Start Tick*/ - tickstart = HAL_GetTick(); + tickstart = HAL_GetTick(); /* Wait till PLL is ready */ while (LL_RCC_PLL_IsReady() != 0U) @@ -328,7 +333,7 @@ /* once PLL is OFF, reset PLLCFGR register to default value */ WRITE_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLQ_0 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLN_0); - +#if defined(SAI1) /* Get Start Tick*/ tickstart = HAL_GetTick(); @@ -342,6 +347,7 @@ } /* once PLLSAI1 is OFF, reset PLLSAI1CFGR register to default value */ WRITE_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLR_0 | RCC_PLLSAI1CFGR_PLLQ_0 | RCC_PLLSAI1CFGR_PLLP_1 | RCC_PLLSAI1CFGR_PLLN_0); +#endif /* Disable all interrupts */ CLEAR_REG(RCC->CIER); @@ -356,7 +362,7 @@ SystemCoreClock = MSI_VALUE; /* Adapt Systick interrupt period */ - if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + if (HAL_InitTick(uwTickPrio) != HAL_OK) { return HAL_ERROR; } @@ -379,7 +385,7 @@ uint32_t tickstart; /* Check Null pointer */ - if(RCC_OscInitStruct == NULL) + if (RCC_OscInitStruct == NULL) { return HAL_ERROR; } @@ -440,8 +446,8 @@ } /* Update the SystemCoreClock global variable */ - SystemCoreClockUpdate(); - if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + SystemCoreClockUpdate(); + if (HAL_InitTick(uwTickPrio) != HAL_OK) { return HAL_ERROR; } @@ -480,7 +486,7 @@ /* Get timeout */ tickstart = HAL_GetTick(); - /* Wait till MSI is ready */ + /* Wait till MSI is disabled */ while (LL_RCC_MSI_IsReady() != 0U) { if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) @@ -630,16 +636,16 @@ /* 1. Check LSI1 state and enable if required */ if (LL_RCC_LSI1_IsReady() == 0U) { - /* This is required to enable LSI1 before enabling LSI2 */ + /* This is required to enable LSI1 before enabling LSI2 */ __HAL_RCC_LSI1_ENABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till LSI1 is ready */ - while(LL_RCC_LSI1_IsReady() == 0U) + while (LL_RCC_LSI1_IsReady() == 0U) { - if((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -918,8 +924,11 @@ /* Disable all PLL outputs to save power */ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSOURCE_NONE); +#if defined(SAI1) && defined(USB) __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_USBCLK | RCC_PLL_SAI1CLK); - +#else + __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK); +#endif /* Get Start Tick*/ tickstart = HAL_GetTick(); @@ -936,18 +945,26 @@ } else { - /* Do not return HAL_ERROR if request repeats the current configuration */ - uint32_t pllcfgr = RCC->PLLCFGR; - - if((READ_BIT(pllcfgr, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - (READ_BIT(pllcfgr, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || - ((READ_BIT(pllcfgr, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) != RCC_OscInitStruct->PLL.PLLN) || - (READ_BIT(pllcfgr, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || - (READ_BIT(pllcfgr, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) || - (READ_BIT(pllcfgr, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR)) + /* Check if there is a request to disable the PLL used as System clock source */ + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) { return HAL_ERROR; } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + uint32_t pllcfgr = RCC->PLLCFGR; + + if ((READ_BIT(pllcfgr, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(pllcfgr, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + ((READ_BIT(pllcfgr, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) != RCC_OscInitStruct->PLL.PLLN) || + (READ_BIT(pllcfgr, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || + (READ_BIT(pllcfgr, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) || + (READ_BIT(pllcfgr, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR)) + { + return HAL_ERROR; + } + } } } return HAL_OK; @@ -955,7 +972,7 @@ /** - * @brief Initialize the CPU, AHB and APB busses clocks according to the specified + * @brief Initialize the CPU, AHB and APB buses clocks according to the specified * parameters in the RCC_ClkInitStruct. * @param RCC_ClkInitStruct pointer to a @ref RCC_ClkInitTypeDef structure that * contains the configuration information for the RCC peripheral. @@ -995,7 +1012,7 @@ uint32_t tickstart; /* Check Null pointer */ - if(RCC_ClkInitStruct == NULL) + if (RCC_ClkInitStruct == NULL) { return HAL_ERROR; } @@ -1196,7 +1213,7 @@ /* Update the SystemCoreClock global variable */ SystemCoreClockUpdate(); /* Configure the source of time base considering new system clocks settings*/ - return HAL_InitTick (HAL_GetTickPrio()); + return HAL_InitTick(HAL_GetTickPrio()); } /** @@ -1265,7 +1282,7 @@ GPIO_InitStruct.Pull = GPIO_NOPULL; /* RCC_MCO1 */ - if(RCC_MCOx == RCC_MCO1) + if (RCC_MCOx == RCC_MCO1) { /* MCO1 Clock Enable */ __MCO1_CLK_ENABLE(); @@ -1295,8 +1312,8 @@ HAL_GPIO_Init(MCO3_GPIO_PORT, &GPIO_InitStruct); } - /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */ - LL_RCC_ConfigMCO(RCC_MCOSource, RCC_MCODiv); + /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */ + LL_RCC_ConfigMCO(RCC_MCOSource, RCC_MCODiv); } /** @@ -1335,7 +1352,7 @@ uint32_t pllsource; uint32_t sysclockfreq, pllinputfreq; const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); - + if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_MSI) { /* Retrieve MSI frequency range in HZ*/ @@ -1351,13 +1368,13 @@ { /* HSE used as system clock source */ if (LL_RCC_HSE_IsEnabledDiv2() == 1U) - { - sysclockfreq = HSE_VALUE / 2U; - } - else - { - sysclockfreq = HSE_VALUE; - } + { + sysclockfreq = HSE_VALUE / 2U; + } + else + { + sysclockfreq = HSE_VALUE; + } } else { @@ -1369,14 +1386,14 @@ pllinputfreq = HSI_VALUE; break; case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - if (LL_RCC_HSE_IsEnabledDiv2() == 1U) - { - pllinputfreq = HSE_VALUE / 2U; - } - else - { - pllinputfreq = HSE_VALUE; - } + if (LL_RCC_HSE_IsEnabledDiv2() == 1U) + { + pllinputfreq = HSE_VALUE / 2U; + } + else + { + pllinputfreq = HSE_VALUE; + } break; case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ default: @@ -1662,9 +1679,9 @@ /* Check the parameters */ assert_param(IS_RCC_MSI_CLOCK_RANGE(MSI_Range)); - + /* MSI frequency range in Hz */ - if(MSI_Range > RCC_MSIRANGE_11) + if (MSI_Range > RCC_MSIRANGE_11) { msifreq = __LL_RCC_CALC_MSI_FREQ(RCC_MSIRANGE_11); } @@ -1672,10 +1689,14 @@ { msifreq = __LL_RCC_CALC_MSI_FREQ(MSI_Range); } - + flash_clksrcfreq = __LL_RCC_CALC_HCLK4_FREQ(msifreq, LL_RCC_GetAHB4Prescaler()); +#if defined(PWR_CR1_VOS) return RCC_SetFlashLatency((flash_clksrcfreq / MEGA_HZ), HAL_PWREx_GetVoltageRange()); +#else + return RCC_SetFlashLatency((flash_clksrcfreq / MEGA_HZ), PWR_REGULATOR_VOLTAGE_SCALE1); +#endif } @@ -1689,13 +1710,16 @@ { /* Flash Clock source (HCLK4) range in MHz with a VCORE is range1 */ const uint32_t FLASH_CLK_SRC_RANGE_VOS1[] = {18UL, 36UL, 54UL, 64UL}; +#if defined(PWR_CR1_VOS) /* Flash Clock source (HCLK4) range in MHz with a VCORE is range2 */ const uint32_t FLASH_CLK_SRC_RANGE_VOS2[] = {6UL, 12UL, 16UL}; +#endif /* Flash Latency range */ const uint32_t FLASH_LATENCY_RANGE[] = {FLASH_LATENCY_0, FLASH_LATENCY_1, FLASH_LATENCY_2, FLASH_LATENCY_3}; uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ uint32_t tickstart; +#if defined(PWR_CR1_VOS) if (VCORE_Voltage == PWR_REGULATOR_VOLTAGE_SCALE1) { for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++) @@ -1718,6 +1742,16 @@ } } } +#else + for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++) + { + if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS1[index]) + { + latency = FLASH_LATENCY_RANGE[index]; + break; + } + } +#endif __HAL_FLASH_SET_LATENCY(latency);
diff --git a/Src/stm32wbxx_hal_rcc_ex.c b/Src/stm32wbxx_hal_rcc_ex.c index 193611d..968e90f 100644 --- a/Src/stm32wbxx_hal_rcc_ex.c +++ b/Src/stm32wbxx_hal_rcc_ex.c
@@ -12,11 +12,11 @@ ****************************************************************************** * @attention * - * <h2><center>© Copyright (c) 2019 STMicroelectronics. + * <h2><center>© Copyright (c) 2019 STMicroelectronics. * All rights reserved.</center></h2> * * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -71,17 +71,20 @@ /** @defgroup RCCEx_Private_Functions RCCEx Private Functions * @{ */ +#if defined(SAI1) static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNP(RCC_PLLSAI1InitTypeDef *PLLSAI1); static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNQ(RCC_PLLSAI1InitTypeDef *PLLSAI1); static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNR(RCC_PLLSAI1InitTypeDef *PLLSAI1); +#endif static uint32_t RCC_PLL_GetFreqDomain_P(void); static uint32_t RCC_PLL_GetFreqDomain_Q(void); +#if defined(SAI1) static uint32_t RCC_PLLSAI1_GetFreqDomain_R(void); static uint32_t RCC_PLLSAI1_GetFreqDomain_P(void); static uint32_t RCC_PLLSAI1_GetFreqDomain_Q(void); - +#endif /** * @} @@ -151,6 +154,7 @@ /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); +#if defined(SAI1) /*-------------------------- SAI1 clock source configuration ---------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)) { @@ -197,23 +201,24 @@ status = ret; } } +#endif /*-------------------------- RTC clock source configuration ----------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) { uint32_t rtcclocksource = LL_RCC_GetRTCClockSource(); - + /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Configure the clock source only if a different source is expected */ - if(rtcclocksource != PeriphClkInit->RTCClockSelection) + if (rtcclocksource != PeriphClkInit->RTCClockSelection) { /* Enable write access to Backup domain */ HAL_PWR_EnableBkUpAccess(); - + /* If a clock source is not yet selected */ - if(rtcclocksource == RCC_RTCCLKSOURCE_NONE) + if (rtcclocksource == RCC_RTCCLKSOURCE_NONE) { /* Directly set the configuration of the clock source selection */ LL_RCC_SetRTCClockSource(PeriphClkInit->RTCClockSelection); @@ -222,23 +227,23 @@ { /* Store the content of BDCR register before the reset of Backup Domain */ uint32_t bdcr = LL_RCC_ReadReg(BDCR); - + /* RTC Clock selection can be changed only if the Backup Domain is reset */ LL_RCC_ForceBackupDomainReset(); LL_RCC_ReleaseBackupDomainReset(); - + /* Set the value of the clock source selection */ MODIFY_REG(bdcr, RCC_BDCR_RTCSEL, PeriphClkInit->RTCClockSelection); - + /* Restore the content of BDCR register */ LL_RCC_WriteReg(BDCR, bdcr); - + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (LL_RCC_LSE_IsEnabled() == 1U) { /* Get Start Tick*/ tickstart = HAL_GetTick(); - + /* Wait till LSE is ready */ while (LL_RCC_LSE_IsReady() != 1U) { @@ -272,7 +277,7 @@ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); } - +#if defined(LPUART1) /*-------------------------- LPUART1 clock source configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) { @@ -282,6 +287,7 @@ /* Configure the LPUAR1 clock source */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); } +#endif /*-------------------------- LPTIM1 clock source configuration -------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) @@ -307,6 +313,7 @@ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); } +#if defined(I2C3) /*-------------------------- I2C3 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) { @@ -316,9 +323,9 @@ /* Configure the I2C3 clock source */ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); } +#endif /*-------------------------- USB clock source configuration ----------------------*/ - if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB)) { assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); @@ -329,7 +336,8 @@ /* Enable PLLQ output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_USBCLK); } - + +#if defined(SAI1) if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1) { /* PLLSAI1 parameters N & Q configuration and clock output (PLLSAI1ClockOut) */ @@ -341,14 +349,23 @@ status = ret; } } +#endif } /*-------------------------- RNG clock source configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) { + /* Check the parameters */ assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); + + /* Configure the RNG clock source */ __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); + if (PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) + { + /* Enable PLLQ output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_RNGCLK); + } } /*-------------------------- ADC clock source configuration ----------------------*/ @@ -365,7 +382,8 @@ /* Enable RCC_PLL_RNGCLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK); } - + +#if defined(SAI1) if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1) { /* PLLSAI1 parameters N & R configuration and clock output (PLLSAI1ClockOut) */ @@ -377,6 +395,7 @@ status = ret; } } +#endif } /*-------------------------- RFWKP clock source configuration ----------------------*/ @@ -390,6 +409,7 @@ } +#if defined(RCC_SMPS_SUPPORT) /*-------------------------- SMPS clock source configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SMPS) == RCC_PERIPHCLK_SMPS) { @@ -402,8 +422,8 @@ /* Configure the SMPS interface clock source */ __HAL_RCC_SMPS_CONFIG(PeriphClkInit->SmpsClockSelection); - } +#endif return status; } @@ -420,28 +440,52 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { /* Set all possible values for the extended clock type parameter------------*/ - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C3 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_USB | \ - RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RFWAKEUP | \ - RCC_PERIPHCLK_SMPS; + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ + RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RFWAKEUP; +#if defined(LPUART1) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPUART1; +#endif + +#if defined(I2C3) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C3; +#endif + +#if defined(SAI1) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI1; +#endif + + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; + +#if defined(RCC_SMPS_SUPPORT) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SMPS; +#endif + +#if defined(SAI1) /* Get the PLLSAI1 Clock configuration -----------------------------------------------*/ PeriphClkInit->PLLSAI1.PLLN = LL_RCC_PLLSAI1_GetN(); PeriphClkInit->PLLSAI1.PLLP = LL_RCC_PLLSAI1_GetP(); PeriphClkInit->PLLSAI1.PLLR = LL_RCC_PLLSAI1_GetR(); PeriphClkInit->PLLSAI1.PLLQ = LL_RCC_PLLSAI1_GetQ(); +#endif /* Get the USART1 clock source ---------------------------------------------*/ PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); +#if defined(LPUART1) /* Get the LPUART1 clock source --------------------------------------------*/ PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); +#endif /* Get the I2C1 clock source -----------------------------------------------*/ PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); +#if defined(I2C3) /* Get the I2C3 clock source -----------------------------------------------*/ PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); +#endif /* Get the LPTIM1 clock source ---------------------------------------------*/ PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); @@ -449,8 +493,10 @@ /* Get the LPTIM2 clock source ---------------------------------------------*/ PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE(); +#if defined(SAI1) /* Get the SAI1 clock source -----------------------------------------------*/ PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); +#endif /* Get the RTC clock source ------------------------------------------------*/ PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); @@ -459,7 +505,7 @@ PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); /* Get the RNG clock source ------------------------------------------------*/ - PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE(); + PeriphClkInit->RngClockSelection = HAL_RCCEx_GetRngCLKSource(); /* Get the ADC clock source ------------------------------------------------*/ PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); @@ -467,11 +513,13 @@ /* Get the RFWKP clock source ----------------------------------------------*/ PeriphClkInit->RFWakeUpClockSelection = __HAL_RCC_GET_RFWAKEUP_SOURCE(); +#if defined(RCC_SMPS_SUPPORT) /* Get the SMPS clock division factor --------------------------------------*/ PeriphClkInit->SmpsDivSelection = __HAL_RCC_GET_SMPS_DIV(); /* Get the SMPS clock source -----------------------------------------------*/ PeriphClkInit->SmpsClockSelection = __HAL_RCC_GET_SMPS_SOURCE(); +#endif } /** @@ -498,16 +546,19 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { uint32_t frequency; + +#if defined(RCC_SMPS_SUPPORT) uint32_t smps_prescaler_index = ((LL_RCC_GetSMPSPrescaler()) >> RCC_SMPSCR_SMPSDIV_Pos); +#endif /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); - if(PeriphClk == RCC_PERIPHCLK_RTC) + if (PeriphClk == RCC_PERIPHCLK_RTC) { uint32_t rtcClockSource = LL_RCC_GetRTCClockSource(); - - if(rtcClockSource == LL_RCC_RTC_CLKSOURCE_LSE) /* LSE clock used as RTC clock source */ + + if (rtcClockSource == LL_RCC_RTC_CLKSOURCE_LSE) /* LSE clock used as RTC clock source */ { if (LL_RCC_LSE_IsReady() == 1U) { @@ -518,7 +569,7 @@ frequency = 0U; } } - else if(rtcClockSource == LL_RCC_RTC_CLKSOURCE_LSI) /* LSI clock used as RTC clock source */ + else if (rtcClockSource == LL_RCC_RTC_CLKSOURCE_LSI) /* LSI clock used as RTC clock source */ { const uint32_t temp_lsi1ready = LL_RCC_LSI1_IsReady(); const uint32_t temp_lsi2ready = LL_RCC_LSI2_IsReady(); @@ -540,6 +591,7 @@ frequency = 0; } } +#if defined(SAI1) else if (PeriphClk == RCC_PERIPHCLK_SAI1) { switch (LL_RCC_GetSAIClockSource(LL_RCC_SAI1_CLKSOURCE)) @@ -565,7 +617,7 @@ frequency = 0U; } break; - + case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */ if (LL_RCC_PLL_IsReady() == 1U) { @@ -582,11 +634,12 @@ break; } } - else if(PeriphClk == RCC_PERIPHCLK_RNG) +#endif + else if (PeriphClk == RCC_PERIPHCLK_RNG) { - uint32_t rngClockSource = LL_RCC_GetRNGClockSource(LL_RCC_RNG_CLKSOURCE); - - if(rngClockSource == LL_RCC_RNG_CLKSOURCE_LSI) /* LSI clock used as RNG clock source */ + uint32_t rngClockSource = HAL_RCCEx_GetRngCLKSource(); + + if (rngClockSource == RCC_RNGCLKSOURCE_LSI) /* LSI clock used as RNG clock source */ { const uint32_t temp_lsi1ready = LL_RCC_LSI1_IsReady(); const uint32_t temp_lsi2ready = LL_RCC_LSI2_IsReady(); @@ -599,7 +652,7 @@ frequency = 0U; } } - else if(rngClockSource == LL_RCC_RNG_CLKSOURCE_LSE) /* LSE clock used as RNG clock source */ + else if (rngClockSource == RCC_RNGCLKSOURCE_LSE) /* LSE clock used as RNG clock source */ { if (LL_RCC_LSE_IsReady() == 1U) { @@ -610,61 +663,45 @@ frequency = 0U; } } - else /* CLK48 clock used as RNG clock source */ + else if (rngClockSource == RCC_RNGCLKSOURCE_PLL) /* PLL clock divided by 3 used as RNG clock source */ { - switch (LL_RCC_GetUSBClockSource(LL_RCC_USB_CLKSOURCE)) + if (LL_RCC_PLL_IsReady() == 1U) { - case LL_RCC_USB_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as USB clock source */ - if (LL_RCC_PLLSAI1_IsReady() == 1U) - { - frequency = RCC_PLLSAI1_GetFreqDomain_Q(); - } - else - { - frequency = 0U; - } - break; - - case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ - if (LL_RCC_PLL_IsReady() == 1U) - { - frequency = RCC_PLL_GetFreqDomain_Q(); - } - else - { - frequency = 0U; - } - break; - - case LL_RCC_USB_CLKSOURCE_MSI: /* MSI clock used as USB clock source */ - if (LL_RCC_MSI_IsReady() == 1U) - { - frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()); - } - else - { - frequency = 0U; - } - break; - - default: /* HSI48 clock used as USB clock source */ - if (LL_RCC_HSI48_IsReady() == 1U) - { - frequency = HSI48_VALUE; - } - else - { - frequency = 0U; - } - break; + frequency = (RCC_PLL_GetFreqDomain_Q() / 3U); } - frequency = frequency / 3U; + else + { + frequency = 0U; + } + } + else if (rngClockSource == RCC_RNGCLKSOURCE_MSI) /* MSI clock divided by 3 used as RNG clock source */ + { + if (LL_RCC_MSI_IsReady() == 1U) + { + frequency = (__LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()) / 3U); + } + else + { + frequency = 0U; + } + } + else /* HSI48 clock divided by 3 used as RNG clock source */ + { + if (LL_RCC_HSI48_IsReady() == 1U) + { + frequency = HSI48_VALUE / 3U; + } + else + { + frequency = 0U; + } } } else if (PeriphClk == RCC_PERIPHCLK_USB) { switch (LL_RCC_GetUSBClockSource(LL_RCC_USB_CLKSOURCE)) { +#if defined(SAI1) case LL_RCC_USB_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as USB clock source */ if (LL_RCC_PLLSAI1_IsReady() == 1U) { @@ -675,7 +712,7 @@ frequency = 0U; } break; - +#endif case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ if (LL_RCC_PLL_IsReady() == 1U) { @@ -697,7 +734,7 @@ frequency = 0U; } break; - + default: /* HSI48 clock used as USB clock source */ if (LL_RCC_HSI48_IsReady() == 1U) { @@ -710,6 +747,7 @@ break; } } + else if (PeriphClk == RCC_PERIPHCLK_USART1) { switch (LL_RCC_GetUSARTClockSource(LL_RCC_USART1_CLKSOURCE)) @@ -746,6 +784,7 @@ break; } } +#if defined(LPUART1) else if (PeriphClk == RCC_PERIPHCLK_LPUART1) { switch (LL_RCC_GetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE)) @@ -782,10 +821,12 @@ break; } } +#endif else if (PeriphClk == RCC_PERIPHCLK_ADC) { switch (LL_RCC_GetADCClockSource(LL_RCC_ADC_CLKSOURCE)) { +#if defined(SAI1) case LL_RCC_ADC_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as ADC clock source */ if (LL_RCC_PLLSAI1_IsReady() == 1U) { @@ -796,7 +837,7 @@ frequency = 0U; } break; - +#endif case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */ frequency = HAL_RCC_GetSysClockFreq(); break; @@ -811,7 +852,7 @@ frequency = 0U; } break; - + default: /* No clock used as ADC clock source */ frequency = 0; break; @@ -842,6 +883,7 @@ break; } } +#if defined(I2C3) else if (PeriphClk == RCC_PERIPHCLK_I2C3) { switch (LL_RCC_GetI2CClockSource(LL_RCC_I2C3_CLKSOURCE)) @@ -867,11 +909,12 @@ break; } } +#endif else if (PeriphClk == RCC_PERIPHCLK_LPTIM1) { uint32_t lptimClockSource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE); - - if(lptimClockSource == LL_RCC_LPTIM1_CLKSOURCE_LSI) /* LPTIM1 Clock is LSI Osc. */ + + if (lptimClockSource == LL_RCC_LPTIM1_CLKSOURCE_LSI) /* LPTIM1 Clock is LSI Osc. */ { const uint32_t temp_lsi1ready = LL_RCC_LSI1_IsReady(); const uint32_t temp_lsi2ready = LL_RCC_LSI2_IsReady(); @@ -884,7 +927,7 @@ frequency = 0U; } } - else if( lptimClockSource == LL_RCC_LPTIM1_CLKSOURCE_HSI) /* LPTIM1 Clock is HSI Osc. */ + else if (lptimClockSource == LL_RCC_LPTIM1_CLKSOURCE_HSI) /* LPTIM1 Clock is HSI Osc. */ { if (LL_RCC_HSI_IsReady() == 1U) { @@ -895,7 +938,7 @@ frequency = 0U; } } - else if(lptimClockSource == LL_RCC_LPTIM1_CLKSOURCE_LSE) /* LPTIM1 Clock is LSE Osc. */ + else if (lptimClockSource == LL_RCC_LPTIM1_CLKSOURCE_LSE) /* LPTIM1 Clock is LSE Osc. */ { if (LL_RCC_LSE_IsReady() == 1U) { @@ -914,8 +957,8 @@ else if (PeriphClk == RCC_PERIPHCLK_LPTIM2) { uint32_t lptimClockSource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE); - - if( lptimClockSource == LL_RCC_LPTIM2_CLKSOURCE_LSI) /* LPTIM2 Clock is LSI Osc. */ + + if (lptimClockSource == LL_RCC_LPTIM2_CLKSOURCE_LSI) /* LPTIM2 Clock is LSI Osc. */ { const uint32_t temp_lsi1ready = LL_RCC_LSI1_IsReady(); const uint32_t temp_lsi2ready = LL_RCC_LSI2_IsReady(); @@ -958,7 +1001,7 @@ else if (PeriphClk == RCC_PERIPHCLK_RFWAKEUP) { uint32_t rfwkpClockSource = LL_RCC_GetRFWKPClockSource(); - + if (rfwkpClockSource == LL_RCC_RFWKP_CLKSOURCE_LSE) /* LSE clock used as RF Wakeup clock source */ { if (LL_RCC_LSE_IsReady() == 1U) @@ -992,11 +1035,12 @@ frequency = 0; } } +#if defined(RCC_SMPS_SUPPORT) else if (PeriphClk == RCC_PERIPHCLK_SMPS) { uint32_t smpsClockSource = LL_RCC_GetSMPSClockSource(); - - if(smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_HSI) /* SMPS Clock source is HSI Osc. */ + + if (smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_HSI) /* SMPS Clock source is HSI Osc. */ { if (LL_RCC_HSI_IsReady() == 1U) { @@ -1008,7 +1052,7 @@ frequency = 0U; } } - else if(smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_HSE) /* SMPS Clock source is HSE Osc. */ + else if (smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_HSE) /* SMPS Clock source is HSE Osc. */ { if (LL_RCC_HSE_IsReady() == 1U) { @@ -1020,7 +1064,7 @@ frequency = 0U; } } - else if(smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_MSI) /* SMPS Clock source is MSI Osc. */ + else if (smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_MSI) /* SMPS Clock source is MSI Osc. */ { switch (LL_RCC_MSI_GetRange()) { @@ -1047,6 +1091,7 @@ frequency = 0U; } } +#endif else { frequency = 0U; @@ -1055,6 +1100,30 @@ } /** + * @brief Return the RNG clock source + * @retval The RNG clock source can be one of the following values: + * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 clock divided by 3 selected as RNG clock + * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock divided by 3 selected as RNG clock + * @arg @ref RCC_RNGCLKSOURCE_MSI MSI clock divided by 3 selected as RNG clock + * @arg @ref RCC_RNGCLKSOURCE_LSI LSI clock selected as RNG clock + * @arg @ref RCC_RNGCLKSOURCE_LSE LSE clock selected as RNG clock + */ +uint32_t HAL_RCCEx_GetRngCLKSource(void) +{ + uint32_t rng_clock_source = LL_RCC_GetRNGClockSource(LL_RCC_RNG_CLKSOURCE); + uint32_t clk48_clock_source; + + /* RNG clock source originates from 48 MHz RC oscillator */ + if (rng_clock_source == RCC_RNGCLKSOURCE_CLK48) + { + clk48_clock_source = LL_RCC_GetCLK48ClockSource(LL_RCC_CLK48_CLKSOURCE); + rng_clock_source = (CLK48_MASK | clk48_clock_source); + } + + return rng_clock_source; +} + +/** * @} */ @@ -1073,6 +1142,7 @@ * @{ */ +#if defined(SAI1) /** * @brief Enable PLLSAI1. * @param PLLSAI1Init pointer to an RCC_PLLSAI1InitTypeDef structure that @@ -1161,10 +1231,11 @@ } /* Disable the PLLSAI1 Clock outputs */ - __HAL_RCC_PLLSAI1CLKOUT_DISABLE(RCC_PLLSAI1_SAI1CLK | RCC_PLLSAI1_USBCLK | RCC_PLLSAI1_RNGCLK | RCC_PLLSAI1_ADCCLK); + __HAL_RCC_PLLSAI1CLKOUT_DISABLE(RCC_PLLSAI1_SAI1CLK | RCC_PLLSAI1_USBCLK | RCC_PLLSAI1_ADCCLK); return status; } +#endif /***********************************************************************************************/ @@ -1287,7 +1358,7 @@ GPIO_InitStruct.Pull = GPIO_NOPULL; /* RCC_LSCO1 */ - if(RCC_LSCOx == RCC_LSCO1) + if (RCC_LSCOx == RCC_LSCO1) { /* LSCO1 Clock Enable */ __LSCO1_CLK_ENABLE(); @@ -1317,23 +1388,23 @@ HAL_GPIO_Init(LSCO3_GPIO_PORT, &GPIO_InitStruct); } - /* Update LSCOSEL clock source in Backup Domain control register */ - if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) - { - HAL_PWR_EnableBkUpAccess(); - backupchanged = SET; - } - else - { - backupchanged = RESET; - } + /* Update LSCOSEL clock source in Backup Domain control register */ + if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + { + HAL_PWR_EnableBkUpAccess(); + backupchanged = SET; + } + else + { + backupchanged = RESET; + } - MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, RCC_LSCOSource | RCC_BDCR_LSCOEN); + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, RCC_LSCOSource | RCC_BDCR_LSCOEN); - if (backupchanged == SET) - { - HAL_PWR_DisableBkUpAccess(); - } + if (backupchanged == SET) + { + HAL_PWR_DisableBkUpAccess(); + } } @@ -1448,12 +1519,12 @@ */ HAL_StatusTypeDef HAL_RCCEx_TrimOsc(uint32_t OscillatorType) { - #define FTLSI2TRIM (0xFUL) +#define FTLSI2TRIM (0xFUL) HAL_StatusTypeDef status = HAL_OK; assert_param(IS_RCC_TRIMOSC(OscillatorType)); - if(OscillatorType == RCC_OSCILLATORTYPE_LSI2) + if (OscillatorType == RCC_OSCILLATORTYPE_LSI2) { if (LL_RCC_LSI2_IsReady() == 1U) { @@ -1478,7 +1549,7 @@ * @} */ - +#if defined(CRS) /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions * @brief Extended Clock Recovery System Control functions * @@ -1646,7 +1717,7 @@ { if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { crsstatus = RCC_CRS_TIMEOUT; } @@ -1833,6 +1904,7 @@ /** * @} */ +#endif /** * @} @@ -1842,6 +1914,7 @@ * @{ */ +#if defined(SAI1) /** * @brief Configure the parameters N & P of PLLSAI1 and enable PLLSAI1 output clock(s). * @param PLLSAI1 pointer to an RCC_PLLSAI1InitTypeDef structure that @@ -2046,6 +2119,7 @@ return status; } +#endif /** * @brief Return PLL clock (PLLPCLK) frequency used for SAI domain @@ -2085,7 +2159,7 @@ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()); break; } - return __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + return __LL_RCC_CALC_PLLCLK_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP()); } @@ -2114,14 +2188,14 @@ break; case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - if (LL_RCC_HSE_IsEnabledDiv2() == 1U) - { - pllinputfreq = HSE_VALUE / 2U; - } - else - { - pllinputfreq = HSE_VALUE; - } + if (LL_RCC_HSE_IsEnabledDiv2() == 1U) + { + pllinputfreq = HSE_VALUE / 2U; + } + else + { + pllinputfreq = HSE_VALUE; + } break; @@ -2133,6 +2207,7 @@ LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ()); } +#if defined(SAI1) /** * @brief Return PLLSAI1 clock (PLLSAI1RCLK) frequency used for ADC domain * @retval PLLSAI1RCLK clock frequency (in Hz) @@ -2197,14 +2272,14 @@ break; case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */ - if (LL_RCC_HSE_IsEnabledDiv2() == 1U) - { - pllinputfreq = HSE_VALUE / 2U; - } - else - { - pllinputfreq = HSE_VALUE; - } + if (LL_RCC_HSE_IsEnabledDiv2() == 1U) + { + pllinputfreq = HSE_VALUE / 2U; + } + else + { + pllinputfreq = HSE_VALUE; + } break; default: @@ -2238,14 +2313,14 @@ break; case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */ - if (LL_RCC_HSE_IsEnabledDiv2() == 1U) - { - pllinputfreq = HSE_VALUE / 2U; - } - else - { - pllinputfreq = HSE_VALUE; - } + if (LL_RCC_HSE_IsEnabledDiv2() == 1U) + { + pllinputfreq = HSE_VALUE / 2U; + } + else + { + pllinputfreq = HSE_VALUE; + } break; default: @@ -2255,7 +2330,7 @@ return __LL_RCC_CALC_PLLSAI1_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetQ()); } - +#endif /** * @} */
diff --git a/Src/stm32wbxx_hal_rng.c b/Src/stm32wbxx_hal_rng.c index 8e7f099..6bc79ac 100644 --- a/Src/stm32wbxx_hal_rng.c +++ b/Src/stm32wbxx_hal_rng.c
@@ -308,7 +308,7 @@ if (pCallback == NULL) { /* Update the error code */ - hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; return HAL_ERROR; } /* Process locked */ @@ -332,7 +332,7 @@ default : /* Update the error code */ - hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; break; @@ -352,7 +352,7 @@ default : /* Update the error code */ - hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; break; @@ -361,7 +361,7 @@ else { /* Update the error code */ - hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; } @@ -407,7 +407,7 @@ default : /* Update the error code */ - hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; break; @@ -427,7 +427,7 @@ default : /* Update the error code */ - hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; break; @@ -436,7 +436,7 @@ else { /* Update the error code */ - hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; } @@ -460,7 +460,7 @@ if (pCallback == NULL) { /* Update the error code */ - hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; return HAL_ERROR; } /* Process locked */ @@ -473,7 +473,7 @@ else { /* Update the error code */ - hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; } @@ -503,7 +503,7 @@ else { /* Update the error code */ - hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; } @@ -537,8 +537,16 @@ /** * @brief Generates a 32-bit random number. - * @note Each time the random number data is read the RNG_FLAG_DRDY flag - * is automatically cleared. + * @note This function checks value of RNG_FLAG_DRDY flag to know if valid + * random number is available in the DR register (RNG_FLAG_DRDY flag set + * whenever a random number is available through the RNG_DR register). + * After transitioning from 0 to 1 (random number available), + * RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading + * four words from the RNG_DR register, i.e. further function calls + * will immediately return a new u32 random number (additional words are + * available and can be read by the application, till RNG_FLAG_DRDY flag remains high). + * @note When no more random number data is available in DR register, RNG_FLAG_DRDY + * flag is automatically cleared. * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @param random32bit pointer to generated random number variable if successful. @@ -568,7 +576,7 @@ if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { hrng->State = HAL_RNG_STATE_READY; - hrng->ErrorCode |= HAL_RNG_ERROR_TIMEOUT; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; /* Process Unlocked */ __HAL_UNLOCK(hrng); return HAL_ERROR; @@ -583,6 +591,7 @@ } else { + hrng->ErrorCode = HAL_RNG_ERROR_BUSY; status = HAL_ERROR; } @@ -619,6 +628,7 @@ /* Process Unlocked */ __HAL_UNLOCK(hrng); + hrng->ErrorCode = HAL_RNG_ERROR_BUSY; status = HAL_ERROR; } @@ -653,10 +663,14 @@ /* RNG clock error interrupt occurred */ if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_CLOCK; rngclockerror = 1U; } else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_SEED; rngclockerror = 1U; } else @@ -721,6 +735,11 @@ /** * @brief Data Ready callback in non-blocking mode. + * @note When RNG_FLAG_DRDY flag value is set, first random number has been read + * from DR register in IRQ Handler and is provided as callback parameter. + * Depending on valid data available in the conditioning output buffer, + * additional words can be read by the application from DR register till + * DRDY bit remains high. * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @param random32bit generated random number.
diff --git a/Src/stm32wbxx_hal_rtc.c b/Src/stm32wbxx_hal_rtc.c index 24e9c3c..61d83e8 100644 --- a/Src/stm32wbxx_hal_rtc.c +++ b/Src/stm32wbxx_hal_rtc.c
@@ -256,9 +256,13 @@ hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */ hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */ hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */ +#if defined(RTC_TAMPER1_SUPPORT) hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ +#endif hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ +#if defined(RTC_TAMPER3_SUPPORT) hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */ +#endif if(hrtc->MspInitCallback == NULL) { @@ -470,11 +474,14 @@ * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID - * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID + * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID (*) * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID - * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID + * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID (*) * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * + * (*) Value not defined in all devices. \n + * * @param pCallback pointer to the Callback function * @retval HAL status */ @@ -510,17 +517,21 @@ hrtc->WakeUpTimerEventCallback = pCallback; break; +#if defined(RTC_TAMPER1_SUPPORT) case HAL_RTC_TAMPER1_EVENT_CB_ID : hrtc->Tamper1EventCallback = pCallback; break; - +#endif + case HAL_RTC_TAMPER2_EVENT_CB_ID : hrtc->Tamper2EventCallback = pCallback; break; +#if defined(RTC_TAMPER3_SUPPORT) case HAL_RTC_TAMPER3_EVENT_CB_ID : hrtc->Tamper3EventCallback = pCallback; break; +#endif case HAL_RTC_MSPINIT_CB_ID : hrtc->MspInitCallback = pCallback; @@ -576,11 +587,14 @@ * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID - * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID + * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID (*) * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID - * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID - * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID - * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID (*) + * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID + * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * + * (*) Value not defined in all devices. \n + * * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID) @@ -610,17 +624,21 @@ hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */ break; +#if defined(RTC_TAMPER1_SUPPORT) case HAL_RTC_TAMPER1_EVENT_CB_ID : hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ break; - +#endif + case HAL_RTC_TAMPER2_EVENT_CB_ID : hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ break; +#if defined(RTC_TAMPER3_SUPPORT) case HAL_RTC_TAMPER3_EVENT_CB_ID : hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */ break; +#endif case HAL_RTC_MSPINIT_CB_ID : hrtc->MspInitCallback = HAL_RTC_MspInit;
diff --git a/Src/stm32wbxx_hal_rtc_ex.c b/Src/stm32wbxx_hal_rtc_ex.c index 7b5928e..5fcee17 100644 --- a/Src/stm32wbxx_hal_rtc_ex.c +++ b/Src/stm32wbxx_hal_rtc_ex.c
@@ -479,8 +479,8 @@ uint32_t tmpreg; /* Check the parameters */ - assert_param( IS_RTC_TAMPER(sTamper->Tamper)); - assert_param( IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + assert_param(IS_RTC_TAMPER(sTamper->Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
diff --git a/Src/stm32wbxx_hal_sai.c b/Src/stm32wbxx_hal_sai.c index 4b158ab..9242715 100644 --- a/Src/stm32wbxx_hal_sai.c +++ b/Src/stm32wbxx_hal_sai.c
@@ -218,13 +218,15 @@ * @{ */ +#ifdef HAL_SAI_MODULE_ENABLED + +#if defined (SAI1) + /** @defgroup SAI SAI * @brief SAI HAL module driver * @{ */ -#ifdef HAL_SAI_MODULE_ENABLED - /* Private typedef -----------------------------------------------------------*/ /** @defgroup SAI_Private_Typedefs SAI Private Typedefs * @{ @@ -367,7 +369,6 @@ */ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) { - uint32_t tmpregisterGCR; uint32_t ckstr_bits; uint32_t syncen_bits; @@ -461,22 +462,6 @@ /* SAI Block Synchro Configuration -----------------------------------------*/ /* This setting must be done with both audio block (A & B) disabled */ - switch (hsai->Init.SynchroExt) - { - case SAI_SYNCEXT_DISABLE : - tmpregisterGCR = 0; - break; - case SAI_SYNCEXT_OUTBLOCKA_ENABLE : - tmpregisterGCR = SAI_GCR_SYNCOUT_0; - break; - case SAI_SYNCEXT_OUTBLOCKB_ENABLE : - tmpregisterGCR = SAI_GCR_SYNCOUT_1; - break; - default : - tmpregisterGCR = 0; - break; - } - switch (hsai->Init.Synchro) { case SAI_ASYNCHRONOUS : @@ -485,19 +470,12 @@ case SAI_SYNCHRONOUS : syncen_bits = SAI_xCR1_SYNCEN_0; break; - case SAI_SYNCHRONOUS_EXT_SAI1 : - syncen_bits = SAI_xCR1_SYNCEN_1; - break; - case SAI_SYNCHRONOUS_EXT_SAI2 : - syncen_bits = SAI_xCR1_SYNCEN_1; - tmpregisterGCR |= SAI_GCR_SYNCIN_0; - break; default : syncen_bits = 0; break; } - SAI1->GCR = tmpregisterGCR; + SAI1->GCR = 0; if (hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV) { @@ -515,8 +493,26 @@ if (hsai->Init.NoDivider == SAI_MASTERDIVIDER_DISABLE) { /* NODIV = 1 */ + uint32_t tmpframelength; + + if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL) + { + /* For SPDIF protocol, frame length is set by hardware to 64 */ + tmpframelength = 64U; + } + else if (hsai->Init.Protocol == SAI_AC97_PROTOCOL) + { + /* For AC97 protocol, frame length is set by hardware to 256 */ + tmpframelength = 256U; + } + else + { + /* For free protocol, frame length is set by user */ + tmpframelength = hsai->FrameInit.FrameLength; + } + /* (freq x 10) to keep Significant digits */ - tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * hsai->FrameInit.FrameLength); + tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * tmpframelength); } else { @@ -533,6 +529,12 @@ { hsai->Init.Mckdiv += 1U; } + + /* For SPDIF protocol, SAI shall provide a bit clock twice faster the symbol-rate */ + if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL) + { + hsai->Init.Mckdiv = hsai->Init.Mckdiv >> 1; + } } /* Check the SAI Block master clock divider parameter */ assert_param(IS_SAI_BLOCK_MASTER_DIVIDER(hsai->Init.Mckdiv)); @@ -1345,29 +1347,17 @@ /* Abort the SAI Tx DMA Stream */ if ((hsai->State == HAL_SAI_STATE_BUSY_TX) && (hsai->hdmatx != NULL)) { - if (HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) - { - /* If the DMA Tx errorCode is different from DMA No Transfer then return Error */ - if (hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER) - { - status = HAL_ERROR; - hsai->ErrorCode |= HAL_SAI_ERROR_DMA; - } - } + /* No need to check the returned value of HAL_DMA_Abort. */ + /* Only HAL_DMA_ERROR_NO_XFER can be returned in case of error and it's not an error for SAI. */ + (void) HAL_DMA_Abort(hsai->hdmatx); } /* Abort the SAI Rx DMA Stream */ if ((hsai->State == HAL_SAI_STATE_BUSY_RX) && (hsai->hdmarx != NULL)) { - if (HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) - { - /* If the DMA Rx errorCode is different from DMA No Transfer then return Error */ - if (hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER) - { - status = HAL_ERROR; - hsai->ErrorCode |= HAL_SAI_ERROR_DMA; - } - } + /* No need to check the returned value of HAL_DMA_Abort. */ + /* Only HAL_DMA_ERROR_NO_XFER can be returned in case of error and it's not an error for SAI. */ + (void) HAL_DMA_Abort(hsai->hdmarx); } /* Disable SAI peripheral */ @@ -1410,29 +1400,17 @@ /* Abort the SAI Tx DMA Stream */ if ((hsai->State == HAL_SAI_STATE_BUSY_TX) && (hsai->hdmatx != NULL)) { - if (HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) - { - /* If the DMA Tx errorCode is different from DMA No Transfer then return Error */ - if (hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER) - { - status = HAL_ERROR; - hsai->ErrorCode |= HAL_SAI_ERROR_DMA; - } - } + /* No need to check the returned value of HAL_DMA_Abort. */ + /* Only HAL_DMA_ERROR_NO_XFER can be returned in case of error and it's not an error for SAI. */ + (void) HAL_DMA_Abort(hsai->hdmatx); } /* Abort the SAI Rx DMA Stream */ if ((hsai->State == HAL_SAI_STATE_BUSY_RX) && (hsai->hdmarx != NULL)) { - if (HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) - { - /* If the DMA Rx errorCode is different from DMA No Transfer then return Error */ - if (hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER) - { - status = HAL_ERROR; - hsai->ErrorCode |= HAL_SAI_ERROR_DMA; - } - } + /* No need to check the returned value of HAL_DMA_Abort. */ + /* Only HAL_DMA_ERROR_NO_XFER can be returned in case of error and it's not an error for SAI. */ + (void) HAL_DMA_Abort(hsai->hdmarx); } } @@ -1591,6 +1569,12 @@ return HAL_ERROR; } + /* Enable the interrupts for error handling */ + __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); + + /* Enable SAI Rx DMA Request */ + hsai->Instance->CR1 |= SAI_xCR1_DMAEN; + /* Check if the SAI is already enabled */ if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) { @@ -1598,12 +1582,6 @@ __HAL_SAI_ENABLE(hsai); } - /* Enable the interrupts for error handling */ - __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); - - /* Enable SAI Rx DMA Request */ - hsai->Instance->CR1 |= SAI_xCR1_DMAEN; - /* Process Unlocked */ __HAL_UNLOCK(hsai); @@ -1746,6 +1724,9 @@ /* SAI AFSDET interrupt occurred ----------------------------------*/ else if (((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET)) { + /* Clear the SAI AFSDET flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_AFSDET); + /* Change the SAI error code */ hsai->ErrorCode |= HAL_SAI_ERROR_AFSDET; @@ -1809,6 +1790,9 @@ /* SAI LFSDET interrupt occurred ----------------------------------*/ else if (((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET)) { + /* Clear the SAI LFSDET flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_LFSDET); + /* Change the SAI error code */ hsai->ErrorCode |= HAL_SAI_ERROR_LFSDET; @@ -1872,6 +1856,9 @@ /* SAI WCKCFG interrupt occurred ----------------------------------*/ else if (((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG)) { + /* Clear the SAI WCKCFG flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_WCKCFG); + /* Change the SAI error code */ hsai->ErrorCode |= HAL_SAI_ERROR_WCKCFG; @@ -2132,20 +2119,16 @@ return HAL_ERROR; } - switch (protocol) + if (protocol == SAI_I2S_STANDARD) { - case SAI_I2S_STANDARD : - hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; - hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; - break; - case SAI_I2S_MSBJUSTIFIED : - case SAI_I2S_LSBJUSTIFIED : - hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH; - hsai->FrameInit.FSOffset = SAI_FS_FIRSTBIT; - break; - default : - status = HAL_ERROR; - break; + hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; + hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; + } + else + { + /* SAI_I2S_MSBJUSTIFIED or SAI_I2S_LSBJUSTIFIED */ + hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH; + hsai->FrameInit.FSOffset = SAI_FS_FIRSTBIT; } /* Frame definition */ @@ -2227,17 +2210,14 @@ hsai->SlotInit.SlotNumber = nbslot; hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL; - switch (protocol) + if (protocol == SAI_PCM_SHORT) { - case SAI_PCM_SHORT : - hsai->FrameInit.ActiveFrameLength = 1; - break; - case SAI_PCM_LONG : - hsai->FrameInit.ActiveFrameLength = 13; - break; - default : - status = HAL_ERROR; - break; + hsai->FrameInit.ActiveFrameLength = 1; + } + else + { + /* SAI_PCM_LONG */ + hsai->FrameInit.ActiveFrameLength = 13; } switch (datasize) @@ -2752,11 +2732,13 @@ * @} */ -#endif /* HAL_SAI_MODULE_ENABLED */ /** * @} */ +#endif /* SAI1 */ + +#endif /* HAL_SAI_MODULE_ENABLED */ /** * @} */
diff --git a/Src/stm32wbxx_hal_sai_ex.c b/Src/stm32wbxx_hal_sai_ex.c index 82b83d6..7200571 100644 --- a/Src/stm32wbxx_hal_sai_ex.c +++ b/Src/stm32wbxx_hal_sai_ex.c
@@ -29,6 +29,8 @@ */ #ifdef HAL_SAI_MODULE_ENABLED +#if defined (SAI1) + /** @defgroup SAIEx SAIEx * @brief SAI Extended HAL module driver * @{ @@ -123,6 +125,8 @@ * @} */ +#endif /* SAI1 */ + #endif /* HAL_SAI_MODULE_ENABLED */ /** * @}
diff --git a/Src/stm32wbxx_hal_smartcard.c b/Src/stm32wbxx_hal_smartcard.c index ddbf3e7..954da87 100644 --- a/Src/stm32wbxx_hal_smartcard.c +++ b/Src/stm32wbxx_hal_smartcard.c
@@ -2287,6 +2287,7 @@ SMARTCARD_ClockSourceTypeDef clocksource; HAL_StatusTypeDef ret = HAL_OK; const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; + uint32_t pclk; /* Check the parameters */ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); @@ -2341,7 +2342,7 @@ /*-------------------------- USART GTPR Configuration ----------------------*/ tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << USART_GTPR_GT_Pos)); - MODIFY_REG(hsmartcard->Instance->GTPR, (USART_GTPR_GT | USART_GTPR_PSC), tmpreg); + MODIFY_REG(hsmartcard->Instance->GTPR, (uint16_t)(USART_GTPR_GT | USART_GTPR_PSC), (uint16_t)tmpreg); /*-------------------------- USART RTOR Configuration ----------------------*/ tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos); @@ -2358,13 +2359,15 @@ switch (clocksource) { case SMARTCARD_CLOCKSOURCE_PCLK2: - tmpreg = (uint16_t)(((HAL_RCC_GetPCLK2Freq() / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + pclk = HAL_RCC_GetPCLK2Freq(); + tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_HSI: tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_SYSCLK: - tmpreg = (uint16_t)(((HAL_RCC_GetSysClockFreq() / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + pclk = HAL_RCC_GetSysClockFreq(); + tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_LSE: tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
diff --git a/Src/stm32wbxx_hal_spi.c b/Src/stm32wbxx_hal_spi.c index 24197ba..1011413 100644 --- a/Src/stm32wbxx_hal_spi.c +++ b/Src/stm32wbxx_hal_spi.c
@@ -65,16 +65,16 @@ Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback. Function HAL_SPI_RegisterCallback() allows to register following callbacks: - (+) TxCpltCallback : SPI Tx Completed callback - (+) RxCpltCallback : SPI Rx Completed callback - (+) TxRxCpltCallback : SPI TxRx Completed callback - (+) TxHalfCpltCallback : SPI Tx Half Completed callback - (+) RxHalfCpltCallback : SPI Rx Half Completed callback - (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback - (+) ErrorCallback : SPI Error callback - (+) AbortCpltCallback : SPI Abort callback - (+) MspInitCallback : SPI Msp Init callback - (+) MspDeInitCallback : SPI Msp DeInit callback + (++) TxCpltCallback : SPI Tx Completed callback + (++) RxCpltCallback : SPI Rx Completed callback + (++) TxRxCpltCallback : SPI TxRx Completed callback + (++) TxHalfCpltCallback : SPI Tx Half Completed callback + (++) RxHalfCpltCallback : SPI Rx Half Completed callback + (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (++) ErrorCallback : SPI Error callback + (++) AbortCpltCallback : SPI Abort callback + (++) MspInitCallback : SPI Msp Init callback + (++) MspDeInitCallback : SPI Msp DeInit callback This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. @@ -84,17 +84,18 @@ HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: - (+) TxCpltCallback : SPI Tx Completed callback - (+) RxCpltCallback : SPI Rx Completed callback - (+) TxRxCpltCallback : SPI TxRx Completed callback - (+) TxHalfCpltCallback : SPI Tx Half Completed callback - (+) RxHalfCpltCallback : SPI Rx Half Completed callback - (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback - (+) ErrorCallback : SPI Error callback - (+) AbortCpltCallback : SPI Abort callback - (+) MspInitCallback : SPI Msp Init callback - (+) MspDeInitCallback : SPI Msp DeInit callback + (++) TxCpltCallback : SPI Tx Completed callback + (++) RxCpltCallback : SPI Rx Completed callback + (++) TxRxCpltCallback : SPI TxRx Completed callback + (++) TxHalfCpltCallback : SPI Tx Half Completed callback + (++) RxHalfCpltCallback : SPI Rx Half Completed callback + (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (++) ErrorCallback : SPI Error callback + (++) AbortCpltCallback : SPI Abort callback + (++) MspInitCallback : SPI Msp Init callback + (++) MspDeInitCallback : SPI Msp DeInit callback + [..] By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET all callbacks are set to the corresponding weak functions: examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback(). @@ -104,6 +105,7 @@ If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state, @@ -112,7 +114,8 @@ using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit() or HAL_SPI_Init() function. - When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or + [..] + When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available and weak (surcharged) callbacks are used. @@ -269,8 +272,8 @@ */ /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -535,7 +538,8 @@ * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, + pSPI_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -745,8 +749,8 @@ */ /** @defgroup SPI_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions - * + * @brief Data transfers functions + * @verbatim ============================================================================== ##### IO operation functions ##### @@ -1872,7 +1876,8 @@ } /* Enable the Tx DMA Stream/Channel */ - if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount)) + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, + hspi->TxXferCount)) { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); @@ -2014,7 +2019,8 @@ hspi->hdmarx->XferAbortCallback = NULL; /* Enable the Rx DMA Stream/Channel */ - if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount)) + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount)) { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); @@ -2181,7 +2187,8 @@ hspi->hdmarx->XferAbortCallback = NULL; /* Enable the Rx DMA Stream/Channel */ - if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount)) + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount)) { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); @@ -2202,7 +2209,8 @@ hspi->hdmatx->XferAbortCallback = NULL; /* Enable the Tx DMA Stream/Channel */ - if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount)) + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, + hspi->TxXferCount)) { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); @@ -2242,11 +2250,12 @@ * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) { HAL_StatusTypeDef errorcode; - __IO uint32_t count, resetcount; + __IO uint32_t count; + __IO uint32_t resetcount; /* Initialized local variable */ errorcode = HAL_OK; @@ -2269,8 +2278,7 @@ break; } count--; - } - while (hspi->State != HAL_SPI_STATE_ABORT); + } while (hspi->State != HAL_SPI_STATE_ABORT); /* Reset Timeout Counter */ count = resetcount; } @@ -2287,8 +2295,7 @@ break; } count--; - } - while (hspi->State != HAL_SPI_STATE_ABORT); + } while (hspi->State != HAL_SPI_STATE_ABORT); /* Reset Timeout Counter */ count = resetcount; } @@ -2403,12 +2410,13 @@ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) { HAL_StatusTypeDef errorcode; uint32_t abortcplt ; - __IO uint32_t count, resetcount; + __IO uint32_t count; + __IO uint32_t resetcount; /* Initialized local variable */ errorcode = HAL_OK; @@ -2432,8 +2440,7 @@ break; } count--; - } - while (hspi->State != HAL_SPI_STATE_ABORT); + } while (hspi->State != HAL_SPI_STATE_ABORT); /* Reset Timeout Counter */ count = resetcount; } @@ -2450,8 +2457,7 @@ break; } count--; - } - while (hspi->State != HAL_SPI_STATE_ABORT); + } while (hspi->State != HAL_SPI_STATE_ABORT); /* Reset Timeout Counter */ count = resetcount; } @@ -2667,7 +2673,8 @@ } /* SPI in Error Treatment --------------------------------------------------*/ - if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET)) + if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) + || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET)) { /* SPI Overrun error interrupt occurred ----------------------------------*/ if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) @@ -4164,8 +4171,7 @@ break; } count--; - } - while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); + } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) @@ -4206,8 +4212,7 @@ break; } count--; - } - while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)); + } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)); if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) { @@ -4238,8 +4243,7 @@ break; } count--; - } - while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); + } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
diff --git a/Src/stm32wbxx_hal_tim.c b/Src/stm32wbxx_hal_tim.c index 740506f..9ebfa33 100644 --- a/Src/stm32wbxx_hal_tim.c +++ b/Src/stm32wbxx_hal_tim.c
@@ -498,11 +498,11 @@ /* Check the parameters */ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { @@ -950,11 +950,11 @@ /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { @@ -1529,11 +1529,11 @@ /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { @@ -2077,11 +2077,11 @@ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { @@ -2988,11 +2988,11 @@ /* Check the parameters */ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) { @@ -3755,6 +3755,10 @@ * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @note To output a waveform with a minimum delay user can enable the fast + * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx + * output is forced in response to the edge detection on TIx input, + * without taking in account the comparison. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, @@ -3911,11 +3915,11 @@ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { if ((BurstBuffer == NULL) && (BurstLength > 0U)) { @@ -4182,11 +4186,11 @@ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { if ((BurstBuffer == NULL) && (BurstLength > 0U)) {
diff --git a/Src/stm32wbxx_hal_tim_ex.c b/Src/stm32wbxx_hal_tim_ex.c index f3bee11..2504060 100644 --- a/Src/stm32wbxx_hal_tim_ex.c +++ b/Src/stm32wbxx_hal_tim_ex.c
@@ -409,11 +409,11 @@ /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { if (((uint32_t)pData == 0U) && (Length > 0U)) { @@ -721,11 +721,11 @@ /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { if (((uint32_t)pData == 0U) && (Length > 0U)) { @@ -1129,11 +1129,11 @@ /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { if (((uint32_t)pData == 0U) && (Length > 0U)) { @@ -1705,6 +1705,9 @@ * @param htim TIM handle * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that * contains the BDTR Register configuration information for the TIM peripheral. + * @note Interrupts can be generated when an active level is detected on the + * break input, the break 2 input or the system break input. Break + * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, @@ -1777,10 +1780,10 @@ { uint32_t tmporx; - uint32_t bkin_enable_mask = 0U; - uint32_t bkin_polarity_mask = 0U; - uint32_t bkin_enable_bitpos = 0U; - uint32_t bkin_polarity_bitpos = 0U; + uint32_t bkin_enable_mask; + uint32_t bkin_polarity_mask; + uint32_t bkin_enable_bitpos; + uint32_t bkin_polarity_bitpos; /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); @@ -1797,10 +1800,12 @@ case TIM_BREAKINPUTSOURCE_BKIN: { bkin_enable_mask = TIM1_AF1_BKINE; + bkin_enable_bitpos = TIM1_AF1_BKINE_Pos; bkin_polarity_mask = TIM1_AF1_BKINP; bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos; break; } +#if defined(COMP1) && defined(COMP2) case TIM_BREAKINPUTSOURCE_COMP1: { bkin_enable_mask = TIM1_AF1_BKCMP1E; @@ -1817,9 +1822,16 @@ bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos; break; } +#endif /* COMP1 && COMP2 */ default: + { + bkin_enable_mask = 0U; + bkin_polarity_mask = 0U; + bkin_enable_bitpos = 0U; + bkin_polarity_bitpos = 0U; break; + } } switch (BreakInput) @@ -1878,29 +1890,29 @@ * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3 - * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output - * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output + * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output (*) + * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output (*) * field2 can have the following values: * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to I/O - * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output + * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output (*) * * For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3): * * field1 can have the following values: * @arg TIM_TIM2_ITR1_NONE: No internal trigger on TIM2_ITR1 - * @arg TIM_TIM2_ITR1_USB: TIM2_ITR1 is connected to USB SOF + * @arg TIM_TIM2_ITR1_USB: TIM2_ITR1 is connected to USB SOF (*) * * field2 can have the following values: * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to I/O * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE - * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output - * @arg TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output + * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output (*) + * @arg TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output (*) * * field3 can have the following values: * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to I/O - * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output - * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output - * @arg TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output + * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output (*) + * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output (*) + * @arg TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output (*) * * For TIM16, the parameter can have the following values: * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to I/O @@ -1910,10 +1922,12 @@ * * For TIM17, the parameter can have the following values: * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to I/O - * @arg TIM_TIM17_TI1_MSI: TIM17 TI1 is connected to MSI (contraints: MSI clock < 1/4 TIM APB clock) + * @arg TIM_TIM17_TI1_MSI: TIM17 TI1 is connected to MSI (constraint: MSI clock < 1/4 TIM APB clock) * @arg TIM_TIM17_TI1_HSE: TIM17 TI1 is connected to HSE div 32 * @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO * + * (*) Value not defined in all devices. + * * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
diff --git a/Src/stm32wbxx_hal_tsc.c b/Src/stm32wbxx_hal_tsc.c index 5a69a6e..9abed26 100644 --- a/Src/stm32wbxx_hal_tsc.c +++ b/Src/stm32wbxx_hal_tsc.c
@@ -193,6 +193,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32wbxx_hal.h" +#if defined(TSC) /** @addtogroup STM32WBxx_HAL_Driver * @{ */ @@ -1117,4 +1118,5 @@ * @} */ +#endif /* TSC */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32wbxx_hal_uart.c b/Src/stm32wbxx_hal_uart.c index b7a2174..de225f7 100644 --- a/Src/stm32wbxx_hal_uart.c +++ b/Src/stm32wbxx_hal_uart.c
@@ -179,8 +179,10 @@ #define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \ USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ +#if defined(LPUART1) #define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */ #define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */ +#endif #define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ #define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ @@ -308,7 +310,11 @@ else { /* Check the parameters */ +#if defined(LPUART1) assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); +#else + assert_param(IS_UART_INSTANCE(huart->Instance)); +#endif } if (huart->gState == HAL_UART_STATE_RESET) @@ -334,7 +340,6 @@ huart->gState = HAL_UART_STATE_BUSY; - /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); /* Set the UART Communication parameters */ @@ -354,7 +359,6 @@ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ @@ -401,7 +405,6 @@ huart->gState = HAL_UART_STATE_BUSY; - /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); /* Set the UART Communication parameters */ @@ -424,7 +427,6 @@ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); - /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ @@ -489,7 +491,6 @@ huart->gState = HAL_UART_STATE_BUSY; - /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); /* Set the UART Communication parameters */ @@ -515,7 +516,6 @@ /* Set the USART LIN Break detection length. */ MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); - /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ @@ -575,7 +575,6 @@ huart->gState = HAL_UART_STATE_BUSY; - /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); /* Set the UART Communication parameters */ @@ -604,7 +603,6 @@ /* Set the wake up method by setting the WAKE bit in the CR1 register */ MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); - /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ @@ -626,11 +624,14 @@ } /* Check the parameters */ +#if defined(LPUART1) assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); +#else + assert_param(IS_UART_INSTANCE(huart->Instance)); +#endif huart->gState = HAL_UART_STATE_BUSY; - /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); huart->Instance->CR1 = 0x0U; @@ -653,7 +654,6 @@ huart->gState = HAL_UART_STATE_RESET; huart->RxState = HAL_UART_STATE_RESET; - /* Process Unlock */ __HAL_UNLOCK(huart); return HAL_OK; @@ -712,18 +712,18 @@ * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; if (pCallback == NULL) { - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; return HAL_ERROR; } - /* Process locked */ + __HAL_LOCK(huart); if (huart->gState == HAL_UART_STATE_READY) @@ -783,10 +783,8 @@ break; default : - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; break; } @@ -804,24 +802,19 @@ break; default : - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; break; } } else { - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; } - /* Release Lock */ __HAL_UNLOCK(huart); return status; @@ -852,7 +845,6 @@ { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ __HAL_LOCK(huart); if (HAL_UART_STATE_READY == huart->gState) @@ -912,10 +904,8 @@ break; default : - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; break; } @@ -933,24 +923,19 @@ break; default : - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; break; } } else { - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; } - /* Release Lock */ __HAL_UNLOCK(huart); return status; @@ -1040,13 +1025,16 @@ /** * @brief Send an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. * @note When FIFO mode is enabled, writing a data in the TDR register adds one * data to the TXFIFO. Write operations to the TDR register are performed * when TXFNF flag is set. From hardware perspective, TXFNF flag and * TXE are mapped on the same bit-field. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @param Timeout Timeout duration. * @retval HAL status */ @@ -1064,7 +1052,6 @@ return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -1076,7 +1063,7 @@ huart->TxXferSize = Size; huart->TxXferCount = Size; - /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { pdata8bits = NULL; @@ -1115,7 +1102,6 @@ /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -1128,13 +1114,16 @@ /** * @brief Receive an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO * is not empty. Read operations from the RDR register are performed when * RXFNE flag is set. From hardware perspective, RXFNE flag and * RXNE are mapped on the same bit-field. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @param Timeout Timeout duration. * @retval HAL status */ @@ -1153,7 +1142,6 @@ return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -1204,7 +1192,6 @@ /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -1217,9 +1204,12 @@ /** * @brief Send an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -1232,7 +1222,6 @@ return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(huart); huart->pTxBuffPtr = pData; @@ -1256,7 +1245,6 @@ huart->TxISR = UART_TxISR_8BIT_FIFOEN; } - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the TX FIFO threshold interrupt */ @@ -1274,7 +1262,6 @@ huart->TxISR = UART_TxISR_8BIT; } - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the Transmit Data Register Empty interrupt */ @@ -1291,9 +1278,12 @@ /** * @brief Receive an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -1306,7 +1296,6 @@ return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(huart); huart->pRxBuffPtr = pData; @@ -1336,7 +1325,6 @@ huart->RxISR = UART_RxISR_8BIT_FIFOEN; } - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ @@ -1355,7 +1343,6 @@ huart->RxISR = UART_RxISR_8BIT; } - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ @@ -1372,9 +1359,12 @@ /** * @brief Send an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -1387,7 +1377,6 @@ return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(huart); huart->pTxBuffPtr = pData; @@ -1417,7 +1406,6 @@ /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Restore huart->gState to ready */ @@ -1429,7 +1417,6 @@ /* Clear the TC flag in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the DMA transfer for transmit request by setting the DMAT bit @@ -1448,9 +1435,12 @@ * @brief Receive an amount of data in DMA mode. * @note When the UART parity is enabled (PCE = 1), the received data contain * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -1463,7 +1453,6 @@ return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(huart); huart->pRxBuffPtr = pData; @@ -1492,7 +1481,6 @@ /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Restore huart->gState to ready */ @@ -1501,7 +1489,6 @@ return HAL_ERROR; } } - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the UART Parity Error Interrupt */ @@ -1532,7 +1519,6 @@ const HAL_UART_StateTypeDef gstate = huart->gState; const HAL_UART_StateTypeDef rxstate = huart->RxState; - /* Process Locked */ __HAL_LOCK(huart); if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && @@ -1552,7 +1538,6 @@ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -1565,7 +1550,6 @@ */ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); if (huart->gState == HAL_UART_STATE_BUSY_TX) @@ -1586,7 +1570,6 @@ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -1671,7 +1654,7 @@ * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) { /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ @@ -1748,7 +1731,6 @@ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - /* Reset Handle ErrorCode to No Error */ huart->ErrorCode = HAL_UART_ERROR_NONE; return HAL_OK; @@ -1765,7 +1747,7 @@ * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) { /* Disable TCIE, TXEIE and TXFTIE interrupts */ @@ -1823,7 +1805,7 @@ * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) { /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */ @@ -1883,7 +1865,7 @@ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) { uint32_t abortcplt = 1U; @@ -2027,7 +2009,7 @@ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) { /* Disable interrupts */ @@ -2117,7 +2099,7 @@ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ @@ -2212,7 +2194,7 @@ uint32_t errorcode; /* If no error occurs */ - errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); if (errorflags == 0U) { /* UART in mode Receiver ---------------------------------------------------*/ @@ -2231,7 +2213,7 @@ /* If some errors occur */ if ((errorflags != 0U) && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) - || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U)))) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) @@ -2267,10 +2249,18 @@ huart->ErrorCode |= HAL_UART_ERROR_ORE; } - /* Call UART Error Call back function if need be --------------------------*/ + /* UART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + huart->ErrorCode |= HAL_UART_ERROR_RTO; + } + + /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) { - /* UART in mode Receiver ---------------------------------------------------*/ + /* UART in mode Receiver --------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || ((cr3its & USART_CR3_RXFTIE) != 0U))) @@ -2281,11 +2271,14 @@ } } - /* If Overrun error occurs, or if any error occurs in DMA mode reception, - consider error as blocking */ + /* If Error is to be considered as blocking : + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception + */ errorcode = huart->ErrorCode; if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || - ((errorcode & HAL_UART_ERROR_ORE) != 0U)) + ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, @@ -2551,6 +2544,9 @@ =============================================================================== [..] This subsection provides a set of functions allowing to control the UART. + (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly + (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature + (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode @@ -2565,6 +2561,99 @@ */ /** + * @brief Update on the fly the receiver timeout value in RTOR register. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param TimeoutValue receiver timeout value in number of baud blocks. The timeout + * value must be less or equal to 0x0FFFFFFFF. + * @retval None + */ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue)); + MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue); + } +} + +/** + * @brief Enable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Set the USART RTOEN bit */ + SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Disable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear the USART RTOEN bit */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } + } + else + { + return HAL_ERROR; + } +} + +/** * @brief Enable UART in mute mode (does not mean UART enters mute mode; * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). * @param huart UART handle. @@ -2572,7 +2661,6 @@ */ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; @@ -2593,7 +2681,6 @@ */ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; @@ -2624,7 +2711,6 @@ */ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; @@ -2636,7 +2722,6 @@ huart->gState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -2649,7 +2734,6 @@ */ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; @@ -2661,7 +2745,6 @@ huart->gState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -2678,7 +2761,6 @@ /* Check the parameters */ assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); - /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; @@ -2688,7 +2770,6 @@ huart->gState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -2699,8 +2780,8 @@ */ /** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions - * @brief UART Peripheral State functions - * + * @brief UART Peripheral State functions + * @verbatim ============================================================================== ##### Peripheral State and Error functions ##### @@ -2722,7 +2803,8 @@ */ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) { - uint32_t temp1, temp2; + uint32_t temp1; + uint32_t temp2; temp1 = huart->gState; temp2 = huart->RxState; @@ -2734,7 +2816,7 @@ * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART. * @retval UART Error Code -*/ + */ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) { return huart->ErrorCode; @@ -2787,11 +2869,15 @@ UART_ClockSourceTypeDef clocksource; uint32_t usartdiv = 0x00000000U; HAL_StatusTypeDef ret = HAL_OK; +#if defined(LPUART1) uint32_t lpuart_ker_ck_pres = 0x00000000U; +#endif + uint32_t pclk; /* Check the parameters */ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); +#if defined(LPUART1) if (UART_INSTANCE_LOWPOWER(huart)) { assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits)); @@ -2801,6 +2887,10 @@ assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); } +#else + assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); + assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); +#endif assert_param(IS_UART_PARITY(huart->Init.Parity)); assert_param(IS_UART_MODE(huart->Init.Mode)); @@ -2832,10 +2922,14 @@ * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; +#if defined(LPUART1) if (!(UART_INSTANCE_LOWPOWER(huart))) { tmpreg |= huart->Init.OneBitSampling; } +#else + tmpreg |= huart->Init.OneBitSampling; +#endif MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); /*-------------------------- USART PRESC Configuration -----------------------*/ @@ -2846,6 +2940,7 @@ /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); +#if defined(LPUART1) /* Check LPUART instance */ if (UART_INSTANCE_LOWPOWER(huart)) { @@ -2883,13 +2978,15 @@ switch (clocksource) { case UART_CLOCKSOURCE_PCLK1: - usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK1Freq(); + usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_HSI: usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_SYSCLK: - usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetSysClockFreq(); + usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_LSE: usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); @@ -2913,20 +3010,25 @@ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) +#else + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) +#endif /* LPUART1 */ { switch (clocksource) { case UART_CLOCKSOURCE_PCLK2: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK2Freq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_HSI: usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_SYSCLK: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetSysClockFreq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_LSE: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; default: ret = HAL_ERROR; @@ -2950,16 +3052,18 @@ switch (clocksource) { case UART_CLOCKSOURCE_PCLK2: - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK2Freq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_HSI: usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_SYSCLK: - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetSysClockFreq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_LSE: - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; default: ret = HAL_ERROR; @@ -3087,6 +3191,7 @@ return HAL_TIMEOUT; } } + /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) { @@ -3102,7 +3207,6 @@ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -3117,7 +3221,8 @@ * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) @@ -3134,11 +3239,32 @@ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_TIMEOUT; } + + if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) + { + /* Clear Receiver Timeout flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ErrorCode = HAL_UART_ERROR_RTO; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_TIMEOUT; + } + } } } return HAL_OK; @@ -3570,7 +3696,7 @@ else { tmp = (uint16_t *) huart->pTxBuffPtr; - huart->Instance->TDR = (uint16_t)(*tmp & USART_TDR_TDR_Msk); + huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); huart->pTxBuffPtr += 2U; huart->TxXferCount--; } @@ -3647,7 +3773,7 @@ else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) { tmp = (uint16_t *) huart->pTxBuffPtr; - huart->Instance->TDR = (uint16_t)(*tmp & USART_TDR_TDR_Msk); + huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); huart->pTxBuffPtr += 2U; huart->TxXferCount--; }
diff --git a/Src/stm32wbxx_hal_uart_ex.c b/Src/stm32wbxx_hal_uart_ex.c index 9154997..1ab7a12 100644 --- a/Src/stm32wbxx_hal_uart_ex.c +++ b/Src/stm32wbxx_hal_uart_ex.c
@@ -163,7 +163,8 @@ * oversampling rate). * @retval HAL status */ -HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime) +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime) { uint32_t temp; @@ -239,7 +240,6 @@ return (UART_CheckIdleState(huart)); } - /** * @} */ @@ -315,7 +315,7 @@ /** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions * @brief Extended Peripheral Control functions - * + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -336,9 +336,6 @@ * @{ */ - - - /** * @brief By default in multiprocessor mode, when the wake up method is set * to address mark, the UART handles only 4-bit long addresses detection; @@ -378,7 +375,6 @@ return (UART_CheckIdleState(huart)); } - /** * @brief Set Wakeup from Stop mode interrupt flag selection. * @note It is the application responsibility to enable the interrupt used as @@ -440,7 +436,6 @@ return status; } - /** * @brief Enable UART Stop Mode. * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
diff --git a/Src/stm32wbxx_hal_usart.c b/Src/stm32wbxx_hal_usart.c index 4d1dfdb..a17bd51 100644 --- a/Src/stm32wbxx_hal_usart.c +++ b/Src/stm32wbxx_hal_usart.c
@@ -2823,6 +2823,7 @@ HAL_StatusTypeDef ret = HAL_OK; uint16_t brrtemp; uint32_t usartdiv = 0x00000000; + uint32_t pclk; /* Check the parameters */ assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity)); @@ -2869,13 +2870,15 @@ switch (clocksource) { case USART_CLOCKSOURCE_PCLK2: - usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate, husart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK2Freq(); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler)); break; case USART_CLOCKSOURCE_HSI: usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); break; case USART_CLOCKSOURCE_SYSCLK: - usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), husart->Init.BaudRate, husart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetSysClockFreq(); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler)); break; case USART_CLOCKSOURCE_LSE: usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler));
diff --git a/Src/stm32wbxx_ll_adc.c b/Src/stm32wbxx_ll_adc.c index 06a8259..2aa46ee 100644 --- a/Src/stm32wbxx_ll_adc.c +++ b/Src/stm32wbxx_ll_adc.c
@@ -23,9 +23,9 @@ #include "stm32wbxx_ll_bus.h" #ifdef USE_FULL_ASSERT - #include "stm32_assert.h" +#include "stm32_assert.h" #else - #define assert_param(expr) ((void)0U) +#define assert_param(expr) ((void)0U) #endif /** @addtogroup STM32WBxx_LL_Driver @@ -244,13 +244,13 @@ { /* Check the parameters */ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); - + /* Force reset of ADC clock (core clock) */ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC); - + /* Release reset of ADC clock (core clock) */ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC); - + return SUCCESS; } @@ -272,33 +272,33 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock)); - + /* Note: Hardware constraint (refer to description of functions */ /* "LL_ADC_SetCommonXXX()": */ /* On this STM32 serie, setting of these features is conditioned to */ /* ADC state: */ /* All ADC instances of the ADC common group must be disabled. */ - if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL) + if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - common to several ADC */ /* (all ADC instances belonging to the same ADC common instance) */ /* - Set ADC clock (conversion clock) */ #if defined(ADC_MULTIMODE_SUPPORT) - if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) + if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) { MODIFY_REG(ADCxy_COMMON->CCR, - ADC_CCR_CKMODE + ADC_CCR_CKMODE | ADC_CCR_PRESC | ADC_CCR_DUAL | ADC_CCR_MDMA | ADC_CCR_DELAY - , - ADC_CommonInitStruct->CommonClock + , + ADC_CommonInitStruct->CommonClock | ADC_CommonInitStruct->Multimode | ADC_CommonInitStruct->MultiDMATransfer | ADC_CommonInitStruct->MultiTwoSamplingDelay @@ -307,13 +307,13 @@ else { MODIFY_REG(ADCxy_COMMON->CCR, - ADC_CCR_CKMODE + ADC_CCR_CKMODE | ADC_CCR_PRESC | ADC_CCR_DUAL | ADC_CCR_MDMA | ADC_CCR_DELAY - , - ADC_CommonInitStruct->CommonClock + , + ADC_CommonInitStruct->CommonClock | LL_ADC_MULTI_INDEPENDENT ); } @@ -327,7 +327,7 @@ /* the same ADC common instance are not disabled. */ status = ERROR; } - + return status; } @@ -343,7 +343,7 @@ /* Set fields of ADC common */ /* (all ADC instances belonging to the same ADC common instance) */ ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; - + } /** @@ -364,71 +364,71 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) { ErrorStatus status = SUCCESS; - + __IO uint32_t timeout_cpu_cycles = 0UL; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - + /* Disable ADC instance if not already disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 1UL) + if (LL_ADC_IsEnabled(ADCx) == 1UL) { /* Set ADC group regular trigger source to SW start to ensure to not */ /* have an external trigger event occurring during the conversion stop */ /* ADC disable process. */ LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); - + /* Stop potential ADC conversion on going on ADC group regular. */ - if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL) + if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL) { - if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL) + if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL) { LL_ADC_REG_StopConversion(ADCx); } } - + /* Set ADC group injected trigger source to SW start to ensure to not */ /* have an external trigger event occurring during the conversion stop */ /* ADC disable process. */ LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); - + /* Stop potential ADC conversion on going on ADC group injected. */ - if(LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL) + if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL) { - if(LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL) + if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL) { LL_ADC_INJ_StopConversion(ADCx); } } - + /* Wait for ADC conversions are effectively stopped */ timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES; - while (( LL_ADC_REG_IsStopConversionOngoing(ADCx) + while ((LL_ADC_REG_IsStopConversionOngoing(ADCx) | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL) { timeout_cpu_cycles--; - if(timeout_cpu_cycles == 0UL) + if (timeout_cpu_cycles == 0UL) { /* Time-out error */ status = ERROR; break; } } - + /* Flush group injected contexts queue (register JSQR): */ /* Note: Bit JQM must be set to empty the contexts queue (otherwise */ /* contexts queue is maintained with the last active context). */ LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY); - + /* Disable the ADC instance */ LL_ADC_Disable(ADCx); - + /* Wait for ADC instance is effectively disabled */ timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES; while (LL_ADC_IsDisableOngoing(ADCx) == 1UL) { timeout_cpu_cycles--; - if(timeout_cpu_cycles == 0UL) + if (timeout_cpu_cycles == 0UL) { /* Time-out error */ status = ERROR; @@ -436,18 +436,18 @@ } } } - + /* Check whether ADC state is compliant with expected state */ - if(READ_BIT(ADCx->CR, - ( ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART - | ADC_CR_ADDIS | ADC_CR_ADEN ) - ) - == 0UL) + if (READ_BIT(ADCx->CR, + (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART + | ADC_CR_ADDIS | ADC_CR_ADEN) + ) + == 0UL) { /* ========== Reset ADC registers ========== */ /* Reset register IER */ CLEAR_BIT(ADCx->IER, - ( LL_ADC_IT_ADRDY + (LL_ADC_IT_ADRDY | LL_ADC_IT_EOC | LL_ADC_IT_EOS | LL_ADC_IT_OVR @@ -460,10 +460,10 @@ | LL_ADC_IT_AWD3 ) ); - + /* Reset register ISR */ SET_BIT(ADCx->ISR, - ( LL_ADC_FLAG_ADRDY + (LL_ADC_FLAG_ADRDY | LL_ADC_FLAG_EOC | LL_ADC_FLAG_EOS | LL_ADC_FLAG_OVR @@ -476,7 +476,7 @@ | LL_ADC_FLAG_AWD3 ) ); - + /* Reset register CR */ /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */ /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */ @@ -489,79 +489,79 @@ /* already done above. */ CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF); SET_BIT(ADCx->CR, ADC_CR_DEEPPWD); - + /* Reset register CFGR */ MODIFY_REG(ADCx->CFGR, - ( ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN + (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN - | ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN ), - ADC_CFGR_JQDIS + | ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN), + ADC_CFGR_JQDIS ); - + /* Reset register CFGR2 */ CLEAR_BIT(ADCx->CFGR2, - ( ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS + (ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS | ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) ); - + /* Reset register SMPR1 */ CLEAR_BIT(ADCx->SMPR1, - ( ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 + (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1) ); - + /* Reset register SMPR2 */ CLEAR_BIT(ADCx->SMPR2, - ( ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 + (ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10) ); - + /* Reset register TR1 */ MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1); - + /* Reset register TR2 */ MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2); - + /* Reset register TR3 */ MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3); - + /* Reset register SQR1 */ CLEAR_BIT(ADCx->SQR1, - ( ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 + (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 | ADC_SQR1_SQ1 | ADC_SQR1_L) ); - + /* Reset register SQR2 */ CLEAR_BIT(ADCx->SQR2, - ( ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 + (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5) ); - + /* Reset register SQR3 */ CLEAR_BIT(ADCx->SQR3, - ( ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 + (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10) ); - + /* Reset register SQR4 */ CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15); - + /* Reset register JSQR */ CLEAR_BIT(ADCx->JSQR, - ( ADC_JSQR_JL + (ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 - | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ) + | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1) ); - + /* Reset register DR */ /* Note: bits in access mode read only, no direct reset applicable */ - + /* Reset register OFR1 */ CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1); /* Reset register OFR2 */ @@ -570,19 +570,19 @@ CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3); /* Reset register OFR4 */ CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4); - + /* Reset registers JDR1, JDR2, JDR3, JDR4 */ /* Note: bits in access mode read only, no direct reset applicable */ - + /* Reset register AWD2CR */ CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH); - + /* Reset register AWD3CR */ CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH); - + /* Reset register DIFSEL */ CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL); - + /* Reset register CALFACT */ CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S); } @@ -596,7 +596,7 @@ /* all ADC instances belonging to the common ADC instance. */ status = ERROR; } - + return status; } @@ -636,17 +636,17 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - + assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode)); - + /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 0UL) + if (LL_ADC_IsEnabled(ADCx) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - ADC instance */ @@ -654,15 +654,15 @@ /* - Set ADC conversion data alignment */ /* - Set ADC low power mode */ MODIFY_REG(ADCx->CFGR, - ADC_CFGR_RES + ADC_CFGR_RES | ADC_CFGR_ALIGN | ADC_CFGR_AUTDLY - , - ADC_InitStruct->Resolution + , + ADC_InitStruct->Resolution | ADC_InitStruct->DataAlignment | ADC_InitStruct->LowPowerMode ); - + } else { @@ -685,7 +685,7 @@ ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE; - + } /** @@ -723,22 +723,22 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); - if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); } assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun)); - + /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 0UL) + if (LL_ADC_IsEnabled(ADCx) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - ADC group regular */ @@ -751,10 +751,10 @@ /* - Set ADC group regular overrun behavior */ /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ - if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { MODIFY_REG(ADCx->CFGR, - ADC_CFGR_EXTSEL + ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN | ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM @@ -762,8 +762,8 @@ | ADC_CFGR_DMAEN | ADC_CFGR_DMACFG | ADC_CFGR_OVRMOD - , - ADC_REG_InitStruct->TriggerSource + , + ADC_REG_InitStruct->TriggerSource | ADC_REG_InitStruct->SequencerDiscont | ADC_REG_InitStruct->ContinuousMode | ADC_REG_InitStruct->DMATransfer @@ -773,7 +773,7 @@ else { MODIFY_REG(ADCx->CFGR, - ADC_CFGR_EXTSEL + ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN | ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM @@ -781,15 +781,15 @@ | ADC_CFGR_DMAEN | ADC_CFGR_DMACFG | ADC_CFGR_OVRMOD - , - ADC_REG_InitStruct->TriggerSource + , + ADC_REG_InitStruct->TriggerSource | LL_ADC_REG_SEQ_DISCONT_DISABLE | ADC_REG_InitStruct->ContinuousMode | ADC_REG_InitStruct->DMATransfer | ADC_REG_InitStruct->Overrun ); } - + /* Set ADC group regular sequencer length and scan direction */ LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); } @@ -856,20 +856,20 @@ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource)); assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); - if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) + if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) { assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); } assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto)); - + /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 0UL) + if (LL_ADC_IsEnabled(ADCx) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - ADC group injected */ @@ -880,33 +880,33 @@ /* from ADC group regular */ /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ - if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { MODIFY_REG(ADCx->CFGR, - ADC_CFGR_JDISCEN + ADC_CFGR_JDISCEN | ADC_CFGR_JAUTO - , - ADC_INJ_InitStruct->SequencerDiscont + , + ADC_INJ_InitStruct->SequencerDiscont | ADC_INJ_InitStruct->TrigAuto ); } else { MODIFY_REG(ADCx->CFGR, - ADC_CFGR_JDISCEN + ADC_CFGR_JDISCEN | ADC_CFGR_JAUTO - , - LL_ADC_REG_SEQ_DISCONT_DISABLE + , + LL_ADC_REG_SEQ_DISCONT_DISABLE | ADC_INJ_InitStruct->TrigAuto ); } - + MODIFY_REG(ADCx->JSQR, - ADC_JSQR_JEXTSEL + ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | ADC_JSQR_JL - , - ADC_INJ_InitStruct->TriggerSource + , + ADC_INJ_InitStruct->TriggerSource | ADC_INJ_InitStruct->SequencerLength ); }
diff --git a/Src/stm32wbxx_ll_comp.c b/Src/stm32wbxx_ll_comp.c index e3974a2..772ae4c 100644 --- a/Src/stm32wbxx_ll_comp.c +++ b/Src/stm32wbxx_ll_comp.c
@@ -31,7 +31,7 @@ * @{ */ - +#if defined (COMP1) || defined (COMP2) /** @addtogroup COMP_LL COMP * @{ @@ -245,7 +245,7 @@ * @} */ - +#endif /* COMP1 || COMP2 */ /** * @}
diff --git a/Src/stm32wbxx_ll_exti.c b/Src/stm32wbxx_ll_exti.c index 0556fec..10e79c2 100644 --- a/Src/stm32wbxx_ll_exti.c +++ b/Src/stm32wbxx_ll_exti.c
@@ -90,19 +90,19 @@ LL_EXTI_WriteReg(SWIER1, 0x00000000U); /* Pending register set to default reset values */ - LL_EXTI_WriteReg(PR1, EXTI_PR1_PIF_Msk); + LL_EXTI_WriteReg(PR1, 0xFFFFFFFFu); /* Rising Trigger selection register 2 set to default reset values */ - LL_EXTI_WriteReg(RTSR2, 0x00000000U); + LL_EXTI_WriteReg(RTSR2, 0x00000000U); /* Falling Trigger selection register 2 set to default reset values */ - LL_EXTI_WriteReg(FTSR2, 0x00000000U); + LL_EXTI_WriteReg(FTSR2, 0x00000000U); /* Software interrupt event register 2 set to default reset values */ - LL_EXTI_WriteReg(SWIER2, 0x00000000U); + LL_EXTI_WriteReg(SWIER2, 0x00000000U); /* Pending register 2 set to default reset values */ - LL_EXTI_WriteReg(PR2, EXTI_PR2_PIF_Msk); + LL_EXTI_WriteReg(PR2, 0xFFFFFFFFu); /* Interrupt mask register set to default reset values */ LL_EXTI_WriteReg(IMR1, 0x00000000U);
diff --git a/Src/stm32wbxx_ll_i2c.c b/Src/stm32wbxx_ll_i2c.c index 2c04e04..c19c719 100644 --- a/Src/stm32wbxx_ll_i2c.c +++ b/Src/stm32wbxx_ll_i2c.c
@@ -99,6 +99,7 @@ /* Release reset of I2C clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1); } +#if defined(I2C3) else if (I2Cx == I2C3) { /* Force reset of I2C clock */ @@ -107,6 +108,7 @@ /* Release reset of I2C clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3); } +#endif else { status = ERROR;
diff --git a/Src/stm32wbxx_ll_lpuart.c b/Src/stm32wbxx_ll_lpuart.c index df625ee..6f44fd2 100644 --- a/Src/stm32wbxx_ll_lpuart.c +++ b/Src/stm32wbxx_ll_lpuart.c
@@ -22,11 +22,11 @@ #include "stm32wbxx_ll_lpuart.h" #include "stm32wbxx_ll_rcc.h" #include "stm32wbxx_ll_bus.h" -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32WBxx_LL_Driver * @{ @@ -58,17 +58,17 @@ /* Check of parameters for configuration of LPUART registers */ #define IS_LL_LPUART_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPUART_PRESCALER_DIV1) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV2) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV4) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV6) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV8) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV10) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV12) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV16) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV32) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV64) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV128) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV256)) + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV6) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV10) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV12) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV128) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV256)) /* __BAUDRATE__ Depending on constraints applicable for LPUART BRR register */ /* value : */ @@ -85,25 +85,25 @@ #define IS_LL_LPUART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x000FFFFFU) #define IS_LL_LPUART_DIRECTION(__VALUE__) (((__VALUE__) == LL_LPUART_DIRECTION_NONE) \ - || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \ - || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \ - || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX)) + || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \ + || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \ + || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX)) #define IS_LL_LPUART_PARITY(__VALUE__) (((__VALUE__) == LL_LPUART_PARITY_NONE) \ - || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \ - || ((__VALUE__) == LL_LPUART_PARITY_ODD)) + || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \ + || ((__VALUE__) == LL_LPUART_PARITY_ODD)) #define IS_LL_LPUART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_LPUART_DATAWIDTH_7B) \ - || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \ - || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B)) + || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \ + || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B)) #define IS_LL_LPUART_STOPBITS(__VALUE__) (((__VALUE__) == LL_LPUART_STOPBITS_1) \ - || ((__VALUE__) == LL_LPUART_STOPBITS_2)) + || ((__VALUE__) == LL_LPUART_STOPBITS_2)) #define IS_LL_LPUART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_LPUART_HWCONTROL_NONE) \ - || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \ - || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \ - || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS)) + || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \ + || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \ + || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS)) /** * @}
diff --git a/Src/stm32wbxx_ll_pwr.c b/Src/stm32wbxx_ll_pwr.c index 3043a45..d039338 100644 --- a/Src/stm32wbxx_ll_pwr.c +++ b/Src/stm32wbxx_ll_pwr.c
@@ -95,8 +95,10 @@ LL_PWR_WriteReg(PDCRB, PWR_PDCRB_RESET_VALUE); LL_PWR_WriteReg(PUCRC, PWR_PUCRC_RESET_VALUE); LL_PWR_WriteReg(PDCRC, PWR_PDCRC_RESET_VALUE); +#if defined(GPIOD) LL_PWR_WriteReg(PUCRD, PWR_PUCRD_RESET_VALUE); LL_PWR_WriteReg(PDCRD, PWR_PDCRD_RESET_VALUE); +#endif LL_PWR_WriteReg(PUCRE, PWR_PUCRE_RESET_VALUE); LL_PWR_WriteReg(PDCRE, PWR_PDCRE_RESET_VALUE); LL_PWR_WriteReg(PUCRH, PWR_PUCRH_RESET_VALUE); @@ -112,8 +114,10 @@ | LL_PWR_SCR_CCRPEF | LL_PWR_SCR_C802WUF | LL_PWR_SCR_CBLEWUF +#if defined(PWR_CR5_SMPSEN) | LL_PWR_SCR_CBORHF | LL_PWR_SCR_CSMPSFBF +#endif | LL_PWR_SCR_CWUF );
diff --git a/Src/stm32wbxx_ll_rcc.c b/Src/stm32wbxx_ll_rcc.c index 0abf0a6..1a964c4 100644 --- a/Src/stm32wbxx_ll_rcc.c +++ b/Src/stm32wbxx_ll_rcc.c
@@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - * <h2><center>© Copyright (c) 2019 STMicroelectronics. + * <h2><center>© Copyright (c) 2019 STMicroelectronics. * All rights reserved.</center></h2> * * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -42,23 +42,33 @@ /** @addtogroup RCC_LL_Private_Macros * @{ */ -#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE)) +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_USART1_CLKSOURCE) -#define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE)) +#if defined(LPUART1) +#define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE) +#endif +#if defined(I2C3) #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE)) +#else +#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) +#endif #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE)) +#if defined(SAI1) #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) +#endif #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE)) #define IS_LL_RCC_CLK48_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CLK48_CLKSOURCE)) +#if defined(USB) #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE)) +#endif #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE)) @@ -75,9 +85,11 @@ uint32_t RCC_PLL_GetFreqDomain_ADC(void); uint32_t RCC_PLL_GetFreqDomain_48M(void); +#if defined(SAI1) uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void); uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void); uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void); +#endif uint32_t RCC_GetSystemClockFreq(void); @@ -142,42 +154,49 @@ /* Reset CFGR register */ LL_RCC_WriteReg(CFGR, 0x00070000U); /* MSI selected as System Clock and all prescaler to not divided */ - /* Reset CR register */ - vl_mask = 0xFFFFFFFFU; - /* Reset HSION, HSIKERON, HSIASFS, HSEON, PLLSYSON bits */ - CLEAR_BIT(vl_mask, (RCC_CR_HSION | RCC_CR_HSIASFS | RCC_CR_HSIKERON | RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_HSEPRE | RCC_CR_PLLON | RCC_CR_PLLSAI1ON)); + /* Wait for MSI oscillator used as system clock */ + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_MSI) + {} /* Write new mask in CR register */ - LL_RCC_WriteReg(CR, vl_mask); + LL_RCC_WriteReg(CR, 0x00000061); /* Wait for PLL READY bit to be reset */ - while(LL_RCC_PLL_IsReady() != 0U) + while (LL_RCC_PLL_IsReady() != 0U) {} /* Reset PLLCFGR register */ LL_RCC_WriteReg(PLLCFGR, 0x22041000U); +#if defined(SAI1) /* Wait for PLLSAI READY bit to be reset */ - while(LL_RCC_PLLSAI1_IsReady() != 0U) + while (LL_RCC_PLLSAI1_IsReady() != 0U) {} /* Reset PLLSAI1CFGR register */ LL_RCC_WriteReg(PLLSAI1CFGR, 0x22041000U); +#endif /* Disable all interrupts */ LL_RCC_WriteReg(CIER, 0x00000000U); /* Clear all interrupt flags */ - vl_mask = RCC_CICR_LSI1RDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | RCC_CICR_PLLSAI1RDYC |\ +#if defined(SAI1) + vl_mask = RCC_CICR_LSI1RDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | RCC_CICR_PLLSAI1RDYC | \ RCC_CICR_CSSC | RCC_CICR_HSI48RDYC | RCC_CICR_LSECSSC | RCC_CICR_LSI2RDYC; - +#else + vl_mask = RCC_CICR_LSI1RDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | \ + RCC_CICR_CSSC | RCC_CICR_HSI48RDYC | RCC_CICR_LSECSSC | RCC_CICR_LSI2RDYC; +#endif LL_RCC_WriteReg(CICR, vl_mask); /* Clear reset flags */ LL_RCC_ClearResetFlags(); +#if defined(RCC_SMPS_SUPPORT) /* SMPS reset */ LL_RCC_WriteReg(SMPSCR, 0x00000301U); /* MSI default clock source */ +#endif /* RF Wakeup Clock Source selection */ LL_RCC_SetRFWKPClockSource(LL_RCC_RFWKP_CLKSOURCE_NONE); @@ -254,6 +273,7 @@ RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK1_Frequency); } +#if defined(RCC_SMPS_SUPPORT) /** * @brief Return SMPS clock frequency * @note This function is only applicable when CPU runs, @@ -268,8 +288,8 @@ uint32_t smps_frequency; uint32_t smps_prescaler_index = ((LL_RCC_GetSMPSPrescaler()) >> RCC_SMPSCR_SMPSDIV_Pos); uint32_t smpsClockSource = LL_RCC_GetSMPSClockSource(); - - if(smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_HSI)/* SMPS Clock source is HSI Osc. */ + + if (smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_HSI) /* SMPS Clock source is HSI Osc. */ { if (LL_RCC_HSI_IsReady() == 1U) { @@ -280,7 +300,7 @@ smps_frequency = LL_RCC_PERIPH_FREQUENCY_NO; } } - else if( smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_HSE) /* SMPS Clock source is HSE Osc. */ + else if (smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_HSE) /* SMPS Clock source is HSE Osc. */ { if (LL_RCC_HSE_IsReady() == 1U) { @@ -291,11 +311,11 @@ smps_frequency = LL_RCC_PERIPH_FREQUENCY_NO; } } - else if( smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_MSI) /* SMPS Clock source is MSI Osc. */ + else if (smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_MSI) /* SMPS Clock source is MSI Osc. */ { uint32_t msiRange = LL_RCC_MSI_GetRange(); - - if(msiRange == LL_RCC_MSIRANGE_8) + + if (msiRange == LL_RCC_MSIRANGE_8) { smps_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_8) / SmpsPrescalerTable[smps_prescaler_index][4]; } @@ -330,6 +350,7 @@ return smps_frequency; } +#endif /** * @brief Return USARTx clock frequency @@ -411,6 +432,7 @@ break; } } +#if defined(I2C3) else { /* I2C3 CLK clock frequency */ @@ -433,11 +455,12 @@ break; } } +#endif return i2c_frequency; } - +#if defined(LPUART1) /** * @brief Return LPUARTx clock frequency * @param LPUARTxSource This parameter can be one of the following values: @@ -481,6 +504,7 @@ return lpuart_frequency; } +#endif /** * @brief Return LPTIMx clock frequency @@ -566,6 +590,7 @@ return lptim_frequency; } +#if defined(SAI1) /** * @brief Return SAIx clock frequency * @param SAIxSource This parameter can be one of the following values: @@ -611,6 +636,7 @@ } return sai_frequency; } +#endif /** * @brief Return CLK48x clock frequency @@ -627,14 +653,16 @@ assert_param(IS_LL_RCC_CLK48_CLKSOURCE(CLK48xSource)); /* CLK48CLK clock frequency */ - switch (LL_RCC_GetUSBClockSource(CLK48xSource)) + switch (LL_RCC_GetCLK48ClockSource(CLK48xSource)) { +#if defined(SAI1) case LL_RCC_CLK48_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as CLK48 clock source */ if (LL_RCC_PLLSAI1_IsReady() == 1U) { clk48_frequency = RCC_PLLSAI1_GetFreqDomain_48M(); } break; +#endif case LL_RCC_CLK48_CLKSOURCE_PLL: /* PLL clock used as CLK48 clock source */ if (LL_RCC_PLL_IsReady() == 1U) @@ -662,6 +690,7 @@ return clk48_frequency; } +#if defined(USB) /** * @brief Return USBx clock frequency * @param USBxSource This parameter can be one of the following values: @@ -673,6 +702,7 @@ { return LL_RCC_GetCLK48ClockFreq(USBxSource); } +#endif /** * @brief Return RNGx clock frequency @@ -685,12 +715,12 @@ { uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO; uint32_t rngClockSource = LL_RCC_GetRNGClockSource(RNGxSource); - + /* Check parameter */ assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource)); /* RNGCLK clock frequency */ - if(rngClockSource == LL_RCC_RNG_CLKSOURCE_LSI) /* LSI clock used as RNG clock source */ + if (rngClockSource == LL_RCC_RNG_CLKSOURCE_LSI) /* LSI clock used as RNG clock source */ { const uint32_t temp_lsi1Status = LL_RCC_LSI1_IsReady(); const uint32_t temp_lsi2Status = LL_RCC_LSI2_IsReady(); @@ -699,7 +729,7 @@ rng_frequency = LSI_VALUE; } } - else if(rngClockSource == LL_RCC_RNG_CLKSOURCE_LSE) /* LSE clock used as RNG clock source */ + else if (rngClockSource == LL_RCC_RNG_CLKSOURCE_LSE) /* LSE clock used as RNG clock source */ { if (LL_RCC_LSE_IsReady() == 1U) { @@ -709,7 +739,7 @@ else /* CLK48 clock used as RNG clock source */ { /* Systematic Div by 3 */ - rng_frequency = LL_RCC_GetCLK48ClockFreq(LL_RCC_CLK48_CLKSOURCE)/ 3U; + rng_frequency = LL_RCC_GetCLK48ClockFreq(LL_RCC_CLK48_CLKSOURCE) / 3U; } return rng_frequency; } @@ -732,12 +762,14 @@ /* ADCCLK clock frequency */ switch (LL_RCC_GetADCClockSource(ADCxSource)) { +#if defined(SAI1) case LL_RCC_ADC_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as ADC clock source */ if (LL_RCC_PLLSAI1_IsReady() == 1U) { adc_frequency = RCC_PLLSAI1_GetFreqDomain_ADC(); } break; +#endif case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */ adc_frequency = RCC_GetSystemClockFreq(); @@ -1023,6 +1055,7 @@ LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR()); } +#if defined(SAI1) /** * @brief Return PLL clock (PLLPCLK) frequency used for SAI domain * @retval PLLPCLK clock frequency (in Hz) @@ -1064,6 +1097,7 @@ return __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP()); } +#endif /** * @brief Return PLL clock (PLLPCLK) frequency used for ADC domain @@ -1089,14 +1123,14 @@ break; case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - if (LL_RCC_HSE_IsEnabledDiv2() == 1U) - { - pllinputfreq = HSE_VALUE / 2U; - } - else - { - pllinputfreq = HSE_VALUE; - } + if (LL_RCC_HSE_IsEnabledDiv2() == 1U) + { + pllinputfreq = HSE_VALUE / 2U; + } + else + { + pllinputfreq = HSE_VALUE; + } break; @@ -1133,14 +1167,14 @@ break; case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - if (LL_RCC_HSE_IsEnabledDiv2() == 1U) - { - pllinputfreq = HSE_VALUE / 2U; - } - else - { - pllinputfreq = HSE_VALUE; - } + if (LL_RCC_HSE_IsEnabledDiv2() == 1U) + { + pllinputfreq = HSE_VALUE / 2U; + } + else + { + pllinputfreq = HSE_VALUE; + } break; @@ -1152,6 +1186,7 @@ LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ()); } +#if defined(SAI1) /** * @brief Return PLLSAI1 clock (PLLSAI1PCLK) frequency used for SAI domain * @retval PLLSAI1PCLK clock frequency (in Hz) @@ -1175,14 +1210,14 @@ break; case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */ - if (LL_RCC_HSE_IsEnabledDiv2() == 1U) - { - pllinputfreq = HSE_VALUE / 2U; - } - else - { - pllinputfreq = HSE_VALUE; - } + if (LL_RCC_HSE_IsEnabledDiv2() == 1U) + { + pllinputfreq = HSE_VALUE / 2U; + } + else + { + pllinputfreq = HSE_VALUE; + } break; @@ -1217,14 +1252,14 @@ break; case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */ - if (LL_RCC_HSE_IsEnabledDiv2() == 1U) - { - pllinputfreq = HSE_VALUE / 2U; - } - else - { - pllinputfreq = HSE_VALUE; - } + if (LL_RCC_HSE_IsEnabledDiv2() == 1U) + { + pllinputfreq = HSE_VALUE / 2U; + } + else + { + pllinputfreq = HSE_VALUE; + } break; default: @@ -1275,7 +1310,7 @@ return __LL_RCC_CALC_PLLSAI1_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetR()); } - +#endif /** * @}
diff --git a/Src/stm32wbxx_ll_spi.c b/Src/stm32wbxx_ll_spi.c index a021a33..8d8c422 100644 --- a/Src/stm32wbxx_ll_spi.c +++ b/Src/stm32wbxx_ll_spi.c
@@ -59,52 +59,52 @@ /** @defgroup SPI_LL_Private_Macros SPI Private Macros * @{ */ -#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \ - || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \ - || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \ - || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX)) +#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \ + || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \ + || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \ + || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX)) #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \ - || ((__VALUE__) == LL_SPI_MODE_SLAVE)) + || ((__VALUE__) == LL_SPI_MODE_SLAVE)) -#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT)) +#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT)) #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \ - || ((__VALUE__) == LL_SPI_POLARITY_HIGH)) + || ((__VALUE__) == LL_SPI_POLARITY_HIGH)) #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \ - || ((__VALUE__) == LL_SPI_PHASE_2EDGE)) + || ((__VALUE__) == LL_SPI_PHASE_2EDGE)) -#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \ - || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \ - || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT)) +#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \ + || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \ + || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT)) -#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256)) +#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256)) #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \ - || ((__VALUE__) == LL_SPI_MSB_FIRST)) + || ((__VALUE__) == LL_SPI_MSB_FIRST)) #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \ - || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE)) + || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE)) #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
diff --git a/Src/stm32wbxx_ll_tim.c b/Src/stm32wbxx_ll_tim.c index ff13b61..a3f240a 100644 --- a/Src/stm32wbxx_ll_tim.c +++ b/Src/stm32wbxx_ll_tim.c
@@ -654,9 +654,9 @@ * and DTG[7:0] can be write-locked depending on the LOCK configuration, it * can be necessary to configure all of them during the first write access to * the TIMx_BDTR register. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. - * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a second break input. * @param TIMx Timer Instance * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
diff --git a/Src/stm32wbxx_ll_utils.c b/Src/stm32wbxx_ll_utils.c index 2202760..ec56897 100644 --- a/Src/stm32wbxx_ll_utils.c +++ b/Src/stm32wbxx_ll_utils.c
@@ -42,7 +42,9 @@ * @{ */ #define UTILS_MAX_FREQUENCY_SCALE1 64000000U /*!< Maximum frequency for system clock at power scale1, in Hz */ +#if defined(PWR_CR1_VOS) #define UTILS_MAX_FREQUENCY_SCALE2 16000000U /*!< Maximum frequency for system clock at power scale2, in Hz */ +#endif /* Defines used for PLL range */ #define UTILS_PLLVCO_INPUT_MIN 4000000U /*!< Frequency min for PLLVCO input, in Hz */ @@ -111,8 +113,12 @@ #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX)) +#if defined(PWR_CR1_VOS) #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \ ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2)) +#else +#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) +#endif #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \ || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) @@ -522,9 +528,11 @@ /* Flash Clock source (HCLK4) range in MHz with a VCORE is range1 */ const uint32_t UTILS_CLK_SRC_RANGE_VOS1[] = {18000000U, 36000000U, 54000000U, UTILS_MAX_FREQUENCY_SCALE1}; + #if defined(PWR_CR1_VOS) /* Flash Clock source (HCLK4) range in MHz with a VCORE is range2 */ const uint32_t UTILS_CLK_SRC_RANGE_VOS2[] = {6000000U, 12000000U, UTILS_MAX_FREQUENCY_SCALE2}; - + #endif + /* Flash Latency range */ const uint32_t UTILS_LATENCY_RANGE[] = {LL_FLASH_LATENCY_0, LL_FLASH_LATENCY_1, LL_FLASH_LATENCY_2, LL_FLASH_LATENCY_3}; @@ -535,6 +543,7 @@ } else { + #if defined(PWR_CR1_VOS) if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) { for(index = 0; index < countof(UTILS_CLK_SRC_RANGE_VOS1); index++) @@ -557,6 +566,16 @@ } } } + #else + for(index = 0; index < countof(UTILS_CLK_SRC_RANGE_VOS1); index++) + { + if(HCLK4_Frequency <= UTILS_CLK_SRC_RANGE_VOS1[index]) + { + latency = UTILS_LATENCY_RANGE[index]; + break; + } + } + #endif LL_FLASH_SetLatency(latency); @@ -617,12 +636,14 @@ /* PLL configuration cannot be modified */ status = ERROR; } +#if defined(SAI1) /* Check if PLLSAI1 is busy*/ if(LL_RCC_PLLSAI1_IsReady() != 0U) { /* PLLSAI1 configuration cannot be modified */ status = ERROR; } +#endif return status; }