Release v1.7.0
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index e57e823..41b79bd 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -7,7 +7,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -38,7 +38,6 @@
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
-
/**
* @}
*/
@@ -896,7 +895,7 @@
#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
-
+
/**
* @}
*/
@@ -1459,7 +1458,7 @@
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
-#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
@@ -1481,7 +1480,7 @@
#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
-#endif /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */
+#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
/**
* @}
*/
@@ -3252,7 +3251,7 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3381,7 +3380,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
diff --git a/Inc/stm32wbxx_hal_adc.h b/Inc/stm32wbxx_hal_adc.h
index 0968ba9..4c6992c 100644
--- a/Inc/stm32wbxx_hal_adc.h
+++ b/Inc/stm32wbxx_hal_adc.h
@@ -44,6 +44,9 @@
* @{
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC oversampling" not available on ADC peripheral of this STM32WB device */
+#else
/**
* @brief ADC group regular oversampling structure definition
*/
@@ -67,6 +70,7 @@
This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */
} ADC_OversamplingTypeDef;
+#endif
/**
* @brief Structure definition of ADC instance and ADC group regular.
@@ -131,6 +135,13 @@
use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start.
(in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
+#if defined(ADC_SUPPORT_2_5_MSPS)
+ FunctionalState LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
+ This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
+ This parameter can be set to ENABLE or DISABLE.
+ Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */
+
+#endif
FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
after the first ADC conversion start trigger occurred (software start or external trigger).
This parameter can be set to ENABLE or DISABLE. */
@@ -147,9 +158,13 @@
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
This parameter can be set to ENABLE or DISABLE. */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group regular number of discontinuous conversions" not available on ADC peripheral of this STM32WB device */
+#else
uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided.
If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
+#endif
uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start.
If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
@@ -176,12 +191,47 @@
overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
- Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ uint32_t SamplingTimeCommon1; /*!< Set sampling time common to a group of channels.
+ Unit: ADC clock cycles
+ Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+ Note: On this STM32 family, two different sampling time settings are available, each channel can use one of these two settings. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure.
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME_INST_SCOPE
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+ sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: few tens of microseconds). */
+
+ uint32_t SamplingTimeCommon2; /*!< Set sampling time common to a group of channels, second common setting possible.
+ Unit: ADC clock cycles
+ Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+ Note: On this STM32 family, two different sampling time settings are available, each channel can use one of these two settings. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure.
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME_INST_SCOPE
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+ sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: few tens of microseconds). */
+#endif
+
+#if !defined (ADC_SUPPORT_2_5_MSPS)
FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled.
This parameter can be set to ENABLE or DISABLE.
- Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */
+ Note: This parameter can be modified only if there is no conversion is ongoing on ADC group regular. */
ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters.
Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
+#endif
+
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ uint32_t TriggerFrequencyMode; /*!< Set ADC trigger frequency mode.
+ This parameter can be a value of @ref ADC_HAL_EC_REG_TRIGGER_FREQ.
+ Note: ADC trigger frequency mode must be set to low frequency when
+ a duration is exceeded before ADC conversion start trigger event
+ (between ADC enable and ADC conversion start trigger event
+ or between two ADC conversion start trigger event).
+ Duration value: Refer to device datasheet, parameter "tIdle".
+ Note: When ADC trigger frequency mode is set to low frequency,
+ some rearm cycles are inserted before performing ADC conversion
+ start, inducing a delay of 2 ADC clock cycles. */
+#endif
} ADC_InitTypeDef;
@@ -253,7 +303,7 @@
{
uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel.
For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
- For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
+ For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel). Note: Analog Watchdog 2 and 3 are not available on devices: STM32WB10xx, STM32WB15xx.
This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */
uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels.
@@ -367,7 +417,11 @@
HAL_LockTypeDef Lock; /*!< ADC locking object */
__IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
__IO uint32_t ErrorCode; /*!< ADC Error code */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ uint32_t ADCGroupRegularSequencerRanks; /*!< ADC group regular sequencer memorization of ranks setting, used in mode "fully configurable" (refer to parameter 'ScanConvMode') */
+#else
ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */
+#endif
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */
void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */
@@ -474,7 +528,7 @@
* @{
*/
#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
-#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
+#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
/**
* @}
*/
@@ -482,8 +536,33 @@
/** @defgroup ADC_Scan_mode ADC sequencer scan mode
* @{
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Note: On STM32WB10xx, STM32WB15xx devices, ADC group regular sequencer */
+/* both modes "fully configurable" or "not fully configurable" are */
+/* available. */
+/* Scan mode values must be compatible with other STM32 devices having */
+/* a configurable sequencer. */
+/* Scan direction setting values are defined by taking in account */
+/* already defined values for other STM32 devices: */
+/* ADC_SCAN_DISABLE (0x00000000UL) */
+/* ADC_SCAN_ENABLE (0x00000001UL) */
+/* Sequencer fully configurable with only rank 1 enabled is considered */
+/* as default setting equivalent to scan enable. */
+/* In case of migration from another STM32 device, the user will be */
+/* warned of change of setting choices with assert check. */
+#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Sequencer set to fully configurable: only the rank 1 is enabled (no scan sequence on several ranks) */
+#define ADC_SCAN_ENABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer set to fully configurable: sequencer length and each rank affectation to a channel are configurable. */
+
+#define ADC_SCAN_SEQ_FIXED (ADC_SCAN_SEQ_FIXED_INT) /*!< Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction forward: from channel 0 to channel 18 */
+#define ADC_SCAN_SEQ_FIXED_BACKWARD (ADC_SCAN_SEQ_FIXED_INT | ADC_CFGR1_SCANDIR) /*!< Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction backward: from channel 18 to channel 0 */
+
+#define ADC_SCAN_DIRECTION_FORWARD (ADC_SCAN_SEQ_FIXED) /* For compatibility with other STM32 devices */
+#define ADC_SCAN_DIRECTION_BACKWARD (ADC_SCAN_SEQ_FIXED_BACKWARD) /* For compatibility with other STM32 devices */
+
+#else
#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */
#define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @}
*/
@@ -493,6 +572,14 @@
*/
/* ADC group regular trigger sources for all ADC instances */
#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T2_CC4 (LL_ADC_REG_TRIG_EXT_TIM2_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T2_CC3 (LL_ADC_REG_TRIG_EXT_TIM2_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
+#else
#define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
@@ -501,6 +588,7 @@
#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
+#endif
/**
* @}
*/
@@ -537,6 +625,19 @@
/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
* @{
*/
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define ADC_RANK_CHANNEL_NUMBER (0x00000001U) /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */
+#define ADC_RANK_NONE (0x00000002U) /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Disable the selected rank (selected channel) from sequencer */
+
+#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */
+#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */
+#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */
+#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */
+#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */
+#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */
+#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */
+#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */
+#else
#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */
#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */
#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */
@@ -553,10 +654,36 @@
#define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */
#define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */
#define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */
+#endif
/**
* @}
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME ADC instance - Sampling time common to a group of channels
+ * @{
+ */
+#define ADC_SAMPLINGTIME_COMMON_1 (LL_ADC_SAMPLINGTIME_COMMON_1) /*!< Set sampling time common to a group of channels: sampling time nb 1 */
+#define ADC_SAMPLINGTIME_COMMON_2 (LL_ADC_SAMPLINGTIME_COMMON_2) /*!< Set sampling time common to a group of channels: sampling time nb 2 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME_INST_SCOPE Channel - Sampling time (ADC instance scope for sampling time common 1 or 2, not channel wise)
+ * @{
+ */
+#define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycle */
+#define ADC_SAMPLETIME_3CYCLES_5 (LL_ADC_SAMPLINGTIME_3CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles */
+#define ADC_SAMPLETIME_7CYCLES_5 (LL_ADC_SAMPLINGTIME_7CYCLES_5) /*!< Sampling time 7.5 ADC clock cycles */
+#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */
+#define ADC_SAMPLETIME_19CYCLES_5 (LL_ADC_SAMPLINGTIME_19CYCLES_5) /*!< Sampling time 19.5 ADC clock cycles */
+#define ADC_SAMPLETIME_39CYCLES_5 (LL_ADC_SAMPLINGTIME_39CYCLES_5) /*!< Sampling time 39.5 ADC clock cycles */
+#define ADC_SAMPLETIME_79CYCLES_5 (LL_ADC_SAMPLINGTIME_79CYCLES_5) /*!< Sampling time 79.5 ADC clock cycles */
+#define ADC_SAMPLETIME_160CYCLES_5 (LL_ADC_SAMPLINGTIME_160CYCLES_5) /*!< Sampling time 160.5 ADC clock cycles */
+/**
+ * @}
+ */
+#else
/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
* @{
*/
@@ -571,6 +698,7 @@
/**
* @}
*/
+#endif
/** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number
* @{
@@ -607,8 +735,12 @@
* @{
*/
#define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC analog watchdog 2 and 3" not available on ADC peripheral of this STM32WB device */
+#else
#define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */
#define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */
+#endif
/**
* @}
*/
@@ -627,6 +759,9 @@
* @}
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC oversampling" not available on ADC peripheral of this STM32WB device */
+#else
/** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio
* @{
*/
@@ -657,6 +792,7 @@
/**
* @}
*/
+#endif
/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
* @{
@@ -676,6 +812,17 @@
* @}
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/** @defgroup ADC_HAL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode
+ * @{
+ */
+#define ADC_TRIGGER_FREQ_HIGH (LL_ADC_TRIGGER_FREQ_HIGH) /*!< ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
+#define ADC_TRIGGER_FREQ_LOW (LL_ADC_TRIGGER_FREQ_LOW) /*!< ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
+/**
+ * @}
+ */
+#endif
+
/** @defgroup ADC_Event_type ADC Event type
* @{
@@ -685,7 +832,9 @@
#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */
#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */
#define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */
+#if !defined (ADC_SUPPORT_2_5_MSPS)
#define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
+#endif
/**
* @}
*/
@@ -699,12 +848,17 @@
#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */
#define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */
#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC end of calibration interrupt source */
+#define ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC channel configuration ready interrupt source */
+#else
#define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */
#define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */
+#define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */
+#endif
#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */
#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */
-#define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */
#define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */
@@ -720,13 +874,17 @@
#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
#define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */
#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC end of calibration flag */
+#define ADC_FLAG_CCRDY ADC_ISR_CCRDY /*!< ADC channel configuration ready flag */
+#else
#define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */
#define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */
+#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */
+#endif
#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */
#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */
#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
-#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */
-
/**
* @}
*/
@@ -781,7 +939,11 @@
* @param __LENGTH__ number of programmed conversions.
* @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large)
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (8UL)))
+#else
#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
+#endif
/**
@@ -863,6 +1025,15 @@
* @param __REGTRIG__ programmed ADC regular conversions external trigger.
* @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid)
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC4) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC4) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \
+ ((__REGTRIG__) == ADC_SOFTWARE_START) )
+#else
#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
@@ -872,6 +1043,7 @@
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
((__REGTRIG__) == ADC_SOFTWARE_START) )
+#endif
/**
* @brief Verify the ADC regular conversions check for converted data availability.
@@ -889,11 +1061,26 @@
#define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \
((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) )
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define IS_ADC_SAMPLING_TIME_COMMON(SAMPLING_TIME_COMMON) (((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_1) || \
+ ((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_2) )
+#endif
+
/**
* @brief Verify the ADC conversions sampling time.
* @param __TIME__ ADC conversions sampling time.
* @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid)
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_1CYCLE_5) || \
+ ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5) || \
+ ((__TIME__) == ADC_SAMPLETIME_7CYCLES_5) || \
+ ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \
+ ((__TIME__) == ADC_SAMPLETIME_19CYCLES_5) || \
+ ((__TIME__) == ADC_SAMPLETIME_39CYCLES_5) || \
+ ((__TIME__) == ADC_SAMPLETIME_79CYCLES_5) || \
+ ((__TIME__) == ADC_SAMPLETIME_160CYCLES_5) )
+#else
#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \
@@ -902,28 +1089,45 @@
((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) )
+#endif
+
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define IS_ADC_REGULAR_RANK_SEQ_FIXED(RANK) (((RANK) == ADC_RANK_CHANNEL_NUMBER) || \
+ ((RANK) == ADC_RANK_NONE) )
+#endif
/**
* @brief Verify the ADC regular channel setting.
- * @param __CHANNEL__ programmed ADC regular channel.
- * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+ * @param RANK programmed ADC regular channel.
+ * @retval SET (RANK is valid) or RESET (RANK is invalid)
*/
-#define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_16) )
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) == ADC_REGULAR_RANK_1 ) || \
+ ((RANK) == ADC_REGULAR_RANK_2 ) || \
+ ((RANK) == ADC_REGULAR_RANK_3 ) || \
+ ((RANK) == ADC_REGULAR_RANK_4 ) || \
+ ((RANK) == ADC_REGULAR_RANK_5 ) || \
+ ((RANK) == ADC_REGULAR_RANK_6 ) || \
+ ((RANK) == ADC_REGULAR_RANK_7 ) || \
+ ((RANK) == ADC_REGULAR_RANK_8 ) )
+#else
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) == ADC_REGULAR_RANK_1 ) || \
+ ((RANK) == ADC_REGULAR_RANK_2 ) || \
+ ((RANK) == ADC_REGULAR_RANK_3 ) || \
+ ((RANK) == ADC_REGULAR_RANK_4 ) || \
+ ((RANK) == ADC_REGULAR_RANK_5 ) || \
+ ((RANK) == ADC_REGULAR_RANK_6 ) || \
+ ((RANK) == ADC_REGULAR_RANK_7 ) || \
+ ((RANK) == ADC_REGULAR_RANK_8 ) || \
+ ((RANK) == ADC_REGULAR_RANK_9 ) || \
+ ((RANK) == ADC_REGULAR_RANK_10) || \
+ ((RANK) == ADC_REGULAR_RANK_11) || \
+ ((RANK) == ADC_REGULAR_RANK_12) || \
+ ((RANK) == ADC_REGULAR_RANK_13) || \
+ ((RANK) == ADC_REGULAR_RANK_14) || \
+ ((RANK) == ADC_REGULAR_RANK_15) || \
+ ((RANK) == ADC_REGULAR_RANK_16) )
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @}
@@ -950,6 +1154,10 @@
/* Unit: us */
#define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US)
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define ADC_SCAN_SEQ_FIXED_INT 0x80000000U /* Internal definition to differentiate sequencer setting fixed or configurable */
+#endif
+
/**
* @}
*/
@@ -994,10 +1202,12 @@
* @arg @ref ADC_IT_OVR ADC overrun interrupt source
* @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
* @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
+ * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
* @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
* @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
- * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @retval None
*/
#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
@@ -1015,10 +1225,12 @@
* @arg @ref ADC_IT_OVR ADC overrun interrupt source
* @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
* @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
+ * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
* @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
* @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
- * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @retval None
*/
#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
@@ -1033,12 +1245,14 @@
* @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
* @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
* @arg @ref ADC_IT_OVR ADC overrun interrupt source
- * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
- * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
+ * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source (1)
+ * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source (1)
+ * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source (1)
* @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
* @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
- * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @retval State of interruption (SET or RESET)
*/
#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
@@ -1054,12 +1268,14 @@
* @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
* @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
* @arg @ref ADC_FLAG_OVR ADC overrun flag
- * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag
- * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
+ * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag (1)
+ * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag (1)
+ * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag (1)
* @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
* @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
* @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
- * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @retval State of flag (TRUE or FALSE).
*/
#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
@@ -1075,12 +1291,14 @@
* @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
* @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
* @arg @ref ADC_FLAG_OVR ADC overrun flag
- * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag
- * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
+ * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag (1)
+ * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag (1)
+ * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag (1)
* @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
* @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
* @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
- * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @retval None
*/
/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
diff --git a/Inc/stm32wbxx_hal_adc_ex.h b/Inc/stm32wbxx_hal_adc_ex.h
index 2bf99de..59864e5 100644
--- a/Inc/stm32wbxx_hal_adc_ex.h
+++ b/Inc/stm32wbxx_hal_adc_ex.h
@@ -41,6 +41,9 @@
* @{
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/**
* @brief ADC Injected Conversion Oversampling structure definition
*/
@@ -170,6 +173,7 @@
Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled.
Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
} ADC_InjectionConfTypeDef;
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @}
@@ -181,6 +185,9 @@
* @{
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source
* @{
*/
@@ -206,12 +213,15 @@
/**
* @}
*/
+#endif /* ADC_SUPPORT_2_5_MSPS */
/** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
* @{
*/
#define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
+#if !defined (ADC_SUPPORT_2_5_MSPS)
#define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
+#endif
/**
* @}
*/
@@ -228,6 +238,9 @@
* @}
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
* @{
*/
@@ -238,13 +251,18 @@
/**
* @}
*/
+#endif /* ADC_SUPPORT_2_5_MSPS */
/** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups
* @{
*/
#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
#define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/
#define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @}
*/
@@ -315,6 +333,9 @@
*/
#define ADC_IS_INDEPENDENT(__HANDLE__) (SET)
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/**
* @brief Set the selected injected Channel rank.
* @param __CHANNELNB__ Channel number.
@@ -336,6 +357,7 @@
* @retval None
*/
#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Configure ADC discontinuous conversion mode for regular group
@@ -365,6 +387,47 @@
*/
#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/**
+ * @brief Enable ADC overrun mode.
+ * @param _OVERRUN_MODE_ Overrun mode.
+ * @retval Overun bit setting to be programmed into CFGR register
+ */
+/* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */
+/* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */
+/* as the default case to be compliant with other STM32 devices. */
+#define ADC_CFGR_OVERRUN(_OVERRUN_MODE_) \
+ ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \
+ )? (ADC_CFGR1_OVRMOD) : (0x00000000UL) \
+ )
+
+/**
+ * @brief Enable the ADC auto off mode.
+ * @param _AUTOOFF_ Auto off bit enable or disable.
+ * @retval None
+ */
+#define ADC_CFGR_AUTOOFF(_AUTOOFF_) \
+ ((_AUTOOFF_) << 15UL)
+
+/**
+ * @brief Set ADC scan mode with differentiation of sequencer setting
+ * fixed or configurable
+ * @param _SCAN_MODE_ Scan conversion mode.
+ * @retval None
+ */
+/* Note: Scan mode set using this macro (instead of parameter direct set) */
+/* due to different modes on other STM32 devices: */
+/* if scan mode is disabled, sequencer is set to fully configurable */
+/* with setting of only rank 1 enabled afterwards. */
+#define ADC_SCAN_SEQ_MODE(_SCAN_MODE_) \
+ ( (((_SCAN_MODE_) & ADC_SCAN_SEQ_FIXED_INT) != 0UL \
+ )? \
+ ((_SCAN_MODE_) & (~ADC_SCAN_SEQ_FIXED_INT)) \
+ : \
+ (ADC_CFGR1_CHSELRMOD) \
+ )
+
+#endif
/**
* @brief Configure the ADC DMA continuous request.
* @param __DMACONTREQ_MODE__ DMA continuous request mode.
@@ -400,8 +463,13 @@
* @param __THRESHOLD__ Value to be shifted
* @retval None
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
+ ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3UL) * 2UL))
+#else
#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
+#endif
/**
* @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.
@@ -414,22 +482,38 @@
* @param __THRESHOLD__ Value to be shifted
* @retval None
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
+ ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) != (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0)) ? \
+ ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \
+ ((__THRESHOLD__) << 2UL) \
+ )
+#else
#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) ? \
((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \
((__THRESHOLD__) << 2UL) \
)
+#endif
/**
* @brief Clear Common Control Register.
* @param __HANDLE__ ADC handle.
* @retval None
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \
+ ADC_CCR_PRESC | \
+ ADC_CCR_VBATEN | \
+ ADC_CCR_TSEN | \
+ ADC_CCR_VREFEN )
+#else
#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \
ADC_CCR_PRESC | \
ADC_CCR_VBATEN | \
ADC_CCR_TSEN | \
ADC_CCR_VREFEN )
+#endif
/**
@@ -453,12 +537,16 @@
*/
#define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/**
* @brief Verify the length of scheduled injected conversions group.
* @param __LENGTH__ number of programmed conversions.
* @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large)
*/
#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Calibration factor size verification (7 bits maximum).
@@ -525,8 +613,12 @@
* @param __SING_DIFF__ programmed channel setting.
* @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) ((__SING_DIFF__) == ADC_SINGLE_ENDED)
+#else
#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \
((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) )
+#endif
/**
* @brief Verify the ADC offset management setting.
@@ -539,6 +631,9 @@
((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \
((__OFFSET_NUMBER__) == ADC_OFFSET_4) )
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/**
* @brief Verify the ADC injected channel setting.
* @param __CHANNEL__ programmed ADC injected channel.
@@ -572,21 +667,31 @@
((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \
((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \
((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Verify the ADC analog watchdog setting.
* @param __WATCHDOG__ programmed ADC analog watchdog setting.
* @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1)
+#else
#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) )
+#endif
/**
* @brief Verify the ADC analog watchdog mode setting.
* @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting.
* @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) )
+#else
#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
@@ -594,6 +699,12 @@
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
+#endif /* ADC_SUPPORT_2_5_MSPS */
+
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define IS_ADC_TRIGGER_FREQ(TRIGGER_FREQ) (((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_HIGH) || \
+ ((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_LOW) )
+#endif
/**
* @brief Verify the ADC conversion (regular or injected or both).
@@ -609,13 +720,24 @@
* @param __EVENT__ ADC event.
* @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \
+ ((__EVENT__) == ADC_AWD1_EVENT) || \
+ ((__EVENT__) == ADC_AWD2_EVENT) || \
+ ((__EVENT__) == ADC_AWD3_EVENT) || \
+ ((__EVENT__) == ADC_OVR_EVENT) )
+#else
#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \
((__EVENT__) == ADC_AWD_EVENT) || \
((__EVENT__) == ADC_AWD2_EVENT) || \
((__EVENT__) == ADC_AWD3_EVENT) || \
((__EVENT__) == ADC_OVR_EVENT) || \
((__EVENT__) == ADC_JQOVF_EVENT) )
+#endif /* ADC_SUPPORT_2_5_MSPS */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC oversampling" not available on ADC peripheral of this STM32WB device */
+#else
/**
* @brief Verify the ADC oversampling ratio.
* @param __RATIO__ programmed ADC oversampling ratio.
@@ -629,6 +751,7 @@
((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \
((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
+#endif
/**
* @brief Verify the ADC oversampling shift.
@@ -653,6 +776,8 @@
#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#else
/**
* @brief Verify the ADC oversampling regular conversion resumed or continued mode.
* @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode.
@@ -660,6 +785,7 @@
*/
#define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
+#endif
/**
* @brief Verify the DFSDM mode configuration.
@@ -702,6 +828,9 @@
HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
uint32_t CalibrationFactor);
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc);
@@ -710,21 +839,34 @@
/* Non-blocking mode: Interruption */
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);
+#endif /* ADC_SUPPORT_2_5_MSPS */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/* ADC retrieve conversion value intended to be used with polling or interruption */
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc);
+#endif /* ADC_SUPPORT_2_5_MSPS */
void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc);
void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc);
void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/* ADC group regular conversions stop */
HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc);
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @}
*/
@@ -733,11 +875,23 @@
* @{
*/
/* Peripheral Control functions ***********************************************/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,ADC_InjectionConfTypeDef* sConfigInjected);
+#endif /* ADC_SUPPORT_2_5_MSPS */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc);
+#endif /* ADC_SUPPORT_2_5_MSPS */
HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature " ADC deep power-down" not available on ADC peripheral of this STM32WB device */
+#else
HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc);
+#endif
/**
* @}
diff --git a/Inc/stm32wbxx_hal_comp.h b/Inc/stm32wbxx_hal_comp.h
index 914d080..defa4e7 100644
--- a/Inc/stm32wbxx_hal_comp.h
+++ b/Inc/stm32wbxx_hal_comp.h
@@ -181,7 +181,7 @@
/** @defgroup COMP_InputPlus COMP input plus (non-inverting input)
* @{
*/
-#define COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1 (except device STM32WB35xx), pin PB4 for COMP2) */
+#define COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1 (except device STM32WB35xx), pin PB4 for COMP2). Note: On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. */
#define COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */
#define COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1) /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2) */
/**
@@ -196,7 +196,7 @@
#define COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 3/4 VrefInt */
#define COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN ) /*!< Comparator input minus connected to VrefInt */
#define COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2) */
-#define COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1 (except device STM32WB35xx), pin PB7 for COMP2) */
+#define COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1 (except device STM32WB35xx), pin PB7 for COMP2). Note: On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. */
#define COMP_INPUT_MINUS_IO3 ( COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO3 (pin PA0 for COMP1, pin PA2 for COMP2) */
#define COMP_INPUT_MINUS_IO4 (COMP_CSR_INMESEL_1 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO4 (pin PA4 for COMP1, pin PA4 for COMP2) */
#define COMP_INPUT_MINUS_IO5 (COMP_CSR_INMESEL_1 | COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO5 (pin PA5 for COMP1, pin PA5 for COMP2) */
@@ -595,7 +595,7 @@
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3))
#endif
-/* Note: On this STM32 serie, comparator input minus parameters are */
+/* Note: On this STM32 series, comparator input minus parameters are */
/* the same on all COMP instances. */
/* However, comparator instance kept as macro parameter for */
/* compatibility with other STM32 families. */
diff --git a/Inc/stm32wbxx_hal_conf_template.h b/Inc/stm32wbxx_hal_conf_template.h
index 72c9b3b..8f947e5 100644
--- a/Inc/stm32wbxx_hal_conf_template.h
+++ b/Inc/stm32wbxx_hal_conf_template.h
@@ -44,7 +44,6 @@
#define HAL_GPIO_MODULE_ENABLED
#define HAL_HSEM_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
-#define HAL_I2S_MODULE_ENABLED
#define HAL_IPCC_MODULE_ENABLED
#define HAL_IRDA_MODULE_ENABLED
#define HAL_IWDG_MODULE_ENABLED
@@ -71,7 +70,6 @@
#define USE_HAL_COMP_REGISTER_CALLBACKS 0u
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0u
#define USE_HAL_I2C_REGISTER_CALLBACKS 0u
-#define USE_HAL_I2C_REGISTER_CALLBACKS 0u
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0u
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0u
#define USE_HAL_PCD_REGISTER_CALLBACKS 0u
@@ -159,15 +157,6 @@
#endif /* LSE_STARTUP_TIMEOUT */
/**
- * @brief External clock source for I2S peripheral
- * This value is used by the RCC HAL module to compute the I2S clock source
- * frequency.
- */
-#if !defined (EXTERNAL_CLOCK_VALUE)
-#define EXTERNAL_CLOCK_VALUE (48000UL) /*!< Value of the I2S External clock source in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/**
* @brief External clock source for SAI1 peripheral
* This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
* frequency.
@@ -254,10 +243,6 @@
#include "stm32wbxx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32wbxx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
#ifdef HAL_IPCC_MODULE_ENABLED
#include "stm32wbxx_hal_ipcc.h"
#endif /* HAL_IPCC_MODULE_ENABLED */
diff --git a/Inc/stm32wbxx_hal_cryp.h b/Inc/stm32wbxx_hal_cryp.h
index 62c8b2d..4dabd50 100644
--- a/Inc/stm32wbxx_hal_cryp.h
+++ b/Inc/stm32wbxx_hal_cryp.h
@@ -109,7 +109,7 @@
typedef struct
#endif
{
- AES_TypeDef *Instance; /*!< AES Register base address */
+ AES_TypeDef *Instance; /*!< AES Register base address */
CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */
@@ -120,13 +120,13 @@
uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
- __IO uint16_t CrypHeaderCount; /*!< Counter of header data */
+ __IO uint16_t CrypHeaderCount; /*!< Counter of header data in words */
- __IO uint16_t CrypInCount; /*!< Counter of input data */
+ __IO uint16_t CrypInCount; /*!< Counter of input data in words */
- __IO uint16_t CrypOutCount; /*!< Counter of output data */
+ __IO uint16_t CrypOutCount; /*!< Counter of output data in words */
- uint16_t Size; /*!< length of input data in words */
+ uint16_t Size; /*!< Length of input data */
uint32_t Phase; /*!< CRYP peripheral phase */
diff --git a/Inc/stm32wbxx_hal_exti.h b/Inc/stm32wbxx_hal_exti.h
index 2c12b6a..5f7ecc2 100644
--- a/Inc/stm32wbxx_hal_exti.h
+++ b/Inc/stm32wbxx_hal_exti.h
@@ -273,21 +273,21 @@
/** @defgroup EXTI_Private_Macros EXTI Private Macros
* @{
*/
-#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \
- ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
- (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
- (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
- (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
+#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \
+ ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
+ (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
+ (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
+ (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
(((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
-#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \
- (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))
+#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
+ (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
-#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
+#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
-#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)
+#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)
-#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
+#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
#if defined (STM32WB55xx) || defined (STM32WB5Mxx)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
diff --git a/Inc/stm32wbxx_hal_flash.h b/Inc/stm32wbxx_hal_flash.h
index 683e0f2..bdcd1bb 100644
--- a/Inc/stm32wbxx_hal_flash.h
+++ b/Inc/stm32wbxx_hal_flash.h
@@ -75,6 +75,7 @@
uint32_t UserConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER).
This parameter can be a combination of the values of
@ref FLASH_OB_USER_AGC_TRIM, @ref FLASH_OB_USER_BOR_LEVEL
+ @ref FLASH_OB_USER_RESET_CONFIG(*), @ref FLASH_OB_USER_INPUT_RESET_HOLDER(*)
@ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
@ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
@ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
@@ -280,6 +281,9 @@
#define OB_USER_nRST_STOP FLASH_OPTR_nRST_STOP /*!< Reset generated when entering the stop mode */
#define OB_USER_nRST_STDBY FLASH_OPTR_nRST_STDBY /*!< Reset generated when entering the standby mode */
#define OB_USER_nRST_SHDW FLASH_OPTR_nRST_SHDW /*!< Reset generated when entering the shutdown mode */
+#if defined(FLASH_OPTR_IRHEN)
+#define OB_USER_INPUT_RESET_HOLDER FLASH_OPTR_IRHEN /*!< Internal reset holder enable */
+#endif
#define OB_USER_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Independent watchdog selection */
#define OB_USER_IWDG_STOP FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter freeze in stop mode */
#define OB_USER_IWDG_STDBY FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter freeze in standby mode */
@@ -289,12 +293,24 @@
#define OB_USER_SRAM2RST FLASH_OPTR_SRAM2RST /*!< SRAM2 erase when system reset */
#define OB_USER_nSWBOOT0 FLASH_OPTR_nSWBOOT0 /*!< Software BOOT0 */
#define OB_USER_nBOOT0 FLASH_OPTR_nBOOT0 /*!< nBOOT0 option bit */
+#if defined(FLASH_OPTR_nRST_MODE)
+#define OB_USER_NRST_MODE FLASH_OPTR_nRST_MODE /*!< Reset pin configuration */
+#endif
#define OB_USER_AGC_TRIM FLASH_OPTR_AGC_TRIM /*!< Automatic Gain Control Trimming */
+#if defined(FLASH_OPTR_IRHEN) && defined(FLASH_OPTR_nRST_MODE)
+#define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \
+ OB_USER_nRST_SHDW | OB_USER_IWDG_SW | OB_USER_IWDG_STOP | \
+ OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | OB_USER_nBOOT1 | \
+ OB_USER_SRAM2PE | OB_USER_SRAM2RST | OB_USER_nSWBOOT0 | \
+ OB_USER_nBOOT0 | OB_USER_AGC_TRIM | OB_USER_NRST_MODE | \
+ OB_USER_INPUT_RESET_HOLDER) /*!< all option bits */
+#else
#define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \
OB_USER_nRST_SHDW | OB_USER_IWDG_SW | OB_USER_IWDG_STOP | \
OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | OB_USER_nBOOT1 | \
OB_USER_SRAM2PE | OB_USER_SRAM2RST | OB_USER_nSWBOOT0 | \
OB_USER_nBOOT0 | OB_USER_AGC_TRIM) /*!< all option bits */
+#endif
/**
* @}
@@ -435,6 +451,29 @@
* @}
*/
+#if defined(FLASH_OPTR_nRST_MODE)
+/** @defgroup FLASH_OB_USER_RESET_CONFIG FLASH Option Bytes User reset config bit
+ * @{
+ */
+#define OB_RESET_MODE_INPUT_ONLY FLASH_OPTR_nRST_MODE_0 /*!< Reset pin is in Reset input mode only */
+#define OB_RESET_MODE_GPIO FLASH_OPTR_nRST_MODE_1 /*!< Reset pin is in GPIO normal mode only */
+#define OB_RESET_MODE_INPUT_OUTPUT (FLASH_OPTR_nRST_MODE_0 | FLASH_OPTR_nRST_MODE_1) /*!< Reset pin is in Reset input and output mode */
+/**
+ * @}
+ */
+#endif
+
+#if defined(FLASH_OPTR_IRHEN)
+/** @defgroup FLASH_OB_USER_INPUT_RESET_HOLDER FLASH Option Bytes User input reset holder bit
+ * @{
+ */
+#define OB_IRH_ENABLE 0x00000000U /*!< Internal Reset handler enable */
+#define OB_IRH_DISABLE FLASH_OPTR_IRHEN /*!< Internal Reset handler disable */
+/**
+ * @}
+ */
+#endif
+
/** @defgroup FLASH_OB_PCROP_ZONE FLASH PCROP ZONE
* @{
*/
@@ -857,7 +896,7 @@
#define IS_FLASH_TYPEPROGRAM(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
((__VALUE__) == FLASH_TYPEPROGRAM_FAST))
-#define IS_OB_SFSA_START_ADDR(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= FLASH_END_ADDR) && (((__VALUE__) & ~(uint32_t)0xFFFU) == (__VALUE__)))
+#define IS_OB_SFSA_START_ADDR(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= FLASH_END_ADDR) && (((__VALUE__) & ~(uint32_t)(FLASH_PAGE_SIZE - 1U)) == (__VALUE__)))
#define IS_OB_SBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2A_BASE) && ((__VALUE__) <= (SRAM2A_BASE + SRAM2A_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__)))
#define IS_OB_SNBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2B_BASE) && ((__VALUE__) <= (SRAM2B_BASE + SRAM2B_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__)))
#define IS_OB_SECURE_MODE(__VALUE__) (((__VALUE__) == SYSTEM_IN_SECURE_MODE) || ((__VALUE__) == SYSTEM_NOT_IN_SECURE_MODE))
diff --git a/Inc/stm32wbxx_hal_i2c_ex.h b/Inc/stm32wbxx_hal_i2c_ex.h
index 1ae6f86..9cdef10 100644
--- a/Inc/stm32wbxx_hal_i2c_ex.h
+++ b/Inc/stm32wbxx_hal_i2c_ex.h
@@ -38,7 +38,6 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
* @{
*/
@@ -75,24 +74,51 @@
*/
/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
+/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
* @{
*/
-/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
- * @brief Extended features functions
+/** @addtogroup I2CEx_Exported_Functions_Group1 I2C Extended Filter Mode Functions
* @{
*/
-
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
+/**
+ * @}
+ */
+
+/** @addtogroup I2CEx_Exported_Functions_Group2 I2C Extended WakeUp Mode Functions
+ * @{
+ */
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
+/**
+ * @}
+ */
+
+/** @addtogroup I2CEx_Exported_Functions_Group3 I2C Extended FastModePlus Functions
+ * @{
+ */
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
@@ -118,9 +144,6 @@
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3))
-
-
-
/**
* @}
*/
@@ -142,14 +165,6 @@
* @}
*/
-/**
- * @}
- */
-
-/**
- * @}
- */
-
#ifdef __cplusplus
}
#endif
diff --git a/Inc/stm32wbxx_hal_pwr.h b/Inc/stm32wbxx_hal_pwr.h
index df07fd2..9ed9c4f 100644
--- a/Inc/stm32wbxx_hal_pwr.h
+++ b/Inc/stm32wbxx_hal_pwr.h
@@ -105,7 +105,9 @@
*/
#define PWR_LOWPOWERMODE_STOP0 (0x00000000u) /*!< Stop 0: stop mode with main regulator */
#define PWR_LOWPOWERMODE_STOP1 (PWR_CR1_LPMS_0) /*!< Stop 1: stop mode with low power regulator */
+#if defined(PWR_SUPPORT_STOP2)
#define PWR_LOWPOWERMODE_STOP2 (PWR_CR1_LPMS_1) /*!< Stop 2: stop mode with low power regulator and VDD12I interruptible digital core domain supply OFF (less peripherals activated than low power mode stop 1 to reduce power consumption)*/
+#endif
#define PWR_LOWPOWERMODE_STANDBY (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1) /*!< Standby mode */
#define PWR_LOWPOWERMODE_SHUTDOWN (PWR_CR1_LPMS_2) /*!< Shutdown mode */
/**
diff --git a/Inc/stm32wbxx_hal_pwr_ex.h b/Inc/stm32wbxx_hal_pwr_ex.h
index 612cfa2..0adc7c0 100644
--- a/Inc/stm32wbxx_hal_pwr_ex.h
+++ b/Inc/stm32wbxx_hal_pwr_ex.h
@@ -366,7 +366,9 @@
#endif
#define PWR_FLAG_PVDO (PWR_FLAG_REG_SR2 | PWR_SR2_PVDO_Pos) /*!< Power Voltage Detector output flag */
+#if defined(PWR_CR2_PVME1)
#define PWR_FLAG_PVMO1 (PWR_FLAG_REG_SR2 | PWR_SR2_PVMO1_Pos) /*!< Power Voltage Monitoring 1 output flag */
+#endif
#define PWR_FLAG_PVMO3 (PWR_FLAG_REG_SR2 | PWR_SR2_PVMO3_Pos) /*!< Power Voltage Monitoring 3 output flag */
/*------------------------------EXTSCR---------------------------*/
@@ -938,7 +940,9 @@
void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);
void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);
+#if defined(PWR_SUPPORT_STOP2)
void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry);
+#endif
void HAL_PWREx_EnterSHUTDOWNMode(void);
void HAL_PWREx_PVD_PVM_IRQHandler(void);
diff --git a/Inc/stm32wbxx_hal_rcc.h b/Inc/stm32wbxx_hal_rcc.h
index bb0d762..110a33d 100644
--- a/Inc/stm32wbxx_hal_rcc.h
+++ b/Inc/stm32wbxx_hal_rcc.h
@@ -59,23 +59,28 @@
* @{
*/
+#if defined(RCC_HSI48_SUPPORT)
+#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI1) == RCC_OSCILLATORTYPE_LSI1) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI2) == RCC_OSCILLATORTYPE_LSI2) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
+#else
#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI1) == RCC_OSCILLATORTYPE_LSI1) || \
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI2) == RCC_OSCILLATORTYPE_LSI2) || \
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
-
-
-#if defined(RCC_CR_HSEBYP)
-#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
- ((__HSE__) == RCC_HSE_BYPASS))
-#else
-#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON))
#endif
+
+#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON))
+
#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
((__LSE__) == RCC_LSE_BYPASS))
@@ -93,9 +98,9 @@
#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U)
-
+#if defined(RCC_HSI48_SUPPORT)
#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
-
+#endif
#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \
((__PLL__) == RCC_PLL_ON))
@@ -177,16 +182,28 @@
((__MCOX__) == RCC_MCO2))
#endif
+#if defined(RCC_HSI48_SUPPORT)
#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_LSI1) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_LSI2) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_LSI1) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_LSI2) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
+#else
+#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_LSI1) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_LSI2) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
+#endif
#define IS_RCC_MCO2SOURCE(__SOURCE__) IS_RCC_MCO1SOURCE((__SOURCE__))
#define IS_RCC_MCO3SOURCE(__SOURCE__) IS_RCC_MCO1SOURCE((__SOURCE__))
@@ -279,8 +296,10 @@
uint32_t MSIClockRange; /*!< The MSI frequency range.
This parameter can be a value of @ref RCC_MSI_Clock_Range */
+#if defined(RCC_HSI48_SUPPORT)
uint32_t HSI48State; /*!< The new state of the HSI48 .
This parameter can be a value of @ref RCC_HSI48_Config */
+#endif
RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */
@@ -342,7 +361,9 @@
#define RCC_OSCILLATORTYPE_LSI1 0x00000008U /*!< LSI1 to configure */
#define RCC_OSCILLATORTYPE_LSI2 0x00000010U /*!< LSI2 to configure */
#define RCC_OSCILLATORTYPE_MSI 0x00000020U /*!< MSI to configure */
+#if defined(RCC_HSI48_SUPPORT)
#define RCC_OSCILLATORTYPE_HSI48 0x00000040U /*!< HSI48 to configure */
+#endif
/**
* @}
*/
@@ -352,9 +373,6 @@
*/
#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */
#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
-#if defined(RCC_CR_HSEBYP)
-#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
-#endif
/**
* @}
*/
@@ -400,7 +418,7 @@
* @}
*/
-
+#if defined(RCC_HSI48_SUPPORT)
/** @defgroup RCC_HSI48_Config HSI48 Config
* @{
*/
@@ -409,7 +427,7 @@
/**
* @}
*/
-
+#endif
/** @defgroup RCC_PLL_Config PLL Config
* @{
@@ -523,9 +541,6 @@
#define RCC_PLL_SAI1CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI1CLK selection from main PLL */
#endif
#define RCC_PLL_ADCCLK RCC_PLLCFGR_PLLPEN /*!< PLLADCCLK selection from main PLL */
-#if defined(SPI_I2S_SUPPORT)
-#define RCC_PLL_I2SCLK RCC_PLLCFGR_PLLPEN /*!< PLLI2SCLK selection from main PLL */
-#endif
/**
* @}
*/
@@ -666,7 +681,9 @@
#define RCC_MCO1SOURCE_LSI1 LL_RCC_MCO1SOURCE_LSI1 /*!< LSI1 selection as MCO1 source */
#define RCC_MCO1SOURCE_LSI2 LL_RCC_MCO1SOURCE_LSI2 /*!< LSI2 selection as MCO1 source */
#define RCC_MCO1SOURCE_LSE LL_RCC_MCO1SOURCE_LSE /*!< LSE selection as MCO1 source */
+#if defined(RCC_HSI48_SUPPORT)
#define RCC_MCO1SOURCE_HSI48 LL_RCC_MCO1SOURCE_HSI48 /*!< HSI48 selection as MCO1 source */
+#endif
#define RCC_MCO1SOURCE_HSE_BEFORE_STAB LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB /*!< HSE before stabilization selection as MCO1 source */
/**
@@ -726,7 +743,9 @@
#endif
#define RCC_IT_HSECSS LL_RCC_CIFR_CSSF /*!< HSE Clock Security System Interrupt flag */
#define RCC_IT_LSECSS LL_RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
+#if defined(RCC_HSI48_SUPPORT)
#define RCC_IT_HSI48RDY LL_RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
+#endif
/**
* @}
*/
@@ -767,8 +786,9 @@
#define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */
/* Flags in the CRRCR register */
+#if defined(RCC_HSI48_SUPPORT)
#define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */
-
+#endif
/**
* @}
*/
@@ -850,8 +870,9 @@
#endif
#define __HAL_RCC_GPIOE_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOE)
#define __HAL_RCC_GPIOH_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOH)
-
+#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_ADC_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADC)
+#endif
#if defined(AES1)
#define __HAL_RCC_AES1_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_AES1)
#endif
@@ -863,9 +884,9 @@
#endif
#define __HAL_RCC_GPIOE_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOE)
#define __HAL_RCC_GPIOH_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOH)
-
+#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_ADC_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_ADC)
-
+#endif
#if defined(AES1)
#define __HAL_RCC_AES1_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_AES1)
#endif
@@ -976,6 +997,9 @@
* @{
*/
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define __HAL_RCC_ADC_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_ADC)
+#endif
#define __HAL_RCC_TIM1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1)
#define __HAL_RCC_SPI1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1)
#define __HAL_RCC_USART1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1)
@@ -985,6 +1009,9 @@
#define __HAL_RCC_SAI1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SAI1)
#endif
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define __HAL_RCC_ADC_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_ADC)
+#endif
#define __HAL_RCC_TIM1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM1)
#define __HAL_RCC_SPI1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SPI1)
#define __HAL_RCC_USART1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_USART1)
@@ -1046,7 +1073,9 @@
#endif
#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOE)
#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOH)
+#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_ADC_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADC)
+#endif
#if defined(AES1)
#define __HAL_RCC_AES1_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_AES1)
#endif
@@ -1059,7 +1088,9 @@
#endif
#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOE))
#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOH))
+#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_ADC_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADC))
+#endif
#if defined(AES1)
#define __HAL_RCC_AES1_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_AES1))
#endif
@@ -1172,6 +1203,9 @@
* @{
*/
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define __HAL_RCC_ADC_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_ADC)
+#endif
#define __HAL_RCC_TIM1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM1)
#define __HAL_RCC_SPI1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI1)
#define __HAL_RCC_USART1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1)
@@ -1182,6 +1216,9 @@
#endif
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define __HAL_RCC_ADC_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_ADC))
+#endif
#define __HAL_RCC_TIM1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM1))
#define __HAL_RCC_SPI1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI1))
#define __HAL_RCC_USART1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1))
@@ -1245,7 +1282,9 @@
#endif
#define __HAL_RCC_C2GPIOE_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE)
#define __HAL_RCC_C2GPIOH_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
+#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_C2ADC_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_ADC)
+#endif
#if defined(AES1)
#define __HAL_RCC_C2AES1_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_AES1)
#endif
@@ -1258,7 +1297,9 @@
#endif
#define __HAL_RCC_C2GPIOE_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE)
#define __HAL_RCC_C2GPIOH_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
+#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_C2ADC_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_ADC)
+#endif
#if defined(AES1)
#define __HAL_RCC_C2AES1_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_AES1)
#endif
@@ -1363,6 +1404,9 @@
* @{
*/
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define __HAL_RCC_C2ADC_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_ADC)
+#endif
#define __HAL_RCC_C2TIM1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM1)
#define __HAL_RCC_C2SPI1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_SPI1)
#define __HAL_RCC_C2USART1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_USART1)
@@ -1372,6 +1416,9 @@
#define __HAL_RCC_C2SAI1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_SAI1)
#endif
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define __HAL_RCC_C2ADC_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_ADC)
+#endif
#define __HAL_RCC_C2TIM1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM1)
#define __HAL_RCC_C2SPI1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_SPI1)
#define __HAL_RCC_C2USART1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_USART1)
@@ -1394,11 +1441,14 @@
*/
#define __HAL_RCC_C2BLE_CLK_ENABLE() LL_C2_APB3_GRP1_EnableClock(LL_C2_APB3_GRP1_PERIPH_BLE)
+#if defined(RCC_802_SUPPORT)
#define __HAL_RCC_C2802_CLK_ENABLE() LL_C2_APB3_GRP1_EnableClock(LL_C2_APB3_GRP1_PERIPH_802)
+#endif
#define __HAL_RCC_C2BLE_CLK_DISABLE() LL_C2_APB3_GRP1_DisableClock(LL_C2_APB3_GRP1_PERIPH_BLE)
+#if defined(RCC_802_SUPPORT)
#define __HAL_RCC_C2802_CLK_DISABLE() LL_C2_APB3_GRP1_DisableClock(LL_C2_APB3_GRP1_PERIPH_802)
-
+#endif
/**
* @}
@@ -1454,7 +1504,9 @@
#endif
#define __HAL_RCC_C2GPIOE_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE)
#define __HAL_RCC_C2GPIOH_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
+#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_C2ADC_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_ADC)
+#endif
#if defined(AES1)
#define __HAL_RCC_C2AES1_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_AES1)
#endif
@@ -1467,7 +1519,9 @@
#endif
#define __HAL_RCC_C2GPIOE_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE))
#define __HAL_RCC_C2GPIOH_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH))
+#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_C2ADC_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_ADC))
+#endif
#if defined(AES1)
#define __HAL_RCC_C2AES1_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_AES1))
#endif
@@ -1572,6 +1626,9 @@
* @{
*/
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define __HAL_RCC_C2ADC_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_ADC)
+#endif
#define __HAL_RCC_C2TIM1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM1)
#define __HAL_RCC_C2SPI1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SPI1)
#define __HAL_RCC_C2USART1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_USART1)
@@ -1581,6 +1638,9 @@
#define __HAL_RCC_C2SAI1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SAI1)
#endif
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define __HAL_RCC_C2ADC_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_ADC))
+#endif
#define __HAL_RCC_C2TIM1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM1))
#define __HAL_RCC_C2SPI1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SPI1))
#define __HAL_RCC_C2USART1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_USART1))
@@ -1604,10 +1664,14 @@
*/
#define __HAL_RCC_C2BLE_IS_CLK_ENABLED() LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_BLE)
+#if defined(RCC_802_SUPPORT)
#define __HAL_RCC_C2802_IS_CLK_ENABLED() LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_802)
+#endif
#define __HAL_RCC_C2BLE_IS_CLK_DISABLED() !(LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_BLE))
+#if defined(RCC_802_SUPPORT)
#define __HAL_RCC_C2802_IS_CLK_DISABLED() !(LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_802))
+#endif
/**
* @}
@@ -1659,7 +1723,9 @@
#endif
#define __HAL_RCC_GPIOE_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOE)
#define __HAL_RCC_GPIOH_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOH)
+#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_ADC_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC)
+#endif
#if defined(AES1)
#define __HAL_RCC_AES1_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_AES1)
#endif
@@ -1673,7 +1739,9 @@
#endif
#define __HAL_RCC_GPIOE_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOE)
#define __HAL_RCC_GPIOH_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOH)
+#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_ADC_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC)
+#endif
#if defined(AES1)
#define __HAL_RCC_AES1_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_AES1)
#endif
@@ -1786,6 +1854,9 @@
* @{
*/
#define __HAL_RCC_APB2_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ALL)
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define __HAL_RCC_ADC_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC)
+#endif
#define __HAL_RCC_TIM1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1)
#define __HAL_RCC_SPI1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1)
#define __HAL_RCC_USART1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1)
@@ -1796,6 +1867,9 @@
#endif
#define __HAL_RCC_APB2_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ALL)
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define __HAL_RCC_ADC_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC)
+#endif
#define __HAL_RCC_TIM1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1)
#define __HAL_RCC_SPI1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1)
#define __HAL_RCC_USART1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1)
@@ -1895,7 +1969,9 @@
#endif
#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOE)
#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH)
+#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_ADC)
+#endif
#if defined(AES1)
#define __HAL_RCC_AES1_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_AES1)
#endif
@@ -1908,7 +1984,9 @@
#endif
#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOE)
#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH)
+#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_ADC)
+#endif
#if defined(AES1)
#define __HAL_RCC_AES1_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_AES1)
#endif
@@ -1921,7 +1999,9 @@
#endif
#define __HAL_RCC_C2GPIOE_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOE)
#define __HAL_RCC_C2GPIOH_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
+#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_C2ADC_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_ADC)
+#endif
#if defined(AES1)
#define __HAL_RCC_C2AES1_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_AES1)
#endif
@@ -1934,7 +2014,9 @@
#endif
#define __HAL_RCC_C2GPIOE_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOE)
#define __HAL_RCC_C2GPIOH_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
+#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_C2ADC_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_ADC)
+#endif
#if defined(AES1)
#define __HAL_RCC_C2AES1_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_AES1)
#endif
@@ -2103,6 +2185,9 @@
* @note By default, all peripheral clocks are enabled during SLEEP mode.
* @{
*/
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_ADC)
+#endif
#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM1)
#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_SPI1)
#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_USART1)
@@ -2112,6 +2197,9 @@
#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_SAI1)
#endif
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_ADC)
+#endif
#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM1)
#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_SPI1)
#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_USART1)
@@ -2121,6 +2209,9 @@
#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_SAI1)
#endif
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define __HAL_RCC_C2ADC_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_ADC)
+#endif
#define __HAL_RCC_C2TIM1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1)
#define __HAL_RCC_C2SPI1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1)
#define __HAL_RCC_C2USART1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1)
@@ -2130,6 +2221,9 @@
#define __HAL_RCC_C2SAI1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_SAI1)
#endif
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define __HAL_RCC_C2ADC_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_ADC)
+#endif
#define __HAL_RCC_C2TIM1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1)
#define __HAL_RCC_C2SPI1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1)
#define __HAL_RCC_C2USART1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1)
@@ -2213,7 +2307,9 @@
#endif
#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET)
#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET)
+#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET)
+#endif
#if defined(AES1)
#define __HAL_RCC_AES1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AES1SMEN) != RESET)
#endif
@@ -2226,7 +2322,9 @@
#endif
#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET)
#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET)
+#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET)
+#endif
#if defined(AES1)
#define __HAL_RCC_AES1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AES1SMEN) == RESET)
#endif
@@ -2239,7 +2337,9 @@
#endif
#define __HAL_RCC_C2GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOESMEN) != RESET)
#define __HAL_RCC_C2GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOHSMEN) != RESET)
+#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_C2ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_ADCSMEN) != RESET)
+#endif
#if defined(AES1)
#define __HAL_RCC_C2AES1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_AES1SMEN) != RESET)
#endif
@@ -2252,7 +2352,9 @@
#endif
#define __HAL_RCC_C2GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOESMEN) == RESET)
#define __HAL_RCC_C2GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOHSMEN) == RESET)
+#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_C2ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_ADCSMEN) == RESET)
+#endif
#if defined(AES1)
#define __HAL_RCC_C2AES1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_AES1SMEN) == RESET)
#endif
@@ -2419,6 +2521,9 @@
* @note By default, all peripheral clocks are enabled during SLEEP mode.
* @{
*/
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_ADCSMEN) != RESET)
+#endif
#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET)
#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET)
#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET)
@@ -2428,6 +2533,9 @@
#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET)
#endif
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_ADCSMEN) == RESET)
+#endif
#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET)
#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET)
#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET)
@@ -2437,6 +2545,9 @@
#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET)
#endif
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define __HAL_RCC_C2ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_ADCSMEN) != RESET)
+#endif
#define __HAL_RCC_C2TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM1SMEN) != RESET)
#define __HAL_RCC_C2SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SPI1SMEN) != RESET)
#define __HAL_RCC_C2USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_USART1SMEN) != RESET)
@@ -2446,6 +2557,9 @@
#define __HAL_RCC_C2SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SAI1SMEN) != RESET)
#endif
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define __HAL_RCC_C2ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_ADCSMEN) == RESET)
+#endif
#define __HAL_RCC_C2TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM1SMEN) == RESET)
#define __HAL_RCC_C2SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SPI1SMEN) == RESET)
#define __HAL_RCC_C2USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_USART1SMEN) == RESET)
@@ -2467,10 +2581,14 @@
* @{
*/
#define __HAL_RCC_C2BLE_CLK_SLEEP_ENABLE() LL_C2_APB3_GRP1_EnableClockSleep(LL_C2_APB3_GRP1_PERIPH_BLE)
+#if defined(RCC_802_SUPPORT)
#define __HAL_RCC_C2802_CLK_SLEEP_ENABLE() LL_C2_APB3_GRP1_EnableClockSleep(LL_C2_APB3_GRP1_PERIPH_802)
+#endif
#define __HAL_RCC_C2BLE_CLK_SLEEP_DISABLE() LL_C2_APB3_GRP1_DisableClockSleep(LL_C2_APB3_GRP1_PERIPH_BLE)
+#if defined(RCC_802_SUPPORT)
#define __HAL_RCC_C2802_CLK_SLEEP_DISABLE() LL_C2_APB3_GRP1_DisableClockSleep(LL_C2_APB3_GRP1_PERIPH_802)
+#endif
/**
* @}
*/
@@ -2484,10 +2602,14 @@
* @{
*/
#define __HAL_RCC_C2BLE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_BLESMEN) != RESET)
+#if defined(RCC_802_SUPPORT)
#define __HAL_RCC_C2802_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_802SMEN) != RESET)
+#endif
#define __HAL_RCC_C2BLE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_BLESMEN) == RESET)
+#if defined(RCC_802_SUPPORT)
#define __HAL_RCC_C2802_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_802SMEN) == RESET)
+#endif
/**
* @}
*/
@@ -2689,10 +2811,7 @@
/**
* @brief Macro to configure the External High Speed oscillator (HSE).
- * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
- * supported by this macro. User should request a transition to HSE Off
- * first and then HSE On or HSE Bypass.
- * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
+ * @note After enabling the HSE (RCC_HSE_ON), the application
* software should wait on HSERDY flag to be set indicating that HSE clock
* is stable and can be used to clock the PLL and/or system clock.
* @note HSE state can not be changed if it is used directly or through the
@@ -2707,29 +2826,9 @@
* @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after
* 6 HSE oscillator clock cycles.
* @arg @ref RCC_HSE_ON Turn ON the HSE oscillator.
- * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. (*)
* @note (*) Value not defined for all devices
* @retval None
*/
-#if defined(RCC_CR_HSEBYP)
-#define __HAL_RCC_HSE_CONFIG(__STATE__) \
- do { \
- if((__STATE__) == RCC_HSE_ON) \
- { \
- LL_RCC_HSE_Enable(); \
- } \
- else if((__STATE__) == RCC_HSE_BYPASS) \
- { \
- LL_RCC_HSE_EnableBypass(); \
- LL_RCC_HSE_Enable(); \
- } \
- else \
- { \
- LL_RCC_HSE_Disable(); \
- LL_RCC_HSE_DisableBypass(); \
- } \
- } while(0U)
-#else
#define __HAL_RCC_HSE_CONFIG(__STATE__) \
do { \
if((__STATE__) == RCC_HSE_ON) \
@@ -2741,7 +2840,6 @@
LL_RCC_HSE_Disable(); \
} \
} while(0U)
-#endif
/** @brief Macros to enable or disable the HSE Prescaler
* @note HSE div2 could be used as Sysclk or PLL entry in Range2
@@ -2789,6 +2887,7 @@
} while(0U)
+#if defined(RCC_HSI48_SUPPORT)
/** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
* @note After enabling the HSI48, the application software should wait on HSI48RDY
@@ -2798,6 +2897,7 @@
*/
#define __HAL_RCC_HSI48_ENABLE() LL_RCC_HSI48_Enable()
#define __HAL_RCC_HSI48_DISABLE() LL_RCC_HSI48_Disable()
+#endif
/** @brief Macros to configure HSE sense amplifier threshold.
* @note to configure HSE sense amplifier, first disable HSE
@@ -2988,7 +3088,6 @@
* @arg @ref RCC_PLL_USBCLK This Clock is used to generate the clock for the USB FS (48 MHz)
* @arg @ref RCC_PLL_RNGCLK This clock is used to generate the clock for RNG
* @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 64MHz)
- * @arg @ref RCC_PLL_I2SCLK This Clock is used to generate the clock for the I2S
* @retval None
*/
#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
@@ -3069,8 +3168,8 @@
* @arg @ref RCC_MCO1SOURCE_LSI1 LSI1 clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_LSI2 LSI2 clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source
-
+ * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source (*)
+ *
* @param __MCODIV__ specifies the MCO clock prescaler.
* This parameter can be one of the following values:
* @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
@@ -3078,6 +3177,8 @@
* @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
* @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
* @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
+ *
+ * @note (*) Value not defined for all devices
*/
#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) LL_RCC_ConfigMCO((__MCOCLKSOURCE__), (__MCODIV__))
@@ -3098,8 +3199,11 @@
* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt enable
* @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt enable
* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt enable
- * @arg @ref RCC_IT_HSI48RDY PLLHSI48 ready interrupt enable
+ * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt enable (*)
* @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt enable
+ *
+ * @note (*) Value not defined for all devices
+ *
* @retval None
*/
#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
@@ -3115,8 +3219,11 @@
* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt enable
* @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt enable
* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt enable
- * @arg @ref RCC_IT_HSI48RDY PLLHSI48 ready interrupt enable
+ * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt enable (*)
* @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt enable
+ *
+ * @note (*) Value not defined for all devices
+ *
* @retval None
*/
#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
@@ -3134,8 +3241,10 @@
* @arg @ref RCC_IT_PLLRDY PLLSAI1 ready interrupt clear
* @arg @ref RCC_IT_HSECSS HSE Clock security system interrupt clear
* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt clear
- * @arg @ref RCC_IT_HSI48RDY PLLHSI48 ready interrupt clear
+ * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt clear (*)
* @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt clear
+ *
+ * @note (*) Value not defined for all devices
*/
#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
@@ -3151,8 +3260,11 @@
* @arg @ref RCC_IT_PLLRDY PLLSAI1 ready interrupt flag
* @arg @ref RCC_IT_HSECSS HSE Clock security system interrupt flag
* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt flag
- * @arg @ref RCC_IT_HSI48RDY PLLHSI48 ready interrupt flag
+ * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt flag (*)
* @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt flag
+ *
+ * @note (*) Value not defined for all devices
+ *
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
@@ -3167,23 +3279,26 @@
/** @brief Check whether the selected RCC flag is set or not.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
- * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready
- * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready
- * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready
- * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready
- * @arg @ref RCC_FLAG_PLLRDY PLLSAI1 clock ready
- * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48
- * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready
- * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection
- * @arg @ref RCC_FLAG_LSI1RDY LSI1 oscillator clock ready
- * @arg @ref RCC_FLAG_LSI2RDY LSI2 oscillator clock ready
- * @arg @ref RCC_FLAG_BORRST BOR reset
- * @arg @ref RCC_FLAG_OBLRST OBLRST reset
- * @arg @ref RCC_FLAG_PINRST Pin reset
- * @arg @ref RCC_FLAG_SFTRST Software reset
- * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset
- * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset
- * @arg @ref RCC_FLAG_LPWRRST Low Power reset
+ * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready
+ * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready
+ * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready
+ * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready
+ * @arg @ref RCC_FLAG_PLLRDY PLLSAI1 clock ready
+ * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 (*)
+ * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready
+ * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection
+ * @arg @ref RCC_FLAG_LSI1RDY LSI1 oscillator clock ready
+ * @arg @ref RCC_FLAG_LSI2RDY LSI2 oscillator clock ready
+ * @arg @ref RCC_FLAG_BORRST BOR reset
+ * @arg @ref RCC_FLAG_OBLRST OBLRST reset
+ * @arg @ref RCC_FLAG_PINRST Pin reset
+ * @arg @ref RCC_FLAG_SFTRST Software reset
+ * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset
+ * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset
+ * @arg @ref RCC_FLAG_LPWRRST Low Power reset
+ *
+ * @note (*) Value not defined for all devices
+ *
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \
diff --git a/Inc/stm32wbxx_hal_rcc_ex.h b/Inc/stm32wbxx_hal_rcc_ex.h
index 920bf86..7d527e9 100644
--- a/Inc/stm32wbxx_hal_rcc_ex.h
+++ b/Inc/stm32wbxx_hal_rcc_ex.h
@@ -86,21 +86,17 @@
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
(((__SELECTION__) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP)|| \
(((__SELECTION__) & RCC_PERIPHCLK_SMPS) == RCC_PERIPHCLK_SMPS))
-#elif defined(LPUART1) && defined(USB) && defined(RCC_SMPS_SUPPORT) && defined(SPI_I2S_SUPPORT)
+#elif defined(LPUART1)
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP)|| \
- (((__SELECTION__) & RCC_PERIPHCLK_SMPS) == RCC_PERIPHCLK_SMPS) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S))
+ (((__SELECTION__) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP))
#else
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
@@ -159,6 +155,7 @@
((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \
((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
+#if defined(RCC_HSI48_SUPPORT)
#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \
((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \
@@ -166,6 +163,14 @@
((__SOURCE__) == RCC_RNGCLKSOURCE_CLK48) || \
((__SOURCE__) == RCC_RNGCLKSOURCE_LSI) || \
((__SOURCE__) == RCC_RNGCLKSOURCE_LSE))
+#else
+#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \
+ ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI) || \
+ ((__SOURCE__) == RCC_RNGCLKSOURCE_CLK48) || \
+ ((__SOURCE__) == RCC_RNGCLKSOURCE_LSI) || \
+ ((__SOURCE__) == RCC_RNGCLKSOURCE_LSE))
+#endif
#if defined(USB)
#if defined(SAI1)
@@ -195,18 +200,10 @@
((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
#endif
-#if defined(STM32WB55xx) || defined (STM32WB5Mxx) || defined(STM32WB35xx) || defined (STM32WB15xx)
-#define IS_RCC_RFWKPCLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_RFWKPCLKSOURCE_NONE) || \
- ((__SOURCE__) == RCC_RFWKPCLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_RFWKPCLKSOURCE_LSI) || \
- ((__SOURCE__) == RCC_RFWKPCLKSOURCE_HSE_DIV1024))
-#else
#define IS_RCC_RFWKPCLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_RFWKPCLKSOURCE_NONE) || \
((__SOURCE__) == RCC_RFWKPCLKSOURCE_LSE) || \
((__SOURCE__) == RCC_RFWKPCLKSOURCE_HSE_DIV1024))
-#endif
#if defined(RCC_SMPS_SUPPORT)
#define IS_RCC_SMPSCLKDIV(__DIV__) \
@@ -221,13 +218,6 @@
((__SOURCE__) == RCC_SMPSCLKSOURCE_HSE))
#endif
-#if defined(SPI_I2S_SUPPORT)
-#define IS_RCC_I2SCLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_I2SCLKSOURCE_NONE) || \
- ((__SOURCE__) == RCC_I2SCLKSOURCE_HSI) || \
- ((__SOURCE__) == RCC_I2SCLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_I2SCLKSOURCE_PIN))
-#endif
#if defined(SAI1)
#define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U))
@@ -364,10 +354,6 @@
This parameter can be a value of @ref RCCEx_SMPS_Clock_Divider */
#endif
-#if defined(SPI_I2S_SUPPORT)
- uint32_t I2sClockSelection; /*!< Specifies I2s clock source.
- This parameter can be a value of @ref RCCEx_I2s_Clock_Source */
-#endif
} RCC_PeriphCLKInitTypeDef;
@@ -479,9 +465,6 @@
#if defined(RCC_SMPS_SUPPORT)
#define RCC_PERIPHCLK_SMPS 0x00002000U /*!< SMPS Peripheral Clock Selection */
#endif
-#if defined(SPI_I2S_SUPPORT)
-#define RCC_PERIPHCLK_I2S 0x00004000U /*!< I2S Peripheral Clock Selection */
-#endif
/**
* @}
*/
@@ -627,9 +610,6 @@
#define RCC_RFWKPCLKSOURCE_NONE LL_RCC_RFWKP_CLKSOURCE_NONE /*!< None clock selected as RF system wakeup clock */
#define RCC_RFWKPCLKSOURCE_LSE LL_RCC_RFWKP_CLKSOURCE_LSE /*!< LSE clock selected as RF system wakeup clock */
-#if defined(STM32WB55xx) || defined (STM32WB5Mxx) || defined(STM32WB35xx) || defined (STM32WB15xx)
-#define RCC_RFWKPCLKSOURCE_LSI LL_RCC_RFWKP_CLKSOURCE_LSI /*!< LSI clock selected as RF system wakeup clock */
-#endif
#define RCC_RFWKPCLKSOURCE_HSE_DIV1024 LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024 /*!< HSE clock divided by 1024 selected as RF system wakeup clock */
/**
@@ -670,18 +650,6 @@
*/
#endif
-#if defined(SPI_I2S_SUPPORT)
-/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
- * @{
- */
-#define RCC_I2SCLKSOURCE_NONE LL_RCC_I2S_CLKSOURCE_NONE /*!< No clock selected as I2S clock */
-#define RCC_I2SCLKSOURCE_PLL LL_RCC_I2S_CLKSOURCE_PLL /*!< PLL "Q" clock selected as I2S clock source */
-#define RCC_I2SCLKSOURCE_HSI LL_RCC_I2S_CLKSOURCE_HSI /*!< HSI clock selected as I2S clock */
-#define RCC_I2SCLKSOURCE_PIN LL_RCC_I2S_CLKSOURCE_PIN /*!< External clock selected as I2S clock */
-/**
- * @}
- */
-#endif
/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
* @{
@@ -1220,9 +1188,7 @@
* This parameter can be one of the following values:
* @arg @ref RCC_RFWKPCLKSOURCE_NONE No clock selected as RFWKP clock
* @arg @ref RCC_RFWKPCLKSOURCE_LSE LSE Clock selected as RFWKP clock
- * @arg @ref RCC_RFWKPCLKSOURCE_LSI LSI Clock selected as RFWKP clock (*)
* @arg @ref RCC_RFWKPCLKSOURCE_HSE_DIV1024 HSE div1024 Clock selected as RFWKP clock
- * @note (*) Value not defined for all devices
* @retval None
*/
#define __HAL_RCC_RFWAKEUP_CONFIG(__RFWKP_CLKSOURCE__) LL_RCC_SetRFWKPClockSource(__RFWKP_CLKSOURCE__)
@@ -1231,9 +1197,7 @@
* This parameter can be one of the following values:
* @arg @ref RCC_RFWKPCLKSOURCE_NONE No clock selected as RFWKP clock
* @arg @ref RCC_RFWKPCLKSOURCE_LSE LSE Clock selected as RFWKP clock
- * @arg @ref RCC_RFWKPCLKSOURCE_LSI LSI Clock selected as RFWKP clock (*)
* @arg @ref RCC_RFWKPCLKSOURCE_HSE_DIV1024 HSE div1024 Clock selected as RFWKP clock
- * @note (*) Value not defined for all devices
*/
#define __HAL_RCC_GET_RFWAKEUP_SOURCE() LL_RCC_GetRFWKPClockSource()
@@ -1297,27 +1261,6 @@
* @{
*/
-#if defined(SPI_I2S_SUPPORT)
-/** @brief Macro to configure the I2S clock (I2SCLK).
- * @param __I2S_CLKSOURCE__ specifies the I2S clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_I2SCLKSOURCE_NONE No clock selected as I2S clock
- * @arg @ref RCC_I2SCLKSOURCE_PLL PLL "Q" selected as I2S clock
- * @arg @ref RCC_I2SCLKSOURCE_HSI HSI selected as I2S clock
- * @arg @ref RCC_I2SCLKSOURCE_PIN External clock selected as I2S clock
- * @retval None
- */
-#define __HAL_RCC_I2S_CONFIG(__I2S_CLKSOURCE__) LL_RCC_SetI2SClockSource(__I2S_CLKSOURCE__)
-
-/** @brief Macro to get the I2S clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_I2SCLKSOURCE_NONE No clock selected as I2S clock
- * @arg @ref RCC_I2SCLKSOURCE_PLL PLL "Q" selected as I2S clock
- * @arg @ref RCC_I2SCLKSOURCE_HSI HSI selected as I2S clock
- * @arg @ref RCC_I2SCLKSOURCE_PIN External clock selected as I2S clock
- */
-#define __HAL_RCC_GET_I2S_SOURCE() LL_RCC_GetI2SClockSource(LL_RCC_I2S_CLKSOURCE)
-#endif
#if defined(SAI1)
/** @brief Enable PLLSAI1RDY interrupt.
diff --git a/Inc/stm32wbxx_hal_smbus.h b/Inc/stm32wbxx_hal_smbus.h
index 57ef924..f522139 100644
--- a/Inc/stm32wbxx_hal_smbus.h
+++ b/Inc/stm32wbxx_hal_smbus.h
@@ -65,7 +65,7 @@
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
This parameter can be a 7-bit address. */
- uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
+ uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
This parameter can be a value of @ref SMBUS_own_address2_masks. */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
diff --git a/Inc/stm32wbxx_hal_tim.h b/Inc/stm32wbxx_hal_tim.h
index e7fd6c9..eaad4ea 100644
--- a/Inc/stm32wbxx_hal_tim.h
+++ b/Inc/stm32wbxx_hal_tim.h
@@ -400,35 +400,35 @@
*/
typedef enum
{
- HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
- ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
- ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
- ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
- ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
- ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
- ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
- ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
- ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
- ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
- ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
- ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
- ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
- ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
- ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
- ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
- ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
- ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
+ HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
+ , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
+ , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
+ , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
+ , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
+ , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
+ , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
+ , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
+ , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
+ , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
+ , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
+ , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
+ , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
+ , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
+ , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
+ , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
- ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
- ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
- ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
- ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
- ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
- ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
- ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
- ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
- ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
- ,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */
+ , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
+ , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
+ , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
+ , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
+ , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
+ , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
+ , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
+ , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
+ , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
+ , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */
} HAL_TIM_CallbackIDTypeDef;
/**
@@ -924,7 +924,7 @@
* @{
*/
#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
-#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
+#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
(if none of the break inputs BRK and BRK2 is active) */
/**
* @}
@@ -2019,6 +2019,8 @@
((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
+#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
+
#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
@@ -2062,7 +2064,7 @@
((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\
((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\
(__HANDLE__)->ChannelState[5])
-
+
#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
@@ -2085,7 +2087,7 @@
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
(__HANDLE__)->ChannelNState[3])
-
+
#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
@@ -2270,9 +2272,15 @@
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
+ uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
+ uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
diff --git a/Inc/stm32wbxx_hal_tim_ex.h b/Inc/stm32wbxx_hal_tim_ex.h
index 7b31bb2..efd46fc 100644
--- a/Inc/stm32wbxx_hal_tim_ex.h
+++ b/Inc/stm32wbxx_hal_tim_ex.h
@@ -206,46 +206,45 @@
* @{
*/
#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx)
-#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \
- ((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFF3FECU) == 0x00000000U))) \
- || (((__INSTANCE__) == TIM2) && ((((__REMAP__) & 0xFFFF3FF0U) == 0x00000000U))) \
- || (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))) \
- || (((__INSTANCE__) == TIM17) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))))
+#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \
+ ((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFE3FECU) == 0x00000000U))) \
+ || (((__INSTANCE__) == TIM2) && ((((__REMAP__) & 0xFFFE3FF0U) == 0x00000000U))) \
+ || (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))) \
+ || (((__INSTANCE__) == TIM17) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))))
#else
#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \
- ((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))) \
- || (((__INSTANCE__) == TIM2) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \
- || (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))) \
- || (((__INSTANCE__) == TIM17) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))))
+ ((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))) \
+ || (((__INSTANCE__) == TIM2) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \
+ || (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))) \
+ || (((__INSTANCE__) == TIM17) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))))
#endif
-#define IS_TIM_BREAKINPUT(__BREAKINPUT__) \
- (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
- ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
+#define IS_TIM_BREAKINPUT(__BREAKINPUT__) \
+ (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
+ ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
#if defined(COMP1)
#if defined(COMP2)
-#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) \
- (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
- ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
- ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2))
+#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) \
+ (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
+ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
+ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2))
#else
-#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) \
- (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
- ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1))
+#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) \
+ (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN))
#endif
#else
#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) \
- (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN))
+ (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN))
#endif
-#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) \
- (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
- ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
+#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) \
+ (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
+ ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
-#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) \
- (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \
- ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
+#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) \
+ (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \
+ ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
/**
* @}
diff --git a/Inc/stm32wbxx_hal_usart.h b/Inc/stm32wbxx_hal_usart.h
index 6405572..1cc6d45 100644
--- a/Inc/stm32wbxx_hal_usart.h
+++ b/Inc/stm32wbxx_hal_usart.h
@@ -138,7 +138,7 @@
uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */
- uint32_t SlaveMode; /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value
+ uint32_t SlaveMode; /*!< Enable/Disable USART SPI Slave Mode. This parameter can be a value
of @ref USARTEx_Slave_Mode */
uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value
@@ -697,7 +697,7 @@
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
* @param __PCLK__ USART clock.
* @param __BAUD__ Baud rate set by the user.
- * @param __CLOCKPRESCALER__ UART prescaler value.
+ * @param __CLOCKPRESCALER__ USART prescaler value.
* @retval Division result
*/
#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U) + ((__BAUD__)/2U)) / (__BAUD__))
diff --git a/Inc/stm32wbxx_hal_wwdg.h b/Inc/stm32wbxx_hal_wwdg.h
index 8d69784..982848c 100644
--- a/Inc/stm32wbxx_hal_wwdg.h
+++ b/Inc/stm32wbxx_hal_wwdg.h
@@ -56,7 +56,7 @@
uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
- uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
+ uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not.
This parameter can be a value of @ref WWDG_EWI_Mode */
} WWDG_InitTypeDef;
@@ -68,17 +68,17 @@
typedef struct __WWDG_HandleTypeDef
#else
typedef struct
-#endif
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
{
WWDG_TypeDef *Instance; /*!< Register base address */
WWDG_InitTypeDef Init; /*!< WWDG required parameters */
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
- void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
+ void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
- void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
-#endif
+ void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
} WWDG_HandleTypeDef;
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
@@ -87,8 +87,8 @@
*/
typedef enum
{
- HAL_WWDG_EWI_CB_ID = 0x00u, /*!< WWDG EWI callback ID */
- HAL_WWDG_MSPINIT_CB_ID = 0x01u, /*!< WWDG MspInit callback ID */
+ HAL_WWDG_EWI_CB_ID = 0x00U, /*!< WWDG EWI callback ID */
+ HAL_WWDG_MSPINIT_CB_ID = 0x01U, /*!< WWDG MspInit callback ID */
} HAL_WWDG_CallbackIDTypeDef;
/**
@@ -96,7 +96,7 @@
*/
typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */
-#endif
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -268,9 +268,10 @@
void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
+ pWWDG_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
-#endif
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/**
* @}
diff --git a/Inc/stm32wbxx_ll_adc.h b/Inc/stm32wbxx_ll_adc.h
index 83f03ed..17e53a3 100644
--- a/Inc/stm32wbxx_ll_adc.h
+++ b/Inc/stm32wbxx_ll_adc.h
@@ -53,6 +53,9 @@
/* Internal register offset for ADC group regular sequencer configuration */
/* (offset placed into a spare area of literal definition) */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* No register ADC_SQRx on this ADC peripheral version */
+#else
#define ADC_SQR1_REGOFFSET (0x00000000UL)
#define ADC_SQR2_REGOFFSET (0x00000100UL)
#define ADC_SQR3_REGOFFSET (0x00000200UL)
@@ -60,10 +63,21 @@
#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
#define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
+#endif /* ADC_SUPPORT_2_5_MSPS */
#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
/* Definition of ADC group regular sequencer bits information to be inserted */
/* into ADC group regular sequencer ranks literals definition. */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ1" position in register */
+#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 4UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ2" position in register */
+#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ3" position in register */
+#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ4" position in register */
+#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ5" position in register */
+#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ6" position in register */
+#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ7" position in register */
+#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (28UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ8" position in register */
+#else
#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR1_SQ1" position in register */
#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR1_SQ2" position in register */
#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR1_SQ3" position in register */
@@ -80,6 +94,7 @@
#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR3_SQ14" position in register */
#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR4_SQ15" position in register */
#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR4_SQ16" position in register */
+#endif /* ADC_SUPPORT_2_5_MSPS */
@@ -176,11 +191,18 @@
/* - channel sampling time defined by SMPRx register offset */
/* and SMPx bits positions into SMPRx register */
#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL)
+#else
#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
+#endif
#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define ADC_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Value equivalent to ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 serie, ADC group regular sequencer, if set to mode "fully configurable", can contain channels with a restricted channel number. Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */
+#endif
#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
-#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
+#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FUL) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
/* Channel differentiation between external and internal channels */
#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
@@ -221,6 +243,27 @@
/* Definition of channels ID bitfield information to be inserted into */
/* channels literals definition. */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define ADC_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0)
+#define ADC_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1)
+#define ADC_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2)
+#define ADC_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3)
+#define ADC_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4)
+#define ADC_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5)
+#define ADC_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6)
+#define ADC_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7)
+#define ADC_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8)
+#define ADC_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9)
+#define ADC_CHANNEL_10_BITFIELD (ADC_CHSELR_CHSEL10)
+#define ADC_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11)
+#define ADC_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12)
+#define ADC_CHANNEL_13_BITFIELD (ADC_CHSELR_CHSEL13)
+#define ADC_CHANNEL_14_BITFIELD (ADC_CHSELR_CHSEL14)
+#define ADC_CHANNEL_15_BITFIELD (ADC_CHSELR_CHSEL15)
+#define ADC_CHANNEL_16_BITFIELD (ADC_CHSELR_CHSEL16)
+#define ADC_CHANNEL_17_BITFIELD (ADC_CHSELR_CHSEL17)
+#define ADC_CHANNEL_18_BITFIELD (ADC_CHSELR_CHSEL18)
+#else
#define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
#define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
#define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
@@ -240,6 +283,7 @@
#define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
#define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
#define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
+#endif
/* Definition of channels sampling time information to be inserted into */
/* channels literals definition. */
@@ -264,6 +308,20 @@
#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */
+#if defined(ADC_SUPPORT_2_5_MSPS)
+/* Internal mask for ADC channel sampling time: */
+/* To select into literals LL_ADC_SAMPLINGTIME_x */
+/* the relevant bits for: */
+/* (concatenation of multiple bits used in register SMPR) */
+/* - ADC channels sampling time: setting channel wise, to map each channel */
+/* on one of the common sampling time available. */
+/* - ADC channels common sampling time: set a sampling time into one of the */
+/* common sampling time available. */
+#define ADC_SAMPLING_TIME_CH_MASK (ADC_CHANNEL_ID_BITFIELD_MASK << ADC_SMPR_SMPSEL0_BITOFFSET_POS)
+#define ADC_SAMPLING_TIME_SMP_MASK (ADC_SMPR_SMP2 | ADC_SMPR_SMP1)
+#define ADC_SAMPLING_TIME_SMP_SHIFT_MASK (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SMPR_SMP1_BITOFFSET_POS)
+
+#endif
/* Internal mask for ADC mode single or differential ended: */
/* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
/* the relevant bits for: */
@@ -298,10 +356,16 @@
#define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
+#define ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS (20UL)
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
+#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
+#else
#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
+#endif
#define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
@@ -325,15 +389,49 @@
/* ADC registers bits positions */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define ADC_CFGR1_RES_BITOFFSET_POS ( 3UL) /* Value equivalent to bitfield "ADC_CFGR1_RES" position in register */
+#define ADC_CFGR1_AWDSGL_BITOFFSET_POS (22UL) /* Value equivalent to bitfield "ADC_CFGR1_AWDSGL" position in register */
+#define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_TR1_HT1" position in register */
+#define ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL0" position in register */
+#define ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL1" position in register */
+#define ADC_CHSELR_CHSEL2_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL2" position in register */
+#define ADC_CHSELR_CHSEL3_BITOFFSET_POS ( 3UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL3" position in register */
+#define ADC_CHSELR_CHSEL4_BITOFFSET_POS ( 4UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL4" position in register */
+#define ADC_CHSELR_CHSEL5_BITOFFSET_POS ( 5UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL5" position in register */
+#define ADC_CHSELR_CHSEL6_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL6" position in register */
+#define ADC_CHSELR_CHSEL7_BITOFFSET_POS ( 7UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL7" position in register */
+#define ADC_CHSELR_CHSEL8_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL8" position in register */
+#define ADC_CHSELR_CHSEL9_BITOFFSET_POS ( 9UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL9" position in register */
+#define ADC_CHSELR_CHSEL10_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL10" position in register */
+#define ADC_CHSELR_CHSEL11_BITOFFSET_POS (11UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL11" position in register */
+#define ADC_CHSELR_CHSEL12_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL12" position in register */
+#define ADC_CHSELR_CHSEL13_BITOFFSET_POS (13UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL13" position in register */
+#define ADC_CHSELR_CHSEL14_BITOFFSET_POS (14UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL14" position in register */
+#define ADC_CHSELR_CHSEL15_BITOFFSET_POS (15UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL15" position in register */
+#define ADC_CHSELR_CHSEL16_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL16" position in register */
+#define ADC_CHSELR_CHSEL17_BITOFFSET_POS (17UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL17" position in register */
+#define ADC_CHSELR_CHSEL18_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL18" position in register */
+#define ADC_SMPR_SMP1_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SMPR_SMP1" position in register */
+#define ADC_SMPR_SMP2_BITOFFSET_POS ( 4UL) /* Value equivalent to bitfield "ADC_SMPR_SMP2" position in register */
+#define ADC_SMPR_SMPSEL0_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_SMPR_SMPSEL0" position in register */
+#define ADC_CFGR_RES_BITOFFSET_POS ADC_CFGR1_RES_BITOFFSET_POS
+#define ADC_CFGR_AWDSGL_BITOFFSET_POS ADC_CFGR1_AWDSGL_BITOFFSET_POS
+#else
#define ADC_CFGR_RES_BITOFFSET_POS ( 3UL) /* Value equivalent to bitfield "ADC_CFGR_RES" position in register */
#define ADC_CFGR_AWD1SGL_BITOFFSET_POS (22UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1SGL" position in register */
#define ADC_CFGR_AWD1EN_BITOFFSET_POS (23UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1EN" position in register */
#define ADC_CFGR_JAWD1EN_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_CFGR_JAWD1EN" position in register */
#define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_TR1_HT1" position in register */
+#endif
/* ADC registers bits groups */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
+#else
#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
+#endif
/* ADC internal channels related definitions */
@@ -424,6 +522,17 @@
*/
typedef struct
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ uint32_t Clock; /*!< Set ADC instance clock source and prescaler.
+ This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE
+ @note On this STM32 serie, this parameter has some clock ratio constraints:
+ ADC clock synchronous (from PCLK) with prescaler 1 must be enabled only if PCLK has a 50% duty clock cycle
+ (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle).
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetClock().
+ For more details, refer to description of this function. */
+
+#endif
uint32_t Resolution; /*!< Set ADC resolution.
This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
@@ -501,6 +610,9 @@
} LL_ADC_REG_InitTypeDef;
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/**
* @brief Structure definition of some features of ADC group injected.
* @note These parameters have an impact on ADC scope: ADC group injected.
@@ -549,6 +661,7 @@
This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
} LL_ADC_INJ_InitTypeDef;
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @}
@@ -565,6 +678,10 @@
* @{
*/
#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define LL_ADC_FLAG_CCRDY ADC_ISR_CCRDY /*!< ADC flag ADC channel configuration ready */
+#else
+#endif
#define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
#define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
#define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
@@ -575,6 +692,9 @@
#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
#define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
#define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define LL_ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC flag end of calibration */
+#endif
/**
* @}
*/
@@ -584,6 +704,10 @@
* @{
*/
#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define LL_ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC interruption channel configuration ready */
+#else
+#endif
#define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */
#define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */
#define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
@@ -594,6 +718,9 @@
#define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
#define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
#define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define LL_ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC interruption ADC end of calibration */
+#endif
/**
* @}
*/
@@ -612,9 +739,11 @@
/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
* @{
*/
+#if !defined (ADC_SUPPORT_2_5_MSPS)
#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */
#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
+#endif
#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without prescaler */
#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2 */
#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4 */
@@ -639,7 +768,7 @@
/* If they are not listed below, they do not require any specific */
/* path enable. In this case, Access to measurement path is done */
/* only by selecting the corresponding ADC internal channel. */
-#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement pathes all disabled */
+#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */
#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
@@ -647,6 +776,19 @@
* @}
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/** @defgroup ADC_LL_EC_CLOCK_SOURCE ADC instance - Clock source
+ * @{
+ */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by 4 */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock divided by 2 */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock not divided */
+#define LL_ADC_CLOCK_ASYNC (0x00000000UL) /*!< ADC asynchronous clock. Asynchronous clock prescaler can be configured using function @ref LL_ADC_SetCommonClock(). */
+/**
+ * @}
+ */
+#endif
+
/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
* @{
*/
@@ -662,7 +804,7 @@
* @{
*/
#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
-#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
+#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
/**
* @}
*/
@@ -671,11 +813,37 @@
* @{
*/
#define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
+#define LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF) /*!< ADC low power mode auto power-off: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function @ref LL_ADC_SetLowPowerMode(). */
+#define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */
+#else
#define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
+#endif
/**
* @}
*/
+/** @defgroup ADC_LL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode
+ * @{
+ */
+#define LL_ADC_TRIGGER_FREQ_HIGH (0x00000000UL) /*!< ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
+#define LL_ADC_TRIGGER_FREQ_LOW (ADC_CFGR2_LFTRIG) /*!< ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
+/**
+ * @}
+ */
+
+#if defined(ADC_SUPPORT_2_5_MSPS)
+/** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels
+* @{
+*/
+#define LL_ADC_SAMPLINGTIME_COMMON_1 (ADC_SMPR_SMP1_BITOFFSET_POS) /*!< Set sampling time common to a group of channels: sampling time nb 1 */
+#define LL_ADC_SAMPLINGTIME_COMMON_2 (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SAMPLING_TIME_CH_MASK) /*!< Set sampling time common to a group of channels: sampling time nb 2 */
+/**
+ * @}
+ */
+
+#endif
/** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number
* @{
*/
@@ -700,8 +868,10 @@
* @{
*/
#define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
+#if !defined (ADC_SUPPORT_2_5_MSPS)
#define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/
#define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */
+#endif
/**
* @}
*/
@@ -709,6 +879,30 @@
/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
* @{
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
+#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
+#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
+#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
+#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
+#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
+#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
+#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
+#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
+#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
+#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
+#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
+#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
+#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
+#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
+#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
+#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
+#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
+#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
+#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */
+#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */
+#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */
+#else
#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
@@ -731,6 +925,8 @@
#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_0 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */
#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */
#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/2: Vbat voltage through a divider ladder of factor 1/2 to have Vbat always below Vdda. */
+
+#endif
/**
* @}
*/
@@ -738,6 +934,15 @@
/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
* @{
*/
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 ( ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH4 ( ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO ( ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH4 ( ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
+#else
#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */
#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
@@ -747,6 +952,7 @@
#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
+#endif
/**
* @}
*/
@@ -791,9 +997,30 @@
* @}
*/
+#if defined(ADC_SUPPORT_2_5_MSPS)
+/** @defgroup ADC_LL_EC_REG_SEQ_MODE ADC group regular - Sequencer configuration flexibility
+* @{
+*/
+#define LL_ADC_REG_SEQ_FIXED (0x00000000UL) /*!< Sequencer configured to fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). */
+#define LL_ADC_REG_SEQ_CONFIGURABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer configured to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number. Refer to description of function @ref LL_ADC_REG_SetSequencerChannels(). */
+/**
+ * @}
+ */
+
+#endif
/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
* @{
*/
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define LL_ADC_REG_SEQ_SCAN_DISABLE (ADC_CHSELR_SQ2) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_CHSELR_SQ3) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_CHSELR_SQ4) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_CHSELR_SQ6) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_CHSELR_SQ7) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_CHSELR_SQ8) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (0x00000000UL) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
+#else
#define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
@@ -810,14 +1037,29 @@
#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
+#endif
/**
* @}
*/
+#if defined(ADC_SUPPORT_2_5_MSPS)
+/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction
+ * @{
+ */
+#define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000UL) /*!< On this STM32 serie, parameter relevant only is sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward. */
+#define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /*!< On this STM32 serie, parameter relevant only is sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer) */
+/**
+ * @}
+ */
+
+#endif
/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
* @{
*/
#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
+#else
#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
@@ -826,6 +1068,7 @@
#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @}
*/
@@ -833,6 +1076,16 @@
/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
* @{
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define LL_ADC_REG_RANK_1 (ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
+#define LL_ADC_REG_RANK_2 (ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
+#define LL_ADC_REG_RANK_3 (ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
+#define LL_ADC_REG_RANK_4 (ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
+#define LL_ADC_REG_RANK_5 (ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
+#define LL_ADC_REG_RANK_6 (ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
+#define LL_ADC_REG_RANK_7 (ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
+#define LL_ADC_REG_RANK_8 (ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
+#else
#define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
#define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
#define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
@@ -849,10 +1102,14 @@
#define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
#define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
#define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @}
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
* @{
*/
@@ -926,10 +1183,21 @@
/**
* @}
*/
+#endif /* ADC_SUPPORT_2_5_MSPS */
/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
* @{
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycle */
+#define LL_ADC_SAMPLINGTIME_3CYCLES_5 (ADC_SMPR_SMP1_0) /*!< Sampling time 3.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP1_1) /*!< Sampling time 7.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_0) /*!< Sampling time 12.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR_SMP1_2) /*!< Sampling time 19.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_39CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_0) /*!< Sampling time 39.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_79CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_1) /*!< Sampling time 79.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_160CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_0) /*!< Sampling time 160.5 ADC clock cycles */
+#else
#define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL) /*!< Sampling time 2.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_6CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_12CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 12.5 ADC clock cycles */
@@ -938,6 +1206,7 @@
#define LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 247.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */
+#endif
/**
* @}
*/
@@ -945,9 +1214,13 @@
/** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
* @{
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define LL_ADC_SINGLE_ENDED (0x00000000UL) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
+#else
#define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
#define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
#define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
+#endif
/**
* @}
*/
@@ -956,8 +1229,12 @@
* @{
*/
#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC analog watchdog 2 and 3" not available on ADC peripheral of this STM32WB device */
+#else
#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
+#endif
/**
* @}
*/
@@ -965,6 +1242,32 @@
/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
* @{
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */
+#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CFGR1_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
+#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
+#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
+#else
#define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */
#define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
#define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
@@ -1035,6 +1338,7 @@
#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @}
*/
@@ -1052,11 +1356,16 @@
/** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
* @{
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
+#define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_OVSE) /*!< ADC oversampling on conversions of ADC group regular. Literal suffix "continued" is kept for compatibility with other STM32 devices featuring ADC group injected, in this case other oversampling scope parameters are available. */
+#else
#define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
#define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */
#define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
#define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /*!< ADC oversampling on conversions of ADC group injected. */
#define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
+#endif
/**
* @}
*/
@@ -1065,7 +1374,11 @@
* @{
*/
#define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TOVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
+#else
#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
+#endif
/**
* @}
*/
@@ -1144,7 +1457,8 @@
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tSTART"). */
/* Unit: us */
-#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */
+#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */
+#define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL) /*!< Delay for temperature sensor buffer stabilization time (starting from ADC enable, refer to @ref LL_ADC_Enable()) */
/* Delay required between ADC end of calibration and ADC enable. */
/* Note: On this STM32 serie, a minimum number of ADC clock cycles */
@@ -1230,7 +1544,7 @@
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
* @arg @ref LL_ADC_CHANNEL_VBAT
*
- * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+ * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
* @retval Value between Min_Data=0 and Max_Data=18
*/
@@ -1276,12 +1590,19 @@
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
* @arg @ref LL_ADC_CHANNEL_VBAT (4)
*
- * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+ * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
* (4) For ADC channel read back from ADC register,
* comparison with internal channel parameter to be done
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
+ ( \
+ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
+ (ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__)) \
+ )
+#else
#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
(((__DECIMAL_NB__) <= 9UL) \
? ( \
@@ -1296,6 +1617,7 @@
(ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
) \
)
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Helper macro to determine whether the selected channel
@@ -1338,7 +1660,7 @@
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
* @arg @ref LL_ADC_CHANNEL_VBAT
*
- * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+ * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
* @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
* Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
@@ -1383,7 +1705,7 @@
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
* @arg @ref LL_ADC_CHANNEL_VBAT
*
- * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+ * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0
@@ -1437,6 +1759,7 @@
((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
)
+#if defined (ADC_SUPPORT_2_5_MSPS)
/**
* @brief Helper macro to define ADC analog watchdog parameter:
* define a single channel to monitor with analog watchdog
@@ -1470,7 +1793,78 @@
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
* @arg @ref LL_ADC_CHANNEL_VBAT (4)
*
- * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+ * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+ * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
+ * (4) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ * @param __GROUP__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_GROUP_REGULAR
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_AWD_DISABLE
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)
+ *
+ * (0) On STM32WB, parameter available only on analog watchdog number: AWD1.
+ */
+#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
+ (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
+#else
+/**
+ * @brief Helper macro to define ADC analog watchdog parameter:
+ * define a single channel to monitor with analog watchdog
+ * from sequencer channel and groups definition.
+ * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
+ * Example:
+ * LL_ADC_SetAnalogWDMonitChannels(
+ * ADC1, LL_ADC_AWD1,
+ * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1 (7)
+ * @arg @ref LL_ADC_CHANNEL_2 (7)
+ * @arg @ref LL_ADC_CHANNEL_3 (7)
+ * @arg @ref LL_ADC_CHANNEL_4 (7)
+ * @arg @ref LL_ADC_CHANNEL_5 (7)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (4)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (4)
+ *
+ * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
* (4) For ADC channel read back from ADC register,
* comparison with internal channel parameter to be done
@@ -1482,76 +1876,77 @@
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_AWD_DISABLE
* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)
- * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)
- * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)
- * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)
- * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)
- * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)
- * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ
+ * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
*
* (0) On STM32WB, parameter available only on analog watchdog number: AWD1.
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
*/
#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
(((__GROUP__) == LL_ADC_GROUP_REGULAR) \
@@ -1562,6 +1957,7 @@
: \
(((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
)
+#endif
/**
* @brief Helper macro to set the value of ADC analog watchdog threshold high
@@ -1993,9 +2389,9 @@
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @param CommonClock This parameter can be one of the following values:
- * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
- * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
- * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (*)
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 (*)
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 (*)
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
@@ -2008,11 +2404,17 @@
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
+ *
+ * (*) Value available on all STM32 devices except: STM32W10xxx, STM32W15xxx.
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock);
+#else
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
+#endif
}
/**
@@ -2022,9 +2424,9 @@
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
- * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
- * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (*)
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 (*)
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 (*)
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
@@ -2037,10 +2439,16 @@
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
+ *
+ * (*) Value available on all STM32 devices except: STM32W10xxx, STM32W15xxx.
*/
__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC));
+#else
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
+#endif
}
/**
@@ -2186,6 +2594,95 @@
* @{
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/**
+ * @brief Set ADC instance clock source and prescaler.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled.
+ * @rmtoll CFGR2 CKMODE LL_ADC_SetClock
+ * @param ADCx ADC instance
+ * @param ClockSource This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2)
+ * @arg @ref LL_ADC_CLOCK_ASYNC (1)
+ *
+ * (1) Asynchronous clock prescaler can be configured using
+ * function @ref LL_ADC_SetCommonClock().\n
+ * (2) Caution: This parameter has some clock ratio constraints:
+ * This configuration must be enabled only if PCLK has a 50%
+ * duty clock cycle (APB prescaler configured inside the RCC
+ * must be bypassed and the system clock must by 50% duty
+ * cycle).
+ * Refer to reference manual.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource)
+{
+ MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource);
+}
+
+/**
+ * @brief Get ADC instance clock source and prescaler.
+ * @rmtoll CFGR2 CKMODE LL_ADC_GetClock
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2)
+ * @arg @ref LL_ADC_CLOCK_ASYNC (1)
+ *
+ * (1) Asynchronous clock prescaler can be retrieved using
+ * function @ref LL_ADC_GetCommonClock().\n
+ * (2) Caution: This parameter has some clock ratio constraints:
+ * This configuration must be enabled only if PCLK has a 50%
+ * duty clock cycle (APB prescaler configured inside the RCC
+ * must be bypassed and the system clock must by 50% duty
+ * cycle).
+ * Refer to reference manual.
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetClock(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE));
+}
+#endif
+
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/**
+ * @brief Set ADC calibration factor in the mode single-ended
+ * or differential (for devices with differential mode available).
+ * @note This function is intended to set calibration parameters
+ * without having to perform a new calibration using
+ * @ref LL_ADC_StartCalibration().
+ * @note For devices with differential mode available:
+ * Calibration of offset is specific to each of
+ * single-ended and differential modes
+ * (calibration factor must be specified for each of these
+ * differential modes, if used afterwards and if the application
+ * requires their calibration).
+ * @note In case of setting calibration factors of both modes single ended
+ * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
+ * both calibration factors must be concatenated.
+ * To perform this processing, use helper macro
+ * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled, without calibration on going, without conversion
+ * on going on group regular.
+ * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n
+ * CALFACT CALFACT_D LL_ADC_SetCalibrationFactor
+ * @param ADCx ADC instance
+ * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t CalibrationFactor)
+{
+ MODIFY_REG(ADCx->CALFACT,
+ ADC_CALFACT_CALFACT,
+ CalibrationFactor);
+}
+#else
/**
* @brief Set ADC calibration factor in the mode single-ended
* or differential (for devices with differential mode available).
@@ -2212,8 +2709,10 @@
* @param ADCx ADC instance
* @param SingleDiff This parameter can be one of the following values:
* @arg @ref LL_ADC_SINGLE_ENDED
- * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
- * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
+ * @arg @ref LL_ADC_DIFFERENTIAL_ENDED (1)
+ * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED (1)
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
* @retval None
*/
@@ -2223,7 +2722,27 @@
SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/**
+ * @brief Get ADC calibration factor in the mode single-ended
+ * or differential (for devices with differential mode available).
+ * @note Calibration factors are set by hardware after performing
+ * a calibration run using function @ref LL_ADC_StartCalibration().
+ * @note For devices with differential mode available:
+ * Calibration of offset is specific to each of
+ * single-ended and differential modes
+ * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n
+ * CALFACT CALFACT_D LL_ADC_GetCalibrationFactor
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x7F
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT));
+}
+#else
/**
* @brief Get ADC calibration factor in the mode single-ended
* or differential (for devices with differential mode available).
@@ -2248,7 +2767,7 @@
/* containing other bits reserved for other purpose. */
return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
}
-
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Set ADC resolution.
* Refer to reference manual for alignments formats
@@ -2268,7 +2787,11 @@
*/
__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution);
+#else
MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
+#endif
}
/**
@@ -2285,7 +2808,11 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
+#else
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
+#endif
}
/**
@@ -2305,7 +2832,11 @@
*/
__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment);
+#else
MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
+#endif
}
/**
@@ -2320,7 +2851,11 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN));
+#else
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
+#endif
}
/**
@@ -2372,11 +2907,19 @@
* @param LowPowerMode This parameter can be one of the following values:
* @arg @ref LL_ADC_LP_MODE_NONE
* @arg @ref LL_ADC_LP_AUTOWAIT
+ * @arg @ref LL_ADC_LP_AUTOPOWEROFF (1)
+ * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (1)
+ *
+ * (1) On STM32WB serie, parameter available only on devices: STM32WB10xx, STM32WB15xx.
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF), LowPowerMode);
+#else
MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
+#endif
}
/**
@@ -2424,12 +2967,157 @@
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_LP_MODE_NONE
* @arg @ref LL_ADC_LP_AUTOWAIT
+ * @arg @ref LL_ADC_LP_AUTOPOWEROFF (1)
+ * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (1)
+ *
+ * (1) On STM32WB serie, parameter available only on devices: STM32WB10xx, STM32WB15xx.
*/
__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF)));
+#else
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
+#endif
}
+#if defined(ADC_SUPPORT_2_5_MSPS)
+/**
+ * @brief Set ADC trigger frequency mode.
+ * @note ADC trigger frequency mode must be set to low frequency when
+ * a duration is exceeded before ADC conversion start trigger event
+ * (between ADC enable and ADC conversion start trigger event
+ * or between two ADC conversion start trigger event).
+ * Duration value: Refer to device datasheet, parameter "tIdle".
+ * @note When ADC trigger frequency mode is set to low frequency,
+ * some rearm cycles are inserted before performing ADC conversion
+ * start, inducing a delay of 2 ADC clock cycles.
+ * @note Usage of ADC trigger frequency mode with ADC low power mode:
+ * - Low power mode auto wait: Only the first ADC conversion
+ * start trigger inserts the rearm delay.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR2 LFTRIG LL_ADC_SetTriggerFrequencyMode
+ * @param ADCx ADC instance
+ * @param TriggerFrequencyMode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
+ * @arg @ref LL_ADC_TRIGGER_FREQ_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef *ADCx, uint32_t TriggerFrequencyMode)
+{
+ MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, TriggerFrequencyMode);
+}
+
+/**
+ * @brief Get ADC trigger frequency mode.
+ * @rmtoll CFGR2 LFTRIG LL_ADC_GetTriggerFrequencyMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
+ * @arg @ref LL_ADC_TRIGGER_FREQ_LOW
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG));
+}
+
+#endif
+#if defined(ADC_SUPPORT_2_5_MSPS)
+/**
+ * @brief Set sampling time common to a group of channels.
+ * @note Unit: ADC clock cycles.
+ * @note On this STM32 serie, sampling time scope is on ADC instance:
+ * Sampling time common to all channels, independently
+ * of channels mapped on ADC group regular or injected.
+ * (on some other STM32 families, sampling time is channel wise)
+ * @note In case of internal channel (VrefInt, TempSensor, ...) to be
+ * converted:
+ * sampling time constraints must be respected (sampling time can be
+ * adjusted in function of ADC clock frequency and sampling time
+ * setting).
+ * Refer to device datasheet for timings values (parameters TS_vrefint,
+ * TS_temp, ...).
+ * @note Conversion time is the addition of sampling time and processing time.
+ * On this STM32 serie, ADC processing time is:
+ * - 12.5 ADC clock cycles at ADC resolution 12 bits
+ * - 10.5 ADC clock cycles at ADC resolution 10 bits
+ * - 8.5 ADC clock cycles at ADC resolution 8 bits
+ * - 6.5 ADC clock cycles at ADC resolution 6 bits
+ * @note In case of ADC conversion of internal channel (VrefInt,
+ * temperature sensor, ...), a sampling time minimum value
+ * is required.
+ * Refer to device datasheet.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll SMPR SMP1 LL_ADC_SetSamplingTimeCommonChannels\n
+ * @rmtoll SMPR SMP2 LL_ADC_SetSamplingTimeCommonChannels
+ * @param ADCx ADC instance
+ * @param SamplingTimeY This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
+ * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
+ * @param SamplingTime This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY, uint32_t SamplingTime)
+{
+ MODIFY_REG(ADCx->SMPR,
+ ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK),
+ SamplingTime << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));
+}
+
+/**
+ * @brief Get sampling time common to a group of channels.
+ * @note Unit: ADC clock cycles.
+ * @note On this STM32 serie, sampling time scope is on ADC instance:
+ * Sampling time common to all channels, independently
+ * of channels mapped on ADC group regular or injected.
+ * (on some other STM32 families, sampling time is channel wise)
+ * @note Conversion time is the addition of sampling time and processing time.
+ * On this STM32 serie, ADC processing time is:
+ * - 12.5 ADC clock cycles at ADC resolution 12 bits
+ * - 10.5 ADC clock cycles at ADC resolution 10 bits
+ * - 8.5 ADC clock cycles at ADC resolution 8 bits
+ * - 6.5 ADC clock cycles at ADC resolution 6 bits
+ * @rmtoll SMPR SMP1 LL_ADC_GetSamplingTimeCommonChannels\n
+ * @rmtoll SMPR SMP2 LL_ADC_GetSamplingTimeCommonChannels
+ * @param ADCx ADC instance
+ * @param SamplingTimeY This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
+ * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY)
+{
+ return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)))
+ >> (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));
+}
+
+#endif
+
+#if defined(ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC offset" not available on ADC peripheral of this STM32WB device */
+#else
/**
* @brief Set ADC selected offset number 1, 2, 3 or 4.
* @note This function set the 2 items of offset configuration:
@@ -2449,7 +3137,7 @@
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
- * @note On STM32WB, some fast channels are available: fast analog inputs
+ * @note On STM32WB (except devices: STM32WB10xx, STM32WB15xx), some fast channels are available: fast analog inputs
* coming from GPIO pads (ADC_IN1..5).
* @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n
* OFR1 OFFSET1 LL_ADC_SetOffset\n
@@ -2493,7 +3181,7 @@
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
* @arg @ref LL_ADC_CHANNEL_VBAT
*
- * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+ * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
* @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
@@ -2523,7 +3211,7 @@
* - To get the channel number in decimal format:
* process the returned value with the helper macro
* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
- * @note On STM32WB, some fast channels are available: fast analog inputs
+ * @note On STM32WB (except devices: STM32WB10xx, STM32WB15xx), some fast channels are available: fast analog inputs
* coming from GPIO pads (ADC_IN1..5).
* @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n
* OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n
@@ -2559,7 +3247,7 @@
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
* @arg @ref LL_ADC_CHANNEL_VBAT (4)
*
- * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+ * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
* (4) For ADC channel read back from ADC register,
* comparison with internal channel parameter to be done
@@ -2657,6 +3345,7 @@
return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
}
+#endif
/**
* @}
@@ -2676,6 +3365,10 @@
* STM32 families having this setting set by HW default value).
* In case of need to modify trigger edge, use
* function @ref LL_ADC_REG_SetTriggerEdge().
+ * @note On devices STM32WB10xx, STM32WB15xx: ADC trigger frequency mode must be set
+ * in function of frequency of ADC group regular conversion trigger.
+ * Refer to description of function
+ * "LL_ADC_SetTriggerFrequencyMode()".
* @note Availability of parameters of trigger sources from timer
* depends on timers availability on the selected device.
* @note On this STM32 serie, setting of this feature is conditioned to
@@ -2687,19 +3380,29 @@
* @param ADCx ADC instance
* @param TriggerSource This parameter can be one of the following values:
* @arg @ref LL_ADC_REG_TRIG_SOFTWARE
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO (1)
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (1)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (1)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4 (2)
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4 (2)
* @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
+ * (2) On STM32WB serie, parameter available only devices: STM32WB10xx, STM32WB15xx.
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource);
+#else
MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
+#endif
}
/**
@@ -2719,17 +3422,37 @@
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_REG_TRIG_SOFTWARE
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO (1)
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (1)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (1)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4 (2)
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4 (2)
* @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
+ * (2) On STM32WB serie, parameter available only devices: STM32WB10xx, STM32WB15xx.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);
+
+ /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
+ /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */
+ uint32_t ShiftExten = ((TriggerSource & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
+
+ /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL */
+ /* to match with triggers literals definition. */
+ return ((TriggerSource
+ & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR1_EXTSEL)
+ | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR1_EXTEN)
+ );
+#else
__IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
@@ -2742,6 +3465,7 @@
& (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
| ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
);
+#endif
}
/**
@@ -2757,7 +3481,11 @@
*/
__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL);
+#else
return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
+#endif
}
/**
@@ -2777,7 +3505,11 @@
*/
__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);
+#else
MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
+#endif
}
/**
@@ -2792,9 +3524,72 @@
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));
+#else
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
+#endif
}
+#if defined(ADC_SUPPORT_2_5_MSPS)
+/**
+ * @brief Set ADC group regular sequencer configuration flexibility.
+ * @note On this STM32 serie, ADC group regular sequencer both modes
+ * "fully configurable" or "not fully configurable" are
+ * available:
+ * - sequencer configured to fully configurable:
+ * sequencer length and each rank
+ * affectation to a channel are configurable.
+ * Refer to description of function
+ * @ref LL_ADC_REG_SetSequencerLength().
+ * - sequencer configured to not fully configurable:
+ * sequencer length and each rank affectation to a channel
+ * are fixed by channel HW number.
+ * Refer to description of function
+ * @ref LL_ADC_REG_SetSequencerChannels().
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable
+ * @param ADCx ADC instance
+ * @param Configurability This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_FIXED
+ * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef *ADCx, uint32_t Configurability)
+{
+ MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD, Configurability);
+}
+
+/**
+ * @brief Get ADC group regular sequencer configuration flexibility.
+ * @note On this STM32 serie, ADC group regular sequencer both modes
+ * "fully configurable" or "not fully configurable" are
+ * available:
+ * - sequencer configured to fully configurable:
+ * sequencer length and each rank
+ * affectation to a channel are configurable.
+ * Refer to description of function
+ * @ref LL_ADC_REG_SetSequencerLength().
+ * - sequencer configured to not fully configurable:
+ * sequencer length and each rank affectation to a channel
+ * are fixed by channel HW number.
+ * Refer to description of function
+ * @ref LL_ADC_REG_SetSequencerChannels().
+ * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_FIXED
+ * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD));
+}
+
+#endif
/**
* @brief Set ADC group regular sequencer length and scan direction.
* @note Description of ADC group regular sequencer features:
@@ -2822,13 +3617,30 @@
* highest channel number).
* Sequencer ranks are selected using
* function "LL_ADC_REG_SetSequencerChannels()".
+ * To set scan direction differently, refer to function
+ * "LL_ADC_REG_SetSequencerScanDirection()".
+ * @note On devices STM32WB10xx, STM32WB15xx: after calling functions
+ * @ref LL_ADC_REG_SetSequencerLength()
+ * or @ref LL_ADC_REG_SetSequencerRanks(),
+ * it is mandatory to wait for the assertion of CCRDY flag
+ * using "LL_ADC_IsActiveFlag_CCRDY()".
+ * Otherwise, performing some actions (configuration update,
+ * ADC conversion start, ... ) will be ignored.
+ * Refer to reference manual for more details.
* @note Sequencer disabled is equivalent to sequencer of 1 rank:
* ADC conversion on only 1 channel.
* @note On this STM32 serie, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
- * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
+ * @rmtoll CHSELR SQ1 LL_ADC_REG_SetSequencerLength\n
+ * CHSELR SQ2 LL_ADC_REG_SetSequencerLength\n
+ * CHSELR SQ3 LL_ADC_REG_SetSequencerLength\n
+ * CHSELR SQ4 LL_ADC_REG_SetSequencerLength\n
+ * CHSELR SQ5 LL_ADC_REG_SetSequencerLength\n
+ * CHSELR SQ6 LL_ADC_REG_SetSequencerLength\n
+ * CHSELR SQ7 LL_ADC_REG_SetSequencerLength\n
+ * CHSELR SQ8 LL_ADC_REG_SetSequencerLength
* @param ADCx ADC instance
* @param SequencerNbRanks This parameter can be one of the following values:
* @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
@@ -2839,19 +3651,25 @@
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (1)
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (1)
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (1)
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (1)
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (1)
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (1)
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (1)
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (1)
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ SET_BIT(ADCx->CHSELR, SequencerNbRanks);
+#else
MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
+#endif
}
/**
@@ -2881,9 +3699,18 @@
* highest channel number).
* Sequencer ranks are selected using
* function "LL_ADC_REG_SetSequencerChannels()".
+ * To set scan direction differently, refer to function
+ * "LL_ADC_REG_SetSequencerScanDirection()".
* @note Sequencer disabled is equivalent to sequencer of 1 rank:
* ADC conversion on only 1 channel.
- * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
+ * @rmtoll CHSELR SQ1 LL_ADC_REG_GetSequencerLength\n
+ * CHSELR SQ2 LL_ADC_REG_GetSequencerLength\n
+ * CHSELR SQ3 LL_ADC_REG_GetSequencerLength\n
+ * CHSELR SQ4 LL_ADC_REG_GetSequencerLength\n
+ * CHSELR SQ5 LL_ADC_REG_GetSequencerLength\n
+ * CHSELR SQ6 LL_ADC_REG_GetSequencerLength\n
+ * CHSELR SQ7 LL_ADC_REG_GetSequencerLength\n
+ * CHSELR SQ8 LL_ADC_REG_GetSequencerLength
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
@@ -2894,20 +3721,80 @@
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (1)
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (1)
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (1)
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (1)
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (1)
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (1)
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (1)
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (1)
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ __IO uint32_t ChannelsRanks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL);
+ uint32_t SequencerLength = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS;
+ uint32_t RankIndex;
+
+ /* Parse register for end of sequence identifier */
+ for(RankIndex = 0UL; RankIndex < (32U - 4U); RankIndex+=4U)
+ {
+ if((ChannelsRanks & (ADC_CHSELR_SQ2 << RankIndex)) == (ADC_CHSELR_SQ2 << RankIndex))
+ {
+ SequencerLength = (ADC_CHSELR_SQ2 << RankIndex);
+ break;
+ }
+ }
+
+ return SequencerLength;
+#else
return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
+#endif
}
+#if defined(ADC_SUPPORT_2_5_MSPS)
+/**
+ * @brief Set ADC group regular sequencer scan direction.
+ * @note On this STM32 serie, parameter relevant only is sequencer is set
+ * to mode not fully configurable,
+ * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
+ * @note On some other STM32 families, this setting is not available and
+ * the default scan direction is forward.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection
+ * @param ADCx ADC instance
+ * @param ScanDirection This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection)
+{
+ MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection);
+}
+
+/**
+ * @brief Get ADC group regular sequencer scan direction.
+ * @note On some other STM32 families, this setting is not available and
+ * the default scan direction is forward.
+ * @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR));
+}
+
+#endif
/**
* @brief Set ADC group regular sequencer discontinuous mode:
* sequence subdivided and scan conversions interrupted every selected
@@ -2926,18 +3813,24 @@
* @param SeqDiscont This parameter can be one of the following values:
* @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
* @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS (1)
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS (1)
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS (1)
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS (1)
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS (1)
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS (1)
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS (1)
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont);
+#else
MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
+#endif
}
/**
@@ -2950,17 +3843,23 @@
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
* @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS (1)
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS (1)
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS (1)
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS (1)
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS (1)
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS (1)
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS (1)
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN));
+#else
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
+#endif
}
/**
@@ -2979,6 +3878,14 @@
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @note On devices STM32WB10xx, STM32WB15xx: after calling functions
+ * @ref LL_ADC_REG_SetSequencerLength()
+ * or @ref LL_ADC_REG_SetSequencerRanks(),
+ * it is mandatory to wait for the assertion of CCRDY flag
+ * using "LL_ADC_IsActiveFlag_CCRDY()".
+ * Otherwise, performing some actions (configuration update,
+ * ADC conversion start, ... ) will be ignored.
+ * Refer to reference manual for more details.
* @note On this STM32 serie, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
@@ -3009,14 +3916,16 @@
* @arg @ref LL_ADC_REG_RANK_6
* @arg @ref LL_ADC_REG_RANK_7
* @arg @ref LL_ADC_REG_RANK_8
- * @arg @ref LL_ADC_REG_RANK_9
- * @arg @ref LL_ADC_REG_RANK_10
- * @arg @ref LL_ADC_REG_RANK_11
- * @arg @ref LL_ADC_REG_RANK_12
- * @arg @ref LL_ADC_REG_RANK_13
- * @arg @ref LL_ADC_REG_RANK_14
- * @arg @ref LL_ADC_REG_RANK_15
- * @arg @ref LL_ADC_REG_RANK_16
+ * @arg @ref LL_ADC_REG_RANK_9 (1)
+ * @arg @ref LL_ADC_REG_RANK_10 (1)
+ * @arg @ref LL_ADC_REG_RANK_11 (1)
+ * @arg @ref LL_ADC_REG_RANK_12 (1)
+ * @arg @ref LL_ADC_REG_RANK_13 (1)
+ * @arg @ref LL_ADC_REG_RANK_14 (1)
+ * @arg @ref LL_ADC_REG_RANK_15 (1)
+ * @arg @ref LL_ADC_REG_RANK_16 (1)
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0
* @arg @ref LL_ADC_CHANNEL_1 (7)
@@ -3041,12 +3950,21 @@
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
* @arg @ref LL_ADC_CHANNEL_VBAT
*
- * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+ * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Set bits with content of parameter "Channel" with bits position */
+ /* in register depending on parameter "Rank". */
+ /* Parameters "Rank" and "Channel" are used with masks because containing */
+ /* other bits reserved for other purpose. */
+ MODIFY_REG(ADCx->CHSELR,
+ ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
+ ((Channel & ADC_CHANNEL_ID_NUMBER_MASK_SEQ) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
+#else
/* Set bits with content of parameter "Channel" with bits position */
/* in register and register position depending on parameter "Rank". */
/* Parameters "Rank" and "Channel" are used with masks because containing */
@@ -3056,6 +3974,7 @@
MODIFY_REG(*preg,
ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
+#endif
}
/**
@@ -3104,14 +4023,16 @@
* @arg @ref LL_ADC_REG_RANK_6
* @arg @ref LL_ADC_REG_RANK_7
* @arg @ref LL_ADC_REG_RANK_8
- * @arg @ref LL_ADC_REG_RANK_9
- * @arg @ref LL_ADC_REG_RANK_10
- * @arg @ref LL_ADC_REG_RANK_11
- * @arg @ref LL_ADC_REG_RANK_12
- * @arg @ref LL_ADC_REG_RANK_13
- * @arg @ref LL_ADC_REG_RANK_14
- * @arg @ref LL_ADC_REG_RANK_15
- * @arg @ref LL_ADC_REG_RANK_16
+ * @arg @ref LL_ADC_REG_RANK_9 (1)
+ * @arg @ref LL_ADC_REG_RANK_10 (1)
+ * @arg @ref LL_ADC_REG_RANK_11 (1)
+ * @arg @ref LL_ADC_REG_RANK_12 (1)
+ * @arg @ref LL_ADC_REG_RANK_13 (1)
+ * @arg @ref LL_ADC_REG_RANK_14 (1)
+ * @arg @ref LL_ADC_REG_RANK_15 (1)
+ * @arg @ref LL_ADC_REG_RANK_16 (1)
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0
* @arg @ref LL_ADC_CHANNEL_1 (7)
@@ -3136,7 +4057,7 @@
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
* @arg @ref LL_ADC_CHANNEL_VBAT (4)
*
- * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+ * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
* (4) For ADC channel read back from ADC register,
* comparison with internal channel parameter to be done
@@ -3144,14 +4065,382 @@
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ return (uint32_t) ((READ_BIT(ADCx->CHSELR,
+ ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
+ >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
+ ) << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+ );
+#else
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
return (uint32_t)((READ_BIT(*preg,
ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
>> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
);
+#endif
}
+#if defined(ADC_SUPPORT_2_5_MSPS)
+/**
+ * @brief Set ADC group regular sequence: channel on rank corresponding to
+ * channel number.
+ * @note This function performs:
+ * - Channels ordering into each rank of scan sequence:
+ * rank of each channel is fixed by channel HW number
+ * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ * - Set channels selected by overwriting the current sequencer
+ * configuration.
+ * @note On this STM32 serie, ADC group regular sequencer both modes
+ * "fully configurable" or "not fully configurable"
+ * are available, they can be chosen using
+ * function @ref LL_ADC_REG_SetSequencerConfigurable().
+ * This function can be used with setting "not fully configurable".
+ * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
+ * and @ref LL_ADC_REG_SetSequencerLength().
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @note On STM32WB (except devices: STM32WB10xx, STM32WB15xx), some fast channels are available: fast analog inputs
+ * coming from GPIO pads (ADC_IN1..5).
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+ * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels\n
+ * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels\n
+ * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels\n
+ * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels\n
+ * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels\n
+ * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels\n
+ * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels\n
+ * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels\n
+ * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels\n
+ * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels\n
+ * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels\n
+ * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels\n
+ * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels\n
+ * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels\n
+ * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels\n
+ * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels\n
+ * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels\n
+ * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels\n
+ * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1 (7)
+ * @arg @ref LL_ADC_CHANNEL_2 (7)
+ * @arg @ref LL_ADC_CHANNEL_3 (7)
+ * @arg @ref LL_ADC_CHANNEL_4 (7)
+ * @arg @ref LL_ADC_CHANNEL_5 (7)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
+ * @arg @ref LL_ADC_CHANNEL_VBAT
+ *
+ * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+ * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+ /* Parameter "Channel" is used with masks because containing */
+ /* other bits reserved for other purpose. */
+ WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
+}
+
+/**
+ * @brief Add channel to ADC group regular sequence: channel on rank corresponding to
+ * channel number.
+ * @note This function performs:
+ * - Channels ordering into each rank of scan sequence:
+ * rank of each channel is fixed by channel HW number
+ * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ * - Set channels selected by adding them to the current sequencer
+ * configuration.
+ * @note On this STM32 serie, ADC group regular sequencer both modes
+ * "fully configurable" or "not fully configurable"
+ * are available, they can be chosen using
+ * function @ref LL_ADC_REG_SetSequencerConfigurable().
+ * This function can be used with setting "not fully configurable".
+ * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
+ * and @ref LL_ADC_REG_SetSequencerLength().
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @note On STM32WB (except devices: STM32WB10xx, STM32WB15xx), some fast channels are available: fast analog inputs
+ * coming from GPIO pads (ADC_IN1..5).
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+ * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd\n
+ * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd\n
+ * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd\n
+ * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd\n
+ * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd\n
+ * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd\n
+ * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd\n
+ * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd\n
+ * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd\n
+ * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd\n
+ * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd\n
+ * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd\n
+ * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd\n
+ * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd\n
+ * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd\n
+ * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd\n
+ * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd\n
+ * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd\n
+ * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1 (7)
+ * @arg @ref LL_ADC_CHANNEL_2 (7)
+ * @arg @ref LL_ADC_CHANNEL_3 (7)
+ * @arg @ref LL_ADC_CHANNEL_4 (7)
+ * @arg @ref LL_ADC_CHANNEL_5 (7)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
+ * @arg @ref LL_ADC_CHANNEL_VBAT
+ *
+ * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+ * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+ /* Parameter "Channel" is used with masks because containing */
+ /* other bits reserved for other purpose. */
+ SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
+}
+
+/**
+ * @brief Remove channel to ADC group regular sequence: channel on rank corresponding to
+ * channel number.
+ * @note This function performs:
+ * - Channels ordering into each rank of scan sequence:
+ * rank of each channel is fixed by channel HW number
+ * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ * - Set channels selected by removing them to the current sequencer
+ * configuration.
+ * @note On this STM32 serie, ADC group regular sequencer both modes
+ * "fully configurable" or "not fully configurable"
+ * are available, they can be chosen using
+ * function @ref LL_ADC_REG_SetSequencerConfigurable().
+ * This function can be used with setting "not fully configurable".
+ * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
+ * and @ref LL_ADC_REG_SetSequencerLength().
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @note On STM32WB (except devices: STM32WB10xx, STM32WB15xx), some fast channels are available: fast analog inputs
+ * coming from GPIO pads (ADC_IN1..5).
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+ * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem\n
+ * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem\n
+ * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem\n
+ * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem\n
+ * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem\n
+ * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem\n
+ * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem\n
+ * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem\n
+ * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem\n
+ * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem\n
+ * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem\n
+ * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem\n
+ * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem\n
+ * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem\n
+ * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem\n
+ * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem\n
+ * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem\n
+ * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem\n
+ * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1 (7)
+ * @arg @ref LL_ADC_CHANNEL_2 (7)
+ * @arg @ref LL_ADC_CHANNEL_3 (7)
+ * @arg @ref LL_ADC_CHANNEL_4 (7)
+ * @arg @ref LL_ADC_CHANNEL_5 (7)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
+ * @arg @ref LL_ADC_CHANNEL_VBAT
+ *
+ * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+ * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+ /* Parameter "Channel" is used with masks because containing */
+ /* other bits reserved for other purpose. */
+ CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
+}
+
+/**
+ * @brief Get ADC group regular sequence: channel on rank corresponding to
+ * channel number.
+ * @note This function performs:
+ * - Channels order reading into each rank of scan sequence:
+ * rank of each channel is fixed by channel HW number
+ * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ * @note On this STM32 serie, ADC group regular sequencer both modes
+ * "fully configurable" or "not fully configurable"
+ * are available, they can be chosen using
+ * function @ref LL_ADC_REG_SetSequencerConfigurable().
+ * This function can be used with setting "not fully configurable".
+ * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
+ * and @ref LL_ADC_REG_SetSequencerLength().
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @note On STM32WB (except devices: STM32WB10xx, STM32WB15xx), some fast channels are available: fast analog inputs
+ * coming from GPIO pads (ADC_IN1..5).
+*/
+//TBC
+/*
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @note One or several values can be retrieved.
+ * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+ * @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels\n
+ * CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels\n
+ * CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels\n
+ * CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels\n
+ * CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels\n
+ * CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels\n
+ * CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels\n
+ * CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels\n
+ * CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels\n
+ * CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels\n
+ * CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels\n
+ * CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels\n
+ * CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels\n
+ * CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels\n
+ * CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels\n
+ * CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels\n
+ * CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels\n
+ * CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels\n
+ * CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels
+ * @param ADCx ADC instance
+ * @retval Returned value can be a combination of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1 (7)
+ * @arg @ref LL_ADC_CHANNEL_2 (7)
+ * @arg @ref LL_ADC_CHANNEL_3 (7)
+ * @arg @ref LL_ADC_CHANNEL_4 (7)
+ * @arg @ref LL_ADC_CHANNEL_5 (7)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
+ * @arg @ref LL_ADC_CHANNEL_VBAT
+ *
+ * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+ * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx)
+{
+ uint32_t ChannelsBitfield = READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL);
+
+ return ( (((ChannelsBitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0)
+ | (((ChannelsBitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1)
+ | (((ChannelsBitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2)
+ | (((ChannelsBitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3)
+ | (((ChannelsBitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4)
+ | (((ChannelsBitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5)
+ | (((ChannelsBitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6)
+ | (((ChannelsBitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7)
+ | (((ChannelsBitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8)
+ | (((ChannelsBitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9)
+ | (((ChannelsBitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10)
+ | (((ChannelsBitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11)
+ | (((ChannelsBitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12)
+ | (((ChannelsBitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13)
+ | (((ChannelsBitfield & ADC_CHSELR_CHSEL14) >> ADC_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14)
+ | (((ChannelsBitfield & ADC_CHSELR_CHSEL15) >> ADC_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15)
+ | (((ChannelsBitfield & ADC_CHSELR_CHSEL16) >> ADC_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16)
+ | (((ChannelsBitfield & ADC_CHSELR_CHSEL17) >> ADC_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17)
+ | (((ChannelsBitfield & ADC_CHSELR_CHSEL18) >> ADC_CHSELR_CHSEL18_BITOFFSET_POS) * LL_ADC_CHANNEL_18)
+ );
+}
+#endif
/**
* @brief Set ADC continuous conversion mode on ADC group regular.
* @note Description of ADC continuous conversion mode:
@@ -3173,7 +4462,11 @@
*/
__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);
+#else
MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
+#endif
}
/**
@@ -3190,7 +4483,11 @@
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));
+#else
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
+#endif
}
/**
@@ -3228,7 +4525,11 @@
*/
__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG, DMATransfer);
+#else
MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
+#endif
}
/**
@@ -3261,7 +4562,11 @@
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG));
+#else
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
+#endif
}
@@ -3287,7 +4592,11 @@
*/
__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);
+#else
MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
+#endif
}
/**
@@ -3301,13 +4610,20 @@
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));
+#else
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
+#endif
}
/**
* @}
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
* @{
*/
@@ -3526,7 +4842,7 @@
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
- * @note On STM32WB, some fast channels are available: fast analog inputs
+ * @note On STM32WB (except devices: STM32WB10xx, STM32WB15xx), some fast channels are available: fast analog inputs
* coming from GPIO pads (ADC_IN1..5).
* @note On this STM32 serie, setting of this feature is conditioned to
* ADC state:
@@ -3566,7 +4882,7 @@
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
* @arg @ref LL_ADC_CHANNEL_VBAT
*
- * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+ * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
* @retval None
*/
@@ -3631,7 +4947,7 @@
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
* @arg @ref LL_ADC_CHANNEL_VBAT (4)
*
- * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+ * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
* (4) For ADC channel read back from ADC register,
* comparison with internal channel parameter to be done
@@ -3776,7 +5092,7 @@
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
- * @note On STM32WB, some fast channels are available: fast analog inputs
+ * @note On STM32WB (except devices: STM32WB10xx, STM32WB15xx), some fast channels are available: fast analog inputs
* coming from GPIO pads (ADC_IN1..5).
* @note On this STM32 serie, setting of this feature is conditioned to
* ADC state:
@@ -3834,7 +5150,7 @@
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
* @arg @ref LL_ADC_CHANNEL_VBAT
*
- * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+ * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
* @param Rank2_Channel This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0
@@ -3860,7 +5176,7 @@
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
* @arg @ref LL_ADC_CHANNEL_VBAT
*
- * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+ * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
* @param Rank3_Channel This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0
@@ -3886,7 +5202,7 @@
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
* @arg @ref LL_ADC_CHANNEL_VBAT
*
- * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+ * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
* @param Rank4_Channel This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0
@@ -3912,7 +5228,7 @@
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
* @arg @ref LL_ADC_CHANNEL_VBAT
*
- * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+ * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
* @retval None
*/
@@ -3954,10 +5270,12 @@
* @}
*/
+#endif /* ADC_SUPPORT_2_5_MSPS */
/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
* @{
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
/**
* @brief Set sampling time of the selected ADC channel
* Unit: ADC clock cycles.
@@ -4028,7 +5346,94 @@
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
* @arg @ref LL_ADC_CHANNEL_VBAT
*
- * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+ * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+ * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
+ * @param SamplingTimeY This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
+ * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTimeY)
+{
+ /* Parameter "Channel" is used with masks because containing */
+ /* other bits reserved for other purpose. */
+ MODIFY_REG(ADCx->SMPR,
+ (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS),
+ (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS) & (SamplingTimeY & ADC_SAMPLING_TIME_CH_MASK)
+ );
+}
+#else
+/**
+ * @brief Set sampling time of the selected ADC channel
+ * Unit: ADC clock cycles.
+ * @note On this device, sampling time is on channel scope: independently
+ * of channel mapped on ADC group regular or injected.
+ * @note In case of internal channel (VrefInt, TempSensor, ...) to be
+ * converted:
+ * sampling time constraints must be respected (sampling time can be
+ * adjusted in function of ADC clock frequency and sampling time
+ * setting).
+ * Refer to device datasheet for timings values (parameters TS_vrefint,
+ * TS_temp, ...).
+ * @note Conversion time is the addition of sampling time and processing time.
+ * On this STM32 serie, ADC processing time is:
+ * - 12.5 ADC clock cycles at ADC resolution 12 bits
+ * - 10.5 ADC clock cycles at ADC resolution 10 bits
+ * - 8.5 ADC clock cycles at ADC resolution 8 bits
+ * - 6.5 ADC clock cycles at ADC resolution 6 bits
+ * @note In case of ADC conversion of internal channel (VrefInt,
+ * temperature sensor, ...), a sampling time minimum value
+ * is required.
+ * Refer to device datasheet.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1 (7)
+ * @arg @ref LL_ADC_CHANNEL_2 (7)
+ * @arg @ref LL_ADC_CHANNEL_3 (7)
+ * @arg @ref LL_ADC_CHANNEL_4 (7)
+ * @arg @ref LL_ADC_CHANNEL_5 (7)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
+ * @arg @ref LL_ADC_CHANNEL_VBAT
+ *
+ * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
* @param SamplingTime This parameter can be one of the following values:
* @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
@@ -4043,6 +5448,14 @@
*/
__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Parameter "Channel" is used with masks because containing */
+ /* other bits reserved for other purpose. */
+ MODIFY_REG(ADCx->SMPR,
+ (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS),
+ (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS) & (SamplingTimeY & ADC_SAMPLING_TIME_CH_MASK)
+ );
+#else
/* Set bits with content of parameter "SamplingTime" with bits position */
/* in register and register position depending on parameter "Channel". */
/* Parameter "Channel" is used with masks because containing */
@@ -4052,8 +5465,11 @@
MODIFY_REG(*preg,
ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
+#endif
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
+#if defined (ADC_SUPPORT_2_5_MSPS)
/**
* @brief Get sampling time of the selected ADC channel
* Unit: ADC clock cycles.
@@ -4109,7 +5525,82 @@
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
* @arg @ref LL_ADC_CHANNEL_VBAT
*
- * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+ * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
+ * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
+ * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+ __IO uint32_t smpr = READ_REG(ADCx->SMPR);
+
+ /* Retrieve sampling time bit corresponding to the selected channel */
+ /* and shift it to position 0. */
+ uint32_t smp_channel_posbit0 = ((smpr & ADC_SAMPLING_TIME_CH_MASK)
+ >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + ADC_SMPR_SMPSEL0_BITOFFSET_POS) & 0x1FUL));
+
+ /* Select sampling time bitfield depending on sampling time bit value 0 or 1. */
+ return( (~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1)
+ | (smp_channel_posbit0 * LL_ADC_SAMPLINGTIME_COMMON_2) );
+}
+#else
+/**
+ * @brief Get sampling time of the selected ADC channel
+ * Unit: ADC clock cycles.
+ * @note On this device, sampling time is on channel scope: independently
+ * of channel mapped on ADC group regular or injected.
+ * @note Conversion time is the addition of sampling time and processing time.
+ * On this STM32 serie, ADC processing time is:
+ * - 12.5 ADC clock cycles at ADC resolution 12 bits
+ * - 10.5 ADC clock cycles at ADC resolution 10 bits
+ * - 8.5 ADC clock cycles at ADC resolution 8 bits
+ * - 6.5 ADC clock cycles at ADC resolution 6 bits
+ * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1 (7)
+ * @arg @ref LL_ADC_CHANNEL_2 (7)
+ * @arg @ref LL_ADC_CHANNEL_3 (7)
+ * @arg @ref LL_ADC_CHANNEL_4 (7)
+ * @arg @ref LL_ADC_CHANNEL_5 (7)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
+ * @arg @ref LL_ADC_CHANNEL_VBAT
+ *
+ * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
@@ -4123,14 +5614,31 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ __IO uint32_t smpr = READ_REG(ADCx->SMPR);
+
+ /* Retrieve sampling time bit corresponding to the selected channel */
+ /* and shift it to position 0. */
+ uint32_t smp_channel_posbit0 = ((smpr & ADC_SAMPLING_TIME_CH_MASK)
+ >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + ADC_SMPR_SMPSEL0_BITOFFSET_POS) & 0x1FUL));
+
+ /* Select sampling time bitfield depending on sampling time bit value 0 or 1. */
+ return( (~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1)
+ | (smp_channel_posbit0 * LL_ADC_SAMPLINGTIME_COMMON_2) );
+#else
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
return (uint32_t)(READ_BIT(*preg,
ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
>> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
);
+#endif
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC channel differential mode" not available on ADC peripheral of this STM32WB device */
+#else
/**
* @brief Set mode single-ended or differential input of the selected
* ADC channel.
@@ -4234,6 +5742,7 @@
return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @}
*/
@@ -4290,80 +5799,89 @@
* @param AWDChannelGroup This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD_DISABLE
* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)
- * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)
- * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)
- * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)
- * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)
- * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)
- * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ
+ * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
*
* (0) On STM32WB, parameter available only on analog watchdog number: AWD1.
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Prevent unused argument(s) compilation warning */
+ (void)(AWDy);
+
+ MODIFY_REG(ADCx->CFGR1,
+ (LL_ADC_AWD1 & ADC_AWD_CR_ALL_CHANNEL_MASK),
+ AWDChannelGroup & LL_ADC_AWD1);
+#else
/* Set bits with content of parameter "AWDChannelGroup" with bits position */
/* in register and register position depending on parameter "AWDy". */
/* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
@@ -4374,6 +5892,7 @@
MODIFY_REG(*preg,
(AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
AWDChannelGroup & AWDy);
+#endif
}
/**
@@ -4425,81 +5944,113 @@
* @param ADCx ADC instance
* @param AWDy This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD1
- * @arg @ref LL_ADC_AWD2 (1)
- * @arg @ref LL_ADC_AWD3 (1)
+ * @arg @ref LL_ADC_AWD2 (1)(2)
+ * @arg @ref LL_ADC_AWD3 (1)(2)
*
* (1) On this AWD number, monitored channel can be retrieved
* if only 1 channel is programmed (or none or all channels).
* This function cannot retrieve monitored channel if
* multiple channels are programmed simultaneously
* by bitfield.
+ * (2) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_AWD_DISABLE
* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ (1)
*
* (0) On STM32WB, parameter available only on analog watchdog number: AWD1.
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
*/
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Prevent unused argument(s) compilation warning */
+ (void)(AWDy);
+
+ uint32_t AnalogWDMonitChannels = (READ_BIT(ADCx->CFGR1, LL_ADC_AWD1) & LL_ADC_AWD1 & ADC_AWD_CR_ALL_CHANNEL_MASK);
+
+ /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */
+ /* (parameter value LL_ADC_AWD_DISABLE). */
+ /* Else, the selected AWD is enabled and is monitoring a group of channels */
+ /* or a single channel. */
+ if(AnalogWDMonitChannels != 0UL)
+ {
+ if((AnalogWDMonitChannels & ADC_CFGR1_AWD1SGL) == 0UL)
+ {
+ /* AWD monitoring a group of channels */
+ AnalogWDMonitChannels = (AnalogWDMonitChannels
+ & (~(ADC_CFGR1_AWD1CH))
+ );
+ }
+ else
+ {
+ /* AWD monitoring a single channel */
+ AnalogWDMonitChannels = (AnalogWDMonitChannels
+ | (0x01UL << (AnalogWDMonitChannels >> ADC_CFGR1_AWD1CH_Pos))
+ );
+ }
+ }
+
+ return AnalogWDMonitChannels;
+#else
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
+ ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
@@ -4552,6 +6103,7 @@
}
return AnalogWDMonitChannels;
+#endif
}
/**
@@ -4600,8 +6152,10 @@
* @param ADCx ADC instance
* @param AWDy This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD1
- * @arg @ref LL_ADC_AWD2
- * @arg @ref LL_ADC_AWD3
+ * @arg @ref LL_ADC_AWD2 (1)
+ * @arg @ref LL_ADC_AWD3 (1)
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
* @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
@@ -4614,11 +6168,20 @@
/* "AWDy". */
/* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
/* containing other bits reserved for other purpose. */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Prevent unused argument(s) compilation warning */
+ (void)(AWDy);
+
+ MODIFY_REG(ADCx->TR1,
+ ADC_TR1_HT1 | ADC_TR1_LT1,
+ (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
+#else
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
MODIFY_REG(*preg,
ADC_TR1_HT1 | ADC_TR1_LT1,
(AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
+#endif
}
/**
@@ -4667,8 +6230,10 @@
* @param ADCx ADC instance
* @param AWDy This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD1
- * @arg @ref LL_ADC_AWD2
- * @arg @ref LL_ADC_AWD3
+ * @arg @ref LL_ADC_AWD2 (1)
+ * @arg @ref LL_ADC_AWD3 (1)
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @param AWDThresholdsHighLow This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
@@ -4683,11 +6248,20 @@
/* "AWDThresholdsHighLow" and "AWDy". */
/* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
/* containing other bits reserved for other purpose. */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Prevent unused argument(s) compilation warning */
+ (void)(AWDy);
+
+ MODIFY_REG(ADCx->TR1,
+ AWDThresholdsHighLow,
+ AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
+#else
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
MODIFY_REG(*preg,
AWDThresholdsHighLow,
AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
+#endif
}
/**
@@ -4710,8 +6284,10 @@
* @param ADCx ADC instance
* @param AWDy This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD1
- * @arg @ref LL_ADC_AWD2
- * @arg @ref LL_ADC_AWD3
+ * @arg @ref LL_ADC_AWD2 (1)
+ * @arg @ref LL_ADC_AWD3 (1)
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @param AWDThresholdsHighLow This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
@@ -4720,18 +6296,31 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Prevent unused argument(s) compilation warning */
+ (void)(AWDy);
+
+ return (uint32_t)(READ_BIT(ADCx->TR1,
+ (AWDThresholdsHighLow | ADC_TR1_LT1))
+ >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR1_LT1))
+ );
+#else
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
return (uint32_t)(READ_BIT(*preg,
(AWDThresholdsHighLow | ADC_TR1_LT1))
>> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR1_LT1))
);
+#endif
}
/**
* @}
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC oversampling" not available on ADC peripheral of this STM32WB device */
+#else
/** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
* @{
*/
@@ -4756,14 +6345,20 @@
* @param OvsScope This parameter can be one of the following values:
* @arg @ref LL_ADC_OVS_DISABLE
* @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
- * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
- * @arg @ref LL_ADC_OVS_GRP_INJECTED
- * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
+ * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED (1)
+ * @arg @ref LL_ADC_OVS_GRP_INJECTED (1)
+ * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED (1)
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope);
+#else
MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
+#endif
}
/**
@@ -4782,13 +6377,19 @@
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_OVS_DISABLE
* @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
- * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
- * @arg @ref LL_ADC_OVS_GRP_INJECTED
- * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
+ * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED (1)
+ * @arg @ref LL_ADC_OVS_GRP_INJECTED (1)
+ * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED (1)
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
*/
__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE));
+#else
return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
+#endif
}
/**
@@ -4815,7 +6416,11 @@
*/
__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont);
+#else
MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
+#endif
}
/**
@@ -4834,7 +6439,11 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS));
+#else
return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
+#endif
}
/**
@@ -4921,10 +6530,14 @@
* @}
*/
+#endif /* ADC_SUPPORT_2_5_MSPS */
/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
* @{
*/
+#if defined(ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC deep power down" not available on ADC peripheral of this STM32WB device */
+#else
/**
* @brief Put ADC instance in deep power down state.
* @note In case of ADC calibration necessary: When ADC is in deep-power-down
@@ -4979,6 +6592,7 @@
{
return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Enable ADC instance internal voltage regulator.
@@ -5100,6 +6714,37 @@
return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
}
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/**
+ * @brief Start ADC calibration in the mode single-ended
+ * or differential (for devices with differential mode available).
+ * @note On this STM32 serie, a minimum number of ADC clock cycles
+ * are required between ADC end of calibration and ADC enable.
+ * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
+ * @note For devices with differential mode available:
+ * Calibration of offset is specific to each of
+ * single-ended and differential modes
+ * (calibration run must be performed for each of these
+ * differential modes, if used afterwards and if the application
+ * requires their calibration).
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled.
+ * @rmtoll CR ADCAL LL_ADC_StartCalibration\n
+ * CR ADCALDIF LL_ADC_StartCalibration
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR,
+ ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_ADCAL);
+}
+#else
/**
* @brief Start ADC calibration in the mode single-ended
* or differential (for devices with differential mode available).
@@ -5132,6 +6777,7 @@
ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Get ADC calibration state.
@@ -5300,6 +6946,9 @@
* @}
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
* @{
*/
@@ -5512,6 +7161,7 @@
* @}
*/
+#endif /* ADC_SUPPORT_2_5_MSPS */
/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
* @{
*/
@@ -5530,6 +7180,23 @@
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
}
+#if defined(ADC_SUPPORT_2_5_MSPS)
+/**
+ * @brief Get flag ADC channel configuration ready.
+ * @note Duration of ADC channel configuration ready: CCRDY handshake
+ * requires 1APB + 2 ADC + 3 APB cycles after the channel configuration
+ * has been changed.
+ * @rmtoll ISR CCRDY LL_ADC_IsActiveFlag_CCRDY
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_CCRDY(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL);
+}
+
+#else
+#endif
/**
* @brief Get flag ADC group regular end of unitary conversion.
* @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
@@ -5574,6 +7241,9 @@
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
}
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/**
* @brief Get flag ADC group injected end of unitary conversion.
* @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
@@ -5607,6 +7277,7 @@
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Get flag ADC analog watchdog 1 flag
* @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
@@ -5640,6 +7311,19 @@
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
}
+#if defined(ADC_SUPPORT_2_5_MSPS)
+/**
+ * @brief Get flag ADC end of calibration.
+ * @rmtoll ISR EOCAL LL_ADC_IsActiveFlag_EOCAL
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOCAL) == (LL_ADC_FLAG_EOCAL)) ? 1UL : 0UL);
+}
+
+#endif
/**
* @brief Clear flag ADC ready.
* @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
@@ -5654,6 +7338,20 @@
WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
}
+#if defined(ADC_SUPPORT_2_5_MSPS)
+/**
+ * @brief Clear flag ADC channel configuration ready.
+ * @rmtoll ISR CCRDY LL_ADC_ClearFlag_CCRDY
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_CCRDY(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_CCRDY);
+}
+
+#else
+#endif
/**
* @brief Clear flag ADC group regular end of unitary conversion.
* @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
@@ -5698,6 +7396,9 @@
WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
}
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/**
* @brief Clear flag ADC group injected end of unitary conversion.
* @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
@@ -5731,6 +7432,7 @@
WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Clear flag ADC analog watchdog 1.
* @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
@@ -5764,6 +7466,19 @@
WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
}
+#if defined(ADC_SUPPORT_2_5_MSPS)
+/**
+ * @brief Clear flag ADC end of calibration.
+ * @rmtoll ISR EOCAL LL_ADC_ClearFlag_EOCAL
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOCAL(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOCAL);
+}
+
+#endif
/**
* @}
*/
@@ -5783,6 +7498,20 @@
SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
}
+#if defined(ADC_SUPPORT_2_5_MSPS)
+/**
+ * @brief Enable interruption ADC channel configuration ready.
+ * @rmtoll IER ADRDYIE LL_ADC_EnableIT_CCRDY
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_CCRDY(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY);
+}
+
+#else
+#endif
/**
* @brief Enable interruption ADC group regular end of unitary conversion.
* @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
@@ -5827,6 +7556,9 @@
SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
}
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/**
* @brief Enable interruption ADC group injected end of unitary conversion.
* @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
@@ -5860,6 +7592,7 @@
SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Enable interruption ADC analog watchdog 1.
* @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
@@ -5893,6 +7626,19 @@
SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
}
+#if defined(ADC_SUPPORT_2_5_MSPS)
+/**
+ * @brief Enable interruption ADC end of calibration.
+ * @rmtoll IER EOCALIE LL_ADC_EnableIT_EOCAL
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_EOCAL(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
+}
+
+#endif
/**
* @brief Disable interruption ADC ready.
* @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
@@ -5904,6 +7650,20 @@
CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
}
+#if defined(ADC_SUPPORT_2_5_MSPS)
+/**
+ * @brief Disable interruption ADC channel configuration ready.
+ * @rmtoll IER ADRDYIE LL_ADC_DisableIT_CCRDY
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_CCRDY(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY);
+}
+
+#else
+#endif
/**
* @brief Disable interruption ADC group regular end of unitary conversion.
* @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
@@ -5948,6 +7708,9 @@
CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
}
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/**
* @brief Disable interruption ADC group regular end of unitary conversion.
* @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
@@ -5981,6 +7744,7 @@
CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Disable interruption ADC analog watchdog 1.
* @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
@@ -6014,6 +7778,19 @@
CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
}
+#if defined(ADC_SUPPORT_2_5_MSPS)
+/**
+ * @brief Disable interruption ADC end of calibration.
+ * @rmtoll IER EOCALIE LL_ADC_DisableIT_EOCAL
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_EOCAL(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
+}
+
+#endif
/**
* @brief Get state of interruption ADC ready
* (0: interrupt disabled, 1: interrupt enabled).
@@ -6026,6 +7803,20 @@
return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
}
+#if defined(ADC_SUPPORT_2_5_MSPS)
+/**
+ * @brief Get state of interruption ADC channel configuration ready.
+ * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_CCRDY
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_CCRDY(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL);
+}
+
+#else
+#endif
/**
* @brief Get state of interruption ADC group regular end of unitary conversion
* (0: interrupt disabled, 1: interrupt enabled).
@@ -6074,6 +7865,9 @@
return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
}
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/**
* @brief Get state of interruption ADC group injected end of unitary conversion
* (0: interrupt disabled, 1: interrupt enabled).
@@ -6110,6 +7904,7 @@
return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Get state of interruption ADC analog watchdog 1
* (0: interrupt disabled, 1: interrupt enabled).
@@ -6146,6 +7941,20 @@
return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
}
+#if defined(ADC_SUPPORT_2_5_MSPS)
+/**
+ * @brief Get state of interruption ADC end of calibration
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER EOCALIE LL_ADC_IsEnabledIT_EOCAL
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL)) ? 1UL : 0UL);
+}
+
+#endif
/**
* @}
*/
@@ -6172,10 +7981,14 @@
ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/* Initialization of some features of ADC instance and ADC group injected */
ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
+#endif
/**
* @}
*/
diff --git a/Inc/stm32wbxx_ll_bus.h b/Inc/stm32wbxx_ll_bus.h
index 09b3d15..98e2b5d 100644
--- a/Inc/stm32wbxx_ll_bus.h
+++ b/Inc/stm32wbxx_ll_bus.h
@@ -101,7 +101,9 @@
#endif
#define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN
#define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN
+#if defined(ADC_SUPPORT_5_MSPS)
#define LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN
+#endif
#if defined(AES1)
#define LL_AHB2_GRP1_PERIPH_AES1 RCC_AHB2ENR_AES1EN
#endif
@@ -173,12 +175,19 @@
* @{
*/
#define LL_APB2_GRP1_PERIPH_ALL (0xFFFFFFFFU)
-
+
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define LL_APB2_GRP1_PERIPH_ADC RCC_APB2ENR_ADCEN
+#endif
#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
+#if defined(TIM16)
#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
+#endif
+#if defined(TIM17)
#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
+#endif
#if defined(SAI1)
#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
#endif
@@ -225,7 +234,9 @@
#endif
#define LL_C2_AHB2_GRP1_PERIPH_GPIOE RCC_C2AHB2ENR_GPIOEEN
#define LL_C2_AHB2_GRP1_PERIPH_GPIOH RCC_C2AHB2ENR_GPIOHEN
+#if defined(ADC_SUPPORT_5_MSPS)
#define LL_C2_AHB2_GRP1_PERIPH_ADC RCC_C2AHB2ENR_ADCEN
+#endif
#if defined(AES1)
#define LL_C2_AHB2_GRP1_PERIPH_AES1 RCC_C2AHB2ENR_AES1EN
#endif
@@ -287,11 +298,18 @@
/** @defgroup BUS_LL_EC_C2_APB2_GRP1_PERIPH C2 APB2 GRP1 PERIPH
* @{
*/
+#if defined(ADC_SUPPORT_2_5_MSPS)
+#define LL_C2_APB2_GRP1_PERIPH_ADC RCC_C2APB2ENR_ADCEN
+#endif
#define LL_C2_APB2_GRP1_PERIPH_TIM1 RCC_C2APB2ENR_TIM1EN
#define LL_C2_APB2_GRP1_PERIPH_SPI1 RCC_C2APB2ENR_SPI1EN
#define LL_C2_APB2_GRP1_PERIPH_USART1 RCC_C2APB2ENR_USART1EN
+#if defined(TIM16)
#define LL_C2_APB2_GRP1_PERIPH_TIM16 RCC_C2APB2ENR_TIM16EN
+#endif
+#if defined(TIM17)
#define LL_C2_APB2_GRP1_PERIPH_TIM17 RCC_C2APB2ENR_TIM17EN
+#endif
#if defined(SAI1)
#define LL_C2_APB2_GRP1_PERIPH_SAI1 RCC_C2APB2ENR_SAI1EN
#endif
@@ -304,7 +322,9 @@
* @{
*/
#define LL_C2_APB3_GRP1_PERIPH_BLE RCC_C2APB3ENR_BLEEN
+#if defined(RCC_802_SUPPORT)
#define LL_C2_APB3_GRP1_PERIPH_802 RCC_C2APB3ENR_802EN
+#endif
/**
* @}
*/
@@ -335,12 +355,13 @@
* AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -359,12 +380,13 @@
* AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @note (*) Not supported by all the devices
* @retval uint32_t
-*/
+ */
__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->AHB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
@@ -379,12 +401,13 @@
* AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB1ENR, Periphs);
@@ -400,12 +423,13 @@
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
{
SET_BIT(RCC->AHB1RSTR, Periphs);
@@ -421,12 +445,13 @@
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB1RSTR, Periphs);
@@ -442,13 +467,14 @@
* AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockSleep
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -468,13 +494,14 @@
* AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockSleep
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB1SMENR, Periphs);
@@ -502,13 +529,14 @@
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
- * @arg @ref LL_AHB2_GRP1_PERIPH_AES1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*)
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -532,13 +560,14 @@
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
- * @arg @ref LL_AHB2_GRP1_PERIPH_AES1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*)
+ * @note (*) Not supported by all the devices
* @retval uint32_t
-*/
+ */
__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->AHB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
@@ -558,13 +587,14 @@
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
- * @arg @ref LL_AHB2_GRP1_PERIPH_AES1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*)
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB2ENR, Periphs);
@@ -585,13 +615,14 @@
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
- * @arg @ref LL_AHB2_GRP1_PERIPH_AES1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*)
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
{
SET_BIT(RCC->AHB2RSTR, Periphs);
@@ -612,13 +643,14 @@
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
- * @arg @ref LL_AHB2_GRP1_PERIPH_AES1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*)
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB2RSTR, Periphs);
@@ -638,13 +670,14 @@
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
- * @arg @ref LL_AHB2_GRP1_PERIPH_AES1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*)
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -668,13 +701,14 @@
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
- * @arg @ref LL_AHB2_GRP1_PERIPH_AES1
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*)
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB2SMENR, Periphs);
@@ -698,15 +732,16 @@
* AHB3ENR IPCCEN LL_AHB3_GRP1_EnableClock\n
* AHB3ENR FLASHEN LL_AHB3_GRP1_EnableClock
* @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_PKA
* @arg @ref LL_AHB3_GRP1_PERIPH_AES2
* @arg @ref LL_AHB3_GRP1_PERIPH_RNG
* @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
* @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
* @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -726,15 +761,16 @@
* AHB3ENR IPCCEN LL_AHB3_GRP1_IsEnabledClock\n
* AHB3ENR FLASHEN LL_AHB3_GRP1_IsEnabledClock
* @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_PKA
* @arg @ref LL_AHB3_GRP1_PERIPH_AES2
* @arg @ref LL_AHB3_GRP1_PERIPH_RNG
* @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
* @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
* @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+ * @note (*) Not supported by all the devices
* @retval uint32_t
-*/
+ */
__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->AHB3ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
@@ -750,15 +786,16 @@
* AHB3ENR IPCCEN LL_AHB3_GRP1_DisableClock\n
* AHB3ENR FLASHEN LL_AHB3_GRP1_DisableClock
* @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_PKA
* @arg @ref LL_AHB3_GRP1_PERIPH_AES2
* @arg @ref LL_AHB3_GRP1_PERIPH_RNG
* @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
* @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
* @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB3ENR, Periphs);
@@ -775,15 +812,16 @@
* AHB3RSTR FLASHRST LL_AHB3_GRP1_ForceReset
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB3_GRP1_PERIPH_ALL
- * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_PKA
* @arg @ref LL_AHB3_GRP1_PERIPH_AES2
* @arg @ref LL_AHB3_GRP1_PERIPH_RNG
* @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
* @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
* @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
{
SET_BIT(RCC->AHB3RSTR, Periphs);
@@ -800,15 +838,16 @@
* AHB3RSTR FLASHRST LL_AHB3_GRP1_ReleaseReset
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
- * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_PKA
* @arg @ref LL_AHB3_GRP1_PERIPH_AES2
* @arg @ref LL_AHB3_GRP1_PERIPH_RNG
* @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
* @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
* @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB3RSTR, Periphs);
@@ -823,14 +862,15 @@
* AHB3SMENR SRAM2SMEN LL_AHB3_GRP1_EnableClockSleep\n
* AHB3SMENR FLASHSMEN LL_AHB3_GRP1_EnableClockSleep
* @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_PKA
* @arg @ref LL_AHB3_GRP1_PERIPH_AES2
* @arg @ref LL_AHB3_GRP1_PERIPH_RNG
* @arg @ref LL_AHB3_GRP1_PERIPH_SRAM2
+ * @note (*) Not supported by all the devices
* @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -849,14 +889,15 @@
* AHB3SMENR SRAM2SMEN LL_AHB3_GRP1_DisableClockSleep\n
* AHB3SMENR FLASHSMEN LL_AHB3_GRP1_DisableClockSleep
* @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_PKA
* @arg @ref LL_AHB3_GRP1_PERIPH_AES2
* @arg @ref LL_AHB3_GRP1_PERIPH_RNG
* @arg @ref LL_AHB3_GRP1_PERIPH_SRAM2
* @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB3SMENR, Periphs);
@@ -884,17 +925,18 @@
* APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_LCD
+ * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
- * @arg @ref LL_APB1_GRP1_PERIPH_CRS
- * @arg @ref LL_APB1_GRP1_PERIPH_USB
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -909,10 +951,11 @@
* @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock\n
* APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock
* @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -936,17 +979,18 @@
* APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_LCD
+ * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
- * @arg @ref LL_APB1_GRP1_PERIPH_CRS
- * @arg @ref LL_APB1_GRP1_PERIPH_USB
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+ * @note (*) Not supported by all the devices
* @retval uint32_t
-*/
+ */
__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->APB1ENR1, Periphs) == (Periphs)) ? 1UL : 0UL);
@@ -957,10 +1001,11 @@
* @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock\n
* APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock
* @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+ * @note (*) Not supported by all the devices
* @retval uint32_t
-*/
+ */
__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->APB1ENR2, Periphs) == (Periphs)) ? 1UL : 0UL);
@@ -979,17 +1024,18 @@
* APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_LCD
+ * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
- * @arg @ref LL_APB1_GRP1_PERIPH_CRS
- * @arg @ref LL_APB1_GRP1_PERIPH_USB
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_ (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB1ENR1, Periphs);
@@ -1000,10 +1046,11 @@
* @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock\n
* APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock
* @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB1ENR2, Periphs);
@@ -1022,15 +1069,16 @@
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP1_PERIPH_ALL
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_LCD
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+ * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
- * @arg @ref LL_APB1_GRP1_PERIPH_CRS
- * @arg @ref LL_APB1_GRP1_PERIPH_USB
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
{
SET_BIT(RCC->APB1RSTR1, Periphs);
@@ -1042,10 +1090,11 @@
* APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP2_PERIPH_ALL
- * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
{
SET_BIT(RCC->APB1RSTR2, Periphs);
@@ -1064,15 +1113,16 @@
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP1_PERIPH_ALL
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_LCD
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+ * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
- * @arg @ref LL_APB1_GRP1_PERIPH_CRS
- * @arg @ref LL_APB1_GRP1_PERIPH_USB
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB1RSTR1, Periphs);
@@ -1084,10 +1134,11 @@
* APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP2_PERIPH_ALL
- * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB1RSTR2, Periphs);
@@ -1107,17 +1158,18 @@
* APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockSleep
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_LCD
+ * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
- * @arg @ref LL_APB1_GRP1_PERIPH_CRS
- * @arg @ref LL_APB1_GRP1_PERIPH_USB
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -1132,10 +1184,11 @@
* @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockSleep\n
* APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockSleep
* @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -1159,17 +1212,18 @@
* APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockSleep
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_LCD
+ * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
- * @arg @ref LL_APB1_GRP1_PERIPH_CRS
- * @arg @ref LL_APB1_GRP1_PERIPH_USB
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB1SMENR1, Periphs);
@@ -1180,10 +1234,11 @@
* @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockSleep\n
* APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockSleep
* @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB1SMENR2, Periphs);
@@ -1199,21 +1254,24 @@
/**
* @brief Enable APB2 peripherals clock.
- * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
+ * @rmtoll APB2ENR ADCEN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
* APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
* APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
* APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
* APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
* APB2ENR SAI1EN LL_APB2_GRP1_EnableClock
* @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC (*)
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -1225,21 +1283,24 @@
/**
* @brief Check if APB2 peripheral clock is enabled or not
- * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
+ * @rmtoll APB2ENR ADCEN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
* APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
* APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
* APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
* APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
* APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock
* @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC (*)
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
+ * @note (*) Not supported by all the devices
* @retval uint32_t
-*/
+ */
__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->APB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
@@ -1247,21 +1308,24 @@
/**
* @brief Disable APB2 peripherals clock.
- * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
+ * @rmtoll APB2ENR ADCEN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
* APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
* APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
* APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
* APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
* APB2ENR SAI1EN LL_APB2_GRP1_DisableClock
* @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC (*)
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB2ENR, Periphs);
@@ -1269,7 +1333,8 @@
/**
* @brief Force APB2 peripherals reset.
- * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
+ * @rmtoll APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
@@ -1277,14 +1342,16 @@
* APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC (*)
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
{
SET_BIT(RCC->APB2RSTR, Periphs);
@@ -1292,7 +1359,8 @@
/**
* @brief Release APB2 peripherals reset.
- * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
+ * @rmtoll APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
* APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
* APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
* APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
@@ -1300,14 +1368,16 @@
* APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC (*)
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB2RSTR, Periphs);
@@ -1315,21 +1385,24 @@
/**
* @brief Enable APB2 peripherals clock during Low Power (Sleep) mode.
- * @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockSleep\n
+ * @rmtoll APB2SMENR ADCSMEN LL_APB2_GRP1_EnableClockSleep\n
+ * APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockSleep\n
* APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockSleep\n
* APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockSleep\n
* APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockSleep\n
* APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockSleep\n
* APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockSleep
* @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC (*)
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -1341,21 +1414,24 @@
/**
* @brief Disable APB2 peripherals clock during Low Power (Sleep) mode.
- * @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockSleep\n
+ * @rmtoll APB2SMENR ADCSMEN LL_APB2_GRP1_DisableClockSleep\n
+ * APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockSleep\n
* APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockSleep\n
* APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockSleep\n
* APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockSleep\n
* APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockSleep\n
* APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockSleep
* @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC (*)
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB2SMENR, Periphs);
@@ -1375,7 +1451,7 @@
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB3_GRP1_PERIPH_RF
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs)
{
SET_BIT(RCC->APB3RSTR, Periphs);
@@ -1387,7 +1463,7 @@
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB3_GRP1_PERIPH_RF
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB3RSTR, Periphs);
@@ -1410,13 +1486,14 @@
* C2AHB1ENR TSCEN LL_C2_AHB1_GRP1_EnableClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 (*)
* @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
* @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1
* @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs)
{
@@ -1437,13 +1514,14 @@
* C2AHB1ENR TSCEN LL_C2_AHB1_GRP1_IsEnabledClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 (*)
* @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
* @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1
* @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC
+ * @note (*) Not supported by all the devices
* @retval uint32_t
-*/
+ */
__STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
{
@@ -1460,13 +1538,14 @@
* C2AHB1ENR TSCEN LL_C2_AHB1_GRP1_DisableClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 (*)
* @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
* @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1
* @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs)
{
@@ -1483,13 +1562,14 @@
* C2AHB1SMENR TSCSMEN LL_C2_AHB1_GRP1_EnableClockSleep
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 (*)
* @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
* @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1
* @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
{
@@ -1510,13 +1590,14 @@
* C2AHB1SMENR TSCSMEN LL_C2_AHB1_GRP1_DisableClockSleep
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 (*)
* @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
* @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1
* @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
{
@@ -1545,13 +1626,14 @@
* @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA
* @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB
* @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD (*)
* @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE
* @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH
- * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC
- * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1
+ * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC (*)
+ * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1 (*)
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -1575,13 +1657,14 @@
* @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA
* @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB
* @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD (*)
* @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE
* @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH
- * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC
- * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1
+ * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC (*)
+ * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1 (*)
+ * @note (*) Not supported by all the devices
* @retval uint32_t
-*/
+ */
__STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->C2AHB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
@@ -1601,13 +1684,14 @@
* @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA
* @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB
* @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD (*)
* @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE
* @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH
- * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC
- * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1
+ * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC (*)
+ * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1 (*)
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->C2AHB2ENR, Periphs);
@@ -1627,13 +1711,14 @@
* @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA
* @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB
* @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD (*)
* @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE
* @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH
- * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC
- * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1
+ * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC (*)
+ * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1 (*)
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -1657,13 +1742,14 @@
* @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA
* @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB
* @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD (*)
* @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE
* @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH
- * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC
- * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1
+ * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC (*)
+ * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1 (*)
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->C2AHB2SMENR, Periphs);
@@ -1693,7 +1779,7 @@
* @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC
* @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH
* @retval None
-*/
+ */
__STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -1719,7 +1805,7 @@
* @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC
* @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH
* @retval uint32_t
-*/
+ */
__STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->C2AHB3ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
@@ -1741,7 +1827,7 @@
* @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC
* @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH
* @retval None
-*/
+ */
__STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->C2AHB3ENR, Periphs);
@@ -1761,7 +1847,7 @@
* @arg @ref LL_C2_AHB3_GRP1_PERIPH_SRAM2
* @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH
* @retval None
-*/
+ */
__STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -1785,7 +1871,7 @@
* @arg @ref LL_C2_AHB3_GRP1_PERIPH_SRAM2
* @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH
* @retval None
-*/
+ */
__STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->C2AHB3SMENR, Periphs);
@@ -1812,16 +1898,17 @@
* C2APB1ENR1 LPTIM1EN LL_C2_APB1_GRP1_EnableClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD
+ * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD (*)
* @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB
- * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2
+ * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 (*)
* @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3
- * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS
- * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB
+ * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 (*)
+ * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS (*)
+ * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB (*)
* @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -1836,10 +1923,11 @@
* @rmtoll C2APB1ENR2 LPUART1EN LL_C2_APB1_GRP2_EnableClock\n
* C2APB1ENR2 LPTIM2EN LL_C2_APB1_GRP2_EnableClock
* @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1
+ * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 (*)
* @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -1862,16 +1950,17 @@
* C2APB1ENR1 LPTIM1EN LL_C2_APB1_GRP1_IsEnabledClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD
+ * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD (*)
* @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB
- * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2
+ * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 (*)
* @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3
- * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS
- * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB
+ * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 (*)
+ * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS (*)
+ * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB (*)
* @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1
+ * @note (*) Not supported by all the devices
* @retval uint32_t
-*/
+ */
__STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->C2APB1ENR1, Periphs) == (Periphs)) ? 1UL : 0UL);
@@ -1882,10 +1971,11 @@
* @rmtoll C2APB1ENR2 LPUART1EN LL_C2_APB1_GRP2_IsEnabledClock\n
* C2APB1ENR2 LPTIM2EN LL_C2_APB1_GRP2_IsEnabledClock
* @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1
+ * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 (*)
* @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2
+ * @note (*) Not supported by all the devices
* @retval uint32_t
-*/
+ */
__STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->C2APB1ENR2, Periphs) == (Periphs)) ? 1UL : 0UL);
@@ -1904,16 +1994,17 @@
* C2APB1ENR1 LPTIM1EN LL_C2_APB1_GRP1_DisableClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD
+ * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD (*)
* @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB
- * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2
+ * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 (*)
* @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3
- * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS
- * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB
+ * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 (*)
+ * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS (*)
+ * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB (*)
* @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->C2APB1ENR1, Periphs);
@@ -1924,10 +2015,11 @@
* @rmtoll C2APB1ENR2 LPUART1EN LL_C2_APB1_GRP2_DisableClock\n
* C2APB1ENR2 LPTIM2EN LL_C2_APB1_GRP2_DisableClock
* @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1
+ * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 (*)
* @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->C2APB1ENR2, Periphs);
@@ -1946,16 +2038,17 @@
* C2APB1SMENR1 LPTIM1SMEN LL_C2_APB1_GRP1_EnableClockSleep
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD
+ * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD (*)
* @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB
- * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2
+ * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 (*)
* @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3
- * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS
- * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB
+ * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 (*)
+ * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS (*)
+ * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB (*)
* @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -1970,10 +2063,11 @@
* @rmtoll C2APB1SMENR2 LPUART1SMEN LL_C2_APB1_GRP2_EnableClockSleep\n
* C2APB1SMENR2 LPTIM2SMEN LL_C2_APB1_GRP2_EnableClockSleep
* @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1
+ * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 (*)
* @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -1996,16 +2090,17 @@
* C2APB1SMENR1 LPTIM1SMEN LL_C2_APB1_GRP1_DisableClockSleep
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD
+ * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD (*)
* @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB
- * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2
+ * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 (*)
* @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3
- * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS
- * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB
+ * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 (*)
+ * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS (*)
+ * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB (*)
* @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->C2APB1SMENR1, Periphs);
@@ -2016,10 +2111,11 @@
* @rmtoll C2APB1SMENR2 LPUART1SMEN LL_C2_APB1_GRP2_DisableClockSleep\n
* C2APB1SMENR2 LPTIM2SMEN LL_C2_APB1_GRP2_DisableClockSleep
* @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1
+ * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 (*)
* @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->C2APB1SMENR2, Periphs);
@@ -2035,21 +2131,24 @@
/**
* @brief Enable C2APB2 peripherals clock.
- * @rmtoll C2APB2ENR TIM1EN LL_C2_APB2_GRP1_EnableClock\n
+ * @rmtoll C2APB2ENR ADCEN LL_C2_APB2_GRP1_EnableClock\n
+ * C2APB2ENR TIM1EN LL_C2_APB2_GRP1_EnableClock\n
* C2APB2ENR SPI1EN LL_C2_APB2_GRP1_EnableClock\n
* C2APB2ENR USART1EN LL_C2_APB2_GRP1_EnableClock\n
* C2APB2ENR TIM16EN LL_C2_APB2_GRP1_EnableClock\n
* C2APB2ENR TIM17EN LL_C2_APB2_GRP1_EnableClock\n
* C2APB2ENR SAI1EN LL_C2_APB2_GRP1_EnableClock
* @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC (*)
* @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1
* @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16
- * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17
- * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 (*)
+ * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1 (*)
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -2061,21 +2160,24 @@
/**
* @brief Check if C2APB2 peripheral clock is enabled or not
- * @rmtoll C2APB2ENR TIM1EN LL_C2_APB2_GRP1_IsEnabledClock\n
+ * @rmtoll C2APB2ENR ADCEN LL_C2_APB2_GRP1_IsEnabledClock\n
+ * C2APB2ENR TIM1EN LL_C2_APB2_GRP1_IsEnabledClock\n
* C2APB2ENR SPI1EN LL_C2_APB2_GRP1_IsEnabledClock\n
* C2APB2ENR USART1EN LL_C2_APB2_GRP1_IsEnabledClock\n
* C2APB2ENR TIM16EN LL_C2_APB2_GRP1_IsEnabledClock\n
* C2APB2ENR TIM17EN LL_C2_APB2_GRP1_IsEnabledClock\n
* C2APB2ENR SAI1EN LL_C2_APB2_GRP1_IsEnabledClock
* @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC (*)
* @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1
* @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16
- * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17
- * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 (*)
+ * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1 (*)
+ * @note (*) Not supported by all the devices
* @retval uint32_t
-*/
+ */
__STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->C2APB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
@@ -2083,21 +2185,24 @@
/**
* @brief Disable C2APB2 peripherals clock.
- * @rmtoll C2APB2ENR TIM1EN LL_C2_APB2_GRP1_DisableClock\n
+ * @rmtoll C2APB2ENR ADCEN LL_C2_APB2_GRP1_DisableClock\n
+ * C2APB2ENR TIM1EN LL_C2_APB2_GRP1_DisableClock\n
* C2APB2ENR SPI1EN LL_C2_APB2_GRP1_DisableClock\n
* C2APB2ENR USART1EN LL_C2_APB2_GRP1_DisableClock\n
* C2APB2ENR TIM16EN LL_C2_APB2_GRP1_DisableClock\n
* C2APB2ENR TIM17EN LL_C2_APB2_GRP1_DisableClock\n
* C2APB2ENR SAI1EN LL_C2_APB2_GRP1_DisableClock
* @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC (*)
* @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1
* @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16
- * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17
- * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 (*)
+ * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1 (*)
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->C2APB2ENR, Periphs);
@@ -2105,21 +2210,24 @@
/**
* @brief Enable C2APB2 peripherals clock during Low Power (Sleep) mode.
- * @rmtoll C2APB2SMENR TIM1SMEN LL_C2_APB2_GRP1_EnableClockSleep\n
+ * @rmtoll C2APB2SMENR ADCSMEN LL_C2_APB2_GRP1_EnableClockSleep\n
+ * C2APB2SMENR TIM1SMEN LL_C2_APB2_GRP1_EnableClockSleep\n
* C2APB2SMENR SPI1SMEN LL_C2_APB2_GRP1_EnableClockSleep\n
* C2APB2SMENR USART1SMEN LL_C2_APB2_GRP1_EnableClockSleep\n
* C2APB2SMENR TIM16SMEN LL_C2_APB2_GRP1_EnableClockSleep\n
* C2APB2SMENR TIM17SMEN LL_C2_APB2_GRP1_EnableClockSleep\n
* C2APB2SMENR SAI1SMEN LL_C2_APB2_GRP1_EnableClockSleep
* @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC (*)
* @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1
* @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16
- * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17
- * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 (*)
+ * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1 (*)
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -2131,21 +2239,24 @@
/**
* @brief Disable C2APB2 peripherals clock during Low Power (Sleep) mode.
- * @rmtoll C2APB2SMENR TIM1SMEN LL_C2_APB2_GRP1_DisableClockSleep\n
+ * @rmtoll C2APB2SMENR ADCSMEN LL_C2_APB2_GRP1_DisableClockSleep\n
+ * C2APB2SMENR TIM1SMEN LL_C2_APB2_GRP1_DisableClockSleep\n
* C2APB2SMENR SPI1SMEN LL_C2_APB2_GRP1_DisableClockSleep\n
* C2APB2SMENR USART1SMEN LL_C2_APB2_GRP1_DisableClockSleep\n
* C2APB2SMENR TIM16SMEN LL_C2_APB2_GRP1_DisableClockSleep\n
* C2APB2SMENR TIM17SMEN LL_C2_APB2_GRP1_DisableClockSleep\n
* C2APB2SMENR SAI1SMEN LL_C2_APB2_GRP1_DisableClockSleep
* @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC (*)
* @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1
* @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16
- * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17
- * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 (*)
+ * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1 (*)
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->C2APB2SMENR, Periphs);
@@ -2162,12 +2273,13 @@
/**
* @brief Enable C2APB3 peripherals clock.
* @rmtoll C2APB3ENR BLEEN LL_C2_APB3_GRP1_EnableClock\n
- * C2APB3ENR 802EN LL_C2_APB3_GRP1_EnableClock
+ * C2APB3ENR 802EN LL_C2_APB3_GRP1_EnableClock (*)
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE
- * @arg @ref LL_C2_APB3_GRP1_PERIPH_802
+ * @arg @ref LL_C2_APB3_GRP1_PERIPH_802 (*)
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -2180,12 +2292,13 @@
/**
* @brief Check if C2APB3 peripheral clock is enabled or not
* @rmtoll C2APB3ENR BLEEN LL_C2_APB3_GRP1_IsEnabledClock\n
- * C2APB3ENR 802EN LL_C2_APB3_GRP1_IsEnabledClock
+ * C2APB3ENR 802EN LL_C2_APB3_GRP1_IsEnabledClock (*)
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE
- * @arg @ref LL_C2_APB3_GRP1_PERIPH_802
+ * @arg @ref LL_C2_APB3_GRP1_PERIPH_802 (*)
+ * @note (*) Not supported by all the devices
* @retval uint32_t
-*/
+ */
__STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->C2APB3ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
@@ -2194,12 +2307,13 @@
/**
* @brief Disable C2APB3 peripherals clock.
* @rmtoll C2APB3ENR BLEEN LL_C2_APB3_GRP1_DisableClock\n
- * C2APB3ENR 802EN LL_C2_APB3_GRP1_DisableClock
+ * C2APB3ENR 802EN LL_C2_APB3_GRP1_DisableClock (*)
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE
- * @arg @ref LL_C2_APB3_GRP1_PERIPH_802
+ * @arg @ref LL_C2_APB3_GRP1_PERIPH_802 (*)
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->C2APB3ENR, Periphs);
@@ -2208,12 +2322,13 @@
/**
* @brief Enable C2APB3 peripherals clock during Low Power (Sleep) mode.
* @rmtoll C2APB3SMENR BLESMEN LL_C2_APB3_GRP1_EnableClockSleep\n
- * C2APB3SMENR 802SMEN LL_C2_APB3_GRP1_EnableClockSleep
+ * C2APB3SMENR 802SMEN LL_C2_APB3_GRP1_EnableClockSleep (*)
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE
- * @arg @ref LL_C2_APB3_GRP1_PERIPH_802
+ * @arg @ref LL_C2_APB3_GRP1_PERIPH_802 (*)
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -2226,12 +2341,13 @@
/**
* @brief Disable C2APB3 peripherals clock during Low Power (Sleep) mode.
* @rmtoll C2APB3SMENR BLESMEN LL_C2_APB3_GRP1_DisableClockSleep\n
- * C2APB3SMENR 802SMEN LL_C2_APB3_GRP1_DisableClockSleep
+ * C2APB3SMENR 802SMEN LL_C2_APB3_GRP1_DisableClockSleep (*)
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE
- * @arg @ref LL_C2_APB3_GRP1_PERIPH_802
+ * @arg @ref LL_C2_APB3_GRP1_PERIPH_802 (*)
+ * @note (*) Not supported by all the devices
* @retval None
-*/
+ */
__STATIC_INLINE void LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->C2APB3SMENR, Periphs);
diff --git a/Inc/stm32wbxx_ll_comp.h b/Inc/stm32wbxx_ll_comp.h
index 127db62..9785ee3 100644
--- a/Inc/stm32wbxx_ll_comp.h
+++ b/Inc/stm32wbxx_ll_comp.h
@@ -138,7 +138,7 @@
/** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection
* @{
*/
-#define LL_COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1 (except device STM32WB35xx), pin PB4 for COMP2) */
+#define LL_COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1 (except device STM32WB35xx), pin PB4 for COMP2). Note: On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. */
#define LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */
#define LL_COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1) /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2) */
/**
@@ -153,7 +153,7 @@
#define LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 3/4 VrefInt */
#define LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN ) /*!< Comparator input minus connected to VrefInt */
#define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PA9 for COMP1, pin PB3 for COMP2) */
-#define LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1 (except device STM32WB35xx), pin PB7 for COMP2) */
+#define LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1 (except device STM32WB35xx), pin PB7 for COMP2). Note: On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. */
#define LL_COMP_INPUT_MINUS_IO3 ( COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO3 (pin PA0 for COMP1, pin PA2 for COMP2) */
#define LL_COMP_INPUT_MINUS_IO4 (COMP_CSR_INMESEL_1 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO4 (pin PA4 for COMP1, pin PA4 for COMP2) */
#define LL_COMP_INPUT_MINUS_IO5 (COMP_CSR_INMESEL_1 | COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO5 (pin PA5 for COMP1, pin PA5 for COMP2) */
@@ -307,7 +307,7 @@
*/
__STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
{
- /* Note: On this STM32 serie, window mode can be set only */
+ /* Note: On this STM32 series, window mode can be set only */
/* from COMP instance: COMP2. */
MODIFY_REG(COMPxy_COMMON->CSR, COMP_CSR_WINMODE, WindowMode);
}
@@ -378,7 +378,7 @@
* @note In case of comparator input selected to be connected to IO:
* GPIO pins are specific to each comparator instance.
* Refer to description of parameters or to reference manual.
- * @note On this STM32 serie, scaler bridge is configurable:
+ * @note On this STM32 series, scaler bridge is configurable:
* to optimize power consumption, this function enables the
* voltage scaler bridge only when required
* (when selecting comparator input based on VrefInt: VrefInt or
@@ -464,7 +464,7 @@
* @note In case of comparator input selected to be connected to IO:
* GPIO pins are specific to each comparator instance.
* Refer to description of parameters or to reference manual.
- * @note On this STM32 serie, scaler bridge is configurable:
+ * @note On this STM32 series, scaler bridge is configurable:
* to optimize power consumption, this function enables the
* voltage scaler bridge only when required
* (when selecting comparator input based on VrefInt: VrefInt or
diff --git a/Inc/stm32wbxx_ll_exti.h b/Inc/stm32wbxx_ll_exti.h
index d2c5cbb..37b702d 100644
--- a/Inc/stm32wbxx_ll_exti.h
+++ b/Inc/stm32wbxx_ll_exti.h
@@ -180,7 +180,7 @@
#define LL_EXTI_LINE_ALL_32_63 (LL_EXTI_LINE_33 | LL_EXTI_LINE_36 | LL_EXTI_LINE_37 | \
LL_EXTI_LINE_38 | LL_EXTI_LINE_39 | LL_EXTI_LINE_40 | \
LL_EXTI_LINE_41 | LL_EXTI_LINE_42 | LL_EXTI_LINE_44 | \
- LL_EXTI_LINE_45 | LL_EXTI_LINE_48) /*!< All Extended line not reserved*/
+ LL_EXTI_LINE_45 | LL_EXTI_LINE_46 | LL_EXTI_LINE_48) /*!< All Extended line not reserved*/
#else
#define LL_EXTI_LINE_ALL_32_63 (LL_EXTI_LINE_33 | LL_EXTI_LINE_36 | LL_EXTI_LINE_37 | \
LL_EXTI_LINE_38 | LL_EXTI_LINE_39 | LL_EXTI_LINE_40 | \
diff --git a/Inc/stm32wbxx_ll_i2c.h b/Inc/stm32wbxx_ll_i2c.h
index 44fb4fe..29160c3 100644
--- a/Inc/stm32wbxx_ll_i2c.h
+++ b/Inc/stm32wbxx_ll_i2c.h
@@ -1163,7 +1163,7 @@
}
/**
- * @brief Get the SMBus Extented Cumulative Clock TimeoutB setting.
+ * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting.
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
diff --git a/Inc/stm32wbxx_ll_pwr.h b/Inc/stm32wbxx_ll_pwr.h
index 852c3a0..4c8a15a 100644
--- a/Inc/stm32wbxx_ll_pwr.h
+++ b/Inc/stm32wbxx_ll_pwr.h
@@ -90,10 +90,12 @@
#endif
#define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1
#define LL_PWR_SCR_CC2HF PWR_SCR_CC2HF
-#define LL_PWR_SCR_C802AF PWR_SCR_C802AF
#define LL_PWR_SCR_CBLEAF PWR_SCR_CBLEAF
#define LL_PWR_SCR_CCRPEF PWR_SCR_CCRPEF
+#if defined(PWR_CR3_E802A)
+#define LL_PWR_SCR_C802AF PWR_SCR_C802AF
#define LL_PWR_SCR_C802WUF PWR_SCR_C802WUF
+#endif
#define LL_PWR_SCR_CBLEWUF PWR_SCR_CBLEWUF
#if defined(PWR_CR5_SMPSEN)
#define LL_PWR_SCR_CBORHF PWR_SCR_CBORHF
@@ -145,9 +147,12 @@
/* Radio (BLE or 802.15.4) flags */
#define LL_PWR_FLAG_BLEWU PWR_SR1_BLEWUF /* BLE wakeup interrupt flag */
-#define LL_PWR_FLAG_802WU PWR_SR1_802WUF /* 802.15.4 wakeup interrupt flag */
+
#define LL_PWR_FLAG_BLEA PWR_SR1_BLEAF /* BLE end of activity interrupt flag */
+#if defined(PWR_CR3_E802A)
+#define LL_PWR_FLAG_802WU PWR_SR1_802WUF /* 802.15.4 wakeup interrupt flag */
#define LL_PWR_FLAG_802A PWR_SR1_802AF /* 802.15.4 end of activity interrupt flag */
+#endif
#define LL_PWR_FLAG_CRPE PWR_SR1_CRPEF /* Critical radio phase end of activity interrupt flag */
#define LL_PWR_FLAG_CRP PWR_EXTSCR_CRPF /* Critical radio system phase */
@@ -179,7 +184,9 @@
*/
#define LL_PWR_MODE_STOP0 (0x000000000U)
#define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_0)
+#if defined(PWR_SUPPORT_STOP2)
#define LL_PWR_MODE_STOP2 (PWR_CR1_LPMS_1)
+#endif
#define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_1 | PWR_CR1_LPMS_0)
#define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_2)
/**
@@ -521,9 +528,11 @@
* @param LowPowerMode This parameter can be one of the following values:
* @arg @ref LL_PWR_MODE_STOP0
* @arg @ref LL_PWR_MODE_STOP1
- * @arg @ref LL_PWR_MODE_STOP2
+ * @arg @ref LL_PWR_MODE_STOP2 (*)
* @arg @ref LL_PWR_MODE_STANDBY
* @arg @ref LL_PWR_MODE_SHUTDOWN
+ *
+ * (*) Not available on devices STM32WB15xx, STM32WB10xx
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
@@ -537,9 +546,11 @@
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_MODE_STOP0
* @arg @ref LL_PWR_MODE_STOP1
- * @arg @ref LL_PWR_MODE_STOP2
+ * @arg @ref LL_PWR_MODE_STOP2 (*)
* @arg @ref LL_PWR_MODE_STANDBY
* @arg @ref LL_PWR_MODE_SHUTDOWN
+ *
+ * (*) Not available on devices STM32WB15xx, STM32WB10xx
*/
__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
{
@@ -557,7 +568,7 @@
__STATIC_INLINE void LL_PWR_SetFlashPowerModeLPRun(uint32_t FlashLowPowerMode)
{
/* Unlock bit FPDR */
- WRITE_REG(PWR->CR1, 0x0000C1B0U);
+ WRITE_REG(PWR->CR1, 0x0000C1B0UL);
/* Update bit FPDR */
MODIFY_REG(PWR->CR1, PWR_CR1_FPDR, FlashLowPowerMode);
@@ -640,7 +651,7 @@
* @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
* @arg @ref LL_PWR_PVM_VDDA_1_62V
*
- * (*) Not available on devices STM32WB50xx, STM32WB30xx
+ * (*) Not available on devices STM32WB50xx, STM32WB30xx, STM32WB15xx, STM32WB10xx
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
@@ -656,7 +667,7 @@
* @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
* @arg @ref LL_PWR_PVM_VDDA_1_62V
*
- * (*) Not available on devices STM32WB50xx, STM32WB30xx
+ * (*) Not available on devices STM32WB50xx, STM32WB30xx, STM32WB15xx, STM32WB10xx
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
@@ -672,7 +683,7 @@
* @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
* @arg @ref LL_PWR_PVM_VDDA_1_62V
*
- * (*) Not available on devices STM32WB50xx, STM32WB30xx
+ * (*) Not available on devices STM32WB50xx, STM32WB30xx, STM32WB15xx, STM32WB10xx
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)
@@ -808,7 +819,9 @@
}
/**
- * @brief Enable SRAM2 content retention in Standby mode
+ * @brief Enable SRAM2a content retention in Standby mode
+ * @note On devices STM32WB15xx, STM32WB10xx, retention is extended
+ * to SRAM1, SRAM2a and SRAM2b.
* @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention
* @retval None
*/
@@ -818,7 +831,9 @@
}
/**
- * @brief Disable SRAM2 content retention in Standby mode
+ * @brief Disable SRAM2a content retention in Standby mode
+ * @note On devices STM32WB15xx, STM32WB10xx, retention is extended
+ * to SRAM1, SRAM2a and SRAM2b.
* @rmtoll CR3 RRS LL_PWR_DisableSRAM2Retention
* @retval None
*/
@@ -829,6 +844,8 @@
/**
* @brief Check if SRAM2 content retention in Standby mode is enabled
+ * @note On devices STM32WB15xx, STM32WB10xx, retention is extended
+ * to SRAM1, SRAM2a and SRAM2b.
* @rmtoll CR3 RRS LL_PWR_IsEnabledSRAM2Retention
* @retval State of bit (1 or 0).
*/
@@ -851,7 +868,7 @@
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5 (*)
*
- * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx
+ * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
@@ -873,7 +890,7 @@
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5 (*)
*
- * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx
+ * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
@@ -895,7 +912,7 @@
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5 (*)
*
- * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx
+ * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
@@ -972,7 +989,7 @@
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5 (*)
*
- * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx
+ * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
@@ -994,7 +1011,7 @@
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5 (*)
*
- * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx
+ * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
@@ -1016,7 +1033,7 @@
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5 (*)
*
- * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx
+ * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
@@ -1323,7 +1340,7 @@
*
* (1) SMPS operating mode step down or open depends on system low-power mode:
* - step down mode if system low power mode is run, LP run or stop0,
- * - open mode if system low power mode is stop1, stop2, standby or shutdown
+ * - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown
* @retval None
*/
__STATIC_INLINE void LL_PWR_SMPS_SetMode(uint32_t OperatingMode)
@@ -1345,7 +1362,7 @@
*
* (1) SMPS operating mode step down or open depends on system low-power mode:
* - step down mode if system low power mode is run, LP run or stop0,
- * - open mode if system low power mode is stop1, stop2, standby or shutdown
+ * - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown
*/
__STATIC_INLINE uint32_t LL_PWR_SMPS_GetMode(void)
{
@@ -1366,7 +1383,7 @@
* requested operating mode can differ from effective low power mode.
* - dependency on system low-power mode:
* - step down mode if system low power mode is run, LP run or stop0,
- * - open mode if system low power mode is stop1, stop2, standby or shutdown
+ * - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown
* - dependency on BOR level:
* - bypass mode if supply voltage drops below BOR level
* @note This functions check flags of SMPS operating modes step down
@@ -1380,7 +1397,7 @@
*
* (1) SMPS operating mode step down or open depends on system low-power mode:
* - step down mode if system low power mode is run, LP run or stop0,
- * - open mode if system low power mode is stop1, stop2, standby or shutdown
+ * - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown
*/
__STATIC_INLINE uint32_t LL_PWR_SMPS_GetEffectiveMode(void)
{
@@ -1637,9 +1654,11 @@
* @param LowPowerMode This parameter can be one of the following values:
* @arg @ref LL_PWR_MODE_STOP0
* @arg @ref LL_PWR_MODE_STOP1
- * @arg @ref LL_PWR_MODE_STOP2
+ * @arg @ref LL_PWR_MODE_STOP2 (*)
* @arg @ref LL_PWR_MODE_STANDBY
* @arg @ref LL_PWR_MODE_SHUTDOWN
+ *
+ * (*) Not available on devices STM32WB15xx, STM32WB10xx
* @retval None
*/
__STATIC_INLINE void LL_C2_PWR_SetPowerMode(uint32_t LowPowerMode)
@@ -1653,9 +1672,11 @@
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_MODE_STOP0
* @arg @ref LL_PWR_MODE_STOP1
- * @arg @ref LL_PWR_MODE_STOP2
+ * @arg @ref LL_PWR_MODE_STOP2 (*)
* @arg @ref LL_PWR_MODE_STANDBY
* @arg @ref LL_PWR_MODE_SHUTDOWN
+ *
+ * (*) Not available on devices STM32WB15xx, STM32WB10xx
*/
__STATIC_INLINE uint32_t LL_C2_PWR_GetPowerMode(void)
{
@@ -1673,7 +1694,7 @@
__STATIC_INLINE void LL_C2_PWR_SetFlashPowerModeLPRun(uint32_t FlashLowPowerMode)
{
/* Unlock bit FPDR */
- WRITE_REG(PWR->C2CR1, 0x0000C1B0U);
+ WRITE_REG(PWR->C2CR1, 0x0000C1B0UL);
/* Update bit FPDR */
MODIFY_REG(PWR->C2CR1, PWR_C2CR1_FPDR, FlashLowPowerMode);
@@ -1761,7 +1782,7 @@
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5 (*)
*
- * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx
+ * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx
* @retval None
*/
__STATIC_INLINE void LL_C2_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
@@ -1783,7 +1804,7 @@
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5 (*)
*
- * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx
+ * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx
* @retval None
*/
__STATIC_INLINE void LL_C2_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
@@ -1805,7 +1826,7 @@
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5 (*)
*
- * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx
+ * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx
* @retval None
*/
__STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
@@ -1874,6 +1895,7 @@
return ((READ_BIT(PWR->C2CR1, PWR_C2CR1_BLEEWKUP) == (PWR_C2CR1_BLEEWKUP)) ? 1UL : 0UL);
}
+#if defined(PWR_CR3_E802A)
/**
* @brief Wakeup 802.15.4 controller from its sleep mode
* @note This bit is automatically reset when 802.15.4 controller
@@ -1896,6 +1918,7 @@
{
return ((READ_BIT(PWR->C2CR1, PWR_C2CR1_802EWKUP) == (PWR_C2CR1_802EWKUP)) ? 1UL : 0UL);
}
+#endif
/**
* @}
@@ -2179,6 +2202,7 @@
return ((READ_BIT(PWR->SR1, PWR_SR1_BLEWUF) == (PWR_SR1_BLEWUF)) ? 1UL : 0UL);
}
+#if defined(PWR_CR3_E802A)
/**
* @brief Get 802.15.4 wakeup interrupt flag
* @rmtoll SR1 802WUF LL_PWR_IsActiveFlag_802WU
@@ -2188,6 +2212,7 @@
{
return ((READ_BIT(PWR->SR1, PWR_SR1_802WUF) == (PWR_SR1_802WUF)) ? 1UL : 0UL);
}
+#endif
/**
* @brief Get BLE end of activity interrupt flag
@@ -2199,6 +2224,7 @@
return ((READ_BIT(PWR->SR1, PWR_SR1_BLEAF) == (PWR_SR1_BLEAF)) ? 1UL : 0UL);
}
+#if defined(PWR_CR3_E802A)
/**
* @brief Get 802.15.4 end of activity interrupt flag
* @rmtoll SR1 802AF LL_PWR_IsActiveFlag_802A
@@ -2208,6 +2234,7 @@
{
return ((READ_BIT(PWR->SR1, PWR_SR1_802AF) == (PWR_SR1_802AF)) ? 1UL : 0UL);
}
+#endif
/**
* @brief Get critical radio phase end of activity interrupt flag
@@ -2239,6 +2266,7 @@
WRITE_REG(PWR->SCR, PWR_SCR_CBLEWUF);
}
+#if defined(PWR_CR3_E802A)
/**
* @brief Clear 802.15.4 wakeup interrupt flag
* @rmtoll SCR 802WU LL_PWR_ClearFlag_802WU
@@ -2248,6 +2276,7 @@
{
WRITE_REG(PWR->SCR, PWR_SCR_C802WUF);
}
+#endif
/**
* @brief Clear BLE end of activity interrupt flag
@@ -2259,6 +2288,7 @@
WRITE_REG(PWR->SCR, PWR_SCR_CBLEAF);
}
+#if defined(PWR_CR3_E802A)
/**
* @brief Clear 802.15.4 end of activity interrupt flag
* @rmtoll SCR 802AF LL_PWR_ClearFlag_802A
@@ -2268,6 +2298,7 @@
{
WRITE_REG(PWR->SCR, PWR_SCR_C802AF);
}
+#endif
/**
* @brief Clear critical radio phase end of activity interrupt flag
@@ -2461,6 +2492,7 @@
SET_BIT(PWR->CR3, PWR_CR3_EBLEA);
}
+#if defined(PWR_CR3_E802A)
/**
* @brief Enable 802.15.4 end of activity interrupt for CPU1
* @rmtoll CR3 E802A LL_PWR_EnableIT_802A
@@ -2470,7 +2502,7 @@
{
SET_BIT(PWR->CR3, PWR_CR3_E802A);
}
-
+#endif
/**
* @brief Disable BLE end of activity interrupt for CPU1
@@ -2482,6 +2514,7 @@
CLEAR_BIT(PWR->CR3, PWR_CR3_EBLEA);
}
+#if defined(PWR_CR3_E802A)
/**
* @brief Disable 802.15.4 end of activity interrupt for CPU1
* @rmtoll CR3 E802A LL_PWR_DisableIT_802A
@@ -2491,6 +2524,7 @@
{
CLEAR_BIT(PWR->CR3, PWR_CR3_E802A);
}
+#endif
/**
* @brief Check if BLE end of activity interrupt is enabled for CPU1
@@ -2502,6 +2536,7 @@
return ((READ_BIT(PWR->CR3, PWR_CR3_EBLEA) == (PWR_CR3_EBLEA)) ? 1UL : 0UL);
}
+#if defined(PWR_CR3_E802A)
/**
* @brief Check if 802.15.4 end of activity interrupt is enabled for CPU1
* @rmtoll CR3 E802A LL_PWR_IsEnabledIT_802A
@@ -2511,6 +2546,7 @@
{
return ((READ_BIT(PWR->CR3, PWR_CR3_E802A) == (PWR_CR3_E802A)) ? 1UL : 0UL);
}
+#endif
/**
* @brief Enable critical radio phase end of activity interrupt for CPU1
@@ -2598,6 +2634,7 @@
SET_BIT(PWR->C2CR3, PWR_C2CR3_EBLEWUP);
}
+#if defined(PWR_CR3_E802A)
/**
* @brief Enable 802.15.4 host wakeup interrupt for CPU2
* @rmtoll C2CR3 E802WUP LL_C2_PWR_EnableIT_802WU
@@ -2607,6 +2644,7 @@
{
SET_BIT(PWR->C2CR3, PWR_C2CR3_E802WUP);
}
+#endif
/**
* @brief Disable BLE host wakeup interrupt for CPU2
@@ -2618,6 +2656,7 @@
CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_EBLEWUP);
}
+#if defined(PWR_CR3_E802A)
/**
* @brief Disable 802.15.4 host wakeup interrupt for CPU2
* @rmtoll C2CR3 E802WUP LL_C2_PWR_DisableIT_802WU
@@ -2627,6 +2666,7 @@
{
CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_E802WUP);
}
+#endif
/**
* @brief Check if BLE host wakeup interrupt is enabled for CPU2
@@ -2638,6 +2678,7 @@
return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_EBLEWUP) == (PWR_C2CR3_EBLEWUP)) ? 1UL : 0UL);
}
+#if defined(PWR_CR3_E802A)
/**
* @brief Check if 802.15.4 host wakeup interrupt is enabled for CPU2
* @rmtoll C2CR3 E802WUP LL_C2_PWR_IsEnabledIT_802WU
@@ -2647,6 +2688,7 @@
{
return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_E802WUP) == (PWR_C2CR3_E802WUP)) ? 1UL : 0UL);
}
+#endif
/**
* @}
diff --git a/Inc/stm32wbxx_ll_rcc.h b/Inc/stm32wbxx_ll_rcc.h
index 067b633..553b3b1 100644
--- a/Inc/stm32wbxx_ll_rcc.h
+++ b/Inc/stm32wbxx_ll_rcc.h
@@ -80,7 +80,7 @@
uint32_t HCLK1_Frequency; /*!< HCLK1 clock frequency */
uint32_t HCLK2_Frequency; /*!< HCLK2 clock frequency */
uint32_t HCLK4_Frequency; /*!< HCLK4 clock frequency */
- uint32_t HCLK5_Frequency; /*!< HCLK5 clock frequency */
+ uint32_t HCLK5_Frequency; /*!< HCLK5 clock frequency */
uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
} LL_RCC_ClocksTypeDef;
@@ -121,15 +121,12 @@
#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
#endif /* LSI_VALUE */
+#if defined(RCC_HSI48_SUPPORT)
#if !defined (HSI48_VALUE)
#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
#endif /* HSI48_VALUE */
-
-#if defined(SPI_I2S_SUPPORT)
-#if !defined (EXTERNAL_CLOCK_VALUE)
-#define EXTERNAL_CLOCK_VALUE 48000U /*!< Value of the I2S_CKIN external oscillator in Hz */
-#endif /* EXTERNAL_CLOCK_VALUE */
#endif
+
/**
* @}
*/
@@ -138,19 +135,21 @@
* @brief Flags defines which can be used with LL_RCC_WriteReg function
* @{
*/
-#define LL_RCC_CICR_LSI1RDYC RCC_CICR_LSI1RDYC /*!< LSI1 Ready Interrupt Clear */
-#define LL_RCC_CICR_LSI2RDYC RCC_CICR_LSI2RDYC /*!< LSI1 Ready Interrupt Clear */
-#define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */
-#define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /*!< MSI Ready Interrupt Clear */
-#define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */
-#define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */
-#define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */
-#define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */
+#define LL_RCC_CICR_LSI1RDYC RCC_CICR_LSI1RDYC /*!< LSI1 Ready Interrupt Clear */
+#define LL_RCC_CICR_LSI2RDYC RCC_CICR_LSI2RDYC /*!< LSI1 Ready Interrupt Clear */
+#define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */
+#define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /*!< MSI Ready Interrupt Clear */
+#define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */
+#define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */
+#define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */
+#if defined(RCC_HSI48_SUPPORT)
+#define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */
+#endif
#if defined(SAI1)
-#define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC /*!< PLLSAI1 Ready Interrupt Clear */
+#define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC /*!< PLLSAI1 Ready Interrupt Clear */
#endif
#define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */
-#define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */
+#define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */
/**
* @}
*/
@@ -159,26 +158,28 @@
* @brief Flags defines which can be used with LL_RCC_ReadReg function
* @{
*/
-#define LL_RCC_CIFR_LSI1RDYF RCC_CIFR_LSI1RDYF /*!< LSI1 Ready Interrupt flag */
-#define LL_RCC_CIFR_LSI2RDYF RCC_CIFR_LSI2RDYF /*!< LSI2 Ready Interrupt flag */
-#define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
-#define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */
-#define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
-#define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
-#define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
-#define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
+#define LL_RCC_CIFR_LSI1RDYF RCC_CIFR_LSI1RDYF /*!< LSI1 Ready Interrupt flag */
+#define LL_RCC_CIFR_LSI2RDYF RCC_CIFR_LSI2RDYF /*!< LSI2 Ready Interrupt flag */
+#define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
+#define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */
+#define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
+#define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
+#define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
+#if defined(RCC_HSI48_SUPPORT)
+#define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
+#endif
#if defined(SAI1)
-#define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */
+#define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */
#endif
#define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
-#define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
-#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
-#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
-#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
-#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
-#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
-#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
-#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
+#define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
+#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
+#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
+#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
+#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
+#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
+#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
+#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
/**
* @}
*/
@@ -187,18 +188,20 @@
* @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
* @{
*/
-#define LL_RCC_CIER_LSI1RDYIE RCC_CIER_LSI1RDYIE /*!< LSI1 Ready Interrupt Enable */
-#define LL_RCC_CIER_LSI2RDYIE RCC_CIER_LSI2RDYIE /*!< LSI Ready Interrupt Enable */
-#define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */
-#define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /*!< MSI Ready Interrupt Enable */
-#define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */
-#define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */
-#define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */
-#define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */
+#define LL_RCC_CIER_LSI1RDYIE RCC_CIER_LSI1RDYIE /*!< LSI1 Ready Interrupt Enable */
+#define LL_RCC_CIER_LSI2RDYIE RCC_CIER_LSI2RDYIE /*!< LSI Ready Interrupt Enable */
+#define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */
+#define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /*!< MSI Ready Interrupt Enable */
+#define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */
+#define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */
+#define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */
+#if defined(RCC_HSI48_SUPPORT)
+#define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */
+#endif
#if defined(SAI1)
#define LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE /*!< PLLSAI1 Ready Interrupt Enable */
#endif
-#define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */
+#define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */
/**
* @}
*/
@@ -206,10 +209,10 @@
/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
* @{
*/
-#define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */
-#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
+#define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */
+#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
-#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
+#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
/**
* @}
*/
@@ -237,13 +240,13 @@
/** @defgroup RCC_LL_EC_HSE_CURRENT_CONTROL HSE current control max limits
* @{
*/
-#define LL_RCC_HSE_CURRENTMAX_0 0x000000000U /*!< HSE current control max limit = 0.18 ma/V*/
-#define LL_RCC_HSE_CURRENTMAX_1 RCC_HSECR_HSEGMC0 /*!< HSE current control max limit = 0.57 ma/V*/
-#define LL_RCC_HSE_CURRENTMAX_2 RCC_HSECR_HSEGMC1 /*!< HSE current control max limit = 0.78 ma/V*/
-#define LL_RCC_HSE_CURRENTMAX_3 (RCC_HSECR_HSEGMC1|RCC_HSECR_HSEGMC0) /*!< HSE current control max limit = 1.13 ma/V*/
-#define LL_RCC_HSE_CURRENTMAX_4 RCC_HSECR_HSEGMC2 /*!< HSE current control max limit = 0.61 ma/V*/
-#define LL_RCC_HSE_CURRENTMAX_5 (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC0) /*!< HSE current control max limit = 1.65 ma/V*/
-#define LL_RCC_HSE_CURRENTMAX_6 (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC1) /*!< HSE current control max limit = 2.12 ma/V*/
+#define LL_RCC_HSE_CURRENTMAX_0 0x000000000U /*!< HSE current control max limit = 0.18 ma/V*/
+#define LL_RCC_HSE_CURRENTMAX_1 RCC_HSECR_HSEGMC0 /*!< HSE current control max limit = 0.57 ma/V*/
+#define LL_RCC_HSE_CURRENTMAX_2 RCC_HSECR_HSEGMC1 /*!< HSE current control max limit = 0.78 ma/V*/
+#define LL_RCC_HSE_CURRENTMAX_3 (RCC_HSECR_HSEGMC1|RCC_HSECR_HSEGMC0) /*!< HSE current control max limit = 1.13 ma/V*/
+#define LL_RCC_HSE_CURRENTMAX_4 RCC_HSECR_HSEGMC2 /*!< HSE current control max limit = 0.61 ma/V*/
+#define LL_RCC_HSE_CURRENTMAX_5 (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC0) /*!< HSE current control max limit = 1.65 ma/V*/
+#define LL_RCC_HSE_CURRENTMAX_6 (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC1) /*!< HSE current control max limit = 2.12 ma/V*/
#define LL_RCC_HSE_CURRENTMAX_7 (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC1|RCC_HSECR_HSEGMC0) /*!< HSE current control max limit = 2.84 ma/V*/
/**
* @}
@@ -252,8 +255,8 @@
/** @defgroup RCC_LL_EC_HSE_SENSE_AMPLIFIER HSE sense amplifier threshold
* @{
*/
-#define LL_RCC_HSEAMPTHRESHOLD_1_2 (0x000000000U) /*!< HSE sense amplifier bias current factor = 1/2*/
-#define LL_RCC_HSEAMPTHRESHOLD_3_4 RCC_HSECR_HSES /*!< HSE sense amplifier bias current factor = 3/4*/
+#define LL_RCC_HSEAMPTHRESHOLD_1_2 (0x000000000U) /*!< HSE sense amplifier bias current factor = 1/2*/
+#define LL_RCC_HSEAMPTHRESHOLD_3_4 RCC_HSECR_HSES /*!< HSE sense amplifier bias current factor = 3/4*/
/**
* @}
*/
@@ -270,10 +273,10 @@
/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
* @{
*/
-#define LL_RCC_SYS_CLKSOURCE_MSI 0x00000000U /*!< MSI selection as system clock */
-#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_0 /*!< HSI selection as system clock */
-#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_1 /*!< HSE selection as system clock */
-#define LL_RCC_SYS_CLKSOURCE_PLL (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< PLL selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_MSI 0x00000000U /*!< MSI selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_0 /*!< HSI selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_1 /*!< HSE selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_PLL (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< PLL selection as system clock */
/**
* @}
*/
@@ -281,10 +284,10 @@
/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
* @{
*/
-#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI 0x00000000U /*!< MSI used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_0 /*!< HSI used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_1 /*!< HSE used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< PLL used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI 0x00000000U /*!< MSI used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_0 /*!< HSI used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_1 /*!< HSE used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< PLL used as system clock */
/**
* @}
*/
@@ -292,7 +295,7 @@
/** @defgroup RCC_LL_EC_RF_CLKSOURCE_STATUS RF system clock switch status
* @{
*/
-#define LL_RCC_RF_CLKSOURCE_HSI 0x00000000U /*!< HSI used as RF system clock */
+#define LL_RCC_RF_CLKSOURCE_HSI 0x00000000U /*!< HSI used as RF system clock */
#define LL_RCC_RF_CLKSOURCE_HSE_DIV2 RCC_EXTCFGR_RFCSS /*!< HSE divided by 2 used as RF system clock */
/**
* @}
@@ -301,19 +304,19 @@
/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
* @{
*/
-#define LL_RCC_SYSCLK_DIV_1 0x00000000U /*!< SYSCLK not divided */
-#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 2 */
-#define LL_RCC_SYSCLK_DIV_3 RCC_CFGR_HPRE_0 /*!< SYSCLK divided by 3 */
-#define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 4 */
-#define LL_RCC_SYSCLK_DIV_5 RCC_CFGR_HPRE_1 /*!< SYSCLK divided by 5 */
-#define LL_RCC_SYSCLK_DIV_6 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 6 */
-#define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 8 */
-#define LL_RCC_SYSCLK_DIV_10 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 10 */
-#define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 16 */
-#define LL_RCC_SYSCLK_DIV_32 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 32 */
-#define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< SYSCLK divided by 64 */
-#define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 128 */
-#define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 256 */
+#define LL_RCC_SYSCLK_DIV_1 0x00000000U /*!< SYSCLK not divided */
+#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 2 */
+#define LL_RCC_SYSCLK_DIV_3 RCC_CFGR_HPRE_0 /*!< SYSCLK divided by 3 */
+#define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 4 */
+#define LL_RCC_SYSCLK_DIV_5 RCC_CFGR_HPRE_1 /*!< SYSCLK divided by 5 */
+#define LL_RCC_SYSCLK_DIV_6 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 6 */
+#define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 8 */
+#define LL_RCC_SYSCLK_DIV_10 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 10 */
+#define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 16 */
+#define LL_RCC_SYSCLK_DIV_32 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 32 */
+#define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< SYSCLK divided by 64 */
+#define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 128 */
+#define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 256 */
#define LL_RCC_SYSCLK_DIV_512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 512 */
/**
* @}
@@ -322,10 +325,10 @@
/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
* @{
*/
-#define LL_RCC_APB1_DIV_1 0x00000000U /*!< HCLK1 not divided */
-#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_2 /*!< HCLK1 divided by 2 */
-#define LL_RCC_APB1_DIV_4 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_0) /*!< HCLK1 divided by 4 */
-#define LL_RCC_APB1_DIV_8 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1) /*!< HCLK1 divided by 8 */
+#define LL_RCC_APB1_DIV_1 0x00000000U /*!< HCLK1 not divided */
+#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_2 /*!< HCLK1 divided by 2 */
+#define LL_RCC_APB1_DIV_4 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_0) /*!< HCLK1 divided by 4 */
+#define LL_RCC_APB1_DIV_8 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1) /*!< HCLK1 divided by 8 */
#define LL_RCC_APB1_DIV_16 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1 | RCC_CFGR_PPRE1_0) /*!< HCLK1 divided by 16 */
/**
* @}
@@ -334,10 +337,10 @@
/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
* @{
*/
-#define LL_RCC_APB2_DIV_1 0x00000000U /*!< HCLK1 not divided */
-#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_2 /*!< HCLK1 divided by 2 */
-#define LL_RCC_APB2_DIV_4 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_0) /*!< HCLK1 divided by 4 */
-#define LL_RCC_APB2_DIV_8 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1) /*!< HCLK1 divided by 8 */
+#define LL_RCC_APB2_DIV_1 0x00000000U /*!< HCLK1 not divided */
+#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_2 /*!< HCLK1 divided by 2 */
+#define LL_RCC_APB2_DIV_4 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_0) /*!< HCLK1 divided by 4 */
+#define LL_RCC_APB2_DIV_8 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1) /*!< HCLK1 divided by 8 */
#define LL_RCC_APB2_DIV_16 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1 | RCC_CFGR_PPRE2_0) /*!< HCLK1 divided by 16 */
/**
* @}
@@ -355,17 +358,19 @@
/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
* @{
*/
-#define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */
-#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
-#define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */
-#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */
-#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE after stabilization selection as MCO1 source */
-#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLL selection as MCO1 source */
-#define LL_RCC_MCO1SOURCE_LSI1 (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI1 selection as MCO1 source */
-#define LL_RCC_MCO1SOURCE_LSI2 (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI2 selection as MCO1 source */
-#define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_3 /*!< LSE selection as MCO1 source */
-#define LL_RCC_MCO1SOURCE_HSI48 (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_3) /*!< HSI48 selection as MCO1 source */
-#define LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB (RCC_CFGR_MCOSEL_2|RCC_CFGR_MCOSEL_3) /*!< HSE before stabilization selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */
+#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE after stabilization selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLL selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_LSI1 (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI1 selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_LSI2 (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI2 selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_3 /*!< LSE selection as MCO1 source */
+#if defined(RCC_HSI48_SUPPORT)
+#define LL_RCC_MCO1SOURCE_HSI48 (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_3) /*!< HSI48 selection as MCO1 source */
+#endif
+#define LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB (RCC_CFGR_MCOSEL_2|RCC_CFGR_MCOSEL_3) /*!< HSE before stabilization selection as MCO1 source */
/**
* @}
*/
@@ -373,11 +378,11 @@
/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
* @{
*/
-#define LL_RCC_MCO1_DIV_1 0x00000000U /*!< MCO not divided */
-#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO divided by 2 */
-#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO divided by 4 */
-#define LL_RCC_MCO1_DIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 8 */
-#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO divided by 16 */
+#define LL_RCC_MCO1_DIV_1 0x00000000U /*!< MCO not divided */
+#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO divided by 2 */
+#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO divided by 4 */
+#define LL_RCC_MCO1_DIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 8 */
+#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO divided by 16 */
/**
* @}
*/
@@ -396,9 +401,9 @@
/** @defgroup RCC_LL_EC_SMPS_CLKSOURCE_STATUS SMPS clock switch status
* @{
*/
-#define LL_RCC_SMPS_CLKSOURCE_STATUS_HSI 0x00000000U /*!< HSI used as SMPS clock */
-#define LL_RCC_SMPS_CLKSOURCE_STATUS_MSI RCC_SMPSCR_SMPSSWS_0 /*!< MSI used as SMPS clock */
-#define LL_RCC_SMPS_CLKSOURCE_STATUS_HSE RCC_SMPSCR_SMPSSWS_1 /*!< HSE used as SMPS clock */
+#define LL_RCC_SMPS_CLKSOURCE_STATUS_HSI 0x00000000U /*!< HSI used as SMPS clock */
+#define LL_RCC_SMPS_CLKSOURCE_STATUS_MSI RCC_SMPSCR_SMPSSWS_0 /*!< MSI used as SMPS clock */
+#define LL_RCC_SMPS_CLKSOURCE_STATUS_HSE RCC_SMPSCR_SMPSSWS_1 /*!< HSE used as SMPS clock */
#define LL_RCC_SMPS_CLKSOURCE_STATUS_NO_CLOCK (RCC_SMPSCR_SMPSSWS_0|RCC_SMPSCR_SMPSSWS_1) /*!< No Clock used as SMPS clock */
/**
* @}
@@ -430,10 +435,10 @@
/** @defgroup RCC_LL_EC_USART1_CLKSOURCE USART1 CLKSOURCE
* @{
*/
-#define LL_RCC_USART1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 selected as USART1 clock */
+#define LL_RCC_USART1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 selected as USART1 clock */
#define LL_RCC_USART1_CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 /*!< SYSCLK selected as USART1 clock */
-#define LL_RCC_USART1_CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 /*!< HSI selected as USART1 clock */
-#define LL_RCC_USART1_CLKSOURCE_LSE RCC_CCIPR_USART1SEL /*!< LSE selected as USART1 clock */
+#define LL_RCC_USART1_CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 /*!< HSI selected as USART1 clock */
+#define LL_RCC_USART1_CLKSOURCE_LSE RCC_CCIPR_USART1SEL /*!< LSE selected as USART1 clock */
/**
* @}
*/
@@ -444,8 +449,8 @@
*/
#define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 selected as LPUART1 clock */
#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /*!< SYCLK selected as LPUART1 clock */
-#define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI selected as LPUART1 clock */
-#define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /*!< LSE selected as LPUART1 clock */
+#define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI selected as LPUART1 clock */
+#define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /*!< LSE selected as LPUART1 clock */
/**
* @}
*/
@@ -454,13 +459,13 @@
/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE I2Cx CLKSOURCE
* @{
*/
-#define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (0x00000000U >> 4)) /*!< PCLK1 selected as I2C1 clock */
+#define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (0x00000000U >> 4)) /*!< PCLK1 selected as I2C1 clock */
#define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_0 >> 4)) /*!< SYSCLK selected as I2C1 clock */
-#define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_1 >> 4)) /*!< HSI selected as I2C1 clock */
+#define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_1 >> 4)) /*!< HSI selected as I2C1 clock */
#if defined(I2C3)
-#define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (0x00000000U >> 4)) /*!< PCLK1 selected as I2C3 clock */
+#define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (0x00000000U >> 4)) /*!< PCLK1 selected as I2C3 clock */
#define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_0 >> 4)) /*!< SYSCLK selected as I2C3 clock */
-#define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_1 >> 4)) /*!< HSI selected as I2C3 clock */
+#define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_1 >> 4)) /*!< HSI selected as I2C3 clock */
#endif
/**
* @}
@@ -470,13 +475,13 @@
* @{
*/
#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM1SEL | (0x00000000U >> 16)) /*!< PCLK1 selected as LPTIM1 clock */
-#define LL_RCC_LPTIM1_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16)) /*!< LSI selected as LPTIM1 clock */
-#define LL_RCC_LPTIM1_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16)) /*!< HSI selected as LPTIM1 clock */
-#define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16)) /*!< LSE selected as LPTIM1 clock */
+#define LL_RCC_LPTIM1_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16)) /*!< LSI selected as LPTIM1 clock */
+#define LL_RCC_LPTIM1_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16)) /*!< HSI selected as LPTIM1 clock */
+#define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16)) /*!< LSE selected as LPTIM1 clock */
#define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM2SEL | (0x00000000U >> 16)) /*!< PCLK1 selected as LPTIM2 clock */
-#define LL_RCC_LPTIM2_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16)) /*!< LSI selected as LPTIM2 clock */
-#define LL_RCC_LPTIM2_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16)) /*!< HSI selected as LPTIM2 clock */
-#define LL_RCC_LPTIM2_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16)) /*!< LSE selected as LPTIM2 clock */
+#define LL_RCC_LPTIM2_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16)) /*!< LSI selected as LPTIM2 clock */
+#define LL_RCC_LPTIM2_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16)) /*!< HSI selected as LPTIM2 clock */
+#define LL_RCC_LPTIM2_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16)) /*!< LSE selected as LPTIM2 clock */
/**
* @}
*/
@@ -485,9 +490,9 @@
/** @defgroup RCC_LL_EC_SAI1_CLKSOURCE SAI1 CLKSOURCE
* @{
*/
-#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 0x00000000U /*!< PLLSAI1 selected as SAI1 clock */
-#define LL_RCC_SAI1_CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0 /*!< PLL selected as SAI1 clock */
-#define LL_RCC_SAI1_CLKSOURCE_HSI RCC_CCIPR_SAI1SEL_1 /*!< HSI selected as SAI1 clock */
+#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 0x00000000U /*!< PLLSAI1 selected as SAI1 clock */
+#define LL_RCC_SAI1_CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0 /*!< PLL selected as SAI1 clock */
+#define LL_RCC_SAI1_CLKSOURCE_HSI RCC_CCIPR_SAI1SEL_1 /*!< HSI selected as SAI1 clock */
#define LL_RCC_SAI1_CLKSOURCE_PIN RCC_CCIPR_SAI1SEL /*!< External input selected as SAI1 clock */
/**
* @}
@@ -497,12 +502,14 @@
/** @defgroup RCC_LL_EC_CLK48_CLKSOURCE CLK48 CLKSOURCE
* @{
*/
-#define LL_RCC_CLK48_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 selected as CLK48 clock*/
-#if defined(SAI1)
-#define LL_RCC_CLK48_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 selected as CLK48 clock*/
+#if defined(RCC_HSI48_SUPPORT)
+#define LL_RCC_CLK48_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 selected as CLK48 clock */
#endif
-#define LL_RCC_CLK48_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL selected as CLK48 clock*/
-#define LL_RCC_CLK48_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI selected as CLK48 clock*/
+#if defined(SAI1)
+#define LL_RCC_CLK48_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 selected as CLK48 clock */
+#endif
+#define LL_RCC_CLK48_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL selected as CLK48 clock */
+#define LL_RCC_CLK48_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI selected as CLK48 clock */
/**
* @}
*/
@@ -510,12 +517,14 @@
/** @defgroup RCC_LL_EC_USB_CLKSOURCE USB CLKSOURCE
* @{
*/
-#define LL_RCC_USB_CLKSOURCE_HSI48 LL_RCC_CLK48_CLKSOURCE_HSI48 /*!< HSI48 selected as USB clock*/
-#if defined(SAI1)
-#define LL_RCC_USB_CLKSOURCE_PLLSAI1 LL_RCC_CLK48_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 selected as USB clock*/
+#if defined(RCC_HSI48_SUPPORT)
+#define LL_RCC_USB_CLKSOURCE_HSI48 LL_RCC_CLK48_CLKSOURCE_HSI48 /*!< HSI48 selected as USB clock */
#endif
-#define LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CLK48_CLKSOURCE_PLL /*!< PLL selected as USB clock*/
-#define LL_RCC_USB_CLKSOURCE_MSI LL_RCC_CLK48_CLKSOURCE_MSI /*!< MSI selected as USB clock*/
+#if defined(SAI1)
+#define LL_RCC_USB_CLKSOURCE_PLLSAI1 LL_RCC_CLK48_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 selected as USB clock */
+#endif
+#define LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CLK48_CLKSOURCE_PLL /*!< PLL selected as USB clock */
+#define LL_RCC_USB_CLKSOURCE_MSI LL_RCC_CLK48_CLKSOURCE_MSI /*!< MSI selected as USB clock */
/**
* @}
*/
@@ -527,8 +536,8 @@
#if defined(STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx)
#define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 /*!< PLLSAI1 selected as ADC clock*/
#endif
-#define LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_1 /*!< PLL selected as ADC clock*/
-#define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK selected as ADC clock*/
+#define LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_1 /*!< PLL selected as ADC clock */
+#define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK selected as ADC clock */
/**
* @}
*/
@@ -537,24 +546,12 @@
* @{
*/
#define LL_RCC_RNG_CLKSOURCE_CLK48 0x00000000U /*!< CLK48 divided by 3 selected as RNG Clock */
-#define LL_RCC_RNG_CLKSOURCE_LSI RCC_CCIPR_RNGSEL_0 /*!< LSI selected as ADC clock*/
-#define LL_RCC_RNG_CLKSOURCE_LSE RCC_CCIPR_RNGSEL_1 /*!< LSE selected as ADC clock*/
+#define LL_RCC_RNG_CLKSOURCE_LSI RCC_CCIPR_RNGSEL_0 /*!< LSI selected as ADC clock */
+#define LL_RCC_RNG_CLKSOURCE_LSE RCC_CCIPR_RNGSEL_1 /*!< LSE selected as ADC clock */
/**
* @}
*/
-#if defined(SPI_I2S_SUPPORT)
-/** @defgroup RCC_LL_EC_I2SCLKSOURCE Peripheral I2S clock source selection
- * @{
- */
-#define LL_RCC_I2S_CLKSOURCE_NONE 0x00000000U /*!< no Clock used as I2S clock*/
-#define LL_RCC_I2S_CLKSOURCE_HSI RCC_CCIPR_I2SSEL_0 /*!< HSI clock used as I2S clock source */
-#define LL_RCC_I2S_CLKSOURCE_PLL RCC_CCIPR_I2SSEL_1 /*!< PLL clock used as I2S clock source */
-#define LL_RCC_I2S_CLKSOURCE_PIN RCC_CCIPR_I2SSEL /*!< External clock used as I2S clock source */
-/**
- * @}
- */
-#endif
/** @defgroup RCC_LL_EC_USART1 USART1
* @{
@@ -634,22 +631,13 @@
* @}
*/
-#if defined(SPI_I2S_SUPPORT)
-/** @defgroup RCC_LL_EC_I2S I2S
- * @{
- */
-#define LL_RCC_I2S_CLKSOURCE RCC_CCIPR_I2SSEL /*!< I2S clock source selection bits */
-/**
- * @}
- */
-#endif
/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
* @{
*/
-#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
/**
@@ -659,10 +647,9 @@
/** @defgroup RCC_LL_EC_RFWKP_CLKSOURCE RF Wakeup clock source selection
* @{
*/
-#define LL_RCC_RFWKP_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RF Wakeup clock */
-#define LL_RCC_RFWKP_CLKSOURCE_LSE RCC_CSR_RFWKPSEL_0 /*!< LSE oscillator clock used as RF Wakeup clock */
-#define LL_RCC_RFWKP_CLKSOURCE_LSI RCC_CSR_RFWKPSEL_1 /*!< LSI oscillator clock used as RF Wakeup clock */
-#define LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024 RCC_CSR_RFWKPSEL /*!< HSE oscillator clock divided by 1024 used as RF Wakeup clock */
+#define LL_RCC_RFWKP_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RF Wakeup clock */
+#define LL_RCC_RFWKP_CLKSOURCE_LSE RCC_CSR_RFWKPSEL_0 /*!< LSE oscillator clock used as RF Wakeup clock */
+#define LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024 RCC_CSR_RFWKPSEL /*!< HSE oscillator clock divided by 1024 used as RF Wakeup clock */
/**
* @}
@@ -672,9 +659,9 @@
/** @defgroup RCC_LL_EC_PLLSOURCE PLL and PLLSAI1 entry clock source
* @{
*/
-#define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */
-#define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_0 /*!< MSI clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_1 /*!< HSI clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */
+#define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_0 /*!< MSI clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_1 /*!< HSI clock selected as PLL entry clock source */
#define LL_RCC_PLLSOURCE_HSE (RCC_PLLCFGR_PLLSRC_1 | RCC_PLLCFGR_PLLSRC_0) /*!< HSE clock selected as PLL entry clock source */
/**
* @}
@@ -712,37 +699,37 @@
/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
* @{
*/
-#define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 2 */
-#define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 3 */
-#define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 4 */
-#define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 5 */
-#define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 6 */
-#define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 7 */
-#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 8 */
-#define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 9 */
-#define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 10 */
-#define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 11 */
-#define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 12 */
-#define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 13 */
-#define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 14 */
-#define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 15 */
-#define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)/*!< Main PLL division factor for PLLP output by 16 */
-#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 17 */
-#define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 18 */
-#define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 19 */
-#define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 20 */
-#define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 21 */
-#define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 22 */
-#define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 23 */
-#define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 24 */
-#define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 25 */
-#define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 26 */
-#define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 27*/
-#define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 28 */
-#define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 29 */
-#define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 30 */
-#define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 31 */
-#define LL_RCC_PLLP_DIV_32 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 32 */
+#define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 2 */
+#define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 3 */
+#define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 4 */
+#define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 5 */
+#define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 6 */
+#define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 7 */
+#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 8 */
+#define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 9 */
+#define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 10 */
+#define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 11 */
+#define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 12 */
+#define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 13 */
+#define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 14 */
+#define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 15 */
+#define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 16 */
+#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 17 */
+#define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 18 */
+#define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 19 */
+#define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 20 */
+#define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 21 */
+#define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 22 */
+#define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 23 */
+#define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 24 */
+#define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 25 */
+#define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 26 */
+#define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 27 */
+#define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 28 */
+#define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 29 */
+#define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 30 */
+#define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 31 */
+#define LL_RCC_PLLP_DIV_32 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 32 */
/**
* @}
*/
@@ -766,12 +753,12 @@
/** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLQ)
* @{
*/
-#define LL_RCC_PLLSAI1Q_DIV_2 (RCC_PLLSAI1CFGR_PLLQ_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 2 */
-#define LL_RCC_PLLSAI1Q_DIV_3 (RCC_PLLSAI1CFGR_PLLQ_1) /*!< PLLSAI1 division factor for PLLSAI1Q output by 3 */
-#define LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLQ_1 | RCC_PLLSAI1CFGR_PLLQ_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 4 */
-#define LL_RCC_PLLSAI1Q_DIV_5 (RCC_PLLSAI1CFGR_PLLQ_2) /*!< PLLSAI1 division factor for PLLSAI1Q output by 5 */
-#define LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 6 */
-#define LL_RCC_PLLSAI1Q_DIV_7 (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_1) /*!< PLLSAI1 division factor for PLLSAI1Q output by 7 */
+#define LL_RCC_PLLSAI1Q_DIV_2 (RCC_PLLSAI1CFGR_PLLQ_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 2 */
+#define LL_RCC_PLLSAI1Q_DIV_3 (RCC_PLLSAI1CFGR_PLLQ_1) /*!< PLLSAI1 division factor for PLLSAI1Q output by 3 */
+#define LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLQ_1 | RCC_PLLSAI1CFGR_PLLQ_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 4 */
+#define LL_RCC_PLLSAI1Q_DIV_5 (RCC_PLLSAI1CFGR_PLLQ_2) /*!< PLLSAI1 division factor for PLLSAI1Q output by 5 */
+#define LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 6 */
+#define LL_RCC_PLLSAI1Q_DIV_7 (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_1) /*!< PLLSAI1 division factor for PLLSAI1Q output by 7 */
#define LL_RCC_PLLSAI1Q_DIV_8 (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_1 | RCC_PLLSAI1CFGR_PLLQ_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 8 */
/**
* @}
@@ -780,37 +767,37 @@
/** @defgroup RCC_LL_EC_PLLSAI1P PLLSAI1 division factor (PLLP)
* @{
*/
-#define LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 2 */
-#define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 3 */
-#define LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 4 */
-#define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 5 */
-#define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 6 */
-#define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 7 */
-#define LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2)/*!< Main PLL division factor for PLLP output by 8 */
-#define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 9 */
-#define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 10 */
-#define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 11 */
-#define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3)/*!< Main PLL division factor for PLLP output by 12 */
-#define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 13 */
-#define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3)/*!< Main PLL division factor for PLLP output by 14 */
-#define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3)/*!< Main PLL division factor for PLLP output by 15 */
-#define LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3)/*!< Main PLL division factor for PLLP output by 16 */
-#define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 17 */
-#define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 18 */
-#define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 19 */
-#define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 20 */
-#define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 21 */
-#define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 22 */
-#define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 23 */
-#define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 24 */
-#define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 25 */
-#define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 26 */
-#define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 27*/
-#define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 28 */
-#define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 29 */
-#define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 30 */
-#define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 31 */
-#define LL_RCC_PLLSAI1P_DIV_32 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 32 */
+#define LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 2 */
+#define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 3 */
+#define LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 4 */
+#define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 5 */
+#define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 6 */
+#define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 7 */
+#define LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 8 */
+#define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 9 */
+#define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 10 */
+#define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 11 */
+#define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 12 */
+#define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 13 */
+#define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 14 */
+#define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 15 */
+#define LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 16 */
+#define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 17 */
+#define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 18 */
+#define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 19 */
+#define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 20 */
+#define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 21 */
+#define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 22 */
+#define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 23 */
+#define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 24 */
+#define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 25 */
+#define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 26 */
+#define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 27*/
+#define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 28 */
+#define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 29 */
+#define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 30 */
+#define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 31 */
+#define LL_RCC_PLLSAI1P_DIV_32 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 32 */
/**
* @}
*/
@@ -818,12 +805,12 @@
/** @defgroup RCC_LL_EC_PLLSAI1R PLLSAI1 division factor (PLLR)
* @{
*/
-#define LL_RCC_PLLSAI1R_DIV_2 (RCC_PLLSAI1CFGR_PLLR_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 2 */
-#define LL_RCC_PLLSAI1R_DIV_3 (RCC_PLLSAI1CFGR_PLLR_1) /*!< PLLSAI1 division factor for PLLSAI1R output by 3 */
-#define LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLR_1 | RCC_PLLSAI1CFGR_PLLR_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 4 */
-#define LL_RCC_PLLSAI1R_DIV_5 (RCC_PLLSAI1CFGR_PLLR_2) /*!< PLLSAI1 division factor for PLLSAI1R output by 5 */
-#define LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 6 */
-#define LL_RCC_PLLSAI1R_DIV_7 (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_1) /*!< PLLSAI1 division factor for PLLSAI1R output by 7 */
+#define LL_RCC_PLLSAI1R_DIV_2 (RCC_PLLSAI1CFGR_PLLR_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 2 */
+#define LL_RCC_PLLSAI1R_DIV_3 (RCC_PLLSAI1CFGR_PLLR_1) /*!< PLLSAI1 division factor for PLLSAI1R output by 3 */
+#define LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLR_1 | RCC_PLLSAI1CFGR_PLLR_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 4 */
+#define LL_RCC_PLLSAI1R_DIV_5 (RCC_PLLSAI1CFGR_PLLR_2) /*!< PLLSAI1 division factor for PLLSAI1R output by 5 */
+#define LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 6 */
+#define LL_RCC_PLLSAI1R_DIV_7 (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_1) /*!< PLLSAI1 division factor for PLLSAI1R output by 7 */
#define LL_RCC_PLLSAI1R_DIV_8 (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_1 | RCC_PLLSAI1CFGR_PLLR_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 8 */
/**
* @}
@@ -998,59 +985,6 @@
#define __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
(((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))
-#if defined(SPI_I2S_SUPPORT)
-/**
- * @brief Helper macro to calculate the PLLPCLK frequency used on I2S domain
- * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
- * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
- * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
- * @param __PLLM__ This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLM_DIV_1
- * @arg @ref LL_RCC_PLLM_DIV_2
- * @arg @ref LL_RCC_PLLM_DIV_3
- * @arg @ref LL_RCC_PLLM_DIV_4
- * @arg @ref LL_RCC_PLLM_DIV_5
- * @arg @ref LL_RCC_PLLM_DIV_6
- * @arg @ref LL_RCC_PLLM_DIV_7
- * @arg @ref LL_RCC_PLLM_DIV_8
- * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86
- * @param __PLLP__ This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLP_DIV_2
- * @arg @ref LL_RCC_PLLP_DIV_3
- * @arg @ref LL_RCC_PLLP_DIV_4
- * @arg @ref LL_RCC_PLLP_DIV_5
- * @arg @ref LL_RCC_PLLP_DIV_6
- * @arg @ref LL_RCC_PLLP_DIV_7
- * @arg @ref LL_RCC_PLLP_DIV_8
- * @arg @ref LL_RCC_PLLP_DIV_9
- * @arg @ref LL_RCC_PLLP_DIV_10
- * @arg @ref LL_RCC_PLLP_DIV_11
- * @arg @ref LL_RCC_PLLP_DIV_12
- * @arg @ref LL_RCC_PLLP_DIV_13
- * @arg @ref LL_RCC_PLLP_DIV_14
- * @arg @ref LL_RCC_PLLP_DIV_15
- * @arg @ref LL_RCC_PLLP_DIV_16
- * @arg @ref LL_RCC_PLLP_DIV_17
- * @arg @ref LL_RCC_PLLP_DIV_18
- * @arg @ref LL_RCC_PLLP_DIV_19
- * @arg @ref LL_RCC_PLLP_DIV_20
- * @arg @ref LL_RCC_PLLP_DIV_21
- * @arg @ref LL_RCC_PLLP_DIV_22
- * @arg @ref LL_RCC_PLLP_DIV_23
- * @arg @ref LL_RCC_PLLP_DIV_24
- * @arg @ref LL_RCC_PLLP_DIV_25
- * @arg @ref LL_RCC_PLLP_DIV_26
- * @arg @ref LL_RCC_PLLP_DIV_27
- * @arg @ref LL_RCC_PLLP_DIV_28
- * @arg @ref LL_RCC_PLLP_DIV_29
- * @arg @ref LL_RCC_PLLP_DIV_30
- * @arg @ref LL_RCC_PLLP_DIV_31
- * @arg @ref LL_RCC_PLLP_DIV_32
- * @retval PLL clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_PLLCLK_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
- (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))
-#endif
/**
* @brief Helper macro to calculate the PLLQCLK frequency used on 48M domain
@@ -1362,28 +1296,6 @@
SET_BIT(RCC->CR, RCC_CR_CSSON);
}
-#if defined(RCC_CR_HSEBYP)
-/**
- * @brief Enable HSE external oscillator (HSE Bypass)
- * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
-{
- SET_BIT(RCC->CR, RCC_CR_HSEBYP);
-}
-
-/**
- * @brief Disable HSE external oscillator (HSE Bypass)
- * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
-{
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
-}
-#endif
-
/**
* @brief Enable HSE crystal oscillator (HSE ON)
* @rmtoll CR HSEON LL_RCC_HSE_Enable
@@ -1635,6 +1547,7 @@
* @}
*/
+#if defined(RCC_HSI48_SUPPORT)
/** @defgroup RCC_LL_EF_HSI48 HSI48
* @{
*/
@@ -1682,6 +1595,7 @@
/**
* @}
*/
+#endif
/** @defgroup RCC_LL_EF_LSE LSE
* @{
@@ -2164,9 +2078,7 @@
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_RFWKP_CLKSOURCE_NONE
* @arg @ref LL_RCC_RFWKP_CLKSOURCE_LSE
- * @arg @ref LL_RCC_RFWKP_CLKSOURCE_LSI (*)
* @arg @ref LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024
- * @note (*) Value not defined for all devices
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetRFWKPClockSource(uint32_t Source)
@@ -2180,9 +2092,7 @@
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_RFWKP_CLKSOURCE_NONE
* @arg @ref LL_RCC_RFWKP_CLKSOURCE_LSE
- * @arg @ref LL_RCC_RFWKP_CLKSOURCE_LSI (*)
* @arg @ref LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024
- * @note (*) Value not defined for all devices
*/
__STATIC_INLINE uint32_t LL_RCC_GetRFWKPClockSource(void)
{
@@ -2536,7 +2446,7 @@
* @arg @ref LL_RCC_MCO1SOURCE_MSI
* @arg @ref LL_RCC_MCO1SOURCE_HSI
* @arg @ref LL_RCC_MCO1SOURCE_HSE
- * @arg @ref LL_RCC_MCO1SOURCE_HSI48
+ * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*)
* @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
* @arg @ref LL_RCC_MCO1SOURCE_LSI1
* @arg @ref LL_RCC_MCO1SOURCE_LSI2
@@ -2548,6 +2458,7 @@
* @arg @ref LL_RCC_MCO1_DIV_4
* @arg @ref LL_RCC_MCO1_DIV_8
* @arg @ref LL_RCC_MCO1_DIV_16
+ * @note (*) Value not defined for all devices
* @retval None
*/
__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
@@ -2602,9 +2513,10 @@
* @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
- * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
- * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*)
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
+ * @note (*) Value not defined for all devices
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
@@ -2667,7 +2579,7 @@
* @brief Configure CLK48 clock source
* @rmtoll CCIPR CLK48SEL LL_RCC_SetCLK48ClockSource
* @param CLK48xSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48
+ * @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48 (*)
* @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1 (*)
* @arg @ref LL_RCC_CLK48_CLKSOURCE_PLL
* @arg @ref LL_RCC_CLK48_CLKSOURCE_MSI
@@ -2707,7 +2619,7 @@
* @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
* @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
* @param CLK48xSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48
+ * @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48 (*)
* @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1 (*)
* @arg @ref LL_RCC_CLK48_CLKSOURCE_PLL
* @arg @ref LL_RCC_CLK48_CLKSOURCE_MSI
@@ -2732,6 +2644,7 @@
* @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 (*)
* @arg @ref LL_RCC_ADC_CLKSOURCE_PLL
* @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI (*)
* @note (*) Value not defined for all devices
* @retval None
*/
@@ -2740,22 +2653,6 @@
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
}
-#if defined(SPI_I2S_SUPPORT)
-/**
- * @brief Configure I2Sx clock source
- * @rmtoll CCIPR I2SSEL LL_RCC_SetI2SClockSource
- * @param I2SxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_I2S_CLKSOURCE_NONE
- * @arg @ref LL_RCC_I2S_CLKSOURCE_PLL
- * @arg @ref LL_RCC_I2S_CLKSOURCE_HSI
- * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
-{
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2SSEL, I2SxSource);
-}
-#endif
/**
* @brief Get USARTx clock source
@@ -2801,9 +2698,10 @@
* @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
- * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
- * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*)
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
+ * @note (*) Value not defined for all devices
*/
__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
{
@@ -2870,7 +2768,7 @@
* @param CLK48x This parameter can be one of the following values:
* @arg @ref LL_RCC_CLK48_CLKSOURCE
* @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48
+ * @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48 (*)
* @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1 (*)
* @arg @ref LL_RCC_CLK48_CLKSOURCE_PLL
* @arg @ref LL_RCC_CLK48_CLKSOURCE_MSI
@@ -2909,6 +2807,7 @@
* @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 (*)
* @arg @ref LL_RCC_ADC_CLKSOURCE_PLL
* @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI (*)
* @note (*) Value not defined for all devices
*/
__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
@@ -2916,23 +2815,6 @@
return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));
}
-#if defined(SPI_I2S_SUPPORT)
-/**
- * @brief Get I2Sx clock source
- * @rmtoll CCIPR I2SSEL LL_RCC_GetI2SClockSource
- * @param I2Sx This parameter can be one of the following values:
- * @arg @ref LL_RCC_I2S_CLKSOURCE
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_I2S_CLKSOURCE_NONE
- * @arg @ref LL_RCC_I2S_CLKSOURCE_PLL
- * @arg @ref LL_RCC_I2S_CLKSOURCE_HSI
- * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
- */
-__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
-{
- return (uint32_t)(READ_BIT(RCC->CCIPR, I2Sx));
-}
-#endif
/**
* @}
*/
@@ -3920,6 +3802,7 @@
SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
}
+#if defined(RCC_HSI48_SUPPORT)
/**
* @brief Clear HSI48 ready interrupt flag
* @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
@@ -3929,6 +3812,7 @@
{
SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
}
+#endif
#if defined(SAI1)
/**
@@ -4032,6 +3916,7 @@
return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL);
}
+#if defined(RCC_HSI48_SUPPORT)
/**
* @brief Check if HSI48 ready interrupt occurred or not
* @rmtoll CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
@@ -4041,6 +3926,7 @@
{
return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL);
}
+#endif
#if defined(SAI1)
/**
@@ -4282,6 +4168,7 @@
SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
}
+#if defined(RCC_HSI48_SUPPORT)
/**
* @brief Enable HSI48 ready interrupt
* @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
@@ -4291,6 +4178,7 @@
{
SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
}
+#endif
#if defined(SAI1)
/**
@@ -4383,6 +4271,7 @@
CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
}
+#if defined(RCC_HSI48_SUPPORT)
/**
* @brief Disable HSI48 ready interrupt
* @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
@@ -4392,6 +4281,7 @@
{
CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
}
+#endif
#if defined(SAI1)
/**
@@ -4484,6 +4374,7 @@
return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE)) ? 1UL : 0UL);
}
+#if defined(RCC_HSI48_SUPPORT)
/**
* @brief Checks if HSI48 ready interrupt source is enabled or disabled.
* @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
@@ -4493,6 +4384,7 @@
{
return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE)) ? 1UL : 0UL);
}
+#endif
#if defined(SAI1)
/**
@@ -4553,9 +4445,6 @@
uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
uint32_t LL_RCC_GetRTCClockFreq(void);
uint32_t LL_RCC_GetRFWKPClockFreq(void);
-#if defined(SPI_I2S_SUPPORT)
-uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
-#endif
/**
* @}
*/
diff --git a/Inc/stm32wbxx_ll_tim.h b/Inc/stm32wbxx_ll_tim.h
index 4ef0717..6e9f42d 100644
--- a/Inc/stm32wbxx_ll_tim.h
+++ b/Inc/stm32wbxx_ll_tim.h
@@ -127,7 +127,7 @@
#define TIMx_OR_RMP_SHIFT 16U
#define TIMx_OR_RMP_MASK 0x0000FFFFU
#define TIM1_OR_RMP_MASK ((TIM1_OR_ETR_ADC1_RMP | TIM1_OR_TI1_RMP) << TIMx_OR_RMP_SHIFT)
-#define TIM2_OR_RMP_MASK ((TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP | TIM2_OR_ITR1_RMP) << TIMx_OR_RMP_SHIFT)
+#define TIM2_OR_RMP_MASK ((TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP) << TIMx_OR_RMP_SHIFT)
#if defined(TIM16)
#define TIM16_OR_RMP_MASK (TIM16_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
#endif /* TIM16 */
@@ -1999,8 +1999,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
@@ -2044,8 +2044,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
}
@@ -2083,8 +2083,8 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
}
@@ -2117,7 +2117,7 @@
*/
__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
}
@@ -2149,7 +2149,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
}
@@ -2186,7 +2186,7 @@
*/
__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
}
@@ -2218,7 +2218,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
}
@@ -2243,8 +2243,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2269,8 +2269,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2295,9 +2295,9 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
@@ -2321,8 +2321,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2346,8 +2346,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2371,9 +2371,9 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
@@ -2400,8 +2400,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2427,8 +2427,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2456,9 +2456,9 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
@@ -2727,8 +2727,8 @@
*/
__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
@@ -2755,8 +2755,8 @@
*/
__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@@ -2779,8 +2779,8 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -2805,8 +2805,8 @@
*/
__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@@ -2830,8 +2830,8 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -2868,8 +2868,8 @@
*/
__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@@ -2905,8 +2905,8 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -2934,7 +2934,7 @@
*/
__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
ICPolarity << SHIFT_TAB_CCxP[iChannel]);
}
@@ -2962,7 +2962,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
SHIFT_TAB_CCxP[iChannel]);
}
@@ -3361,7 +3361,6 @@
*/
__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
{
-
MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
}
@@ -3700,7 +3699,7 @@
*/
__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
{
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
SET_BIT(*pReg, Source);
}
@@ -3728,7 +3727,7 @@
*/
__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
{
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
CLEAR_BIT(*pReg, Source);
}
@@ -3760,7 +3759,7 @@
__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
uint32_t Polarity)
{
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
}
/**
diff --git a/README.md b/README.md
index 66a10e5..c87e016 100644
--- a/README.md
+++ b/README.md
@@ -45,6 +45,8 @@
Tag v1.4.0 | Tag v1.3.0 | Tag v5.4.0_cm4 | Tag v1.4.0 (and following, if any, till next tag)
Tag v1.5.0 | Tag v1.4.0 | Tag v5.4.0_cm4 | Tag v1.5.0 (and following, if any, till next tag)
Tag v1.6.0 | Tag v1.5.0 | Tag v5.4.0_cm4 | Tag v1.8.0 (and following, if any, till next tag)
+Tag v1.6.0 | Tag v1.5.0 | Tag v5.4.0_cm4 | Tag v1.9.0 (and following, if any, till next tag)
+Tag v1.7.0 | Tag v1.7.0 | Tag v5.4.0_cm4 | Tag v1.10.0 (and following, if any, till next tag)
The full **STM32CubeWB** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeWB).
diff --git a/Release_Notes.html b/Release_Notes.html
index ebbbcf5..b4d635f 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -46,7 +46,7 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section7" checked aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">v1.6.0 / 05-June-2020</label>
+<input type="checkbox" id="collapse-section8" checked aria-hidden="true"> <label for="collapse-section8" aria-hidden="true">v1.7.0 / 30-October-2020</label>
<div>
<h2 id="main-changes">Main Changes</h2>
<h3 id="maitenance-release">Maitenance release</h3>
@@ -60,6 +60,86 @@
</thead>
<tbody>
<tr class="odd">
+<td>CRYP</td>
+<td style="text-align: left;">Add precision on data types</td>
+</tr>
+<tr class="even">
+<td>CRYP</td>
+<td style="text-align: left;">AES GCM: handling of AUD with size not multiple of 4 bytes not properly handle in CRYP_AESGCM_Process_IT</td>
+</tr>
+<tr class="odd">
+<td>CRYP</td>
+<td style="text-align: left;">Fix CRYP HAL driver to manage GCM header lengths not multiple of 4 bytes in 8-bit, 16-bit and 32-bit data types.</td>
+</tr>
+<tr class="even">
+<td>CRYP</td>
+<td style="text-align: left;">Update to be able to manage GCM/GMAC/CCM header feed in DMA mode</td>
+</tr>
+<tr class="odd">
+<td>CRYP</td>
+<td style="text-align: left;">Fix the enciphering issue and pass all the official NIST CCM test patterns.</td>
+</tr>
+<tr class="even">
+<td>EXTI</td>
+<td style="text-align: left;">Replace reserved word __LINE__ by __EXTI_LINE__</td>
+</tr>
+<tr class="odd">
+<td>EXTI</td>
+<td style="text-align: left;">Add missing line 46 to LL_EXTI_LINE_ALL_32_63</td>
+</tr>
+<tr class="even">
+<td>I2C</td>
+<td style="text-align: left;">Refactor documentation</td>
+</tr>
+<tr class="odd">
+<td>PWR</td>
+<td style="text-align: left;">Remove ‘register’ storage class specifier</td>
+</tr>
+<tr class="even">
+<td>RCC</td>
+<td style="text-align: left;">HSE bypass related API must be removed from RCC LL/HAL drivers</td>
+</tr>
+<tr class="odd">
+<td>RCC</td>
+<td style="text-align: left;">LSI is no longer a source for RF WUP</td>
+</tr>
+<tr class="even">
+<td>RCC</td>
+<td style="text-align: left;">SystemCoreClockUpdate shall not be called by the HAL</td>
+</tr>
+<tr class="odd">
+<td>TIM</td>
+<td style="text-align: left;">Add HAL_TIM_DMABurst_MultiWriteStart and HAL_TIM_DMABurst_MultiReadStart to support multiple DMA bursts.</td>
+</tr>
+<tr class="even">
+<td>TIM</td>
+<td style="text-align: left;">Minor correction to fix warnings</td>
+</tr>
+<tr class="odd">
+<td>WWDG</td>
+<td style="text-align: left;">Correct driver description</td>
+</tr>
+</tbody>
+</table>
+<h2 id="backward-compatibility">Backward Compatibility</h2>
+<p>This release is compatible with the previous versions.</p>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">v1.6.0 / 05-June-2020</label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<h3 id="maitenance-release-1">Maitenance release</h3>
+<p>All peripheral</p>
+<table>
+<thead>
+<tr class="header">
+<th>Peripheral</th>
+<th style="text-align: left;">Headline</th>
+</tr>
+</thead>
+<tbody>
+<tr class="odd">
<td>All</td>
<td style="text-align: left;">Remove ‘register’ storage class specifier</td>
</tr>
@@ -84,73 +164,65 @@
<td style="text-align: left;">Sequential transfer MAX_NBYTE_SIZE correspond to no reload</td>
</tr>
<tr class="odd">
-<td>SPI/I2S</td>
-<td style="text-align: left;">HAL_I2S_DMAStop doesn’t check the BSY flag as described in RM0390</td>
-</tr>
-<tr class="even">
-<td>SPI/I2S</td>
+<td>SPI</td>
<td style="text-align: left;">problematic timeout management inside SPI DMA xfer complete handler (interrupt context)</td>
</tr>
-<tr class="odd">
-<td>SPI/I2S</td>
+<tr class="even">
+<td>SPI</td>
<td style="text-align: left;">Issue in 3wires communication (Need Disable / Enable SPI)</td>
</tr>
-<tr class="even">
+<tr class="odd">
<td>IWDG</td>
<td style="text-align: left;">Correct the IWDG start-up timeout (insufficiently low)</td>
</tr>
-<tr class="odd">
+<tr class="even">
<td>USB</td>
<td style="text-align: left;">Improve OUT EP re-enable with double buffering</td>
</tr>
-<tr class="even">
+<tr class="odd">
<td>USB</td>
<td style="text-align: left;">Add workaround for unexpected USB wakeup during stop mode</td>
</tr>
-<tr class="odd">
+<tr class="even">
<td>USB</td>
<td style="text-align: left;">Clear unexpected wakeup during suspend IT</td>
</tr>
-<tr class="even">
+<tr class="odd">
<td>USB</td>
<td style="text-align: left;">Adjust IO address access to be volatile</td>
</tr>
-<tr class="odd">
+<tr class="even">
<td>USB</td>
<td style="text-align: left;">Manage IN isoc IN transfer complete interrupt</td>
</tr>
-<tr class="even">
+<tr class="odd">
<td>RTC</td>
<td style="text-align: left;">Issue on macro when clearing or getting flag TAMP, TIMESTAMP in EXTI</td>
</tr>
-<tr class="odd">
+<tr class="even">
<td>SAI</td>
<td style="text-align: left;">Issue with ‘register’ storage class specifier, should be removed</td>
</tr>
-<tr class="even">
+<tr class="odd">
<td>SMARTCARD</td>
<td style="text-align: left;">No repetition after NACK is received in smartcard T=0</td>
</tr>
-<tr class="odd">
+<tr class="even">
<td>SMARTCARD</td>
<td style="text-align: left;">Improve doxygen visual result</td>
</tr>
-<tr class="even">
+<tr class="odd">
<td>UART</td>
<td style="text-align: left;">Rework BRR register value computation in HAL_UART_Init() for ROM size gain</td>
</tr>
-<tr class="odd">
+<tr class="even">
<td>Utils</td>
<td style="text-align: left;">Align package information to RM0434</td>
</tr>
-<tr class="even">
+<tr class="odd">
<td>Utils</td>
<td style="text-align: left;">Turn UTILS_SetFlashLatency() into LL_SetFlashLatency() public function</td>
</tr>
-<tr class="odd">
-<td>Templates</td>
-<td style="text-align: left;">Correct missing I2S definition in stm32wbxx_hal_conf_template.h</td>
-</tr>
<tr class="even">
<td>TIM</td>
<td style="text-align: left;">Order of disabling in HAL_TIM_IC_Stop_DMA function</td>
@@ -161,19 +233,19 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility">Backward Compatibility</h2>
+<h2 id="backward-compatibility-1">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">v1.5.0 / 12-February-2020</label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
<h3 id="introduction-of-stm32wb5m-stm32wb35xx-and-stm32wb30xx-product">Introduction of STM32WB5M, STM32WB35xx and STM32WB30xx product</h3>
<p>This release introduce the support of STM32WB5Mxx, STM32WB35xx product and its value line STM32WB30xx.</p>
<p>Added features:</p>
<ul>
-<li>Introduction of I2S peripheral support. This only apply to STM32WB35xx.</li>
+<li>Introduction of STM32WB35xx.</li>
</ul>
<table>
<thead>
@@ -211,21 +283,17 @@
<td>RCC</td>
<td style="text-align: left;">Clock reconfiguration issues once PLLSAI used</td>
</tr>
-<tr class="even">
-<td>I2S</td>
-<td style="text-align: left;">Add peripheral for STM32WB35xx</td>
-</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-1">Backward Compatibility</h2>
+<h2 id="backward-compatibility-2">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">v1.4.0 / 15-December-2019</label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
-<h3 id="maitenance-release-1">Maitenance release</h3>
+<h2 id="main-changes-3">Main Changes</h2>
+<h3 id="maitenance-release-2">Maitenance release</h3>
<table>
<thead>
<tr class="header">
@@ -268,7 +336,7 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-2">Backward Compatibility</h2>
+<h2 id="backward-compatibility-3">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
<h2 id="dependencies">Dependencies</h2>
<p>This software release is compatible with:</p>
@@ -278,8 +346,8 @@
<div class="collapse">
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">v1.3.0 / 11-September-2019</label>
<div>
-<h2 id="main-changes-3">Main Changes</h2>
-<h3 id="maitenance-release-2">Maitenance release</h3>
+<h2 id="main-changes-4">Main Changes</h2>
+<h3 id="maitenance-release-3">Maitenance release</h3>
<table>
<thead>
<tr class="header">
@@ -350,7 +418,7 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-3">Backward Compatibility</h2>
+<h2 id="backward-compatibility-4">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
<h2 id="dependencies-1">Dependencies</h2>
<p>This software release is compatible with:</p>
@@ -360,7 +428,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.2.0 / 26-June-2019</label>
<div>
-<h2 id="main-changes-4">Main Changes</h2>
+<h2 id="main-changes-5">Main Changes</h2>
<h3 id="stm32wb50xx-introduction-and-maintenance-release">STM32WB50xx introduction and maintenance release</h3>
<p>First release for STM32WBxx HAL drivers introducing <strong>stm32wb50xx</strong> devices.</p>
<table>
@@ -429,7 +497,7 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-4">Backward Compatibility</h2>
+<h2 id="backward-compatibility-5">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
<h2 id="dependencies-2">Dependencies</h2>
<p>This software release is compatible with:</p>
@@ -439,7 +507,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 05-April-2019</label>
<div>
-<h2 id="main-changes-5">Main Changes</h2>
+<h2 id="main-changes-6">Main Changes</h2>
<h3 id="maintenance-release">Maintenance release</h3>
<p>Maintenance release of HAL and Low layers drivers supporting STM32WB55xx devices.</p>
<table>
@@ -493,7 +561,7 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-5">Backward Compatibility</h2>
+<h2 id="backward-compatibility-6">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
<h2 id="dependencies-3">Dependencies</h2>
<p>This software release is compatible with:</p>
@@ -503,7 +571,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 06-February-2019</label>
<div>
-<h2 id="main-changes-6">Main Changes</h2>
+<h2 id="main-changes-7">Main Changes</h2>
<h3 id="first-release">First release</h3>
<p>First official release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32WB55xx.</p>
</div>
diff --git a/Src/stm32wbxx_hal.c b/Src/stm32wbxx_hal.c
index bf37f6e..758d90f 100644
--- a/Src/stm32wbxx_hal.c
+++ b/Src/stm32wbxx_hal.c
@@ -56,7 +56,7 @@
* @brief STM32WBxx HAL Driver version number
*/
#define __STM32WBxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
-#define __STM32WBxx_HAL_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
+#define __STM32WBxx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */
#define __STM32WBxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32WBxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32WBxx_HAL_VERSION ((__STM32WBxx_HAL_VERSION_MAIN << 24U)\
diff --git a/Src/stm32wbxx_hal_adc.c b/Src/stm32wbxx_hal_adc.c
index ecf52d2..0437f3d 100644
--- a/Src/stm32wbxx_hal_adc.c
+++ b/Src/stm32wbxx_hal_adc.c
@@ -3,7 +3,7 @@
* @file stm32wbxx_hal_adc.c
* @author MCD Application Team
* @brief This file provides firmware functions to manage the following
- * functionalities of the Analog to Digital Convertor (ADC)
+ * functionalities of the Analog to Digital Converter (ADC)
* peripheral:
* + Initialization and de-initialization functions
* ++ Initialization and Configuration of ADC
@@ -341,6 +341,11 @@
/* Unit: cycles of CPU clock. */
#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES (653UL * 4096UL * 256UL) /*!< ADC conversion completion time-out value */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Register CHSELR bits corresponding to ranks 2 to 8 . */
+#define ADC_CHSELR_SQ2_TO_SQ8 (ADC_CHSELR_SQ2 | ADC_CHSELR_SQ3 | ADC_CHSELR_SQ4 | ADC_CHSELR_SQ5 | ADC_CHSELR_SQ6 | ADC_CHSELR_SQ7 | ADC_CHSELR_SQ8)
+#endif
+
/**
* @}
@@ -394,11 +399,15 @@
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- uint32_t tmpCFGR;
+ uint32_t tmpCFGR = 0UL;
uint32_t tmp_adc_reg_is_conversion_on_going;
__IO uint32_t wait_loop_index = 0UL;
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ uint32_t tmpCFGR2 = 0UL;
+#else
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
+#endif
/* Check ADC handle */
if (hadc == NULL)
@@ -419,6 +428,23 @@
assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff));
+ assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon1));
+ assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon2));
+
+ assert_param(IS_ADC_TRIGGER_FREQ(hadc->Init.TriggerFrequencyMode));
+
+ if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+ {
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+
+ if(hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
+ {
+ assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
+ }
+ }
+#else
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
@@ -434,6 +460,7 @@
/* DISCEN and CONT bits cannot be set at the same time */
assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Actions performed only if ADC is coming from state reset: */
/* - Initialization of ADC MSP */
@@ -445,8 +472,10 @@
hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
+#if !defined (ADC_SUPPORT_2_5_MSPS)
hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */
hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; /* Legacy weak callback */
+#endif
hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */
hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */
hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */
@@ -470,7 +499,10 @@
hadc->Lock = HAL_UNLOCKED;
}
- /* - Exit from deep-power-down mode and ADC voltage regulator enable */
+ /* - Exit from deep power-down mode and ADC voltage regulator enable */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Feature "deep power-down" not available on ADC peripheral of this STM32WB device */
+#else
if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
{
/* Disable ADC deep power down mode */
@@ -480,6 +512,7 @@
be relaunched or a previously saved calibration factor
re-applied once the ADC voltage regulator is enabled */
}
+#endif
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
{
@@ -525,6 +558,219 @@
HAL_ADC_STATE_REG_BUSY,
HAL_ADC_STATE_BUSY_INTERNAL);
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Configuration of common ADC parameters */
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - Internal voltage regulator (no parameter in HAL ADC init structure) */
+ /* - Clock configuration */
+ /* - ADC resolution */
+ /* Note: If low power mode AutoPowerOff is enabled, ADC enable */
+ /* and disable phases are performed automatically by hardware */
+ /* (in this case, flag ADC_FLAG_RDY is not set). */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ {
+ /* Some parameters of this register are not reset, since they are set */
+ /* by other functions and must be kept in case of usage of this */
+ /* function on the fly (update of a parameter of ADC_InitTypeDef */
+ /* without needing to reconfigure all other ADC groups/channels */
+ /* parameters): */
+ /* - internal measurement paths: Vbat, temperature sensor, Vref */
+ /* (set into HAL_ADC_ConfigChannel() ) */
+
+ /* Configuration of ADC resolution */
+ MODIFY_REG(hadc->Instance->CFGR1,
+ ADC_CFGR1_RES ,
+ hadc->Init.Resolution );
+
+ /* Configuration of ADC: */
+ /* - clock */
+ /* - oversampling enable */
+ /* - oversampling ratio */
+ /* - oversampling shift */
+ /* - oversampling discontinuous mode (triggered mode) */
+ /* - trigger frequency mode */
+ tmpCFGR2 |= ( (hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
+ hadc->Init.TriggerFrequencyMode
+ );
+
+ MODIFY_REG(hadc->Instance->CFGR2,
+ ADC_CFGR2_CKMODE |
+ ADC_CFGR2_LFTRIG ,
+ tmpCFGR2 );
+
+ /* Configuration of ADC clock mode: asynchronous clock source */
+ /* with selectable prescaler. */
+ if (((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV1) &&
+ ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV2) &&
+ ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV4))
+ {
+ MODIFY_REG(ADC1_COMMON->CCR ,
+ ADC_CCR_PRESC ,
+ hadc->Init.ClockPrescaler & ADC_CCR_PRESC );
+ }
+ }
+
+ /* Configuration of ADC: */
+ /* - discontinuous mode */
+ /* - LowPowerAutoWait mode */
+ /* - LowPowerAutoPowerOff mode */
+ /* - continuous conversion mode */
+ /* - overrun */
+ /* - external trigger to start conversion */
+ /* - external trigger polarity */
+ /* - data alignment */
+ /* - resolution */
+ /* - scan direction */
+ /* - DMA continuous request */
+ tmpCFGR |= (ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
+ ADC_CFGR_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) |
+ ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
+ ADC_CFGR_OVERRUN(hadc->Init.Overrun) |
+ hadc->Init.DataAlign |
+ ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) |
+ ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) );
+
+ /* Update setting of discontinuous mode only if continuous mode is disabled */
+ if (hadc->Init.DiscontinuousConvMode == ENABLE)
+ {
+ if (hadc->Init.ContinuousConvMode == DISABLE)
+ {
+ /* Enable the selected ADC group regular discontinuous mode */
+ tmpCFGR |= ADC_CFGR1_DISCEN;
+ }
+ else
+ {
+ /* ADC regular group discontinuous was intended to be enabled, */
+ /* but ADC regular group modes continuous and sequencer discontinuous */
+ /* cannot be enabled simultaneously. */
+
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+
+ /* Enable external trigger if trigger selection is different of software */
+ /* start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+ {
+ tmpCFGR |= ( (hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) |
+ hadc->Init.ExternalTrigConvEdge );
+ }
+
+ /* Update ADC configuration register with previous settings */
+ MODIFY_REG(hadc->Instance->CFGR1,
+ ADC_CFGR1_DISCEN |
+ ADC_CFGR1_AUTOFF |
+ ADC_CFGR1_WAIT |
+ ADC_CFGR1_CONT |
+ ADC_CFGR1_OVRMOD |
+ ADC_CFGR1_EXTSEL |
+ ADC_CFGR1_EXTEN |
+ ADC_CFGR1_ALIGN |
+ ADC_CFGR1_SCANDIR |
+ ADC_CFGR1_DMACFG ,
+ tmpCFGR );
+
+ /* Channel sampling time configuration */
+ LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1, hadc->Init.SamplingTimeCommon1);
+ LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_2, hadc->Init.SamplingTimeCommon2);
+
+ /* Configuration of regular group sequencer: */
+ /* - if scan mode is disabled, regular channels sequence length is set to */
+ /* 0x00: 1 channel converted (channel on regular rank 1) */
+ /* Parameter "NbrOfConversion" is discarded. */
+ /* Note: Scan mode is not present by hardware on this device, but */
+ /* emulated by software for alignment over all STM32 devices. */
+ /* - if scan mode is enabled, regular channels sequence length is set to */
+ /* parameter "NbrOfConversion". */
+ /* Channels must be configured into each rank using function */
+ /* "HAL_ADC_ConfigChannel()". */
+ if(hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
+ {
+ /* Set sequencer scan length by clearing ranks above rank 1 */
+ /* and do not modify rank 1 value. */
+ SET_BIT(hadc->Instance->CHSELR,
+ ADC_CHSELR_SQ2_TO_SQ8);
+ }
+ else if(hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
+ {
+ /* Count number of ranks available in HAL ADC handle variable */
+ uint32_t ADCGroupRegularSequencerRanksCount;
+
+ /* Parse all ranks from 1 to 8 */
+ for(ADCGroupRegularSequencerRanksCount = 0UL; ADCGroupRegularSequencerRanksCount < (8UL); ADCGroupRegularSequencerRanksCount++)
+ {
+ /* Check each sequencer rank until value of end of sequence */
+ if(((hadc->ADCGroupRegularSequencerRanks >> (ADCGroupRegularSequencerRanksCount * 4UL)) & ADC_CHSELR_SQ1) == ADC_CHSELR_SQ1)
+ {
+ break;
+ }
+ }
+
+ if(ADCGroupRegularSequencerRanksCount == 1UL)
+ {
+ /* Set ADC group regular sequencer: */
+ /* Set sequencer scan length by clearing ranks above rank 1 */
+ /* and do not modify rank 1 value. */
+ SET_BIT(hadc->Instance->CHSELR,
+ ADC_CHSELR_SQ2_TO_SQ8);
+ }
+ else
+ {
+ /* Set ADC group regular sequencer: */
+ /* - Set ADC group regular sequencer to value memorized */
+ /* in HAL ADC handle */
+ /* Note: This value maybe be initialized at a unknown value, */
+ /* therefore afer the first call of "HAL_ADC_Init()", */
+ /* each rank corresponding to parameter "NbrOfConversion" */
+ /* must be set using "HAL_ADC_ConfigChannel()". */
+ /* - Set sequencer scan length by clearing ranks above maximum rank */
+ /* and do not modify other ranks value. */
+ MODIFY_REG(hadc->Instance->CHSELR,
+ ADC_CHSELR_SQ_ALL,
+ (ADC_CHSELR_SQ2_TO_SQ8 << (((hadc->Init.NbrOfConversion - 1UL) * ADC_REGULAR_RANK_2) & 0x1FUL)) | (hadc->ADCGroupRegularSequencerRanks)
+ );
+ }
+ }
+
+ /* Check back that ADC registers have effectively been configured to */
+ /* ensure of no potential problem of ADC core peripheral clocking. */
+ /* Check through register CFGR1 (excluding analog watchdog configuration: */
+ /* set into separate dedicated function, and bits of ADC resolution set */
+ /* out of temporary variable 'tmpCFGR'). */
+ if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_RES))
+ == tmpCFGR)
+ {
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Set the ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+#else
/* Configuration of common ADC parameters */
/* Parameters update conditioned to ADC state: */
@@ -564,7 +810,7 @@
/* - overrun Init.Overrun */
/* - discontinuous mode Init.DiscontinuousConvMode */
/* - discontinuous mode channel count Init.NbrOfDiscConversion */
- tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
+ tmpCFGR |= (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
hadc->Init.Overrun |
hadc->Init.DataAlign |
hadc->Init.Resolution |
@@ -662,6 +908,7 @@
/* Initialize the ADC state */
/* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
+#endif /* ADC_SUPPORT_2_5_MSPS */
}
else
{
@@ -710,8 +957,15 @@
SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
/* Stop potential conversion on going */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+#else
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+#endif /* ADC_SUPPORT_2_5_MSPS */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/* Disable ADC peripheral if conversions are effectively stopped */
/* Flush register JSQR: reset the queue sequencer when injected */
/* queue sequencer is enabled and ADC disabled. */
@@ -719,6 +973,7 @@
/* internally disabled just after the completion of the last valid */
/* injected sequence. */
SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
+#endif
/* Disable ADC peripheral if conversions are effectively stopped */
if (tmp_hal_status == HAL_OK)
@@ -741,18 +996,69 @@
/* system RCC hard reset. */
/* ========== Reset ADC registers ========== */
+#if defined (ADC_SUPPORT_2_5_MSPS)
/* Reset register IER */
- __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 |
- ADC_IT_JQOVF | ADC_IT_OVR |
- ADC_IT_JEOS | ADC_IT_JEOC |
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 |
+ ADC_IT_AWD1 | ADC_IT_OVR |
ADC_IT_EOS | ADC_IT_EOC |
+ ADC_IT_EOSMP | ADC_IT_RDY ) );
+
+ /* Reset register ISR */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 |
+ ADC_FLAG_AWD1 | ADC_FLAG_OVR |
+ ADC_FLAG_EOS | ADC_FLAG_EOC |
+ ADC_FLAG_EOSMP | ADC_FLAG_RDY ) );
+
+ /* Reset register CR */
+ /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
+ /* "read-set": no direct reset applicable. */
+
+ /* Reset register CFGR1 */
+ hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN |
+ ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD |
+ ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES |
+ ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN );
+
+ /* Reset register CFGR2 */
+ /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
+ /* already done above. */
+ hadc->Instance->CFGR2 &= ~ADC_CFGR2_CKMODE;
+
+ /* Reset register SMPR */
+ hadc->Instance->SMPR &= ~ADC_SMPR_SMP1;
+
+ /* Reset register TR1 */
+ hadc->Instance->TR1 &= ~(ADC_TR1_HT1 | ADC_TR1_LT1);
+
+ /* Reset register CHSELR */
+ hadc->Instance->CHSELR &= ~(ADC_CHSELR_SQ_ALL);
+
+ /* Reset register DR */
+ /* bits in access mode read only, no direct reset applicable */
+
+#else
+ /* Reset register IER */
+ __HAL_ADC_DISABLE_IT(hadc, (
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 |
+ ADC_IT_EOCAL | ADC_IT_CCRDY |
+#else
+ ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 |
+ ADC_IT_JEOS | ADC_IT_JEOC | ADC_IT_JQOVF |
+#endif
+ ADC_IT_EOS | ADC_IT_EOC | ADC_IT_OVR |
ADC_IT_EOSMP | ADC_IT_RDY));
/* Reset register ISR */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
- ADC_FLAG_JQOVF | ADC_FLAG_OVR |
- ADC_FLAG_JEOS | ADC_FLAG_JEOC |
- ADC_FLAG_EOS | ADC_FLAG_EOC |
+ __HAL_ADC_CLEAR_FLAG(hadc, (
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
+ ADC_FLAG_EOCAL | ADC_FLAG_CCRDY |
+#else
+ ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
+ ADC_FLAG_JEOS | ADC_FLAG_JEOC | ADC_FLAG_JQOVF |
+#endif
+ ADC_FLAG_EOS | ADC_FLAG_EOC | ADC_FLAG_OVR |
ADC_FLAG_EOSMP | ADC_FLAG_RDY));
/* Reset register CR */
@@ -831,6 +1137,7 @@
/* Reset register CALFACT */
CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* ========== Reset common ADC registers ========== */
@@ -876,9 +1183,14 @@
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Reset HAL ADC handle variable */
+ hadc->ADCGroupRegularSequencerRanks = 0x00000000UL;
+#else
/* Reset injected channel configuration parameters */
hadc->InjectionConfig.ContextQueue = 0;
hadc->InjectionConfig.ChannelCount = 0;
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Set ADC state */
hadc->State = HAL_ADC_STATE_RESET;
@@ -1094,6 +1406,9 @@
hadc->ErrorCallback = HAL_ADC_ErrorCallback;
break;
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
break;
@@ -1101,6 +1416,7 @@
case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback;
break;
+#endif
case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback;
@@ -1225,6 +1541,10 @@
HAL_ADC_STATE_REG_BUSY);
/* Set ADC error code */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Reset all ADC error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+#else
/* Check if a conversion is on going on ADC group injected */
if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
{
@@ -1236,6 +1556,7 @@
/* Reset all ADC error code fields */
ADC_CLEAR_ERRORCODE(hadc);
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Clear ADC group regular conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
@@ -1287,8 +1608,13 @@
/* Process locked */
__HAL_LOCK(hadc);
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* 1. Stop potential conversion on going, on ADC group regular */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+#else
/* 1. Stop potential conversion on going, on ADC groups regular and injected */
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Disable ADC peripheral if conversions are effectively stopped */
if (tmp_hal_status == HAL_OK)
@@ -1300,9 +1626,15 @@
if (tmp_hal_status == HAL_OK)
{
/* Set ADC state */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_READY);
+#else
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_READY);
+#endif /* ADC_SUPPORT_2_5_MSPS */
}
}
@@ -1353,7 +1685,11 @@
/* several ranks and polling for end of each conversion. */
/* For code simplicity sake, this particular case is generalized to */
/* ADC configured in DMA mode and and polling for end of each conversion. */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ if(READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN) != 0UL)
+#else
if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL)
+#endif
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
@@ -1420,7 +1756,11 @@
/* Clear end of conversion EOC flag of regular group if low power feature */
/* "LowPowerAutoWait " is disabled, to not interfere with this feature */
/* until data register is read using function HAL_ADC_GetValue(). */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_WAIT) == 0UL)
+#else
if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_AUTDLY) == 0UL)
+#endif
{
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
}
@@ -1440,7 +1780,9 @@
* @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
* @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
* @arg @ref ADC_OVR_EVENT ADC Overrun event
- * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event
+ * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event (1)
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @param Timeout Timeout value in millisecond.
* @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
* Indeed, the latter is reset only if hadc->Init.Overrun field is set
@@ -1531,6 +1873,9 @@
break;
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/* Injected context queue overflow event */
case ADC_JQOVF_EVENT:
/* Set ADC state */
@@ -1543,6 +1888,7 @@
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
break;
+#endif
/* Overrun event */
default: /* Case ADC_OVR_EVENT */
@@ -1617,6 +1963,10 @@
HAL_ADC_STATE_REG_BUSY);
/* Set ADC error code */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Reset all ADC error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+#else
/* Check if a conversion is on going on ADC group injected */
if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
{
@@ -1628,6 +1978,7 @@
/* Reset all ADC error code fields */
ADC_CLEAR_ERRORCODE(hadc);
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Clear ADC group regular conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
@@ -1702,8 +2053,13 @@
/* Process locked */
__HAL_LOCK(hadc);
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* 1. Stop potential conversion on going, on ADC group regular */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+#else
/* 1. Stop potential conversion on going, on ADC groups regular and injected */
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Disable ADC peripheral if conversions are effectively stopped */
if (tmp_hal_status == HAL_OK)
@@ -1719,9 +2075,15 @@
if (tmp_hal_status == HAL_OK)
{
/* Set ADC state */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_READY);
+#else
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_READY);
+#endif /* ADC_SUPPORT_2_5_MSPS */
}
}
@@ -1768,6 +2130,10 @@
HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
HAL_ADC_STATE_REG_BUSY);
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Reset all ADC error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+#else
/* Check if a conversion is on going on ADC group injected */
if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
{
@@ -1779,6 +2145,7 @@
/* Reset all ADC error code fields */
ADC_CLEAR_ERRORCODE(hadc);
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Set the DMA transfer complete callback */
hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
@@ -1809,7 +2176,11 @@
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
/* Enable ADC DMA mode */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ SET_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN);
+#else
SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
+#endif
/* Start the DMA channel */
tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
@@ -1857,13 +2228,21 @@
__HAL_LOCK(hadc);
/* 1. Stop potential ADC group regular conversion on going */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+#else
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Disable ADC peripheral if conversions are effectively stopped */
if (tmp_hal_status == HAL_OK)
{
/* Disable ADC DMA (ADC DMA configuration of continous requests is kept) */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN);
+#else
CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
+#endif
/* Disable the DMA channel (in case of DMA in circular mode or stop */
/* while DMA transfer is on going) */
@@ -1898,9 +2277,15 @@
if (tmp_hal_status == HAL_OK)
{
/* Set ADC state */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_READY);
+#else
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_READY);
+#endif /* ADC_SUPPORT_2_5_MSPS */
}
}
@@ -1953,9 +2338,11 @@
uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */
uint32_t tmp_isr = hadc->Instance->ISR;
uint32_t tmp_ier = hadc->Instance->IER;
+#if !defined (ADC_SUPPORT_2_5_MSPS)
uint32_t tmp_adc_inj_is_trigger_source_sw_start;
uint32_t tmp_adc_reg_is_trigger_source_sw_start;
uint32_t tmp_cfgr;
+#endif
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -1999,7 +2386,11 @@
if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
{
/* Carry on if continuous mode is disabled */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ if (READ_BIT (hadc->Instance->CFGR1, ADC_CFGR1_CONT) != ADC_CFGR1_CONT)
+#else
if (READ_BIT (hadc->Instance->CFGR, ADC_CFGR_CONT) != ADC_CFGR_CONT)
+#endif
{
/* If End of Sequence is reached, disable interrupts */
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
@@ -2053,6 +2444,9 @@
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
}
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */
if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
(((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)))
@@ -2074,44 +2468,46 @@
/* group having no further conversion upcoming (same conditions as */
/* regular group interruption disabling above), */
/* and if injected scan sequence is completed. */
- if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) ||
- ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) &&
- ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
- (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))))
+ if (tmp_adc_inj_is_trigger_source_sw_start != 0UL)
{
- /* If End of Sequence is reached, disable interrupts */
- if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
+ if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) ||
+ ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
+ (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))
{
- /* Particular case if injected contexts queue is enabled: */
- /* when the last context has been fully processed, JSQR is reset */
- /* by the hardware. Even if no injected conversion is planned to come */
- /* (queue empty, triggers are ignored), it can start again */
- /* immediately after setting a new context (JADSTART is still set). */
- /* Therefore, state of HAL ADC injected group is kept to busy. */
- if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM) == 0UL)
+ /* If End of Sequence is reached, disable interrupts */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
{
- /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
- /* JADSTART==0 (no conversion on going) */
- if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ /* Particular case if injected contexts queue is enabled: */
+ /* when the last context has been fully processed, JSQR is reset */
+ /* by the hardware. Even if no injected conversion is planned to come */
+ /* (queue empty, triggers are ignored), it can start again */
+ /* immediately after setting a new context (JADSTART is still set). */
+ /* Therefore, state of HAL ADC injected group is kept to busy. */
+ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM) == 0UL)
{
- /* Disable ADC end of sequence conversion interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
-
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
-
- if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+ /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
+ /* JADSTART==0 (no conversion on going) */
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
{
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ /* Disable ADC end of sequence conversion interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
- /* Set ADC error code to ADC peripheral internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+ if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
}
}
}
@@ -2132,6 +2528,7 @@
/* Clear injected group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* ========== Check Analog watchdog 1 flag ========== */
if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
@@ -2230,6 +2627,9 @@
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
}
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/* ========== Check Injected context queue overflow flag ========== */
if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
{
@@ -2249,6 +2649,7 @@
HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
}
@@ -2357,12 +2758,190 @@
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmp_config_internal_channel;
+ __IO uint32_t wait_loop_index = 0UL;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_CHANNEL(hadc, sConfig->Channel));
+ assert_param(IS_ADC_SAMPLING_TIME_COMMON(sConfig->SamplingTime));
+
+ if((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
+ (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD) )
+ {
+ assert_param(IS_ADC_REGULAR_RANK_SEQ_FIXED(sConfig->Rank));
+ }
+ else
+ {
+ assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
+
+ assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular group: */
+ /* - Channel number */
+ /* - Channel sampling time */
+ /* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* Configure channel: depending on rank setting, add it or remove it from */
+ /* ADC sequencer. */
+ /* If sequencer set to not fully configurable with channel rank set to */
+ /* none, remove the channel from the sequencer. */
+ /* Otherwise (sequencer set to fully configurable or to to not fully */
+ /* configurable with channel rank to be set), configure the selected */
+ /* channel. */
+ if(sConfig->Rank != ADC_RANK_NONE)
+ {
+ /* Regular sequence configuration */
+ /* Note: ADC channel configuration requires few ADC clock cycles */
+ /* to be ready. Processing of ADC settings in this function */
+ /* induce that a specific wait time is not necessary. */
+ /* For more details on ADC channel configuration ready, */
+ /* refer to function "LL_ADC_IsActiveFlag_CCRDY()". */
+ if((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
+ (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD) )
+ {
+ /* Sequencer set to not fully configurable: */
+ /* Set the channel by enabling the corresponding bitfield. */
+ LL_ADC_REG_SetSequencerChAdd(hadc->Instance, sConfig->Channel);
+ }
+ else
+ {
+ /* Sequencer set to fully configurable: */
+ /* Set the channel by entering it into the selected rank. */
+
+ /* Memorize the channel set into variable in HAL ADC handle */
+ MODIFY_REG(hadc->ADCGroupRegularSequencerRanks,
+ ADC_CHSELR_SQ1 << (sConfig->Rank & 0x1FUL),
+ __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel) << (sConfig->Rank & 0x1FUL));
+
+ /* If the selected rank is below ADC group regular sequencer length, */
+ /* apply the configuration in ADC register. */
+ /* Note: Otherwise, configuration is not applied. */
+ /* To apply it, parameter'NbrOfConversion' must be increased. */
+ if(((sConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion)
+ {
+ LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
+ }
+ }
+
+ /* Set sampling time of the selected ADC channel */
+ LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
+
+ /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
+ /* internal measurement paths enable: If internal channel selected, */
+ /* enable dedicated internal buffers and path. */
+ /* Note: these internal measurement paths can be disabled using */
+ /* HAL_ADC_DeInit() or removing the channel from sequencer with */
+ /* channel configuration parameter "Rank". */
+ if(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
+ {
+ tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+
+ /* If the requested internal measurement path has already been enabled, */
+ /* bypass the configuration processing. */
+ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
+
+ /* Delay for temperature sensor stabilization time */
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially */
+ /* CPU processing cycles, scaling in us split to not */
+ /* exceed 32 bits register capacity and handle low frequency. */
+ wait_loop_index = (((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))) + 1UL);
+ while(wait_loop_index != 0UL)
+ {
+ wait_loop_index--;
+ }
+ }
+ else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
+ }
+ else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
+ }
+ else
+ {
+ /* nothing to do */
+ }
+ }
+ }
+ else
+ {
+ /* Regular sequencer configuration */
+ /* Note: Case of sequencer set to fully configurable: */
+ /* Sequencer rank cannot be disabled, only affected to */
+ /* another channel. */
+ /* To remove a rank, use parameter 'NbrOfConversion". */
+ if((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
+ (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD) )
+ {
+ /* Sequencer set to not fully configurable: */
+ /* Reset the channel by disabling the corresponding bitfield. */
+ LL_ADC_REG_SetSequencerChRem(hadc->Instance, sConfig->Channel);
+ }
+
+ /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */
+ /* If internal channel selected, enable dedicated internal buffers and */
+ /* paths. */
+ if(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
+ {
+ tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+
+ if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), ~LL_ADC_PATH_INTERNAL_TEMPSENSOR & tmp_config_internal_channel);
+ }
+ else if (sConfig->Channel == ADC_CHANNEL_VBAT)
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), ~LL_ADC_PATH_INTERNAL_VBAT & tmp_config_internal_channel);
+ }
+ else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), ~LL_ADC_PATH_INTERNAL_VREFINT & tmp_config_internal_channel);
+ }
+ else
+ {
+ /* nothing to do */
+ }
+ }
+ }
+ }
+
+ /* If a conversion is on going on regular group, no update on regular */
+ /* channel could be done on neither of the channel configuration structure */
+ /* parameters. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+#else
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmpOffsetShifted;
uint32_t tmp_config_internal_channel;
__IO uint32_t wait_loop_index = 0;
+#if !defined (ADC_SUPPORT_2_5_MSPS)
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
+#endif
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -2404,11 +2983,15 @@
/* conversion on going on regular group: */
/* - Channel sampling time */
/* - Channel offset */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+#else
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
)
+#endif /* ADC_SUPPORT_2_5_MSPS */
{
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
@@ -2549,6 +3132,7 @@
/* Process unlocked */
__HAL_UNLOCK(hadc);
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Return function status */
return tmp_hal_status;
@@ -2575,8 +3159,10 @@
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmpAWDHighThresholdShifted;
uint32_t tmpAWDLowThresholdShifted;
+#if !defined (ADC_SUPPORT_2_5_MSPS)
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
+#endif
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -2584,14 +3170,23 @@
assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ if(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)
+#else
if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC))
+#endif
{
assert_param(IS_ADC_CHANNEL(hadc, AnalogWDGConfig->Channel));
}
/* Verify thresholds range */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Verify if thresholds are within the selected ADC resolution */
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
+#else
if (hadc->Init.OversamplingMode == ENABLE)
{
/* Case of oversampling enabled: depending on ratio and shift configuration,
@@ -2606,6 +3201,7 @@
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
}
+#endif
/* Process locked */
__HAL_LOCK(hadc);
@@ -2615,11 +3211,15 @@
/* conversion on going on ADC groups regular and injected: */
/* - Analog watchdog channels */
/* - Analog watchdog thresholds */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+#else
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
)
+#endif /* ADC_SUPPORT_2_5_MSPS */
{
/* Analog watchdog configuration */
if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
@@ -2634,6 +3234,9 @@
LL_ADC_GROUP_REGULAR));
break;
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
LL_ADC_GROUP_INJECTED));
@@ -2643,11 +3246,15 @@
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
LL_ADC_GROUP_REGULAR_INJECTED));
break;
+#endif /* ADC_SUPPORT_2_5_MSPS */
case ADC_ANALOGWATCHDOG_ALL_REG:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG);
break;
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
case ADC_ANALOGWATCHDOG_ALL_INJEC:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ);
break;
@@ -2655,6 +3262,7 @@
case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
break;
+#endif /* ADC_SUPPORT_2_5_MSPS */
default: /* ADC_ANALOGWATCHDOG_NONE */
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE);
@@ -2689,14 +3297,19 @@
LL_ADC_DisableIT_AWD1(hadc->Instance);
}
}
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Feature "ADC analog watchdog 2 and 3" not available on ADC peripheral of this STM32WB device */
+#else
/* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
else
{
switch (AnalogWDGConfig->WatchdogMode)
{
case ADC_ANALOGWATCHDOG_SINGLE_REG:
+#if !defined (ADC_SUPPORT_2_5_MSPS)
case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
+#endif
/* Update AWD by bitfield to keep the possibility to monitor */
/* several channels by successive calls of this function. */
if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
@@ -2710,9 +3323,15 @@
break;
case ADC_ANALOGWATCHDOG_ALL_REG:
+#if !defined (ADC_SUPPORT_2_5_MSPS)
case ADC_ANALOGWATCHDOG_ALL_INJEC:
case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
+#endif
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG);
+#else
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
+#endif
break;
default: /* ADC_ANALOGWATCHDOG_NONE */
@@ -2772,6 +3391,7 @@
}
}
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
}
/* If a conversion is on going on ADC group regular or injected, no update */
@@ -2861,13 +3481,55 @@
* @param hadc ADC handle
* @param ConversionGroup ADC group regular and/or injected.
* This parameter can be one of the following values:
- * @arg @ref ADC_REGULAR_GROUP ADC regular conversion type.
- * @arg @ref ADC_INJECTED_GROUP ADC injected conversion type.
- * @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type.
+ * @arg @ref ADC_REGULAR_GROUP ADC regular conversion type.
+ * @arg @ref ADC_INJECTED_GROUP (1) ADC injected conversion type.
+ * @arg @ref ADC_REGULAR_INJECTED_GROUP (1) ADC regular and injected conversion type.
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ UNUSED(ConversionGroup);
+
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Verification if ADC is not already stopped on regular group to bypass */
+ /* this function if not needed. */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
+ {
+ /* Stop potential conversion on going on regular group */
+ /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
+ if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
+ {
+ /* Stop ADC group regular conversion */
+ LL_ADC_REG_StopConversion(hadc->Instance);
+ }
+
+ /* Wait for conversion effectively stopped */
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ while((hadc->Instance->CR & ADC_CR_ADSTART) != 0UL)
+ {
+ if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ }
+
+ }
+#else
uint32_t tickstart;
uint32_t Conversion_Timeout_CPU_cycles = 0UL;
uint32_t conversion_group_reassigned = ConversionGroup;
@@ -2982,6 +3644,7 @@
}
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Return HAL status */
return HAL_OK;
@@ -2999,6 +3662,7 @@
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
{
uint32_t tickstart;
+ __IO uint32_t wait_loop_index = 0UL;
/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
/* enabling phase not yet completed: flag ADC ready not yet set). */
@@ -3007,7 +3671,11 @@
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
{
/* Check if conditions to enable the ADC are fulfilled */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
+#else
if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
+#endif
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
@@ -3021,33 +3689,54 @@
/* Enable the ADC peripheral */
LL_ADC_Enable(hadc->Instance);
- /* Wait for ADC effectively enabled */
- tickstart = HAL_GetTick();
-
- while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
+ if((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL)
{
- /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
- has been cleared (after a calibration), ADEN bit is reset by the
- calibration logic.
- The workaround is to continue setting ADEN until ADRDY is becomes 1.
- Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
- 4 ADC clock cycle duration */
- /* Note: Test of ADC enabled required due to hardware constraint to */
- /* not enable ADC if already enabled. */
- if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ /* Delay for temperature sensor buffer stabilization time */
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially */
+ /* CPU processing cycles, scaling in us split to not */
+ /* exceed 32 bits register capacity and handle low frequency. */
+ wait_loop_index = (((LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))) + 1UL);
+ while(wait_loop_index != 0UL)
{
- LL_ADC_Enable(hadc->Instance);
+ wait_loop_index--;
}
+ }
- if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* If low power mode AutoPowerOff is enabled, power-on/off phases are */
+ /* performed automatically by hardware and flag ADC ready is not set. */
+ if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
+#endif /*ADC_SUPPORT_2_5_MSPS */
+ {
+ /* Wait for ADC effectively enabled */
+ tickstart = HAL_GetTick();
+
+ while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
{
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC peripheral internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- return HAL_ERROR;
+ /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
+ has been cleared (after a calibration), ADEN bit is reset by the
+ calibration logic.
+ The workaround is to continue setting ADEN until ADRDY is becomes 1.
+ Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
+ 4 ADC clock cycle duration */
+ /* Note: Test of ADC enabled required due to hardware constraint to */
+ /* not enable ADC if already enabled. */
+ if(LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ {
+ LL_ADC_Enable(hadc->Instance);
+ }
+
+ if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
}
}
}
@@ -3076,7 +3765,11 @@
)
{
/* Check if conditions to disable the ADC are fulfilled */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ if ((hadc->Instance->CR & (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
+#else
if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
+#endif
{
/* Disable the ADC peripheral */
LL_ADC_Disable(hadc->Instance);
@@ -3136,6 +3829,41 @@
/* by external trigger, continuous mode or scan sequence on going */
/* to disable interruption. */
/* Is it the end of the regular sequence ? */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ if( (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+ && (hadc->Init.ContinuousConvMode == DISABLE)
+ )
+ {
+ /* If End of Sequence is reached, disable interrupts */
+ if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
+ {
+ /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
+ /* ADSTART==0 (no conversion on going) */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* Disable ADC end of single conversion interrupt on group regular */
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* HAL_Start_IT(), but is not disabled here because can be used */
+ /* by overrun IRQ process below. */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* Change ADC state to error state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+ }
+
+#else
if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL)
{
/* Are conversions software-triggered ? */
@@ -3167,6 +3895,7 @@
}
}
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Conversion complete callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
diff --git a/Src/stm32wbxx_hal_adc_ex.c b/Src/stm32wbxx_hal_adc_ex.c
index 1327585..23ed341 100644
--- a/Src/stm32wbxx_hal_adc_ex.c
+++ b/Src/stm32wbxx_hal_adc_ex.c
@@ -3,18 +3,18 @@
* @file stm32wbxx_hal_adc_ex.c
* @author MCD Application Team
* @brief This file provides firmware functions to manage the following
- * functionalities of the Analog to Digital Convertor (ADC)
+ * functionalities of the Analog to Digital Converter (ADC)
* peripheral:
* + Operation functions
* ++ Start, stop, get result of conversions of ADC group injected,
- * using 2 possible modes: polling, interruption.
+ * using 2 possible modes: polling, interruption (not available on devices: STM32WB10xx, STM32WB15xx).
* ++ Calibration
* +++ ADC automatic self-calibration
* +++ Calibration factors get or set
* + Control functions
- * ++ Channels configuration on ADC group injected
+ * ++ Channels configuration on ADC group injected (not available on devices: STM32WB10xx, STM32WB15xx)
* + State functions
- * ++ ADC group injected contexts queue management
+ * ++ ADC group injected contexts queue management (not available on devices: STM32WB10xx, STM32WB15xx)
* Other functions (generic functions) are available in file
* "stm32wbxx_hal_adc.c".
*
@@ -99,12 +99,12 @@
(+) Get calibration factors for single or differential ending.
(+) Set calibration factors for single or differential ending.
- (+) Start conversion of ADC group injected.
- (+) Stop conversion of ADC group injected.
- (+) Poll for conversion complete on ADC group injected.
- (+) Get result of ADC group injected channel conversion.
- (+) Start conversion of ADC group injected and enable interruptions.
- (+) Stop conversion of ADC group injected and disable interruptions.
+ (+) Start conversion of ADC group injected (not available on devices: STM32WB10xx, STM32WB15xx).
+ (+) Stop conversion of ADC group injected (not available on devices: STM32WB10xx, STM32WB15xx).
+ (+) Poll for conversion complete on ADC group injected (not available on devices: STM32WB10xx, STM32WB15xx).
+ (+) Get result of ADC group injected channel conversion (not available on devices: STM32WB10xx, STM32WB15xx).
+ (+) Start conversion of ADC group injected and enable interruptions (not available on devices: STM32WB10xx, STM32WB15xx).
+ (+) Stop conversion of ADC group injected and disable interruptions (not available on devices: STM32WB10xx, STM32WB15xx).
@endverbatim
* @{
@@ -118,11 +118,17 @@
* @param SingleDiff Selection of single-ended or differential input
* This parameter can be one of the following values:
* @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
- * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
+ * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended (1)
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ UNUSED(SingleDiff);
+#endif
+
HAL_StatusTypeDef tmp_hal_status;
__IO uint32_t wait_loop_index = 0UL;
@@ -142,12 +148,22 @@
if (tmp_hal_status == HAL_OK)
{
/* Set ADC state */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_BUSY_INTERNAL);
+#else
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_BUSY_INTERNAL);
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Start ADC calibration in mode single-ended or differential */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ LL_ADC_StartCalibration(hadc->Instance);
+#else
LL_ADC_StartCalibration(hadc->Instance, SingleDiff);
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Wait for calibration completion */
while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
@@ -192,17 +208,27 @@
* @param hadc ADC handle.
* @param SingleDiff This parameter can be only:
* @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
- * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
+ * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended (1)
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @retval Calibration value.
*/
uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ UNUSED(SingleDiff);
+#endif
+
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
/* Return the selected ADC calibration value */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ return LL_ADC_GetCalibrationFactor(hadc->Instance);
+#else
return LL_ADC_GetCalibrationFactor(hadc->Instance, SingleDiff);
+#endif
}
/**
@@ -211,15 +237,25 @@
* @param hadc ADC handle
* @param SingleDiff This parameter can be only:
* @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
- * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
+ * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended (1)
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
* @retval HAL state
*/
HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ UNUSED(SingleDiff);
+#endif
+
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmp_adc_is_conversion_on_going_regular;
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
uint32_t tmp_adc_is_conversion_on_going_injected;
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -232,15 +268,27 @@
/* Verification of hardware constraints before modifying the calibration */
/* factors register: ADC must be enabled, no conversion on going. */
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+#endif /* ADC_SUPPORT_2_5_MSPS */
if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
&& (tmp_adc_is_conversion_on_going_regular == 0UL)
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
+#endif /* ADC_SUPPORT_2_5_MSPS */
)
{
/* Set the selected ADC calibration value */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ LL_ADC_SetCalibrationFactor(hadc->Instance, CalibrationFactor);
+#else
LL_ADC_SetCalibrationFactor(hadc->Instance, SingleDiff, CalibrationFactor);
+#endif
}
else
{
@@ -260,6 +308,9 @@
return tmp_hal_status;
}
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/**
* @brief Enable ADC, start conversion of injected group.
* @note Interruptions enabled in this function: None.
@@ -705,7 +756,11 @@
/* Return function status */
return tmp_hal_status;
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/**
* @brief Get ADC injected group conversion result.
* @note Reading register JDRx automatically clears ADC flag JEOC
@@ -797,6 +852,7 @@
function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
*/
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Analog watchdog 2 callback in non-blocking mode.
@@ -844,6 +900,9 @@
*/
}
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/**
* @brief Stop ADC conversion of regular group (and injected channels in
* case of auto_injection mode), disable ADC peripheral if no
@@ -1038,11 +1097,15 @@
/* Return function status */
return tmp_hal_status;
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @}
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
* @brief ADC Extended Peripheral Control functions
*
@@ -1506,7 +1569,11 @@
/* Return function status */
return tmp_hal_status;
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/**
* @brief Enable Injected Queue
* @note This function resets CFGR register JQDIS bit in order to enable the
@@ -1584,6 +1651,7 @@
return tmp_hal_status;
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Disable ADC voltage regulator.
@@ -1615,8 +1683,11 @@
return tmp_hal_status;
}
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature " ADC deep power-down" not available on ADC peripheral of this STM32WB device */
+#else
/**
- * @brief Enter ADC deep-power-down mode
+ * @brief Enter ADC deep power-down mode
* @note This mode is achieved in setting DEEPPWD bit and allows to save power
* in reducing leakage currents. It is particularly interesting before
* entering stop modes.
@@ -1651,6 +1722,7 @@
return tmp_hal_status;
}
+#endif
/**
* @}
diff --git a/Src/stm32wbxx_hal_comp.c b/Src/stm32wbxx_hal_comp.c
index 91c1979..be27bc5 100644
--- a/Src/stm32wbxx_hal_comp.c
+++ b/Src/stm32wbxx_hal_comp.c
@@ -18,7 +18,8 @@
[..]
The STM32WBxx device family integrates two analog comparators instances:
- COMP1, COMP2.
+ COMP1, COMP2 except for the STM32WB15xx, STM32WB10xx products featuring only
+ one instance: COMP1.
In the rest of the file, all comments related to a pair of comparators are not
applicable to STM32WB15xx, STM32WB10xx.
(#) Comparators input minus (inverting input) and input plus (non inverting input)
diff --git a/Src/stm32wbxx_hal_cryp.c b/Src/stm32wbxx_hal_cryp.c
index 12c62c5..31e9f38 100644
--- a/Src/stm32wbxx_hal_cryp.c
+++ b/Src/stm32wbxx_hal_cryp.c
@@ -6,7 +6,7 @@
* This file provides firmware functions to manage the following
* functionalities of the Cryptography (CRYP) peripheral:
* + Initialization, de-initialization, set config and get config functions
- * + DES/TDES, AES processing functions
+ * + AES processing functions
* + DMA callback functions
* + CRYP IRQ handler management
* + Peripheral State functions
@@ -32,8 +32,8 @@
(+++) Associate the initialized DMA handle to the CRYP DMA handle
using __HAL_LINKDMA()
(+++) Configure the priority and enable the NVIC for the transfer complete
- interrupt on the two DMA Streams. The output stream should have higher
- priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
+ interrupt on the two DMA channels. The output channel should have higher
+ priority than the input channel HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
(#)Initialize the CRYP according to the specified parameters :
(##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
@@ -44,9 +44,13 @@
(+++) In some specific configurations, the key is written by the application
code out of the HAL scope. In that case, user can still resort to the
HAL APIs as usual but must make sure that pKey pointer is set to NULL.
+ (##) The DataWidthUnit field. It specifies whether the data length (or the payload length for authentication
+ algorithms) is in words or bytes.
(##) The Header used only in AES GCM and CCM Algorithm for authentication.
- (##) The HeaderSize The size of header buffer in word.
- (##) The B0 block is the first authentication block used only in AES CCM mode.
+ (##) The HeaderSize providing the size of the header buffer in words or bytes, depending upon HeaderWidthUnit field.
+ (##) The HeaderWidthUnit field. It specifies whether the header length (for authentication algorithms) is in words or bytes.
+ (##) The B0 block is the first authentication block used only in AES CCM mode.
+ (##) The KeyIVConfigSkip used to process several messages in a row (please see more information below).
(#)Three processing (encryption/decryption) functions are available:
(##) Polling mode: encryption and decryption APIs are blocking functions
@@ -321,6 +325,7 @@
#define CRYP_PHASE_HEADER_SUSPENDED 0x00000004U /*!< GCM/GMAC/CCM header phase is suspended */
#define CRYP_PHASE_PAYLOAD_SUSPENDED 0x00000005U /*!< GCM/CCM payload phase is suspended */
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+#define CRYP_PHASE_HEADER_DMA_FEED 0x00000006U /*!< GCM/GMAC/CCM header is fed to the peripheral in DMA mode */
#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode(Mode 1) */
#define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC decryptions (Mode 2) */
@@ -345,9 +350,7 @@
* @{
*/
-#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~AES_CR_GCMPH);\
- (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
- }while(0U)
+#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_GCMPH, (uint32_t)(__PHASE__))
/**
* @}
@@ -361,6 +364,7 @@
*/
static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
+static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size);
static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
@@ -370,6 +374,7 @@
static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp);
static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
@@ -383,6 +388,7 @@
static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output);
static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input);
@@ -1185,7 +1191,7 @@
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input Pointer to the input buffer (plaintext)
- * @param Size Length of the plaintext buffer in word.
+ * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
* @param Output Pointer to the output buffer(ciphertext)
* @param Timeout Specify Timeout value
* @retval HAL status
@@ -1285,7 +1291,7 @@
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input Pointer to the input buffer (ciphertext )
- * @param Size Length of the plaintext buffer in word.
+ * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
* @param Output Pointer to the output buffer(plaintext)
* @param Timeout Specify Timeout value
* @retval HAL status
@@ -1385,7 +1391,7 @@
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input Pointer to the input buffer (plaintext)
- * @param Size Length of the plaintext buffer in word
+ * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
* @param Output Pointer to the output buffer(ciphertext)
* @retval HAL status
*/
@@ -1495,7 +1501,7 @@
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input Pointer to the input buffer (ciphertext )
- * @param Size Length of the plaintext buffer in word.
+ * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
* @param Output Pointer to the output buffer(plaintext)
* @retval HAL status
*/
@@ -1604,7 +1610,7 @@
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input Pointer to the input buffer (plaintext)
- * @param Size Length of the plaintext buffer in word.
+ * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
* @param Output Pointer to the output buffer(ciphertext)
* @retval HAL status
*/
@@ -1731,7 +1737,7 @@
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input Pointer to the input buffer (ciphertext )
- * @param Size Length of the plaintext buffer in word
+ * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
* @param Output Pointer to the output buffer(plaintext)
* @retval HAL status
*/
@@ -1869,7 +1875,7 @@
/* Clear computation complete flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || (hcryp->Init.Algorithm == CRYP_AES_CCM))
{
/* if header phase */
@@ -1882,18 +1888,6 @@
CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
}
}
- else if (hcryp->Init.Algorithm == CRYP_AES_CCM)
- {
- /* if header phase */
- if (hcryp->Init.HeaderSize >= hcryp->CrypHeaderCount)
- {
- CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
- }
- else /* if payload phase */
- {
- CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
- }
- }
else /* AES Algorithm ECB,CBC or CTR*/
{
CRYP_AES_IT(hcryp);
@@ -2502,10 +2496,81 @@
static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
{
CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ uint32_t loopcounter;
+ uint32_t headersize_in_bytes;
+ uint32_t tmp;
+ uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
/* Stop the DMA transfers to the IN FIFO by clearing to "0" the DMAINEN */
CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
+ if (hcryp->Phase == CRYP_PHASE_HEADER_DMA_FEED)
+ {
+ /* DMA is disabled, CCF is meaningful. Wait for computation completion before moving forward */
+ CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
+ }
+ else
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize;
+ }
+
+ if ((headersize_in_bytes % 16U) != 0U)
+ {
+ /* Write last words that couldn't be fed by DMA */
+ hcryp->CrypHeaderCount = (uint16_t)((headersize_in_bytes / 16U) * 4U);
+ for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ /* If the header size is a multiple of words */
+ if ((headersize_in_bytes % 4U) == 0U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+ else
+ {
+ /* Enter last bytes, padded with zeros */
+ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
+ hcryp->Instance->DINR = tmp;
+ loopcounter++;
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+
+ /* Wait for computation completion before moving forward */
+ CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE);
+ } /* if ((headersize_in_bytes % 16U) != 0U) */
+
+ /* Set to 0 the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
+
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Initiate payload DMA IN and processed data DMA OUT transfers */
+ (void)CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp);
+ }
+
/* Call input data transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Input complete callback*/
@@ -2526,7 +2591,7 @@
uint32_t count;
uint32_t npblb;
uint32_t lastwordsize;
- uint32_t temp; /* Temporary CrypOutBuff */
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
uint32_t mode;
CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
@@ -2579,44 +2644,21 @@
}
/*Wait on CCF flag*/
- count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
- do
- {
- count-- ;
- if (count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
- /*Call registered error callback*/
- hcryp->ErrorCallback(hcryp);
-#else
- /*Call legacy weak error callback*/
- HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE);
/*Read the output block from the output FIFO */
for (count = 0U; count < 4U; count++)
{
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUTR;
+ temp[count] = hcryp->Instance->DOUTR;
+ }
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ count = 0U;
+ while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (count<4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[count];
hcryp->CrypOutCount++;
+ count++;
}
}
@@ -2675,7 +2717,7 @@
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param inputaddr address of the input buffer
- * @param Size size of the input buffer, must be a multiple of 16.
+ * @param Size size of the input and output buffers in words, must be a multiple of 4
* @param outputaddr address of the output buffer
* @retval None
*/
@@ -2734,6 +2776,43 @@
}
/**
+ * @brief Set the DMA configuration and start the header DMA transfer
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param inputaddr address of the input buffer
+ * @param Size size of the input buffer in words, must be a multiple of 4
+ * @retval None
+ */
+static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size)
+{
+ /* Set the CRYP DMA transfer complete callback */
+ hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
+
+ /* Set the DMA input error callback */
+ hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
+
+ /* Mark that header is fed to the peripheral in DMA mode */
+ hcryp->Phase = CRYP_PHASE_HEADER_DMA_FEED;
+ /* Enable the DMA input stream */
+ if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size) != HAL_OK)
+ {
+ /* DMA error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ /* Call error callback */
+ }
+
+ /* Enable IN DMA requests */
+ SET_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
+
+ return HAL_OK;
+}
+
+/**
* @brief Process Data: Write Input data in polling mode and used in AES functions.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
@@ -3162,6 +3241,12 @@
uint32_t lastwordsize;
uint32_t npblb;
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+ uint32_t headersize_in_bytes;
+ uint32_t tmp;
+ uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
+
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED))
@@ -3171,6 +3256,17 @@
}
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+ /* Manage header size given in bytes to handle cases where
+ header size is not a multiple of 4 bytes */
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
+ }
+ else
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize;
+ }
+
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
if (hcryp->KeyIVConfig == 1U)
@@ -3337,27 +3433,43 @@
}
}
}
- else if ((hcryp->Init.HeaderSize) < 4U)
+ /* Enter header data */
+ /* Cher first whether header length is small enough to enter the full header in one shot */
+ else if (headersize_in_bytes <= 16U)
{
- for (loopcounter = 0U; loopcounter < hcryp->Init.HeaderSize ; loopcounter++)
+ /* Write header data, padded with zeros if need be */
+ for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
}
+ /* If the header size is a multiple of words */
+ if ((headersize_in_bytes % 4U) == 0U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ hcryp->CrypHeaderCount++;
+ }
+ }
+ else
+ {
+ /* Enter last bytes, padded with zeros */
+ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
+ hcryp->Instance->DINR = tmp;
+ loopcounter++;
+ hcryp->CrypHeaderCount++ ;
+ /* Pad the data with zeros to have a complete block */
while (loopcounter < 4U)
{
- /* pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0x0U;
loopcounter++;
+ hcryp->CrypHeaderCount++;
+ }
}
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Select payload phase once the header phase is performed */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Set to 0 the number of non-valid bytes using NPBLB register*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
/* Call Input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
@@ -3370,7 +3482,8 @@
}
else
{
- /* Write the input block in the IN FIFO */
+ /* Write the first input header block in the Input FIFO,
+ the following header data will be fed after interrupt occurrence */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
@@ -3482,12 +3595,7 @@
*/
static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
{
- __IO uint32_t count;
- uint16_t wordsize = hcryp->Size / 4U ;
- uint32_t index;
- uint32_t npblb;
- uint32_t lastwordsize;
- uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t count;
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
@@ -3566,122 +3674,16 @@
return HAL_ERROR;
}
- /************************ Payload phase ************************************/
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Set to 0 the number of non-valid bytes using NPBLB register*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
-
- /* Select payload phase once the header phase is performed */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
+ }
+ else
+ {
+ /* Initialization and header phases already done, only do payload phase */
+ if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
} /* if (DoKeyIVConfig == 1U) */
- if (hcryp->Size == 0U)
- {
- /* Process unLocked */
- __HAL_UNLOCK(hcryp);
-
- /* Change the CRYP state and phase */
- hcryp->State = HAL_CRYP_STATE_READY;
- }
- else if (hcryp->Size >= 16U)
- {
- /*DMA transfer must not include the last block in case of Size is not %16 */
- wordsize = wordsize - (wordsize % 4U);
-
- /*DMA transfer */
- CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr));
- }
- else /* length of input data is < 16 */
- {
- /* Compute the number of padding bytes in last block of payload */
- npblb = 16U - (uint32_t)hcryp->Size;
-
- /* Set Npblb in case of AES GCM payload encryption to get right tag*/
- if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
- {
- /* Specify the number of non-valid bytes using NPBLB register*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
- }
-
- /* Enable CRYP to start the final phase */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Number of valid words (lastwordsize) in last block */
- if ((npblb % 4U) == 0U)
- {
- lastwordsize = (16U - npblb) / 4U;
- }
- else
- {
- lastwordsize = ((16U - npblb) / 4U) + 1U;
- }
-
- /* last block optionally pad the data with zeros*/
- for (index = 0U; index < lastwordsize; index ++)
- {
- /* Write the last Input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
- hcryp->CrypInCount++;
- }
- while (index < 4U)
- {
- /* pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0U;
- index++;
- }
- /* Wait for CCF flag to be raised */
- count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
- do
- {
- count-- ;
- if (count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
- /*Call registered error callback*/
- hcryp->ErrorCallback(hcryp);
-#else
- /*Call legacy weak error callback*/
- HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
- /*Read the output block from the output FIFO */
- for (index = 0U; index < 4U; index++)
- {
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp[index] = hcryp->Instance->DOUTR;
- }
- for (index = 0U; index < lastwordsize; index++)
- {
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
- hcryp->CrypOutCount++;
- }
-
- /* Change the CRYP state to ready */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- }
-
/* Return function status */
return HAL_OK;
}
@@ -4196,12 +4198,7 @@
*/
static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
{
- __IO uint32_t count = 0U;
- uint16_t wordsize = hcryp->Size / 4U ;
- uint32_t index;
- uint32_t npblb;
- uint32_t lastwordsize;
- uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t count;
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
@@ -4282,119 +4279,16 @@
return HAL_ERROR;
}
- /******************** Payload phase *****************************************/
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Set to 0 the number of non-valid bytes using NPBLB register*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
-
- /* Select payload phase once the header phase is performed */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
-
+ }
+ else
+ {
+ /* Initialization and header phases already done, only do payload phase */
+ if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
} /* if (DoKeyIVConfig == 1U) */
- if (hcryp->Size == 0U)
- {
- /* Process unLocked */
- __HAL_UNLOCK(hcryp);
-
- /* Change the CRYP state and phase */
- hcryp->State = HAL_CRYP_STATE_READY;
- }
- else if (hcryp->Size >= 16U)
- {
- /*DMA transfer must not include the last block in case of Size is not %16 */
- wordsize = wordsize - (wordsize % 4U);
-
- /*DMA transfer */
- CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr));
- }
- else /* length of input data is < 16 */
- {
- /* Compute the number of padding bytes in last block of payload */
- npblb = 16U - (uint32_t)hcryp->Size;
-
- /* Set Npblb in case of AES CCM payload decryption to get right tag*/
- if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT)
- {
- /* Specify the number of non-valid bytes using NPBLB register*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
- }
-
- /* Number of valid words (lastwordsize) in last block */
- if ((npblb % 4U) == 0U)
- {
- lastwordsize = (16U - npblb) / 4U;
- }
- else
- {
- lastwordsize = ((16U - npblb) / 4U) + 1U;
- }
-
- /* last block optionally pad the data with zeros*/
- for (index = 0U; index < lastwordsize; index ++)
- {
- /* Write the last Input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
- hcryp->CrypInCount++;
- }
- while (index < 4U)
- {
- /* pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0U;
- index++;
- }
- /* Wait for CCF flag to be raised */
- count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
- do
- {
- count-- ;
- if (count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
- /*Call registered error callback*/
- hcryp->ErrorCallback(hcryp);
-#else
- /*Call legacy weak error callback*/
- HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
- /*Read the output block from the output FIFO */
- for (index = 0U; index < 4U; index++)
- {
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp[index] = hcryp->Instance->DOUTR;
- }
- for (index = 0U; index < lastwordsize; index++)
- {
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
- hcryp->CrypOutCount++;
- }
-
- /* Change the CRYP state to ready */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- }
-
/* Return function status */
return HAL_OK;
}
@@ -4546,6 +4440,122 @@
/**
+ * @brief Sets the payload phase in DMA mode
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval state
+ */
+static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcryp)
+{
+ uint16_t wordsize = hcryp->Size / 4U ;
+ uint32_t index;
+ uint32_t npblb;
+ uint32_t lastwordsize;
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t count;
+ uint32_t reg;
+
+ /************************ Payload phase ************************************/
+ if (hcryp->Size == 0U)
+ {
+ /* Process unLocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Change the CRYP state and phase */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ }
+ else if (hcryp->Size >= 16U)
+ {
+ /*DMA transfer must not include the last block in case of Size is not %16 */
+ wordsize = wordsize - (wordsize % 4U);
+
+ /*DMA transfer */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr));
+ }
+ else /* length of input data is < 16 */
+ {
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = 16U - (uint32_t)hcryp->Size;
+
+ /* Set Npblb in case of AES GCM payload encryption or AES CCM payload decryption to get right tag*/
+ reg = hcryp->Instance->CR & (AES_CR_CHMOD|AES_CR_MODE);
+ if ((reg == (CRYP_AES_GCM_GMAC|CRYP_OPERATINGMODE_ENCRYPT)) ||\
+ (reg == (CRYP_AES_CCM|CRYP_OPERATINGMODE_DECRYPT)))
+ {
+ /* Specify the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
+ }
+
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) == 0U)
+ {
+ lastwordsize = (16U - npblb) / 4U;
+ }
+ else
+ {
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
+ }
+
+ /* last block optionally pad the data with zeros*/
+ for (index = 0U; index < lastwordsize; index ++)
+ {
+ /* Write the last Input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ }
+ while (index < 4U)
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0U;
+ index++;
+ }
+ /* Wait for CCF flag to be raised */
+ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ /*Read the output block from the output FIFO */
+ for (index = 0U; index < 4U; index++)
+ {
+ /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+ temp[index] = hcryp->Instance->DOUTR;
+ }
+ for (index = 0U; index < lastwordsize; index++)
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
+ hcryp->CrypOutCount++;
+ }
+
+ /* Change the CRYP state to ready */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ }
+
+ return HAL_OK;
+}
+
+/**
* @brief Sets the header phase in polling mode
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module(Header & HeaderSize)
@@ -4557,7 +4567,9 @@
uint32_t loopcounter;
uint32_t size_in_bytes;
uint32_t tmp;
- uint32_t mask[4] = {0x0U, 0x0FFU, 0x0FFFFU, 0x0FFFFFFU};
+ uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
/***************************** Header phase for GCM/GMAC or CCM *********************************/
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
@@ -4659,9 +4671,9 @@
}
else
{
- /* Enter last bytes, padded with zeroes */
+ /* Enter last bytes, padded with zeros */
tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- tmp &= mask[size_in_bytes % 4U];
+ tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)];
hcryp->Instance->DINR = tmp;
loopcounter++;
/* Pad the data with zeros to have a complete block */
@@ -4691,17 +4703,14 @@
}
else
{
- if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
- {
- /*Workaround 1: only AES, before re-enabling the peripheral, datatype can be configured.*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
+ /*Workaround 1: only AES, before re-enabling the peripheral, datatype can be configured.*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
- }
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
}
/* Return function status */
return HAL_OK;
@@ -4715,143 +4724,112 @@
*/
static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp)
{
- __IO uint32_t count = 0U;
uint32_t loopcounter;
+ uint32_t headersize_in_bytes;
+ uint32_t tmp;
+ uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
/***************************** Header phase for GCM/GMAC or CCM *********************************/
- if ((hcryp->Init.HeaderSize != 0U))
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
{
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+ headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
+ }
+ else
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize;
+ }
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
- if ((hcryp->Init.HeaderSize % 4U) == 0U)
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* If header size is at least equal to 16 bytes, feed the header through DMA.
+ If size_in_bytes is not a multiple of blocks (is not a multiple of four 32-bit words ),
+ last bytes feeding and padding will be done in CRYP_DMAInCplt() */
+ if (headersize_in_bytes >= 16U)
+ {
+ /* Initiate header DMA transfer */
+ if (CRYP_SetHeaderDMAConfig(hcryp, (uint32_t)(hcryp->Init.Header), (uint16_t)((headersize_in_bytes / 16U) * 4U)) != HAL_OK)
{
- /* HeaderSize %4, no padding */
- for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
- {
- /* Write the input block in the data input register */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
-
- /*Wait on CCF flag*/
- count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
- do
- {
- count-- ;
- if (count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- }
- }
- else
- {
- /*Write header block in the IN FIFO without last block */
- for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
- {
- /* Write the Input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
-
- /*Wait on CCF flag*/
- count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
- do
- {
- count-- ;
- if (count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- }
- /* Last block optionally pad the data with zeros*/
- for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
- {
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- }
- while (loopcounter < 4U)
- {
- /* Pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0x0U;
- loopcounter++;
- }
-
- /*Wait on CCF flag*/
- count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
- do
- {
- count-- ;
- if (count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ return HAL_ERROR;
}
}
else
{
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+ if (headersize_in_bytes != 0U)
+ {
+ /* Header length is larger than 0 and strictly less than 16 bytes */
+ /* Write last complete words */
+ for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ /* If the header size is a multiple of words */
+ if ((headersize_in_bytes % 4U) == 0U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+ else
+ {
+ /* Enter last bytes, padded with zeros */
+ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
+ hcryp->Instance->DINR = tmp;
+ loopcounter++;
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
- }
+ if (CRYP_WaitOnCCFlag(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ } /* if (headersize_in_bytes != 0U) */
+
+ /* Move to payload phase if header length is null or
+ if the header length was less than 16 and header written by software instead of DMA */
+
+ /* Set to 0 the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
+
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Initiate payload DMA IN and processed data DMA OUT transfers */
+ if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ } /* if (headersize_in_bytes >= 16U) */
+
/* Return function status */
return HAL_OK;
}
@@ -4868,9 +4846,25 @@
uint32_t lastwordsize;
uint32_t npblb;
uint32_t mode;
+ uint32_t headersize_in_bytes;
+ uint32_t tmp;
+ uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
+
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
+ }
+ else
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize;
+ }
/***************************** Header phase *********************************/
- if (hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
+ /* Test whether or not the header phase is over.
+ If the test below is true, move to payload phase */
+ if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U))
{
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
@@ -4955,9 +4949,9 @@
}
}
}
- else if ((((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U))
+ else if ((((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U))
{
-
+ /* Can enter full 4 header words */
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
/* If suspension flag has been raised, suspend processing
only if not already at the end of the header */
@@ -4992,19 +4986,40 @@
hcryp->CrypHeaderCount++;
}
}
- else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/
+ else /* Write last header block (4 words), padded with zeros if needed */
{
- /* Last block optionally pad the data with zeros*/
- for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
+
+ for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
}
+ /* If the header size is a multiple of words */
+ if ((headersize_in_bytes % 4U) == 0U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ hcryp->CrypHeaderCount++;
+ }
+ }
+ else
+ {
+ /* Enter last bytes, padded with zeros */
+ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
+ hcryp->Instance->DINR = tmp;
+ loopcounter++;
+ hcryp->CrypHeaderCount++;
+ /* Pad the data with zeros to have a complete block */
while (loopcounter < 4U)
{
- /* pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0x0U;
loopcounter++;
+ hcryp->CrypHeaderCount++;
+ }
}
}
}
@@ -5014,6 +5029,7 @@
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module.
* @param Timeout Timeout duration.
+ * @note This function can only be used in thread mode.
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
@@ -5037,6 +5053,47 @@
return HAL_OK;
}
+/**
+ * @brief Wait for Computation Complete Flag (CCF) to raise then clear it.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Timeout Timeout duration.
+ * @note This function can be used in thread or handler mode.
+ * @retval HAL status
+ */
+static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+ uint32_t count = Timeout;
+
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+}
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
/**
diff --git a/Src/stm32wbxx_hal_flash_ex.c b/Src/stm32wbxx_hal_flash_ex.c
index ce93882..e7c9a5c 100644
--- a/Src/stm32wbxx_hal_flash_ex.c
+++ b/Src/stm32wbxx_hal_flash_ex.c
@@ -607,6 +607,7 @@
* @arg @ref OB_STOP_RST or @ref OB_STOP_NORST
* @arg @ref OB_STANDBY_RST or @ref OB_STANDBY_NORST
* @arg @ref OB_SHUTDOWN_RST or @ref OB_SHUTDOWN_NORST
+ * @arg @ref OB_IRH_ENABLE or @ref OB_IRH_DISABLE (*)
* @arg @ref OB_IWDG_SW or @ref OB_IWDG_HW
* @arg @ref OB_IWDG_STOP_FREEZE or @ref OB_IWDG_STOP_RUN
* @arg @ref OB_IWDG_STDBY_FREEZE or @ref OB_IWDG_STDBY_RUN
@@ -616,6 +617,7 @@
* @arg @ref OB_SRAM2_RST_ERASE or @ref OB_SRAM2_RST_NOT_ERASE
* @arg @ref OB_BOOT0_FROM_OB or @ref OB_BOOT0_FROM_PIN
* @arg @ref OB_BOOT0_RESET or @ref OB_BOOT0_SET
+ * @arg @ref OB_RESET_MODE_INPUT_ONLY or @ref OB_RESET_MODE_GPIO or @ref OB_RESET_MODE_INPUT_OUTPUT (*)
* @arg @ref OB_AGC_TRIM_0 or @ref OB_AGC_TRIM_1 or ... or @ref OB_AGC_TRIM_7
* @param RDPLevel: specifies the read protection level.
* This parameter can be one of the following values:
@@ -768,21 +770,35 @@
MODIFY_REG(sfr_reg_val, FLASH_SFR_SFSA, (((pOBParam->SecureFlashStartAddr - FLASH_BASE) / FLASH_PAGE_SIZE) << FLASH_SFR_SFSA_Pos));
/* Configure SRRVR register */
+#if defined(FLASH_SRRVR_SBRSA_A)
+ MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRSA_A | FLASH_SRRVR_SBRSA_B), \
+ (((((pOBParam->SecureRAM2aStartAddr - SRAM2A_BASE) >> SRAM_SECURE_PAGE_GRANULARITY_OFFSET) << FLASH_SRRVR_SBRSA_A_Pos)) | \
+ ((((pOBParam->SecureRAM2bStartAddr - SRAM2B_BASE) >> SRAM_SECURE_PAGE_GRANULARITY_OFFSET) << FLASH_SRRVR_SBRSA_B_Pos))));
+#else
MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRSA | FLASH_SRRVR_SNBRSA), \
(((((pOBParam->SecureRAM2aStartAddr - SRAM2A_BASE) >> SRAM_SECURE_PAGE_GRANULARITY_OFFSET) << FLASH_SRRVR_SBRSA_Pos)) | \
((((pOBParam->SecureRAM2bStartAddr - SRAM2B_BASE) >> SRAM_SECURE_PAGE_GRANULARITY_OFFSET) << FLASH_SRRVR_SNBRSA_Pos))));
+#endif
/* If Full System Secure mode is requested, clear all the corresponding bit */
/* Else set the corresponding bit */
if (pOBParam->SecureMode == SYSTEM_IN_SECURE_MODE)
{
CLEAR_BIT(sfr_reg_val, FLASH_SFR_FSD);
+#if defined(FLASH_SRRVR_BRSD_A)
+ CLEAR_BIT(srrvr_reg_val, (FLASH_SRRVR_BRSD_A | FLASH_SRRVR_BRSD_B));
+#else
CLEAR_BIT(srrvr_reg_val, (FLASH_SRRVR_BRSD | FLASH_SRRVR_NBRSD));
+#endif
}
else
{
SET_BIT(sfr_reg_val, FLASH_SFR_FSD);
+#if defined(FLASH_SRRVR_BRSD_A)
+ SET_BIT(srrvr_reg_val, (FLASH_SRRVR_BRSD_A | FLASH_SRRVR_BRSD_B));
+#else
SET_BIT(srrvr_reg_val, (FLASH_SRRVR_BRSD | FLASH_SRRVR_NBRSD));
+#endif
}
/* Update Flash registers */
@@ -870,6 +886,7 @@
* @arg @ref OB_STOP_RST or @ref OB_STOP_RST
* @arg @ref OB_STANDBY_RST or @ref OB_STANDBY_NORST
* @arg @ref OB_SHUTDOWN_RST or @ref OB_SHUTDOWN_NORST
+ * @arg @ref OB_IRH_ENABLE or @ref OB_IRH_DISABLE (*)
* @arg @ref OB_IWDG_SW or @ref OB_IWDG_HW
* @arg @ref OB_IWDG_STOP_FREEZE or @ref OB_IWDG_STOP_RUN
* @arg @ref OB_IWDG_STDBY_FREEZE or @ref OB_IWDG_STDBY_RUN
@@ -879,6 +896,7 @@
* @arg @ref OB_SRAM2_RST_ERASE or @ref OB_SRAM2_RST_NOT_ERASE
* @arg @ref OB_BOOT0_FROM_OB or @ref OB_BOOT0_FROM_PIN
* @arg @ref OB_BOOT0_RESET or @ref OB_BOOT0_SET
+ * @arg @ref OB_RESET_MODE_INPUT_ONLY or @ref OB_RESET_MODE_GPIO or @ref OB_RESET_MODE_INPUT_OUTPUT (*)
* @arg @ref OB_AGC_TRIM_0 or @ref OB_AGC_TRIM_1 or ... or @ref OB_AGC_TRIM_7
*/
static uint32_t FLASH_OB_GetUser(void)
@@ -952,12 +970,20 @@
*SecureFlashStartAddr = ((user_config * FLASH_PAGE_SIZE) + FLASH_BASE);
/* Get Secure SRAM2a start address */
+#if defined(FLASH_SRRVR_SBRSA_A)
+ user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SBRSA_A) >> FLASH_SRRVR_SBRSA_A_Pos);
+#else
user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SBRSA) >> FLASH_SRRVR_SBRSA_Pos);
+#endif
*SecureRAM2aStartAddr = ((user_config << SRAM_SECURE_PAGE_GRANULARITY_OFFSET) + SRAM2A_BASE);
/* Get Secure SRAM2b start address */
+#if defined(FLASH_SRRVR_SBRSA_B)
+ user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SBRSA_B) >> FLASH_SRRVR_SBRSA_B_Pos);
+#else
user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SNBRSA) >> FLASH_SRRVR_SNBRSA_Pos);
+#endif
*SecureRAM2bStartAddr = ((user_config << SRAM_SECURE_PAGE_GRANULARITY_OFFSET) + SRAM2B_BASE);
diff --git a/Src/stm32wbxx_hal_i2c.c b/Src/stm32wbxx_hal_i2c.c
index 9f0e2ce..6e9af79 100644
--- a/Src/stm32wbxx_hal_i2c.c
+++ b/Src/stm32wbxx_hal_i2c.c
@@ -93,7 +93,7 @@
[..]
(+) A specific option field manage the different steps of a sequential transfer
(+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
- (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
+ (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode
(++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
and data to transfer without a final stop condition
(++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
@@ -112,7 +112,7 @@
or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
- Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
+ Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit
without stopping the communication and so generate a restart condition.
(++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
interface.
@@ -122,7 +122,7 @@
or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
- (+) Differents sequential I2C interfaces are listed below:
+ (+) Different sequential I2C interfaces are listed below:
(++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()
or using @ref HAL_I2C_Master_Seq_Transmit_DMA()
(+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
@@ -4835,7 +4835,7 @@
{
/* Write data to TXDR only if XferCount not reach "0" */
/* A TXIS flag can be set, during STOP treatment */
- /* Check if all Datas have already been sent */
+ /* Check if all data have already been sent */
/* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
if (hi2c->XferCount > 0U)
{
@@ -5719,7 +5719,7 @@
}
else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
{
- /* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */
+ /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
I2C_ITSlaveSeqCplt(hi2c);
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
@@ -5856,7 +5856,7 @@
/* Disable all interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
- /* If state is an abort treatment on goind, don't change state */
+ /* If state is an abort treatment on going, don't change state */
/* This change will be do later */
if (hi2c->State != HAL_I2C_STATE_ABORT)
{
@@ -6570,7 +6570,7 @@
}
/**
- * @brief Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.
+ * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
* @param hi2c I2C handle.
* @retval None
*/
diff --git a/Src/stm32wbxx_hal_iwdg.c b/Src/stm32wbxx_hal_iwdg.c
index a522899..3174654 100644
--- a/Src/stm32wbxx_hal_iwdg.c
+++ b/Src/stm32wbxx_hal_iwdg.c
@@ -47,7 +47,7 @@
[..] Default timeout value (necessary for IWDG_SR status register update):
Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
- This frequency being subject to variations as mentioned above, the
+ This frequency being subject to variations as mentioned above, the
default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
below) may become too short or too long.
In such cases, this default timeout value can be tuned by redefining
diff --git a/Src/stm32wbxx_hal_pwr.c b/Src/stm32wbxx_hal_pwr.c
index af8a039..d910205 100644
--- a/Src/stm32wbxx_hal_pwr.c
+++ b/Src/stm32wbxx_hal_pwr.c
@@ -127,11 +127,13 @@
/* Clear all flags */
LL_PWR_WriteReg(SCR,
- LL_PWR_SCR_CC2HF
- | LL_PWR_SCR_C802AF
+ LL_PWR_SCR_CC2HF
| LL_PWR_SCR_CBLEAF
| LL_PWR_SCR_CCRPEF
+#if defined(PWR_CR3_E802A)
+ | LL_PWR_SCR_C802AF
| LL_PWR_SCR_C802WUF
+#endif
| LL_PWR_SCR_CBLEWUF
#if defined(PWR_CR5_SMPSEN)
| LL_PWR_SCR_CBORHF
@@ -222,8 +224,9 @@
(+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
(+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.
- (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on.
- (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
+ (+) Standby mode with SRAM2a: all clocks are stopped except LSI and LSE, SRAM2a content preserved, main regulator off, low power regulator on.
+ Note: On devices STM32WB15xx, STM32WB10xx, retention is extended to SRAM1, SRAM2a, SRAM2b.
+ (+) Standby mode without SRAM2a: all clocks are stopped except LSI and LSE, main and low power regulators off.
(+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
@@ -266,6 +269,7 @@
The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:
(++) HAL_PWREx_EnterSTOP0Mode() for mode 0, HAL_PWREx_EnterSTOP1Mode() for mode 1, HAL_PWREx_EnterSTOP2Mode() for mode 2
or for porting reasons HAL_PWR_EnterSTOPMode().
+ Note: Low power Stop2 mode is not available on devices STM32WB15xx, STM32WB10xx.
(+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
(++) PWR_MAINREGULATOR_ON: Regulator in main mode (STOP0 mode)
diff --git a/Src/stm32wbxx_hal_pwr_ex.c b/Src/stm32wbxx_hal_pwr_ex.c
index 3b394c6..37ede3e 100644
--- a/Src/stm32wbxx_hal_pwr_ex.c
+++ b/Src/stm32wbxx_hal_pwr_ex.c
@@ -281,7 +281,7 @@
CLEAR_BIT(PWR->CR3, PWR_CR3_EBLEA);
}
-
+#if defined(PWR_CR3_E802A)
/**
* @brief Enable 802.15.4 Activity interrupt.
* @retval None
@@ -299,6 +299,7 @@
{
CLEAR_BIT(PWR->CR3, PWR_CR3_E802A);
}
+#endif
/**
* @brief Enable CPU2 on-Hold interrupt.
@@ -640,9 +641,11 @@
/****************************************************************************/
/**
- * @brief Enable BKRAM content retention in Standby mode.
- * @note When RRS bit is set, SRAM is powered by the low-power regulator in
+ * @brief Enable SRAM2a content retention in Standby mode.
+ * @note When RRS bit is set, SRAM2a is powered by the low-power regulator in
* Standby mode and its content is kept.
+ * @note On devices STM32WB15xx, STM32WB10xx, retention is extended
+ * to SRAM1, SRAM2a and SRAM2b.
* @retval None
*/
void HAL_PWREx_EnableSRAMRetention(void)
@@ -651,9 +654,11 @@
}
/**
- * @brief Disable BKRAM content retention in Standby mode.
- * @note When RRS bit is reset, SRAM is powered off in Standby mode
+ * @brief Disable SRAM2a content retention in Standby mode.
+ * @note When RRS bit is reset, SRAM2a is powered off in Standby mode
* and its content is lost.
+ * @note On devices STM32WB15xx, STM32WB10xx, retention is extended
+ * to SRAM1, SRAM2a and SRAM2b.
* @retval None
*/
void HAL_PWREx_DisableSRAMRetention(void)
@@ -678,7 +683,7 @@
if((PowerMode & PWR_FLASHPD_LPRUN) != 0U)
{
/* Unlock bit FPDR */
- WRITE_REG(PWR->CR1, 0x0000C1B0U);
+ WRITE_REG(PWR->CR1, 0x0000C1B0UL);
}
/* Set flash power down mode */
@@ -910,7 +915,7 @@
*
* (1) SMPS operating mode step down or open depends on system low-power mode:
* - step down mode if system low power mode is run, LP run or stop,
- * - open mode if system low power mode is stop1, stop2, standby or shutdown
+ * - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown
* @retval None
*/
void HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode)
@@ -924,7 +929,7 @@
* requested operating mode can differ from effective low power mode.
* - dependency on system low-power mode:
* - step down mode if system low power mode is run, LP run or stop,
- * - open mode if system low power mode is stop1, stop2, standby or shutdown
+ * - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown
* - dependency on BOR level:
* - bypass mode if supply voltage drops below BOR level
* @note This functions check flags of SMPS operating modes step down
@@ -936,7 +941,7 @@
*
* (1) SMPS operating mode step down or open depends on system low-power mode:
* - step down mode if system low power mode is run, LP run or stop,
- * - open mode if system low power mode is stop1, stop2, standby or shutdown
+ * - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown
*/
uint32_t HAL_PWREx_SMPS_GetEffectiveMode(void)
{
@@ -1129,7 +1134,6 @@
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
-
/**
* @brief Enter Stop 1 mode.
* @note In Stop 1 mode, only low power voltage regulator is ON.
@@ -1182,7 +1186,7 @@
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
-
+#if defined(PWR_SUPPORT_STOP2)
/**
* @brief Enter Stop 2 mode.
* @note In Stop 2 mode, only low power voltage regulator is ON.
@@ -1244,10 +1248,7 @@
/* Reset SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
-
-
-
-
+#endif
/**
* @brief Enter Shutdown mode.
diff --git a/Src/stm32wbxx_hal_rcc.c b/Src/stm32wbxx_hal_rcc.c
index 2d153f3..d591a17 100644
--- a/Src/stm32wbxx_hal_rcc.c
+++ b/Src/stm32wbxx_hal_rcc.c
@@ -320,11 +320,6 @@
CLEAR_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSIASFS | RCC_CR_HSEON | RCC_CR_HSEPRE | RCC_CR_PLLON);
#endif
-#if defined(RCC_CR_HSEBYP)
- /* Reset HSEBYP bit once HSE is OFF */
- LL_RCC_HSE_DisableBypass();
-#endif
-
/* Get Start Tick*/
tickstart = HAL_GetTick();
@@ -454,7 +449,8 @@
}
/* Update the SystemCoreClock global variable */
- SystemCoreClockUpdate();
+ SystemCoreClock = HAL_RCC_GetHCLKFreq();
+
if (HAL_InitTick(uwTickPrio) != HAL_OK)
{
return HAL_ERROR;
@@ -822,6 +818,7 @@
}
}
+#if defined(RCC_HSI48_SUPPORT)
/*------------------------------ HSI48 Configuration -----------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
{
@@ -864,6 +861,7 @@
}
}
}
+#endif
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
@@ -1261,7 +1259,8 @@
/*---------------------------------------------------------------------------*/
/* Update the SystemCoreClock global variable */
- SystemCoreClockUpdate();
+ SystemCoreClock = HAL_RCC_GetHCLKFreq();
+
/* Configure the source of time base considering new system clocks settings*/
return HAL_InitTick(HAL_GetTickPrio());
}
@@ -1530,25 +1529,17 @@
/* Set all possible values for the Oscillator type parameter ---------------*/
RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \
- RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI1 | RCC_OSCILLATORTYPE_LSI2 | RCC_OSCILLATORTYPE_HSI48;
+ RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI1 | RCC_OSCILLATORTYPE_LSI2;
+#if defined(RCC_HSI48_SUPPORT)
+ RCC_OscInitStruct->OscillatorType |= RCC_OSCILLATORTYPE_HSI48;
+#endif
/* Get the HSE configuration -----------------------------------------------*/
-#if defined(RCC_CR_HSEBYP)
- if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
- {
- RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
- }
- else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
- {
- RCC_OscInitStruct->HSEState = RCC_HSE_ON;
- }
-#else
if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
{
RCC_OscInitStruct->HSEState = RCC_HSE_ON;
}
-#endif
else
{
RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
@@ -1604,6 +1595,7 @@
RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
}
+#if defined(RCC_HSI48_SUPPORT)
/* Get the HSI48 configuration ---------------------------------------------*/
if ((RCC->CRRCR & RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON)
{
@@ -1613,7 +1605,7 @@
{
RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
}
-
+#endif
/* Get the PLL configuration -----------------------------------------------*/
if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
diff --git a/Src/stm32wbxx_hal_rcc_ex.c b/Src/stm32wbxx_hal_rcc_ex.c
index 8554028..bf0fa9e 100644
--- a/Src/stm32wbxx_hal_rcc_ex.c
+++ b/Src/stm32wbxx_hal_rcc_ex.c
@@ -139,7 +139,6 @@
* @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
* @arg @ref RCC_PERIPHCLK_RFWAKEUP RFWKP peripheral clock
* @arg @ref RCC_PERIPHCLK_SMPS SMPS peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
*
*
* @note Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to select
@@ -429,23 +428,6 @@
}
#endif
-#if defined(SPI_I2S_SUPPORT)
- /*-------------------- I2S clock source configuration ----------------------*/
- if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
-
- /* Configure the I2S clock source */
- __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
-
- if (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL)
- {
- /* Enable RCC_PLL_I2SCLK output */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_I2SCLK);
- }
- }
-#endif
return status;
}
@@ -456,7 +438,7 @@
* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
* returns the configuration information for the Extended Peripherals
* clocks(SAI1, LPTIM1, LPTIM2, I2C1, I2C3, LPUART1,
- * USART1, RTC, ADCx, USB, RNG, RFWKP, SMPS, I2S).
+ * USART1, RTC, ADCx, USB, RNG, RFWKP, SMPS).
* @retval None
*/
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
@@ -487,9 +469,6 @@
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SMPS;
#endif
-#if defined(SPI_I2S_SUPPORT)
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S;
-#endif
#if defined(SAI1)
/* Get the PLLSAI1 Clock configuration -----------------------------------------------*/
@@ -551,10 +530,6 @@
PeriphClkInit->SmpsClockSelection = __HAL_RCC_GET_SMPS_SOURCE();
#endif
-#if defined(SPI_I2S_SUPPORT)
- /* Get the I2S clock source -----------------------------------------------*/
- PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2S_SOURCE();
-#endif
}
/**
@@ -575,7 +550,6 @@
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
* @arg @ref RCC_PERIPHCLK_RFWAKEUP RFWKP peripheral clock
* @arg @ref RCC_PERIPHCLK_SMPS SMPS peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
* @retval Frequency in Hz
*/
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
@@ -724,6 +698,7 @@
}
else /* HSI48 clock divided by 3 used as RNG clock source */
{
+#if defined(RCC_HSI48_SUPPORT)
if (LL_RCC_HSI48_IsReady() == 1U)
{
frequency = HSI48_VALUE / 3U;
@@ -732,6 +707,9 @@
{
/* Nothing to do as frequency already initialized to 0U */
}
+#else
+ /* Nothing to do as frequency already initialized to 0U */
+#endif
}
}
#if defined(USB)
@@ -1050,19 +1028,6 @@
/* Nothing to do as frequency already initialized to 0U */
}
}
- else if (rfwkpClockSource == LL_RCC_RFWKP_CLKSOURCE_LSI) /* LSI clock used as RF Wakeup clock source */
- {
- const uint32_t temp_lsi1ready = LL_RCC_LSI1_IsReady();
- const uint32_t temp_lsi2ready = LL_RCC_LSI2_IsReady();
- if ((temp_lsi1ready == 1U) || (temp_lsi2ready == 1U))
- {
- frequency = LSI_VALUE;
- }
- else
- {
- /* Nothing to do as frequency already initialized to 0U */
- }
- }
else if (rfwkpClockSource == LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024) /* HSE clock used as RF Wakeup clock source */
{
frequency = HSE_VALUE / 1024U;
@@ -1128,32 +1093,6 @@
}
}
#endif
-#if defined(SPI_I2S_SUPPORT)
- if (PeriphClk == RCC_PERIPHCLK_I2S)
- {
- switch (LL_RCC_GetI2SClockSource(LL_RCC_I2S_CLKSOURCE))
- {
- case LL_RCC_I2S_CLKSOURCE_PIN: /* I2S Clock is External clock */
- frequency = EXTERNAL_CLOCK_VALUE;
- break;
-
- case LL_RCC_I2S_CLKSOURCE_HSI: /* I2S Clock is HSI Osc. */
- if (LL_RCC_HSI_IsReady() == 1U)
- {
- frequency = HSI_VALUE;
- }
- break;
-
- case LL_RCC_I2S_CLKSOURCE_PLL: /* I2S Clock is PLL */
- frequency = RCC_PLL_GetFreqDomain_P();
- break;
-
- case LL_RCC_I2S_CLKSOURCE_NONE: /* No clock used as I2S clock source */
- default:
- break;
- }
- }
-#endif
return (frequency);
}
diff --git a/Src/stm32wbxx_hal_smbus.c b/Src/stm32wbxx_hal_smbus.c
index c5a24db..9d336dd 100644
--- a/Src/stm32wbxx_hal_smbus.c
+++ b/Src/stm32wbxx_hal_smbus.c
@@ -1854,7 +1854,7 @@
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
- /* REenable the selected SMBUS peripheral */
+ /* Re-enable the selected SMBUS peripheral */
__HAL_SMBUS_ENABLE(hsmbus);
/* Call the corresponding callback to inform upper layer of End of Transfer */
@@ -2616,7 +2616,7 @@
}
/**
- * @brief Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
+ * @brief Convert SMBUSx OTHER_xxx XferOptions to functional XferOptions.
* @param hsmbus SMBUS handle.
* @retval None
*/
diff --git a/Src/stm32wbxx_hal_tim.c b/Src/stm32wbxx_hal_tim.c
index 5a07b9e..29a2fb8 100644
--- a/Src/stm32wbxx_hal_tim.c
+++ b/Src/stm32wbxx_hal_tim.c
@@ -512,7 +512,7 @@
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
-
+
/* Disable the TIM Update interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
@@ -571,6 +571,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -1087,6 +1088,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -1107,6 +1109,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -1127,6 +1130,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 3 DMA request */
@@ -1146,6 +1150,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 4 DMA request */
@@ -1723,6 +1728,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -1743,6 +1749,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 2 DMA request */
@@ -1762,6 +1769,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Capture/Compare 3 request */
@@ -1781,6 +1789,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 4 DMA request */
@@ -2076,7 +2085,7 @@
/* Check the TIM channel state */
if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -2158,7 +2167,7 @@
/* Check the TIM channel state */
if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -2310,12 +2319,12 @@
/* Set the TIM channel state */
if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
+ && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((pData == NULL) && (Length > 0U))
{
@@ -2346,6 +2355,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 1 DMA request */
@@ -2365,6 +2375,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 2 DMA request */
@@ -2384,6 +2395,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 3 DMA request */
@@ -2403,6 +2415,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 4 DMA request */
@@ -2452,6 +2465,9 @@
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -2490,9 +2506,6 @@
break;
}
- /* Disable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
@@ -2704,9 +2717,9 @@
/* Check the TIM channels state */
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -2802,9 +2815,9 @@
/* Check the TIM channels state */
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3139,7 +3152,7 @@
if (Channel == TIM_CHANNEL_1)
{
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3152,7 +3165,7 @@
else if (Channel == TIM_CHANNEL_2)
{
if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3165,9 +3178,9 @@
else
{
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3257,7 +3270,7 @@
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
}
- else
+ else
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
@@ -3293,7 +3306,7 @@
if (Channel == TIM_CHANNEL_1)
{
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3306,7 +3319,7 @@
else if (Channel == TIM_CHANNEL_2)
{
if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3319,9 +3332,9 @@
else
{
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3419,7 +3432,7 @@
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
}
- else
+ else
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
@@ -3459,12 +3472,12 @@
if (Channel == TIM_CHANNEL_1)
{
if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((pData1 == NULL) && (Length > 0U))
{
@@ -3484,12 +3497,12 @@
else if (Channel == TIM_CHANNEL_2)
{
if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+ && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((pData2 == NULL) && (Length > 0U))
{
@@ -3509,16 +3522,16 @@
else
{
if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
- && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+ && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
{
@@ -3552,6 +3565,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Input Capture DMA request */
@@ -3576,6 +3590,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Input Capture DMA request */
@@ -3601,6 +3616,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -3614,6 +3630,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the Peripheral */
@@ -3692,7 +3709,7 @@
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
}
- else
+ else
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
@@ -4419,8 +4436,8 @@
* @arg TIM_DMABASE_CCMR3
* @arg TIM_DMABASE_CCR5
* @arg TIM_DMABASE_CCR6
- * @arg TIM_DMABASE_AF1
- * @arg TIM_DMABASE_AF2
+ * @arg TIM_DMABASE_AF1
+ * @arg TIM_DMABASE_AF2
* @param BurstRequestSrc TIM DMA Request sources
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
@@ -4436,14 +4453,68 @@
* @note This function should be used only when BurstLength is equal to DMA data transfer length.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
- uint32_t *BurstBuffer, uint32_t BurstLength)
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
+{
+ return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+ ((BurstLength) >> 8U) + 1U);
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_OR
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_AF1
+ * @arg TIM_DMABASE_AF2
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @param DataLength Data length. This parameter can be one value
+ * between 1 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+ uint32_t BurstLength, uint32_t DataLength)
{
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+ assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
{
@@ -4476,8 +4547,10 @@
htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4493,8 +4566,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4510,8 +4584,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4527,8 +4602,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4544,8 +4620,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4561,8 +4638,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4578,8 +4656,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4587,9 +4666,9 @@
default:
break;
}
- /* configure the DMA Burst Mode */
- htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+ /* Configure the DMA Burst Mode */
+ htim->Instance->DCR = (BurstBaseAddress | BurstLength);
/* Enable the TIM DMA Request */
__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
@@ -4605,7 +4684,6 @@
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
{
- HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
@@ -4614,54 +4692,51 @@
{
case TIM_DMA_UPDATE:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
break;
}
case TIM_DMA_CC1:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
break;
}
case TIM_DMA_CC2:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
break;
}
case TIM_DMA_CC3:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
break;
}
case TIM_DMA_CC4:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
break;
}
case TIM_DMA_COM:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
break;
}
case TIM_DMA_TRIGGER:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
break;
}
default:
break;
}
- if (HAL_OK == status)
- {
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
- }
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
/* Change the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
/* Return function status */
- return status;
+ return HAL_OK;
}
/**
@@ -4691,8 +4766,8 @@
* @arg TIM_DMABASE_CCMR3
* @arg TIM_DMABASE_CCR5
* @arg TIM_DMABASE_CCR6
- * @arg TIM_DMABASE_AF1
- * @arg TIM_DMABASE_AF2
+ * @arg TIM_DMABASE_AF1
+ * @arg TIM_DMABASE_AF2
* @param BurstRequestSrc TIM DMA Request sources
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
@@ -4711,11 +4786,65 @@
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
{
+ return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+ ((BurstLength) >> 8U) + 1U);
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_OR
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_AF1
+ * @arg TIM_DMABASE_AF2
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @param DataLength Data length. This parameter can be one value
+ * between 1 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+ uint32_t BurstLength, uint32_t DataLength)
+{
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+ assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
{
@@ -4748,8 +4877,10 @@
htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4764,15 +4895,17 @@
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
}
case TIM_DMA_CC2:
{
- /* Set the DMA capture/compare callbacks */
+ /* Set the DMA capture callbacks */
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
@@ -4780,8 +4913,10 @@
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4796,8 +4931,10 @@
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4812,8 +4949,10 @@
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4828,8 +4967,10 @@
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4844,8 +4985,10 @@
htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4854,14 +4997,12 @@
break;
}
- /* configure the DMA Burst Mode */
+ /* Configure the DMA Burst Mode */
htim->Instance->DCR = (BurstBaseAddress | BurstLength);
/* Enable the TIM DMA Request */
__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
- htim->State = HAL_TIM_STATE_READY;
-
/* Return function status */
return HAL_OK;
}
@@ -4874,7 +5015,6 @@
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
{
- HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
@@ -4883,54 +5023,51 @@
{
case TIM_DMA_UPDATE:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
break;
}
case TIM_DMA_CC1:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
break;
}
case TIM_DMA_CC2:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
break;
}
case TIM_DMA_CC3:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
break;
}
case TIM_DMA_CC4:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
break;
}
case TIM_DMA_COM:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
break;
}
case TIM_DMA_TRIGGER:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
break;
}
default:
break;
}
- if (HAL_OK == status)
- {
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
- }
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
/* Change the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
/* Return function status */
- return status;
+ return HAL_OK;
}
/**
@@ -5286,13 +5423,13 @@
case TIM_CLOCKSOURCE_ITR1:
case TIM_CLOCKSOURCE_ITR2:
case TIM_CLOCKSOURCE_ITR3:
- {
- /* Check whether or not the timer instance supports internal trigger input */
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+ {
+ /* Check whether or not the timer instance supports internal trigger input */
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
- TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
- break;
- }
+ TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+ break;
+ }
default:
break;
@@ -6258,12 +6395,12 @@
HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel)
{
HAL_TIM_ChannelStateTypeDef channel_state;
-
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
-
+
return channel_state;
}
@@ -6276,7 +6413,7 @@
{
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
-
+
return htim->DMABurstState;
}
@@ -6340,14 +6477,14 @@
* @param hdma pointer to DMA handle.
* @retval None
*/
-void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
@@ -6356,7 +6493,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
@@ -6365,7 +6502,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
@@ -6374,7 +6511,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
@@ -6445,7 +6582,7 @@
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
@@ -6455,7 +6592,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
@@ -6465,7 +6602,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
@@ -6475,7 +6612,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
@@ -6660,7 +6797,7 @@
/**
* @brief Timer Output Compare 1 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -6735,7 +6872,7 @@
/**
* @brief Timer Output Compare 2 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -6811,7 +6948,7 @@
/**
* @brief Timer Output Compare 3 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -6885,7 +7022,7 @@
/**
* @brief Timer Output Compare 4 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -6945,7 +7082,7 @@
/**
* @brief Timer Output Compare 5 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
@@ -6998,7 +7135,7 @@
/**
* @brief Timer Output Compare 6 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
@@ -7102,7 +7239,7 @@
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
- if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
+ if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
{
return HAL_ERROR;
}
@@ -7154,11 +7291,11 @@
case TIM_TS_ITR1:
case TIM_TS_ITR2:
case TIM_TS_ITR3:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- break;
- }
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ break;
+ }
default:
break;
diff --git a/Src/stm32wbxx_hal_tim_ex.c b/Src/stm32wbxx_hal_tim_ex.c
index 0ce23de..1343a82 100644
--- a/Src/stm32wbxx_hal_tim_ex.c
+++ b/Src/stm32wbxx_hal_tim_ex.c
@@ -352,9 +352,9 @@
/* Check the TIM channels state */
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -364,7 +364,7 @@
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
+
/* Enable the Input Capture channel 1
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
@@ -432,9 +432,9 @@
/* Check the TIM channels state */
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -518,12 +518,12 @@
/* Set the TIM channel state */
if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
- ||(complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((pData == NULL) && (Length > 0U))
{
@@ -553,6 +553,7 @@
/* Enable the DMA channel for Capture 1*/
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the capture compare 1 Interrupt */
@@ -654,7 +655,7 @@
{
return HAL_ERROR;
}
-
+
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
@@ -918,6 +919,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Compare DMA request */
@@ -937,6 +939,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Compare DMA request */
@@ -956,6 +959,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Compare DMA request */
@@ -1372,6 +1376,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 1 DMA request */
@@ -1391,6 +1396,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 2 DMA request */
@@ -1410,6 +1416,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 3 DMA request */
@@ -1550,7 +1557,7 @@
/* Check the TIM channels state */
if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)
- || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -1626,7 +1633,7 @@
/* Check the TIM channels state */
if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)
- || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -2538,12 +2545,12 @@
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN)
{
HAL_TIM_ChannelStateTypeDef channel_state;
-
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
-
+
return channel_state;
}
/**
@@ -2610,7 +2617,7 @@
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
@@ -2619,7 +2626,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
@@ -2628,7 +2635,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
@@ -2637,7 +2644,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
@@ -2662,7 +2669,7 @@
* @param hdma pointer to DMA handle.
* @retval None
*/
-void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
+static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
@@ -2685,13 +2692,13 @@
{
/* nothing to do */
}
-
+
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->ErrorCallback(htim);
#else
HAL_TIM_ErrorCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
+
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
diff --git a/Src/stm32wbxx_hal_usart.c b/Src/stm32wbxx_hal_usart.c
index e6c7363..9b0ded6 100644
--- a/Src/stm32wbxx_hal_usart.c
+++ b/Src/stm32wbxx_hal_usart.c
@@ -49,7 +49,7 @@
by calling the customized HAL_USART_MspInit(&husart) API.
[..]
- (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
+ (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to USART API's
HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.
@@ -529,9 +529,9 @@
}
/**
- * @brief Unregister an UART Callback
- * UART callaback is redirected to the weak predefined callback
- * @param husart uart handle
+ * @brief Unregister an USART Callback
+ * USART callaback is redirected to the weak predefined callback
+ * @param husart usart handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
@@ -732,7 +732,7 @@
/**
* @brief Simplex send an amount of data in blocking mode.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pTxData.
* @param husart USART handle.
@@ -830,7 +830,7 @@
/**
* @brief Receive an amount of data in blocking mode.
* @note To receive synchronous data, dummy data are simultaneously transmitted.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pRxData.
* @param husart USART handle.
@@ -942,7 +942,7 @@
/**
* @brief Full-Duplex Send and Receive an amount of data in blocking mode.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
* of u16 available through pTxData and through pRxData.
* @param husart USART handle.
@@ -1091,7 +1091,7 @@
/**
* @brief Send an amount of data in interrupt mode.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pTxData.
* @param husart USART handle.
@@ -1175,7 +1175,7 @@
/**
* @brief Receive an amount of data in interrupt mode.
* @note To receive synchronous data, dummy data are simultaneously transmitted.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pRxData.
* @param husart USART handle.
@@ -1279,7 +1279,7 @@
/**
* @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
* of u16 available through pTxData and through pRxData.
* @param husart USART handle.
@@ -1377,7 +1377,7 @@
/**
* @brief Send an amount of data in DMA mode.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pTxData.
* @param husart USART handle.
@@ -1463,7 +1463,7 @@
* @note When the USART parity is enabled (PCE = 1), the received data contain
* the parity bit (MSB position).
* @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pRxData.
* @param husart USART handle.
@@ -1580,7 +1580,7 @@
/**
* @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
* @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
* of u16 available through pTxData and through pRxData.
* @param husart USART handle.
diff --git a/Src/stm32wbxx_hal_usart_ex.c b/Src/stm32wbxx_hal_usart_ex.c
index 6218677..af2c15b 100644
--- a/Src/stm32wbxx_hal_usart_ex.c
+++ b/Src/stm32wbxx_hal_usart_ex.c
@@ -57,10 +57,10 @@
/** @defgroup USARTEx_Private_Constants USARTEx Private Constants
* @{
*/
-/* UART RX FIFO depth */
+/* USART RX FIFO depth */
#define RX_FIFO_DEPTH 8U
-/* UART TX FIFO depth */
+/* USART TX FIFO depth */
#define TX_FIFO_DEPTH 8U
/**
* @}
diff --git a/Src/stm32wbxx_hal_wwdg.c b/Src/stm32wbxx_hal_wwdg.c
index e70227c..0c0a470 100644
--- a/Src/stm32wbxx_hal_wwdg.c
+++ b/Src/stm32wbxx_hal_wwdg.c
@@ -21,6 +21,13 @@
before the counter has reached the refresh window value. This
implies that the counter must be refreshed in a limited window.
(+) Once enabled the WWDG cannot be disabled except by a system reset.
+ (+) If required by application, an Early Wakeup Interrupt can be triggered
+ in order to be warned before WWDG expiration. The Early Wakeup Interrupt
+ (EWI) can be used if specific safety operations or data logging must
+ be performed before the actual reset is generated. When the downcounter
+ reaches 0x40, interrupt occurs. This mechanism requires WWDG interrupt
+ line to be enabled in NVIC. Once enabled, EWI interrupt cannot be
+ disabled except by a system reset.
(+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG
reset occurs.
(+) The WWDG counter input clock is derived from the APB clock divided
@@ -34,7 +41,8 @@
(+) Typical values:
(++) Counter min (T[5;0] = 0x00) at 64 MHz (PCLK1) with zero prescaler:
max timeout before reset: approximately 64us
- (++) Counter max (T[5;0] = 0x3F) at 64 MHz (PCLK1) with prescaler dividing by 128:
+ (++) Counter max (T[5;0] = 0x3F) at 64 MHz (PCLK1) with prescaler
+ dividing by 128:
max timeout before reset: approximately 524.28ms
##### How to use this driver #####
@@ -45,16 +53,16 @@
[..]
(+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
- (+) Set the WWDG prescaler, refresh window and counter value
- using HAL_WWDG_Init() function.
- (+) Start the WWDG using HAL_WWDG_Start() function.
- When the WWDG is enabled the counter value should be configured to
- a value greater than 0x40 to prevent generating an immediate reset.
- (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is
- generated when the counter reaches 0x40, and then start the WWDG using
- HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can
- add his own code by customization of callback HAL_WWDG_WakeupCallback.
- Once enabled, EWI interrupt cannot be disabled except by a system reset.
+ (+) Configure the WWDG prescaler, refresh window value, counter value and early
+ interrupt status using HAL_WWDG_Init() function. This will automatically
+ enable WWDG and start its downcounter. Time reference can be taken from
+ function exit. Care must be taken to provide a counter value
+ greater than 0x40 to prevent generation of immediate reset.
+ (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is
+ generated when the counter reaches 0x40. When HAL_WWDG_IRQHandler is
+ triggered by the interrupt service routine, flag will be automatically
+ cleared and HAL_WWDG_WakeupCallback user callback will be executed. User
+ can add his own code by customization of callback HAL_WWDG_WakeupCallback.
(+) Then the application program must refresh the WWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
HAL_WWDG_Refresh() function. This operation must occur only when
@@ -64,7 +72,7 @@
=============================
[..]
- The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
+ The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
the user to configure dynamically the driver callbacks. Use Functions
HAL_WWDG_RegisterCallback() to register a user callback.
@@ -96,7 +104,7 @@
*** WWDG HAL driver macros list ***
===================================
[..]
- Below the list of most used macros in WWDG HAL driver.
+ Below the list of available macros in WWDG HAL driver.
(+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
(+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
(+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
@@ -197,7 +205,7 @@
#else
/* Init the low level hardware */
HAL_WWDG_MspInit(hwwdg);
-#endif
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/* Set WWDG Counter */
WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
@@ -242,7 +250,8 @@
* @param pCallback pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
+ pWWDG_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -303,7 +312,7 @@
return status;
}
-#endif
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/**
* @}
@@ -371,7 +380,7 @@
#else
/* Early Wakeup callback */
HAL_WWDG_EarlyWakeupCallback(hwwdg);
-#endif
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
}
}
}
diff --git a/Src/stm32wbxx_ll_adc.c b/Src/stm32wbxx_ll_adc.c
index 2aa46ee..a543fcd 100644
--- a/Src/stm32wbxx_ll_adc.c
+++ b/Src/stm32wbxx_ll_adc.c
@@ -67,6 +67,12 @@
#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Note: CCRDY handshake requires 1APB + 2 ADC + 3 APB cycles */
+/* after the channel configuration has been changed. */
+/* Driver timeout is approximated to 6 CPU cycles. */
+#define ADC_TIMEOUT_CCRDY_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 6UL)
+#endif
/**
* @}
@@ -80,6 +86,22 @@
/* Check of parameters for configuration of ADC hierarchical scope: */
/* common to several ADC instances. */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
+ ( ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
+ )
+#else
#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
|| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
@@ -97,9 +119,19 @@
|| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
|| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
)
+#endif
/* Check of parameters for configuration of ADC hierarchical scope: */
/* ADC instance. */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define IS_LL_ADC_CLOCK(__CLOCK__) \
+ ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC) \
+ )
+
+#endif
#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
|| ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
@@ -112,13 +144,32 @@
|| ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
)
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
+ ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
+ || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
+ || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF) \
+ || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF) \
+ )
+#else
#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
|| ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
)
-
+#endif
/* Check of parameters for configuration of ADC hierarchical scope: */
/* ADC group regular */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
+ ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 ) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
+ )
+#else
#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
@@ -130,6 +181,7 @@
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
)
+#endif
#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
@@ -147,6 +199,25 @@
|| ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
)
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define IS_LL_ADC_REG_SEQ_MODE(__REG_SEQ_MODE__) \
+ ( ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_FIXED) \
+ || ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_CONFIGURABLE) \
+ )
+#endif
+
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
+ ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
+ )
+#else
#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
@@ -165,7 +236,13 @@
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
)
-
+#endif
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
+ ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
+ )
+#else
#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
@@ -177,7 +254,7 @@
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
)
-
+#endif
/* Check of parameters for configuration of ADC hierarchical scope: */
/* ADC group injected */
#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
@@ -245,11 +322,19 @@
/* Check the parameters */
assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Force reset of ADC clock (core clock) */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);
+
+ /* Release reset of ADC clock (core clock) */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC);
+#else
/* Force reset of ADC clock (core clock) */
LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC);
/* Release reset of ADC clock (core clock) */
LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC);
+#endif /* ADC_SUPPORT_2_5_MSPS */
return SUCCESS;
}
@@ -342,7 +427,11 @@
/* Set ADC_CommonInitStruct fields to default values */
/* Set fields of ADC common */
/* (all ADC instances belonging to the same ADC common instance) */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2;
+#else
ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
+#endif /* ADC_SUPPORT_2_5_MSPS */
}
@@ -387,6 +476,7 @@
}
}
+#if !defined (ADC_SUPPORT_2_5_MSPS)
/* Set ADC group injected trigger source to SW start to ensure to not */
/* have an external trigger event occurring during the conversion stop */
/* ADC disable process. */
@@ -414,12 +504,28 @@
break;
}
}
+#else
+ /* Wait for ADC conversions are effectively stopped */
+ timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
+ while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1UL)
+ {
+ timeout_cpu_cycles--;
+ if(timeout_cpu_cycles == 0UL)
+ {
+ /* Time-out error */
+ status = ERROR;
+ break;
+ }
+ }
+#endif /* ADC_SUPPORT_2_5_MSPS */
+#if !defined (ADC_SUPPORT_2_5_MSPS)
/* Flush group injected contexts queue (register JSQR): */
/* Note: Bit JQM must be set to empty the contexts queue (otherwise */
/* contexts queue is maintained with the last active context). */
LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
-
+
+#endif
/* Disable the ADC instance */
LL_ADC_Disable(ADCx);
@@ -438,11 +544,19 @@
}
/* Check whether ADC state is compliant with expected state */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ if (READ_BIT(ADCx->CR,
+ (ADC_CR_ADSTP | ADC_CR_ADSTART
+ | ADC_CR_ADDIS | ADC_CR_ADEN )
+ )
+ == 0UL)
+#else
if (READ_BIT(ADCx->CR,
(ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
| ADC_CR_ADDIS | ADC_CR_ADEN)
)
== 0UL)
+#endif
{
/* ========== Reset ADC registers ========== */
/* Reset register IER */
@@ -452,12 +566,17 @@
| LL_ADC_IT_EOS
| LL_ADC_IT_OVR
| LL_ADC_IT_EOSMP
+#if !defined (ADC_SUPPORT_2_5_MSPS)
| LL_ADC_IT_JEOC
| LL_ADC_IT_JEOS
| LL_ADC_IT_JQOVF
+#endif
| LL_ADC_IT_AWD1
| LL_ADC_IT_AWD2
| LL_ADC_IT_AWD3
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ | LL_ADC_IT_CCRDY
+#endif
)
);
@@ -468,15 +587,26 @@
| LL_ADC_FLAG_EOS
| LL_ADC_FLAG_OVR
| LL_ADC_FLAG_EOSMP
+#if !defined (ADC_SUPPORT_2_5_MSPS)
| LL_ADC_FLAG_JEOC
| LL_ADC_FLAG_JEOS
| LL_ADC_FLAG_JQOVF
+#endif
| LL_ADC_FLAG_AWD1
| LL_ADC_FLAG_AWD2
| LL_ADC_FLAG_AWD3
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ | LL_ADC_FLAG_CCRDY
+#endif
)
);
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Reset register CR */
+ /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
+ /* "read-set": no direct reset applicable. */
+ CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN);
+#else
/* Reset register CR */
/* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */
/* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */
@@ -489,7 +619,66 @@
/* already done above. */
CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
+#endif
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Reset register CFGR1 */
+ CLEAR_BIT(ADCx->CFGR1,
+ ( ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN
+ | ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD
+ | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES
+ | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN )
+ );
+
+ /* Reset register SMPR */
+ CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP1 | ADC_SMPR_SMP2 | ADC_SMPR_SMPSEL);
+
+ /* Reset register TR1 */
+ MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
+
+ /* Reset register CHSELR */
+ CLEAR_BIT(ADCx->CHSELR,
+ ( ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
+ | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
+ | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8
+ | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4
+ | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 )
+ );
+
+ /* Wait for ADC channel configuration ready */
+ timeout_cpu_cycles = ADC_TIMEOUT_CCRDY_CPU_CYCLES;
+ while (LL_ADC_IsActiveFlag_CCRDY(ADCx) == 0UL)
+ {
+ timeout_cpu_cycles--;
+ if(timeout_cpu_cycles == 0UL)
+ {
+ /* Time-out error */
+ status = ERROR;
+ break;
+ }
+ }
+
+ /* Clear flag ADC channel configuration ready */
+ LL_ADC_ClearFlag_CCRDY(ADCx);
+
+ /* Reset register DR */
+ /* bits in access mode read only, no direct reset applicable */
+
+ /* Reset register CALFACT */
+ CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT);
+
+ /* Reset register CFGR2 */
+ /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
+ /* already done above. */
+ /* Note: Register reset last due to selection of asynchronous clock, */
+ /* ADC clock then depends of configuration clock source at system */
+ /* level. */
+ CLEAR_BIT(ADCx->CFGR2,
+ ( ADC_CFGR2_CKMODE
+ | ADC_CFGR2_LFTRIG )
+ );
+
+#else
/* Reset register CFGR */
MODIFY_REG(ADCx->CFGR,
(ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN
@@ -506,6 +695,7 @@
(ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS
| ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
);
+
/* Reset register SMPR1 */
CLEAR_BIT(ADCx->SMPR1,
@@ -585,6 +775,7 @@
/* Reset register CALFACT */
CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
+#endif
}
else
{
@@ -640,6 +831,9 @@
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock));
+#endif
assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
@@ -653,6 +847,24 @@
/* - Set ADC data resolution */
/* - Set ADC conversion data alignment */
/* - Set ADC low power mode */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ MODIFY_REG(ADCx->CFGR1,
+ ADC_CFGR1_RES
+ | ADC_CFGR1_ALIGN
+ | ADC_CFGR1_WAIT
+ | ADC_CFGR1_AUTOFF
+ ,
+ ADC_InitStruct->Resolution
+ | ADC_InitStruct->DataAlignment
+ | ADC_InitStruct->LowPowerMode
+ );
+
+ MODIFY_REG(ADCx->CFGR2,
+ ADC_CFGR2_CKMODE
+ ,
+ ADC_InitStruct->Clock
+ );
+#else
MODIFY_REG(ADCx->CFGR,
ADC_CFGR_RES
| ADC_CFGR_ALIGN
@@ -662,7 +874,7 @@
| ADC_InitStruct->DataAlignment
| ADC_InitStruct->LowPowerMode
);
-
+#endif
}
else
{
@@ -682,6 +894,9 @@
{
/* Set ADC_InitStruct fields to default values */
/* Set fields of ADC instance */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ ADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
+#endif
ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
@@ -706,6 +921,9 @@
* and potentially with ADC in a different state than disabled,
* refer to description of each function for setting
* conditioned to ADC state.
+ * @note On devices STM32WB10xx, STM32WB15xx: Before using this function,
+ * ADC group regular sequencer must be configured: refer to function
+ * @ref LL_ADC_REG_SetSequencerConfigurable().
* @note After using this function, other features must be configured
* using LL unitary functions.
* The minimum configuration remaining to be done is:
@@ -727,11 +945,34 @@
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
+ {
+ assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
+ }
+ if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
+ || (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ )
+ {
+ assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
+
+ /* ADC group regular continuous mode and discontinuous mode */
+ /* can not be enabled simultenaeously */
+ assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
+ || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
+ }
+#else
assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
{
assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
+
+ /* ADC group regular continuous mode and discontinuous mode */
+ /* can not be enabled simultenaeously */
+ assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
+ || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
}
+#endif
assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
@@ -751,6 +992,52 @@
/* - Set ADC group regular overrun behavior */
/* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
/* setting of trigger source to SW start. */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ if( (LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
+ || (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ )
+ {
+ /* Case of sequencer mode fixed
+ or sequencer length >= 2 ranks with sequencer mode fully configurable:
+ discontinuous mode configured */
+ MODIFY_REG(ADCx->CFGR1,
+ ADC_CFGR1_EXTSEL
+ | ADC_CFGR1_EXTEN
+ | ADC_CFGR1_DISCEN
+ | ADC_CFGR1_CONT
+ | ADC_CFGR1_DMAEN
+ | ADC_CFGR1_DMACFG
+ | ADC_CFGR1_OVRMOD
+ ,
+ ADC_REG_InitStruct->TriggerSource
+ | ADC_REG_InitStruct->SequencerDiscont
+ | ADC_REG_InitStruct->ContinuousMode
+ | ADC_REG_InitStruct->DMATransfer
+ | ADC_REG_InitStruct->Overrun
+ );
+ }
+ else
+ {
+ /* Case of sequencer mode fully configurable
+ and sequencer length 1 rank (sequencer disabled):
+ discontinuous mode discarded (fixed to disable) */
+ MODIFY_REG(ADCx->CFGR1,
+ ADC_CFGR1_EXTSEL
+ | ADC_CFGR1_EXTEN
+ | ADC_CFGR1_DISCEN
+ | ADC_CFGR1_CONT
+ | ADC_CFGR1_DMAEN
+ | ADC_CFGR1_DMACFG
+ | ADC_CFGR1_OVRMOD
+ ,
+ ADC_REG_InitStruct->TriggerSource
+ | LL_ADC_REG_SEQ_DISCONT_DISABLE
+ | ADC_REG_InitStruct->ContinuousMode
+ | ADC_REG_InitStruct->DMATransfer
+ | ADC_REG_InitStruct->Overrun
+ );
+ }
+#else
if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
{
MODIFY_REG(ADCx->CFGR,
@@ -789,9 +1076,17 @@
| ADC_REG_InitStruct->Overrun
);
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Set ADC group regular sequencer length and scan direction */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
+ {
+ LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
+ }
+#else
LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
+#endif
}
else
{
@@ -821,6 +1116,9 @@
ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
}
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/**
* @brief Initialize some features of ADC group injected.
* @note These parameters have an impact on ADC scope: ADC group injected.
@@ -847,6 +1145,12 @@
* Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
* - Set ADC channel sampling time
* Refer to function LL_ADC_SetChannelSamplingTime();
+ * @note Caution if feature ADC group injected contexts queue is enabled
+ * (refer to with function @ref LL_ADC_INJ_SetQueueMode() ):
+ * using successively several times this function will appear as
+ * having no effect.
+ * To set several features of ADC group injected, use
+ * function @ref LL_ADC_INJ_ConfigQueueContext().
* @param ADCx ADC instance
* @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
* @retval An ErrorStatus enumeration value:
@@ -934,6 +1238,7 @@
ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
}
+#endif
/**
* @}
*/
diff --git a/Src/stm32wbxx_ll_comp.c b/Src/stm32wbxx_ll_comp.c
index f5c1967..7495e21 100644
--- a/Src/stm32wbxx_ll_comp.c
+++ b/Src/stm32wbxx_ll_comp.c
@@ -55,7 +55,7 @@
|| ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER) \
)
-/* Note: On this STM32 serie, comparator input plus parameters are */
+/* Note: On this STM32 series, comparator input plus parameters are */
/* the same on all COMP instances. */
/* However, comparator instance kept as macro parameter for */
/* compatibility with other STM32 families. */
@@ -72,7 +72,7 @@
)
#endif
-/* Note: On this STM32 serie, comparator input minus parameters are */
+/* Note: On this STM32 series, comparator input minus parameters are */
/* the same on all COMP instances. */
/* However, comparator instance kept as macro parameter for */
/* compatibility with other STM32 families. */
diff --git a/Src/stm32wbxx_ll_pwr.c b/Src/stm32wbxx_ll_pwr.c
index d039338..b275ced 100644
--- a/Src/stm32wbxx_ll_pwr.c
+++ b/Src/stm32wbxx_ll_pwr.c
@@ -109,10 +109,12 @@
/* Clear all flags */
LL_PWR_WriteReg(SCR,
LL_PWR_SCR_CC2HF
- | LL_PWR_SCR_C802AF
| LL_PWR_SCR_CBLEAF
| LL_PWR_SCR_CCRPEF
+#if defined(PWR_CR3_E802A)
+ | LL_PWR_SCR_C802AF
| LL_PWR_SCR_C802WUF
+#endif
| LL_PWR_SCR_CBLEWUF
#if defined(PWR_CR5_SMPSEN)
| LL_PWR_SCR_CBORHF
diff --git a/Src/stm32wbxx_ll_rcc.c b/Src/stm32wbxx_ll_rcc.c
index 23aa838..417ebc5 100644
--- a/Src/stm32wbxx_ll_rcc.c
+++ b/Src/stm32wbxx_ll_rcc.c
@@ -72,9 +72,6 @@
#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
-#if defined(SPI_I2S_SUPPORT)
-#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2S_CLKSOURCE)
-#endif
/**
* @}
*/
@@ -96,9 +93,6 @@
uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void);
#endif
-#if defined(SPI_I2S_SUPPORT)
-uint32_t RCC_PLL_GetFreqDomain_I2S(void);
-#endif
uint32_t RCC_GetSystemClockFreq(void);
@@ -190,13 +184,17 @@
LL_RCC_WriteReg(CIER, 0x00000000U);
/* Clear all interrupt flags */
-#if defined(SAI1)
- vl_mask = RCC_CICR_LSI1RDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | RCC_CICR_PLLSAI1RDYC | \
- RCC_CICR_CSSC | RCC_CICR_HSI48RDYC | RCC_CICR_LSECSSC | RCC_CICR_LSI2RDYC;
-#else
vl_mask = RCC_CICR_LSI1RDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | \
- RCC_CICR_CSSC | RCC_CICR_HSI48RDYC | RCC_CICR_LSECSSC | RCC_CICR_LSI2RDYC;
+ RCC_CICR_CSSC | RCC_CICR_LSECSSC | RCC_CICR_LSI2RDYC;
+
+#if defined(SAI1)
+ vl_mask |= RCC_CICR_PLLSAI1RDYC;
#endif
+
+#if defined(RCC_HSI48_SUPPORT)
+ vl_mask |= RCC_CICR_HSI48RDYC;
+#endif
+
LL_RCC_WriteReg(CICR, vl_mask);
/* Clear reset flags */
@@ -210,8 +208,10 @@
/* RF Wakeup Clock Source selection */
LL_RCC_SetRFWKPClockSource(LL_RCC_RFWKP_CLKSOURCE_NONE);
+#if defined(RCC_HSI48_SUPPORT)
/* HSI48 reset */
LL_RCC_HSI48_Disable();
+#endif
/* HSECR register write unlock & then reset*/
LL_RCC_WriteReg(HSECR, HSE_CONTROL_UNLOCK_KEY);
@@ -407,7 +407,8 @@
* @brief Return I2Cx clock frequency
* @param I2CxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_I2C1_CLKSOURCE
- * @arg @ref LL_RCC_I2C3_CLKSOURCE
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE (*)
+ * @note (*) Value not defined for all devices
* @retval I2C clock frequency (in Hz)
* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
*/
@@ -689,6 +690,7 @@
}
break;
+#if defined(RCC_HSI48_SUPPORT)
case LL_RCC_CLK48_CLKSOURCE_HSI48: /* HSI48 clock used as CLK48 clock source */
default:
if (LL_RCC_HSI48_IsReady() == 1U)
@@ -696,6 +698,11 @@
clk48_frequency = HSI48_VALUE;
}
break;
+#else
+ default:
+ /* Nothing to do */
+ break;
+#endif
}
return clk48_frequency;
@@ -853,7 +860,6 @@
uint32_t LL_RCC_GetRFWKPClockFreq(void)
{
uint32_t rfwkp_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
- uint32_t temp = LL_RCC_LSI2_IsReady();
/* RTCCLK clock frequency */
switch (LL_RCC_GetRFWKPClockSource())
@@ -865,13 +871,6 @@
}
break;
- case LL_RCC_RFWKP_CLKSOURCE_LSI: /* LSI clock used as RF Wakeup clock source */
- if ((LL_RCC_LSI1_IsReady() == 1UL) || (temp == 1UL))
- {
- rfwkp_frequency = LSI_VALUE;
- }
- break;
-
case LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024: /* HSE clock used as RF Wakeup clock source */
rfwkp_frequency = HSE_VALUE / 1024U;
break;
@@ -885,46 +884,6 @@
return rfwkp_frequency;
}
-#if defined(SPI_I2S_SUPPORT)
-/**
- * @brief Return I2Sx clock frequency
- * @param I2SxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_I2S_CLKSOURCE
- * @retval I2S clock frequency (in Hz)
- * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) or PLLs (PLL) is not ready
- */
-uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
-{
- uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
- /* Check parameter */
- assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
-
- /* I2SCLK clock frequency */
- switch (LL_RCC_GetI2SClockSource(I2SxSource))
- {
- case LL_RCC_I2S_CLKSOURCE_PLL: /* I2S2 Clock is PLL"P" */
- if (LL_RCC_PLL_IsReady() == 1U)
- {
- i2s_frequency = RCC_PLL_GetFreqDomain_I2S();
- }
- break;
-
- case LL_RCC_I2S_CLKSOURCE_PIN: /* I2S2 Clock is External clock */
- i2s_frequency = EXTERNAL_CLOCK_VALUE;
- break;
-
- case LL_RCC_I2S_CLKSOURCE_HSI: /* HSI clock used as I2S clock source */
- default:
- if (LL_RCC_HSI_IsReady() == 1U)
- {
- i2s_frequency = HSI_VALUE;
- }
- break;
- }
- return i2s_frequency;
-}
-#endif
/**
* @}
@@ -1363,35 +1322,6 @@
}
#endif
-#if defined(SPI_I2S_SUPPORT)
-/**
- * @brief Return PLL clock frequency used for I2S domain
- * @retval PLL clock frequency (in Hz)
- */
-uint32_t RCC_PLL_GetFreqDomain_I2S(void)
-{
- uint32_t pllinputfreq, pllsource;
-
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
- I2S Domain clock = PLL_VCO / PLLP
- */
- pllsource = LL_RCC_PLL_GetMainSource();
-
- switch (pllsource)
- {
- case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
- pllinputfreq = HSE_VALUE;
- break;
-
- case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
- default:
- pllinputfreq = HSI_VALUE;
- break;
- }
- return __LL_RCC_CALC_PLLCLK_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
- LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
-}
-#endif
/**
* @}
diff --git a/Src/stm32wbxx_ll_utils.c b/Src/stm32wbxx_ll_utils.c
index 19cbaaf..d77d920 100644
--- a/Src/stm32wbxx_ll_utils.c
+++ b/Src/stm32wbxx_ll_utils.c
@@ -258,7 +258,7 @@
*/
ErrorStatus LL_SetFlashLatency(uint32_t HCLK4Frequency)
{
- ErrorStatus status = SUCCESS;
+ ErrorStatus status = ERROR;
uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
uint16_t index;
uint32_t timeout;
@@ -283,11 +283,7 @@
const uint32_t UTILS_LATENCY_RANGE[] = {LL_FLASH_LATENCY_0, LL_FLASH_LATENCY_1, LL_FLASH_LATENCY_2, LL_FLASH_LATENCY_3};
/* Frequency cannot be equal to 0 or greater than max clock */
- if ((HCLK4Frequency == 0U) || (HCLK4Frequency > maxfreq))
- {
- status = ERROR;
- }
- else
+ if ((HCLK4Frequency > 0U) && (HCLK4Frequency <= maxfreq))
{
#if defined(PWR_CR1_VOS)
if (voltagescaling == LL_PWR_REGU_VOLTAGE_SCALE1)
@@ -297,6 +293,7 @@
if (HCLK4Frequency <= UTILS_CLK_SRC_RANGE_VOS1[index])
{
latency = UTILS_LATENCY_RANGE[index];
+ status = SUCCESS;
break;
}
}
@@ -308,6 +305,7 @@
if (HCLK4Frequency <= UTILS_CLK_SRC_RANGE_VOS2[index])
{
latency = UTILS_LATENCY_RANGE[index];
+ status = SUCCESS;
break;
}
}
@@ -318,11 +316,15 @@
if (HCLK4Frequency <= UTILS_CLK_SRC_RANGE_VOS1[index])
{
latency = UTILS_LATENCY_RANGE[index];
+ status = SUCCESS;
break;
}
}
#endif
+ }
+ if (status != ERROR)
+ {
LL_FLASH_SetLatency(latency);
/* Check that the new number of wait states is taken into account to access the Flash
