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Ali Labbenec8987162020-01-29 17:08:08 +01001/**
2 ******************************************************************************
3 * @file stm32wbxx_ll_rng.h
4 * @author MCD Application Team
5 * @brief Header file of RNG LL module.
6 ******************************************************************************
7 * @attention
8 *
rihab kouki2c5f0662021-11-23 15:17:42 +01009 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
Ali Labbenec8987162020-01-29 17:08:08 +010011 *
rihab kouki2c5f0662021-11-23 15:17:42 +010012 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
Ali Labbenec8987162020-01-29 17:08:08 +010015 *
16 ******************************************************************************
17 */
18
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32WBxx_LL_RNG_H
21#define STM32WBxx_LL_RNG_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32wbxx.h"
29
30/** @addtogroup STM32WBxx_LL_Driver
31 * @{
32 */
33
34#if defined (RNG)
35
36/** @defgroup RNG_LL RNG
37 * @{
38 */
39
40/* Private types -------------------------------------------------------------*/
Rania JMAI821c95a2023-07-07 11:31:39 +010041/* Private defines -----------------------------------------------------------*/
Ali Labbenec8987162020-01-29 17:08:08 +010042/* Private variables ---------------------------------------------------------*/
43/* Private constants ---------------------------------------------------------*/
44/* Private macros ------------------------------------------------------------*/
45
46/* Exported types ------------------------------------------------------------*/
47#if defined(USE_FULL_LL_DRIVER)
48/** @defgroup RNG_LL_ES_Init_Struct RNG Exported Init structures
49 * @{
50 */
51
52
53/**
54 * @brief LL RNG Init Structure Definition
55 */
56typedef struct
57{
58 uint32_t ClockErrorDetection; /*!< Clock error detection.
59 This parameter can be one value of @ref RNG_LL_CED.
Rania JMAI821c95a2023-07-07 11:31:39 +010060 This parameter can be modified using unitary
61 functions @ref LL_RNG_EnableClkErrorDetect(). */
Ali Labbenec8987162020-01-29 17:08:08 +010062} LL_RNG_InitTypeDef;
63
64/**
65 * @}
66 */
67#endif /* USE_FULL_LL_DRIVER */
68/* Exported constants --------------------------------------------------------*/
69/** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
70 * @{
71 */
72
73/** @defgroup RNG_LL_CED Clock Error Detection
74 * @{
75 */
76#define LL_RNG_CED_ENABLE 0x00000000U /*!< Clock error detection enabled */
77#define LL_RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection disabled */
78/**
79 * @}
80 */
81
82/** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
83 * @brief Flags defines which can be used with LL_RNG_ReadReg function
84 * @{
85 */
86#define LL_RNG_SR_DRDY RNG_SR_DRDY /*!< Register contains valid random data */
87#define LL_RNG_SR_CECS RNG_SR_CECS /*!< Clock error current status */
88#define LL_RNG_SR_SECS RNG_SR_SECS /*!< Seed error current status */
89#define LL_RNG_SR_CEIS RNG_SR_CEIS /*!< Clock error interrupt status */
90#define LL_RNG_SR_SEIS RNG_SR_SEIS /*!< Seed error interrupt status */
91/**
92 * @}
93 */
94
95/** @defgroup RNG_LL_EC_IT IT Defines
96 * @brief IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros
97 * @{
98 */
99#define LL_RNG_CR_IE RNG_CR_IE /*!< RNG Interrupt enable */
100/**
101 * @}
102 */
103
104/**
105 * @}
106 */
107
108/* Exported macro ------------------------------------------------------------*/
109/** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
110 * @{
111 */
112
113/** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
114 * @{
115 */
116
117/**
118 * @brief Write a value in RNG register
119 * @param __INSTANCE__ RNG Instance
120 * @param __REG__ Register to be written
121 * @param __VALUE__ Value to be written in the register
122 * @retval None
123 */
124#define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
125
126/**
127 * @brief Read a value in RNG register
128 * @param __INSTANCE__ RNG Instance
129 * @param __REG__ Register to be read
130 * @retval Register value
131 */
132#define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
133/**
134 * @}
135 */
136
137/**
138 * @}
139 */
140
141
142/* Exported functions --------------------------------------------------------*/
143/** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
144 * @{
145 */
146/** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
147 * @{
148 */
149
150/**
151 * @brief Enable Random Number Generation
152 * @rmtoll CR RNGEN LL_RNG_Enable
153 * @param RNGx RNG Instance
154 * @retval None
155 */
156__STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
157{
158 SET_BIT(RNGx->CR, RNG_CR_RNGEN);
159}
160
161/**
162 * @brief Disable Random Number Generation
163 * @rmtoll CR RNGEN LL_RNG_Disable
164 * @param RNGx RNG Instance
165 * @retval None
166 */
167__STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
168{
169 CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
170}
171
172/**
173 * @brief Check if Random Number Generator is enabled
174 * @rmtoll CR RNGEN LL_RNG_IsEnabled
175 * @param RNGx RNG Instance
176 * @retval State of bit (1 or 0).
177 */
Rania JMAI821c95a2023-07-07 11:31:39 +0100178__STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx)
Ali Labbenec8987162020-01-29 17:08:08 +0100179{
180 return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
181}
182
183/**
184 * @brief Enable Clock Error Detection
185 * @rmtoll CR CED LL_RNG_EnableClkErrorDetect
186 * @param RNGx RNG Instance
187 * @retval None
188 */
189__STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx)
190{
191 CLEAR_BIT(RNGx->CR, RNG_CR_CED);
192}
193
194/**
195 * @brief Disable RNG Clock Error Detection
196 * @rmtoll CR CED LL_RNG_DisableClkErrorDetect
197 * @param RNGx RNG Instance
198 * @retval None
199 */
200__STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx)
201{
202 SET_BIT(RNGx->CR, RNG_CR_CED);
203}
204
205/**
206 * @brief Check if RNG Clock Error Detection is enabled
207 * @rmtoll CR CED LL_RNG_IsEnabledClkErrorDetect
208 * @param RNGx RNG Instance
209 * @retval State of bit (1 or 0).
210 */
Rania JMAI821c95a2023-07-07 11:31:39 +0100211__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(const RNG_TypeDef *RNGx)
Ali Labbenec8987162020-01-29 17:08:08 +0100212{
213 return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL);
214}
215
216/**
217 * @}
218 */
219
220/** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
221 * @{
222 */
223
224/**
225 * @brief Indicate if the RNG Data ready Flag is set or not
226 * @rmtoll SR DRDY LL_RNG_IsActiveFlag_DRDY
227 * @param RNGx RNG Instance
228 * @retval State of bit (1 or 0).
229 */
Rania JMAI821c95a2023-07-07 11:31:39 +0100230__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef *RNGx)
Ali Labbenec8987162020-01-29 17:08:08 +0100231{
232 return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
233}
234
235/**
236 * @brief Indicate if the Clock Error Current Status Flag is set or not
237 * @rmtoll SR CECS LL_RNG_IsActiveFlag_CECS
238 * @param RNGx RNG Instance
239 * @retval State of bit (1 or 0).
240 */
Rania JMAI821c95a2023-07-07 11:31:39 +0100241__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef *RNGx)
Ali Labbenec8987162020-01-29 17:08:08 +0100242{
243 return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
244}
245
246/**
247 * @brief Indicate if the Seed Error Current Status Flag is set or not
248 * @rmtoll SR SECS LL_RNG_IsActiveFlag_SECS
249 * @param RNGx RNG Instance
250 * @retval State of bit (1 or 0).
251 */
Rania JMAI821c95a2023-07-07 11:31:39 +0100252__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef *RNGx)
Ali Labbenec8987162020-01-29 17:08:08 +0100253{
254 return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
255}
256
257/**
258 * @brief Indicate if the Clock Error Interrupt Status Flag is set or not
259 * @rmtoll SR CEIS LL_RNG_IsActiveFlag_CEIS
260 * @param RNGx RNG Instance
261 * @retval State of bit (1 or 0).
262 */
Rania JMAI821c95a2023-07-07 11:31:39 +0100263__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef *RNGx)
Ali Labbenec8987162020-01-29 17:08:08 +0100264{
265 return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
266}
267
268/**
269 * @brief Indicate if the Seed Error Interrupt Status Flag is set or not
270 * @rmtoll SR SEIS LL_RNG_IsActiveFlag_SEIS
271 * @param RNGx RNG Instance
272 * @retval State of bit (1 or 0).
273 */
Rania JMAI821c95a2023-07-07 11:31:39 +0100274__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef *RNGx)
Ali Labbenec8987162020-01-29 17:08:08 +0100275{
276 return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
277}
278
279/**
280 * @brief Clear Clock Error interrupt Status (CEIS) Flag
281 * @rmtoll SR CEIS LL_RNG_ClearFlag_CEIS
282 * @param RNGx RNG Instance
283 * @retval None
284 */
285__STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
286{
287 WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
288}
289
290/**
291 * @brief Clear Seed Error interrupt Status (SEIS) Flag
292 * @rmtoll SR SEIS LL_RNG_ClearFlag_SEIS
293 * @param RNGx RNG Instance
294 * @retval None
295 */
296__STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
297{
298 WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
299}
300
301/**
302 * @}
303 */
304
305/** @defgroup RNG_LL_EF_IT_Management IT Management
306 * @{
307 */
308
309/**
310 * @brief Enable Random Number Generator Interrupt
311 * (applies for either Seed error, Clock Error or Data ready interrupts)
312 * @rmtoll CR IE LL_RNG_EnableIT
313 * @param RNGx RNG Instance
314 * @retval None
315 */
316__STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
317{
318 SET_BIT(RNGx->CR, RNG_CR_IE);
319}
320
321/**
322 * @brief Disable Random Number Generator Interrupt
323 * (applies for either Seed error, Clock Error or Data ready interrupts)
324 * @rmtoll CR IE LL_RNG_DisableIT
325 * @param RNGx RNG Instance
326 * @retval None
327 */
328__STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
329{
330 CLEAR_BIT(RNGx->CR, RNG_CR_IE);
331}
332
333/**
334 * @brief Check if Random Number Generator Interrupt is enabled
335 * (applies for either Seed error, Clock Error or Data ready interrupts)
336 * @rmtoll CR IE LL_RNG_IsEnabledIT
337 * @param RNGx RNG Instance
338 * @retval State of bit (1 or 0).
339 */
Rania JMAI821c95a2023-07-07 11:31:39 +0100340__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(const RNG_TypeDef *RNGx)
Ali Labbenec8987162020-01-29 17:08:08 +0100341{
342 return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
343}
344
345/**
346 * @}
347 */
348
349/** @defgroup RNG_LL_EF_Data_Management Data Management
350 * @{
351 */
352
353/**
354 * @brief Return32-bit Random Number value
355 * @rmtoll DR RNDATA LL_RNG_ReadRandData32
356 * @param RNGx RNG Instance
357 * @retval Generated 32-bit random value
358 */
Rania JMAI821c95a2023-07-07 11:31:39 +0100359__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx)
Ali Labbenec8987162020-01-29 17:08:08 +0100360{
361 return (uint32_t)(READ_REG(RNGx->DR));
362}
363
364/**
365 * @}
366 */
367
368#if defined(USE_FULL_LL_DRIVER)
369/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
370 * @{
371 */
372ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct);
373void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct);
Rania JMAI821c95a2023-07-07 11:31:39 +0100374ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx);
Ali Labbenec8987162020-01-29 17:08:08 +0100375
376/**
377 * @}
378 */
379#endif /* USE_FULL_LL_DRIVER */
380
381/**
382 * @}
383 */
384
385/**
386 * @}
387 */
388
389#endif /* RNG */
390
391/**
392 * @}
393 */
394
395#ifdef __cplusplus
396}
397#endif
398
399#endif /* __STM32WBxx_LL_RNG_H */
Rania JMAI821c95a2023-07-07 11:31:39 +0100400