Added KiCad project template
diff --git a/hardware/esp-rs_craboard/esp-rs_craboard-cache.lib b/hardware/esp-rs_craboard/esp-rs_craboard-cache.lib new file mode 100644 index 0000000..e933dba --- /dev/null +++ b/hardware/esp-rs_craboard/esp-rs_craboard-cache.lib
@@ -0,0 +1,4 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +#End Library
diff --git a/hardware/esp-rs_craboard/esp-rs_craboard.kicad_pcb b/hardware/esp-rs_craboard/esp-rs_craboard.kicad_pcb new file mode 100644 index 0000000..8fb29ff --- /dev/null +++ b/hardware/esp-rs_craboard/esp-rs_craboard.kicad_pcb
@@ -0,0 +1,132 @@ +(kicad_pcb (version 20171130) (host pcbnew 5.1.9+dfsg1-1) + + (general + (thickness 0.8) + (drawings 0) + (tracks 0) + (zones 0) + (modules 0) + (nets 1) + ) + + (page A4) + (title_block + (title "ESP32-C3 Rust Craboard") + (date 2021-11-19) + (rev 0.1a) + (company "Rust Community") + ) + + (layers + (0 F.Cu signal) + (31 B.Cu signal) + (32 B.Adhes user) + (33 F.Adhes user) + (34 B.Paste user) + (35 F.Paste user) + (36 B.SilkS user) + (37 F.SilkS user) + (38 B.Mask user) + (39 F.Mask user) + (40 Dwgs.User user) + (41 Cmts.User user) + (42 Eco1.User user) + (43 Eco2.User user) + (44 Edge.Cuts user) + (45 Margin user) + (46 B.CrtYd user) + (47 F.CrtYd user) + (48 B.Fab user) + (49 F.Fab user) + ) + + (setup + (last_trace_width 0.25) + (user_trace_width 0.127) + (user_trace_width 0.1524) + (user_trace_width 0.1778) + (user_trace_width 0.2032) + (user_trace_width 0.2286) + (user_trace_width 0.254) + (user_trace_width 0.3048) + (user_trace_width 0.3556) + (user_trace_width 0.4064) + (user_trace_width 0.4572) + (user_trace_width 0.508) + (user_trace_width 0.6096) + (user_trace_width 0.6604) + (user_trace_width 0.762) + (user_trace_width 0.9144) + (user_trace_width 1.016) + (user_trace_width 1.27) + (user_trace_width 2.54) + (trace_clearance 0.2) + (zone_clearance 0.508) + (zone_45_only no) + (trace_min 0.127) + (via_size 0.8) + (via_drill 0.4) + (via_min_size 0.4) + (via_min_drill 0.2) + (user_via 0.4 0.2) + (user_via 0.6 0.3) + (user_via 0.8 0.4) + (user_via 1 0.8) + (uvia_size 0.3) + (uvia_drill 0.1) + (uvias_allowed no) + (uvia_min_size 0.2) + (uvia_min_drill 0.1) + (edge_width 0.05) + (segment_width 0.127) + (pcb_text_width 0.2) + (pcb_text_size 1 1) + (mod_edge_width 0.1524) + (mod_text_size 1 1) + (mod_text_width 0.2) + (pad_size 1.524 1.524) + (pad_drill 0.762) + (pad_to_mask_clearance 0) + (aux_axis_origin 0 0) + (visible_elements FFFFFF7F) + (pcbplotparams + (layerselection 0x010fc_ffffffff) + (usegerberextensions false) + (usegerberattributes true) + (usegerberadvancedattributes true) + (creategerberjobfile true) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "")) + ) + + (net 0 "") + + (net_class Default "This is the default net class." + (clearance 0.2) + (trace_width 0.25) + (via_dia 0.8) + (via_drill 0.4) + (uvia_dia 0.3) + (uvia_drill 0.1) + ) + +)
diff --git a/hardware/esp-rs_craboard/esp-rs_craboard.pro b/hardware/esp-rs_craboard/esp-rs_craboard.pro new file mode 100644 index 0000000..70c1da7 --- /dev/null +++ b/hardware/esp-rs_craboard/esp-rs_craboard.pro
@@ -0,0 +1,270 @@ +update=sex 19 nov 2021 10:10:57 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +[pcbnew] +version=1 +PageLayoutDescrFile= +LastNetListRead= +CopperLayerCount=2 +BoardThickness=0.8 +AllowMicroVias=0 +AllowBlindVias=0 +RequireCourtyardDefinitions=0 +ProhibitOverlappingCourtyards=1 +MinTrackWidth=0.127 +MinViaDiameter=0.4 +MinViaDrill=0.2 +MinMicroViaDiameter=0.2 +MinMicroViaDrill=0.09999999999999999 +MinHoleToHole=0.25 +TrackWidth1=0.25 +TrackWidth2=0.127 +TrackWidth3=0.1524 +TrackWidth4=0.1778 +TrackWidth5=0.2032 +TrackWidth6=0.2286 +TrackWidth7=0.254 +TrackWidth8=0.3048 +TrackWidth9=0.3556 +TrackWidth10=0.4064 +TrackWidth11=0.4572 +TrackWidth12=0.508 +TrackWidth13=0.6096 +TrackWidth14=0.6604 +TrackWidth15=0.762 +TrackWidth16=0.9144 +TrackWidth17=1.016 +TrackWidth18=1.27 +TrackWidth19=2.54 +ViaDiameter1=0.8 +ViaDrill1=0.4 +ViaDiameter2=0.4 +ViaDrill2=0.2 +ViaDiameter3=0.6 +ViaDrill3=0.3 +ViaDiameter4=0.8 +ViaDrill4=0.4 +ViaDiameter5=1 +ViaDrill5=0.8 +dPairWidth1=0.2 +dPairGap1=0.25 +dPairViaGap1=0.25 +dPairWidth2=0.1524 +dPairGap2=0.1524 +dPairViaGap2=0.157 +dPairWidth3=0.2032 +dPairGap3=0.1524 +dPairViaGap3=0.2032 +SilkLineWidth=0.1524 +SilkTextSizeV=1 +SilkTextSizeH=1 +SilkTextSizeThickness=0.2 +SilkTextItalic=0 +SilkTextUpright=1 +CopperLineWidth=0.127 +CopperTextSizeV=1 +CopperTextSizeH=1 +CopperTextThickness=0.2 +CopperTextItalic=0 +CopperTextUpright=1 +EdgeCutLineWidth=0.05 +CourtyardLineWidth=0.05 +OthersLineWidth=0.15 +OthersTextSizeV=1 +OthersTextSizeH=1 +OthersTextSizeThickness=0.15 +OthersTextItalic=0 +OthersTextUpright=1 +SolderMaskClearance=0 +SolderMaskMinWidth=0 +SolderPasteClearance=0 +SolderPasteRatio=-0 +[pcbnew/Layer.F.Cu] +Name=F.Cu +Type=0 +Enabled=1 +[pcbnew/Layer.In1.Cu] +Name=In1.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In2.Cu] +Name=In2.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In3.Cu] +Name=In3.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In4.Cu] +Name=In4.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In5.Cu] +Name=In5.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In6.Cu] +Name=In6.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In7.Cu] +Name=In7.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In8.Cu] +Name=In8.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In9.Cu] +Name=In9.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In10.Cu] +Name=In10.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In11.Cu] +Name=In11.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In12.Cu] +Name=In12.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In13.Cu] +Name=In13.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In14.Cu] +Name=In14.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In15.Cu] +Name=In15.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In16.Cu] +Name=In16.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In17.Cu] +Name=In17.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In18.Cu] +Name=In18.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In19.Cu] +Name=In19.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In20.Cu] +Name=In20.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In21.Cu] +Name=In21.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In22.Cu] +Name=In22.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In23.Cu] +Name=In23.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In24.Cu] +Name=In24.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In25.Cu] +Name=In25.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In26.Cu] +Name=In26.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In27.Cu] +Name=In27.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In28.Cu] +Name=In28.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In29.Cu] +Name=In29.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In30.Cu] +Name=In30.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.B.Cu] +Name=B.Cu +Type=0 +Enabled=1 +[pcbnew/Layer.B.Adhes] +Enabled=1 +[pcbnew/Layer.F.Adhes] +Enabled=1 +[pcbnew/Layer.B.Paste] +Enabled=1 +[pcbnew/Layer.F.Paste] +Enabled=1 +[pcbnew/Layer.B.SilkS] +Enabled=1 +[pcbnew/Layer.F.SilkS] +Enabled=1 +[pcbnew/Layer.B.Mask] +Enabled=1 +[pcbnew/Layer.F.Mask] +Enabled=1 +[pcbnew/Layer.Dwgs.User] +Enabled=1 +[pcbnew/Layer.Cmts.User] +Enabled=1 +[pcbnew/Layer.Eco1.User] +Enabled=1 +[pcbnew/Layer.Eco2.User] +Enabled=1 +[pcbnew/Layer.Edge.Cuts] +Enabled=1 +[pcbnew/Layer.Margin] +Enabled=1 +[pcbnew/Layer.B.CrtYd] +Enabled=1 +[pcbnew/Layer.F.CrtYd] +Enabled=1 +[pcbnew/Layer.B.Fab] +Enabled=1 +[pcbnew/Layer.F.Fab] +Enabled=1 +[pcbnew/Layer.Rescue] +Enabled=0 +[pcbnew/Netclasses] +[pcbnew/Netclasses/Default] +Name=Default +Clearance=0.2 +TrackWidth=0.25 +ViaDiameter=0.8 +ViaDrill=0.4 +uViaDiameter=0.3 +uViaDrill=0.1 +dPairWidth=0.2 +dPairGap=0.25 +dPairViaGap=0.25
diff --git a/hardware/esp-rs_craboard/esp-rs_craboard.sch b/hardware/esp-rs_craboard/esp-rs_craboard.sch new file mode 100644 index 0000000..91d7308 --- /dev/null +++ b/hardware/esp-rs_craboard/esp-rs_craboard.sch
@@ -0,0 +1,16 @@ +EESchema Schematic File Version 4 +EELAYER 30 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "ESP32-C3 Rust Craboard" +Date "2021-11-19" +Rev "0.1a" +Comp "Rust Community" +Comment1 "ESP32-C3 Development board for Rust" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$EndSCHEMATC