stm32c5a3nucleo: use a local linker script, register the board
The DFP linker script marks sections (READONLY), which ld.lld rejects
("symbol not found: READONLY"), so every arm-clang link failed. Copy it
to hw/bsp/stm32c5/linker the way stm32c542nucleo does: READONLY dropped
and a 4 KB stack instead of the template's 1 KB.
Add the board's family.json row and CMake presets, and indent the
stm32c5 board.mk flags with two spaces.
diff --git a/hw/bsp/BoardPresets.json b/hw/bsp/BoardPresets.json
index a324517..e90c521 100644
--- a/hw/bsp/BoardPresets.json
+++ b/hw/bsp/BoardPresets.json
@@ -555,6 +555,10 @@
"inherits": "default"
},
{
+ "name": "ra4m2_ek",
+ "inherits": "default"
+ },
+ {
"name": "ra4m3_ek",
"inherits": "default"
},
@@ -659,6 +663,10 @@
"inherits": "default"
},
{
+ "name": "stm32c5a3nucleo",
+ "inherits": "default"
+ },
+ {
"name": "stm32f070rbnucleo",
"inherits": "default"
},
@@ -899,6 +907,10 @@
"inherits": "default"
},
{
+ "name": "weact_ch32x035_core_board",
+ "inherits": "default"
+ },
+ {
"name": "xmc4500_relax",
"inherits": "default"
},
@@ -959,6 +971,10 @@
"inherits": "default single config"
},
{
+ "name": "espressif_s31_function_core",
+ "inherits": "default single config"
+ },
+ {
"name": "espressif_s3_devkitc",
"inherits": "default single config"
},
@@ -1273,6 +1289,11 @@
"configurePreset": "espressif_s2_devkitc"
},
{
+ "name": "espressif_s31_function_core",
+ "description": "Build preset for the espressif_s31_function_core board",
+ "configurePreset": "espressif_s31_function_core"
+ },
+ {
"name": "espressif_s3_devkitc",
"description": "Build preset for the espressif_s3_devkitc board",
"configurePreset": "espressif_s3_devkitc"
@@ -1713,6 +1734,11 @@
"configurePreset": "ra4m1_ek"
},
{
+ "name": "ra4m2_ek",
+ "description": "Build preset for the ra4m2_ek board",
+ "configurePreset": "ra4m2_ek"
+ },
+ {
"name": "ra4m3_ek",
"description": "Build preset for the ra4m3_ek board",
"configurePreset": "ra4m3_ek"
@@ -1843,6 +1869,11 @@
"configurePreset": "stm32c542nucleo"
},
{
+ "name": "stm32c5a3nucleo",
+ "description": "Build preset for the stm32c5a3nucleo board",
+ "configurePreset": "stm32c5a3nucleo"
+ },
+ {
"name": "stm32f070rbnucleo",
"description": "Build preset for the stm32f070rbnucleo board",
"configurePreset": "stm32f070rbnucleo"
@@ -2143,6 +2174,11 @@
"configurePreset": "waveshare_openh743i"
},
{
+ "name": "weact_ch32x035_core_board",
+ "description": "Build preset for the weact_ch32x035_core_board board",
+ "configurePreset": "weact_ch32x035_core_board"
+ },
+ {
"name": "xmc4500_relax",
"description": "Build preset for the xmc4500_relax board",
"configurePreset": "xmc4500_relax"
@@ -2940,6 +2976,19 @@
]
},
{
+ "name": "espressif_s31_function_core",
+ "steps": [
+ {
+ "type": "configure",
+ "name": "espressif_s31_function_core"
+ },
+ {
+ "type": "build",
+ "name": "espressif_s31_function_core"
+ }
+ ]
+ },
+ {
"name": "espressif_s3_devkitc",
"steps": [
{
@@ -4084,6 +4133,19 @@
]
},
{
+ "name": "ra4m2_ek",
+ "steps": [
+ {
+ "type": "configure",
+ "name": "ra4m2_ek"
+ },
+ {
+ "type": "build",
+ "name": "ra4m2_ek"
+ }
+ ]
+ },
+ {
"name": "ra4m3_ek",
"steps": [
{
@@ -4422,6 +4484,19 @@
]
},
{
+ "name": "stm32c5a3nucleo",
+ "steps": [
+ {
+ "type": "configure",
+ "name": "stm32c5a3nucleo"
+ },
+ {
+ "type": "build",
+ "name": "stm32c5a3nucleo"
+ }
+ ]
+ },
+ {
"name": "stm32f070rbnucleo",
"steps": [
{
@@ -5202,6 +5277,19 @@
]
},
{
+ "name": "weact_ch32x035_core_board",
+ "steps": [
+ {
+ "type": "configure",
+ "name": "weact_ch32x035_core_board"
+ },
+ {
+ "type": "build",
+ "name": "weact_ch32x035_core_board"
+ }
+ ]
+ },
+ {
"name": "xmc4500_relax",
"steps": [
{
diff --git a/hw/bsp/family.json b/hw/bsp/family.json
index cb17f19..10d8e26 100644
--- a/hw/bsp/family.json
+++ b/hw/bsp/family.json
@@ -3393,6 +3393,26 @@
"host"
]
}
+ },
+ "stm32c5a3nucleo": {
+ "cmake": {
+ "defines": {},
+ "family_mcus": [
+ "STM32C5"
+ ],
+ "mcu": "OPT_MCU_STM32C5",
+ "options": {},
+ "portable": [
+ "st/stm32_fsdev/dcd_stm32_fsdev.c",
+ "st/stm32_fsdev/fsdev_common.c",
+ "st/stm32_fsdev/hcd_stm32_fsdev.c"
+ ],
+ "roles": [
+ "device",
+ "dual",
+ "host"
+ ]
+ }
}
},
"stm32f0": {
diff --git a/hw/bsp/stm32c5/boards/stm32c542nucleo/board.mk b/hw/bsp/stm32c5/boards/stm32c542nucleo/board.mk
index d515d1e..ddca1e7 100644
--- a/hw/bsp/stm32c5/boards/stm32c542nucleo/board.mk
+++ b/hw/bsp/stm32c5/boards/stm32c542nucleo/board.mk
@@ -1,9 +1,9 @@
MCU_VARIANT = stm32c542xx
CFLAGS += \
- -DSTM32C542xx \
- -DHSE_VALUE=24000000 \
- -DHSE_STARTUP_TIMEOUT=100
+ -DSTM32C542xx \
+ -DHSE_VALUE=24000000 \
+ -DHSE_STARTUP_TIMEOUT=100
# GCC
LD_FILE = $(FAMILY_PATH)/linker/stm32c542xc_flash.ld
diff --git a/hw/bsp/stm32c5/boards/stm32c5a3nucleo/board.cmake b/hw/bsp/stm32c5/boards/stm32c5a3nucleo/board.cmake
index 79f90e2..57a29fc 100644
--- a/hw/bsp/stm32c5/boards/stm32c5a3nucleo/board.cmake
+++ b/hw/bsp/stm32c5/boards/stm32c5a3nucleo/board.cmake
@@ -1,8 +1,8 @@
set(MCU_VARIANT stm32c5a3xx)
set(JLINK_DEVICE stm32c5a3zg)
-set(LD_FILE_GNU ${TOP}/hw/mcu/st/stm32c5xx-dfp/Source/Templates/gcc/linker/stm32c5a3xg_flash.ld)
-set(LD_FILE_IAR ${TOP}/hw/mcu/st/stm32c5xx-dfp/Source/Templates/iar/linker/stm32c5a3xg_flash.icf)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/stm32c5a3xg_flash.ld)
+set(LD_FILE_IAR ${CMAKE_CURRENT_LIST_DIR}/../../linker/stm32c5a3xg_flash.icf)
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC
diff --git a/hw/bsp/stm32c5/boards/stm32c5a3nucleo/board.h b/hw/bsp/stm32c5/boards/stm32c5a3nucleo/board.h
index 497e27b..893007e 100644
--- a/hw/bsp/stm32c5/boards/stm32c5a3nucleo/board.h
+++ b/hw/bsp/stm32c5/boards/stm32c5a3nucleo/board.h
@@ -48,7 +48,7 @@
#define UART_TX_PIN HAL_GPIO_PIN_2
#define UART_RX_PIN HAL_GPIO_PIN_3
-# if CFG_TUSB_MCU == OPT_MCU_STM32C5
+#if CFG_TUSB_MCU == OPT_MCU_STM32C5
static inline void board_clock_init(void) {
HAL_RCC_HSE_Enable(HAL_RCC_HSE_ON);
@@ -81,5 +81,5 @@
HAL_RCC_PSIDIV3_Enable();
HAL_RCC_CK48_SetKernelClkSource(HAL_RCC_CK48_CLK_SRC_PSIDIV3);
}
-# endif
+#endif
#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32c5/boards/stm32c5a3nucleo/board.mk b/hw/bsp/stm32c5/boards/stm32c5a3nucleo/board.mk
index 3d6ec62..45297cb 100644
--- a/hw/bsp/stm32c5/boards/stm32c5a3nucleo/board.mk
+++ b/hw/bsp/stm32c5/boards/stm32c5a3nucleo/board.mk
@@ -6,8 +6,7 @@
-DHSE_STARTUP_TIMEOUT=100
# GCC
-LD_FILE = hw/mcu/st/stm32c5xx-dfp/Source/Templates/gcc/linker/stm32c5a3xg_flash.ld
-
+LD_FILE = $(FAMILY_PATH)/linker/stm32c5a3xg_flash.ld
# For flash-jlink target
JLINK_DEVICE = stm32c5a3zg
diff --git a/hw/bsp/stm32c5/linker/stm32c5a3xg_flash.icf b/hw/bsp/stm32c5/linker/stm32c5a3xg_flash.icf
new file mode 100644
index 0000000..bbbb541
--- /dev/null
+++ b/hw/bsp/stm32c5/linker/stm32c5a3xg_flash.icf
@@ -0,0 +1,46 @@
+/**
+******************************************************************************
+* @file stm32c5a3xg_flash.icf
+* @brief Linker File
+******************************************************************************
+* @attention
+*
+* Copyright (c) 2026 STMicroelectronics.
+* All rights reserved.
+*
+* This software is licensed under terms that can be found in the LICENSE file
+* in the root directory of this software component.
+* If no LICENSE file comes with this software, it is provided AS-IS.
+*
+******************************************************************************
+*/
+
+define memory mem with size = 4G;
+define region ROM = mem:[from 0x8000000 size 0x100000];
+define region RAM = mem:[from 0x20000000 size 0x40000];
+
+/* define blocks */
+define block HEAP with alignment = 8, size = 0x200 { };
+define block CSTACK with alignment = 8, size = 0x1000 { };
+
+/* setup initialization strategies */
+initialize by copy {
+ readwrite
+};
+
+do not initialize {
+ section .noinit
+};
+
+place at start of ROM { readonly section .intvec } ;
+
+/* sections placements */
+place in ROM {
+ readonly
+};
+
+place in RAM {
+ readwrite,
+ block HEAP,
+ block CSTACK
+};
diff --git a/hw/bsp/stm32c5/linker/stm32c5a3xg_flash.ld b/hw/bsp/stm32c5/linker/stm32c5a3xg_flash.ld
new file mode 100644
index 0000000..51fe057
--- /dev/null
+++ b/hw/bsp/stm32c5/linker/stm32c5a3xg_flash.ld
@@ -0,0 +1,185 @@
+/**
+******************************************************************************
+* @file stm32c5a3xg_flash.ld
+* @brief Linker File
+******************************************************************************
+* @attention
+*
+* Copyright (c) 2026 STMicroelectronics.
+* All rights reserved.
+*
+* This software is licensed under terms that can be found in the LICENSE file
+* in the root directory of this software component.
+* If no LICENSE file comes with this software, it is provided AS-IS.
+*
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = 0x200;
+STACK_SIZE = 0x1000;
+
+
+MEMORY
+{
+ ROM (rx) : org = 0x8000000, len = 0x100000
+ RAM (xrw) : org = 0x20000000, len = 0x40000
+}
+
+SECTIONS
+{
+ .vectors :
+ {
+ . = ALIGN(8);
+ KEEP(*(.vectors));
+ . = ALIGN(8);
+ } > ROM
+
+ .text :
+ {
+ . = ALIGN(8);
+ *(.text);
+ *(.text*);
+ *(.glue_7);
+ *(.glue_7t);
+ *(.eh_frame);
+ KEEP (*(.init));
+ KEEP (*(.fini));
+ . = ALIGN(8);
+ _etext = .;
+ } > ROM
+
+ .rodata :
+ {
+ . = ALIGN(8);
+ *(.rodata);
+ *(.rodata*);
+ . = ALIGN(8);
+ } > ROM
+
+ .ARM.extab : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(8);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(8);
+ } > ROM
+
+ .ARM : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(8);
+ __exidx_start = .;
+ *(.ARM.exidx*);
+ __exidx_end = .;
+ . = ALIGN(8);
+ } > ROM
+
+ .preinit_array : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(8);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*));
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(8);
+ } > ROM
+
+ .init_array : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(8);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)));
+ KEEP (*(.init_array*));
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(8);
+ } > ROM
+
+ .fini_array : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(8);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)));
+ KEEP (*(.fini_array*));
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(8);
+ } > ROM
+
+ .copy.table : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(8);
+ __copy_table_start__ = .;
+ LONG(LOADADDR(.data));
+ LONG (ADDR(.data));
+ LONG (SIZEOF(.data) / 4);
+ __copy_table_end__ = .;
+ } > ROM
+
+ .zero.table : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(8);
+ __zero_table_start__ = .;
+ LONG (ADDR(.bss));
+ LONG (SIZEOF(.bss) / 4);
+ __zero_table_end__ = .;
+ } > ROM
+
+ .data :
+ {
+ . = ALIGN(8);
+ _sidata = LOADADDR(.data);
+ __data_start__ = .;
+ _sdata = .;
+ *(.data);
+ *(.data*);
+ . = ALIGN(8);
+ _edata = .;
+ } > RAM AT> ROM
+
+ .bss :
+ {
+ . = ALIGN(8);
+ _sbss = .;
+ __bss_start__ = _sbss;
+ *(.bss);
+ *(.bss*);
+ *(COMMON);
+ . = ALIGN(8);
+ _ebss = .;
+ __bss_end__ = _ebss;
+ } > RAM
+
+ .heap (NOLOAD) :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE (end = .);
+ _heap_start = .;
+ . += HEAP_SIZE;
+ . = ALIGN(8);
+ _heap_end = .;
+ __HeapLimit = .;
+ } > RAM
+
+ .stack (NOLOAD) :
+ {
+ . = ALIGN(8);
+ __StackLimit = .;
+ . += STACK_SIZE;
+ . = ALIGN(8);
+ __StackTop = .;
+ _estack = .;
+ __stack = .;
+ } > RAM
+
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 :
+ {
+ *(.ARM.attributes)
+ }
+}
