ehci: add ChipIdea isochronous transfers

Opt in with CFG_TUH_CHIPIDEA_ISO_ENABLE (about 2.2 KiB without hub
support); the audio_host example enables it and now builds for LPC43 and
i.MX RT. Supported: HS endpoints with up to three transactions per
microframe, FS endpoints on a native FS port, and FS endpoints behind a HS
hub through split transactions.

- One outstanding transfer and one iTD/siTD per endpoint, sharing the QH
  and qTD pools. Completion unlinks the TD before USBH gets the buffer back,
  so the class callback can submit the next interval.
- No SOF interrupt (ChipIdea raises one every 125 us, even on a FS port):
  completions drive the scheduler; frame-list rollover arms TDs beyond the
  8-frame ring, retires slots that passed unvisited and keeps the extended
  microframe counter current. FRINDEX is rechecked just before linking, so a
  delayed submission moves to a later slot of its phase. A TD is published
  for the next microframe (ChipIdea caches no descriptors).
- Missed slots, cancellation and close retire a TD only when the controller
  cannot be on it (iso_td_idle), without stopping the periodic schedule.
  Schedule waits are bounded; bulk/interrupt abort keeps the transfer when
  the schedule does not stop.
- FS behind a HS hub reserves best-effort MTT windows per hub port; split
  code is compiled out without CFG_TUH_HUB.
- EHCI descriptors and the frame list move to CFG_TUH_UNCACHED_MEM_SECTION
  with barriers instead of descriptor cache maintenance.
- Endpoint lookup by address, idempotent ISO reopen, named iTD/siTD masks.

Host-driver fixtures run under CTest and pre-commit: generic EHCI, ISO
disabled/enabled, cached payloads and no hub. The deferred USBH abort and
endpoint-lifetime work is recorded in docs/superpowers/followup.