commit a029d90af014078a5a58c27e6063abe16b289243
author prabhukr <prabhukr@google.com> Wed Apr 19 08:17:51 2023 -0700
committer prabhukr <prabhukr@google.com> Wed Apr 19 08:37:17 2023 -0700
tree 75c135df0aa8565cb7fa27f2f7a623cd63b4d9f0
parent 13721361f72877decb07cc7747b7a104dbdb0656

Update ARM inline assembly constraints.

Inline assembly in uECC_vli_add is underspecified; the output
registers are written to before the input registers are fully
consumed. Updating the constraints to include earlyclobber `&`.

asm_arm.inc

diff --git a/asm_arm.inc b/asm_arm.inc
index e3c8cb1..12e747f 100644
--- a/asm_arm.inc
+++ b/asm_arm.inc
@@ -20,19 +20,19 @@
 #endif
 
 #if (uECC_PLATFORM == uECC_arm_thumb)
-    #define REG_RW "+l"
-    #define REG_WRITE "=l"
+    #define REG_RW "+&l"
+    #define REG_WRITE "=&l"
 #else
-    #define REG_RW "+r"
-    #define REG_WRITE "=r"
+    #define REG_RW "+&r"
+    #define REG_WRITE "=&r"
 #endif
 
 #if (uECC_PLATFORM == uECC_arm_thumb || uECC_PLATFORM == uECC_arm_thumb2)
-    #define REG_RW_LO "+l"
-    #define REG_WRITE_LO "=l"
+    #define REG_RW_LO "+&l"
+    #define REG_WRITE_LO "=&l"
 #else
-    #define REG_RW_LO "+r"
-    #define REG_WRITE_LO "=r"
+    #define REG_RW_LO "+&r"
+    #define REG_WRITE_LO "=&r"
 #endif
 
 #if (uECC_PLATFORM == uECC_arm_thumb2)