Fix error handling in STM32 test cases
diff --git a/tests/site_scons/platforms/stm32/run_test.sh b/tests/site_scons/platforms/stm32/run_test.sh
index 2c111f5..a3097b7 100755
--- a/tests/site_scons/platforms/stm32/run_test.sh
+++ b/tests/site_scons/platforms/stm32/run_test.sh
@@ -7,13 +7,13 @@
test X$OPENOCD_BOARD == X && export OPENOCD_BOARD=board/stm32f7discovery.cfg
-openocd -f $OPENOCD_BOARD \
+timeout 1200s openocd -f $OPENOCD_BOARD \
-c "reset_config srst_only srst_nogate connect_assert_srst" \
-c "init" -c "arm semihosting enable" \
-c "arm semihosting_cmdline $BASENAME $ARGS" \
-c "reset halt" \
-c "load_image $BINARY 0" \
- -c "reset halt" -c "resume 0x20000000" 2>openocd.log
+ -c "reset halt" -c "resume 0x20000040" 2>openocd.log
RESULT=$?
diff --git a/tests/site_scons/platforms/stm32/stm32_ram.ld b/tests/site_scons/platforms/stm32/stm32_ram.ld
index afaccbc..9fbe9ca 100644
--- a/tests/site_scons/platforms/stm32/stm32_ram.ld
+++ b/tests/site_scons/platforms/stm32/stm32_ram.ld
@@ -46,8 +46,8 @@
{
.text :
{
- KEEP(*(.ramboot))
KEEP(*(.isr_vector))
+ KEEP(*(.ramboot))
*(.text*)
KEEP(*(.init))
diff --git a/tests/site_scons/platforms/stm32/vectors.c b/tests/site_scons/platforms/stm32/vectors.c
index f5b1d11..7e98098 100644
--- a/tests/site_scons/platforms/stm32/vectors.c
+++ b/tests/site_scons/platforms/stm32/vectors.c
@@ -21,7 +21,7 @@
while(1);
}
-void* const g_vector_table[] __attribute__((section(".isr_vector"))) = {
+void* const g_vector_table[16] __attribute__((section(".isr_vector"))) = {
(void*)&__StackTop,
(void*)&_start,
(void*)&HardFaultHandler,
