| # Copyright (c) 2021 Project CHIP Authors |
| # |
| # Licensed under the Apache License, Version 2.0 (the "License"); |
| # you may not use this file except in compliance with the License. |
| # You may obtain a copy of the License at |
| # |
| # http://www.apache.org/licenses/LICENSE-2.0 |
| # |
| # Unless required by applicable law or agreed to in writing, software |
| # distributed under the License is distributed on an "AS IS" BASIS, |
| # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| # See the License for the specific language governing permissions and |
| # limitations under the License. |
| |
| # Memory tools default configuation for TI CC13x2/CC26x2 |
| |
| { |
| 'section': { |
| # By default, only these sections will be included |
| # when operating by sections. |
| 'default': ['.text', '.rodata', '.data', '.bss'] |
| }, |
| 'symbol': { |
| 'free': { |
| # These symbols mark the start or end of areas where memory that |
| # does not belong to any symbol is considered unused (rather than |
| # a gap that may be in use for some non-symbol purpose, e.g. string |
| # constants or alignment). |
| 'start': ['_stack'], |
| 'end': ['_stack_end', '__stack_end'], |
| } |
| }, |
| 'region': { |
| # Regions are sets of sections that can be used for aggregate reports. |
| 'sections': { |
| 'FLASH': [ |
| '.text', |
| '.rodata', |
| '.resetVecs', |
| '.ccfg', |
| '.ARM.exidx', |
| ], |
| 'RAM': [ |
| '.bss', |
| '.data', |
| '.heap', |
| '.nvs', |
| '.stack', |
| 'vtable_ram', |
| ], |
| } |
| }, |
| 'collect': { |
| # Strip these prefixes from compilation unit paths. |
| 'prefix': [ |
| r'C:\\.conan\\1233bc\\1\\source\\ti\\', |
| ], |
| 'prefix-file': True, |
| }, |
| } |