- clang format
diff --git a/src/arm/api.h b/src/arm/api.h
index b1be639..dc3858d 100644
--- a/src/arm/api.h
+++ b/src/arm/api.h
@@ -1,9 +1,9 @@
#pragma once
#ifdef _MSC_VER
- #define RESTRICT_STATIC /* nothing for MSVC */
+#define RESTRICT_STATIC /* nothing for MSVC */
#else
- #define RESTRICT_STATIC restrict static
+#define RESTRICT_STATIC restrict static
#endif
#include <stdbool.h>
@@ -13,121 +13,112 @@
#include <cpuinfo/common.h>
enum cpuinfo_arm_chipset_vendor {
- cpuinfo_arm_chipset_vendor_unknown = 0,
- cpuinfo_arm_chipset_vendor_qualcomm,
- cpuinfo_arm_chipset_vendor_mediatek,
- cpuinfo_arm_chipset_vendor_samsung,
- cpuinfo_arm_chipset_vendor_hisilicon,
- cpuinfo_arm_chipset_vendor_actions,
- cpuinfo_arm_chipset_vendor_allwinner,
- cpuinfo_arm_chipset_vendor_amlogic,
- cpuinfo_arm_chipset_vendor_broadcom,
- cpuinfo_arm_chipset_vendor_lg,
- cpuinfo_arm_chipset_vendor_leadcore,
- cpuinfo_arm_chipset_vendor_marvell,
- cpuinfo_arm_chipset_vendor_mstar,
- cpuinfo_arm_chipset_vendor_novathor,
- cpuinfo_arm_chipset_vendor_nvidia,
- cpuinfo_arm_chipset_vendor_pinecone,
- cpuinfo_arm_chipset_vendor_renesas,
- cpuinfo_arm_chipset_vendor_rockchip,
- cpuinfo_arm_chipset_vendor_spreadtrum,
- cpuinfo_arm_chipset_vendor_telechips,
- cpuinfo_arm_chipset_vendor_texas_instruments,
- cpuinfo_arm_chipset_vendor_unisoc,
- cpuinfo_arm_chipset_vendor_wondermedia,
- cpuinfo_arm_chipset_vendor_max,
+ cpuinfo_arm_chipset_vendor_unknown = 0,
+ cpuinfo_arm_chipset_vendor_qualcomm,
+ cpuinfo_arm_chipset_vendor_mediatek,
+ cpuinfo_arm_chipset_vendor_samsung,
+ cpuinfo_arm_chipset_vendor_hisilicon,
+ cpuinfo_arm_chipset_vendor_actions,
+ cpuinfo_arm_chipset_vendor_allwinner,
+ cpuinfo_arm_chipset_vendor_amlogic,
+ cpuinfo_arm_chipset_vendor_broadcom,
+ cpuinfo_arm_chipset_vendor_lg,
+ cpuinfo_arm_chipset_vendor_leadcore,
+ cpuinfo_arm_chipset_vendor_marvell,
+ cpuinfo_arm_chipset_vendor_mstar,
+ cpuinfo_arm_chipset_vendor_novathor,
+ cpuinfo_arm_chipset_vendor_nvidia,
+ cpuinfo_arm_chipset_vendor_pinecone,
+ cpuinfo_arm_chipset_vendor_renesas,
+ cpuinfo_arm_chipset_vendor_rockchip,
+ cpuinfo_arm_chipset_vendor_spreadtrum,
+ cpuinfo_arm_chipset_vendor_telechips,
+ cpuinfo_arm_chipset_vendor_texas_instruments,
+ cpuinfo_arm_chipset_vendor_unisoc,
+ cpuinfo_arm_chipset_vendor_wondermedia,
+ cpuinfo_arm_chipset_vendor_max,
};
enum cpuinfo_arm_chipset_series {
- cpuinfo_arm_chipset_series_unknown = 0,
- cpuinfo_arm_chipset_series_qualcomm_qsd,
- cpuinfo_arm_chipset_series_qualcomm_msm,
- cpuinfo_arm_chipset_series_qualcomm_apq,
- cpuinfo_arm_chipset_series_qualcomm_snapdragon,
- cpuinfo_arm_chipset_series_mediatek_mt,
- cpuinfo_arm_chipset_series_samsung_exynos,
- cpuinfo_arm_chipset_series_hisilicon_k3v,
- cpuinfo_arm_chipset_series_hisilicon_hi,
- cpuinfo_arm_chipset_series_hisilicon_kirin,
- cpuinfo_arm_chipset_series_actions_atm,
- cpuinfo_arm_chipset_series_allwinner_a,
- cpuinfo_arm_chipset_series_amlogic_aml,
- cpuinfo_arm_chipset_series_amlogic_s,
- cpuinfo_arm_chipset_series_broadcom_bcm,
- cpuinfo_arm_chipset_series_lg_nuclun,
- cpuinfo_arm_chipset_series_leadcore_lc,
- cpuinfo_arm_chipset_series_marvell_pxa,
- cpuinfo_arm_chipset_series_mstar_6a,
- cpuinfo_arm_chipset_series_novathor_u,
- cpuinfo_arm_chipset_series_nvidia_tegra_t,
- cpuinfo_arm_chipset_series_nvidia_tegra_ap,
- cpuinfo_arm_chipset_series_nvidia_tegra_sl,
- cpuinfo_arm_chipset_series_pinecone_surge_s,
- cpuinfo_arm_chipset_series_renesas_mp,
- cpuinfo_arm_chipset_series_rockchip_rk,
- cpuinfo_arm_chipset_series_spreadtrum_sc,
- cpuinfo_arm_chipset_series_telechips_tcc,
- cpuinfo_arm_chipset_series_texas_instruments_omap,
- cpuinfo_arm_chipset_series_unisoc_t,
- cpuinfo_arm_chipset_series_unisoc_ums,
- cpuinfo_arm_chipset_series_wondermedia_wm,
- cpuinfo_arm_chipset_series_max,
+ cpuinfo_arm_chipset_series_unknown = 0,
+ cpuinfo_arm_chipset_series_qualcomm_qsd,
+ cpuinfo_arm_chipset_series_qualcomm_msm,
+ cpuinfo_arm_chipset_series_qualcomm_apq,
+ cpuinfo_arm_chipset_series_qualcomm_snapdragon,
+ cpuinfo_arm_chipset_series_mediatek_mt,
+ cpuinfo_arm_chipset_series_samsung_exynos,
+ cpuinfo_arm_chipset_series_hisilicon_k3v,
+ cpuinfo_arm_chipset_series_hisilicon_hi,
+ cpuinfo_arm_chipset_series_hisilicon_kirin,
+ cpuinfo_arm_chipset_series_actions_atm,
+ cpuinfo_arm_chipset_series_allwinner_a,
+ cpuinfo_arm_chipset_series_amlogic_aml,
+ cpuinfo_arm_chipset_series_amlogic_s,
+ cpuinfo_arm_chipset_series_broadcom_bcm,
+ cpuinfo_arm_chipset_series_lg_nuclun,
+ cpuinfo_arm_chipset_series_leadcore_lc,
+ cpuinfo_arm_chipset_series_marvell_pxa,
+ cpuinfo_arm_chipset_series_mstar_6a,
+ cpuinfo_arm_chipset_series_novathor_u,
+ cpuinfo_arm_chipset_series_nvidia_tegra_t,
+ cpuinfo_arm_chipset_series_nvidia_tegra_ap,
+ cpuinfo_arm_chipset_series_nvidia_tegra_sl,
+ cpuinfo_arm_chipset_series_pinecone_surge_s,
+ cpuinfo_arm_chipset_series_renesas_mp,
+ cpuinfo_arm_chipset_series_rockchip_rk,
+ cpuinfo_arm_chipset_series_spreadtrum_sc,
+ cpuinfo_arm_chipset_series_telechips_tcc,
+ cpuinfo_arm_chipset_series_texas_instruments_omap,
+ cpuinfo_arm_chipset_series_unisoc_t,
+ cpuinfo_arm_chipset_series_unisoc_ums,
+ cpuinfo_arm_chipset_series_wondermedia_wm,
+ cpuinfo_arm_chipset_series_max,
};
#define CPUINFO_ARM_CHIPSET_SUFFIX_MAX 8
struct cpuinfo_arm_chipset {
- enum cpuinfo_arm_chipset_vendor vendor;
- enum cpuinfo_arm_chipset_series series;
- uint32_t model;
- char suffix[CPUINFO_ARM_CHIPSET_SUFFIX_MAX];
+ enum cpuinfo_arm_chipset_vendor vendor;
+ enum cpuinfo_arm_chipset_series series;
+ uint32_t model;
+ char suffix[CPUINFO_ARM_CHIPSET_SUFFIX_MAX];
};
#define CPUINFO_ARM_CHIPSET_NAME_MAX CPUINFO_PACKAGE_NAME_MAX
#ifndef __cplusplus
CPUINFO_INTERNAL void cpuinfo_arm_chipset_to_string(
- const struct cpuinfo_arm_chipset chipset[RESTRICT_STATIC 1],
- char name[RESTRICT_STATIC CPUINFO_ARM_CHIPSET_NAME_MAX]);
+ const struct cpuinfo_arm_chipset chipset[RESTRICT_STATIC 1],
+ char name[RESTRICT_STATIC CPUINFO_ARM_CHIPSET_NAME_MAX]);
-CPUINFO_INTERNAL void cpuinfo_arm_fixup_chipset(
- struct cpuinfo_arm_chipset chipset[RESTRICT_STATIC 1],
- uint32_t cores,
- uint32_t max_cpu_freq_max);
+CPUINFO_INTERNAL void
+cpuinfo_arm_fixup_chipset(struct cpuinfo_arm_chipset chipset[RESTRICT_STATIC 1],
+ uint32_t cores, uint32_t max_cpu_freq_max);
-CPUINFO_INTERNAL void cpuinfo_arm_decode_vendor_uarch(
- uint32_t midr,
+CPUINFO_INTERNAL void
+cpuinfo_arm_decode_vendor_uarch(uint32_t midr,
#if CPUINFO_ARCH_ARM
- bool has_vfpv4,
+ bool has_vfpv4,
#endif
- enum cpuinfo_vendor vendor[RESTRICT_STATIC 1],
- enum cpuinfo_uarch uarch[RESTRICT_STATIC 1]);
+ enum cpuinfo_vendor vendor[RESTRICT_STATIC 1],
+ enum cpuinfo_uarch uarch[RESTRICT_STATIC 1]);
CPUINFO_INTERNAL void cpuinfo_arm_decode_cache(
- enum cpuinfo_uarch uarch,
- uint32_t cluster_cores,
- uint32_t midr,
- const struct cpuinfo_arm_chipset chipset[RESTRICT_STATIC 1],
- uint32_t cluster_id,
- uint32_t arch_version,
- struct cpuinfo_cache l1i[RESTRICT_STATIC 1],
- struct cpuinfo_cache l1d[RESTRICT_STATIC 1],
- struct cpuinfo_cache l2[RESTRICT_STATIC 1],
- struct cpuinfo_cache l3[RESTRICT_STATIC 1]);
+ enum cpuinfo_uarch uarch, uint32_t cluster_cores, uint32_t midr,
+ const struct cpuinfo_arm_chipset chipset[RESTRICT_STATIC 1],
+ uint32_t cluster_id, uint32_t arch_version,
+ struct cpuinfo_cache l1i[RESTRICT_STATIC 1],
+ struct cpuinfo_cache l1d[RESTRICT_STATIC 1],
+ struct cpuinfo_cache l2[RESTRICT_STATIC 1],
+ struct cpuinfo_cache l3[RESTRICT_STATIC 1]);
-CPUINFO_INTERNAL uint32_t
-cpuinfo_arm_compute_max_cache_size(const struct cpuinfo_processor processor[RESTRICT_STATIC 1]);
+CPUINFO_INTERNAL uint32_t cpuinfo_arm_compute_max_cache_size(
+ const struct cpuinfo_processor processor[RESTRICT_STATIC 1]);
#else /* defined(__cplusplus) */
CPUINFO_INTERNAL void cpuinfo_arm_decode_cache(
- enum cpuinfo_uarch uarch,
- uint32_t cluster_cores,
- uint32_t midr,
- const struct cpuinfo_arm_chipset chipset[1],
- uint32_t cluster_id,
- uint32_t arch_version,
- struct cpuinfo_cache l1i[1],
- struct cpuinfo_cache l1d[1],
- struct cpuinfo_cache l2[1],
- struct cpuinfo_cache l3[1]);
+ enum cpuinfo_uarch uarch, uint32_t cluster_cores, uint32_t midr,
+ const struct cpuinfo_arm_chipset chipset[1], uint32_t cluster_id,
+ uint32_t arch_version, struct cpuinfo_cache l1i[1],
+ struct cpuinfo_cache l1d[1], struct cpuinfo_cache l2[1],
+ struct cpuinfo_cache l3[1]);
#endif
diff --git a/src/arm/windows/init.c b/src/arm/windows/init.c
index 8409843..2e4ec2e 100644
--- a/src/arm/windows/init.c
+++ b/src/arm/windows/init.c
@@ -15,213 +15,214 @@
struct cpuinfo_arm_isa cpuinfo_isa;
static void set_cpuinfo_isa_fields(void);
-static struct woa_chip_info* get_system_info_from_registry(void);
+static struct woa_chip_info *get_system_info_from_registry(void);
-static struct woa_chip_info woa_chip_unknown = {L"Unknown", {{cpuinfo_vendor_unknown, cpuinfo_uarch_unknown, 0}}};
+static struct woa_chip_info woa_chip_unknown = {
+ L"Unknown", {{cpuinfo_vendor_unknown, cpuinfo_uarch_unknown, 0}}};
-BOOL CALLBACK cpuinfo_arm_windows_init(PINIT_ONCE init_once, PVOID parameter, PVOID* context) {
- struct woa_chip_info* chip_info = NULL;
- enum cpuinfo_vendor vendor = cpuinfo_vendor_unknown;
+BOOL CALLBACK cpuinfo_arm_windows_init(PINIT_ONCE init_once, PVOID parameter,
+ PVOID *context) {
+ struct woa_chip_info *chip_info = NULL;
+ enum cpuinfo_vendor vendor = cpuinfo_vendor_unknown;
- set_cpuinfo_isa_fields();
+ set_cpuinfo_isa_fields();
- chip_info = get_system_info_from_registry();
- if (chip_info == NULL) {
- chip_info = &woa_chip_unknown;
- }
+ chip_info = get_system_info_from_registry();
+ if (chip_info == NULL) {
+ chip_info = &woa_chip_unknown;
+ }
- cpuinfo_is_initialized = cpu_info_init_by_logical_sys_info(chip_info, chip_info->uarchs[0].vendor);
+ cpuinfo_is_initialized =
+ cpu_info_init_by_logical_sys_info(chip_info, chip_info->uarchs[0].vendor);
- return true;
+ return true;
}
/* Static helper functions */
-static wchar_t* read_registry(LPCWSTR subkey, LPCWSTR value) {
- DWORD key_type = 0;
- DWORD data_size = 0;
- const DWORD flags = RRF_RT_REG_SZ; /* Only read strings (REG_SZ) */
- wchar_t* text_buffer = NULL;
- LSTATUS result = 0;
- HANDLE heap = GetProcessHeap();
+static wchar_t *read_registry(LPCWSTR subkey, LPCWSTR value) {
+ DWORD key_type = 0;
+ DWORD data_size = 0;
+ const DWORD flags = RRF_RT_REG_SZ; /* Only read strings (REG_SZ) */
+ wchar_t *text_buffer = NULL;
+ LSTATUS result = 0;
+ HANDLE heap = GetProcessHeap();
- result = RegGetValueW(
- HKEY_LOCAL_MACHINE,
- subkey,
- value,
- flags,
- &key_type,
- NULL, /* Request buffer size */
- &data_size);
- if (result != 0 || data_size == 0) {
- cpuinfo_log_error("Registry entry size read error");
- return NULL;
- }
+ result = RegGetValueW(HKEY_LOCAL_MACHINE, subkey, value, flags, &key_type,
+ NULL, /* Request buffer size */
+ &data_size);
+ if (result != 0 || data_size == 0) {
+ cpuinfo_log_error("Registry entry size read error");
+ return NULL;
+ }
- text_buffer = HeapAlloc(heap, HEAP_ZERO_MEMORY, data_size);
- if (text_buffer == NULL) {
- cpuinfo_log_error("Registry textbuffer allocation error");
- return NULL;
- }
+ text_buffer = HeapAlloc(heap, HEAP_ZERO_MEMORY, data_size);
+ if (text_buffer == NULL) {
+ cpuinfo_log_error("Registry textbuffer allocation error");
+ return NULL;
+ }
- result = RegGetValueW(
- HKEY_LOCAL_MACHINE,
- subkey,
- value,
- flags,
- NULL,
- text_buffer, /* Write string in this destination buffer */
- &data_size);
- if (result != 0) {
- cpuinfo_log_error("Registry read error");
- HeapFree(heap, 0, text_buffer);
- return NULL;
- }
- return text_buffer;
+ result =
+ RegGetValueW(HKEY_LOCAL_MACHINE, subkey, value, flags, NULL,
+ text_buffer, /* Write string in this destination buffer */
+ &data_size);
+ if (result != 0) {
+ cpuinfo_log_error("Registry read error");
+ HeapFree(heap, 0, text_buffer);
+ return NULL;
+ }
+ return text_buffer;
}
static uint64_t read_registry_qword(LPCWSTR subkey, LPCWSTR value) {
- DWORD key_type = 0;
- DWORD data_size = sizeof(uint64_t);
- const DWORD flags = RRF_RT_REG_QWORD; /* Only read QWORD (REG_QWORD) values */
- uint64_t qword_value = 0;
- LSTATUS result = RegGetValueW(HKEY_LOCAL_MACHINE, subkey, value, flags, &key_type, &qword_value, &data_size);
- if (result != ERROR_SUCCESS || data_size != sizeof(uint64_t)) {
- cpuinfo_log_error("Registry QWORD read error");
- return 0;
- }
- return qword_value;
+ DWORD key_type = 0;
+ DWORD data_size = sizeof(uint64_t);
+ const DWORD flags = RRF_RT_REG_QWORD; /* Only read QWORD (REG_QWORD) values */
+ uint64_t qword_value = 0;
+ LSTATUS result = RegGetValueW(HKEY_LOCAL_MACHINE, subkey, value, flags,
+ &key_type, &qword_value, &data_size);
+ if (result != ERROR_SUCCESS || data_size != sizeof(uint64_t)) {
+ cpuinfo_log_error("Registry QWORD read error");
+ return 0;
+ }
+ return qword_value;
}
static uint64_t read_registry_dword(LPCWSTR subkey, LPCWSTR value) {
- DWORD key_type = 0;
- DWORD data_size = sizeof(DWORD);
- DWORD dword_value = 0;
- LSTATUS result = RegGetValueW(
- HKEY_LOCAL_MACHINE,
- subkey,
- value,
- RRF_RT_REG_DWORD,
- &key_type,
- &dword_value,
- &data_size);
- if (result != ERROR_SUCCESS || data_size != sizeof(DWORD)) {
- cpuinfo_log_error("Registry DWORD read error");
- return 0;
- }
- return (uint64_t)dword_value;
+ DWORD key_type = 0;
+ DWORD data_size = sizeof(DWORD);
+ DWORD dword_value = 0;
+ LSTATUS result =
+ RegGetValueW(HKEY_LOCAL_MACHINE, subkey, value, RRF_RT_REG_DWORD,
+ &key_type, &dword_value, &data_size);
+ if (result != ERROR_SUCCESS || data_size != sizeof(DWORD)) {
+ cpuinfo_log_error("Registry DWORD read error");
+ return 0;
+ }
+ return (uint64_t)dword_value;
}
-static wchar_t* wcsndup(const wchar_t* src, size_t n) {
- size_t len = wcsnlen(src, n);
- wchar_t* dup = HeapAlloc(GetProcessHeap(), HEAP_ZERO_MEMORY, (len + 1) * sizeof(wchar_t));
- if (dup) {
- wcsncpy_s(dup, len + 1, src, len);
- dup[len] = L'\0';
- }
- return dup;
+static wchar_t *wcsndup(const wchar_t *src, size_t n) {
+ size_t len = wcsnlen(src, n);
+ wchar_t *dup = HeapAlloc(GetProcessHeap(), HEAP_ZERO_MEMORY,
+ (len + 1) * sizeof(wchar_t));
+ if (dup) {
+ wcsncpy_s(dup, len + 1, src, len);
+ dup[len] = L'\0';
+ }
+ return dup;
}
-static struct core_info_by_chip_name get_core_info_from_midr(uint32_t midr, uint64_t frequency) {
- struct core_info_by_chip_name info;
- enum cpuinfo_vendor vendor;
- enum cpuinfo_uarch uarch;
+static struct core_info_by_chip_name
+get_core_info_from_midr(uint32_t midr, uint64_t frequency) {
+ struct core_info_by_chip_name info;
+ enum cpuinfo_vendor vendor;
+ enum cpuinfo_uarch uarch;
#if CPUINFO_ARCH_ARM
- bool has_vfpv4 = false;
- cpuinfo_arm_decode_vendor_uarch(midr, has_vfpv4, &vendor, &uarch);
+ bool has_vfpv4 = false;
+ cpuinfo_arm_decode_vendor_uarch(midr, has_vfpv4, &vendor, &uarch);
#else
- cpuinfo_arm_decode_vendor_uarch(midr, &vendor, &uarch);
+ cpuinfo_arm_decode_vendor_uarch(midr, &vendor, &uarch);
#endif
- info.vendor = vendor;
- info.uarch = uarch;
- info.frequency = frequency;
- return info;
+ info.vendor = vendor;
+ info.uarch = uarch;
+ info.frequency = frequency;
+ return info;
}
-static struct woa_chip_info* get_system_info_from_registry(void) {
- wchar_t* text_buffer = NULL;
- LPCWSTR cpu0_subkey = L"HARDWARE\\DESCRIPTION\\System\\CentralProcessor\\0";
- LPCWSTR chip_name_value = L"ProcessorNameString";
- LPCWSTR chip_midr_value = L"CP 4000";
- LPCWSTR chip_mhz_value = L"~MHz";
- struct woa_chip_info* chip_info = NULL;
+static struct woa_chip_info *get_system_info_from_registry(void) {
+ wchar_t *text_buffer = NULL;
+ LPCWSTR cpu0_subkey = L"HARDWARE\\DESCRIPTION\\System\\CentralProcessor\\0";
+ LPCWSTR chip_name_value = L"ProcessorNameString";
+ LPCWSTR chip_midr_value = L"CP 4000";
+ LPCWSTR chip_mhz_value = L"~MHz";
+ struct woa_chip_info *chip_info = NULL;
- /* Read processor model name from registry and find in the hard-coded
- * list. */
- text_buffer = read_registry(cpu0_subkey, chip_name_value);
- if (text_buffer == NULL) {
- cpuinfo_log_error("Registry read error for processor name");
- return NULL;
- }
+ /* Read processor model name from registry and find in the hard-coded
+ * list. */
+ text_buffer = read_registry(cpu0_subkey, chip_name_value);
+ if (text_buffer == NULL) {
+ cpuinfo_log_error("Registry read error for processor name");
+ return NULL;
+ }
- /*
- * https://developer.arm.com/documentation/100442/0100/register-descriptions/aarch32-system-registers/midr--main-id-register
- * Regedit for MIDR : HKEY_LOCAL_MACHINE\HARDWARE\DESCRIPTION\System\CentralProcessor\0\CP 4000
- */
- uint64_t midr_qword = (uint32_t)read_registry_qword(cpu0_subkey, chip_midr_value);
- if (midr_qword == 0) {
- cpuinfo_log_error("Registry read error for MIDR value");
- return NULL;
- }
- // MIDR is only 32 bits, so we need to cast it to uint32_t
- uint32_t midr_value = (uint32_t)midr_qword;
+ /*
+ * https://developer.arm.com/documentation/100442/0100/register-descriptions/aarch32-system-registers/midr--main-id-register
+ * Regedit for MIDR :
+ *HKEY_LOCAL_MACHINE\HARDWARE\DESCRIPTION\System\CentralProcessor\0\CP 4000
+ */
+ uint64_t midr_qword =
+ (uint32_t)read_registry_qword(cpu0_subkey, chip_midr_value);
+ if (midr_qword == 0) {
+ cpuinfo_log_error("Registry read error for MIDR value");
+ return NULL;
+ }
+ // MIDR is only 32 bits, so we need to cast it to uint32_t
+ uint32_t midr_value = (uint32_t)midr_qword;
- /* Read the frequency from the registry
- * The value is in MHz, so we need to convert it to Hz */
- uint64_t frequency_mhz = read_registry_dword(cpu0_subkey, chip_mhz_value);
- if (frequency_mhz == 0) {
- cpuinfo_log_error("Registry read error for frequency value");
- return NULL;
- }
- // Convert MHz to Hz
- uint64_t frequency_hz = frequency_mhz * 1000000;
+ /* Read the frequency from the registry
+ * The value is in MHz, so we need to convert it to Hz */
+ uint64_t frequency_mhz = read_registry_dword(cpu0_subkey, chip_mhz_value);
+ if (frequency_mhz == 0) {
+ cpuinfo_log_error("Registry read error for frequency value");
+ return NULL;
+ }
+ // Convert MHz to Hz
+ uint64_t frequency_hz = frequency_mhz * 1000000;
- // Allocate chip_info before using it.
- chip_info = HeapAlloc(GetProcessHeap(), HEAP_ZERO_MEMORY, sizeof(struct woa_chip_info));
- if (chip_info == NULL) {
- cpuinfo_log_error("Heap allocation error for chip_info");
- return NULL;
- }
+ // Allocate chip_info before using it.
+ chip_info = HeapAlloc(GetProcessHeap(), HEAP_ZERO_MEMORY,
+ sizeof(struct woa_chip_info));
+ if (chip_info == NULL) {
+ cpuinfo_log_error("Heap allocation error for chip_info");
+ return NULL;
+ }
- // set chip_info fields
- chip_info->chip_name_string = wcsndup(text_buffer, CPUINFO_PACKAGE_NAME_MAX - 1);
- chip_info->uarchs[0] = get_core_info_from_midr(midr_value, frequency_hz);
-
- cpuinfo_log_debug("detected chip model name: %ls", chip_info->chip_name_string);
+ // set chip_info fields
+ chip_info->chip_name_string =
+ wcsndup(text_buffer, CPUINFO_PACKAGE_NAME_MAX - 1);
+ chip_info->uarchs[0] = get_core_info_from_midr(midr_value, frequency_hz);
- return chip_info;
+ cpuinfo_log_debug("detected chip model name: %ls",
+ chip_info->chip_name_string);
+
+ return chip_info;
}
static void set_cpuinfo_isa_fields(void) {
- cpuinfo_isa.atomics = IsProcessorFeaturePresent(PF_ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE) != 0;
+ cpuinfo_isa.atomics =
+ IsProcessorFeaturePresent(PF_ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE) != 0;
- const bool dotprod = IsProcessorFeaturePresent(PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE) != 0;
- cpuinfo_isa.dot = dotprod;
+ const bool dotprod =
+ IsProcessorFeaturePresent(PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE) != 0;
+ cpuinfo_isa.dot = dotprod;
- SYSTEM_INFO system_info;
- GetSystemInfo(&system_info);
- switch (system_info.wProcessorLevel) {
- case 0x803: // Kryo 385 Silver (Snapdragon 850)
- cpuinfo_isa.fp16arith = dotprod;
- cpuinfo_isa.rdm = dotprod;
- break;
- default:
- // Assume that Dot Product support implies FP16
- // arithmetics and RDM support. ARM manuals don't
- // guarantee that, but it holds in practice.
- cpuinfo_isa.fp16arith = dotprod;
- cpuinfo_isa.rdm = dotprod;
- break;
- }
+ SYSTEM_INFO system_info;
+ GetSystemInfo(&system_info);
+ switch (system_info.wProcessorLevel) {
+ case 0x803: // Kryo 385 Silver (Snapdragon 850)
+ cpuinfo_isa.fp16arith = dotprod;
+ cpuinfo_isa.rdm = dotprod;
+ break;
+ default:
+ // Assume that Dot Product support implies FP16
+ // arithmetics and RDM support. ARM manuals don't
+ // guarantee that, but it holds in practice.
+ cpuinfo_isa.fp16arith = dotprod;
+ cpuinfo_isa.rdm = dotprod;
+ break;
+ }
- /* Windows API reports all or nothing for cryptographic instructions. */
- const bool crypto = IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE) != 0;
- cpuinfo_isa.aes = crypto;
- cpuinfo_isa.sha1 = crypto;
- cpuinfo_isa.sha2 = crypto;
- cpuinfo_isa.pmull = crypto;
+ /* Windows API reports all or nothing for cryptographic instructions. */
+ const bool crypto =
+ IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE) != 0;
+ cpuinfo_isa.aes = crypto;
+ cpuinfo_isa.sha1 = crypto;
+ cpuinfo_isa.sha2 = crypto;
+ cpuinfo_isa.pmull = crypto;
- cpuinfo_isa.crc32 = IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE) != 0;
+ cpuinfo_isa.crc32 =
+ IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE) != 0;
}
\ No newline at end of file
