Adding ro.soc.model support to cpuinfo to detect Qualcomm SM8850 SoC (#381)
* Adding ro.soc.model support to cpuinfo to detect Qualcomm SM8850 SoC.
* style: format src/riscv/linux/riscv-hw.c with clang-format
diff --git a/src/arm/android/api.h b/src/arm/android/api.h
index 48ef142..51cc822 100644
--- a/src/arm/android/api.h
+++ b/src/arm/android/api.h
@@ -13,6 +13,7 @@
cpuinfo_android_chipset_property_ro_arch,
cpuinfo_android_chipset_property_ro_chipname,
cpuinfo_android_chipset_property_ro_hardware_chipname,
+ cpuinfo_android_chipset_property_ro_soc_model,
cpuinfo_android_chipset_property_max,
};
diff --git a/src/arm/android/properties.c b/src/arm/android/properties.c
index 51a2def..2da3fd0 100644
--- a/src/arm/android/properties.c
+++ b/src/arm/android/properties.c
@@ -63,4 +63,7 @@
cpuinfo_android_property_get("ro.hardware.chipname", properties->ro_hardware_chipname);
cpuinfo_log_debug(
"read ro.hardware.chipname = \"%.*s\"", ro_hardware_chipname_length, properties->ro_hardware_chipname);
+
+ const int ro_soc_model_length = cpuinfo_android_property_get("ro.soc.model", properties->ro_soc_model);
+ cpuinfo_log_debug("read ro.soc.model = \"%.*s\"", ro_soc_model_length, properties->ro_soc_model);
}
diff --git a/src/arm/api.h b/src/arm/api.h
index 32a271c..cfb99ff 100644
--- a/src/arm/api.h
+++ b/src/arm/api.h
@@ -45,6 +45,7 @@
cpuinfo_arm_chipset_series_qualcomm_msm,
cpuinfo_arm_chipset_series_qualcomm_apq,
cpuinfo_arm_chipset_series_qualcomm_snapdragon,
+ cpuinfo_arm_chipset_series_qualcomm_sm,
cpuinfo_arm_chipset_series_mediatek_mt,
cpuinfo_arm_chipset_series_samsung_exynos,
cpuinfo_arm_chipset_series_hisilicon_k3v,
diff --git a/src/arm/linux/api.h b/src/arm/linux/api.h
index 14fed7c..453b1e9 100644
--- a/src/arm/linux/api.h
+++ b/src/arm/linux/api.h
@@ -29,6 +29,7 @@
char ro_arch[CPUINFO_BUILD_PROP_VALUE_MAX];
char ro_chipname[CPUINFO_BUILD_PROP_VALUE_MAX];
char ro_hardware_chipname[CPUINFO_BUILD_PROP_VALUE_MAX];
+ char ro_soc_model[CPUINFO_BUILD_PROP_VALUE_MAX];
};
#endif
@@ -364,6 +365,8 @@
const char ro_chipname[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]);
CPUINFO_INTERNAL struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_hardware_chipname(
const char ro_hardware_chipname[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]);
+CPUINFO_INTERNAL struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_soc_model(
+ const char ro_soc_model[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]);
#else
CPUINFO_INTERNAL struct cpuinfo_arm_chipset cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_revision(
const char proc_cpuinfo_revision[restrict static CPUINFO_REVISION_VALUE_MAX]);
diff --git a/src/arm/linux/chipset.c b/src/arm/linux/chipset.c
index 93de535..0a03642 100644
--- a/src/arm/linux/chipset.c
+++ b/src/arm/linux/chipset.c
@@ -264,7 +264,7 @@
/* Return parsed chipset. */
*chipset = (struct cpuinfo_arm_chipset){
.vendor = cpuinfo_arm_chipset_vendor_qualcomm,
- .series = cpuinfo_arm_chipset_series_qualcomm_snapdragon,
+ .series = cpuinfo_arm_chipset_series_qualcomm_sm,
.model = model,
};
return true;
@@ -3491,6 +3491,36 @@
.series = cpuinfo_arm_chipset_series_unknown,
};
}
+
+struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_soc_model(
+ const char soc_model[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]) {
+ struct cpuinfo_arm_chipset chipset;
+ const size_t soc_model_length = strnlen(soc_model, CPUINFO_BUILD_PROP_VALUE_MAX);
+ const char* soc_model_end = soc_model + soc_model_length;
+
+ /* Check Qualcomm SMxxxx signature */
+ if (match_sm(soc_model, soc_model_end, &chipset)) {
+ cpuinfo_log_debug(
+ "matched Qualcomm SM signature in ro.soc.model string \"%.*s\"",
+ (int)soc_model_length,
+ soc_model);
+ return chipset;
+ }
+
+ /* Check Qualcomm MSM/APQ signatures */
+ if (match_msm_apq(soc_model, soc_model_end, &chipset)) {
+ cpuinfo_log_debug(
+ "matched Qualcomm MSM/APQ signature in ro.soc.model string \"%.*s\"",
+ (int)soc_model_length,
+ soc_model);
+ return chipset;
+ }
+
+ return (struct cpuinfo_arm_chipset){
+ .vendor = cpuinfo_arm_chipset_vendor_unknown,
+ .series = cpuinfo_arm_chipset_series_unknown,
+ };
+}
#endif /* __ANDROID__ */
/*
@@ -3837,6 +3867,7 @@
[cpuinfo_arm_chipset_series_qualcomm_msm] = "MSM",
[cpuinfo_arm_chipset_series_qualcomm_apq] = "APQ",
[cpuinfo_arm_chipset_series_qualcomm_snapdragon] = "Snapdragon ",
+ [cpuinfo_arm_chipset_series_qualcomm_sm] = "SM",
[cpuinfo_arm_chipset_series_mediatek_mt] = "MT",
[cpuinfo_arm_chipset_series_samsung_exynos] = "Exynos ",
[cpuinfo_arm_chipset_series_hisilicon_k3v] = "K3V",
@@ -4074,6 +4105,8 @@
cpuinfo_arm_android_decode_chipset_from_ro_chipname(properties->ro_chipname),
[cpuinfo_android_chipset_property_ro_hardware_chipname] =
cpuinfo_arm_android_decode_chipset_from_ro_chipname(properties->ro_hardware_chipname),
+ [cpuinfo_android_chipset_property_ro_soc_model] =
+ cpuinfo_arm_android_decode_chipset_from_ro_soc_model(properties->ro_soc_model),
};
enum cpuinfo_arm_chipset_vendor vendor = cpuinfo_arm_chipset_vendor_unknown;
for (size_t i = 0; i < cpuinfo_android_chipset_property_max; i++) {
diff --git a/src/riscv/linux/riscv-hw.c b/src/riscv/linux/riscv-hw.c
index f820086..f67dc46 100644
--- a/src/riscv/linux/riscv-hw.c
+++ b/src/riscv/linux/riscv-hw.c
@@ -53,30 +53,30 @@
#define RISCV_HWPROBE_EXT_ZBB (1 << 4)
#define RISCV_HWPROBE_EXT_ZBS (1 << 5)
#define RISCV_HWPROBE_EXT_ZICBOZ (1 << 6)
-#define RISCV_HWPROBE_EXT_ZBC (1 << 7)
-#define RISCV_HWPROBE_EXT_ZBKB (1 << 8)
-#define RISCV_HWPROBE_EXT_ZBKC (1 << 9)
-#define RISCV_HWPROBE_EXT_ZBKX (1 << 10)
-#define RISCV_HWPROBE_EXT_ZKND (1 << 11)
-#define RISCV_HWPROBE_EXT_ZKNE (1 << 12)
-#define RISCV_HWPROBE_EXT_ZKNH (1 << 13)
-#define RISCV_HWPROBE_EXT_ZKSED (1 << 14)
-#define RISCV_HWPROBE_EXT_ZKSH (1 << 15)
-#define RISCV_HWPROBE_EXT_ZKT (1 << 16)
-#define RISCV_HWPROBE_EXT_ZVBB (1 << 17)
-#define RISCV_HWPROBE_EXT_ZVBC (1 << 18)
-#define RISCV_HWPROBE_EXT_ZVKB (1 << 19)
-#define RISCV_HWPROBE_EXT_ZVKG (1 << 20)
-#define RISCV_HWPROBE_EXT_ZVKNED (1 << 21)
-#define RISCV_HWPROBE_EXT_ZVKNHA (1 << 22)
-#define RISCV_HWPROBE_EXT_ZVKNHB (1 << 23)
-#define RISCV_HWPROBE_EXT_ZVKSED (1 << 24)
-#define RISCV_HWPROBE_EXT_ZVKSH (1 << 25)
-#define RISCV_HWPROBE_EXT_ZVKT (1 << 26)
-#define RISCV_HWPROBE_EXT_ZFH (1 << 27)
-#define RISCV_HWPROBE_EXT_ZFHMIN (1 << 28)
-#define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 29)
-#define RISCV_HWPROBE_EXT_ZVFH (1 << 30)
+#define RISCV_HWPROBE_EXT_ZBC (1 << 7)
+#define RISCV_HWPROBE_EXT_ZBKB (1 << 8)
+#define RISCV_HWPROBE_EXT_ZBKC (1 << 9)
+#define RISCV_HWPROBE_EXT_ZBKX (1 << 10)
+#define RISCV_HWPROBE_EXT_ZKND (1 << 11)
+#define RISCV_HWPROBE_EXT_ZKNE (1 << 12)
+#define RISCV_HWPROBE_EXT_ZKNH (1 << 13)
+#define RISCV_HWPROBE_EXT_ZKSED (1 << 14)
+#define RISCV_HWPROBE_EXT_ZKSH (1 << 15)
+#define RISCV_HWPROBE_EXT_ZKT (1 << 16)
+#define RISCV_HWPROBE_EXT_ZVBB (1 << 17)
+#define RISCV_HWPROBE_EXT_ZVBC (1 << 18)
+#define RISCV_HWPROBE_EXT_ZVKB (1 << 19)
+#define RISCV_HWPROBE_EXT_ZVKG (1 << 20)
+#define RISCV_HWPROBE_EXT_ZVKNED (1 << 21)
+#define RISCV_HWPROBE_EXT_ZVKNHA (1 << 22)
+#define RISCV_HWPROBE_EXT_ZVKNHB (1 << 23)
+#define RISCV_HWPROBE_EXT_ZVKSED (1 << 24)
+#define RISCV_HWPROBE_EXT_ZVKSH (1 << 25)
+#define RISCV_HWPROBE_EXT_ZVKT (1 << 26)
+#define RISCV_HWPROBE_EXT_ZFH (1 << 27)
+#define RISCV_HWPROBE_EXT_ZFHMIN (1 << 28)
+#define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 29)
+#define RISCV_HWPROBE_EXT_ZVFH (1 << 30)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
