Report correct L2 cache size on ARM (Neoverse V1/V2) (#372)

By fetching the values from `/sys/devices/system/cpu/cpuN/cache/indexM/{size,level,type,...}`, that is populate via 
https://github.com/torvalds/linux/blob/master/arch/arm64/kernel/cacheinfo.c
and
https://github.com/torvalds/linux/blob/master/drivers/acpi/pptt.c

Fixes #369 

Tested on Arm Neoverse V1 and V2 EC2 instances. I reused the reproducer in #369 

```
#include <cstddef>
#include <cstdio>
#include <cpuinfo.h>
size_t l2_bytes() {
  if (!cpuinfo_initialize()) return 0;
  const cpuinfo_processor* p = cpuinfo_get_current_processor();
  if (!p || !p->cache.l2) return 0;
  return p->cache.l2->size; // bytes
}
int main() { std::printf("%zu\n", l2_bytes()); }
```

This now returns the expected results on Arm Neoverse V1 and V2
___

Additionally, here is the output of `./cache-info`.
1. On Neoverse-V1:
```
Max cache size (upper bound): 4194304 bytes
L1 instruction cache: 64 x 64 KB, 4-way set associative (256 sets), 64 byte lines, shared by 1 processors
L1 data cache: 64 x 64 KB, 4-way set associative (256 sets), 64 byte lines, shared by 1 processors
L2 data cache: 64 x 1 MB (inclusive), 8-way set associative (2048 sets), 64 byte lines, shared by 1 processors
```
2. On Neoverse-V2:
```
Max cache size (upper bound): 4194304 bytes
L1 instruction cache: 64 x 64 KB, 4-way set associative (256 sets), 64 byte lines, shared by 1 processors
L1 data cache: 64 x 64 KB, 4-way set associative (256 sets), 64 byte lines, shared by 1 processors
L2 data cache: 64 x 2 MB (inclusive), 8-way set associative (4096 sets), 64 byte lines, shared by 1 processors
```