src/probe.pio

/*
 * The MIT License (MIT)
 *
 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 *
 */

.program probe
.side_set 1 opt

public out_negedge:
    set pindirs, 1 side 0x0 ; Init OE clock 0
    pull           ; Pull number of bits to shift -1 from tx fifo and put into output shift register
    mov x, osr     ; mov bits to shift -1 from output shift register into x
    pull           ; Pull data to shift out
out_negedge_bitloop:
    out pins, 1                  side 0x0 ; clock data out on falling edge
    jmp  x-- out_negedge_bitloop side 0x1 ; data is present for posedge
    set pins, 1                  side 0x0 ; Drive data high (idle bus state)
    push                                 ; Push to rx fifo just so processor knows when done
    jmp out_negedge                      ; Wait for next transaction

public in_posedge:
    set pindirs, 0 side 0x0 ; INIT IE clock 0
    pull                   ; Pull number of bits to shift -1 from tx fifo and put into output shift register
    mov x, osr             ; mov bits to shift -1 from output shift register into x into x
in_posedge_bitloop:
    in pins, 1                        side 0x1 ; Generate posedge and read data
    jmp x-- in_posedge_bitloop        side 0x0 ;
    push                                      ; Push to rx fifo when done
    jmp in_posedge                            ; Jump back to start