add pio_set_input_sync_bypass_with_mask and pio_set_input_sync_bypass_with_mask64 (#3024)

* add pio_sm_set_input_sync_bypass_with_mask and pio_sm_set_input_sync_bypass_with_mask64

* revert changes to check_pio_pin_mask* as they are part of public API; albeit the sm parameter is pretty meaniingless

* bypass_values -> bypass_enables

* Fix function names

And use the new function in the cyw43 pio implementation.

* Second attempt at fixing the new function names

Lose the "sm"?

---------

Co-authored-by: Peter Harper <peter.harper@raspberrypi.com>

src/rp2_common/hardware_pio/include/hardware/pio.h

diff --git a/src/rp2_common/hardware_pio/include/hardware/pio.h b/src/rp2_common/hardware_pio/include/hardware/pio.h
index 6ce52fe..2e1b0df 100644
--- a/src/rp2_common/hardware_pio/include/hardware/pio.h
+++ b/src/rp2_common/hardware_pio/include/hardware/pio.h
@@ -2008,6 +2008,24 @@
  */
 int pio_sm_set_consecutive_pindirs(PIO pio, uint sm, uint pins_base, uint pin_count, bool is_out);
 
+/*! \brief Enable/disable the input synchronizer bypass for multiple pins for the PIO instance
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; e.g. \ref pio0, \ref pio1 etc.
+ * \param bypass_enables the values to set - 1 = enable bypass, 0 = disable bypass (if the corresponding bit in pin_mask is set)
+ * \param pin_mask a bit for each pin to indicate whether the corresponding bypass enable bit for that pin should be updated.
+ */
+void pio_set_input_sync_bypass_with_mask(PIO pio, uint32_t bypass_enables, uint32_t pin_mask);
+
+/*! \brief Enable/disable the input synchronizer bypass for multiple pins for the PIO instance
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; e.g. \ref pio0, \ref pio1 etc.
+ * \param bypass_enables the values to set - 1 = enable bypass, 0 = disable bypass (if the corresponding bit in pin_mask is set)
+ * \param pin_mask a bit for each pin to indicate whether the corresponding bypass enable bit for that pin should be updated.
+ */
+void pio_set_input_sync_bypass_with_mask64(PIO pio, uint64_t bypass_enables, uint64_t pin_mask);
+
 /*! \brief Mark a state machine as used
  *  \ingroup hardware_pio
  *

src/rp2_common/hardware_pio/pio.c

diff --git a/src/rp2_common/hardware_pio/pio.c b/src/rp2_common/hardware_pio/pio.c
index 10698ea..25530cd 100644
--- a/src/rp2_common/hardware_pio/pio.c
+++ b/src/rp2_common/hardware_pio/pio.c
@@ -212,6 +212,7 @@
 #define pio_sm_set_pins_internal pio_sm_set_pins
 #define pio_sm_set_pins_with_mask_internal pio_sm_set_pins_with_mask
 #define pio_sm_set_pindirs_with_mask_internal pio_sm_set_pindirs_with_mask
+#define pio_set_input_sync_bypass_with_mask_internal pio_set_input_sync_bypass_with_mask
 #endif
 
 // Set the value of all PIO pins. This is done by forcibly executing
@@ -341,6 +342,33 @@
     pio_sm_set_pindirs_with_mask_internal(pio, sm, (uint32_t)pindirs, (uint32_t)pin_mask);
 }
 
+void pio_set_input_sync_bypass_with_mask_internal(PIO pio, uint32_t bypass_enables, uint32_t pin_mask) {
+    check_pio_param(pio);
+    hw_xor_bits(&pio->input_sync_bypass, (pio->input_sync_bypass ^ bypass_enables) & pin_mask);
+}
+
+#ifndef pio_set_input_sync_bypass_with_mask_internal
+void pio_set_input_sync_bypass_with_mask(PIO pio, uint32_t bypass_enables, uint32_t pin_mask) {
+    check_pio_pin_mask(pio,0, pin_mask);
+#if PICO_PIO_USE_GPIO_BASE
+    uint gpio_base = pio_get_gpio_base(pio);
+    bypass_enables >>= gpio_base;
+    pin_mask >>= gpio_base;
+#endif
+    pio_set_input_sync_bypass_with_mask_internal(pio, bypass_enables, pin_mask);
+}
+#endif
+
+void pio_set_input_sync_bypass_with_mask64(PIO pio, uint64_t bypass_enables, uint64_t pin_mask) {
+    check_pio_pin_mask64(pio, 0, pin_mask);
+#if PICO_PIO_USE_GPIO_BASE
+    uint gpio_base = pio_get_gpio_base(pio);
+    bypass_enables >>= gpio_base;
+    pin_mask >>= gpio_base;
+#endif
+    pio_set_input_sync_bypass_with_mask_internal(pio, (uint32_t)bypass_enables, (uint32_t)pin_mask);
+}
+
 int pio_sm_set_consecutive_pindirs(PIO pio, uint sm, uint pin, uint count, bool is_out) {
     check_pio_param(pio);
     check_sm_param(sm);

src/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.c

diff --git a/src/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.c b/src/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.c
index 06d5bef..a8743fd 100644
--- a/src/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.c
+++ b/src/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.c
@@ -139,7 +139,7 @@
     sm_config_set_sideset_pins(&config, CYW43_PIN_WL_CLOCK);
     sm_config_set_in_shift(&config, false, true, 32);
     sm_config_set_out_shift(&config, false, true, 32);
-    hw_set_bits(&bus_data->pio->input_sync_bypass, 1u << (CYW43_PIN_WL_DATA_IN - pio_get_gpio_base(bus_data->pio)));
+    pio_set_input_sync_bypass_with_mask64(bus_data->pio, 1ull << CYW43_PIN_WL_DATA_IN, 1ull << CYW43_PIN_WL_DATA_IN);
     pio_sm_set_config(bus_data->pio, bus_data->pio_sm, &config);
     pio_sm_set_consecutive_pindirs(bus_data->pio, bus_data->pio_sm, CYW43_PIN_WL_CLOCK, 1, true);
     gpio_set_function(CYW43_PIN_WL_DATA_OUT, pio_get_funcsel(bus_data->pio));