Update to latest generated headers
diff --git a/src/rp2040/hardware_regs/RP2040.svd b/src/rp2040/hardware_regs/RP2040.svd index 785a90b..d61a3a8 100644 --- a/src/rp2040/hardware_regs/RP2040.svd +++ b/src/rp2040/hardware_regs/RP2040.svd
@@ -48,17 +48,13 @@ <peripherals> <peripheral> <name>ADC</name> - <description>Control and data interface to SAR ADC</description> <baseAddress>0x4004c000</baseAddress> + <description>Control and data interface to SAR ADC</description> <addressBlock> <offset>0</offset> <size>36</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>ADC_IRQ_FIFO</name> - <value>22</value> - </interrupt> <registers> <register> <name>CS</name> @@ -112,6 +108,7 @@ <description>Start a single conversion. Self-clearing. Ignored if start_many is asserted.</description> <bitRange>[2:2]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>TS_EN</name> @@ -314,11 +311,15 @@ </fields> </register> </registers> + <interrupt> + <name>ADC_IRQ_FIFO</name> + <value>22</value> + </interrupt> </peripheral> <peripheral> <name>BUSCTRL</name> - <description>Register block for busfabric control signals and performance counters</description> <baseAddress>0x40030000</baseAddress> + <description>Register block for busfabric control signals and performance counters</description> <addressBlock> <offset>0</offset> <size>40</size> @@ -835,10 +836,6 @@ <size>200</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>CLOCKS_IRQ</name> - <value>17</value> - </interrupt> <registers> <register> <name>CLK_GPOUT0_CTRL</name> @@ -1567,26 +1564,6 @@ </fields> </register> <register> - <name>CLK_PERI_DIV</name> - <addressOffset>0x0000004c</addressOffset> - <description>Clock divisor, can be changed on-the-fly</description> - <resetValue>0x00000100</resetValue> - <fields> - <field> - <name>INT</name> - <description>Integer component of the divisor, 0 -> divide by 2^16</description> - <bitRange>[31:8]</bitRange> - <access>read-write</access> - </field> - <field> - <name>FRAC</name> - <description>Fractional component of the divisor</description> - <bitRange>[7:0]</bitRange> - <access>read-write</access> - </field> - </fields> - </register> - <register> <name>CLK_PERI_SELECTED</name> <addressOffset>0x00000050</addressOffset> <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).</description> @@ -2952,24 +2929,20 @@ </fields> </register> </registers> + <interrupt> + <name>CLOCKS_IRQ</name> + <value>17</value> + </interrupt> </peripheral> <peripheral> <name>DMA</name> - <description>DMA with separate read and write masters</description> <baseAddress>0x50000000</baseAddress> + <description>DMA with separate read and write masters</description> <addressBlock> <offset>0</offset> <size>2760</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>DMA_IRQ_0</name> - <value>11</value> - </interrupt> - <interrupt> - <name>DMA_IRQ_1</name> - <value>12</value> - </interrupt> <registers> <register> <name>CH0_READ_ADDR</name> @@ -3087,6 +3060,31 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>TIMER0</name> + <value>59</value> + <description>Select Timer 0 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER1</name> + <value>60</value> + <description>Select Timer 1 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER2</name> + <value>61</value> + <description>Select Timer 2 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER3</name> + <value>62</value> + <description>Select Timer 3 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>PERMANENT</name> + <value>63</value> + <description>Permanent request, for unpaced transfers.</description> + </enumeratedValue> + <enumeratedValue> <name>PIO0_TX0</name> <value>0</value> <description>Select PIO0's TX FIFO 0 as TREQ</description> @@ -3286,31 +3284,6 @@ <value>39</value> <description>Select the XIP SSI RX FIFO as TREQ</description> </enumeratedValue> - <enumeratedValue> - <name>TIMER0</name> - <value>59</value> - <description>Select Timer 0 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER1</name> - <value>60</value> - <description>Select Timer 1 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER2</name> - <value>61</value> - <description>Select Timer 2 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER3</name> - <value>62</value> - <description>Select Timer 3 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>PERMANENT</name> - <value>63</value> - <description>Permanent request, for unpaced transfers.</description> - </enumeratedValue> </enumeratedValues> </field> <field> @@ -3671,6 +3644,31 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>TIMER0</name> + <value>59</value> + <description>Select Timer 0 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER1</name> + <value>60</value> + <description>Select Timer 1 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER2</name> + <value>61</value> + <description>Select Timer 2 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER3</name> + <value>62</value> + <description>Select Timer 3 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>PERMANENT</name> + <value>63</value> + <description>Permanent request, for unpaced transfers.</description> + </enumeratedValue> + <enumeratedValue> <name>PIO0_TX0</name> <value>0</value> <description>Select PIO0's TX FIFO 0 as TREQ</description> @@ -3870,31 +3868,6 @@ <value>39</value> <description>Select the XIP SSI RX FIFO as TREQ</description> </enumeratedValue> - <enumeratedValue> - <name>TIMER0</name> - <value>59</value> - <description>Select Timer 0 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER1</name> - <value>60</value> - <description>Select Timer 1 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER2</name> - <value>61</value> - <description>Select Timer 2 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER3</name> - <value>62</value> - <description>Select Timer 3 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>PERMANENT</name> - <value>63</value> - <description>Permanent request, for unpaced transfers.</description> - </enumeratedValue> </enumeratedValues> </field> <field> @@ -4255,6 +4228,31 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>TIMER0</name> + <value>59</value> + <description>Select Timer 0 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER1</name> + <value>60</value> + <description>Select Timer 1 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER2</name> + <value>61</value> + <description>Select Timer 2 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER3</name> + <value>62</value> + <description>Select Timer 3 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>PERMANENT</name> + <value>63</value> + <description>Permanent request, for unpaced transfers.</description> + </enumeratedValue> + <enumeratedValue> <name>PIO0_TX0</name> <value>0</value> <description>Select PIO0's TX FIFO 0 as TREQ</description> @@ -4454,31 +4452,6 @@ <value>39</value> <description>Select the XIP SSI RX FIFO as TREQ</description> </enumeratedValue> - <enumeratedValue> - <name>TIMER0</name> - <value>59</value> - <description>Select Timer 0 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER1</name> - <value>60</value> - <description>Select Timer 1 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER2</name> - <value>61</value> - <description>Select Timer 2 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER3</name> - <value>62</value> - <description>Select Timer 3 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>PERMANENT</name> - <value>63</value> - <description>Permanent request, for unpaced transfers.</description> - </enumeratedValue> </enumeratedValues> </field> <field> @@ -4839,6 +4812,31 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>TIMER0</name> + <value>59</value> + <description>Select Timer 0 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER1</name> + <value>60</value> + <description>Select Timer 1 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER2</name> + <value>61</value> + <description>Select Timer 2 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER3</name> + <value>62</value> + <description>Select Timer 3 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>PERMANENT</name> + <value>63</value> + <description>Permanent request, for unpaced transfers.</description> + </enumeratedValue> + <enumeratedValue> <name>PIO0_TX0</name> <value>0</value> <description>Select PIO0's TX FIFO 0 as TREQ</description> @@ -5038,31 +5036,6 @@ <value>39</value> <description>Select the XIP SSI RX FIFO as TREQ</description> </enumeratedValue> - <enumeratedValue> - <name>TIMER0</name> - <value>59</value> - <description>Select Timer 0 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER1</name> - <value>60</value> - <description>Select Timer 1 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER2</name> - <value>61</value> - <description>Select Timer 2 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER3</name> - <value>62</value> - <description>Select Timer 3 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>PERMANENT</name> - <value>63</value> - <description>Permanent request, for unpaced transfers.</description> - </enumeratedValue> </enumeratedValues> </field> <field> @@ -5423,6 +5396,31 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>TIMER0</name> + <value>59</value> + <description>Select Timer 0 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER1</name> + <value>60</value> + <description>Select Timer 1 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER2</name> + <value>61</value> + <description>Select Timer 2 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER3</name> + <value>62</value> + <description>Select Timer 3 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>PERMANENT</name> + <value>63</value> + <description>Permanent request, for unpaced transfers.</description> + </enumeratedValue> + <enumeratedValue> <name>PIO0_TX0</name> <value>0</value> <description>Select PIO0's TX FIFO 0 as TREQ</description> @@ -5622,31 +5620,6 @@ <value>39</value> <description>Select the XIP SSI RX FIFO as TREQ</description> </enumeratedValue> - <enumeratedValue> - <name>TIMER0</name> - <value>59</value> - <description>Select Timer 0 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER1</name> - <value>60</value> - <description>Select Timer 1 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER2</name> - <value>61</value> - <description>Select Timer 2 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER3</name> - <value>62</value> - <description>Select Timer 3 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>PERMANENT</name> - <value>63</value> - <description>Permanent request, for unpaced transfers.</description> - </enumeratedValue> </enumeratedValues> </field> <field> @@ -6007,6 +5980,31 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>TIMER0</name> + <value>59</value> + <description>Select Timer 0 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER1</name> + <value>60</value> + <description>Select Timer 1 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER2</name> + <value>61</value> + <description>Select Timer 2 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER3</name> + <value>62</value> + <description>Select Timer 3 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>PERMANENT</name> + <value>63</value> + <description>Permanent request, for unpaced transfers.</description> + </enumeratedValue> + <enumeratedValue> <name>PIO0_TX0</name> <value>0</value> <description>Select PIO0's TX FIFO 0 as TREQ</description> @@ -6206,31 +6204,6 @@ <value>39</value> <description>Select the XIP SSI RX FIFO as TREQ</description> </enumeratedValue> - <enumeratedValue> - <name>TIMER0</name> - <value>59</value> - <description>Select Timer 0 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER1</name> - <value>60</value> - <description>Select Timer 1 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER2</name> - <value>61</value> - <description>Select Timer 2 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER3</name> - <value>62</value> - <description>Select Timer 3 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>PERMANENT</name> - <value>63</value> - <description>Permanent request, for unpaced transfers.</description> - </enumeratedValue> </enumeratedValues> </field> <field> @@ -6591,6 +6564,31 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>TIMER0</name> + <value>59</value> + <description>Select Timer 0 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER1</name> + <value>60</value> + <description>Select Timer 1 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER2</name> + <value>61</value> + <description>Select Timer 2 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER3</name> + <value>62</value> + <description>Select Timer 3 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>PERMANENT</name> + <value>63</value> + <description>Permanent request, for unpaced transfers.</description> + </enumeratedValue> + <enumeratedValue> <name>PIO0_TX0</name> <value>0</value> <description>Select PIO0's TX FIFO 0 as TREQ</description> @@ -6790,31 +6788,6 @@ <value>39</value> <description>Select the XIP SSI RX FIFO as TREQ</description> </enumeratedValue> - <enumeratedValue> - <name>TIMER0</name> - <value>59</value> - <description>Select Timer 0 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER1</name> - <value>60</value> - <description>Select Timer 1 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER2</name> - <value>61</value> - <description>Select Timer 2 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER3</name> - <value>62</value> - <description>Select Timer 3 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>PERMANENT</name> - <value>63</value> - <description>Permanent request, for unpaced transfers.</description> - </enumeratedValue> </enumeratedValues> </field> <field> @@ -7175,6 +7148,31 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>TIMER0</name> + <value>59</value> + <description>Select Timer 0 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER1</name> + <value>60</value> + <description>Select Timer 1 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER2</name> + <value>61</value> + <description>Select Timer 2 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER3</name> + <value>62</value> + <description>Select Timer 3 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>PERMANENT</name> + <value>63</value> + <description>Permanent request, for unpaced transfers.</description> + </enumeratedValue> + <enumeratedValue> <name>PIO0_TX0</name> <value>0</value> <description>Select PIO0's TX FIFO 0 as TREQ</description> @@ -7374,31 +7372,6 @@ <value>39</value> <description>Select the XIP SSI RX FIFO as TREQ</description> </enumeratedValue> - <enumeratedValue> - <name>TIMER0</name> - <value>59</value> - <description>Select Timer 0 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER1</name> - <value>60</value> - <description>Select Timer 1 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER2</name> - <value>61</value> - <description>Select Timer 2 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER3</name> - <value>62</value> - <description>Select Timer 3 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>PERMANENT</name> - <value>63</value> - <description>Permanent request, for unpaced transfers.</description> - </enumeratedValue> </enumeratedValues> </field> <field> @@ -7759,6 +7732,31 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>TIMER0</name> + <value>59</value> + <description>Select Timer 0 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER1</name> + <value>60</value> + <description>Select Timer 1 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER2</name> + <value>61</value> + <description>Select Timer 2 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER3</name> + <value>62</value> + <description>Select Timer 3 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>PERMANENT</name> + <value>63</value> + <description>Permanent request, for unpaced transfers.</description> + </enumeratedValue> + <enumeratedValue> <name>PIO0_TX0</name> <value>0</value> <description>Select PIO0's TX FIFO 0 as TREQ</description> @@ -7958,31 +7956,6 @@ <value>39</value> <description>Select the XIP SSI RX FIFO as TREQ</description> </enumeratedValue> - <enumeratedValue> - <name>TIMER0</name> - <value>59</value> - <description>Select Timer 0 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER1</name> - <value>60</value> - <description>Select Timer 1 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER2</name> - <value>61</value> - <description>Select Timer 2 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER3</name> - <value>62</value> - <description>Select Timer 3 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>PERMANENT</name> - <value>63</value> - <description>Permanent request, for unpaced transfers.</description> - </enumeratedValue> </enumeratedValues> </field> <field> @@ -8343,6 +8316,31 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>TIMER0</name> + <value>59</value> + <description>Select Timer 0 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER1</name> + <value>60</value> + <description>Select Timer 1 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER2</name> + <value>61</value> + <description>Select Timer 2 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER3</name> + <value>62</value> + <description>Select Timer 3 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>PERMANENT</name> + <value>63</value> + <description>Permanent request, for unpaced transfers.</description> + </enumeratedValue> + <enumeratedValue> <name>PIO0_TX0</name> <value>0</value> <description>Select PIO0's TX FIFO 0 as TREQ</description> @@ -8542,31 +8540,6 @@ <value>39</value> <description>Select the XIP SSI RX FIFO as TREQ</description> </enumeratedValue> - <enumeratedValue> - <name>TIMER0</name> - <value>59</value> - <description>Select Timer 0 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER1</name> - <value>60</value> - <description>Select Timer 1 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER2</name> - <value>61</value> - <description>Select Timer 2 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER3</name> - <value>62</value> - <description>Select Timer 3 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>PERMANENT</name> - <value>63</value> - <description>Permanent request, for unpaced transfers.</description> - </enumeratedValue> </enumeratedValues> </field> <field> @@ -8927,6 +8900,31 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>TIMER0</name> + <value>59</value> + <description>Select Timer 0 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER1</name> + <value>60</value> + <description>Select Timer 1 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER2</name> + <value>61</value> + <description>Select Timer 2 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER3</name> + <value>62</value> + <description>Select Timer 3 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>PERMANENT</name> + <value>63</value> + <description>Permanent request, for unpaced transfers.</description> + </enumeratedValue> + <enumeratedValue> <name>PIO0_TX0</name> <value>0</value> <description>Select PIO0's TX FIFO 0 as TREQ</description> @@ -9126,31 +9124,6 @@ <value>39</value> <description>Select the XIP SSI RX FIFO as TREQ</description> </enumeratedValue> - <enumeratedValue> - <name>TIMER0</name> - <value>59</value> - <description>Select Timer 0 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER1</name> - <value>60</value> - <description>Select Timer 1 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER2</name> - <value>61</value> - <description>Select Timer 2 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER3</name> - <value>62</value> - <description>Select Timer 3 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>PERMANENT</name> - <value>63</value> - <description>Permanent request, for unpaced transfers.</description> - </enumeratedValue> </enumeratedValues> </field> <field> @@ -9511,6 +9484,31 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>TIMER0</name> + <value>59</value> + <description>Select Timer 0 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER1</name> + <value>60</value> + <description>Select Timer 1 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER2</name> + <value>61</value> + <description>Select Timer 2 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER3</name> + <value>62</value> + <description>Select Timer 3 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>PERMANENT</name> + <value>63</value> + <description>Permanent request, for unpaced transfers.</description> + </enumeratedValue> + <enumeratedValue> <name>PIO0_TX0</name> <value>0</value> <description>Select PIO0's TX FIFO 0 as TREQ</description> @@ -9710,31 +9708,6 @@ <value>39</value> <description>Select the XIP SSI RX FIFO as TREQ</description> </enumeratedValue> - <enumeratedValue> - <name>TIMER0</name> - <value>59</value> - <description>Select Timer 0 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER1</name> - <value>60</value> - <description>Select Timer 1 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER2</name> - <value>61</value> - <description>Select Timer 2 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER3</name> - <value>62</value> - <description>Select Timer 3 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>PERMANENT</name> - <value>63</value> - <description>Permanent request, for unpaced transfers.</description> - </enumeratedValue> </enumeratedValues> </field> <field> @@ -10045,27 +10018,6 @@ </fields> </register> <register> - <name>INTR1</name> - <addressOffset>0x00000410</addressOffset> - <description>Interrupt Status (raw)</description> - <resetValue>0x00000000</resetValue> - <fields> - <field> - <name>INTR1</name> - <description>Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. - - Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. - - This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. - - It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0.</description> - <bitRange>[15:0]</bitRange> - <access>read-write</access> - <modifiedWriteValues>oneToClear</modifiedWriteValues> - </field> - </fields> - </register> - <register> <name>INTE1</name> <addressOffset>0x00000414</addressOffset> <description>Interrupt Enables for IRQ 1</description> @@ -10204,6 +10156,7 @@ <description>Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy.</description> <bitRange>[15:0]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> </fields> </register> @@ -10679,9 +10632,18 @@ </fields> </register> </registers> + <interrupt> + <name>DMA_IRQ_0</name> + <value>11</value> + </interrupt> + <interrupt> + <name>DMA_IRQ_1</name> + <value>12</value> + </interrupt> </peripheral> <peripheral> <name>I2C0</name> + <baseAddress>0x40044000</baseAddress> <description>DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): @@ -10754,16 +10716,11 @@ IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 IC_DEFAULT_UFM_SPKLEN ............. 0x1 IC_TX_BUFFER_DEPTH ................ 16</description> - <baseAddress>0x40044000</baseAddress> <addressBlock> <offset>0</offset> <size>256</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>I2C0_IRQ</name> - <value>23</value> - </interrupt> <registers> <register> <name>IC_CON</name> @@ -11095,6 +11052,7 @@ Reset value: 0x0</description> <bitRange>[10:10]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> <name>DISABLE</name> @@ -11115,6 +11073,7 @@ - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0</description> <bitRange>[9:9]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> <name>DISABLE</name> @@ -11139,6 +11098,7 @@ Reset value: 0x0</description> <bitRange>[8:8]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> <name>WRITE</name> @@ -13310,6 +13270,10 @@ </fields> </register> </registers> + <interrupt> + <name>I2C0_IRQ</name> + <value>23</value> + </interrupt> </peripheral> <peripheral derivedFrom="I2C0"> <name>I2C1</name> @@ -13327,10 +13291,6 @@ <size>400</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>IO_IRQ_BANK0</name> - <value>13</value> - </interrupt> <registers> <register> <name>GPIO0_STATUS</name> @@ -26307,6 +26267,10 @@ </fields> </register> </registers> + <interrupt> + <name>IO_IRQ_BANK0</name> + <value>13</value> + </interrupt> </peripheral> <peripheral> <name>IO_QSPI</name> @@ -26316,10 +26280,6 @@ <size>88</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>IO_IRQ_QSPI</name> - <value>14</value> - </interrupt> <registers> <register> <name>GPIO_QSPI_SCLK_STATUS</name> @@ -28772,6 +28732,10 @@ </fields> </register> </registers> + <interrupt> + <name>IO_IRQ_QSPI</name> + <value>14</value> + </interrupt> </peripheral> <peripheral> <name>PADS_BANK0</name> @@ -31431,21 +31395,13 @@ </peripheral> <peripheral> <name>PIO0</name> - <description>Programmable IO block</description> <baseAddress>0x50200000</baseAddress> + <description>Programmable IO block</description> <addressBlock> <offset>0</offset> <size>324</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>PIO0_IRQ_0</name> - <value>7</value> - </interrupt> - <interrupt> - <name>PIO0_IRQ_1</name> - <value>8</value> - </interrupt> <registers> <register> <name>CTRL</name> @@ -31462,6 +31418,7 @@ Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly.</description> <bitRange>[11:8]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>SM_RESTART</name> @@ -31472,6 +31429,7 @@ The program counter, the contents of the output shift register and the X/Y scratch registers are not affected.</description> <bitRange>[7:4]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>SM_ENABLE</name> @@ -33702,6 +33660,14 @@ </fields> </register> </registers> + <interrupt> + <name>PIO0_IRQ_0</name> + <value>7</value> + </interrupt> + <interrupt> + <name>PIO0_IRQ_1</name> + <value>8</value> + </interrupt> </peripheral> <peripheral derivedFrom="PIO0"> <name>PIO1</name> @@ -35103,17 +35069,13 @@ </peripheral> <peripheral> <name>PWM</name> - <description>Simple PWM</description> <baseAddress>0x40050000</baseAddress> + <description>Simple PWM</description> <addressBlock> <offset>0</offset> <size>180</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>PWM_IRQ_WRAP</name> - <value>4</value> - </interrupt> <registers> <register> <name>CH0_CSR</name> @@ -35127,14 +35089,16 @@ Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)</description> <bitRange>[7:7]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>PH_RET</name> <description>Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.</description> <bitRange>[6:6]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>DIVMODE</name> @@ -35265,14 +35229,16 @@ Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)</description> <bitRange>[7:7]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>PH_RET</name> <description>Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.</description> <bitRange>[6:6]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>DIVMODE</name> @@ -35403,14 +35369,16 @@ Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)</description> <bitRange>[7:7]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>PH_RET</name> <description>Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.</description> <bitRange>[6:6]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>DIVMODE</name> @@ -35541,14 +35509,16 @@ Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)</description> <bitRange>[7:7]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>PH_RET</name> <description>Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.</description> <bitRange>[6:6]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>DIVMODE</name> @@ -35679,14 +35649,16 @@ Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)</description> <bitRange>[7:7]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>PH_RET</name> <description>Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.</description> <bitRange>[6:6]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>DIVMODE</name> @@ -35817,14 +35789,16 @@ Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)</description> <bitRange>[7:7]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>PH_RET</name> <description>Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.</description> <bitRange>[6:6]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>DIVMODE</name> @@ -35955,14 +35929,16 @@ Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)</description> <bitRange>[7:7]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>PH_RET</name> <description>Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.</description> <bitRange>[6:6]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>DIVMODE</name> @@ -36093,14 +36069,16 @@ Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)</description> <bitRange>[7:7]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>PH_RET</name> <description>Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.</description> <bitRange>[6:6]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>DIVMODE</name> @@ -36472,6 +36450,10 @@ </fields> </register> </registers> + <interrupt> + <name>PWM_IRQ_WRAP</name> + <value>4</value> + </interrupt> </peripheral> <peripheral> <name>RESETS</name> @@ -37061,7 +37043,7 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>dormant</name> + <name>DORMANT</name> <value>1668246881</value> </enumeratedValue> <enumeratedValue> @@ -37200,17 +37182,13 @@ </peripheral> <peripheral> <name>RTC</name> - <description>Register block to control RTC</description> <baseAddress>0x4005c000</baseAddress> + <description>Register block to control RTC</description> <addressBlock> <offset>0</offset> <size>48</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>RTC_IRQ</name> - <value>25</value> - </interrupt> <registers> <register> <name>CLKDIV_M1</name> @@ -37301,6 +37279,7 @@ <description>Load RTC</description> <bitRange>[4:4]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>RTC_ACTIVE</name> @@ -37543,25 +37522,21 @@ </fields> </register> </registers> + <interrupt> + <name>RTC_IRQ</name> + <value>25</value> + </interrupt> </peripheral> <peripheral> <name>SIO</name> + <baseAddress>0xd0000000</baseAddress> <description>Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access.</description> - <baseAddress>0xd0000000</baseAddress> <addressBlock> <offset>0</offset> <size>384</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>SIO_IRQ_PROC0</name> - <value>15</value> - </interrupt> - <interrupt> - <name>SIO_IRQ_PROC1</name> - <value>16</value> - </interrupt> <registers> <register> <name>CPUID</name> @@ -39362,38 +39337,13 @@ </fields> </register> </registers> - </peripheral> - <peripheral> - <name>SPARE_IRQ</name> - <baseAddress>0x00000000</baseAddress> - <addressBlock> - <offset>0</offset> - <size>4</size> - <usage>reserved</usage> - </addressBlock> <interrupt> - <name>SPARE_IRQ_0</name> - <value>26</value> + <name>SIO_IRQ_PROC0</name> + <value>15</value> </interrupt> <interrupt> - <name>SPARE_IRQ_1</name> - <value>27</value> - </interrupt> - <interrupt> - <name>SPARE_IRQ_2</name> - <value>28</value> - </interrupt> - <interrupt> - <name>SPARE_IRQ_3</name> - <value>29</value> - </interrupt> - <interrupt> - <name>SPARE_IRQ_4</name> - <value>30</value> - </interrupt> - <interrupt> - <name>SPARE_IRQ_5</name> - <value>31</value> + <name>SIO_IRQ_PROC1</name> + <value>16</value> </interrupt> </peripheral> <peripheral> @@ -39404,10 +39354,6 @@ <size>4096</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>SPI0_IRQ</name> - <value>18</value> - </interrupt> <registers> <register> <name>SSPCR0</name> @@ -39809,6 +39755,10 @@ </fields> </register> </registers> + <interrupt> + <name>SPI0_IRQ</name> + <value>18</value> + </interrupt> </peripheral> <peripheral derivedFrom="SPI0"> <name>SPI1</name> @@ -39820,6 +39770,7 @@ </peripheral> <peripheral> <name>SSI</name> + <baseAddress>0x18000000</baseAddress> <description>DW_apb_ssi has the following features: * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation. * APB3 and APB4 protocol support. @@ -39846,7 +39797,6 @@ - Interrupt polarity – active high interrupt lines. - Serial clock polarity – low serial-clock polarity directly after reset. - Serial clock phase – capture on first edge of serial-clock directly after reset.</description> - <baseAddress>0x18000000</baseAddress> <addressBlock> <offset>0</offset> <size>252</size> @@ -40577,8 +40527,8 @@ </peripheral> <peripheral> <name>SYSCFG</name> - <description>Register block for various chip control signals</description> <baseAddress>0x40004000</baseAddress> + <description>Register block for various chip control signals</description> <addressBlock> <offset>0</offset> <size>28</size> @@ -40795,7 +40745,7 @@ <baseAddress>0x40000000</baseAddress> <addressBlock> <offset>0</offset> - <size>20</size> + <size>68</size> <usage>registers</usage> </addressBlock> <registers> @@ -40803,7 +40753,7 @@ <name>CHIP_ID</name> <addressOffset>0x00000000</addressOffset> <description>JEDEC JEP-106 compliant chip identifier.</description> - <resetValue>0x00000000</resetValue> + <resetValue>0x20002927</resetValue> <fields> <field> <name>REVISION</name> @@ -40842,7 +40792,7 @@ </register> <register> <name>GITREF_RP2040</name> - <addressOffset>0x00000010</addressOffset> + <addressOffset>0x00000040</addressOffset> <description>Git hash of the chip source. Used to identify chip version.</description> <resetMask>0x00000000</resetMask> <fields> @@ -40857,8 +40807,8 @@ </peripheral> <peripheral> <name>TBMAN</name> - <description>Testbench manager. Allows the programmer to know what platform their software is running on.</description> <baseAddress>0x4006c000</baseAddress> + <description>Testbench manager. Allows the programmer to know what platform their software is running on.</description> <addressBlock> <offset>0</offset> <size>4</size> @@ -40889,6 +40839,7 @@ </peripheral> <peripheral> <name>TIMER</name> + <baseAddress>0x40054000</baseAddress> <description>Controls time and alarms time is a 64 bit value indicating the time in usec since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits @@ -40899,28 +40850,11 @@ An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq</description> - <baseAddress>0x40054000</baseAddress> <addressBlock> <offset>0</offset> <size>68</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>TIMER_IRQ_0</name> - <value>0</value> - </interrupt> - <interrupt> - <name>TIMER_IRQ_1</name> - <value>1</value> - </interrupt> - <interrupt> - <name>TIMER_IRQ_2</name> - <value>2</value> - </interrupt> - <interrupt> - <name>TIMER_IRQ_3</name> - <value>3</value> - </interrupt> <registers> <register> <name>TIMEHW</name> @@ -41235,6 +41169,22 @@ </fields> </register> </registers> + <interrupt> + <name>TIMER_IRQ_0</name> + <value>0</value> + </interrupt> + <interrupt> + <name>TIMER_IRQ_1</name> + <value>1</value> + </interrupt> + <interrupt> + <name>TIMER_IRQ_2</name> + <value>2</value> + </interrupt> + <interrupt> + <name>TIMER_IRQ_3</name> + <value>3</value> + </interrupt> </peripheral> <peripheral> <name>UART0</name> @@ -41244,10 +41194,6 @@ <size>4096</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>UART0_IRQ</name> - <value>20</value> - </interrupt> <registers> <register> <name>UARTDR</name> @@ -42036,6 +41982,10 @@ </fields> </register> </registers> + <interrupt> + <name>UART0_IRQ</name> + <value>20</value> + </interrupt> </peripheral> <peripheral derivedFrom="UART0"> <name>UART1</name> @@ -42047,17 +41997,13 @@ </peripheral> <peripheral> <name>USB</name> - <description>USB FS/LS controller device registers</description> <baseAddress>0x50110000</baseAddress> + <description>USB FS/LS controller device registers</description> <addressBlock> <offset>0</offset> <size>156</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>USBCTRL_IRQ</name> - <value>5</value> - </interrupt> <registers> <register> <name>ADDR_ENDP</name> @@ -42694,12 +42640,14 @@ <description>Host: Reset bus</description> <bitRange>[13:13]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>RESUME</name> <description>Device: Remote wakeup. Device can initiate its own resume after suspend.</description> <bitRange>[12:12]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>VBUS_EN</name> @@ -42736,6 +42684,7 @@ <description>Host: Stop transaction</description> <bitRange>[4:4]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>RECEIVE_DATA</name> @@ -42760,6 +42709,7 @@ <description>Host: Start transaction</description> <bitRange>[0:0]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> </fields> </register> @@ -42866,7 +42816,8 @@ <name>CONNECTED</name> <description>Device: connected</description> <bitRange>[16:16]</bitRange> - <access>read-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>RESUME</name> @@ -42885,13 +42836,15 @@ <name>SPEED</name> <description>Host: device speed. Disconnected = 00, LS = 01, FS = 10</description> <bitRange>[9:8]</bitRange> - <access>read-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>SUSPENDED</name> <description>Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled.</description> <bitRange>[4:4]</bitRange> - <access>read-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>LINE_STATE</name> @@ -42915,7 +42868,7 @@ <fields> <field> <name>INT_EP_ACTIVE</name> - <description>Host: Enable interrupt endpoint 1 => 15</description> + <description>Host: Enable interrupt endpoint 1 -> 15</description> <bitRange>[15:1]</bitRange> <access>read-write</access> </field> @@ -43926,7 +43879,7 @@ <register> <name>USB_PWR</name> <addressOffset>0x00000078</addressOffset> - <description>Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable so switch over to the override value.</description> + <description>Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value.</description> <resetValue>0x00000000</resetValue> <fields> <field> @@ -43964,143 +43917,138 @@ <register> <name>USBPHY_DIRECT</name> <addressOffset>0x0000007c</addressOffset> - <description>Note that most functions are driven directly from usb_fsls controller. This register allows more detailed control/status from the USB PHY. Useful for debug but not expected to be used in normal operation - Use in conjunction with usbphy_direct_override register</description> + <description>This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit.</description> <resetValue>0x00000000</resetValue> <fields> <field> <name>DM_OVV</name> - <description>Status bit from USB PHY</description> + <description>DM over voltage</description> <bitRange>[22:22]</bitRange> <access>read-only</access> </field> <field> <name>DP_OVV</name> - <description>Status bit from USB PHY</description> + <description>DP over voltage</description> <bitRange>[21:21]</bitRange> <access>read-only</access> </field> <field> <name>DM_OVCN</name> - <description>Status bit from USB PHY</description> + <description>DM overcurrent</description> <bitRange>[20:20]</bitRange> <access>read-only</access> </field> <field> <name>DP_OVCN</name> - <description>Status bit from USB PHY</description> + <description>DP overcurrent</description> <bitRange>[19:19]</bitRange> <access>read-only</access> </field> <field> <name>RX_DM</name> - <description>Status bit from USB PHY - DPM pin state</description> + <description>DPM pin state</description> <bitRange>[18:18]</bitRange> <access>read-only</access> </field> <field> <name>RX_DP</name> - <description>Status bit from USB PHY - DPP pin state</description> + <description>DPP pin state</description> <bitRange>[17:17]</bitRange> <access>read-only</access> </field> <field> <name>RX_DD</name> - <description>Status bit from USB PHY - RX Diff data</description> + <description>Differential RX</description> <bitRange>[16:16]</bitRange> <access>read-only</access> </field> <field> <name>TX_DIFFMODE</name> + <description>TX_DIFFMODE=0: Single ended mode + TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)</description> <bitRange>[15:15]</bitRange> <access>read-write</access> </field> <field> <name>TX_FSSLEW</name> + <description>TX_FSSLEW=0: Low speed slew rate + TX_FSSLEW=1: Full speed slew rate</description> <bitRange>[14:14]</bitRange> <access>read-write</access> </field> <field> <name>TX_PD</name> + <description>TX power down override (if override enable is set). 1 = powered down.</description> <bitRange>[13:13]</bitRange> <access>read-write</access> </field> <field> <name>RX_PD</name> + <description>RX power down override (if override enable is set). 1 = powered down.</description> <bitRange>[12:12]</bitRange> <access>read-write</access> </field> <field> <name>TX_DM</name> - <description>Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller - TX_SEMODE=0, Ignored - TX_SEMODE=1, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM</description> + <description>Output data. TX_DIFFMODE=1, Ignored + TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM</description> <bitRange>[11:11]</bitRange> <access>read-write</access> </field> <field> <name>TX_DP</name> - <description>Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller - TX_SEMODE=0, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP - TX_SEMODE=1, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP</description> + <description>Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP + If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP</description> <bitRange>[10:10]</bitRange> <access>read-write</access> </field> <field> <name>TX_DM_OE</name> - <description>Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller - TX_SEMODE=0, Ignored. - TX_SEMODE=1, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving</description> + <description>Output enable. If TX_DIFFMODE=1, Ignored. + If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving</description> <bitRange>[9:9]</bitRange> <access>read-write</access> </field> <field> <name>TX_DP_OE</name> - <description>Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller - TX_SEMODE=0, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving - TX_SEMODE=1, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving</description> + <description>Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving + If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving</description> <bitRange>[8:8]</bitRange> <access>read-write</access> </field> <field> <name>DM_PULLDN_EN</name> - <description>Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller - 1 - Enable Rpd on DPM</description> + <description>DM pull down enable</description> <bitRange>[6:6]</bitRange> <access>read-write</access> </field> <field> <name>DM_PULLUP_EN</name> - <description>Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller - 1 - Enable Rpu on DPM</description> + <description>DM pull up enable</description> <bitRange>[5:5]</bitRange> <access>read-write</access> </field> <field> <name>DM_PULLUP_HISEL</name> - <description>when dm_pullup_en is set high, this enables second resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2</description> + <description>Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2</description> <bitRange>[4:4]</bitRange> <access>read-write</access> </field> <field> <name>DP_PULLDN_EN</name> - <description>Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller - 1 - Enable Rpd on DPP</description> + <description>DP pull down enable</description> <bitRange>[2:2]</bitRange> <access>read-write</access> </field> <field> <name>DP_PULLUP_EN</name> - <description>Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller</description> + <description>DP pull up enable</description> <bitRange>[1:1]</bitRange> <access>read-write</access> </field> <field> <name>DP_PULLUP_HISEL</name> - <description>when dp_pullup_en is set high, this enables second resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2</description> + <description>Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2</description> <bitRange>[0:0]</bitRange> <access>read-write</access> </field> @@ -44109,6 +44057,7 @@ <register> <name>USBPHY_DIRECT_OVERRIDE</name> <addressOffset>0x00000080</addressOffset> + <description>Override enable for each control in usbphy_direct</description> <resetValue>0x00000000</resetValue> <fields> <field> @@ -44138,43 +44087,36 @@ </field> <field> <name>TX_DM_OVERRIDE_EN</name> - <description>Override default value or value driven from USB Controller to PHY</description> <bitRange>[8:8]</bitRange> <access>read-write</access> </field> <field> <name>TX_DP_OVERRIDE_EN</name> - <description>Override default value or value driven from USB Controller to PHY</description> <bitRange>[7:7]</bitRange> <access>read-write</access> </field> <field> <name>TX_DM_OE_OVERRIDE_EN</name> - <description>Override default value or value driven from USB Controller to PHY</description> <bitRange>[6:6]</bitRange> <access>read-write</access> </field> <field> <name>TX_DP_OE_OVERRIDE_EN</name> - <description>Override default value or value driven from USB Controller to PHY</description> <bitRange>[5:5]</bitRange> <access>read-write</access> </field> <field> <name>DM_PULLDN_EN_OVERRIDE_EN</name> - <description>Override default value or value driven from USB Controller to PHY</description> <bitRange>[4:4]</bitRange> <access>read-write</access> </field> <field> <name>DP_PULLDN_EN_OVERRIDE_EN</name> - <description>Override default value or value driven from USB Controller to PHY</description> <bitRange>[3:3]</bitRange> <access>read-write</access> </field> <field> <name>DP_PULLUP_EN_OVERRIDE_EN</name> - <description>Override default value or value driven from USB Controller to PHY</description> <bitRange>[2:2]</bitRange> <access>read-write</access> </field> @@ -44193,7 +44135,7 @@ <register> <name>USBPHY_TRIM</name> <addressOffset>0x00000084</addressOffset> - <description>Note that most functions are driven directly from usb_fsls controller. This register allows more detailed control/status from the USB PHY. Useful for debug but not expected to be used in normal operation</description> + <description>Used to adjust trim values of USB phy pull down resistors.</description> <resetValue>0x00001f1f</resetValue> <fields> <field> @@ -44246,7 +44188,7 @@ </field> <field> <name>DEV_RESUME_FROM_HOST</name> - <description>Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE</description> + <description>Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME</description> <bitRange>[15:15]</bitRange> <access>read-only</access> </field> @@ -44270,7 +44212,7 @@ </field> <field> <name>VBUS_DETECT</name> - <description>Source: SIE_STATUS.VBUS_DETECT</description> + <description>Source: SIE_STATUS.VBUS_DETECTED</description> <bitRange>[11:11]</bitRange> <access>read-only</access> </field> @@ -44330,7 +44272,7 @@ </field> <field> <name>HOST_RESUME</name> - <description>Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE</description> + <description>Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME</description> <bitRange>[1:1]</bitRange> <access>read-only</access> </field> @@ -44374,7 +44316,7 @@ </field> <field> <name>DEV_RESUME_FROM_HOST</name> - <description>Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE</description> + <description>Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME</description> <bitRange>[15:15]</bitRange> <access>read-write</access> </field> @@ -44398,7 +44340,7 @@ </field> <field> <name>VBUS_DETECT</name> - <description>Source: SIE_STATUS.VBUS_DETECT</description> + <description>Source: SIE_STATUS.VBUS_DETECTED</description> <bitRange>[11:11]</bitRange> <access>read-write</access> </field> @@ -44458,7 +44400,7 @@ </field> <field> <name>HOST_RESUME</name> - <description>Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE</description> + <description>Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME</description> <bitRange>[1:1]</bitRange> <access>read-write</access> </field> @@ -44502,7 +44444,7 @@ </field> <field> <name>DEV_RESUME_FROM_HOST</name> - <description>Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE</description> + <description>Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME</description> <bitRange>[15:15]</bitRange> <access>read-write</access> </field> @@ -44526,7 +44468,7 @@ </field> <field> <name>VBUS_DETECT</name> - <description>Source: SIE_STATUS.VBUS_DETECT</description> + <description>Source: SIE_STATUS.VBUS_DETECTED</description> <bitRange>[11:11]</bitRange> <access>read-write</access> </field> @@ -44586,7 +44528,7 @@ </field> <field> <name>HOST_RESUME</name> - <description>Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE</description> + <description>Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME</description> <bitRange>[1:1]</bitRange> <access>read-write</access> </field> @@ -44630,7 +44572,7 @@ </field> <field> <name>DEV_RESUME_FROM_HOST</name> - <description>Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE</description> + <description>Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME</description> <bitRange>[15:15]</bitRange> <access>read-only</access> </field> @@ -44654,7 +44596,7 @@ </field> <field> <name>VBUS_DETECT</name> - <description>Source: SIE_STATUS.VBUS_DETECT</description> + <description>Source: SIE_STATUS.VBUS_DETECTED</description> <bitRange>[11:11]</bitRange> <access>read-only</access> </field> @@ -44714,7 +44656,7 @@ </field> <field> <name>HOST_RESUME</name> - <description>Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE</description> + <description>Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME</description> <bitRange>[1:1]</bitRange> <access>read-only</access> </field> @@ -44727,11 +44669,15 @@ </fields> </register> </registers> + <interrupt> + <name>USBCTRL_IRQ</name> + <value>5</value> + </interrupt> </peripheral> <peripheral> - <name>USB_DPRAM</name> - <description>DPRAM layout for USB device.</description> + <name>USB_DEVICE_DPRAM</name> <baseAddress>0x50100000</baseAddress> + <description>DPRAM layout for USB device.</description> <addressBlock> <offset>0</offset> <size>256</size> @@ -50335,8 +50281,8 @@ </peripheral> <peripheral> <name>VREG_AND_CHIP_RESET</name> - <description>control and status for on-chip voltage regulator and chip level reset subsystem</description> <baseAddress>0x40064000</baseAddress> + <description>control and status for on-chip voltage regulator and chip level reset subsystem</description> <addressBlock> <offset>0</offset> <size>12</size> @@ -50485,6 +50431,7 @@ <description>Trigger a watchdog reset</description> <bitRange>[31:31]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>ENABLE</name> @@ -50689,17 +50636,13 @@ </peripheral> <peripheral> <name>XIP_CTRL</name> - <description>QSPI flash execute-in-place block</description> <baseAddress>0x14000000</baseAddress> + <description>QSPI flash execute-in-place block</description> <addressBlock> <offset>0</offset> <size>32</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>XIP_IRQ</name> - <value>6</value> - </interrupt> <registers> <register> <name>CTRL</name> @@ -50756,6 +50699,7 @@ completes. Alternatively STAT can be polled until completion.</description> <bitRange>[0:0]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> </fields> </register> @@ -50878,11 +50822,15 @@ </fields> </register> </registers> + <interrupt> + <name>XIP_IRQ</name> + <value>6</value> + </interrupt> </peripheral> <peripheral> <name>XOSC</name> - <description>Controls the crystal oscillator</description> <baseAddress>0x40024000</baseAddress> + <description>Controls the crystal oscillator</description> <addressBlock> <offset>0</offset> <size>32</size> @@ -50898,7 +50846,7 @@ <field> <name>ENABLE</name> <description>On power-up this field is initialised to DISABLE and the chip runs from the ROSC. - If the chip has subsequently been programmed to run from the XOSC then DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. + If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator.</description> <bitRange>[23:12]</bitRange> <access>read-write</access> @@ -50915,7 +50863,7 @@ </field> <field> <name>FREQ_RANGE</name> - <description>Frequency range. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE. This resets to 0xAA0 and cannot be changed.</description> + <description>Frequency range. This resets to 0xAA0 and cannot be changed.</description> <bitRange>[11:0]</bitRange> <access>read-write</access> <enumeratedValues> @@ -51001,13 +50949,13 @@ <description>This is used to save power by pausing the XOSC On power-up this field is initialised to WAKE An invalid write will also select WAKE - Warning: stop the PLLs before selecting dormant mode - Warning: setup the irq before selecting dormant mode</description> + WARNING: stop the PLLs before selecting dormant mode + WARNING: setup the irq before selecting dormant mode</description> <bitRange>[31:0]</bitRange> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>dormant</name> + <name>DORMANT</name> <value>1668246881</value> </enumeratedValue> <enumeratedValue> @@ -51055,5 +51003,33 @@ </register> </registers> </peripheral> + <peripheral> + <name>VIRTUAL</name> + <baseAddress>0x00000000</baseAddress> + <interrupt> + <name>SPARE_IRQ_0</name> + <value>26</value> + </interrupt> + <interrupt> + <name>SPARE_IRQ_1</name> + <value>27</value> + </interrupt> + <interrupt> + <name>SPARE_IRQ_2</name> + <value>28</value> + </interrupt> + <interrupt> + <name>SPARE_IRQ_3</name> + <value>29</value> + </interrupt> + <interrupt> + <name>SPARE_IRQ_4</name> + <value>30</value> + </interrupt> + <interrupt> + <name>SPARE_IRQ_5</name> + <value>31</value> + </interrupt> + </peripheral> </peripherals> </device> \ No newline at end of file
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/dma.h b/src/rp2040/hardware_regs/include/hardware/regs/dma.h index d0976e3..34cddae 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/dma.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/dma.h
@@ -170,6 +170,46 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. +// 0x00 -> Select PIO0's TX FIFO 0 as TREQ +// 0x01 -> Select PIO0's TX FIFO 1 as TREQ +// 0x02 -> Select PIO0's TX FIFO 2 as TREQ +// 0x03 -> Select PIO0's TX FIFO 3 as TREQ +// 0x04 -> Select PIO0's RX FIFO 0 as TREQ +// 0x05 -> Select PIO0's RX FIFO 1 as TREQ +// 0x06 -> Select PIO0's RX FIFO 2 as TREQ +// 0x07 -> Select PIO0's RX FIFO 3 as TREQ +// 0x08 -> Select PIO1's TX FIFO 0 as TREQ +// 0x09 -> Select PIO1's TX FIFO 1 as TREQ +// 0x0a -> Select PIO1's TX FIFO 2 as TREQ +// 0x0b -> Select PIO1's TX FIFO 3 as TREQ +// 0x0c -> Select PIO1's RX FIFO 0 as TREQ +// 0x0d -> Select PIO1's RX FIFO 1 as TREQ +// 0x0e -> Select PIO1's RX FIFO 2 as TREQ +// 0x0f -> Select PIO1's RX FIFO 3 as TREQ +// 0x10 -> Select SPI0's TX FIFO as TREQ +// 0x11 -> Select SPI0's RX FIFO as TREQ +// 0x12 -> Select SPI1's TX FIFO as TREQ +// 0x13 -> Select SPI1's RX FIFO as TREQ +// 0x14 -> Select UART0's TX FIFO as TREQ +// 0x15 -> Select UART0's RX FIFO as TREQ +// 0x16 -> Select UART1's TX FIFO as TREQ +// 0x17 -> Select UART1's RX FIFO as TREQ +// 0x18 -> Select PWM Counter 0's Wrap Value as TREQ +// 0x19 -> Select PWM Counter 1's Wrap Value as TREQ +// 0x1a -> Select PWM Counter 2's Wrap Value as TREQ +// 0x1b -> Select PWM Counter 3's Wrap Value as TREQ +// 0x1c -> Select PWM Counter 4's Wrap Value as TREQ +// 0x1d -> Select PWM Counter 5's Wrap Value as TREQ +// 0x1e -> Select PWM Counter 6's Wrap Value as TREQ +// 0x1f -> Select PWM Counter 7's Wrap Value as TREQ +// 0x20 -> Select I2C0's TX FIFO as TREQ +// 0x21 -> Select I2C0's RX FIFO as TREQ +// 0x22 -> Select I2C1's TX FIFO as TREQ +// 0x23 -> Select I2C1's RX FIFO as TREQ +// 0x24 -> Select the ADC as TREQ +// 0x25 -> Select the XIP Streaming FIFO as TREQ +// 0x26 -> Select the XIP SSI TX FIFO as TREQ +// 0x27 -> Select the XIP SSI RX FIFO as TREQ #define DMA_CH0_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) #define DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) #define DMA_CH0_CTRL_TRIG_TREQ_SEL_MSB _u(20) @@ -180,6 +220,46 @@ #define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) #define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX0 _u(0x00) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX1 _u(0x01) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX2 _u(0x02) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX3 _u(0x03) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX0 _u(0x04) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX1 _u(0x05) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX2 _u(0x06) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX3 _u(0x07) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX0 _u(0x08) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX1 _u(0x09) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX2 _u(0x0a) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX3 _u(0x0b) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX0 _u(0x0c) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX1 _u(0x0d) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX2 _u(0x0e) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX3 _u(0x0f) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_TX _u(0x10) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_RX _u(0x11) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_TX _u(0x12) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_RX _u(0x13) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_UART0_TX _u(0x14) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_UART0_RX _u(0x15) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_UART1_TX _u(0x16) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_UART1_RX _u(0x17) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP0 _u(0x18) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP1 _u(0x19) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP2 _u(0x1a) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP3 _u(0x1b) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP4 _u(0x1c) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP5 _u(0x1d) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP6 _u(0x1e) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP7 _u(0x1f) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_TX _u(0x20) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_RX _u(0x21) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_TX _u(0x22) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_RX _u(0x23) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_ADC _u(0x24) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_XIP_STREAM _u(0x25) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_XIP_SSITX _u(0x26) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_XIP_SSIRX _u(0x27) // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel @@ -558,6 +638,46 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. +// 0x00 -> Select PIO0's TX FIFO 0 as TREQ +// 0x01 -> Select PIO0's TX FIFO 1 as TREQ +// 0x02 -> Select PIO0's TX FIFO 2 as TREQ +// 0x03 -> Select PIO0's TX FIFO 3 as TREQ +// 0x04 -> Select PIO0's RX FIFO 0 as TREQ +// 0x05 -> Select PIO0's RX FIFO 1 as TREQ +// 0x06 -> Select PIO0's RX FIFO 2 as TREQ +// 0x07 -> Select PIO0's RX FIFO 3 as TREQ +// 0x08 -> Select PIO1's TX FIFO 0 as TREQ +// 0x09 -> Select PIO1's TX FIFO 1 as TREQ +// 0x0a -> Select PIO1's TX FIFO 2 as TREQ +// 0x0b -> Select PIO1's TX FIFO 3 as TREQ +// 0x0c -> Select PIO1's RX FIFO 0 as TREQ +// 0x0d -> Select PIO1's RX FIFO 1 as TREQ +// 0x0e -> Select PIO1's RX FIFO 2 as TREQ +// 0x0f -> Select PIO1's RX FIFO 3 as TREQ +// 0x10 -> Select SPI0's TX FIFO as TREQ +// 0x11 -> Select SPI0's RX FIFO as TREQ +// 0x12 -> Select SPI1's TX FIFO as TREQ +// 0x13 -> Select SPI1's RX FIFO as TREQ +// 0x14 -> Select UART0's TX FIFO as TREQ +// 0x15 -> Select UART0's RX FIFO as TREQ +// 0x16 -> Select UART1's TX FIFO as TREQ +// 0x17 -> Select UART1's RX FIFO as TREQ +// 0x18 -> Select PWM Counter 0's Wrap Value as TREQ +// 0x19 -> Select PWM Counter 1's Wrap Value as TREQ +// 0x1a -> Select PWM Counter 2's Wrap Value as TREQ +// 0x1b -> Select PWM Counter 3's Wrap Value as TREQ +// 0x1c -> Select PWM Counter 4's Wrap Value as TREQ +// 0x1d -> Select PWM Counter 5's Wrap Value as TREQ +// 0x1e -> Select PWM Counter 6's Wrap Value as TREQ +// 0x1f -> Select PWM Counter 7's Wrap Value as TREQ +// 0x20 -> Select I2C0's TX FIFO as TREQ +// 0x21 -> Select I2C0's RX FIFO as TREQ +// 0x22 -> Select I2C1's TX FIFO as TREQ +// 0x23 -> Select I2C1's RX FIFO as TREQ +// 0x24 -> Select the ADC as TREQ +// 0x25 -> Select the XIP Streaming FIFO as TREQ +// 0x26 -> Select the XIP SSI TX FIFO as TREQ +// 0x27 -> Select the XIP SSI RX FIFO as TREQ #define DMA_CH1_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) #define DMA_CH1_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) #define DMA_CH1_CTRL_TRIG_TREQ_SEL_MSB _u(20) @@ -568,6 +688,46 @@ #define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) #define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX0 _u(0x00) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX1 _u(0x01) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX2 _u(0x02) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX3 _u(0x03) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX0 _u(0x04) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX1 _u(0x05) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX2 _u(0x06) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX3 _u(0x07) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX0 _u(0x08) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX1 _u(0x09) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX2 _u(0x0a) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX3 _u(0x0b) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX0 _u(0x0c) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX1 _u(0x0d) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX2 _u(0x0e) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX3 _u(0x0f) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_TX _u(0x10) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_RX _u(0x11) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_TX _u(0x12) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_RX _u(0x13) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_UART0_TX _u(0x14) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_UART0_RX _u(0x15) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_UART1_TX _u(0x16) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_UART1_RX _u(0x17) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP0 _u(0x18) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP1 _u(0x19) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP2 _u(0x1a) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP3 _u(0x1b) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP4 _u(0x1c) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP5 _u(0x1d) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP6 _u(0x1e) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP7 _u(0x1f) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_TX _u(0x20) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_RX _u(0x21) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_TX _u(0x22) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_RX _u(0x23) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_ADC _u(0x24) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_XIP_STREAM _u(0x25) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_XIP_SSITX _u(0x26) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_XIP_SSIRX _u(0x27) // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel @@ -946,6 +1106,46 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. +// 0x00 -> Select PIO0's TX FIFO 0 as TREQ +// 0x01 -> Select PIO0's TX FIFO 1 as TREQ +// 0x02 -> Select PIO0's TX FIFO 2 as TREQ +// 0x03 -> Select PIO0's TX FIFO 3 as TREQ +// 0x04 -> Select PIO0's RX FIFO 0 as TREQ +// 0x05 -> Select PIO0's RX FIFO 1 as TREQ +// 0x06 -> Select PIO0's RX FIFO 2 as TREQ +// 0x07 -> Select PIO0's RX FIFO 3 as TREQ +// 0x08 -> Select PIO1's TX FIFO 0 as TREQ +// 0x09 -> Select PIO1's TX FIFO 1 as TREQ +// 0x0a -> Select PIO1's TX FIFO 2 as TREQ +// 0x0b -> Select PIO1's TX FIFO 3 as TREQ +// 0x0c -> Select PIO1's RX FIFO 0 as TREQ +// 0x0d -> Select PIO1's RX FIFO 1 as TREQ +// 0x0e -> Select PIO1's RX FIFO 2 as TREQ +// 0x0f -> Select PIO1's RX FIFO 3 as TREQ +// 0x10 -> Select SPI0's TX FIFO as TREQ +// 0x11 -> Select SPI0's RX FIFO as TREQ +// 0x12 -> Select SPI1's TX FIFO as TREQ +// 0x13 -> Select SPI1's RX FIFO as TREQ +// 0x14 -> Select UART0's TX FIFO as TREQ +// 0x15 -> Select UART0's RX FIFO as TREQ +// 0x16 -> Select UART1's TX FIFO as TREQ +// 0x17 -> Select UART1's RX FIFO as TREQ +// 0x18 -> Select PWM Counter 0's Wrap Value as TREQ +// 0x19 -> Select PWM Counter 1's Wrap Value as TREQ +// 0x1a -> Select PWM Counter 2's Wrap Value as TREQ +// 0x1b -> Select PWM Counter 3's Wrap Value as TREQ +// 0x1c -> Select PWM Counter 4's Wrap Value as TREQ +// 0x1d -> Select PWM Counter 5's Wrap Value as TREQ +// 0x1e -> Select PWM Counter 6's Wrap Value as TREQ +// 0x1f -> Select PWM Counter 7's Wrap Value as TREQ +// 0x20 -> Select I2C0's TX FIFO as TREQ +// 0x21 -> Select I2C0's RX FIFO as TREQ +// 0x22 -> Select I2C1's TX FIFO as TREQ +// 0x23 -> Select I2C1's RX FIFO as TREQ +// 0x24 -> Select the ADC as TREQ +// 0x25 -> Select the XIP Streaming FIFO as TREQ +// 0x26 -> Select the XIP SSI TX FIFO as TREQ +// 0x27 -> Select the XIP SSI RX FIFO as TREQ #define DMA_CH2_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) #define DMA_CH2_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) #define DMA_CH2_CTRL_TRIG_TREQ_SEL_MSB _u(20) @@ -956,6 +1156,46 @@ #define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) #define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX0 _u(0x00) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX1 _u(0x01) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX2 _u(0x02) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX3 _u(0x03) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX0 _u(0x04) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX1 _u(0x05) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX2 _u(0x06) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX3 _u(0x07) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX0 _u(0x08) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX1 _u(0x09) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX2 _u(0x0a) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX3 _u(0x0b) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX0 _u(0x0c) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX1 _u(0x0d) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX2 _u(0x0e) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX3 _u(0x0f) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_TX _u(0x10) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_RX _u(0x11) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_TX _u(0x12) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_RX _u(0x13) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_UART0_TX _u(0x14) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_UART0_RX _u(0x15) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_UART1_TX _u(0x16) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_UART1_RX _u(0x17) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP0 _u(0x18) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP1 _u(0x19) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP2 _u(0x1a) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP3 _u(0x1b) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP4 _u(0x1c) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP5 _u(0x1d) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP6 _u(0x1e) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP7 _u(0x1f) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_TX _u(0x20) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_RX _u(0x21) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_TX _u(0x22) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_RX _u(0x23) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_ADC _u(0x24) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_XIP_STREAM _u(0x25) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_XIP_SSITX _u(0x26) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_XIP_SSIRX _u(0x27) // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel @@ -1334,6 +1574,46 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. +// 0x00 -> Select PIO0's TX FIFO 0 as TREQ +// 0x01 -> Select PIO0's TX FIFO 1 as TREQ +// 0x02 -> Select PIO0's TX FIFO 2 as TREQ +// 0x03 -> Select PIO0's TX FIFO 3 as TREQ +// 0x04 -> Select PIO0's RX FIFO 0 as TREQ +// 0x05 -> Select PIO0's RX FIFO 1 as TREQ +// 0x06 -> Select PIO0's RX FIFO 2 as TREQ +// 0x07 -> Select PIO0's RX FIFO 3 as TREQ +// 0x08 -> Select PIO1's TX FIFO 0 as TREQ +// 0x09 -> Select PIO1's TX FIFO 1 as TREQ +// 0x0a -> Select PIO1's TX FIFO 2 as TREQ +// 0x0b -> Select PIO1's TX FIFO 3 as TREQ +// 0x0c -> Select PIO1's RX FIFO 0 as TREQ +// 0x0d -> Select PIO1's RX FIFO 1 as TREQ +// 0x0e -> Select PIO1's RX FIFO 2 as TREQ +// 0x0f -> Select PIO1's RX FIFO 3 as TREQ +// 0x10 -> Select SPI0's TX FIFO as TREQ +// 0x11 -> Select SPI0's RX FIFO as TREQ +// 0x12 -> Select SPI1's TX FIFO as TREQ +// 0x13 -> Select SPI1's RX FIFO as TREQ +// 0x14 -> Select UART0's TX FIFO as TREQ +// 0x15 -> Select UART0's RX FIFO as TREQ +// 0x16 -> Select UART1's TX FIFO as TREQ +// 0x17 -> Select UART1's RX FIFO as TREQ +// 0x18 -> Select PWM Counter 0's Wrap Value as TREQ +// 0x19 -> Select PWM Counter 1's Wrap Value as TREQ +// 0x1a -> Select PWM Counter 2's Wrap Value as TREQ +// 0x1b -> Select PWM Counter 3's Wrap Value as TREQ +// 0x1c -> Select PWM Counter 4's Wrap Value as TREQ +// 0x1d -> Select PWM Counter 5's Wrap Value as TREQ +// 0x1e -> Select PWM Counter 6's Wrap Value as TREQ +// 0x1f -> Select PWM Counter 7's Wrap Value as TREQ +// 0x20 -> Select I2C0's TX FIFO as TREQ +// 0x21 -> Select I2C0's RX FIFO as TREQ +// 0x22 -> Select I2C1's TX FIFO as TREQ +// 0x23 -> Select I2C1's RX FIFO as TREQ +// 0x24 -> Select the ADC as TREQ +// 0x25 -> Select the XIP Streaming FIFO as TREQ +// 0x26 -> Select the XIP SSI TX FIFO as TREQ +// 0x27 -> Select the XIP SSI RX FIFO as TREQ #define DMA_CH3_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) #define DMA_CH3_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) #define DMA_CH3_CTRL_TRIG_TREQ_SEL_MSB _u(20) @@ -1344,6 +1624,46 @@ #define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) #define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX0 _u(0x00) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX1 _u(0x01) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX2 _u(0x02) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX3 _u(0x03) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX0 _u(0x04) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX1 _u(0x05) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX2 _u(0x06) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX3 _u(0x07) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX0 _u(0x08) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX1 _u(0x09) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX2 _u(0x0a) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX3 _u(0x0b) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX0 _u(0x0c) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX1 _u(0x0d) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX2 _u(0x0e) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX3 _u(0x0f) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_TX _u(0x10) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_RX _u(0x11) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_TX _u(0x12) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_RX _u(0x13) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_UART0_TX _u(0x14) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_UART0_RX _u(0x15) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_UART1_TX _u(0x16) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_UART1_RX _u(0x17) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP0 _u(0x18) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP1 _u(0x19) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP2 _u(0x1a) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP3 _u(0x1b) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP4 _u(0x1c) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP5 _u(0x1d) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP6 _u(0x1e) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP7 _u(0x1f) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_TX _u(0x20) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_RX _u(0x21) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_TX _u(0x22) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_RX _u(0x23) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_ADC _u(0x24) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_XIP_STREAM _u(0x25) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_XIP_SSITX _u(0x26) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_XIP_SSIRX _u(0x27) // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel @@ -1722,6 +2042,46 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. +// 0x00 -> Select PIO0's TX FIFO 0 as TREQ +// 0x01 -> Select PIO0's TX FIFO 1 as TREQ +// 0x02 -> Select PIO0's TX FIFO 2 as TREQ +// 0x03 -> Select PIO0's TX FIFO 3 as TREQ +// 0x04 -> Select PIO0's RX FIFO 0 as TREQ +// 0x05 -> Select PIO0's RX FIFO 1 as TREQ +// 0x06 -> Select PIO0's RX FIFO 2 as TREQ +// 0x07 -> Select PIO0's RX FIFO 3 as TREQ +// 0x08 -> Select PIO1's TX FIFO 0 as TREQ +// 0x09 -> Select PIO1's TX FIFO 1 as TREQ +// 0x0a -> Select PIO1's TX FIFO 2 as TREQ +// 0x0b -> Select PIO1's TX FIFO 3 as TREQ +// 0x0c -> Select PIO1's RX FIFO 0 as TREQ +// 0x0d -> Select PIO1's RX FIFO 1 as TREQ +// 0x0e -> Select PIO1's RX FIFO 2 as TREQ +// 0x0f -> Select PIO1's RX FIFO 3 as TREQ +// 0x10 -> Select SPI0's TX FIFO as TREQ +// 0x11 -> Select SPI0's RX FIFO as TREQ +// 0x12 -> Select SPI1's TX FIFO as TREQ +// 0x13 -> Select SPI1's RX FIFO as TREQ +// 0x14 -> Select UART0's TX FIFO as TREQ +// 0x15 -> Select UART0's RX FIFO as TREQ +// 0x16 -> Select UART1's TX FIFO as TREQ +// 0x17 -> Select UART1's RX FIFO as TREQ +// 0x18 -> Select PWM Counter 0's Wrap Value as TREQ +// 0x19 -> Select PWM Counter 1's Wrap Value as TREQ +// 0x1a -> Select PWM Counter 2's Wrap Value as TREQ +// 0x1b -> Select PWM Counter 3's Wrap Value as TREQ +// 0x1c -> Select PWM Counter 4's Wrap Value as TREQ +// 0x1d -> Select PWM Counter 5's Wrap Value as TREQ +// 0x1e -> Select PWM Counter 6's Wrap Value as TREQ +// 0x1f -> Select PWM Counter 7's Wrap Value as TREQ +// 0x20 -> Select I2C0's TX FIFO as TREQ +// 0x21 -> Select I2C0's RX FIFO as TREQ +// 0x22 -> Select I2C1's TX FIFO as TREQ +// 0x23 -> Select I2C1's RX FIFO as TREQ +// 0x24 -> Select the ADC as TREQ +// 0x25 -> Select the XIP Streaming FIFO as TREQ +// 0x26 -> Select the XIP SSI TX FIFO as TREQ +// 0x27 -> Select the XIP SSI RX FIFO as TREQ #define DMA_CH4_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) #define DMA_CH4_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) #define DMA_CH4_CTRL_TRIG_TREQ_SEL_MSB _u(20) @@ -1732,6 +2092,46 @@ #define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) #define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX0 _u(0x00) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX1 _u(0x01) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX2 _u(0x02) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX3 _u(0x03) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX0 _u(0x04) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX1 _u(0x05) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX2 _u(0x06) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX3 _u(0x07) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX0 _u(0x08) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX1 _u(0x09) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX2 _u(0x0a) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX3 _u(0x0b) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX0 _u(0x0c) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX1 _u(0x0d) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX2 _u(0x0e) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX3 _u(0x0f) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_TX _u(0x10) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_RX _u(0x11) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_TX _u(0x12) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_RX _u(0x13) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_UART0_TX _u(0x14) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_UART0_RX _u(0x15) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_UART1_TX _u(0x16) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_UART1_RX _u(0x17) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP0 _u(0x18) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP1 _u(0x19) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP2 _u(0x1a) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP3 _u(0x1b) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP4 _u(0x1c) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP5 _u(0x1d) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP6 _u(0x1e) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP7 _u(0x1f) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_TX _u(0x20) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_RX _u(0x21) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_TX _u(0x22) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_RX _u(0x23) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_ADC _u(0x24) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_XIP_STREAM _u(0x25) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_XIP_SSITX _u(0x26) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_XIP_SSIRX _u(0x27) // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel @@ -2110,6 +2510,46 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. +// 0x00 -> Select PIO0's TX FIFO 0 as TREQ +// 0x01 -> Select PIO0's TX FIFO 1 as TREQ +// 0x02 -> Select PIO0's TX FIFO 2 as TREQ +// 0x03 -> Select PIO0's TX FIFO 3 as TREQ +// 0x04 -> Select PIO0's RX FIFO 0 as TREQ +// 0x05 -> Select PIO0's RX FIFO 1 as TREQ +// 0x06 -> Select PIO0's RX FIFO 2 as TREQ +// 0x07 -> Select PIO0's RX FIFO 3 as TREQ +// 0x08 -> Select PIO1's TX FIFO 0 as TREQ +// 0x09 -> Select PIO1's TX FIFO 1 as TREQ +// 0x0a -> Select PIO1's TX FIFO 2 as TREQ +// 0x0b -> Select PIO1's TX FIFO 3 as TREQ +// 0x0c -> Select PIO1's RX FIFO 0 as TREQ +// 0x0d -> Select PIO1's RX FIFO 1 as TREQ +// 0x0e -> Select PIO1's RX FIFO 2 as TREQ +// 0x0f -> Select PIO1's RX FIFO 3 as TREQ +// 0x10 -> Select SPI0's TX FIFO as TREQ +// 0x11 -> Select SPI0's RX FIFO as TREQ +// 0x12 -> Select SPI1's TX FIFO as TREQ +// 0x13 -> Select SPI1's RX FIFO as TREQ +// 0x14 -> Select UART0's TX FIFO as TREQ +// 0x15 -> Select UART0's RX FIFO as TREQ +// 0x16 -> Select UART1's TX FIFO as TREQ +// 0x17 -> Select UART1's RX FIFO as TREQ +// 0x18 -> Select PWM Counter 0's Wrap Value as TREQ +// 0x19 -> Select PWM Counter 1's Wrap Value as TREQ +// 0x1a -> Select PWM Counter 2's Wrap Value as TREQ +// 0x1b -> Select PWM Counter 3's Wrap Value as TREQ +// 0x1c -> Select PWM Counter 4's Wrap Value as TREQ +// 0x1d -> Select PWM Counter 5's Wrap Value as TREQ +// 0x1e -> Select PWM Counter 6's Wrap Value as TREQ +// 0x1f -> Select PWM Counter 7's Wrap Value as TREQ +// 0x20 -> Select I2C0's TX FIFO as TREQ +// 0x21 -> Select I2C0's RX FIFO as TREQ +// 0x22 -> Select I2C1's TX FIFO as TREQ +// 0x23 -> Select I2C1's RX FIFO as TREQ +// 0x24 -> Select the ADC as TREQ +// 0x25 -> Select the XIP Streaming FIFO as TREQ +// 0x26 -> Select the XIP SSI TX FIFO as TREQ +// 0x27 -> Select the XIP SSI RX FIFO as TREQ #define DMA_CH5_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) #define DMA_CH5_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) #define DMA_CH5_CTRL_TRIG_TREQ_SEL_MSB _u(20) @@ -2120,6 +2560,46 @@ #define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) #define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX0 _u(0x00) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX1 _u(0x01) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX2 _u(0x02) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX3 _u(0x03) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX0 _u(0x04) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX1 _u(0x05) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX2 _u(0x06) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX3 _u(0x07) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX0 _u(0x08) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX1 _u(0x09) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX2 _u(0x0a) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX3 _u(0x0b) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX0 _u(0x0c) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX1 _u(0x0d) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX2 _u(0x0e) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX3 _u(0x0f) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_TX _u(0x10) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_RX _u(0x11) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_TX _u(0x12) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_RX _u(0x13) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_UART0_TX _u(0x14) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_UART0_RX _u(0x15) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_UART1_TX _u(0x16) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_UART1_RX _u(0x17) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP0 _u(0x18) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP1 _u(0x19) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP2 _u(0x1a) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP3 _u(0x1b) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP4 _u(0x1c) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP5 _u(0x1d) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP6 _u(0x1e) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP7 _u(0x1f) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_TX _u(0x20) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_RX _u(0x21) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_TX _u(0x22) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_RX _u(0x23) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_ADC _u(0x24) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_XIP_STREAM _u(0x25) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_XIP_SSITX _u(0x26) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_XIP_SSIRX _u(0x27) // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel @@ -2498,6 +2978,46 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. +// 0x00 -> Select PIO0's TX FIFO 0 as TREQ +// 0x01 -> Select PIO0's TX FIFO 1 as TREQ +// 0x02 -> Select PIO0's TX FIFO 2 as TREQ +// 0x03 -> Select PIO0's TX FIFO 3 as TREQ +// 0x04 -> Select PIO0's RX FIFO 0 as TREQ +// 0x05 -> Select PIO0's RX FIFO 1 as TREQ +// 0x06 -> Select PIO0's RX FIFO 2 as TREQ +// 0x07 -> Select PIO0's RX FIFO 3 as TREQ +// 0x08 -> Select PIO1's TX FIFO 0 as TREQ +// 0x09 -> Select PIO1's TX FIFO 1 as TREQ +// 0x0a -> Select PIO1's TX FIFO 2 as TREQ +// 0x0b -> Select PIO1's TX FIFO 3 as TREQ +// 0x0c -> Select PIO1's RX FIFO 0 as TREQ +// 0x0d -> Select PIO1's RX FIFO 1 as TREQ +// 0x0e -> Select PIO1's RX FIFO 2 as TREQ +// 0x0f -> Select PIO1's RX FIFO 3 as TREQ +// 0x10 -> Select SPI0's TX FIFO as TREQ +// 0x11 -> Select SPI0's RX FIFO as TREQ +// 0x12 -> Select SPI1's TX FIFO as TREQ +// 0x13 -> Select SPI1's RX FIFO as TREQ +// 0x14 -> Select UART0's TX FIFO as TREQ +// 0x15 -> Select UART0's RX FIFO as TREQ +// 0x16 -> Select UART1's TX FIFO as TREQ +// 0x17 -> Select UART1's RX FIFO as TREQ +// 0x18 -> Select PWM Counter 0's Wrap Value as TREQ +// 0x19 -> Select PWM Counter 1's Wrap Value as TREQ +// 0x1a -> Select PWM Counter 2's Wrap Value as TREQ +// 0x1b -> Select PWM Counter 3's Wrap Value as TREQ +// 0x1c -> Select PWM Counter 4's Wrap Value as TREQ +// 0x1d -> Select PWM Counter 5's Wrap Value as TREQ +// 0x1e -> Select PWM Counter 6's Wrap Value as TREQ +// 0x1f -> Select PWM Counter 7's Wrap Value as TREQ +// 0x20 -> Select I2C0's TX FIFO as TREQ +// 0x21 -> Select I2C0's RX FIFO as TREQ +// 0x22 -> Select I2C1's TX FIFO as TREQ +// 0x23 -> Select I2C1's RX FIFO as TREQ +// 0x24 -> Select the ADC as TREQ +// 0x25 -> Select the XIP Streaming FIFO as TREQ +// 0x26 -> Select the XIP SSI TX FIFO as TREQ +// 0x27 -> Select the XIP SSI RX FIFO as TREQ #define DMA_CH6_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) #define DMA_CH6_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) #define DMA_CH6_CTRL_TRIG_TREQ_SEL_MSB _u(20) @@ -2508,6 +3028,46 @@ #define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) #define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX0 _u(0x00) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX1 _u(0x01) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX2 _u(0x02) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX3 _u(0x03) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX0 _u(0x04) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX1 _u(0x05) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX2 _u(0x06) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX3 _u(0x07) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX0 _u(0x08) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX1 _u(0x09) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX2 _u(0x0a) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX3 _u(0x0b) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX0 _u(0x0c) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX1 _u(0x0d) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX2 _u(0x0e) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX3 _u(0x0f) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_TX _u(0x10) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_RX _u(0x11) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_TX _u(0x12) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_RX _u(0x13) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_UART0_TX _u(0x14) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_UART0_RX _u(0x15) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_UART1_TX _u(0x16) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_UART1_RX _u(0x17) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP0 _u(0x18) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP1 _u(0x19) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP2 _u(0x1a) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP3 _u(0x1b) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP4 _u(0x1c) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP5 _u(0x1d) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP6 _u(0x1e) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP7 _u(0x1f) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_TX _u(0x20) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_RX _u(0x21) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_TX _u(0x22) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_RX _u(0x23) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_ADC _u(0x24) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_XIP_STREAM _u(0x25) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_XIP_SSITX _u(0x26) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_XIP_SSIRX _u(0x27) // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel @@ -2886,6 +3446,46 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. +// 0x00 -> Select PIO0's TX FIFO 0 as TREQ +// 0x01 -> Select PIO0's TX FIFO 1 as TREQ +// 0x02 -> Select PIO0's TX FIFO 2 as TREQ +// 0x03 -> Select PIO0's TX FIFO 3 as TREQ +// 0x04 -> Select PIO0's RX FIFO 0 as TREQ +// 0x05 -> Select PIO0's RX FIFO 1 as TREQ +// 0x06 -> Select PIO0's RX FIFO 2 as TREQ +// 0x07 -> Select PIO0's RX FIFO 3 as TREQ +// 0x08 -> Select PIO1's TX FIFO 0 as TREQ +// 0x09 -> Select PIO1's TX FIFO 1 as TREQ +// 0x0a -> Select PIO1's TX FIFO 2 as TREQ +// 0x0b -> Select PIO1's TX FIFO 3 as TREQ +// 0x0c -> Select PIO1's RX FIFO 0 as TREQ +// 0x0d -> Select PIO1's RX FIFO 1 as TREQ +// 0x0e -> Select PIO1's RX FIFO 2 as TREQ +// 0x0f -> Select PIO1's RX FIFO 3 as TREQ +// 0x10 -> Select SPI0's TX FIFO as TREQ +// 0x11 -> Select SPI0's RX FIFO as TREQ +// 0x12 -> Select SPI1's TX FIFO as TREQ +// 0x13 -> Select SPI1's RX FIFO as TREQ +// 0x14 -> Select UART0's TX FIFO as TREQ +// 0x15 -> Select UART0's RX FIFO as TREQ +// 0x16 -> Select UART1's TX FIFO as TREQ +// 0x17 -> Select UART1's RX FIFO as TREQ +// 0x18 -> Select PWM Counter 0's Wrap Value as TREQ +// 0x19 -> Select PWM Counter 1's Wrap Value as TREQ +// 0x1a -> Select PWM Counter 2's Wrap Value as TREQ +// 0x1b -> Select PWM Counter 3's Wrap Value as TREQ +// 0x1c -> Select PWM Counter 4's Wrap Value as TREQ +// 0x1d -> Select PWM Counter 5's Wrap Value as TREQ +// 0x1e -> Select PWM Counter 6's Wrap Value as TREQ +// 0x1f -> Select PWM Counter 7's Wrap Value as TREQ +// 0x20 -> Select I2C0's TX FIFO as TREQ +// 0x21 -> Select I2C0's RX FIFO as TREQ +// 0x22 -> Select I2C1's TX FIFO as TREQ +// 0x23 -> Select I2C1's RX FIFO as TREQ +// 0x24 -> Select the ADC as TREQ +// 0x25 -> Select the XIP Streaming FIFO as TREQ +// 0x26 -> Select the XIP SSI TX FIFO as TREQ +// 0x27 -> Select the XIP SSI RX FIFO as TREQ #define DMA_CH7_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) #define DMA_CH7_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) #define DMA_CH7_CTRL_TRIG_TREQ_SEL_MSB _u(20) @@ -2896,6 +3496,46 @@ #define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) #define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX0 _u(0x00) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX1 _u(0x01) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX2 _u(0x02) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX3 _u(0x03) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX0 _u(0x04) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX1 _u(0x05) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX2 _u(0x06) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX3 _u(0x07) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX0 _u(0x08) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX1 _u(0x09) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX2 _u(0x0a) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX3 _u(0x0b) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX0 _u(0x0c) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX1 _u(0x0d) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX2 _u(0x0e) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX3 _u(0x0f) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_TX _u(0x10) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_RX _u(0x11) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_TX _u(0x12) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_RX _u(0x13) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_UART0_TX _u(0x14) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_UART0_RX _u(0x15) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_UART1_TX _u(0x16) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_UART1_RX _u(0x17) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP0 _u(0x18) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP1 _u(0x19) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP2 _u(0x1a) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP3 _u(0x1b) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP4 _u(0x1c) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP5 _u(0x1d) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP6 _u(0x1e) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP7 _u(0x1f) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_TX _u(0x20) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_RX _u(0x21) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_TX _u(0x22) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_RX _u(0x23) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_ADC _u(0x24) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_XIP_STREAM _u(0x25) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_XIP_SSITX _u(0x26) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_XIP_SSIRX _u(0x27) // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel @@ -3274,6 +3914,46 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. +// 0x00 -> Select PIO0's TX FIFO 0 as TREQ +// 0x01 -> Select PIO0's TX FIFO 1 as TREQ +// 0x02 -> Select PIO0's TX FIFO 2 as TREQ +// 0x03 -> Select PIO0's TX FIFO 3 as TREQ +// 0x04 -> Select PIO0's RX FIFO 0 as TREQ +// 0x05 -> Select PIO0's RX FIFO 1 as TREQ +// 0x06 -> Select PIO0's RX FIFO 2 as TREQ +// 0x07 -> Select PIO0's RX FIFO 3 as TREQ +// 0x08 -> Select PIO1's TX FIFO 0 as TREQ +// 0x09 -> Select PIO1's TX FIFO 1 as TREQ +// 0x0a -> Select PIO1's TX FIFO 2 as TREQ +// 0x0b -> Select PIO1's TX FIFO 3 as TREQ +// 0x0c -> Select PIO1's RX FIFO 0 as TREQ +// 0x0d -> Select PIO1's RX FIFO 1 as TREQ +// 0x0e -> Select PIO1's RX FIFO 2 as TREQ +// 0x0f -> Select PIO1's RX FIFO 3 as TREQ +// 0x10 -> Select SPI0's TX FIFO as TREQ +// 0x11 -> Select SPI0's RX FIFO as TREQ +// 0x12 -> Select SPI1's TX FIFO as TREQ +// 0x13 -> Select SPI1's RX FIFO as TREQ +// 0x14 -> Select UART0's TX FIFO as TREQ +// 0x15 -> Select UART0's RX FIFO as TREQ +// 0x16 -> Select UART1's TX FIFO as TREQ +// 0x17 -> Select UART1's RX FIFO as TREQ +// 0x18 -> Select PWM Counter 0's Wrap Value as TREQ +// 0x19 -> Select PWM Counter 1's Wrap Value as TREQ +// 0x1a -> Select PWM Counter 2's Wrap Value as TREQ +// 0x1b -> Select PWM Counter 3's Wrap Value as TREQ +// 0x1c -> Select PWM Counter 4's Wrap Value as TREQ +// 0x1d -> Select PWM Counter 5's Wrap Value as TREQ +// 0x1e -> Select PWM Counter 6's Wrap Value as TREQ +// 0x1f -> Select PWM Counter 7's Wrap Value as TREQ +// 0x20 -> Select I2C0's TX FIFO as TREQ +// 0x21 -> Select I2C0's RX FIFO as TREQ +// 0x22 -> Select I2C1's TX FIFO as TREQ +// 0x23 -> Select I2C1's RX FIFO as TREQ +// 0x24 -> Select the ADC as TREQ +// 0x25 -> Select the XIP Streaming FIFO as TREQ +// 0x26 -> Select the XIP SSI TX FIFO as TREQ +// 0x27 -> Select the XIP SSI RX FIFO as TREQ #define DMA_CH8_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) #define DMA_CH8_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) #define DMA_CH8_CTRL_TRIG_TREQ_SEL_MSB _u(20) @@ -3284,6 +3964,46 @@ #define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) #define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX0 _u(0x00) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX1 _u(0x01) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX2 _u(0x02) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX3 _u(0x03) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX0 _u(0x04) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX1 _u(0x05) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX2 _u(0x06) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX3 _u(0x07) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX0 _u(0x08) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX1 _u(0x09) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX2 _u(0x0a) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX3 _u(0x0b) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX0 _u(0x0c) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX1 _u(0x0d) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX2 _u(0x0e) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX3 _u(0x0f) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_TX _u(0x10) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_RX _u(0x11) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_TX _u(0x12) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_RX _u(0x13) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_UART0_TX _u(0x14) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_UART0_RX _u(0x15) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_UART1_TX _u(0x16) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_UART1_RX _u(0x17) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP0 _u(0x18) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP1 _u(0x19) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP2 _u(0x1a) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP3 _u(0x1b) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP4 _u(0x1c) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP5 _u(0x1d) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP6 _u(0x1e) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP7 _u(0x1f) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_TX _u(0x20) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_RX _u(0x21) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_TX _u(0x22) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_RX _u(0x23) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_ADC _u(0x24) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_XIP_STREAM _u(0x25) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_XIP_SSITX _u(0x26) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_XIP_SSIRX _u(0x27) // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel @@ -3662,6 +4382,46 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. +// 0x00 -> Select PIO0's TX FIFO 0 as TREQ +// 0x01 -> Select PIO0's TX FIFO 1 as TREQ +// 0x02 -> Select PIO0's TX FIFO 2 as TREQ +// 0x03 -> Select PIO0's TX FIFO 3 as TREQ +// 0x04 -> Select PIO0's RX FIFO 0 as TREQ +// 0x05 -> Select PIO0's RX FIFO 1 as TREQ +// 0x06 -> Select PIO0's RX FIFO 2 as TREQ +// 0x07 -> Select PIO0's RX FIFO 3 as TREQ +// 0x08 -> Select PIO1's TX FIFO 0 as TREQ +// 0x09 -> Select PIO1's TX FIFO 1 as TREQ +// 0x0a -> Select PIO1's TX FIFO 2 as TREQ +// 0x0b -> Select PIO1's TX FIFO 3 as TREQ +// 0x0c -> Select PIO1's RX FIFO 0 as TREQ +// 0x0d -> Select PIO1's RX FIFO 1 as TREQ +// 0x0e -> Select PIO1's RX FIFO 2 as TREQ +// 0x0f -> Select PIO1's RX FIFO 3 as TREQ +// 0x10 -> Select SPI0's TX FIFO as TREQ +// 0x11 -> Select SPI0's RX FIFO as TREQ +// 0x12 -> Select SPI1's TX FIFO as TREQ +// 0x13 -> Select SPI1's RX FIFO as TREQ +// 0x14 -> Select UART0's TX FIFO as TREQ +// 0x15 -> Select UART0's RX FIFO as TREQ +// 0x16 -> Select UART1's TX FIFO as TREQ +// 0x17 -> Select UART1's RX FIFO as TREQ +// 0x18 -> Select PWM Counter 0's Wrap Value as TREQ +// 0x19 -> Select PWM Counter 1's Wrap Value as TREQ +// 0x1a -> Select PWM Counter 2's Wrap Value as TREQ +// 0x1b -> Select PWM Counter 3's Wrap Value as TREQ +// 0x1c -> Select PWM Counter 4's Wrap Value as TREQ +// 0x1d -> Select PWM Counter 5's Wrap Value as TREQ +// 0x1e -> Select PWM Counter 6's Wrap Value as TREQ +// 0x1f -> Select PWM Counter 7's Wrap Value as TREQ +// 0x20 -> Select I2C0's TX FIFO as TREQ +// 0x21 -> Select I2C0's RX FIFO as TREQ +// 0x22 -> Select I2C1's TX FIFO as TREQ +// 0x23 -> Select I2C1's RX FIFO as TREQ +// 0x24 -> Select the ADC as TREQ +// 0x25 -> Select the XIP Streaming FIFO as TREQ +// 0x26 -> Select the XIP SSI TX FIFO as TREQ +// 0x27 -> Select the XIP SSI RX FIFO as TREQ #define DMA_CH9_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) #define DMA_CH9_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) #define DMA_CH9_CTRL_TRIG_TREQ_SEL_MSB _u(20) @@ -3672,6 +4432,46 @@ #define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) #define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX0 _u(0x00) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX1 _u(0x01) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX2 _u(0x02) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX3 _u(0x03) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX0 _u(0x04) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX1 _u(0x05) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX2 _u(0x06) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX3 _u(0x07) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX0 _u(0x08) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX1 _u(0x09) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX2 _u(0x0a) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX3 _u(0x0b) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX0 _u(0x0c) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX1 _u(0x0d) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX2 _u(0x0e) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX3 _u(0x0f) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_TX _u(0x10) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_RX _u(0x11) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_TX _u(0x12) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_RX _u(0x13) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_UART0_TX _u(0x14) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_UART0_RX _u(0x15) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_UART1_TX _u(0x16) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_UART1_RX _u(0x17) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP0 _u(0x18) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP1 _u(0x19) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP2 _u(0x1a) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP3 _u(0x1b) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP4 _u(0x1c) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP5 _u(0x1d) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP6 _u(0x1e) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP7 _u(0x1f) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_TX _u(0x20) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_RX _u(0x21) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_TX _u(0x22) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_RX _u(0x23) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_ADC _u(0x24) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_XIP_STREAM _u(0x25) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_XIP_SSITX _u(0x26) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_XIP_SSIRX _u(0x27) // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel @@ -4050,6 +4850,46 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. +// 0x00 -> Select PIO0's TX FIFO 0 as TREQ +// 0x01 -> Select PIO0's TX FIFO 1 as TREQ +// 0x02 -> Select PIO0's TX FIFO 2 as TREQ +// 0x03 -> Select PIO0's TX FIFO 3 as TREQ +// 0x04 -> Select PIO0's RX FIFO 0 as TREQ +// 0x05 -> Select PIO0's RX FIFO 1 as TREQ +// 0x06 -> Select PIO0's RX FIFO 2 as TREQ +// 0x07 -> Select PIO0's RX FIFO 3 as TREQ +// 0x08 -> Select PIO1's TX FIFO 0 as TREQ +// 0x09 -> Select PIO1's TX FIFO 1 as TREQ +// 0x0a -> Select PIO1's TX FIFO 2 as TREQ +// 0x0b -> Select PIO1's TX FIFO 3 as TREQ +// 0x0c -> Select PIO1's RX FIFO 0 as TREQ +// 0x0d -> Select PIO1's RX FIFO 1 as TREQ +// 0x0e -> Select PIO1's RX FIFO 2 as TREQ +// 0x0f -> Select PIO1's RX FIFO 3 as TREQ +// 0x10 -> Select SPI0's TX FIFO as TREQ +// 0x11 -> Select SPI0's RX FIFO as TREQ +// 0x12 -> Select SPI1's TX FIFO as TREQ +// 0x13 -> Select SPI1's RX FIFO as TREQ +// 0x14 -> Select UART0's TX FIFO as TREQ +// 0x15 -> Select UART0's RX FIFO as TREQ +// 0x16 -> Select UART1's TX FIFO as TREQ +// 0x17 -> Select UART1's RX FIFO as TREQ +// 0x18 -> Select PWM Counter 0's Wrap Value as TREQ +// 0x19 -> Select PWM Counter 1's Wrap Value as TREQ +// 0x1a -> Select PWM Counter 2's Wrap Value as TREQ +// 0x1b -> Select PWM Counter 3's Wrap Value as TREQ +// 0x1c -> Select PWM Counter 4's Wrap Value as TREQ +// 0x1d -> Select PWM Counter 5's Wrap Value as TREQ +// 0x1e -> Select PWM Counter 6's Wrap Value as TREQ +// 0x1f -> Select PWM Counter 7's Wrap Value as TREQ +// 0x20 -> Select I2C0's TX FIFO as TREQ +// 0x21 -> Select I2C0's RX FIFO as TREQ +// 0x22 -> Select I2C1's TX FIFO as TREQ +// 0x23 -> Select I2C1's RX FIFO as TREQ +// 0x24 -> Select the ADC as TREQ +// 0x25 -> Select the XIP Streaming FIFO as TREQ +// 0x26 -> Select the XIP SSI TX FIFO as TREQ +// 0x27 -> Select the XIP SSI RX FIFO as TREQ #define DMA_CH10_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) #define DMA_CH10_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) #define DMA_CH10_CTRL_TRIG_TREQ_SEL_MSB _u(20) @@ -4060,6 +4900,46 @@ #define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) #define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX0 _u(0x00) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX1 _u(0x01) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX2 _u(0x02) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX3 _u(0x03) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX0 _u(0x04) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX1 _u(0x05) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX2 _u(0x06) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX3 _u(0x07) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX0 _u(0x08) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX1 _u(0x09) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX2 _u(0x0a) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX3 _u(0x0b) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX0 _u(0x0c) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX1 _u(0x0d) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX2 _u(0x0e) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX3 _u(0x0f) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_TX _u(0x10) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_RX _u(0x11) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_TX _u(0x12) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_RX _u(0x13) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_UART0_TX _u(0x14) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_UART0_RX _u(0x15) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_UART1_TX _u(0x16) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_UART1_RX _u(0x17) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP0 _u(0x18) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP1 _u(0x19) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP2 _u(0x1a) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP3 _u(0x1b) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP4 _u(0x1c) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP5 _u(0x1d) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP6 _u(0x1e) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP7 _u(0x1f) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_TX _u(0x20) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_RX _u(0x21) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_TX _u(0x22) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_RX _u(0x23) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_ADC _u(0x24) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_XIP_STREAM _u(0x25) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_XIP_SSITX _u(0x26) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_XIP_SSIRX _u(0x27) // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel @@ -4438,6 +5318,46 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. +// 0x00 -> Select PIO0's TX FIFO 0 as TREQ +// 0x01 -> Select PIO0's TX FIFO 1 as TREQ +// 0x02 -> Select PIO0's TX FIFO 2 as TREQ +// 0x03 -> Select PIO0's TX FIFO 3 as TREQ +// 0x04 -> Select PIO0's RX FIFO 0 as TREQ +// 0x05 -> Select PIO0's RX FIFO 1 as TREQ +// 0x06 -> Select PIO0's RX FIFO 2 as TREQ +// 0x07 -> Select PIO0's RX FIFO 3 as TREQ +// 0x08 -> Select PIO1's TX FIFO 0 as TREQ +// 0x09 -> Select PIO1's TX FIFO 1 as TREQ +// 0x0a -> Select PIO1's TX FIFO 2 as TREQ +// 0x0b -> Select PIO1's TX FIFO 3 as TREQ +// 0x0c -> Select PIO1's RX FIFO 0 as TREQ +// 0x0d -> Select PIO1's RX FIFO 1 as TREQ +// 0x0e -> Select PIO1's RX FIFO 2 as TREQ +// 0x0f -> Select PIO1's RX FIFO 3 as TREQ +// 0x10 -> Select SPI0's TX FIFO as TREQ +// 0x11 -> Select SPI0's RX FIFO as TREQ +// 0x12 -> Select SPI1's TX FIFO as TREQ +// 0x13 -> Select SPI1's RX FIFO as TREQ +// 0x14 -> Select UART0's TX FIFO as TREQ +// 0x15 -> Select UART0's RX FIFO as TREQ +// 0x16 -> Select UART1's TX FIFO as TREQ +// 0x17 -> Select UART1's RX FIFO as TREQ +// 0x18 -> Select PWM Counter 0's Wrap Value as TREQ +// 0x19 -> Select PWM Counter 1's Wrap Value as TREQ +// 0x1a -> Select PWM Counter 2's Wrap Value as TREQ +// 0x1b -> Select PWM Counter 3's Wrap Value as TREQ +// 0x1c -> Select PWM Counter 4's Wrap Value as TREQ +// 0x1d -> Select PWM Counter 5's Wrap Value as TREQ +// 0x1e -> Select PWM Counter 6's Wrap Value as TREQ +// 0x1f -> Select PWM Counter 7's Wrap Value as TREQ +// 0x20 -> Select I2C0's TX FIFO as TREQ +// 0x21 -> Select I2C0's RX FIFO as TREQ +// 0x22 -> Select I2C1's TX FIFO as TREQ +// 0x23 -> Select I2C1's RX FIFO as TREQ +// 0x24 -> Select the ADC as TREQ +// 0x25 -> Select the XIP Streaming FIFO as TREQ +// 0x26 -> Select the XIP SSI TX FIFO as TREQ +// 0x27 -> Select the XIP SSI RX FIFO as TREQ #define DMA_CH11_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) #define DMA_CH11_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) #define DMA_CH11_CTRL_TRIG_TREQ_SEL_MSB _u(20) @@ -4448,6 +5368,46 @@ #define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) #define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX0 _u(0x00) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX1 _u(0x01) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX2 _u(0x02) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX3 _u(0x03) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX0 _u(0x04) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX1 _u(0x05) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX2 _u(0x06) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX3 _u(0x07) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX0 _u(0x08) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX1 _u(0x09) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX2 _u(0x0a) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX3 _u(0x0b) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX0 _u(0x0c) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX1 _u(0x0d) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX2 _u(0x0e) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX3 _u(0x0f) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_TX _u(0x10) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_RX _u(0x11) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_TX _u(0x12) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_RX _u(0x13) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_UART0_TX _u(0x14) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_UART0_RX _u(0x15) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_UART1_TX _u(0x16) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_UART1_RX _u(0x17) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP0 _u(0x18) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP1 _u(0x19) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP2 _u(0x1a) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP3 _u(0x1b) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP4 _u(0x1c) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP5 _u(0x1d) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP6 _u(0x1e) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP7 _u(0x1f) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_TX _u(0x20) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_RX _u(0x21) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_TX _u(0x22) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_RX _u(0x23) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_ADC _u(0x24) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_XIP_STREAM _u(0x25) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_XIP_SSITX _u(0x26) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_XIP_SSIRX _u(0x27) // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel @@ -4928,11 +5888,14 @@ // ----------------------------------------------------------------------------- // Field : DMA_SNIFF_CTRL_CALC // 0x0 -> Calculate a CRC-32 (IEEE802.3 polynomial) -// 0x1 -> Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data +// 0x1 -> Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed +// data // 0x2 -> Calculate a CRC-16-CCITT // 0x3 -> Calculate a CRC-16-CCITT with bit reversed data -// 0xe -> XOR reduction over all data. == 1 if the total 1 population count is odd. -// 0xf -> Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) +// 0xe -> XOR reduction over all data. == 1 if the total 1 population +// count is odd. +// 0xf -> Calculate a simple 32-bit checksum (addition with a 32 bit +// accumulator) #define DMA_SNIFF_CTRL_CALC_RESET _u(0x0) #define DMA_SNIFF_CTRL_CALC_BITS _u(0x000001e0) #define DMA_SNIFF_CTRL_CALC_MSB _u(8) @@ -5020,7 +5983,7 @@ #define DMA_CHAN_ABORT_RESET _u(0x00000000) #define DMA_CHAN_ABORT_MSB _u(15) #define DMA_CHAN_ABORT_LSB _u(0) -#define DMA_CHAN_ABORT_ACCESS "SC" +#define DMA_CHAN_ABORT_ACCESS "WC" // ============================================================================= // Register : DMA_N_CHANNELS // Description : The number of channels this DMA instance is equipped with. This
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/dreq.h b/src/rp2040/hardware_regs/include/hardware/regs/dreq.h index 1e86df8..4dd9009 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/dreq.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/dreq.h
@@ -105,8 +105,8 @@ DREQ_XIP_SSITX = 38, ///< Select the XIP SSI TX FIFO as DREQ DREQ_XIP_SSIRX = 39, ///< Select the XIP SSI RX FIFO as DREQ DREQ_DMA_TIMER0 = 59, ///< Select DMA_TIMER0 as DREQ - DREQ_DMA_TIMER1 = 60, ///< Select DMA_TIMER0 as DREQ - DREQ_DMA_TIMER2 = 61, ///< Select DMA_TIMER1 as DREQ + DREQ_DMA_TIMER1 = 60, ///< Select DMA_TIMER1 as DREQ + DREQ_DMA_TIMER2 = 61, ///< Select DMA_TIMER2 as DREQ DREQ_DMA_TIMER3 = 62, ///< Select DMA_TIMER3 as DREQ DREQ_FORCE = 63, ///< Select FORCE as DREQ DREQ_COUNT
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/i2c.h b/src/rp2040/hardware_regs/include/hardware/regs/i2c.h index 8196b14..c06a98d 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/i2c.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/i2c.h
@@ -1960,7 +1960,8 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Slave-Transmitter -// 0x0 -> Slave trying to transmit to remote master in read mode- scenario not present +// 0x0 -> Slave trying to transmit to remote master in read mode- +// scenario not present // 0x1 -> Slave trying to transmit to remote master in read mode #define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_RESET _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_BITS _u(0x00008000) @@ -2001,8 +2002,10 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Slave-Transmitter -// 0x0 -> Slave flushes existing data in TX-FIFO upon getting read command- scenario not present -// 0x1 -> Slave flushes existing data in TX-FIFO upon getting read command +// 0x0 -> Slave flushes existing data in TX-FIFO upon getting read +// command- scenario not present +// 0x1 -> Slave flushes existing data in TX-FIFO upon getting read +// command #define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_RESET _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_BITS _u(0x00002000) #define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_MSB _u(13) @@ -2019,7 +2022,8 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter -// 0x0 -> Master or Slave-Transmitter lost arbitration- scenario not present +// 0x0 -> Master or Slave-Transmitter lost arbitration- scenario not +// present // 0x1 -> Master or Slave-Transmitter lost arbitration #define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_RESET _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_BITS _u(0x00001000) @@ -2036,7 +2040,8 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Master-Transmitter or Master-Receiver -// 0x0 -> User initiating master operation when MASTER disabled- scenario not present +// 0x0 -> User initiating master operation when MASTER disabled- scenario +// not present // 0x1 -> User initiating master operation when MASTER disabled #define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_RESET _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_BITS _u(0x00000800) @@ -2054,8 +2059,10 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Master-Receiver -// 0x0 -> Master not trying to read in 10Bit addressing mode when RESTART disabled -// 0x1 -> Master trying to read in 10Bit addressing mode when RESTART disabled +// 0x0 -> Master not trying to read in 10Bit addressing mode when RESTART +// disabled +// 0x1 -> Master trying to read in 10Bit addressing mode when RESTART +// disabled #define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_RESET _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_BITS _u(0x00000400) #define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_MSB _u(10) @@ -2080,7 +2087,8 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Master -// 0x0 -> User trying to send START byte when RESTART disabled- scenario not present +// 0x0 -> User trying to send START byte when RESTART disabled- scenario +// not present // 0x1 -> User trying to send START byte when RESTART disabled #define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_RESET _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_BITS _u(0x00000200) @@ -2098,7 +2106,8 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Master-Transmitter or Master-Receiver -// 0x0 -> User trying to switch Master to HS mode when RESTART disabled- scenario not present +// 0x0 -> User trying to switch Master to HS mode when RESTART disabled- +// scenario not present // 0x1 -> User trying to switch Master to HS mode when RESTART disabled #define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_RESET _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_BITS _u(0x00000100) @@ -2188,7 +2197,8 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Master-Transmitter -// 0x0 -> Transmitted data non-ACKed by addressed slave-scenario not present +// 0x0 -> Transmitted data non-ACKed by addressed slave-scenario not +// present // 0x1 -> Transmitted data not ACKed by addressed slave #define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_RESET _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS _u(0x00000008)
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/intctrl.h b/src/rp2040/hardware_regs/include/hardware/regs/intctrl.h index 73172c6..702f249 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/intctrl.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/intctrl.h
@@ -55,7 +55,7 @@ TIMER_IRQ_1 = 1, ///< Select TIMER's IRQ 1 output TIMER_IRQ_2 = 2, ///< Select TIMER's IRQ 2 output TIMER_IRQ_3 = 3, ///< Select TIMER's IRQ 3 output - PWM_IRQ_WRAP = 4, ///< Select PWM's IRQ_WRAP output + PWM_IRQ_WRAP = 4, ///< Select PWM's WRAP IRQ output USBCTRL_IRQ = 5, ///< Select USBCTRL's IRQ output XIP_IRQ = 6, ///< Select XIP's IRQ output PIO0_IRQ_0 = 7, ///< Select PIO0's IRQ 0 output @@ -66,14 +66,14 @@ DMA_IRQ_1 = 12, ///< Select DMA's IRQ 1 output IO_IRQ_BANK0 = 13, ///< Select IO_BANK0's IRQ output IO_IRQ_QSPI = 14, ///< Select IO_QSPI's IRQ output - SIO_IRQ_PROC0 = 15, ///< Select SIO_PROC0's IRQ output - SIO_IRQ_PROC1 = 16, ///< Select SIO_PROC1's IRQ output + SIO_IRQ_PROC0 = 15, ///< Select SIO's PROC0 IRQ output + SIO_IRQ_PROC1 = 16, ///< Select SIO's PROC1 IRQ output CLOCKS_IRQ = 17, ///< Select CLOCKS's IRQ output SPI0_IRQ = 18, ///< Select SPI0's IRQ output SPI1_IRQ = 19, ///< Select SPI1's IRQ output UART0_IRQ = 20, ///< Select UART0's IRQ output UART1_IRQ = 21, ///< Select UART1's IRQ output - ADC_IRQ_FIFO = 22, ///< Select ADC's IRQ_FIFO output + ADC_IRQ_FIFO = 22, ///< Select ADC's FIFO IRQ output I2C0_IRQ = 23, ///< Select I2C0's IRQ output I2C1_IRQ = 24, ///< Select I2C1's IRQ output RTC_IRQ = 25, ///< Select RTC's IRQ output
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/io_bank0.h b/src/rp2040/hardware_regs/include/hardware/regs/io_bank0.h index d62c3d0..b26f4d0 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/io_bank0.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/io_bank0.h
@@ -123,7 +123,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO0_CTRL_OEOVER_RESET _u(0x0) @@ -138,7 +139,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO0_CTRL_OUTOVER_RESET _u(0x0) @@ -290,7 +292,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO1_CTRL_OEOVER_RESET _u(0x0) @@ -305,7 +308,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO1_CTRL_OUTOVER_RESET _u(0x0) @@ -457,7 +461,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO2_CTRL_OEOVER_RESET _u(0x0) @@ -472,7 +477,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO2_CTRL_OUTOVER_RESET _u(0x0) @@ -624,7 +630,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO3_CTRL_OEOVER_RESET _u(0x0) @@ -639,7 +646,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO3_CTRL_OUTOVER_RESET _u(0x0) @@ -791,7 +799,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO4_CTRL_OEOVER_RESET _u(0x0) @@ -806,7 +815,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO4_CTRL_OUTOVER_RESET _u(0x0) @@ -956,7 +966,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO5_CTRL_OEOVER_RESET _u(0x0) @@ -971,7 +982,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO5_CTRL_OUTOVER_RESET _u(0x0) @@ -1121,7 +1133,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO6_CTRL_OEOVER_RESET _u(0x0) @@ -1136,7 +1149,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO6_CTRL_OUTOVER_RESET _u(0x0) @@ -1288,7 +1302,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO7_CTRL_OEOVER_RESET _u(0x0) @@ -1303,7 +1318,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO7_CTRL_OUTOVER_RESET _u(0x0) @@ -1455,7 +1471,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO8_CTRL_OEOVER_RESET _u(0x0) @@ -1470,7 +1487,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO8_CTRL_OUTOVER_RESET _u(0x0) @@ -1622,7 +1640,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO9_CTRL_OEOVER_RESET _u(0x0) @@ -1637,7 +1656,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO9_CTRL_OUTOVER_RESET _u(0x0) @@ -1789,7 +1809,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO10_CTRL_OEOVER_RESET _u(0x0) @@ -1804,7 +1825,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO10_CTRL_OUTOVER_RESET _u(0x0) @@ -1956,7 +1978,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO11_CTRL_OEOVER_RESET _u(0x0) @@ -1971,7 +1994,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO11_CTRL_OUTOVER_RESET _u(0x0) @@ -2123,7 +2147,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO12_CTRL_OEOVER_RESET _u(0x0) @@ -2138,7 +2163,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO12_CTRL_OUTOVER_RESET _u(0x0) @@ -2290,7 +2316,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO13_CTRL_OEOVER_RESET _u(0x0) @@ -2305,7 +2332,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO13_CTRL_OUTOVER_RESET _u(0x0) @@ -2457,7 +2485,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO14_CTRL_OEOVER_RESET _u(0x0) @@ -2472,7 +2501,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO14_CTRL_OUTOVER_RESET _u(0x0) @@ -2624,7 +2654,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO15_CTRL_OEOVER_RESET _u(0x0) @@ -2639,7 +2670,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO15_CTRL_OUTOVER_RESET _u(0x0) @@ -2791,7 +2823,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO16_CTRL_OEOVER_RESET _u(0x0) @@ -2806,7 +2839,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO16_CTRL_OUTOVER_RESET _u(0x0) @@ -2958,7 +2992,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO17_CTRL_OEOVER_RESET _u(0x0) @@ -2973,7 +3008,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO17_CTRL_OUTOVER_RESET _u(0x0) @@ -3123,7 +3159,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO18_CTRL_OEOVER_RESET _u(0x0) @@ -3138,7 +3175,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO18_CTRL_OUTOVER_RESET _u(0x0) @@ -3288,7 +3326,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO19_CTRL_OEOVER_RESET _u(0x0) @@ -3303,7 +3342,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO19_CTRL_OUTOVER_RESET _u(0x0) @@ -3453,7 +3493,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO20_CTRL_OEOVER_RESET _u(0x0) @@ -3468,7 +3509,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO20_CTRL_OUTOVER_RESET _u(0x0) @@ -3620,7 +3662,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO21_CTRL_OEOVER_RESET _u(0x0) @@ -3635,7 +3678,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO21_CTRL_OUTOVER_RESET _u(0x0) @@ -3787,7 +3831,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO22_CTRL_OEOVER_RESET _u(0x0) @@ -3802,7 +3847,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO22_CTRL_OUTOVER_RESET _u(0x0) @@ -3954,7 +4000,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO23_CTRL_OEOVER_RESET _u(0x0) @@ -3969,7 +4016,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO23_CTRL_OUTOVER_RESET _u(0x0) @@ -4121,7 +4169,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO24_CTRL_OEOVER_RESET _u(0x0) @@ -4136,7 +4185,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO24_CTRL_OUTOVER_RESET _u(0x0) @@ -4288,7 +4338,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO25_CTRL_OEOVER_RESET _u(0x0) @@ -4303,7 +4354,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO25_CTRL_OUTOVER_RESET _u(0x0) @@ -4455,7 +4507,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO26_CTRL_OEOVER_RESET _u(0x0) @@ -4470,7 +4523,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO26_CTRL_OUTOVER_RESET _u(0x0) @@ -4620,7 +4674,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO27_CTRL_OEOVER_RESET _u(0x0) @@ -4635,7 +4690,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO27_CTRL_OUTOVER_RESET _u(0x0) @@ -4785,7 +4841,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO28_CTRL_OEOVER_RESET _u(0x0) @@ -4800,7 +4857,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO28_CTRL_OUTOVER_RESET _u(0x0) @@ -4950,7 +5008,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO29_CTRL_OEOVER_RESET _u(0x0) @@ -4965,7 +5024,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO29_CTRL_OUTOVER_RESET _u(0x0)
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/io_qspi.h b/src/rp2040/hardware_regs/include/hardware/regs/io_qspi.h index 3607120..74f7d91 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/io_qspi.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/io_qspi.h
@@ -123,7 +123,8 @@ // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_RESET _u(0x0) @@ -138,7 +139,8 @@ // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_RESET _u(0x0) @@ -276,7 +278,8 @@ // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_RESET _u(0x0) @@ -291,7 +294,8 @@ // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_RESET _u(0x0) @@ -429,7 +433,8 @@ // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_RESET _u(0x0) @@ -444,7 +449,8 @@ // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_RESET _u(0x0) @@ -582,7 +588,8 @@ // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_RESET _u(0x0) @@ -597,7 +604,8 @@ // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_RESET _u(0x0) @@ -735,7 +743,8 @@ // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_RESET _u(0x0) @@ -750,7 +759,8 @@ // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_RESET _u(0x0) @@ -888,7 +898,8 @@ // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_RESET _u(0x0) @@ -903,7 +914,8 @@ // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_RESET _u(0x0)
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/pwm.h b/src/rp2040/hardware_regs/include/hardware/regs/pwm.h index 3bf7947..e257ccf 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/pwm.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/pwm.h
@@ -30,7 +30,7 @@ #define PWM_CH0_CSR_PH_ADV_BITS _u(0x00000080) #define PWM_CH0_CSR_PH_ADV_MSB _u(7) #define PWM_CH0_CSR_PH_ADV_LSB _u(7) -#define PWM_CH0_CSR_PH_ADV_ACCESS "SC" +#define PWM_CH0_CSR_PH_ADV_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH0_CSR_PH_RET // Description : Retard the phase of the counter by 1 count, while it is @@ -41,7 +41,7 @@ #define PWM_CH0_CSR_PH_RET_BITS _u(0x00000040) #define PWM_CH0_CSR_PH_RET_MSB _u(6) #define PWM_CH0_CSR_PH_RET_LSB _u(6) -#define PWM_CH0_CSR_PH_RET_ACCESS "SC" +#define PWM_CH0_CSR_PH_RET_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH0_CSR_DIVMODE // 0x0 -> Free-running counting at rate dictated by fractional divider @@ -166,7 +166,7 @@ #define PWM_CH1_CSR_PH_ADV_BITS _u(0x00000080) #define PWM_CH1_CSR_PH_ADV_MSB _u(7) #define PWM_CH1_CSR_PH_ADV_LSB _u(7) -#define PWM_CH1_CSR_PH_ADV_ACCESS "SC" +#define PWM_CH1_CSR_PH_ADV_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH1_CSR_PH_RET // Description : Retard the phase of the counter by 1 count, while it is @@ -177,7 +177,7 @@ #define PWM_CH1_CSR_PH_RET_BITS _u(0x00000040) #define PWM_CH1_CSR_PH_RET_MSB _u(6) #define PWM_CH1_CSR_PH_RET_LSB _u(6) -#define PWM_CH1_CSR_PH_RET_ACCESS "SC" +#define PWM_CH1_CSR_PH_RET_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH1_CSR_DIVMODE // 0x0 -> Free-running counting at rate dictated by fractional divider @@ -302,7 +302,7 @@ #define PWM_CH2_CSR_PH_ADV_BITS _u(0x00000080) #define PWM_CH2_CSR_PH_ADV_MSB _u(7) #define PWM_CH2_CSR_PH_ADV_LSB _u(7) -#define PWM_CH2_CSR_PH_ADV_ACCESS "SC" +#define PWM_CH2_CSR_PH_ADV_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH2_CSR_PH_RET // Description : Retard the phase of the counter by 1 count, while it is @@ -313,7 +313,7 @@ #define PWM_CH2_CSR_PH_RET_BITS _u(0x00000040) #define PWM_CH2_CSR_PH_RET_MSB _u(6) #define PWM_CH2_CSR_PH_RET_LSB _u(6) -#define PWM_CH2_CSR_PH_RET_ACCESS "SC" +#define PWM_CH2_CSR_PH_RET_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH2_CSR_DIVMODE // 0x0 -> Free-running counting at rate dictated by fractional divider @@ -438,7 +438,7 @@ #define PWM_CH3_CSR_PH_ADV_BITS _u(0x00000080) #define PWM_CH3_CSR_PH_ADV_MSB _u(7) #define PWM_CH3_CSR_PH_ADV_LSB _u(7) -#define PWM_CH3_CSR_PH_ADV_ACCESS "SC" +#define PWM_CH3_CSR_PH_ADV_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH3_CSR_PH_RET // Description : Retard the phase of the counter by 1 count, while it is @@ -449,7 +449,7 @@ #define PWM_CH3_CSR_PH_RET_BITS _u(0x00000040) #define PWM_CH3_CSR_PH_RET_MSB _u(6) #define PWM_CH3_CSR_PH_RET_LSB _u(6) -#define PWM_CH3_CSR_PH_RET_ACCESS "SC" +#define PWM_CH3_CSR_PH_RET_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH3_CSR_DIVMODE // 0x0 -> Free-running counting at rate dictated by fractional divider @@ -574,7 +574,7 @@ #define PWM_CH4_CSR_PH_ADV_BITS _u(0x00000080) #define PWM_CH4_CSR_PH_ADV_MSB _u(7) #define PWM_CH4_CSR_PH_ADV_LSB _u(7) -#define PWM_CH4_CSR_PH_ADV_ACCESS "SC" +#define PWM_CH4_CSR_PH_ADV_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH4_CSR_PH_RET // Description : Retard the phase of the counter by 1 count, while it is @@ -585,7 +585,7 @@ #define PWM_CH4_CSR_PH_RET_BITS _u(0x00000040) #define PWM_CH4_CSR_PH_RET_MSB _u(6) #define PWM_CH4_CSR_PH_RET_LSB _u(6) -#define PWM_CH4_CSR_PH_RET_ACCESS "SC" +#define PWM_CH4_CSR_PH_RET_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH4_CSR_DIVMODE // 0x0 -> Free-running counting at rate dictated by fractional divider @@ -710,7 +710,7 @@ #define PWM_CH5_CSR_PH_ADV_BITS _u(0x00000080) #define PWM_CH5_CSR_PH_ADV_MSB _u(7) #define PWM_CH5_CSR_PH_ADV_LSB _u(7) -#define PWM_CH5_CSR_PH_ADV_ACCESS "SC" +#define PWM_CH5_CSR_PH_ADV_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH5_CSR_PH_RET // Description : Retard the phase of the counter by 1 count, while it is @@ -721,7 +721,7 @@ #define PWM_CH5_CSR_PH_RET_BITS _u(0x00000040) #define PWM_CH5_CSR_PH_RET_MSB _u(6) #define PWM_CH5_CSR_PH_RET_LSB _u(6) -#define PWM_CH5_CSR_PH_RET_ACCESS "SC" +#define PWM_CH5_CSR_PH_RET_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH5_CSR_DIVMODE // 0x0 -> Free-running counting at rate dictated by fractional divider @@ -846,7 +846,7 @@ #define PWM_CH6_CSR_PH_ADV_BITS _u(0x00000080) #define PWM_CH6_CSR_PH_ADV_MSB _u(7) #define PWM_CH6_CSR_PH_ADV_LSB _u(7) -#define PWM_CH6_CSR_PH_ADV_ACCESS "SC" +#define PWM_CH6_CSR_PH_ADV_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH6_CSR_PH_RET // Description : Retard the phase of the counter by 1 count, while it is @@ -857,7 +857,7 @@ #define PWM_CH6_CSR_PH_RET_BITS _u(0x00000040) #define PWM_CH6_CSR_PH_RET_MSB _u(6) #define PWM_CH6_CSR_PH_RET_LSB _u(6) -#define PWM_CH6_CSR_PH_RET_ACCESS "SC" +#define PWM_CH6_CSR_PH_RET_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH6_CSR_DIVMODE // 0x0 -> Free-running counting at rate dictated by fractional divider @@ -982,7 +982,7 @@ #define PWM_CH7_CSR_PH_ADV_BITS _u(0x00000080) #define PWM_CH7_CSR_PH_ADV_MSB _u(7) #define PWM_CH7_CSR_PH_ADV_LSB _u(7) -#define PWM_CH7_CSR_PH_ADV_ACCESS "SC" +#define PWM_CH7_CSR_PH_ADV_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH7_CSR_PH_RET // Description : Retard the phase of the counter by 1 count, while it is @@ -993,7 +993,7 @@ #define PWM_CH7_CSR_PH_RET_BITS _u(0x00000040) #define PWM_CH7_CSR_PH_RET_MSB _u(6) #define PWM_CH7_CSR_PH_RET_LSB _u(6) -#define PWM_CH7_CSR_PH_RET_ACCESS "SC" +#define PWM_CH7_CSR_PH_RET_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH7_CSR_DIVMODE // 0x0 -> Free-running counting at rate dictated by fractional divider
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/rosc.h b/src/rp2040/hardware_regs/include/hardware/regs/rosc.h index 21df157..5f412d9 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/rosc.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/rosc.h
@@ -175,7 +175,7 @@ // On power-up this field is initialised to WAKE // An invalid write will also select WAKE // Warning: setup the irq before selecting dormant mode -// 0x636f6d61 -> dormant +// 0x636f6d61 -> DORMANT // 0x77616b65 -> WAKE #define ROSC_DORMANT_OFFSET _u(0x0000000c) #define ROSC_DORMANT_BITS _u(0xffffffff)
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/ssi.h b/src/rp2040/hardware_regs/include/hardware/regs/ssi.h index f04c466..2ff46a4 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/ssi.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/ssi.h
@@ -141,7 +141,8 @@ // 0x0 -> Both transmit and receive // 0x1 -> Transmit only (not for FRF == 0, standard SPI mode) // 0x2 -> Receive only (not for FRF == 0, standard SPI mode) -// 0x3 -> EEPROM read mode (TX then RX; RX starts after control data TX'd) +// 0x3 -> EEPROM read mode (TX then RX; RX starts after control data +// TX'd) #define SSI_CTRLR0_TMOD_RESET _u(0x0) #define SSI_CTRLR0_TMOD_BITS _u(0x00000300) #define SSI_CTRLR0_TMOD_MSB _u(9) @@ -779,8 +780,10 @@ // Field : SSI_SPI_CTRLR0_TRANS_TYPE // Description : Address and instruction transfer format // 0x0 -> Command and address both in standard SPI frame format -// 0x1 -> Command in standard SPI format, address in format specified by FRF -// 0x2 -> Command and address both in format specified by FRF (e.g. Dual-SPI) +// 0x1 -> Command in standard SPI format, address in format specified by +// FRF +// 0x2 -> Command and address both in format specified by FRF (e.g. Dual- +// SPI) #define SSI_SPI_CTRLR0_TRANS_TYPE_RESET _u(0x0) #define SSI_SPI_CTRLR0_TRANS_TYPE_BITS _u(0x00000003) #define SSI_SPI_CTRLR0_TRANS_TYPE_MSB _u(1)
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/sysinfo.h b/src/rp2040/hardware_regs/include/hardware/regs/sysinfo.h index 6713721..c4118dc 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/sysinfo.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/sysinfo.h
@@ -17,24 +17,24 @@ // Description : JEDEC JEP-106 compliant chip identifier. #define SYSINFO_CHIP_ID_OFFSET _u(0x00000000) #define SYSINFO_CHIP_ID_BITS _u(0xffffffff) -#define SYSINFO_CHIP_ID_RESET _u(0x00000000) +#define SYSINFO_CHIP_ID_RESET _u(0x20002927) // ----------------------------------------------------------------------------- // Field : SYSINFO_CHIP_ID_REVISION -#define SYSINFO_CHIP_ID_REVISION_RESET "-" +#define SYSINFO_CHIP_ID_REVISION_RESET _u(0x2) #define SYSINFO_CHIP_ID_REVISION_BITS _u(0xf0000000) #define SYSINFO_CHIP_ID_REVISION_MSB _u(31) #define SYSINFO_CHIP_ID_REVISION_LSB _u(28) #define SYSINFO_CHIP_ID_REVISION_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SYSINFO_CHIP_ID_PART -#define SYSINFO_CHIP_ID_PART_RESET "-" +#define SYSINFO_CHIP_ID_PART_RESET _u(0x0002) #define SYSINFO_CHIP_ID_PART_BITS _u(0x0ffff000) #define SYSINFO_CHIP_ID_PART_MSB _u(27) #define SYSINFO_CHIP_ID_PART_LSB _u(12) #define SYSINFO_CHIP_ID_PART_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SYSINFO_CHIP_ID_MANUFACTURER -#define SYSINFO_CHIP_ID_MANUFACTURER_RESET "-" +#define SYSINFO_CHIP_ID_MANUFACTURER_RESET _u(0x926) #define SYSINFO_CHIP_ID_MANUFACTURER_BITS _u(0x00000fff) #define SYSINFO_CHIP_ID_MANUFACTURER_MSB _u(11) #define SYSINFO_CHIP_ID_MANUFACTURER_LSB _u(0) @@ -63,7 +63,7 @@ // ============================================================================= // Register : SYSINFO_GITREF_RP2040 // Description : Git hash of the chip source. Used to identify chip version. -#define SYSINFO_GITREF_RP2040_OFFSET _u(0x00000010) +#define SYSINFO_GITREF_RP2040_OFFSET _u(0x00000040) #define SYSINFO_GITREF_RP2040_BITS _u(0xffffffff) #define SYSINFO_GITREF_RP2040_RESET "-" #define SYSINFO_GITREF_RP2040_MSB _u(31)
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/usb.h b/src/rp2040/hardware_regs/include/hardware/regs/usb.h index 4f058fd..b0369c7 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/usb.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/usb.h
@@ -1012,7 +1012,7 @@ #define USB_SIE_STATUS_CONNECTED_BITS _u(0x00010000) #define USB_SIE_STATUS_CONNECTED_MSB _u(16) #define USB_SIE_STATUS_CONNECTED_LSB _u(16) -#define USB_SIE_STATUS_CONNECTED_ACCESS "RO" +#define USB_SIE_STATUS_CONNECTED_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_RESUME // Description : Host: Device has initiated a remote resume. Device: host has @@ -1037,7 +1037,7 @@ #define USB_SIE_STATUS_SPEED_BITS _u(0x00000300) #define USB_SIE_STATUS_SPEED_MSB _u(9) #define USB_SIE_STATUS_SPEED_LSB _u(8) -#define USB_SIE_STATUS_SPEED_ACCESS "RO" +#define USB_SIE_STATUS_SPEED_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_SUSPENDED // Description : Bus in suspended state. Valid for device and host. Host and @@ -1047,7 +1047,7 @@ #define USB_SIE_STATUS_SUSPENDED_BITS _u(0x00000010) #define USB_SIE_STATUS_SUSPENDED_MSB _u(4) #define USB_SIE_STATUS_SUSPENDED_LSB _u(4) -#define USB_SIE_STATUS_SUSPENDED_ACCESS "RO" +#define USB_SIE_STATUS_SUSPENDED_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_LINE_STATE // Description : USB bus line state @@ -1072,7 +1072,7 @@ #define USB_INT_EP_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_INT_EP_CTRL_INT_EP_ACTIVE -// Description : Host: Enable interrupt endpoint 1 => 15 +// Description : Host: Enable interrupt endpoint 1 -> 15 #define USB_INT_EP_CTRL_INT_EP_ACTIVE_RESET _u(0x0000) #define USB_INT_EP_CTRL_INT_EP_ACTIVE_BITS _u(0x0000fffe) #define USB_INT_EP_CTRL_INT_EP_ACTIVE_MSB _u(15) @@ -2329,7 +2329,7 @@ // Register : USB_USB_PWR // Description : Overrides for the power signals in the event that the VBUS // signals are not hooked up to GPIO. Set the value of the -// override and then the override enable so switch over to the +// override and then the override enable to switch over to the // override value. #define USB_USB_PWR_OFFSET _u(0x00000078) #define USB_USB_PWR_BITS _u(0x0000003f) @@ -2378,17 +2378,15 @@ #define USB_USB_PWR_VBUS_EN_ACCESS "RW" // ============================================================================= // Register : USB_USBPHY_DIRECT -// Description : Note that most functions are driven directly from usb_fsls -// controller. This register allows more detailed control/status -// from the USB PHY. Useful for debug but not expected to be used -// in normal operation -// Use in conjunction with usbphy_direct_override register +// Description : This register allows for direct control of the USB phy. Use in +// conjunction with usbphy_direct_override register to enable each +// override bit. #define USB_USBPHY_DIRECT_OFFSET _u(0x0000007c) #define USB_USBPHY_DIRECT_BITS _u(0x007fff77) #define USB_USBPHY_DIRECT_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DM_OVV -// Description : Status bit from USB PHY +// Description : DM over voltage #define USB_USBPHY_DIRECT_DM_OVV_RESET _u(0x0) #define USB_USBPHY_DIRECT_DM_OVV_BITS _u(0x00400000) #define USB_USBPHY_DIRECT_DM_OVV_MSB _u(22) @@ -2396,7 +2394,7 @@ #define USB_USBPHY_DIRECT_DM_OVV_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DP_OVV -// Description : Status bit from USB PHY +// Description : DP over voltage #define USB_USBPHY_DIRECT_DP_OVV_RESET _u(0x0) #define USB_USBPHY_DIRECT_DP_OVV_BITS _u(0x00200000) #define USB_USBPHY_DIRECT_DP_OVV_MSB _u(21) @@ -2404,7 +2402,7 @@ #define USB_USBPHY_DIRECT_DP_OVV_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DM_OVCN -// Description : Status bit from USB PHY +// Description : DM overcurrent #define USB_USBPHY_DIRECT_DM_OVCN_RESET _u(0x0) #define USB_USBPHY_DIRECT_DM_OVCN_BITS _u(0x00100000) #define USB_USBPHY_DIRECT_DM_OVCN_MSB _u(20) @@ -2412,7 +2410,7 @@ #define USB_USBPHY_DIRECT_DM_OVCN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DP_OVCN -// Description : Status bit from USB PHY +// Description : DP overcurrent #define USB_USBPHY_DIRECT_DP_OVCN_RESET _u(0x0) #define USB_USBPHY_DIRECT_DP_OVCN_BITS _u(0x00080000) #define USB_USBPHY_DIRECT_DP_OVCN_MSB _u(19) @@ -2420,8 +2418,7 @@ #define USB_USBPHY_DIRECT_DP_OVCN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_RX_DM -// Description : Status bit from USB PHY -// DPM pin state +// Description : DPM pin state #define USB_USBPHY_DIRECT_RX_DM_RESET _u(0x0) #define USB_USBPHY_DIRECT_RX_DM_BITS _u(0x00040000) #define USB_USBPHY_DIRECT_RX_DM_MSB _u(18) @@ -2429,8 +2426,7 @@ #define USB_USBPHY_DIRECT_RX_DM_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_RX_DP -// Description : Status bit from USB PHY -// DPP pin state +// Description : DPP pin state #define USB_USBPHY_DIRECT_RX_DP_RESET _u(0x0) #define USB_USBPHY_DIRECT_RX_DP_BITS _u(0x00020000) #define USB_USBPHY_DIRECT_RX_DP_MSB _u(17) @@ -2438,8 +2434,7 @@ #define USB_USBPHY_DIRECT_RX_DP_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_RX_DD -// Description : Status bit from USB PHY -// RX Diff data +// Description : Differential RX #define USB_USBPHY_DIRECT_RX_DD_RESET _u(0x0) #define USB_USBPHY_DIRECT_RX_DD_BITS _u(0x00010000) #define USB_USBPHY_DIRECT_RX_DD_MSB _u(16) @@ -2447,6 +2442,9 @@ #define USB_USBPHY_DIRECT_RX_DD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_DIFFMODE +// Description : TX_DIFFMODE=0: Single ended mode +// TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE +// ignored) #define USB_USBPHY_DIRECT_TX_DIFFMODE_RESET _u(0x0) #define USB_USBPHY_DIRECT_TX_DIFFMODE_BITS _u(0x00008000) #define USB_USBPHY_DIRECT_TX_DIFFMODE_MSB _u(15) @@ -2454,6 +2452,8 @@ #define USB_USBPHY_DIRECT_TX_DIFFMODE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_FSSLEW +// Description : TX_FSSLEW=0: Low speed slew rate +// TX_FSSLEW=1: Full speed slew rate #define USB_USBPHY_DIRECT_TX_FSSLEW_RESET _u(0x0) #define USB_USBPHY_DIRECT_TX_FSSLEW_BITS _u(0x00004000) #define USB_USBPHY_DIRECT_TX_FSSLEW_MSB _u(14) @@ -2461,6 +2461,8 @@ #define USB_USBPHY_DIRECT_TX_FSSLEW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_PD +// Description : TX power down override (if override enable is set). 1 = powered +// down. #define USB_USBPHY_DIRECT_TX_PD_RESET _u(0x0) #define USB_USBPHY_DIRECT_TX_PD_BITS _u(0x00002000) #define USB_USBPHY_DIRECT_TX_PD_MSB _u(13) @@ -2468,6 +2470,8 @@ #define USB_USBPHY_DIRECT_TX_PD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_RX_PD +// Description : RX power down override (if override enable is set). 1 = powered +// down. #define USB_USBPHY_DIRECT_RX_PD_RESET _u(0x0) #define USB_USBPHY_DIRECT_RX_PD_BITS _u(0x00001000) #define USB_USBPHY_DIRECT_RX_PD_MSB _u(12) @@ -2475,11 +2479,8 @@ #define USB_USBPHY_DIRECT_RX_PD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_DM -// Description : Value to drive to USB PHY when override enable is set (which -// will override the default value or value driven from USB -// controller -// TX_SEMODE=0, Ignored -// TX_SEMODE=1, Drives DPM only. TX_DM_OE=1 to enable drive. +// Description : Output data. TX_DIFFMODE=1, Ignored +// TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. // DPM=TX_DM #define USB_USBPHY_DIRECT_TX_DM_RESET _u(0x0) #define USB_USBPHY_DIRECT_TX_DM_BITS _u(0x00000800) @@ -2488,12 +2489,9 @@ #define USB_USBPHY_DIRECT_TX_DM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_DP -// Description : Value to drive to USB PHY when override enable is set (which -// will override the default value or value driven from USB -// controller -// TX_SEMODE=0, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable -// drive. DPP=TX_DP, DPM=~TX_DP -// TX_SEMODE=1, Drives DPP only. TX_DP_OE=1 to enable drive. +// Description : Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. +// TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP +// If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. // DPP=TX_DP #define USB_USBPHY_DIRECT_TX_DP_RESET _u(0x0) #define USB_USBPHY_DIRECT_TX_DP_BITS _u(0x00000400) @@ -2502,12 +2500,9 @@ #define USB_USBPHY_DIRECT_TX_DP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_DM_OE -// Description : Value to drive to USB PHY when override enable is set (which -// will override the default value or value driven from USB -// controller -// TX_SEMODE=0, Ignored. -// TX_SEMODE=1, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM -// driving +// Description : Output enable. If TX_DIFFMODE=1, Ignored. +// If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - +// DPM driving #define USB_USBPHY_DIRECT_TX_DM_OE_RESET _u(0x0) #define USB_USBPHY_DIRECT_TX_DM_OE_BITS _u(0x00000200) #define USB_USBPHY_DIRECT_TX_DM_OE_MSB _u(9) @@ -2515,13 +2510,10 @@ #define USB_USBPHY_DIRECT_TX_DM_OE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_DP_OE -// Description : Value to drive to USB PHY when override enable is set (which -// will override the default value or value driven from USB -// controller -// TX_SEMODE=0, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z -// state; 1 - DPP/DPM driving -// TX_SEMODE=1, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP -// driving +// Description : Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - +// DPP/DPM in Hi-Z state; 1 - DPP/DPM driving +// If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - +// DPP driving #define USB_USBPHY_DIRECT_TX_DP_OE_RESET _u(0x0) #define USB_USBPHY_DIRECT_TX_DP_OE_BITS _u(0x00000100) #define USB_USBPHY_DIRECT_TX_DP_OE_MSB _u(8) @@ -2529,10 +2521,7 @@ #define USB_USBPHY_DIRECT_TX_DP_OE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DM_PULLDN_EN -// Description : Value to drive to USB PHY when override enable is set (which -// will override the default value or value driven from USB -// controller -// 1 - Enable Rpd on DPM +// Description : DM pull down enable #define USB_USBPHY_DIRECT_DM_PULLDN_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_DM_PULLDN_EN_BITS _u(0x00000040) #define USB_USBPHY_DIRECT_DM_PULLDN_EN_MSB _u(6) @@ -2540,10 +2529,7 @@ #define USB_USBPHY_DIRECT_DM_PULLDN_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DM_PULLUP_EN -// Description : Value to drive to USB PHY when override enable is set (which -// will override the default value or value driven from USB -// controller -// 1 - Enable Rpu on DPM +// Description : DM pull up enable #define USB_USBPHY_DIRECT_DM_PULLUP_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_DM_PULLUP_EN_BITS _u(0x00000020) #define USB_USBPHY_DIRECT_DM_PULLUP_EN_MSB _u(5) @@ -2551,8 +2537,8 @@ #define USB_USBPHY_DIRECT_DM_PULLUP_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DM_PULLUP_HISEL -// Description : when dm_pullup_en is set high, this enables second resistor. 0 -// - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 +// Description : Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - +// Pull = Rpu1 + Rpu2 #define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_RESET _u(0x0) #define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_BITS _u(0x00000010) #define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_MSB _u(4) @@ -2560,10 +2546,7 @@ #define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DP_PULLDN_EN -// Description : Value to drive to USB PHY when override enable is set (which -// will override the default value or value driven from USB -// controller -// 1 - Enable Rpd on DPP +// Description : DP pull down enable #define USB_USBPHY_DIRECT_DP_PULLDN_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_DP_PULLDN_EN_BITS _u(0x00000004) #define USB_USBPHY_DIRECT_DP_PULLDN_EN_MSB _u(2) @@ -2571,9 +2554,7 @@ #define USB_USBPHY_DIRECT_DP_PULLDN_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DP_PULLUP_EN -// Description : Value to drive to USB PHY when override enable is set (which -// will override the default value or value driven from USB -// controller +// Description : DP pull up enable #define USB_USBPHY_DIRECT_DP_PULLUP_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_DP_PULLUP_EN_BITS _u(0x00000002) #define USB_USBPHY_DIRECT_DP_PULLUP_EN_MSB _u(1) @@ -2581,8 +2562,8 @@ #define USB_USBPHY_DIRECT_DP_PULLUP_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DP_PULLUP_HISEL -// Description : when dp_pullup_en is set high, this enables second resistor. 0 -// - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 +// Description : Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - +// Pull = Rpu1 + Rpu2 #define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_RESET _u(0x0) #define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_BITS _u(0x00000001) #define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_MSB _u(0) @@ -2590,6 +2571,7 @@ #define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_ACCESS "RW" // ============================================================================= // Register : USB_USBPHY_DIRECT_OVERRIDE +// Description : Override enable for each control in usbphy_direct #define USB_USBPHY_DIRECT_OVERRIDE_OFFSET _u(0x00000080) #define USB_USBPHY_DIRECT_OVERRIDE_BITS _u(0x00009fff) #define USB_USBPHY_DIRECT_OVERRIDE_RESET _u(0x00000000) @@ -2630,8 +2612,6 @@ #define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN -// Description : Override default value or value driven from USB Controller to -// PHY #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_BITS _u(0x00000100) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_MSB _u(8) @@ -2639,8 +2619,6 @@ #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN -// Description : Override default value or value driven from USB Controller to -// PHY #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_BITS _u(0x00000080) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_MSB _u(7) @@ -2648,8 +2626,6 @@ #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN -// Description : Override default value or value driven from USB Controller to -// PHY #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_BITS _u(0x00000040) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_MSB _u(6) @@ -2657,8 +2633,6 @@ #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN -// Description : Override default value or value driven from USB Controller to -// PHY #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_BITS _u(0x00000020) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_MSB _u(5) @@ -2666,8 +2640,6 @@ #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN -// Description : Override default value or value driven from USB Controller to -// PHY #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_BITS _u(0x00000010) #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_MSB _u(4) @@ -2675,8 +2647,6 @@ #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN -// Description : Override default value or value driven from USB Controller to -// PHY #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_BITS _u(0x00000008) #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_MSB _u(3) @@ -2684,8 +2654,6 @@ #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN -// Description : Override default value or value driven from USB Controller to -// PHY #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BITS _u(0x00000004) #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_MSB _u(2) @@ -2707,10 +2675,7 @@ #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW" // ============================================================================= // Register : USB_USBPHY_TRIM -// Description : Note that most functions are driven directly from usb_fsls -// controller. This register allows more detailed control/status -// from the USB PHY. Useful for debug but not expected to be used -// in normal operation +// Description : Used to adjust trim values of USB phy pull down resistors. #define USB_USBPHY_TRIM_OFFSET _u(0x00000084) #define USB_USBPHY_TRIM_BITS _u(0x00001f1f) #define USB_USBPHY_TRIM_RESET _u(0x00001f1f) @@ -2780,7 +2745,7 @@ // ----------------------------------------------------------------------------- // Field : USB_INTR_DEV_RESUME_FROM_HOST // Description : Set when the device receives a resume from the host. Cleared by -// writing to SIE_STATUS.RESUME_REMOTE +// writing to SIE_STATUS.RESUME #define USB_INTR_DEV_RESUME_FROM_HOST_RESET _u(0x0) #define USB_INTR_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) #define USB_INTR_DEV_RESUME_FROM_HOST_MSB _u(15) @@ -2814,7 +2779,7 @@ #define USB_INTR_BUS_RESET_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_VBUS_DETECT -// Description : Source: SIE_STATUS.VBUS_DETECT +// Description : Source: SIE_STATUS.VBUS_DETECTED #define USB_INTR_VBUS_DETECT_RESET _u(0x0) #define USB_INTR_VBUS_DETECT_BITS _u(0x00000800) #define USB_INTR_VBUS_DETECT_MSB _u(11) @@ -2898,7 +2863,7 @@ // ----------------------------------------------------------------------------- // Field : USB_INTR_HOST_RESUME // Description : Host: raised when a device wakes up the host. Cleared by -// writing to SIE_STATUS.RESUME_REMOTE +// writing to SIE_STATUS.RESUME #define USB_INTR_HOST_RESUME_RESET _u(0x0) #define USB_INTR_HOST_RESUME_BITS _u(0x00000002) #define USB_INTR_HOST_RESUME_MSB _u(1) @@ -2958,7 +2923,7 @@ // ----------------------------------------------------------------------------- // Field : USB_INTE_DEV_RESUME_FROM_HOST // Description : Set when the device receives a resume from the host. Cleared by -// writing to SIE_STATUS.RESUME_REMOTE +// writing to SIE_STATUS.RESUME #define USB_INTE_DEV_RESUME_FROM_HOST_RESET _u(0x0) #define USB_INTE_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) #define USB_INTE_DEV_RESUME_FROM_HOST_MSB _u(15) @@ -2992,7 +2957,7 @@ #define USB_INTE_BUS_RESET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_VBUS_DETECT -// Description : Source: SIE_STATUS.VBUS_DETECT +// Description : Source: SIE_STATUS.VBUS_DETECTED #define USB_INTE_VBUS_DETECT_RESET _u(0x0) #define USB_INTE_VBUS_DETECT_BITS _u(0x00000800) #define USB_INTE_VBUS_DETECT_MSB _u(11) @@ -3076,7 +3041,7 @@ // ----------------------------------------------------------------------------- // Field : USB_INTE_HOST_RESUME // Description : Host: raised when a device wakes up the host. Cleared by -// writing to SIE_STATUS.RESUME_REMOTE +// writing to SIE_STATUS.RESUME #define USB_INTE_HOST_RESUME_RESET _u(0x0) #define USB_INTE_HOST_RESUME_BITS _u(0x00000002) #define USB_INTE_HOST_RESUME_MSB _u(1) @@ -3136,7 +3101,7 @@ // ----------------------------------------------------------------------------- // Field : USB_INTF_DEV_RESUME_FROM_HOST // Description : Set when the device receives a resume from the host. Cleared by -// writing to SIE_STATUS.RESUME_REMOTE +// writing to SIE_STATUS.RESUME #define USB_INTF_DEV_RESUME_FROM_HOST_RESET _u(0x0) #define USB_INTF_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) #define USB_INTF_DEV_RESUME_FROM_HOST_MSB _u(15) @@ -3170,7 +3135,7 @@ #define USB_INTF_BUS_RESET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_VBUS_DETECT -// Description : Source: SIE_STATUS.VBUS_DETECT +// Description : Source: SIE_STATUS.VBUS_DETECTED #define USB_INTF_VBUS_DETECT_RESET _u(0x0) #define USB_INTF_VBUS_DETECT_BITS _u(0x00000800) #define USB_INTF_VBUS_DETECT_MSB _u(11) @@ -3254,7 +3219,7 @@ // ----------------------------------------------------------------------------- // Field : USB_INTF_HOST_RESUME // Description : Host: raised when a device wakes up the host. Cleared by -// writing to SIE_STATUS.RESUME_REMOTE +// writing to SIE_STATUS.RESUME #define USB_INTF_HOST_RESUME_RESET _u(0x0) #define USB_INTF_HOST_RESUME_BITS _u(0x00000002) #define USB_INTF_HOST_RESUME_MSB _u(1) @@ -3314,7 +3279,7 @@ // ----------------------------------------------------------------------------- // Field : USB_INTS_DEV_RESUME_FROM_HOST // Description : Set when the device receives a resume from the host. Cleared by -// writing to SIE_STATUS.RESUME_REMOTE +// writing to SIE_STATUS.RESUME #define USB_INTS_DEV_RESUME_FROM_HOST_RESET _u(0x0) #define USB_INTS_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) #define USB_INTS_DEV_RESUME_FROM_HOST_MSB _u(15) @@ -3348,7 +3313,7 @@ #define USB_INTS_BUS_RESET_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_VBUS_DETECT -// Description : Source: SIE_STATUS.VBUS_DETECT +// Description : Source: SIE_STATUS.VBUS_DETECTED #define USB_INTS_VBUS_DETECT_RESET _u(0x0) #define USB_INTS_VBUS_DETECT_BITS _u(0x00000800) #define USB_INTS_VBUS_DETECT_MSB _u(11) @@ -3432,7 +3397,7 @@ // ----------------------------------------------------------------------------- // Field : USB_INTS_HOST_RESUME // Description : Host: raised when a device wakes up the host. Cleared by -// writing to SIE_STATUS.RESUME_REMOTE +// writing to SIE_STATUS.RESUME #define USB_INTS_HOST_RESUME_RESET _u(0x0) #define USB_INTS_HOST_RESUME_BITS _u(0x00000002) #define USB_INTS_HOST_RESUME_MSB _u(1)
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/xosc.h b/src/rp2040/hardware_regs/include/hardware/regs/xosc.h index b1e1613..da923d5 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/xosc.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/xosc.h
@@ -24,9 +24,9 @@ // Description : On power-up this field is initialised to DISABLE and the chip // runs from the ROSC. // If the chip has subsequently been programmed to run from the -// XOSC then DISABLE may lock-up the chip. If this is a concern -// then run the clk_ref from the ROSC and enable the clk_sys RESUS -// feature. +// XOSC then setting this field to DISABLE may lock-up the chip. +// If this is a concern then run the clk_ref from the ROSC and +// enable the clk_sys RESUS feature. // The 12-bit code is intended to give some protection against // accidental writes. An invalid setting will enable the // oscillator. @@ -41,9 +41,7 @@ #define XOSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab) // ----------------------------------------------------------------------------- // Field : XOSC_CTRL_FREQ_RANGE -// Description : Frequency range. An invalid setting will retain the previous -// value. The actual value being used can be read from -// STATUS_FREQ_RANGE. This resets to 0xAA0 and cannot be changed. +// Description : Frequency range. This resets to 0xAA0 and cannot be changed. // 0xaa0 -> 1_15MHZ // 0xaa1 -> RESERVED_1 // 0xaa2 -> RESERVED_2 @@ -111,9 +109,9 @@ // This is used to save power by pausing the XOSC // On power-up this field is initialised to WAKE // An invalid write will also select WAKE -// Warning: stop the PLLs before selecting dormant mode -// Warning: setup the irq before selecting dormant mode -// 0x636f6d61 -> dormant +// WARNING: stop the PLLs before selecting dormant mode +// WARNING: setup the irq before selecting dormant mode +// 0x636f6d61 -> DORMANT // 0x77616b65 -> WAKE #define XOSC_DORMANT_OFFSET _u(0x00000008) #define XOSC_DORMANT_BITS _u(0xffffffff)
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/clocks.h b/src/rp2040/hardware_structs/include/hardware/structs/clocks.h index f1efe7b..e655e80 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/clocks.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/clocks.h
@@ -22,7 +22,6 @@ // // Bit-field descriptions are of the form: // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - /** \brief Clock numbers on RP2040 (used as typedef \ref clock_num_t) * \ingroup hardware_clocks */ @@ -203,7 +202,7 @@ // 0x04000000 [26] CLK_PERI_SPI1 (1) // 0x02000000 [25] CLK_SYS_SPI0 (1) // 0x01000000 [24] CLK_PERI_SPI0 (1) - // 0x00800000 [23] CLK_SYS_SIOB (1) + // 0x00800000 [23] CLK_SYS_SIO (1) // 0x00400000 [22] CLK_SYS_RTC (1) // 0x00200000 [21] CLK_RTC_RTC (1) // 0x00100000 [20] CLK_SYS_ROSC (1) @@ -298,7 +297,7 @@ // 0x04000000 [26] CLK_PERI_SPI1 (1) // 0x02000000 [25] CLK_SYS_SPI0 (1) // 0x01000000 [24] CLK_PERI_SPI0 (1) - // 0x00800000 [23] CLK_SYS_SIOB (1) + // 0x00800000 [23] CLK_SYS_SIO (1) // 0x00400000 [22] CLK_SYS_RTC (1) // 0x00200000 [21] CLK_RTC_RTC (1) // 0x00100000 [20] CLK_SYS_ROSC (1) @@ -393,7 +392,7 @@ // 0x04000000 [26] CLK_PERI_SPI1 (0) // 0x02000000 [25] CLK_SYS_SPI0 (0) // 0x01000000 [24] CLK_PERI_SPI0 (0) - // 0x00800000 [23] CLK_SYS_SIOB (0) + // 0x00800000 [23] CLK_SYS_SIO (0) // 0x00400000 [22] CLK_SYS_RTC (0) // 0x00200000 [21] CLK_RTC_RTC (0) // 0x00100000 [20] CLK_SYS_ROSC (0)
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/dma.h b/src/rp2040/hardware_structs/include/hardware/structs/dma.h index 9a1aec9..5a0e938 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/dma.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/dma.h
@@ -229,7 +229,7 @@ _REG_(DMA_CHAN_ABORT_OFFSET) // DMA_CHAN_ABORT // Abort an in-progress transfer sequence on one or more channels // 0x0000ffff [15:0] CHAN_ABORT (0x0000) Each bit corresponds to a channel - io_wo_32 abort; + io_rw_32 abort; } dma_hw_t; #define dma_hw ((dma_hw_t *)DMA_BASE)
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/sysinfo.h b/src/rp2040/hardware_structs/include/hardware/structs/sysinfo.h index 30b8175..1d8fa91 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/sysinfo.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/sysinfo.h
@@ -26,9 +26,9 @@ typedef struct { _REG_(SYSINFO_CHIP_ID_OFFSET) // SYSINFO_CHIP_ID // JEDEC JEP-106 compliant chip identifier - // 0xf0000000 [31:28] REVISION (-) - // 0x0ffff000 [27:12] PART (-) - // 0x00000fff [11:0] MANUFACTURER (-) + // 0xf0000000 [31:28] REVISION (0x2) + // 0x0ffff000 [27:12] PART (0x0002) + // 0x00000fff [11:0] MANUFACTURER (0x926) io_ro_32 chip_id; _REG_(SYSINFO_PLATFORM_OFFSET) // SYSINFO_PLATFORM @@ -37,7 +37,7 @@ // 0x00000001 [0] FPGA (0) io_ro_32 platform; - uint32_t _pad0[2]; + uint32_t _pad0[14]; _REG_(SYSINFO_GITREF_RP2040_OFFSET) // SYSINFO_GITREF_RP2040 // Git hash of the chip source @@ -46,6 +46,6 @@ } sysinfo_hw_t; #define sysinfo_hw ((sysinfo_hw_t *)SYSINFO_BASE) -static_assert(sizeof (sysinfo_hw_t) == 0x0014, ""); +static_assert(sizeof (sysinfo_hw_t) == 0x0044, ""); #endif // _HARDWARE_STRUCTS_SYSINFO_H
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/tbman.h b/src/rp2040/hardware_structs/include/hardware/structs/tbman.h index 78a5f3b..269e72f 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/tbman.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/tbman.h
@@ -35,4 +35,3 @@ static_assert(sizeof (tbman_hw_t) == 0x0004, ""); #endif // _HARDWARE_STRUCTS_TBMAN_H -
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/usb.h b/src/rp2040/hardware_structs/include/hardware/structs/usb.h index 167437c..8abb613 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/usb.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/usb.h
@@ -109,7 +109,7 @@ _REG_(USB_INT_EP_CTRL_OFFSET) // USB_INT_EP_CTRL // interrupt endpoint control register - // 0x0000fffe [15:1] INT_EP_ACTIVE (0x0000) Host: Enable interrupt endpoint 1 => 15 + // 0x0000fffe [15:1] INT_EP_ACTIVE (0x0000) Host: Enable interrupt endpoint 1 -> 15 io_rw_32 int_ep_ctrl; _REG_(USB_BUFF_STATUS_OFFSET) // USB_BUFF_STATUS @@ -323,49 +323,50 @@ io_rw_32 pwr; _REG_(USB_USBPHY_DIRECT_OFFSET) // USB_USBPHY_DIRECT - // Note that most functions are driven directly from usb_fsls controller - // 0x00400000 [22] DM_OVV (0) Status bit from USB PHY - // 0x00200000 [21] DP_OVV (0) Status bit from USB PHY - // 0x00100000 [20] DM_OVCN (0) Status bit from USB PHY - // 0x00080000 [19] DP_OVCN (0) Status bit from USB PHY - // 0x00040000 [18] RX_DM (0) Status bit from USB PHY + - // 0x00020000 [17] RX_DP (0) Status bit from USB PHY + - // 0x00010000 [16] RX_DD (0) Status bit from USB PHY + - // 0x00008000 [15] TX_DIFFMODE (0) - // 0x00004000 [14] TX_FSSLEW (0) - // 0x00002000 [13] TX_PD (0) - // 0x00001000 [12] RX_PD (0) - // 0x00000800 [11] TX_DM (0) Value to drive to USB PHY when override enable is set... - // 0x00000400 [10] TX_DP (0) Value to drive to USB PHY when override enable is set... - // 0x00000200 [9] TX_DM_OE (0) Value to drive to USB PHY when override enable is set... - // 0x00000100 [8] TX_DP_OE (0) Value to drive to USB PHY when override enable is set... - // 0x00000040 [6] DM_PULLDN_EN (0) Value to drive to USB PHY when override enable is set... - // 0x00000020 [5] DM_PULLUP_EN (0) Value to drive to USB PHY when override enable is set... - // 0x00000010 [4] DM_PULLUP_HISEL (0) when dm_pullup_en is set high, this enables second resistor - // 0x00000004 [2] DP_PULLDN_EN (0) Value to drive to USB PHY when override enable is set... - // 0x00000002 [1] DP_PULLUP_EN (0) Value to drive to USB PHY when override enable is set... - // 0x00000001 [0] DP_PULLUP_HISEL (0) when dp_pullup_en is set high, this enables second resistor + // This register allows for direct control of the USB phy + // 0x00400000 [22] DM_OVV (0) DM over voltage + // 0x00200000 [21] DP_OVV (0) DP over voltage + // 0x00100000 [20] DM_OVCN (0) DM overcurrent + // 0x00080000 [19] DP_OVCN (0) DP overcurrent + // 0x00040000 [18] RX_DM (0) DPM pin state + // 0x00020000 [17] RX_DP (0) DPP pin state + // 0x00010000 [16] RX_DD (0) Differential RX + // 0x00008000 [15] TX_DIFFMODE (0) TX_DIFFMODE=0: Single ended mode + + // 0x00004000 [14] TX_FSSLEW (0) TX_FSSLEW=0: Low speed slew rate + + // 0x00002000 [13] TX_PD (0) TX power down override (if override enable is set) + // 0x00001000 [12] RX_PD (0) RX power down override (if override enable is set) + // 0x00000800 [11] TX_DM (0) Output data + // 0x00000400 [10] TX_DP (0) Output data + // 0x00000200 [9] TX_DM_OE (0) Output enable + // 0x00000100 [8] TX_DP_OE (0) Output enable + // 0x00000040 [6] DM_PULLDN_EN (0) DM pull down enable + // 0x00000020 [5] DM_PULLUP_EN (0) DM pull up enable + // 0x00000010 [4] DM_PULLUP_HISEL (0) Enable the second DM pull up resistor + // 0x00000004 [2] DP_PULLDN_EN (0) DP pull down enable + // 0x00000002 [1] DP_PULLUP_EN (0) DP pull up enable + // 0x00000001 [0] DP_PULLUP_HISEL (0) Enable the second DP pull up resistor io_rw_32 phy_direct; _REG_(USB_USBPHY_DIRECT_OVERRIDE_OFFSET) // USB_USBPHY_DIRECT_OVERRIDE + // Override enable for each control in usbphy_direct // 0x00008000 [15] TX_DIFFMODE_OVERRIDE_EN (0) // 0x00001000 [12] DM_PULLUP_OVERRIDE_EN (0) // 0x00000800 [11] TX_FSSLEW_OVERRIDE_EN (0) // 0x00000400 [10] TX_PD_OVERRIDE_EN (0) // 0x00000200 [9] RX_PD_OVERRIDE_EN (0) - // 0x00000100 [8] TX_DM_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY - // 0x00000080 [7] TX_DP_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY - // 0x00000040 [6] TX_DM_OE_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY - // 0x00000020 [5] TX_DP_OE_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY - // 0x00000010 [4] DM_PULLDN_EN_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY - // 0x00000008 [3] DP_PULLDN_EN_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY - // 0x00000004 [2] DP_PULLUP_EN_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY + // 0x00000100 [8] TX_DM_OVERRIDE_EN (0) + // 0x00000080 [7] TX_DP_OVERRIDE_EN (0) + // 0x00000040 [6] TX_DM_OE_OVERRIDE_EN (0) + // 0x00000020 [5] TX_DP_OE_OVERRIDE_EN (0) + // 0x00000010 [4] DM_PULLDN_EN_OVERRIDE_EN (0) + // 0x00000008 [3] DP_PULLDN_EN_OVERRIDE_EN (0) + // 0x00000004 [2] DP_PULLUP_EN_OVERRIDE_EN (0) // 0x00000002 [1] DM_PULLUP_HISEL_OVERRIDE_EN (0) // 0x00000001 [0] DP_PULLUP_HISEL_OVERRIDE_EN (0) io_rw_32 phy_direct_override; _REG_(USB_USBPHY_TRIM_OFFSET) // USB_USBPHY_TRIM - // Note that most functions are driven directly from usb_fsls controller + // Used to adjust trim values of USB phy pull down resistors // 0x00001f00 [12:8] DM_PULLDN_TRIM (0x1f) Value to drive to USB PHY + // 0x0000001f [4:0] DP_PULLDN_TRIM (0x1f) Value to drive to USB PHY + io_rw_32 phy_trim;
diff --git a/src/rp2350/hardware_regs/RP2350.svd b/src/rp2350/hardware_regs/RP2350.svd index d134962..44bf2e4 100644 --- a/src/rp2350/hardware_regs/RP2350.svd +++ b/src/rp2350/hardware_regs/RP2350.svd
@@ -4,7 +4,8 @@ SPDX-License-Identifier: BSD-3-Clause --> -<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd"> <vendor>Raspberry Pi</vendor> +<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd"> + <vendor>Raspberry Pi</vendor> <name>RP2350</name> <series>RP</series> <version>0.1</version> @@ -62,8 +63,8 @@ <peripherals> <peripheral> <name>ACCESSCTRL</name> - <description>Hardware access control registers</description> <baseAddress>0x40060000</baseAddress> + <description>Hardware access control registers</description> <addressBlock> <offset>0</offset> <size>236</size> @@ -131,6 +132,7 @@ <name>CFGRESET</name> <bitRange>[0:0]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> </fields> </register> @@ -1802,9 +1804,9 @@ </fields> </register> <register> - <name>ADC0</name> + <name>ADC</name> <addressOffset>0x0000007c</addressOffset> - <description>Control whether debugger, DMA, core 0 and core 1 can access ADC0, and at what security/privilege levels they can do so. + <description>Control whether debugger, DMA, core 0 and core 1 can access ADC, and at what security/privilege levels they can do so. Defaults to Secure access from any master. @@ -1813,49 +1815,49 @@ <fields> <field> <name>DBG</name> - <description>If 1, ADC0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description> + <description>If 1, ADC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description> <bitRange>[7:7]</bitRange> <access>read-write</access> </field> <field> <name>DMA</name> - <description>If 1, ADC0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description> + <description>If 1, ADC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description> <bitRange>[6:6]</bitRange> <access>read-write</access> </field> <field> <name>CORE1</name> - <description>If 1, ADC0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description> + <description>If 1, ADC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description> <bitRange>[5:5]</bitRange> <access>read-write</access> </field> <field> <name>CORE0</name> - <description>If 1, ADC0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description> + <description>If 1, ADC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description> <bitRange>[4:4]</bitRange> <access>read-write</access> </field> <field> <name>SP</name> - <description>If 1, ADC0 can be accessed from a Secure, Privileged context.</description> + <description>If 1, ADC can be accessed from a Secure, Privileged context.</description> <bitRange>[3:3]</bitRange> <access>read-write</access> </field> <field> <name>SU</name> - <description>If 1, and SP is also set, ADC0 can be accessed from a Secure, Unprivileged context.</description> + <description>If 1, and SP is also set, ADC can be accessed from a Secure, Unprivileged context.</description> <bitRange>[2:2]</bitRange> <access>read-write</access> </field> <field> <name>NSP</name> - <description>If 1, ADC0 can be accessed from a Non-secure, Privileged context.</description> + <description>If 1, ADC can be accessed from a Non-secure, Privileged context.</description> <bitRange>[1:1]</bitRange> <access>read-write</access> </field> <field> <name>NSU</name> - <description>If 1, and NSP is also set, ADC0 can be accessed from a Non-secure, Unprivileged context. + <description>If 1, and NSP is also set, ADC can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description> <bitRange>[0:0]</bitRange> @@ -3290,9 +3292,9 @@ </fields> </register> <register> - <name>RSM</name> + <name>PSM</name> <addressOffset>0x000000dc</addressOffset> - <description>Control whether debugger, DMA, core 0 and core 1 can access RSM, and at what security/privilege levels they can do so. + <description>Control whether debugger, DMA, core 0 and core 1 can access PSM, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. @@ -3301,49 +3303,49 @@ <fields> <field> <name>DBG</name> - <description>If 1, RSM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description> + <description>If 1, PSM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description> <bitRange>[7:7]</bitRange> <access>read-write</access> </field> <field> <name>DMA</name> - <description>If 1, RSM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description> + <description>If 1, PSM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description> <bitRange>[6:6]</bitRange> <access>read-write</access> </field> <field> <name>CORE1</name> - <description>If 1, RSM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description> + <description>If 1, PSM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description> <bitRange>[5:5]</bitRange> <access>read-write</access> </field> <field> <name>CORE0</name> - <description>If 1, RSM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description> + <description>If 1, PSM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.</description> <bitRange>[4:4]</bitRange> <access>read-write</access> </field> <field> <name>SP</name> - <description>If 1, RSM can be accessed from a Secure, Privileged context.</description> + <description>If 1, PSM can be accessed from a Secure, Privileged context.</description> <bitRange>[3:3]</bitRange> <access>read-write</access> </field> <field> <name>SU</name> - <description>If 1, and SP is also set, RSM can be accessed from a Secure, Unprivileged context.</description> + <description>If 1, and SP is also set, PSM can be accessed from a Secure, Unprivileged context.</description> <bitRange>[2:2]</bitRange> <access>read-write</access> </field> <field> <name>NSP</name> - <description>If 1, RSM can be accessed from a Non-secure, Privileged context.</description> + <description>If 1, PSM can be accessed from a Non-secure, Privileged context.</description> <bitRange>[1:1]</bitRange> <access>read-write</access> </field> <field> <name>NSU</name> - <description>If 1, and NSP is also set, RSM can be accessed from a Non-secure, Unprivileged context. + <description>If 1, and NSP is also set, PSM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.</description> <bitRange>[0:0]</bitRange> @@ -3541,17 +3543,13 @@ </peripheral> <peripheral> <name>ADC</name> - <description>Control and data interface to SAR ADC</description> <baseAddress>0x400a0000</baseAddress> + <description>Control and data interface to SAR ADC</description> <addressBlock> <offset>0</offset> <size>36</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>ADC_IRQ_FIFO</name> - <value>35</value> - </interrupt> <registers> <register> <name>CS</name> @@ -3606,6 +3604,7 @@ <description>Start a single conversion. Self-clearing. Ignored if start_many is asserted.</description> <bitRange>[2:2]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>TS_EN</name> @@ -3808,11 +3807,15 @@ </fields> </register> </registers> + <interrupt> + <name>ADC_IRQ_FIFO</name> + <value>35</value> + </interrupt> </peripheral> <peripheral> <name>BOOTRAM</name> - <description>Additional registers mapped adjacent to the bootram, for use by the bootrom.</description> <baseAddress>0x400e0000</baseAddress> + <description>Additional registers mapped adjacent to the bootram, for use by the bootrom.</description> <addressBlock> <offset>0</offset> <size>2092</size> @@ -3966,8 +3969,8 @@ </peripheral> <peripheral> <name>BUSCTRL</name> - <description>Register block for busfabric control signals and performance counters</description> <baseAddress>0x40068000</baseAddress> + <description>Register block for busfabric control signals and performance counters</description> <addressBlock> <offset>0</offset> <size>44</size> @@ -4067,35 +4070,35 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>siob_proc1_stall_upstream</name> + <name>sio_proc1_stall_upstream</name> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc1_stall_downstream</name> + <name>sio_proc1_stall_downstream</name> <value>1</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc1_access_contested</name> + <name>sio_proc1_access_contested</name> <value>2</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc1_access</name> + <name>sio_proc1_access</name> <value>3</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc0_stall_upstream</name> + <name>sio_proc0_stall_upstream</name> <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc0_stall_downstream</name> + <name>sio_proc0_stall_downstream</name> <value>5</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc0_access_contested</name> + <name>sio_proc0_access_contested</name> <value>6</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc0_access</name> + <name>sio_proc0_access</name> <value>7</value> </enumeratedValue> <enumeratedValue> @@ -4372,35 +4375,35 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>siob_proc1_stall_upstream</name> + <name>sio_proc1_stall_upstream</name> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc1_stall_downstream</name> + <name>sio_proc1_stall_downstream</name> <value>1</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc1_access_contested</name> + <name>sio_proc1_access_contested</name> <value>2</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc1_access</name> + <name>sio_proc1_access</name> <value>3</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc0_stall_upstream</name> + <name>sio_proc0_stall_upstream</name> <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc0_stall_downstream</name> + <name>sio_proc0_stall_downstream</name> <value>5</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc0_access_contested</name> + <name>sio_proc0_access_contested</name> <value>6</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc0_access</name> + <name>sio_proc0_access</name> <value>7</value> </enumeratedValue> <enumeratedValue> @@ -4677,35 +4680,35 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>siob_proc1_stall_upstream</name> + <name>sio_proc1_stall_upstream</name> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc1_stall_downstream</name> + <name>sio_proc1_stall_downstream</name> <value>1</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc1_access_contested</name> + <name>sio_proc1_access_contested</name> <value>2</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc1_access</name> + <name>sio_proc1_access</name> <value>3</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc0_stall_upstream</name> + <name>sio_proc0_stall_upstream</name> <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc0_stall_downstream</name> + <name>sio_proc0_stall_downstream</name> <value>5</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc0_access_contested</name> + <name>sio_proc0_access_contested</name> <value>6</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc0_access</name> + <name>sio_proc0_access</name> <value>7</value> </enumeratedValue> <enumeratedValue> @@ -4982,35 +4985,35 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>siob_proc1_stall_upstream</name> + <name>sio_proc1_stall_upstream</name> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc1_stall_downstream</name> + <name>sio_proc1_stall_downstream</name> <value>1</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc1_access_contested</name> + <name>sio_proc1_access_contested</name> <value>2</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc1_access</name> + <name>sio_proc1_access</name> <value>3</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc0_stall_upstream</name> + <name>sio_proc0_stall_upstream</name> <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc0_stall_downstream</name> + <name>sio_proc0_stall_downstream</name> <value>5</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc0_access_contested</name> + <name>sio_proc0_access_contested</name> <value>6</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc0_access</name> + <name>sio_proc0_access</name> <value>7</value> </enumeratedValue> <enumeratedValue> @@ -5267,10 +5270,6 @@ <size>212</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>CLOCKS_IRQ</name> - <value>30</value> - </interrupt> <registers> <register> <name>CLK_GPOUT0_CTRL</name> @@ -7808,11 +7807,15 @@ </fields> </register> </registers> + <interrupt> + <name>CLOCKS_IRQ</name> + <value>30</value> + </interrupt> </peripheral> <peripheral> <name>CORESIGHT_TRACE</name> - <description>Coresight block - RP specific registers</description> <baseAddress>0x50700000</baseAddress> + <description>Coresight block - RP specific registers</description> <addressBlock> <offset>0</offset> <size>8</size> @@ -7872,29 +7875,13 @@ </peripheral> <peripheral> <name>DMA</name> - <description>DMA with separate read and write masters</description> <baseAddress>0x50000000</baseAddress> + <description>DMA with separate read and write masters</description> <addressBlock> <offset>0</offset> <size>3016</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>DMA_IRQ_0</name> - <value>10</value> - </interrupt> - <interrupt> - <name>DMA_IRQ_1</name> - <value>11</value> - </interrupt> - <interrupt> - <name>DMA_IRQ_2</name> - <value>12</value> - </interrupt> - <interrupt> - <name>DMA_IRQ_3</name> - <value>13</value> - </interrupt> <registers> <register> <name>CH0_READ_ADDR</name> @@ -8040,6 +8027,31 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>TIMER0</name> + <value>59</value> + <description>Select Timer 0 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER1</name> + <value>60</value> + <description>Select Timer 1 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER2</name> + <value>61</value> + <description>Select Timer 2 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER3</name> + <value>62</value> + <description>Select Timer 3 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>PERMANENT</name> + <value>63</value> + <description>Permanent request, for unpaced transfers.</description> + </enumeratedValue> + <enumeratedValue> <name>PIO0_TX0</name> <value>0</value> <description>Select PIO0's TX FIFO 0 as TREQ</description> @@ -8252,12 +8264,12 @@ <enumeratedValue> <name>PWM_WRAP10</name> <value>42</value> - <description>Select PWM Counter 0's Wrap Value as TREQ</description> + <description>Select PWM Counter 10's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>PWM_WRAP11</name> <value>43</value> - <description>Select PWM Counter 1's Wrap Value as TREQ</description> + <description>Select PWM Counter 11's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>I2C0_TX</name> @@ -8314,31 +8326,6 @@ <value>54</value> <description>Select SHA256 as TREQ</description> </enumeratedValue> - <enumeratedValue> - <name>TIMER0</name> - <value>59</value> - <description>Select Timer 0 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER1</name> - <value>60</value> - <description>Select Timer 1 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER2</name> - <value>61</value> - <description>Select Timer 2 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER3</name> - <value>62</value> - <description>Select Timer 3 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>PERMANENT</name> - <value>63</value> - <description>Permanent request, for unpaced transfers.</description> - </enumeratedValue> </enumeratedValues> </field> <field> @@ -8745,6 +8732,31 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>TIMER0</name> + <value>59</value> + <description>Select Timer 0 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER1</name> + <value>60</value> + <description>Select Timer 1 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER2</name> + <value>61</value> + <description>Select Timer 2 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER3</name> + <value>62</value> + <description>Select Timer 3 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>PERMANENT</name> + <value>63</value> + <description>Permanent request, for unpaced transfers.</description> + </enumeratedValue> + <enumeratedValue> <name>PIO0_TX0</name> <value>0</value> <description>Select PIO0's TX FIFO 0 as TREQ</description> @@ -8957,12 +8969,12 @@ <enumeratedValue> <name>PWM_WRAP10</name> <value>42</value> - <description>Select PWM Counter 0's Wrap Value as TREQ</description> + <description>Select PWM Counter 10's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>PWM_WRAP11</name> <value>43</value> - <description>Select PWM Counter 1's Wrap Value as TREQ</description> + <description>Select PWM Counter 11's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>I2C0_TX</name> @@ -9019,31 +9031,6 @@ <value>54</value> <description>Select SHA256 as TREQ</description> </enumeratedValue> - <enumeratedValue> - <name>TIMER0</name> - <value>59</value> - <description>Select Timer 0 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER1</name> - <value>60</value> - <description>Select Timer 1 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER2</name> - <value>61</value> - <description>Select Timer 2 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER3</name> - <value>62</value> - <description>Select Timer 3 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>PERMANENT</name> - <value>63</value> - <description>Permanent request, for unpaced transfers.</description> - </enumeratedValue> </enumeratedValues> </field> <field> @@ -9450,6 +9437,31 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>TIMER0</name> + <value>59</value> + <description>Select Timer 0 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER1</name> + <value>60</value> + <description>Select Timer 1 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER2</name> + <value>61</value> + <description>Select Timer 2 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER3</name> + <value>62</value> + <description>Select Timer 3 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>PERMANENT</name> + <value>63</value> + <description>Permanent request, for unpaced transfers.</description> + </enumeratedValue> + <enumeratedValue> <name>PIO0_TX0</name> <value>0</value> <description>Select PIO0's TX FIFO 0 as TREQ</description> @@ -9662,12 +9674,12 @@ <enumeratedValue> <name>PWM_WRAP10</name> <value>42</value> - <description>Select PWM Counter 0's Wrap Value as TREQ</description> + <description>Select PWM Counter 10's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>PWM_WRAP11</name> <value>43</value> - <description>Select PWM Counter 1's Wrap Value as TREQ</description> + <description>Select PWM Counter 11's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>I2C0_TX</name> @@ -9724,31 +9736,6 @@ <value>54</value> <description>Select SHA256 as TREQ</description> </enumeratedValue> - <enumeratedValue> - <name>TIMER0</name> - <value>59</value> - <description>Select Timer 0 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER1</name> - <value>60</value> - <description>Select Timer 1 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER2</name> - <value>61</value> - <description>Select Timer 2 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER3</name> - <value>62</value> - <description>Select Timer 3 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>PERMANENT</name> - <value>63</value> - <description>Permanent request, for unpaced transfers.</description> - </enumeratedValue> </enumeratedValues> </field> <field> @@ -10155,6 +10142,31 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>TIMER0</name> + <value>59</value> + <description>Select Timer 0 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER1</name> + <value>60</value> + <description>Select Timer 1 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER2</name> + <value>61</value> + <description>Select Timer 2 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER3</name> + <value>62</value> + <description>Select Timer 3 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>PERMANENT</name> + <value>63</value> + <description>Permanent request, for unpaced transfers.</description> + </enumeratedValue> + <enumeratedValue> <name>PIO0_TX0</name> <value>0</value> <description>Select PIO0's TX FIFO 0 as TREQ</description> @@ -10367,12 +10379,12 @@ <enumeratedValue> <name>PWM_WRAP10</name> <value>42</value> - <description>Select PWM Counter 0's Wrap Value as TREQ</description> + <description>Select PWM Counter 10's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>PWM_WRAP11</name> <value>43</value> - <description>Select PWM Counter 1's Wrap Value as TREQ</description> + <description>Select PWM Counter 11's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>I2C0_TX</name> @@ -10429,31 +10441,6 @@ <value>54</value> <description>Select SHA256 as TREQ</description> </enumeratedValue> - <enumeratedValue> - <name>TIMER0</name> - <value>59</value> - <description>Select Timer 0 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER1</name> - <value>60</value> - <description>Select Timer 1 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER2</name> - <value>61</value> - <description>Select Timer 2 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER3</name> - <value>62</value> - <description>Select Timer 3 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>PERMANENT</name> - <value>63</value> - <description>Permanent request, for unpaced transfers.</description> - </enumeratedValue> </enumeratedValues> </field> <field> @@ -10860,6 +10847,31 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>TIMER0</name> + <value>59</value> + <description>Select Timer 0 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER1</name> + <value>60</value> + <description>Select Timer 1 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER2</name> + <value>61</value> + <description>Select Timer 2 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER3</name> + <value>62</value> + <description>Select Timer 3 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>PERMANENT</name> + <value>63</value> + <description>Permanent request, for unpaced transfers.</description> + </enumeratedValue> + <enumeratedValue> <name>PIO0_TX0</name> <value>0</value> <description>Select PIO0's TX FIFO 0 as TREQ</description> @@ -11072,12 +11084,12 @@ <enumeratedValue> <name>PWM_WRAP10</name> <value>42</value> - <description>Select PWM Counter 0's Wrap Value as TREQ</description> + <description>Select PWM Counter 10's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>PWM_WRAP11</name> <value>43</value> - <description>Select PWM Counter 1's Wrap Value as TREQ</description> + <description>Select PWM Counter 11's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>I2C0_TX</name> @@ -11134,31 +11146,6 @@ <value>54</value> <description>Select SHA256 as TREQ</description> </enumeratedValue> - <enumeratedValue> - <name>TIMER0</name> - <value>59</value> - <description>Select Timer 0 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER1</name> - <value>60</value> - <description>Select Timer 1 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER2</name> - <value>61</value> - <description>Select Timer 2 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER3</name> - <value>62</value> - <description>Select Timer 3 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>PERMANENT</name> - <value>63</value> - <description>Permanent request, for unpaced transfers.</description> - </enumeratedValue> </enumeratedValues> </field> <field> @@ -11565,6 +11552,31 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>TIMER0</name> + <value>59</value> + <description>Select Timer 0 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER1</name> + <value>60</value> + <description>Select Timer 1 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER2</name> + <value>61</value> + <description>Select Timer 2 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER3</name> + <value>62</value> + <description>Select Timer 3 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>PERMANENT</name> + <value>63</value> + <description>Permanent request, for unpaced transfers.</description> + </enumeratedValue> + <enumeratedValue> <name>PIO0_TX0</name> <value>0</value> <description>Select PIO0's TX FIFO 0 as TREQ</description> @@ -11777,12 +11789,12 @@ <enumeratedValue> <name>PWM_WRAP10</name> <value>42</value> - <description>Select PWM Counter 0's Wrap Value as TREQ</description> + <description>Select PWM Counter 10's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>PWM_WRAP11</name> <value>43</value> - <description>Select PWM Counter 1's Wrap Value as TREQ</description> + <description>Select PWM Counter 11's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>I2C0_TX</name> @@ -11839,31 +11851,6 @@ <value>54</value> <description>Select SHA256 as TREQ</description> </enumeratedValue> - <enumeratedValue> - <name>TIMER0</name> - <value>59</value> - <description>Select Timer 0 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER1</name> - <value>60</value> - <description>Select Timer 1 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER2</name> - <value>61</value> - <description>Select Timer 2 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER3</name> - <value>62</value> - <description>Select Timer 3 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>PERMANENT</name> - <value>63</value> - <description>Permanent request, for unpaced transfers.</description> - </enumeratedValue> </enumeratedValues> </field> <field> @@ -12270,6 +12257,31 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>TIMER0</name> + <value>59</value> + <description>Select Timer 0 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER1</name> + <value>60</value> + <description>Select Timer 1 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER2</name> + <value>61</value> + <description>Select Timer 2 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER3</name> + <value>62</value> + <description>Select Timer 3 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>PERMANENT</name> + <value>63</value> + <description>Permanent request, for unpaced transfers.</description> + </enumeratedValue> + <enumeratedValue> <name>PIO0_TX0</name> <value>0</value> <description>Select PIO0's TX FIFO 0 as TREQ</description> @@ -12482,12 +12494,12 @@ <enumeratedValue> <name>PWM_WRAP10</name> <value>42</value> - <description>Select PWM Counter 0's Wrap Value as TREQ</description> + <description>Select PWM Counter 10's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>PWM_WRAP11</name> <value>43</value> - <description>Select PWM Counter 1's Wrap Value as TREQ</description> + <description>Select PWM Counter 11's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>I2C0_TX</name> @@ -12544,31 +12556,6 @@ <value>54</value> <description>Select SHA256 as TREQ</description> </enumeratedValue> - <enumeratedValue> - <name>TIMER0</name> - <value>59</value> - <description>Select Timer 0 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER1</name> - <value>60</value> - <description>Select Timer 1 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER2</name> - <value>61</value> - <description>Select Timer 2 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER3</name> - <value>62</value> - <description>Select Timer 3 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>PERMANENT</name> - <value>63</value> - <description>Permanent request, for unpaced transfers.</description> - </enumeratedValue> </enumeratedValues> </field> <field> @@ -12975,6 +12962,31 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>TIMER0</name> + <value>59</value> + <description>Select Timer 0 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER1</name> + <value>60</value> + <description>Select Timer 1 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER2</name> + <value>61</value> + <description>Select Timer 2 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER3</name> + <value>62</value> + <description>Select Timer 3 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>PERMANENT</name> + <value>63</value> + <description>Permanent request, for unpaced transfers.</description> + </enumeratedValue> + <enumeratedValue> <name>PIO0_TX0</name> <value>0</value> <description>Select PIO0's TX FIFO 0 as TREQ</description> @@ -13187,12 +13199,12 @@ <enumeratedValue> <name>PWM_WRAP10</name> <value>42</value> - <description>Select PWM Counter 0's Wrap Value as TREQ</description> + <description>Select PWM Counter 10's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>PWM_WRAP11</name> <value>43</value> - <description>Select PWM Counter 1's Wrap Value as TREQ</description> + <description>Select PWM Counter 11's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>I2C0_TX</name> @@ -13249,31 +13261,6 @@ <value>54</value> <description>Select SHA256 as TREQ</description> </enumeratedValue> - <enumeratedValue> - <name>TIMER0</name> - <value>59</value> - <description>Select Timer 0 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER1</name> - <value>60</value> - <description>Select Timer 1 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER2</name> - <value>61</value> - <description>Select Timer 2 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER3</name> - <value>62</value> - <description>Select Timer 3 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>PERMANENT</name> - <value>63</value> - <description>Permanent request, for unpaced transfers.</description> - </enumeratedValue> </enumeratedValues> </field> <field> @@ -13680,6 +13667,31 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>TIMER0</name> + <value>59</value> + <description>Select Timer 0 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER1</name> + <value>60</value> + <description>Select Timer 1 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER2</name> + <value>61</value> + <description>Select Timer 2 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER3</name> + <value>62</value> + <description>Select Timer 3 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>PERMANENT</name> + <value>63</value> + <description>Permanent request, for unpaced transfers.</description> + </enumeratedValue> + <enumeratedValue> <name>PIO0_TX0</name> <value>0</value> <description>Select PIO0's TX FIFO 0 as TREQ</description> @@ -13892,12 +13904,12 @@ <enumeratedValue> <name>PWM_WRAP10</name> <value>42</value> - <description>Select PWM Counter 0's Wrap Value as TREQ</description> + <description>Select PWM Counter 10's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>PWM_WRAP11</name> <value>43</value> - <description>Select PWM Counter 1's Wrap Value as TREQ</description> + <description>Select PWM Counter 11's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>I2C0_TX</name> @@ -13954,31 +13966,6 @@ <value>54</value> <description>Select SHA256 as TREQ</description> </enumeratedValue> - <enumeratedValue> - <name>TIMER0</name> - <value>59</value> - <description>Select Timer 0 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER1</name> - <value>60</value> - <description>Select Timer 1 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER2</name> - <value>61</value> - <description>Select Timer 2 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER3</name> - <value>62</value> - <description>Select Timer 3 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>PERMANENT</name> - <value>63</value> - <description>Permanent request, for unpaced transfers.</description> - </enumeratedValue> </enumeratedValues> </field> <field> @@ -14385,6 +14372,31 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>TIMER0</name> + <value>59</value> + <description>Select Timer 0 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER1</name> + <value>60</value> + <description>Select Timer 1 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER2</name> + <value>61</value> + <description>Select Timer 2 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER3</name> + <value>62</value> + <description>Select Timer 3 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>PERMANENT</name> + <value>63</value> + <description>Permanent request, for unpaced transfers.</description> + </enumeratedValue> + <enumeratedValue> <name>PIO0_TX0</name> <value>0</value> <description>Select PIO0's TX FIFO 0 as TREQ</description> @@ -14597,12 +14609,12 @@ <enumeratedValue> <name>PWM_WRAP10</name> <value>42</value> - <description>Select PWM Counter 0's Wrap Value as TREQ</description> + <description>Select PWM Counter 10's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>PWM_WRAP11</name> <value>43</value> - <description>Select PWM Counter 1's Wrap Value as TREQ</description> + <description>Select PWM Counter 11's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>I2C0_TX</name> @@ -14659,31 +14671,6 @@ <value>54</value> <description>Select SHA256 as TREQ</description> </enumeratedValue> - <enumeratedValue> - <name>TIMER0</name> - <value>59</value> - <description>Select Timer 0 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER1</name> - <value>60</value> - <description>Select Timer 1 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER2</name> - <value>61</value> - <description>Select Timer 2 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER3</name> - <value>62</value> - <description>Select Timer 3 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>PERMANENT</name> - <value>63</value> - <description>Permanent request, for unpaced transfers.</description> - </enumeratedValue> </enumeratedValues> </field> <field> @@ -15090,6 +15077,31 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>TIMER0</name> + <value>59</value> + <description>Select Timer 0 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER1</name> + <value>60</value> + <description>Select Timer 1 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER2</name> + <value>61</value> + <description>Select Timer 2 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER3</name> + <value>62</value> + <description>Select Timer 3 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>PERMANENT</name> + <value>63</value> + <description>Permanent request, for unpaced transfers.</description> + </enumeratedValue> + <enumeratedValue> <name>PIO0_TX0</name> <value>0</value> <description>Select PIO0's TX FIFO 0 as TREQ</description> @@ -15302,12 +15314,12 @@ <enumeratedValue> <name>PWM_WRAP10</name> <value>42</value> - <description>Select PWM Counter 0's Wrap Value as TREQ</description> + <description>Select PWM Counter 10's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>PWM_WRAP11</name> <value>43</value> - <description>Select PWM Counter 1's Wrap Value as TREQ</description> + <description>Select PWM Counter 11's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>I2C0_TX</name> @@ -15364,31 +15376,6 @@ <value>54</value> <description>Select SHA256 as TREQ</description> </enumeratedValue> - <enumeratedValue> - <name>TIMER0</name> - <value>59</value> - <description>Select Timer 0 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER1</name> - <value>60</value> - <description>Select Timer 1 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER2</name> - <value>61</value> - <description>Select Timer 2 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER3</name> - <value>62</value> - <description>Select Timer 3 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>PERMANENT</name> - <value>63</value> - <description>Permanent request, for unpaced transfers.</description> - </enumeratedValue> </enumeratedValues> </field> <field> @@ -15795,6 +15782,31 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>TIMER0</name> + <value>59</value> + <description>Select Timer 0 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER1</name> + <value>60</value> + <description>Select Timer 1 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER2</name> + <value>61</value> + <description>Select Timer 2 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER3</name> + <value>62</value> + <description>Select Timer 3 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>PERMANENT</name> + <value>63</value> + <description>Permanent request, for unpaced transfers.</description> + </enumeratedValue> + <enumeratedValue> <name>PIO0_TX0</name> <value>0</value> <description>Select PIO0's TX FIFO 0 as TREQ</description> @@ -16007,12 +16019,12 @@ <enumeratedValue> <name>PWM_WRAP10</name> <value>42</value> - <description>Select PWM Counter 0's Wrap Value as TREQ</description> + <description>Select PWM Counter 10's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>PWM_WRAP11</name> <value>43</value> - <description>Select PWM Counter 1's Wrap Value as TREQ</description> + <description>Select PWM Counter 11's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>I2C0_TX</name> @@ -16069,31 +16081,6 @@ <value>54</value> <description>Select SHA256 as TREQ</description> </enumeratedValue> - <enumeratedValue> - <name>TIMER0</name> - <value>59</value> - <description>Select Timer 0 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER1</name> - <value>60</value> - <description>Select Timer 1 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER2</name> - <value>61</value> - <description>Select Timer 2 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER3</name> - <value>62</value> - <description>Select Timer 3 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>PERMANENT</name> - <value>63</value> - <description>Permanent request, for unpaced transfers.</description> - </enumeratedValue> </enumeratedValues> </field> <field> @@ -16500,6 +16487,31 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>TIMER0</name> + <value>59</value> + <description>Select Timer 0 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER1</name> + <value>60</value> + <description>Select Timer 1 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER2</name> + <value>61</value> + <description>Select Timer 2 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER3</name> + <value>62</value> + <description>Select Timer 3 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>PERMANENT</name> + <value>63</value> + <description>Permanent request, for unpaced transfers.</description> + </enumeratedValue> + <enumeratedValue> <name>PIO0_TX0</name> <value>0</value> <description>Select PIO0's TX FIFO 0 as TREQ</description> @@ -16712,12 +16724,12 @@ <enumeratedValue> <name>PWM_WRAP10</name> <value>42</value> - <description>Select PWM Counter 0's Wrap Value as TREQ</description> + <description>Select PWM Counter 10's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>PWM_WRAP11</name> <value>43</value> - <description>Select PWM Counter 1's Wrap Value as TREQ</description> + <description>Select PWM Counter 11's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>I2C0_TX</name> @@ -16774,31 +16786,6 @@ <value>54</value> <description>Select SHA256 as TREQ</description> </enumeratedValue> - <enumeratedValue> - <name>TIMER0</name> - <value>59</value> - <description>Select Timer 0 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER1</name> - <value>60</value> - <description>Select Timer 1 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER2</name> - <value>61</value> - <description>Select Timer 2 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER3</name> - <value>62</value> - <description>Select Timer 3 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>PERMANENT</name> - <value>63</value> - <description>Permanent request, for unpaced transfers.</description> - </enumeratedValue> </enumeratedValues> </field> <field> @@ -17205,6 +17192,31 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>TIMER0</name> + <value>59</value> + <description>Select Timer 0 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER1</name> + <value>60</value> + <description>Select Timer 1 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER2</name> + <value>61</value> + <description>Select Timer 2 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER3</name> + <value>62</value> + <description>Select Timer 3 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>PERMANENT</name> + <value>63</value> + <description>Permanent request, for unpaced transfers.</description> + </enumeratedValue> + <enumeratedValue> <name>PIO0_TX0</name> <value>0</value> <description>Select PIO0's TX FIFO 0 as TREQ</description> @@ -17417,12 +17429,12 @@ <enumeratedValue> <name>PWM_WRAP10</name> <value>42</value> - <description>Select PWM Counter 0's Wrap Value as TREQ</description> + <description>Select PWM Counter 10's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>PWM_WRAP11</name> <value>43</value> - <description>Select PWM Counter 1's Wrap Value as TREQ</description> + <description>Select PWM Counter 11's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>I2C0_TX</name> @@ -17479,31 +17491,6 @@ <value>54</value> <description>Select SHA256 as TREQ</description> </enumeratedValue> - <enumeratedValue> - <name>TIMER0</name> - <value>59</value> - <description>Select Timer 0 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER1</name> - <value>60</value> - <description>Select Timer 1 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER2</name> - <value>61</value> - <description>Select Timer 2 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER3</name> - <value>62</value> - <description>Select Timer 3 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>PERMANENT</name> - <value>63</value> - <description>Permanent request, for unpaced transfers.</description> - </enumeratedValue> </enumeratedValues> </field> <field> @@ -17910,6 +17897,31 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>TIMER0</name> + <value>59</value> + <description>Select Timer 0 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER1</name> + <value>60</value> + <description>Select Timer 1 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER2</name> + <value>61</value> + <description>Select Timer 2 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER3</name> + <value>62</value> + <description>Select Timer 3 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>PERMANENT</name> + <value>63</value> + <description>Permanent request, for unpaced transfers.</description> + </enumeratedValue> + <enumeratedValue> <name>PIO0_TX0</name> <value>0</value> <description>Select PIO0's TX FIFO 0 as TREQ</description> @@ -18122,12 +18134,12 @@ <enumeratedValue> <name>PWM_WRAP10</name> <value>42</value> - <description>Select PWM Counter 0's Wrap Value as TREQ</description> + <description>Select PWM Counter 10's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>PWM_WRAP11</name> <value>43</value> - <description>Select PWM Counter 1's Wrap Value as TREQ</description> + <description>Select PWM Counter 11's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>I2C0_TX</name> @@ -18184,31 +18196,6 @@ <value>54</value> <description>Select SHA256 as TREQ</description> </enumeratedValue> - <enumeratedValue> - <name>TIMER0</name> - <value>59</value> - <description>Select Timer 0 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER1</name> - <value>60</value> - <description>Select Timer 1 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER2</name> - <value>61</value> - <description>Select Timer 2 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER3</name> - <value>62</value> - <description>Select Timer 3 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>PERMANENT</name> - <value>63</value> - <description>Permanent request, for unpaced transfers.</description> - </enumeratedValue> </enumeratedValues> </field> <field> @@ -18615,6 +18602,31 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>TIMER0</name> + <value>59</value> + <description>Select Timer 0 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER1</name> + <value>60</value> + <description>Select Timer 1 as TREQ</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER2</name> + <value>61</value> + <description>Select Timer 2 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>TIMER3</name> + <value>62</value> + <description>Select Timer 3 as TREQ (Optional)</description> + </enumeratedValue> + <enumeratedValue> + <name>PERMANENT</name> + <value>63</value> + <description>Permanent request, for unpaced transfers.</description> + </enumeratedValue> + <enumeratedValue> <name>PIO0_TX0</name> <value>0</value> <description>Select PIO0's TX FIFO 0 as TREQ</description> @@ -18827,12 +18839,12 @@ <enumeratedValue> <name>PWM_WRAP10</name> <value>42</value> - <description>Select PWM Counter 0's Wrap Value as TREQ</description> + <description>Select PWM Counter 10's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>PWM_WRAP11</name> <value>43</value> - <description>Select PWM Counter 1's Wrap Value as TREQ</description> + <description>Select PWM Counter 11's Wrap Value as TREQ</description> </enumeratedValue> <enumeratedValue> <name>I2C0_TX</name> @@ -18889,31 +18901,6 @@ <value>54</value> <description>Select SHA256 as TREQ</description> </enumeratedValue> - <enumeratedValue> - <name>TIMER0</name> - <value>59</value> - <description>Select Timer 0 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER1</name> - <value>60</value> - <description>Select Timer 1 as TREQ</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER2</name> - <value>61</value> - <description>Select Timer 2 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>TIMER3</name> - <value>62</value> - <description>Select Timer 3 as TREQ (Optional)</description> - </enumeratedValue> - <enumeratedValue> - <name>PERMANENT</name> - <value>63</value> - <description>Permanent request, for unpaced transfers.</description> - </enumeratedValue> </enumeratedValues> </field> <field> @@ -19248,29 +19235,6 @@ </fields> </register> <register> - <name>INTR1</name> - <addressOffset>0x00000410</addressOffset> - <description>Interrupt Status (raw)</description> - <resetValue>0x00000000</resetValue> - <fields> - <field> - <name>INTR1</name> - <description>Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. - - Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. - - The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. - - It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. - - If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes.</description> - <bitRange>[15:0]</bitRange> - <access>read-write</access> - <modifiedWriteValues>oneToClear</modifiedWriteValues> - </field> - </fields> - </register> - <register> <name>INTE1</name> <addressOffset>0x00000414</addressOffset> <description>Interrupt Enables for IRQ 1</description> @@ -19319,29 +19283,6 @@ </fields> </register> <register> - <name>INTR2</name> - <addressOffset>0x00000420</addressOffset> - <description>Interrupt Status (raw)</description> - <resetValue>0x00000000</resetValue> - <fields> - <field> - <name>INTR2</name> - <description>Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. - - Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. - - The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. - - It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. - - If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes.</description> - <bitRange>[15:0]</bitRange> - <access>read-write</access> - <modifiedWriteValues>oneToClear</modifiedWriteValues> - </field> - </fields> - </register> - <register> <name>INTE2</name> <addressOffset>0x00000424</addressOffset> <description>Interrupt Enables for IRQ 2</description> @@ -19390,29 +19331,6 @@ </fields> </register> <register> - <name>INTR3</name> - <addressOffset>0x00000430</addressOffset> - <description>Interrupt Status (raw)</description> - <resetValue>0x00000000</resetValue> - <fields> - <field> - <name>INTR3</name> - <description>Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. - - Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. - - The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. - - It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. - - If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes.</description> - <bitRange>[15:0]</bitRange> - <access>read-write</access> - <modifiedWriteValues>oneToClear</modifiedWriteValues> - </field> - </fields> - </register> - <register> <name>INTE3</name> <addressOffset>0x00000434</addressOffset> <description>Interrupt Enables for IRQ 3</description> @@ -19555,6 +19473,7 @@ <description>Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy.</description> <bitRange>[15:0]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> </fields> </register> @@ -21356,11 +21275,27 @@ </fields> </register> </registers> + <interrupt> + <name>DMA_IRQ_0</name> + <value>10</value> + </interrupt> + <interrupt> + <name>DMA_IRQ_1</name> + <value>11</value> + </interrupt> + <interrupt> + <name>DMA_IRQ_2</name> + <value>12</value> + </interrupt> + <interrupt> + <name>DMA_IRQ_3</name> + <value>13</value> + </interrupt> </peripheral> <peripheral> <name>EPPB</name> - <description>Cortex-M33 EPPB vendor register block for RP2350</description> <baseAddress>0xe0080000</baseAddress> + <description>Cortex-M33 EPPB vendor register block for RP2350</description> <addressBlock> <offset>0</offset> <size>12</size> @@ -21383,7 +21318,7 @@ <register> <name>NMI_MASK1</name> <addressOffset>0x00000004</addressOffset> - <description>NMI mask for IRQs 0 though 51. This register is core-local, and is reset by a processor warm reset.</description> + <description>NMI mask for IRQs 32 though 51. This register is core-local, and is reset by a processor warm reset.</description> <resetValue>0x00000000</resetValue> <fields> <field> @@ -21425,8 +21360,8 @@ </peripheral> <peripheral> <name>GLITCH_DETECTOR</name> - <description>Glitch detector controls</description> <baseAddress>0x40158000</baseAddress> + <description>Glitch detector controls</description> <addressBlock> <offset>0</offset> <size>24</size> @@ -21627,6 +21562,7 @@ <name>TRIG_FORCE</name> <bitRange>[3:0]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> </fields> </register> @@ -21634,8 +21570,8 @@ </peripheral> <peripheral> <name>HSTX_CTRL</name> - <description>Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block.</description> <baseAddress>0x400c0000</baseAddress> + <description>Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block.</description> <addressBlock> <offset>0</offset> <size>44</size> @@ -22027,37 +21963,37 @@ <fields> <field> <name>L2_NBITS</name> - <description>Number of valid data bits for the lane 2 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits.</description> + <description>Number of valid data bits for the lane 2 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits. Remaining LSBs are masked to 0 after the rotate.</description> <bitRange>[23:21]</bitRange> <access>read-write</access> </field> <field> <name>L2_ROT</name> - <description>Right-rotate applied to the current shifter data before the lane 2 TMDS encoder.</description> + <description>Right-rotate applied to the current shifter data before the lane 2 TMDS encoder. Remaining LSBs are masked to 0 after the rotate.</description> <bitRange>[20:16]</bitRange> <access>read-write</access> </field> <field> <name>L1_NBITS</name> - <description>Number of valid data bits for the lane 1 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits.</description> + <description>Number of valid data bits for the lane 1 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits. Remaining LSBs are masked to 0 after the rotate.</description> <bitRange>[15:13]</bitRange> <access>read-write</access> </field> <field> <name>L1_ROT</name> - <description>Right-rotate applied to the current shifter data before the lane 1 TMDS encoder.</description> + <description>Right-rotate applied to the current shifter data before the lane 1 TMDS encoder. Remaining LSBs are masked to 0 after the rotate.</description> <bitRange>[12:8]</bitRange> <access>read-write</access> </field> <field> <name>L0_NBITS</name> - <description>Number of valid data bits for the lane 0 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits.</description> + <description>Number of valid data bits for the lane 0 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits. Remaining LSBs are masked to 0 after the rotate.</description> <bitRange>[7:5]</bitRange> <access>read-write</access> </field> <field> <name>L0_ROT</name> - <description>Right-rotate applied to the current shifter data before the lane 0 TMDS encoder.</description> + <description>Right-rotate applied to the current shifter data before the lane 0 TMDS encoder. Remaining LSBs are masked to 0 after the rotate.</description> <bitRange>[4:0]</bitRange> <access>read-write</access> </field> @@ -22067,8 +22003,8 @@ </peripheral> <peripheral> <name>HSTX_FIFO</name> - <description>FIFO status and write access for HSTX</description> <baseAddress>0x50600000</baseAddress> + <description>FIFO status and write access for HSTX</description> <addressBlock> <offset>0</offset> <size>8</size> @@ -22122,6 +22058,7 @@ </peripheral> <peripheral> <name>I2C0</name> + <baseAddress>0x40090000</baseAddress> <description>DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): @@ -22194,16 +22131,11 @@ IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 IC_DEFAULT_UFM_SPKLEN ............. 0x1 IC_TX_BUFFER_DEPTH ................ 16</description> - <baseAddress>0x40090000</baseAddress> <addressBlock> <offset>0</offset> <size>256</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>I2C0_IRQ</name> - <value>36</value> - </interrupt> <registers> <register> <name>IC_CON</name> @@ -22535,6 +22467,7 @@ Reset value: 0x0</description> <bitRange>[10:10]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> <name>DISABLE</name> @@ -22555,6 +22488,7 @@ - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0</description> <bitRange>[9:9]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> <name>DISABLE</name> @@ -22579,6 +22513,7 @@ Reset value: 0x0</description> <bitRange>[8:8]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> <name>WRITE</name> @@ -24750,6 +24685,10 @@ </fields> </register> </registers> + <interrupt> + <name>I2C0_IRQ</name> + <value>36</value> + </interrupt> </peripheral> <peripheral derivedFrom="I2C0"> <name>I2C1</name> @@ -24767,14 +24706,6 @@ <size>800</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>IO_IRQ_BANK0</name> - <value>21</value> - </interrupt> - <interrupt> - <name>IO_IRQ_BANK0_NS</name> - <value>22</value> - </interrupt> <registers> <register> <name>GPIO0_STATUS</name> @@ -24948,7 +24879,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_0</name> + <name>sio_0</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -25151,7 +25082,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_1</name> + <name>sio_1</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -25354,7 +25285,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_2</name> + <name>sio_2</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -25561,7 +25492,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_3</name> + <name>sio_3</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -25764,7 +25695,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_4</name> + <name>sio_4</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -25963,7 +25894,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_5</name> + <name>sio_5</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -26162,7 +26093,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_6</name> + <name>sio_6</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -26361,7 +26292,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_7</name> + <name>sio_7</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -26560,7 +26491,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_8</name> + <name>sio_8</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -26759,7 +26690,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_9</name> + <name>sio_9</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -26954,7 +26885,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_10</name> + <name>sio_10</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -27153,7 +27084,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_11</name> + <name>sio_11</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -27356,7 +27287,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_12</name> + <name>sio_12</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -27559,7 +27490,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_13</name> + <name>sio_13</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -27762,7 +27693,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_14</name> + <name>sio_14</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -27969,7 +27900,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_15</name> + <name>sio_15</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -28176,7 +28107,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_16</name> + <name>sio_16</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -28375,7 +28306,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_17</name> + <name>sio_17</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -28574,7 +28505,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_18</name> + <name>sio_18</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -28777,7 +28708,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_19</name> + <name>sio_19</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -28980,7 +28911,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_20</name> + <name>sio_20</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -29179,7 +29110,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_21</name> + <name>sio_21</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -29378,7 +29309,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_22</name> + <name>sio_22</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -29581,7 +29512,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_23</name> + <name>sio_23</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -29784,7 +29715,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_24</name> + <name>sio_24</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -29983,7 +29914,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_25</name> + <name>sio_25</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -30182,7 +30113,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_26</name> + <name>sio_26</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -30381,7 +30312,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_27</name> + <name>sio_27</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -30580,7 +30511,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_28</name> + <name>sio_28</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -30775,7 +30706,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_29</name> + <name>sio_29</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -30970,7 +30901,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_30</name> + <name>sio_30</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -31169,7 +31100,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_31</name> + <name>sio_31</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -31368,7 +31299,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_32</name> + <name>sio_32</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -31563,7 +31494,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_33</name> + <name>sio_33</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -31758,7 +31689,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_34</name> + <name>sio_34</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -31957,7 +31888,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_35</name> + <name>sio_35</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -32156,7 +32087,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_36</name> + <name>sio_36</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -32351,7 +32282,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_37</name> + <name>sio_37</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -32546,7 +32477,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_38</name> + <name>sio_38</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -32745,7 +32676,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_39</name> + <name>sio_39</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -32944,7 +32875,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_40</name> + <name>sio_40</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -33139,7 +33070,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_41</name> + <name>sio_41</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -33334,7 +33265,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_42</name> + <name>sio_42</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -33533,7 +33464,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_43</name> + <name>sio_43</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -33732,7 +33663,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_44</name> + <name>sio_44</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -33927,7 +33858,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_45</name> + <name>sio_45</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -34122,7 +34053,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_46</name> + <name>sio_46</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -34321,7 +34252,7 @@ <value>4</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_47</name> + <name>sio_47</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -46057,6 +45988,14 @@ </fields> </register> </registers> + <interrupt> + <name>IO_IRQ_BANK0</name> + <value>21</value> + </interrupt> + <interrupt> + <name>IO_IRQ_BANK0_NS</name> + <value>22</value> + </interrupt> </peripheral> <peripheral> <name>IO_QSPI</name> @@ -46066,14 +46005,6 @@ <size>576</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>IO_IRQ_QSPI</name> - <value>23</value> - </interrupt> - <interrupt> - <name>IO_IRQ_QSPI_NS</name> - <value>24</value> - </interrupt> <registers> <register> <name>USBPHY_DP_STATUS</name> @@ -46235,7 +46166,7 @@ <value>3</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_56</name> + <name>sio_56</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -46406,7 +46337,7 @@ <value>3</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_57</name> + <name>sio_57</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -46581,7 +46512,7 @@ <value>3</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_58</name> + <name>sio_58</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -46760,7 +46691,7 @@ <value>3</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_59</name> + <name>sio_59</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -46939,7 +46870,7 @@ <value>3</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_60</name> + <name>sio_60</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -47114,7 +47045,7 @@ <value>3</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_61</name> + <name>sio_61</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -47289,7 +47220,7 @@ <value>3</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_62</name> + <name>sio_62</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -47468,7 +47399,7 @@ <value>3</value> </enumeratedValue> <enumeratedValue> - <name>siob_proc_63</name> + <name>sio_63</name> <value>5</value> </enumeratedValue> <enumeratedValue> @@ -49462,20 +49393,24 @@ </fields> </register> </registers> + <interrupt> + <name>IO_IRQ_QSPI</name> + <value>23</value> + </interrupt> + <interrupt> + <name>IO_IRQ_QSPI_NS</name> + <value>24</value> + </interrupt> </peripheral> <peripheral> <name>OTP</name> - <description>SNPS OTP control IF (SBPI and RPi wrapper control)</description> <baseAddress>0x40120000</baseAddress> + <description>SNPS OTP control IF (SBPI and RPi wrapper control)</description> <addressBlock> <offset>0</offset> <size>372</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>OTP_IRQ</name> - <value>38</value> - </interrupt> <registers> <register> <name>SW_LOCK0</name> @@ -52688,6 +52623,7 @@ <description>Execute instruction</description> <bitRange>[30:30]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>IS_WR</name> @@ -52958,6 +52894,7 @@ <description>Clear counter before use</description> <bitRange>[29:29]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>CNT_ENA</name> @@ -53458,11 +53395,15 @@ </fields> </register> </registers> + <interrupt> + <name>OTP_IRQ</name> + <value>38</value> + </interrupt> </peripheral> <peripheral> <name>OTP_DATA</name> - <description>Predefined OTP data layout for RP2350</description> <baseAddress>0x40130000</baseAddress> + <description>Predefined OTP data layout for RP2350</description> <addressBlock> <offset>0</offset> <size>7920</size> @@ -55740,8 +55681,8 @@ </peripheral> <peripheral> <name>OTP_DATA_RAW</name> - <description>Predefined OTP data layout for RP2350</description> <baseAddress>0x40134000</baseAddress> + <description>Predefined OTP data layout for RP2350</description> <addressBlock> <offset>0</offset> <size>16384</size> @@ -55760,7 +55701,7 @@ <fields> <field> <name>CHIPID0</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -55773,7 +55714,7 @@ <fields> <field> <name>CHIPID1</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -55786,7 +55727,7 @@ <fields> <field> <name>CHIPID2</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -55799,7 +55740,7 @@ <fields> <field> <name>CHIPID3</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -55816,7 +55757,7 @@ <fields> <field> <name>RANDID0</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -55829,7 +55770,7 @@ <fields> <field> <name>RANDID1</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -55842,7 +55783,7 @@ <fields> <field> <name>RANDID2</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -55855,7 +55796,7 @@ <fields> <field> <name>RANDID3</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -55868,7 +55809,7 @@ <fields> <field> <name>RANDID4</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -55881,7 +55822,7 @@ <fields> <field> <name>RANDID5</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -55894,7 +55835,7 @@ <fields> <field> <name>RANDID6</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -55907,7 +55848,7 @@ <fields> <field> <name>RANDID7</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -55922,7 +55863,7 @@ <fields> <field> <name>ROSC_CALIB</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -55937,7 +55878,7 @@ <fields> <field> <name>LPOSC_CALIB</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -55950,7 +55891,7 @@ <fields> <field> <name>NUM_GPIOS</name> - <bitRange>[7:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -55963,7 +55904,7 @@ <fields> <field> <name>INFO_CRC0</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -55976,7 +55917,7 @@ <fields> <field> <name>INFO_CRC1</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -56366,11 +56307,6 @@ <bitRange>[1:1]</bitRange> <access>read-only</access> </field> - <field> - <name>DISABLE_BOOTSEL_EXEC2</name> - <bitRange>[0:0]</bitRange> - <access>read-only</access> - </field> </fields> </register> <register> @@ -56568,7 +56504,7 @@ A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used.</description> - <bitRange>[15:12]</bitRange> + <bitRange>[23:12]</bitRange> <access>read-only</access> <enumeratedValues> <enumeratedValue> @@ -56719,7 +56655,7 @@ <fields> <field> <name>FLASH_PARTITION_SLOT_SIZE</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -56734,7 +56670,7 @@ <field> <name>ACTIVELOW</name> <description>LED is active-low. (Default: active-high.)</description> - <bitRange>[8:8]</bitRange> + <bitRange>[23:8]</bitRange> <access>read-only</access> </field> <field> @@ -56772,7 +56708,7 @@ <description>PLL reference divisor, minus one. Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs)</description> - <bitRange>[15:15]</bitRange> + <bitRange>[23:15]</bitRange> <access>read-only</access> </field> <field> @@ -56808,7 +56744,7 @@ <field> <name>RANGE</name> <description>Value of the XOSC_CTRL_FREQ_RANGE register.</description> - <bitRange>[15:14]</bitRange> + <bitRange>[23:14]</bitRange> <access>read-only</access> <enumeratedValues> <enumeratedValue> @@ -57001,7 +56937,7 @@ <fields> <field> <name>USB_WHITE_LABEL_ADDR</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> <enumeratedValues> <enumeratedValue> @@ -57084,7 +57020,7 @@ <fields> <field> <name>OTPBOOT_SRC</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57099,7 +57035,7 @@ <fields> <field> <name>OTPBOOT_LEN</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57114,7 +57050,7 @@ <fields> <field> <name>OTPBOOT_DST0</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57129,6 +57065,53 @@ <fields> <field> <name>OTPBOOT_DST1</name> + <bitRange>[23:0]</bitRange> + <access>read-only</access> + </field> + </fields> + </register> + <register> + <name>MAC0</name> + <addressOffset>0x00000188</addressOffset> + <description>Bytes 0 and 1 of MAC address (ECC) + + The MAC is stored as bytes in network order, so bits 7:0 of this register are the aa in aa:bb:cc:dd:ee:ff, and bits 15:8 are the bb. + + Multiple interfaces are assigned consecutive addresses from the single MAC stored in OTP.</description> + <resetMask>0x00000000</resetMask> + <fields> + <field> + <name>MAC0</name> + <bitRange>[15:0]</bitRange> + <access>read-only</access> + </field> + </fields> + </register> + <register> + <name>MAC1</name> + <addressOffset>0x0000018c</addressOffset> + <description>Bytes 2 and 3 of MAC address (ECC) + + The MAC is stored as bytes in network order, so bits 7:0 of this register are the cc in aa:bb:cc:dd:ee:ff, and bits 15:8 are the dd.</description> + <resetMask>0x00000000</resetMask> + <fields> + <field> + <name>MAC1</name> + <bitRange>[15:0]</bitRange> + <access>read-only</access> + </field> + </fields> + </register> + <register> + <name>MAC2</name> + <addressOffset>0x00000190</addressOffset> + <description>Bytes 4 and 5 of MAC address (ECC) + + The MAC is stored as bytes in network order, so bits 7:0 of this register are the ee in aa:bb:cc:dd:ee:ff, and bits 15:8 are the ff.</description> + <resetMask>0x00000000</resetMask> + <fields> + <field> + <name>MAC2</name> <bitRange>[15:0]</bitRange> <access>read-only</access> </field> @@ -57142,7 +57125,7 @@ <fields> <field> <name>BOOTKEY0_0</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57155,7 +57138,7 @@ <fields> <field> <name>BOOTKEY0_1</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57168,7 +57151,7 @@ <fields> <field> <name>BOOTKEY0_2</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57181,7 +57164,7 @@ <fields> <field> <name>BOOTKEY0_3</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57194,7 +57177,7 @@ <fields> <field> <name>BOOTKEY0_4</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57207,7 +57190,7 @@ <fields> <field> <name>BOOTKEY0_5</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57220,7 +57203,7 @@ <fields> <field> <name>BOOTKEY0_6</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57233,7 +57216,7 @@ <fields> <field> <name>BOOTKEY0_7</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57246,7 +57229,7 @@ <fields> <field> <name>BOOTKEY0_8</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57259,7 +57242,7 @@ <fields> <field> <name>BOOTKEY0_9</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57272,7 +57255,7 @@ <fields> <field> <name>BOOTKEY0_10</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57285,7 +57268,7 @@ <fields> <field> <name>BOOTKEY0_11</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57298,7 +57281,7 @@ <fields> <field> <name>BOOTKEY0_12</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57311,7 +57294,7 @@ <fields> <field> <name>BOOTKEY0_13</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57324,7 +57307,7 @@ <fields> <field> <name>BOOTKEY0_14</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57337,7 +57320,7 @@ <fields> <field> <name>BOOTKEY0_15</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57350,7 +57333,7 @@ <fields> <field> <name>BOOTKEY1_0</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57363,7 +57346,7 @@ <fields> <field> <name>BOOTKEY1_1</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57376,7 +57359,7 @@ <fields> <field> <name>BOOTKEY1_2</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57389,7 +57372,7 @@ <fields> <field> <name>BOOTKEY1_3</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57402,7 +57385,7 @@ <fields> <field> <name>BOOTKEY1_4</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57415,7 +57398,7 @@ <fields> <field> <name>BOOTKEY1_5</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57428,7 +57411,7 @@ <fields> <field> <name>BOOTKEY1_6</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57441,7 +57424,7 @@ <fields> <field> <name>BOOTKEY1_7</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57454,7 +57437,7 @@ <fields> <field> <name>BOOTKEY1_8</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57467,7 +57450,7 @@ <fields> <field> <name>BOOTKEY1_9</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57480,7 +57463,7 @@ <fields> <field> <name>BOOTKEY1_10</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57493,7 +57476,7 @@ <fields> <field> <name>BOOTKEY1_11</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57506,7 +57489,7 @@ <fields> <field> <name>BOOTKEY1_12</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57519,7 +57502,7 @@ <fields> <field> <name>BOOTKEY1_13</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57532,7 +57515,7 @@ <fields> <field> <name>BOOTKEY1_14</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57545,7 +57528,7 @@ <fields> <field> <name>BOOTKEY1_15</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57558,7 +57541,7 @@ <fields> <field> <name>BOOTKEY2_0</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57571,7 +57554,7 @@ <fields> <field> <name>BOOTKEY2_1</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57584,7 +57567,7 @@ <fields> <field> <name>BOOTKEY2_2</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57597,7 +57580,7 @@ <fields> <field> <name>BOOTKEY2_3</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57610,7 +57593,7 @@ <fields> <field> <name>BOOTKEY2_4</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57623,7 +57606,7 @@ <fields> <field> <name>BOOTKEY2_5</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57636,7 +57619,7 @@ <fields> <field> <name>BOOTKEY2_6</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57649,7 +57632,7 @@ <fields> <field> <name>BOOTKEY2_7</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57662,7 +57645,7 @@ <fields> <field> <name>BOOTKEY2_8</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57675,7 +57658,7 @@ <fields> <field> <name>BOOTKEY2_9</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57688,7 +57671,7 @@ <fields> <field> <name>BOOTKEY2_10</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57701,7 +57684,7 @@ <fields> <field> <name>BOOTKEY2_11</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57714,7 +57697,7 @@ <fields> <field> <name>BOOTKEY2_12</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57727,7 +57710,7 @@ <fields> <field> <name>BOOTKEY2_13</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57740,7 +57723,7 @@ <fields> <field> <name>BOOTKEY2_14</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57753,7 +57736,7 @@ <fields> <field> <name>BOOTKEY2_15</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57766,7 +57749,7 @@ <fields> <field> <name>BOOTKEY3_0</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57779,7 +57762,7 @@ <fields> <field> <name>BOOTKEY3_1</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57792,7 +57775,7 @@ <fields> <field> <name>BOOTKEY3_2</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57805,7 +57788,7 @@ <fields> <field> <name>BOOTKEY3_3</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57818,7 +57801,7 @@ <fields> <field> <name>BOOTKEY3_4</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57831,7 +57814,7 @@ <fields> <field> <name>BOOTKEY3_5</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57844,7 +57827,7 @@ <fields> <field> <name>BOOTKEY3_6</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57857,7 +57840,7 @@ <fields> <field> <name>BOOTKEY3_7</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57870,7 +57853,7 @@ <fields> <field> <name>BOOTKEY3_8</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57883,7 +57866,7 @@ <fields> <field> <name>BOOTKEY3_9</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57896,7 +57879,7 @@ <fields> <field> <name>BOOTKEY3_10</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57909,7 +57892,7 @@ <fields> <field> <name>BOOTKEY3_11</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57922,7 +57905,7 @@ <fields> <field> <name>BOOTKEY3_12</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57935,7 +57918,7 @@ <fields> <field> <name>BOOTKEY3_13</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57948,7 +57931,7 @@ <fields> <field> <name>BOOTKEY3_14</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57961,7 +57944,7 @@ <fields> <field> <name>BOOTKEY3_15</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57974,7 +57957,7 @@ <fields> <field> <name>KEY1_0</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -57987,7 +57970,7 @@ <fields> <field> <name>KEY1_1</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58000,7 +57983,7 @@ <fields> <field> <name>KEY1_2</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58013,7 +57996,7 @@ <fields> <field> <name>KEY1_3</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58026,7 +58009,7 @@ <fields> <field> <name>KEY1_4</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58039,7 +58022,7 @@ <fields> <field> <name>KEY1_5</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58052,7 +58035,7 @@ <fields> <field> <name>KEY1_6</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58065,7 +58048,7 @@ <fields> <field> <name>KEY1_7</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58078,7 +58061,7 @@ <fields> <field> <name>KEY2_0</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58091,7 +58074,7 @@ <fields> <field> <name>KEY2_1</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58104,7 +58087,7 @@ <fields> <field> <name>KEY2_2</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58117,7 +58100,7 @@ <fields> <field> <name>KEY2_3</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58130,7 +58113,7 @@ <fields> <field> <name>KEY2_4</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58143,7 +58126,7 @@ <fields> <field> <name>KEY2_5</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58156,7 +58139,7 @@ <fields> <field> <name>KEY2_6</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58169,7 +58152,7 @@ <fields> <field> <name>KEY2_7</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58182,7 +58165,7 @@ <fields> <field> <name>KEY3_0</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58195,7 +58178,7 @@ <fields> <field> <name>KEY3_1</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58208,7 +58191,7 @@ <fields> <field> <name>KEY3_2</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58221,7 +58204,7 @@ <fields> <field> <name>KEY3_3</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58234,7 +58217,7 @@ <fields> <field> <name>KEY3_4</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58247,7 +58230,7 @@ <fields> <field> <name>KEY3_5</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58260,7 +58243,7 @@ <fields> <field> <name>KEY3_6</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58273,7 +58256,7 @@ <fields> <field> <name>KEY3_7</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58286,7 +58269,7 @@ <fields> <field> <name>KEY4_0</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58299,7 +58282,7 @@ <fields> <field> <name>KEY4_1</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58312,7 +58295,7 @@ <fields> <field> <name>KEY4_2</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58325,7 +58308,7 @@ <fields> <field> <name>KEY4_3</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58338,7 +58321,7 @@ <fields> <field> <name>KEY4_4</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58351,7 +58334,7 @@ <fields> <field> <name>KEY4_5</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58364,7 +58347,7 @@ <fields> <field> <name>KEY4_6</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58377,7 +58360,7 @@ <fields> <field> <name>KEY4_7</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58390,7 +58373,7 @@ <fields> <field> <name>KEY5_0</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58403,7 +58386,7 @@ <fields> <field> <name>KEY5_1</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58416,7 +58399,7 @@ <fields> <field> <name>KEY5_2</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58429,7 +58412,7 @@ <fields> <field> <name>KEY5_3</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58442,7 +58425,7 @@ <fields> <field> <name>KEY5_4</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58455,7 +58438,7 @@ <fields> <field> <name>KEY5_5</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58468,7 +58451,7 @@ <fields> <field> <name>KEY5_6</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58481,7 +58464,7 @@ <fields> <field> <name>KEY5_7</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58494,7 +58477,7 @@ <fields> <field> <name>KEY6_0</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58507,7 +58490,7 @@ <fields> <field> <name>KEY6_1</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58520,7 +58503,7 @@ <fields> <field> <name>KEY6_2</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58533,7 +58516,7 @@ <fields> <field> <name>KEY6_3</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58546,7 +58529,7 @@ <fields> <field> <name>KEY6_4</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58559,7 +58542,7 @@ <fields> <field> <name>KEY6_5</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58572,7 +58555,7 @@ <fields> <field> <name>KEY6_6</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -58585,7 +58568,7 @@ <fields> <field> <name>KEY6_7</name> - <bitRange>[15:0]</bitRange> + <bitRange>[23:0]</bitRange> <access>read-only</access> </field> </fields> @@ -73022,21 +73005,13 @@ </peripheral> <peripheral> <name>PIO0</name> - <description>Programmable IO block</description> <baseAddress>0x50200000</baseAddress> + <description>Programmable IO block</description> <addressBlock> <offset>0</offset> <size>392</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>PIO0_IRQ_0</name> - <value>15</value> - </interrupt> - <interrupt> - <name>PIO0_IRQ_1</name> - <value>16</value> - </interrupt> <registers> <register> <name>CTRL</name> @@ -73051,6 +73026,7 @@ This is equivalent to writing 1 to the corresponding CLKDIV_RESTART bits in those PIOs' CTRL registers.</description> <bitRange>[26:26]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>NEXTPREV_SM_DISABLE</name> @@ -73059,6 +73035,7 @@ This is equivalent to clearing the corresponding SM_ENABLE bits in those PIOs' CTRL registers.</description> <bitRange>[25:25]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>NEXTPREV_SM_ENABLE</name> @@ -73069,6 +73046,7 @@ If both OTHERS_SM_ENABLE and OTHERS_SM_DISABLE are set, the disable takes precedence.</description> <bitRange>[24:24]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>NEXT_PIO_MASK</name> @@ -73081,6 +73059,7 @@ Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not.</description> <bitRange>[23:20]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>PREV_PIO_MASK</name> @@ -73091,6 +73070,7 @@ Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not.</description> <bitRange>[19:16]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>CLKDIV_RESTART</name> @@ -73101,6 +73081,7 @@ Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly.</description> <bitRange>[11:8]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>SM_RESTART</name> @@ -73111,6 +73092,7 @@ The contents of the output shift register and the X/Y scratch registers are not affected.</description> <bitRange>[7:4]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>SM_ENABLE</name> @@ -75938,6 +75920,14 @@ </fields> </register> </registers> + <interrupt> + <name>PIO0_IRQ_0</name> + <value>15</value> + </interrupt> + <interrupt> + <name>PIO0_IRQ_1</name> + <value>16</value> + </interrupt> </peripheral> <peripheral derivedFrom="PIO0"> <name>PIO1</name> @@ -75971,10 +75961,6 @@ <size>32</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>PLL_SYS_IRQ</name> - <value>42</value> - </interrupt> <registers> <register> <name>CS</name> @@ -76143,6 +76129,10 @@ </fields> </register> </registers> + <interrupt> + <name>PLL_SYS_IRQ</name> + <value>42</value> + </interrupt> </peripheral> <peripheral derivedFrom="PLL_SYS"> <name>PLL_USB</name> @@ -76154,21 +76144,13 @@ </peripheral> <peripheral> <name>POWMAN</name> - <description>Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use</description> <baseAddress>0x40100000</baseAddress> + <description>Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use</description> <addressBlock> <offset>0</offset> <size>240</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>POWMAN_IRQ_POW</name> - <value>44</value> - </interrupt> - <interrupt> - <name>POWMAN_IRQ_TIMER</name> - <value>45</value> - </interrupt> <registers> <register> <name>BADPASSWD</name> @@ -76610,7 +76592,7 @@ <resetValue>0x00000000</resetValue> <fields> <field> - <name>HAD_WATCHDOG_RESET_RSM</name> + <name>HAD_WATCHDOG_RESET_PSM</name> <description>Last reset was a watchdog timeout which was configured to reset the power-on state machine This resets: double_tap flag no @@ -76826,9 +76808,9 @@ <resetValue>0x00000000</resetValue> <fields> <field> - <name>RESET_RSM</name> + <name>RESET_PSM</name> <description>If set to 1, a watchdog reset will run the full power-on state machine (PSM) sequence - From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD + From a user perspective it is the same as setting PSM_WDSEL_PROC_COLD From a hardware debug perspective it has the same effect as a reset from a glitch detector</description> <bitRange>[12:12]</bitRange> <access>read-write</access> @@ -76836,7 +76818,7 @@ <field> <name>RESET_SWCORE</name> <description>If set to 1, a watchdog reset will reset the switched core power domain and run the full power-on state machine (PSM) sequence - From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD + From a user perspective it is the same as setting PSM_WDSEL_PROC_COLD From a hardware debug perspective it has the same effect as a power-on reset for the switched core power domain</description> <bitRange>[8:8]</bitRange> <access>read-write</access> @@ -77152,12 +77134,26 @@ </field> <field> <name>SOURCE_SEL</name> - <description>0 -> gpio12 - 1 -> gpio20 - 2 -> gpio14 - 3 -> gpio22</description> <bitRange>[1:0]</bitRange> <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>gpio12</name> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>gpio20</name> + <value>1</value> + </enumeratedValue> + <enumeratedValue> + <name>gpio14</name> + <value>2</value> + </enumeratedValue> + <enumeratedValue> + <name>gpio22</name> + <value>3</value> + </enumeratedValue> + </enumeratedValues> </field> </fields> </register> @@ -77387,18 +77383,21 @@ <description>switch to gpio as the source of the 1kHz timer tick</description> <bitRange>[10:10]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>USE_XOSC</name> <description>switch to xosc as the source of the 1kHz timer tick</description> <bitRange>[9:9]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>USE_LPOSC</name> <description>Switch to lposc as the source of the 1kHz timer tick</description> <bitRange>[8:8]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>ALARM</name> @@ -77424,6 +77423,7 @@ <description>Clears the timer, does not disable the timer and does not affect the alarm. This control can be written at any time.</description> <bitRange>[2:2]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>RUN</name> @@ -77812,7 +77812,7 @@ <register> <name>BOOTDIS</name> <addressOffset>0x000000a8</addressOffset> - <description>Tell the bootrom to ignore the BOOT0..3 registers following the next RSM reset (e.g. the next core power down/up). + <description>Tell the bootrom to ignore the BOOT0..3 registers following the next PSM reset (e.g. the next core power down/up). If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by powering the core up and down. @@ -77825,7 +77825,7 @@ <name>NEXT</name> <description>This flag always ORs writes into its current contents. It can be set but not cleared by software. - The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the BOOT0..3 registers will be ignored following the next reset of the RSM by powman. + The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the BOOT0..3 registers will be ignored following the next reset of the PSM by powman. This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it by power cycling.</description> <bitRange>[1:1]</bitRange> @@ -77833,7 +77833,7 @@ </field> <field> <name>NOW</name> - <description>When powman resets the RSM, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. + <description>When powman resets the PSM, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. The bootrom checks this flag before reading the BOOT0..3 registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data.</description> <bitRange>[0:0]</bitRange> @@ -78134,11 +78134,19 @@ </fields> </register> </registers> + <interrupt> + <name>POWMAN_IRQ_POW</name> + <value>44</value> + </interrupt> + <interrupt> + <name>POWMAN_IRQ_TIMER</name> + <value>45</value> + </interrupt> </peripheral> <peripheral> <name>PPB</name> - <description>TEAL registers accessible through the debug interface</description> <baseAddress>0xe0000000</baseAddress> + <description>TEAL registers accessible through the debug interface</description> <addressBlock> <offset>0</offset> <size>274432</size> @@ -78827,11 +78835,6 @@ <description>Provides CoreSight discovery information for the ITM</description> <resetValue>0x00000000</resetValue> <fields> - <field> - <name>ITM_PIDR5</name> - <bitRange>[31:0]</bitRange> - <access>read-write</access> - </field> </fields> </register> <register> @@ -78840,11 +78843,6 @@ <description>Provides CoreSight discovery information for the ITM</description> <resetValue>0x00000000</resetValue> <fields> - <field> - <name>ITM_PIDR6</name> - <bitRange>[31:0]</bitRange> - <access>read-write</access> - </field> </fields> </register> <register> @@ -78853,11 +78851,6 @@ <description>Provides CoreSight discovery information for the ITM</description> <resetValue>0x00000000</resetValue> <fields> - <field> - <name>ITM_PIDR7</name> - <bitRange>[31:0]</bitRange> - <access>read-write</access> - </field> </fields> </register> <register> @@ -79468,11 +79461,6 @@ <description>Provides CoreSight discovery information for the DWT</description> <resetValue>0x00000000</resetValue> <fields> - <field> - <name>DWT_PIDR5</name> - <bitRange>[31:0]</bitRange> - <access>read-write</access> - </field> </fields> </register> <register> @@ -79481,11 +79469,6 @@ <description>Provides CoreSight discovery information for the DWT</description> <resetValue>0x00000000</resetValue> <fields> - <field> - <name>DWT_PIDR6</name> - <bitRange>[31:0]</bitRange> - <access>read-write</access> - </field> </fields> </register> <register> @@ -79494,11 +79477,6 @@ <description>Provides CoreSight discovery information for the DWT</description> <resetValue>0x00000000</resetValue> <fields> - <field> - <name>DWT_PIDR7</name> - <bitRange>[31:0]</bitRange> - <access>read-write</access> - </field> </fields> </register> <register> @@ -79903,11 +79881,6 @@ <description>Provides CoreSight discovery information for the FP</description> <resetValue>0x00000000</resetValue> <fields> - <field> - <name>FP_PIDR5</name> - <bitRange>[31:0]</bitRange> - <access>read-write</access> - </field> </fields> </register> <register> @@ -79916,11 +79889,6 @@ <description>Provides CoreSight discovery information for the FP</description> <resetValue>0x00000000</resetValue> <fields> - <field> - <name>FP_PIDR6</name> - <bitRange>[31:0]</bitRange> - <access>read-write</access> - </field> </fields> </register> <register> @@ -79929,11 +79897,6 @@ <description>Provides CoreSight discovery information for the FP</description> <resetValue>0x00000000</resetValue> <fields> - <field> - <name>FP_PIDR7</name> - <bitRange>[31:0]</bitRange> - <access>read-write</access> - </field> </fields> </register> <register> @@ -81088,15 +81051,13 @@ </field> <field> <name>SYSRESETREQS</name> - <description>System reset request, Secure state only. - 0 SYSRESETREQ functionality is available to both Security states. - 1 SYSRESETREQ functionality is only available to Secure state.</description> + <description>This resets only the core on which SYSRESETREQ is asserted, and not the wider system.</description> <bitRange>[3:3]</bitRange> <access>read-write</access> </field> <field> <name>SYSRESETREQ</name> - <description>Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device.</description> + <description>This resets only the core on which SYSRESETREQ is asserted, and not the wider system.</description> <bitRange>[2:2]</bitRange> <access>read-write</access> </field> @@ -81769,11 +81730,6 @@ <description>Provides information about the implemented memory model and memory management support</description> <resetValue>0x00000000</resetValue> <fields> - <field> - <name>ID_MMFR1</name> - <bitRange>[31:0]</bitRange> - <access>read-write</access> - </field> </fields> </register> <register> @@ -82042,11 +81998,6 @@ <description>Provides information about the instruction set implemented by the PE</description> <resetValue>0x00000000</resetValue> <fields> - <field> - <name>ID_ISAR5</name> - <bitRange>[31:0]</bitRange> - <access>read-write</access> - </field> </fields> </register> <register> @@ -83337,11 +83288,6 @@ <description>Provides CoreSight discovery information for the SCS</description> <resetValue>0x00000000</resetValue> <fields> - <field> - <name>DPIDR5</name> - <bitRange>[31:0]</bitRange> - <access>read-write</access> - </field> </fields> </register> <register> @@ -83350,11 +83296,6 @@ <description>Provides CoreSight discovery information for the SCS</description> <resetValue>0x00000000</resetValue> <fields> - <field> - <name>DPIDR6</name> - <bitRange>[31:0]</bitRange> - <access>read-write</access> - </field> </fields> </register> <register> @@ -83363,11 +83304,6 @@ <description>Provides CoreSight discovery information for the SCS</description> <resetValue>0x00000000</resetValue> <fields> - <field> - <name>DPIDR7</name> - <bitRange>[31:0]</bitRange> - <access>read-write</access> - </field> </fields> </register> <register> @@ -84238,11 +84174,6 @@ <description>TRCIDR6</description> <resetValue>0x00000000</resetValue> <fields> - <field> - <name>TRCIDR6</name> - <bitRange>[31:0]</bitRange> - <access>read-write</access> - </field> </fields> </register> <register> @@ -84251,11 +84182,6 @@ <description>TRCIDR7</description> <resetValue>0x00000000</resetValue> <fields> - <field> - <name>TRCIDR7</name> - <bitRange>[31:0]</bitRange> - <access>read-write</access> - </field> </fields> </register> <register> @@ -84602,11 +84528,6 @@ <description>TRCDEVID</description> <resetValue>0x00000000</resetValue> <fields> - <field> - <name>TRCDEVID</name> - <bitRange>[31:0]</bitRange> - <access>read-write</access> - </field> </fields> </register> <register> @@ -84655,11 +84576,6 @@ <description>TRCPIDR5</description> <resetValue>0x00000000</resetValue> <fields> - <field> - <name>TRCPIDR5</name> - <bitRange>[31:0]</bitRange> - <access>read-write</access> - </field> </fields> </register> <register> @@ -84668,11 +84584,6 @@ <description>TRCPIDR6</description> <resetValue>0x00000000</resetValue> <fields> - <field> - <name>TRCPIDR6</name> - <bitRange>[31:0]</bitRange> - <access>read-write</access> - </field> </fields> </register> <register> @@ -84681,11 +84592,6 @@ <description>TRCPIDR7</description> <resetValue>0x00000000</resetValue> <fields> - <field> - <name>TRCPIDR7</name> - <bitRange>[31:0]</bitRange> - <access>read-write</access> - </field> </fields> </register> <register> @@ -85204,11 +85110,6 @@ <description>External Multiplexer Control register</description> <resetValue>0x00000000</resetValue> <fields> - <field> - <name>ASICCTL</name> - <bitRange>[31:0]</bitRange> - <access>read-write</access> - </field> </fields> </register> <register> @@ -85371,11 +85272,6 @@ <description>CoreSight Peripheral ID5</description> <resetValue>0x00000000</resetValue> <fields> - <field> - <name>PIDR5</name> - <bitRange>[31:0]</bitRange> - <access>read-write</access> - </field> </fields> </register> <register> @@ -85384,11 +85280,6 @@ <description>CoreSight Peripheral ID6</description> <resetValue>0x00000000</resetValue> <fields> - <field> - <name>PIDR6</name> - <bitRange>[31:0]</bitRange> - <access>read-write</access> - </field> </fields> </register> <register> @@ -85397,11 +85288,6 @@ <description>CoreSight Peripheral ID7</description> <resetValue>0x00000000</resetValue> <fields> - <field> - <name>PIDR7</name> - <bitRange>[31:0]</bitRange> - <access>read-write</access> - </field> </fields> </register> <register> @@ -86097,21 +85983,13 @@ </peripheral> <peripheral> <name>PWM</name> - <description>Simple PWM</description> <baseAddress>0x400a8000</baseAddress> + <description>Simple PWM</description> <addressBlock> <offset>0</offset> <size>272</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>PWM_IRQ_WRAP_0</name> - <value>8</value> - </interrupt> - <interrupt> - <name>PWM_IRQ_WRAP_1</name> - <value>9</value> - </interrupt> <registers> <register> <name>CH0_CSR</name> @@ -86125,14 +86003,16 @@ Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)</description> <bitRange>[7:7]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>PH_RET</name> <description>Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.</description> <bitRange>[6:6]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>DIVMODE</name> @@ -86263,14 +86143,16 @@ Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)</description> <bitRange>[7:7]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>PH_RET</name> <description>Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.</description> <bitRange>[6:6]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>DIVMODE</name> @@ -86401,14 +86283,16 @@ Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)</description> <bitRange>[7:7]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>PH_RET</name> <description>Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.</description> <bitRange>[6:6]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>DIVMODE</name> @@ -86539,14 +86423,16 @@ Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)</description> <bitRange>[7:7]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>PH_RET</name> <description>Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.</description> <bitRange>[6:6]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>DIVMODE</name> @@ -86677,14 +86563,16 @@ Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)</description> <bitRange>[7:7]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>PH_RET</name> <description>Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.</description> <bitRange>[6:6]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>DIVMODE</name> @@ -86815,14 +86703,16 @@ Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)</description> <bitRange>[7:7]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>PH_RET</name> <description>Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.</description> <bitRange>[6:6]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>DIVMODE</name> @@ -86953,14 +86843,16 @@ Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)</description> <bitRange>[7:7]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>PH_RET</name> <description>Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.</description> <bitRange>[6:6]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>DIVMODE</name> @@ -87091,14 +86983,16 @@ Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)</description> <bitRange>[7:7]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>PH_RET</name> <description>Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.</description> <bitRange>[6:6]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>DIVMODE</name> @@ -87229,14 +87123,16 @@ Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)</description> <bitRange>[7:7]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>PH_RET</name> <description>Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.</description> <bitRange>[6:6]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>DIVMODE</name> @@ -87367,14 +87263,16 @@ Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)</description> <bitRange>[7:7]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>PH_RET</name> <description>Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.</description> <bitRange>[6:6]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>DIVMODE</name> @@ -87505,14 +87403,16 @@ Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)</description> <bitRange>[7:7]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>PH_RET</name> <description>Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.</description> <bitRange>[6:6]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>DIVMODE</name> @@ -87643,14 +87543,16 @@ Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)</description> <bitRange>[7:7]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>PH_RET</name> <description>Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.</description> <bitRange>[6:6]</bitRange> - <access>write-only</access> + <access>read-write</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>DIVMODE</name> @@ -88330,13 +88232,21 @@ </fields> </register> </registers> + <interrupt> + <name>PWM_IRQ_WRAP_0</name> + <value>8</value> + </interrupt> + <interrupt> + <name>PWM_IRQ_WRAP_1</name> + <value>9</value> + </interrupt> </peripheral> <peripheral> <name>QMI</name> + <baseAddress>0x400d0000</baseAddress> <description>QSPI Memory Interface. Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device.</description> - <baseAddress>0x400d0000</baseAddress> <addressBlock> <offset>0</offset> <size>84</size> @@ -90646,7 +90556,7 @@ <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>dormant</name> + <name>DORMANT</name> <value>1668246881</value> </enumeratedValue> <enumeratedValue> @@ -90785,8 +90695,8 @@ </peripheral> <peripheral> <name>SHA256</name> - <description>SHA-256 hash function implementation</description> <baseAddress>0x400f8000</baseAddress> + <description>SHA-256 hash function implementation</description> <addressBlock> <offset>0</offset> <size>40</size> @@ -90865,6 +90775,7 @@ START must be written before initiating a DMA transfer to the SHA-256 core, because the core will always request 16 transfers at a time (1 512-bit block). Additionally, the DMA channel should be configured for a multiple of 16 32-bit transfers.</description> <bitRange>[0:0]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> </fields> </register> @@ -90996,34 +90907,14 @@ </peripheral> <peripheral> <name>SIO</name> + <baseAddress>0xd0000000</baseAddress> <description>Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access.</description> - <baseAddress>0xd0000000</baseAddress> <addressBlock> <offset>0</offset> <size>488</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>SIO_IRQ_FIFO</name> - <value>25</value> - </interrupt> - <interrupt> - <name>SIO_IRQ_BELL</name> - <value>26</value> - </interrupt> - <interrupt> - <name>SIO_IRQ_FIFO_NS</name> - <value>27</value> - </interrupt> - <interrupt> - <name>SIO_IRQ_BELL_NS</name> - <value>28</value> - </interrupt> - <interrupt> - <name>SIO_IRQ_MTIMECMP</name> - <value>29</value> - </interrupt> <registers> <register> <name>CPUID</name> @@ -93108,7 +92999,7 @@ <register> <name>MTIME</name> <addressOffset>0x000001b0</addressOffset> - <description>Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence.</description> + <description>Read/write access to the low half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence.</description> <resetValue>0x00000000</resetValue> <fields> <field> @@ -93172,6 +93063,7 @@ <description>Clear the running DC balance state of the TMDS encoders. This bit should be written once at the beginning of each scanline.</description> <bitRange>[28:28]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>PIX2_NOSHIFT</name> @@ -93419,45 +93311,31 @@ </fields> </register> </registers> + <interrupt> + <name>SIO_IRQ_FIFO</name> + <value>25</value> + </interrupt> + <interrupt> + <name>SIO_IRQ_BELL</name> + <value>26</value> + </interrupt> + <interrupt> + <name>SIO_IRQ_MTIMECMP</name> + <value>29</value> + </interrupt> </peripheral> <peripheral derivedFrom="SIO"> <name>SIO_NS</name> <baseAddress>0xd0020000</baseAddress> - </peripheral> - <peripheral> - <name>SPARE_IRQ</name> - <baseAddress>0x00000000</baseAddress> - <addressBlock> - <offset>0</offset> - <size>4</size> - <usage>reserved</usage> - </addressBlock> <interrupt> - <name>SPARE_IRQ_0</name> - <value>46</value> + <name>SIO_IRQ_FIFO_NS</name> + <value>27</value> </interrupt> <interrupt> - <name>SPARE_IRQ_1</name> - <value>47</value> - </interrupt> - <interrupt> - <name>SPARE_IRQ_2</name> - <value>48</value> - </interrupt> - <interrupt> - <name>SPARE_IRQ_3</name> - <value>49</value> - </interrupt> - <interrupt> - <name>SPARE_IRQ_4</name> - <value>50</value> - </interrupt> - <interrupt> - <name>SPARE_IRQ_5</name> - <value>51</value> + <name>SIO_IRQ_BELL_NS</name> + <value>28</value> </interrupt> </peripheral> - <peripheral> <name>SPI0</name> <baseAddress>0x40080000</baseAddress> @@ -93466,10 +93344,6 @@ <size>4096</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>SPI0_IRQ</name> - <value>31</value> - </interrupt> <registers> <register> <name>SSPCR0</name> @@ -93871,6 +93745,10 @@ </fields> </register> </registers> + <interrupt> + <name>SPI0_IRQ</name> + <value>31</value> + </interrupt> </peripheral> <peripheral derivedFrom="SPI0"> <name>SPI1</name> @@ -93882,8 +93760,8 @@ </peripheral> <peripheral> <name>SYSCFG</name> - <description>Register block for various chip control signals</description> <baseAddress>0x40008000</baseAddress> + <description>Register block for various chip control signals</description> <addressBlock> <offset>0</offset> <size>24</size> @@ -94085,6 +93963,7 @@ <field> <name>AUXCTRL</name> <description>* Bits 7:3: Reserved + * Bit 2: Set to mask OTP power analogue power supply detection from resetting OTP controller and PSM * Bit 1: When clear, the LPOSC output is XORed into the TRNG ROSC output as an additional, uncorrelated entropy source. When set, this behaviour is disabled. @@ -94110,7 +93989,7 @@ <name>CHIP_ID</name> <addressOffset>0x00000000</addressOffset> <description>JEDEC JEP-106 compliant chip identifier.</description> - <resetValue>0x00000001</resetValue> + <resetValue>0x30004927</resetValue> <fields> <field> <name>REVISION</name> @@ -94137,6 +94016,7 @@ <register> <name>PACKAGE_SEL</name> <addressOffset>0x00000004</addressOffset> + <description>Package selection indicator, 0 = QFN80, 1 = QFN60</description> <resetValue>0x00000000</resetValue> <fields> <field> @@ -94196,8 +94076,8 @@ </peripheral> <peripheral> <name>TBMAN</name> - <description>For managing simulation testbenches</description> <baseAddress>0x40160000</baseAddress> + <description>Testbench manager. Allows the programmer to know what platform their software is running on.</description> <addressBlock> <offset>0</offset> <size>4</size> @@ -94521,40 +94401,29 @@ </peripheral> <peripheral> <name>TIMER0</name> - <description>Controls time and alarms - - time is a 64 bit value indicating the time since power-on - - timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr - - An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing</description> <baseAddress>0x400b0000</baseAddress> + <description>Controls time and alarms + time is a 64 bit value indicating the time since power-on + timeh is the top 32 bits of time & timel is the bottom 32 bits + to change time write to timelw before timehw + to read time read from timelr before timehr + An alarm is set by setting alarm_enable and writing to the corresponding alarm register + When an alarm is pending, the corresponding alarm_running signal will be high + An alarm can be cancelled before it has finished by clearing the alarm_enable + When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared + To clear the interrupt write a 1 to the corresponding alarm_irq + The timer can be locked to prevent writing</description> <addressBlock> <offset>0</offset> <size>76</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>TIMER0_IRQ_0</name> - <value>0</value> - </interrupt> - <interrupt> - <name>TIMER0_IRQ_1</name> - <value>1</value> - </interrupt> - <interrupt> - <name>TIMER0_IRQ_2</name> - <value>2</value> - </interrupt> - <interrupt> - <name>TIMER0_IRQ_3</name> - <value>3</value> - </interrupt> <registers> <register> <name>TIMEHW</name> <addressOffset>0x00000000</addressOffset> - <description>Write to bits 63:32 of time always write timelw before timehw</description> + <description>Write to bits 63:32 of time + always write timelw before timehw</description> <resetValue>0x00000000</resetValue> <fields> <field> @@ -94567,7 +94436,8 @@ <register> <name>TIMELW</name> <addressOffset>0x00000004</addressOffset> - <description>Write to bits 31:0 of time writes do not get copied to time until timehw is written</description> + <description>Write to bits 31:0 of time + writes do not get copied to time until timehw is written</description> <resetValue>0x00000000</resetValue> <fields> <field> @@ -94580,7 +94450,8 @@ <register> <name>TIMEHR</name> <addressOffset>0x00000008</addressOffset> - <description>Read from bits 63:32 of time always read timelr before timehr</description> + <description>Read from bits 63:32 of time + always read timelr before timehr</description> <resetValue>0x00000000</resetValue> <fields> <field> @@ -94607,7 +94478,10 @@ <register> <name>ALARM0</name> <addressOffset>0x00000010</addressOffset> - <description>Arm alarm 0, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register.</description> + <description>Arm alarm 0, and configure the time it will fire. + Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. + The alarm will disarm itself once it fires, and can + be disarmed early using the ARMED status register.</description> <resetValue>0x00000000</resetValue> <fields> <field> @@ -94620,7 +94494,10 @@ <register> <name>ALARM1</name> <addressOffset>0x00000014</addressOffset> - <description>Arm alarm 1, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register.</description> + <description>Arm alarm 1, and configure the time it will fire. + Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. + The alarm will disarm itself once it fires, and can + be disarmed early using the ARMED status register.</description> <resetValue>0x00000000</resetValue> <fields> <field> @@ -94633,7 +94510,10 @@ <register> <name>ALARM2</name> <addressOffset>0x00000018</addressOffset> - <description>Arm alarm 2, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register.</description> + <description>Arm alarm 2, and configure the time it will fire. + Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. + The alarm will disarm itself once it fires, and can + be disarmed early using the ARMED status register.</description> <resetValue>0x00000000</resetValue> <fields> <field> @@ -94646,7 +94526,10 @@ <register> <name>ALARM3</name> <addressOffset>0x0000001c</addressOffset> - <description>Arm alarm 3, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register.</description> + <description>Arm alarm 3, and configure the time it will fire. + Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. + The alarm will disarm itself once it fires, and can + be disarmed early using the ARMED status register.</description> <resetValue>0x00000000</resetValue> <fields> <field> @@ -94659,7 +94542,10 @@ <register> <name>ARMED</name> <addressOffset>0x00000020</addressOffset> - <description>Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing, but writing ones here will disarm immediately without waiting to fire.</description> + <description>Indicates the armed/disarmed status of each alarm. + A write to the corresponding ALARMx register arms the alarm. + Alarms automatically disarm upon firing, but writing ones here + will disarm immediately without waiting to fire.</description> <resetValue>0x00000000</resetValue> <fields> <field> @@ -94732,7 +94618,8 @@ <register> <name>LOCKED</name> <addressOffset>0x00000034</addressOffset> - <description>Set locked bit to disable write access to timer Once set, cannot be cleared (without a reset)</description> + <description>Set locked bit to disable write access to timer + Once set, cannot be cleared (without a reset)</description> <resetValue>0x00000000</resetValue> <fields> <field> @@ -94882,6 +94769,22 @@ </fields> </register> </registers> + <interrupt> + <name>TIMER0_IRQ_0</name> + <value>0</value> + </interrupt> + <interrupt> + <name>TIMER0_IRQ_1</name> + <value>1</value> + </interrupt> + <interrupt> + <name>TIMER0_IRQ_2</name> + <value>2</value> + </interrupt> + <interrupt> + <name>TIMER0_IRQ_3</name> + <value>3</value> + </interrupt> </peripheral> <peripheral derivedFrom="TIMER0"> <name>TIMER1</name> @@ -94905,17 +94808,13 @@ </peripheral> <peripheral> <name>TRNG</name> - <description>ARM TrustZone RNG register block</description> <baseAddress>0x400f0000</baseAddress> + <description>Arm TrustZone RNG register block</description> <addressBlock> <offset>0</offset> <size>492</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>TRNG_IRQ</name> - <value>39</value> - </interrupt> <registers> <register> <name>RNG_IMR</name> @@ -94924,32 +94823,26 @@ <resetValue>0x0000000f</resetValue> <fields> <field> - <name>RESERVED</name> - <description>RESERVED</description> - <bitRange>[31:4]</bitRange> - <access>read-only</access> - </field> - <field> <name>VN_ERR_INT_MASK</name> - <description>1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt.</description> + <description>Set to 1 to mask (disable) this interrupt: no interrupt will be generated. See RNG_ISR for an explanation on this interrupt.</description> <bitRange>[3:3]</bitRange> <access>read-write</access> </field> <field> <name>CRNGT_ERR_INT_MASK</name> - <description>1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt.</description> + <description>Set to 1 to mask (disable) this interrupt: no interrupt will be generated. See RNG_ISR for an explanation on this interrupt.</description> <bitRange>[2:2]</bitRange> <access>read-write</access> </field> <field> <name>AUTOCORR_ERR_INT_MASK</name> - <description>1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt.</description> + <description>Set to 1 to mask (disable) this interrupt: no interrupt will be generated. See RNG_ISR for an explanation on this interrupt.</description> <bitRange>[1:1]</bitRange> <access>read-write</access> </field> <field> <name>EHR_VALID_INT_MASK</name> - <description>1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt.</description> + <description>Set to 1 to mask (disable) this interrupt: no interrupt will be generated. See RNG_ISR for an explanation on this interrupt.</description> <bitRange>[0:0]</bitRange> <access>read-write</access> </field> @@ -94962,32 +94855,26 @@ <resetValue>0x00000000</resetValue> <fields> <field> - <name>RESERVED</name> - <description>RESERVED</description> - <bitRange>[31:4]</bitRange> - <access>read-only</access> - </field> - <field> <name>VN_ERR</name> - <description>1'b1 indicates Von Neuman error. Error in von Neuman occurs if 32 consecutive collected bits are identical, ZERO or ONE.</description> + <description>1 indicates von Neumann error. Error in von Neumann occurs if 32 consecutive collected bits are identical, ZERO or ONE.</description> <bitRange>[3:3]</bitRange> <access>read-only</access> </field> <field> <name>CRNGT_ERR</name> - <description>1'b1 indicates CRNGT in the RNG test failed. Failure occurs when two consecutive blocks of 16 collected bits are equal.</description> + <description>1 indicates CRNGT in the RNG test failed. Failure occurs when two consecutive blocks of 16 collected bits are equal.</description> <bitRange>[2:2]</bitRange> <access>read-only</access> </field> <field> <name>AUTOCORR_ERR</name> - <description>1'b1 indicates Autocorrelation test failed four times in a row. When set, RNG cease from functioning until next reset.</description> + <description>1 indicates Autocorrelation test failed four times in a row. When set, RNG ceases functioning until next reset.</description> <bitRange>[1:1]</bitRange> <access>read-only</access> </field> <field> <name>EHR_VALID</name> - <description>1'b1 indicates that 192 bits have been collected in the RNG, and are ready to be read.</description> + <description>1 indicates that 192 bits have been collected in the RNG, and are ready to be read.</description> <bitRange>[0:0]</bitRange> <access>read-only</access> </field> @@ -95000,20 +94887,14 @@ <resetValue>0x00000000</resetValue> <fields> <field> - <name>RESERVED</name> - <description>RESERVED</description> - <bitRange>[31:4]</bitRange> - <access>read-only</access> - </field> - <field> <name>VN_ERR</name> - <description>Write 1'b1 - clear corresponding bit in RNG_ISR.</description> + <description>Write 1 to clear corresponding bit in RNG_ISR.</description> <bitRange>[3:3]</bitRange> <access>read-write</access> </field> <field> <name>CRNGT_ERR</name> - <description>Write 1'b1 - clear corresponding bit in RNG_ISR.</description> + <description>Write 1 to clear corresponding bit in RNG_ISR.</description> <bitRange>[2:2]</bitRange> <access>read-write</access> </field> @@ -95025,7 +94906,7 @@ </field> <field> <name>EHR_VALID</name> - <description>Write 1'b1 - clear corresponding bit in RNG_ISR.</description> + <description>Write 1 - clear corresponding bit in RNG_ISR.</description> <bitRange>[0:0]</bitRange> <access>read-write</access> </field> @@ -95038,14 +94919,8 @@ <resetValue>0x00000000</resetValue> <fields> <field> - <name>RESERVED</name> - <description>RESERVED</description> - <bitRange>[31:2]</bitRange> - <access>read-only</access> - </field> - <field> <name>RND_SRC_SEL</name> - <description>Selects the number of inverters (out of four possible selections) in the ring oscillator (the entropy source).</description> + <description>Selects the number of inverters (out of four possible selections) in the ring oscillator (the entropy source). Higher values select longer inverter chain lengths.</description> <bitRange>[1:0]</bitRange> <access>read-write</access> </field> @@ -95058,14 +94933,8 @@ <resetValue>0x00000000</resetValue> <fields> <field> - <name>RESERVED</name> - <description>RESERVED</description> - <bitRange>[31:1]</bitRange> - <access>read-only</access> - </field> - <field> <name>EHR_VALID</name> - <description>1'b1 indicates that collection of bits in the RNG is completed, and data can be read from EHR_DATA register.</description> + <description>1 indicates that collection of bits in the RNG is completed, and data can be read from EHR_DATA register.</description> <bitRange>[0:0]</bitRange> <access>read-only</access> </field> @@ -95162,14 +95031,10 @@ <resetValue>0x00000000</resetValue> <fields> <field> - <name>RESERVED</name> - <description>RESERVED</description> - <bitRange>[31:1]</bitRange> - <access>read-only</access> - </field> - <field> <name>RND_SRC_EN</name> - <description>* 1'b1 - entropy source is enabled. *1'b0 - entropy source is disabled</description> + <description>* 1 - entropy source is enabled. + + * 0 - entropy source is disabled</description> <bitRange>[0:0]</bitRange> <access>read-write</access> </field> @@ -95183,7 +95048,9 @@ <fields> <field> <name>SAMPLE_CNTR1</name> - <description>Sets the number of rng_clk cycles between two consecutive ring oscillator samples. Note! If the Von-Neuman is bypassed, the minimum value for sample counter must not be less then decimal seventeen</description> + <description>Sets the number of rng_clk cycles between two consecutive ring oscillator samples. + + Note: If the von Neumann decorrelator is bypassed, the minimum value for sample counter must not be less than seventeen</description> <bitRange>[31:0]</bitRange> <access>read-write</access> </field> @@ -95192,16 +95059,10 @@ <register> <name>AUTOCORR_STATISTIC</name> <addressOffset>0x00000134</addressOffset> - <description>Statistic about Autocorrelation test activations.</description> + <description>Statistics about autocorrelation test activations.</description> <resetValue>0x00000000</resetValue> <fields> <field> - <name>RESERVED</name> - <description>RESERVED</description> - <bitRange>[31:22]</bitRange> - <access>read-only</access> - </field> - <field> <name>AUTOCORR_FAILS</name> <description>Count each time an autocorrelation test fails. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit.</description> <bitRange>[21:14]</bitRange> @@ -95235,16 +95096,11 @@ </field> <field> <name>VNC_BYPASS</name> - <description>When set, the Von-Neuman balancer is bypassed (including the 32 consecutive bits test).</description> + <description>When set, the Von-Neuman balancer is bypassed (including the 32 consecutive bits test). + N/A</description> <bitRange>[1:1]</bitRange> <access>read-write</access> </field> - <field> - <name>RESERVED</name> - <description>N/A</description> - <bitRange>[0:0]</bitRange> - <access>read-only</access> - </field> </fields> </register> <register> @@ -95254,14 +95110,8 @@ <resetValue>0x00000000</resetValue> <fields> <field> - <name>RESERVED</name> - <description>RESERVED</description> - <bitRange>[31:1]</bitRange> - <access>read-only</access> - </field> - <field> <name>TRNG_SW_RESET</name> - <description>Writing 1'b1 to this register causes an internal RNG reset.</description> + <description>Writing 1 to this register causes an internal RNG reset.</description> <bitRange>[0:0]</bitRange> <access>read-write</access> </field> @@ -95274,14 +95124,10 @@ <resetValue>0x00000000</resetValue> <fields> <field> - <name>RESERVED</name> - <description>RESERVED</description> - <bitRange>[31:1]</bitRange> - <access>read-only</access> - </field> - <field> <name>RNG_DEBUG_EN</name> - <description>* 1'b1 - debug mode is enabled. *1'b0 - debug mode is disabled</description> + <description>* 1 - debug mode is enabled. + + * 0 - debug mode is disabled</description> <bitRange>[0:0]</bitRange> <access>read-write</access> </field> @@ -95294,12 +95140,6 @@ <resetValue>0x00000000</resetValue> <fields> <field> - <name>RESERVED</name> - <description>RESERVED</description> - <bitRange>[31:1]</bitRange> - <access>read-only</access> - </field> - <field> <name>TRNG_BUSY</name> <description>Reflects rng_busy status.</description> <bitRange>[0:0]</bitRange> @@ -95314,12 +95154,6 @@ <resetValue>0x00000000</resetValue> <fields> <field> - <name>RESERVED</name> - <description>RESERVED</description> - <bitRange>[31:1]</bitRange> - <access>read-only</access> - </field> - <field> <name>RST_BITS_COUNTER</name> <description>Writing any value to this address will reset the bits counter and RNG valid registers. RND_SORCE_ENABLE register must be unset in order for the reset to take place.</description> <bitRange>[0:0]</bitRange> @@ -95334,56 +95168,66 @@ <resetValue>0x00000000</resetValue> <fields> <field> - <name>RESERVED</name> - <description>RESERVED</description> - <bitRange>[31:8]</bitRange> - <access>read-only</access> - </field> - <field> <name>RNG_USE_5_SBOXES</name> - <description>* 1'b1 - 5 SBOX AES. *1'b0 - 20 SBOX AES</description> + <description>* 1 - 5 SBOX AES. + + * 0 - 20 SBOX AES</description> <bitRange>[7:7]</bitRange> <access>read-only</access> </field> <field> <name>RESEEDING_EXISTS</name> - <description>* 1'b1 - Exists. *1'b0 - Does not exist</description> + <description>* 1 - Exists. + + * 0 - Does not exist</description> <bitRange>[6:6]</bitRange> <access>read-only</access> </field> <field> <name>KAT_EXISTS</name> - <description>* 1'b1 - Exists. *1'b0 - Does not exist</description> + <description>* 1 - Exists. + + * 0 - Does not exist</description> <bitRange>[5:5]</bitRange> <access>read-only</access> </field> <field> <name>PRNG_EXISTS</name> - <description>* 1'b1 - Exists. *1'b0 - Does not exist</description> + <description>* 1 - Exists. + + * 0 - Does not exist</description> <bitRange>[4:4]</bitRange> <access>read-only</access> </field> <field> <name>TRNG_TESTS_BYPASS_EN</name> - <description>* 1'b1 - Exists. *1'b0 - Does not exist</description> + <description>* 1 - Exists. + + * 0 - Does not exist</description> <bitRange>[3:3]</bitRange> <access>read-only</access> </field> <field> <name>AUTOCORR_EXISTS</name> - <description>* 1'b1 - Exists. *1'b0 - Does not exist</description> + <description>* 1 - Exists. + + * 0 - Does not exist</description> <bitRange>[2:2]</bitRange> <access>read-only</access> </field> <field> <name>CRNGT_EXISTS</name> - <description>* 1'b1 - Exists. *1'b0 - Does not exist</description> + <description>* 1 - Exists. + + * 0 - Does not exist</description> <bitRange>[1:1]</bitRange> <access>read-only</access> </field> <field> <name>EHR_WIDTH_192</name> - <description>* 1'b1 - 192-bit EHR. *1'b0 - 128-bit EHR</description> + <description>* 1 - 192-bit EHR. + + * 0 - 128-bit EHR</description> <bitRange>[0:0]</bitRange> <access>read-only</access> </field> @@ -95396,12 +95240,6 @@ <resetValue>0x00000000</resetValue> <fields> <field> - <name>RESERVED</name> - <description>RESERVED</description> - <bitRange>[31:22]</bitRange> - <access>read-only</access> - </field> - <field> <name>ROSC_CNTR_VAL</name> <description>Reflects the results of RNG BIST counter.</description> <bitRange>[21:0]</bitRange> @@ -95416,12 +95254,6 @@ <resetValue>0x00000000</resetValue> <fields> <field> - <name>RESERVED</name> - <description>RESERVED</description> - <bitRange>[31:22]</bitRange> - <access>read-only</access> - </field> - <field> <name>ROSC_CNTR_VAL</name> <description>Reflects the results of RNG BIST counter.</description> <bitRange>[21:0]</bitRange> @@ -95436,12 +95268,6 @@ <resetValue>0x00000000</resetValue> <fields> <field> - <name>RESERVED</name> - <description>RESERVED</description> - <bitRange>[31:22]</bitRange> - <access>read-only</access> - </field> - <field> <name>ROSC_CNTR_VAL</name> <description>Reflects the results of RNG BIST counter.</description> <bitRange>[21:0]</bitRange> @@ -95450,6 +95276,10 @@ </fields> </register> </registers> + <interrupt> + <name>TRNG_IRQ</name> + <value>39</value> + </interrupt> </peripheral> <peripheral> <name>UART0</name> @@ -95459,10 +95289,6 @@ <size>4096</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>UART0_IRQ</name> - <value>33</value> - </interrupt> <registers> <register> <name>UARTDR</name> @@ -96251,6 +96077,10 @@ </fields> </register> </registers> + <interrupt> + <name>UART0_IRQ</name> + <value>33</value> + </interrupt> </peripheral> <peripheral derivedFrom="UART0"> <name>UART1</name> @@ -96262,17 +96092,13 @@ </peripheral> <peripheral> <name>USB</name> - <description>USB FS/LS controller device registers</description> <baseAddress>0x50110000</baseAddress> + <description>USB FS/LS controller device registers</description> <addressBlock> <offset>0</offset> <size>280</size> <usage>registers</usage> </addressBlock> - <interrupt> - <name>USBCTRL_IRQ</name> - <value>14</value> - </interrupt> <registers> <register> <name>ADDR_ENDP</name> @@ -96923,12 +96749,14 @@ <description>Host: Reset bus</description> <bitRange>[13:13]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>RESUME</name> <description>Device: Remote wakeup. Device can initiate its own resume after suspend.</description> <bitRange>[12:12]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>VBUS_EN</name> @@ -96965,6 +96793,7 @@ <description>Host: Stop transaction</description> <bitRange>[4:4]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>RECEIVE_DATA</name> @@ -96989,6 +96818,7 @@ <description>Host: Start transaction</description> <bitRange>[0:0]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> </fields> </register> @@ -97134,8 +96964,7 @@ <name>SUSPENDED</name> <description>Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled.</description> <bitRange>[4:4]</bitRange> - <access>read-write</access> - <modifiedWriteValues>oneToClear</modifiedWriteValues> + <access>read-only</access> </field> <field> <name>LINE_STATE</name> @@ -99574,11 +99403,15 @@ </fields> </register> </registers> + <interrupt> + <name>USBCTRL_IRQ</name> + <value>14</value> + </interrupt> </peripheral> <peripheral> - <name>USB_DPRAM</name> - <description>DPRAM layout for USB device.</description> + <name>USB_DEVICE_DPRAM</name> <baseAddress>0x50100000</baseAddress> + <description>DPRAM layout for USB device.</description> <addressBlock> <offset>0</offset> <size>256</size> @@ -105180,7 +105013,6 @@ </register> </registers> </peripheral> - <peripheral> <name>WATCHDOG</name> <baseAddress>0x400d8000</baseAddress> @@ -105203,6 +105035,7 @@ <description>Trigger a watchdog reset</description> <bitRange>[31:31]</bitRange> <access>write-only</access> + <modifiedWriteValues>oneToClear</modifiedWriteValues> </field> <field> <name>ENABLE</name> @@ -105377,8 +105210,8 @@ </peripheral> <peripheral> <name>XIP_AUX</name> - <description>Auxiliary DMA access to XIP FIFOs, via fast AHB bus access</description> <baseAddress>0x50500000</baseAddress> + <description>Auxiliary DMA access to XIP FIFOs, via fast AHB bus access</description> <addressBlock> <offset>0</offset> <size>12</size> @@ -105481,8 +105314,8 @@ </peripheral> <peripheral> <name>XIP_CTRL</name> - <description>QSPI flash execute-in-place block</description> <baseAddress>0x400c8000</baseAddress> + <description>QSPI flash execute-in-place block</description> <addressBlock> <offset>0</offset> <size>32</size> @@ -105710,8 +105543,8 @@ </peripheral> <peripheral> <name>XOSC</name> - <description>Controls the crystal oscillator</description> <baseAddress>0x40048000</baseAddress> + <description>Controls the crystal oscillator</description> <addressBlock> <offset>0</offset> <size>20</size> @@ -105830,13 +105663,13 @@ <description>This is used to save power by pausing the XOSC On power-up this field is initialised to WAKE An invalid write will also select WAKE - Warning: stop the PLLs before selecting dormant mode - Warning: setup the irq before selecting dormant mode</description> + WARNING: stop the PLLs before selecting dormant mode + WARNING: setup the irq before selecting dormant mode</description> <bitRange>[31:0]</bitRange> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>dormant</name> + <name>DORMANT</name> <value>1668246881</value> </enumeratedValue> <enumeratedValue> @@ -105855,7 +105688,7 @@ <fields> <field> <name>X4</name> - <description>Multiplies the startup_delay by 4, just in case. The reset value is controlled by a mask-programmable tiecell and is provided in case we are booting from XOSC and the default startup delay is insufficient. The reset value is 0x0.</description> + <description>Multiplies the startup_delay by 4, just in case. The reset value is controlled by a mask-programmable tiecell and is provided in case we are booting from XOSC and the default startup delay is insufficient</description> <bitRange>[20:20]</bitRange> <access>read-write</access> </field> @@ -105886,5 +105719,41 @@ </register> </registers> </peripheral> + <peripheral> + <name>VIRTUAL</name> + <baseAddress>0x00000000</baseAddress> + <interrupt> + <name>PROC0_IRQ_CTI</name> + <value>40</value> + </interrupt> + <interrupt> + <name>PROC1_IRQ_CTI</name> + <value>41</value> + </interrupt> + <interrupt> + <name>SPARE_IRQ_0</name> + <value>46</value> + </interrupt> + <interrupt> + <name>SPARE_IRQ_1</name> + <value>47</value> + </interrupt> + <interrupt> + <name>SPARE_IRQ_2</name> + <value>48</value> + </interrupt> + <interrupt> + <name>SPARE_IRQ_3</name> + <value>49</value> + </interrupt> + <interrupt> + <name>SPARE_IRQ_4</name> + <value>50</value> + </interrupt> + <interrupt> + <name>SPARE_IRQ_5</name> + <value>51</value> + </interrupt> + </peripheral> </peripherals> </device> \ No newline at end of file
diff --git a/src/rp2350/hardware_regs/include/hardware/regs/accessctrl.h b/src/rp2350/hardware_regs/include/hardware/regs/accessctrl.h index 041361f..495e7ee 100644 --- a/src/rp2350/hardware_regs/include/hardware/regs/accessctrl.h +++ b/src/rp2350/hardware_regs/include/hardware/regs/accessctrl.h
@@ -2477,93 +2477,93 @@ #define ACCESSCTRL_BUSCTRL_NSU_LSB _u(0) #define ACCESSCTRL_BUSCTRL_NSU_ACCESS "RW" // ============================================================================= -// Register : ACCESSCTRL_ADC0 +// Register : ACCESSCTRL_ADC // Description : Control whether debugger, DMA, core 0 and core 1 can access -// ADC0, and at what security/privilege levels they can do so. +// ADC, and at what security/privilege levels they can do so. // // Defaults to Secure access from any master. // // This register is writable only from a Secure, Privileged // processor or debugger, with the exception of the NSU bit, which // becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_ADC0_OFFSET _u(0x0000007c) -#define ACCESSCTRL_ADC0_BITS _u(0x000000ff) -#define ACCESSCTRL_ADC0_RESET _u(0x000000fc) +#define ACCESSCTRL_ADC_OFFSET _u(0x0000007c) +#define ACCESSCTRL_ADC_BITS _u(0x000000ff) +#define ACCESSCTRL_ADC_RESET _u(0x000000fc) // ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ADC0_DBG -// Description : If 1, ADC0 can be accessed by the debugger, at +// Field : ACCESSCTRL_ADC_DBG +// Description : If 1, ADC can be accessed by the debugger, at // security/privilege levels permitted by SP/NSP/SU/NSU in this // register. -#define ACCESSCTRL_ADC0_DBG_RESET _u(0x1) -#define ACCESSCTRL_ADC0_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_ADC0_DBG_MSB _u(7) -#define ACCESSCTRL_ADC0_DBG_LSB _u(7) -#define ACCESSCTRL_ADC0_DBG_ACCESS "RW" +#define ACCESSCTRL_ADC_DBG_RESET _u(0x1) +#define ACCESSCTRL_ADC_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_ADC_DBG_MSB _u(7) +#define ACCESSCTRL_ADC_DBG_LSB _u(7) +#define ACCESSCTRL_ADC_DBG_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ADC0_DMA -// Description : If 1, ADC0 can be accessed by the DMA, at security/privilege +// Field : ACCESSCTRL_ADC_DMA +// Description : If 1, ADC can be accessed by the DMA, at security/privilege // levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_ADC0_DMA_RESET _u(0x1) -#define ACCESSCTRL_ADC0_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_ADC0_DMA_MSB _u(6) -#define ACCESSCTRL_ADC0_DMA_LSB _u(6) -#define ACCESSCTRL_ADC0_DMA_ACCESS "RW" +#define ACCESSCTRL_ADC_DMA_RESET _u(0x1) +#define ACCESSCTRL_ADC_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_ADC_DMA_MSB _u(6) +#define ACCESSCTRL_ADC_DMA_LSB _u(6) +#define ACCESSCTRL_ADC_DMA_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ADC0_CORE1 -// Description : If 1, ADC0 can be accessed by core 1, at security/privilege +// Field : ACCESSCTRL_ADC_CORE1 +// Description : If 1, ADC can be accessed by core 1, at security/privilege // levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_ADC0_CORE1_RESET _u(0x1) -#define ACCESSCTRL_ADC0_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_ADC0_CORE1_MSB _u(5) -#define ACCESSCTRL_ADC0_CORE1_LSB _u(5) -#define ACCESSCTRL_ADC0_CORE1_ACCESS "RW" +#define ACCESSCTRL_ADC_CORE1_RESET _u(0x1) +#define ACCESSCTRL_ADC_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_ADC_CORE1_MSB _u(5) +#define ACCESSCTRL_ADC_CORE1_LSB _u(5) +#define ACCESSCTRL_ADC_CORE1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ADC0_CORE0 -// Description : If 1, ADC0 can be accessed by core 0, at security/privilege +// Field : ACCESSCTRL_ADC_CORE0 +// Description : If 1, ADC can be accessed by core 0, at security/privilege // levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_ADC0_CORE0_RESET _u(0x1) -#define ACCESSCTRL_ADC0_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_ADC0_CORE0_MSB _u(4) -#define ACCESSCTRL_ADC0_CORE0_LSB _u(4) -#define ACCESSCTRL_ADC0_CORE0_ACCESS "RW" +#define ACCESSCTRL_ADC_CORE0_RESET _u(0x1) +#define ACCESSCTRL_ADC_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_ADC_CORE0_MSB _u(4) +#define ACCESSCTRL_ADC_CORE0_LSB _u(4) +#define ACCESSCTRL_ADC_CORE0_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ADC0_SP -// Description : If 1, ADC0 can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_ADC0_SP_RESET _u(0x1) -#define ACCESSCTRL_ADC0_SP_BITS _u(0x00000008) -#define ACCESSCTRL_ADC0_SP_MSB _u(3) -#define ACCESSCTRL_ADC0_SP_LSB _u(3) -#define ACCESSCTRL_ADC0_SP_ACCESS "RW" +// Field : ACCESSCTRL_ADC_SP +// Description : If 1, ADC can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_ADC_SP_RESET _u(0x1) +#define ACCESSCTRL_ADC_SP_BITS _u(0x00000008) +#define ACCESSCTRL_ADC_SP_MSB _u(3) +#define ACCESSCTRL_ADC_SP_LSB _u(3) +#define ACCESSCTRL_ADC_SP_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ADC0_SU -// Description : If 1, and SP is also set, ADC0 can be accessed from a Secure, +// Field : ACCESSCTRL_ADC_SU +// Description : If 1, and SP is also set, ADC can be accessed from a Secure, // Unprivileged context. -#define ACCESSCTRL_ADC0_SU_RESET _u(0x1) -#define ACCESSCTRL_ADC0_SU_BITS _u(0x00000004) -#define ACCESSCTRL_ADC0_SU_MSB _u(2) -#define ACCESSCTRL_ADC0_SU_LSB _u(2) -#define ACCESSCTRL_ADC0_SU_ACCESS "RW" +#define ACCESSCTRL_ADC_SU_RESET _u(0x1) +#define ACCESSCTRL_ADC_SU_BITS _u(0x00000004) +#define ACCESSCTRL_ADC_SU_MSB _u(2) +#define ACCESSCTRL_ADC_SU_LSB _u(2) +#define ACCESSCTRL_ADC_SU_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ADC0_NSP -// Description : If 1, ADC0 can be accessed from a Non-secure, Privileged +// Field : ACCESSCTRL_ADC_NSP +// Description : If 1, ADC can be accessed from a Non-secure, Privileged // context. -#define ACCESSCTRL_ADC0_NSP_RESET _u(0x0) -#define ACCESSCTRL_ADC0_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_ADC0_NSP_MSB _u(1) -#define ACCESSCTRL_ADC0_NSP_LSB _u(1) -#define ACCESSCTRL_ADC0_NSP_ACCESS "RW" +#define ACCESSCTRL_ADC_NSP_RESET _u(0x0) +#define ACCESSCTRL_ADC_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_ADC_NSP_MSB _u(1) +#define ACCESSCTRL_ADC_NSP_LSB _u(1) +#define ACCESSCTRL_ADC_NSP_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ADC0_NSU -// Description : If 1, and NSP is also set, ADC0 can be accessed from a Non- +// Field : ACCESSCTRL_ADC_NSU +// Description : If 1, and NSP is also set, ADC can be accessed from a Non- // secure, Unprivileged context. // // This bit is writable from a Non-secure, Privileged context, if // and only if the NSP bit is set. -#define ACCESSCTRL_ADC0_NSU_RESET _u(0x0) -#define ACCESSCTRL_ADC0_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_ADC0_NSU_MSB _u(0) -#define ACCESSCTRL_ADC0_NSU_LSB _u(0) -#define ACCESSCTRL_ADC0_NSU_ACCESS "RW" +#define ACCESSCTRL_ADC_NSU_RESET _u(0x0) +#define ACCESSCTRL_ADC_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_ADC_NSU_MSB _u(0) +#define ACCESSCTRL_ADC_NSU_LSB _u(0) +#define ACCESSCTRL_ADC_NSU_ACCESS "RW" // ============================================================================= // Register : ACCESSCTRL_HSTX // Description : Control whether debugger, DMA, core 0 and core 1 can access @@ -4593,93 +4593,93 @@ #define ACCESSCTRL_WATCHDOG_NSU_LSB _u(0) #define ACCESSCTRL_WATCHDOG_NSU_ACCESS "RW" // ============================================================================= -// Register : ACCESSCTRL_RSM +// Register : ACCESSCTRL_PSM // Description : Control whether debugger, DMA, core 0 and core 1 can access -// RSM, and at what security/privilege levels they can do so. +// PSM, and at what security/privilege levels they can do so. // // Defaults to Secure, Privileged processor or debug access only. // // This register is writable only from a Secure, Privileged // processor or debugger, with the exception of the NSU bit, which // becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_RSM_OFFSET _u(0x000000dc) -#define ACCESSCTRL_RSM_BITS _u(0x000000ff) -#define ACCESSCTRL_RSM_RESET _u(0x000000b8) +#define ACCESSCTRL_PSM_OFFSET _u(0x000000dc) +#define ACCESSCTRL_PSM_BITS _u(0x000000ff) +#define ACCESSCTRL_PSM_RESET _u(0x000000b8) // ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_RSM_DBG -// Description : If 1, RSM can be accessed by the debugger, at +// Field : ACCESSCTRL_PSM_DBG +// Description : If 1, PSM can be accessed by the debugger, at // security/privilege levels permitted by SP/NSP/SU/NSU in this // register. -#define ACCESSCTRL_RSM_DBG_RESET _u(0x1) -#define ACCESSCTRL_RSM_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_RSM_DBG_MSB _u(7) -#define ACCESSCTRL_RSM_DBG_LSB _u(7) -#define ACCESSCTRL_RSM_DBG_ACCESS "RW" +#define ACCESSCTRL_PSM_DBG_RESET _u(0x1) +#define ACCESSCTRL_PSM_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_PSM_DBG_MSB _u(7) +#define ACCESSCTRL_PSM_DBG_LSB _u(7) +#define ACCESSCTRL_PSM_DBG_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_RSM_DMA -// Description : If 1, RSM can be accessed by the DMA, at security/privilege +// Field : ACCESSCTRL_PSM_DMA +// Description : If 1, PSM can be accessed by the DMA, at security/privilege // levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_RSM_DMA_RESET _u(0x0) -#define ACCESSCTRL_RSM_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_RSM_DMA_MSB _u(6) -#define ACCESSCTRL_RSM_DMA_LSB _u(6) -#define ACCESSCTRL_RSM_DMA_ACCESS "RW" +#define ACCESSCTRL_PSM_DMA_RESET _u(0x0) +#define ACCESSCTRL_PSM_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_PSM_DMA_MSB _u(6) +#define ACCESSCTRL_PSM_DMA_LSB _u(6) +#define ACCESSCTRL_PSM_DMA_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_RSM_CORE1 -// Description : If 1, RSM can be accessed by core 1, at security/privilege +// Field : ACCESSCTRL_PSM_CORE1 +// Description : If 1, PSM can be accessed by core 1, at security/privilege // levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_RSM_CORE1_RESET _u(0x1) -#define ACCESSCTRL_RSM_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_RSM_CORE1_MSB _u(5) -#define ACCESSCTRL_RSM_CORE1_LSB _u(5) -#define ACCESSCTRL_RSM_CORE1_ACCESS "RW" +#define ACCESSCTRL_PSM_CORE1_RESET _u(0x1) +#define ACCESSCTRL_PSM_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_PSM_CORE1_MSB _u(5) +#define ACCESSCTRL_PSM_CORE1_LSB _u(5) +#define ACCESSCTRL_PSM_CORE1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_RSM_CORE0 -// Description : If 1, RSM can be accessed by core 0, at security/privilege +// Field : ACCESSCTRL_PSM_CORE0 +// Description : If 1, PSM can be accessed by core 0, at security/privilege // levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_RSM_CORE0_RESET _u(0x1) -#define ACCESSCTRL_RSM_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_RSM_CORE0_MSB _u(4) -#define ACCESSCTRL_RSM_CORE0_LSB _u(4) -#define ACCESSCTRL_RSM_CORE0_ACCESS "RW" +#define ACCESSCTRL_PSM_CORE0_RESET _u(0x1) +#define ACCESSCTRL_PSM_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_PSM_CORE0_MSB _u(4) +#define ACCESSCTRL_PSM_CORE0_LSB _u(4) +#define ACCESSCTRL_PSM_CORE0_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_RSM_SP -// Description : If 1, RSM can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_RSM_SP_RESET _u(0x1) -#define ACCESSCTRL_RSM_SP_BITS _u(0x00000008) -#define ACCESSCTRL_RSM_SP_MSB _u(3) -#define ACCESSCTRL_RSM_SP_LSB _u(3) -#define ACCESSCTRL_RSM_SP_ACCESS "RW" +// Field : ACCESSCTRL_PSM_SP +// Description : If 1, PSM can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_PSM_SP_RESET _u(0x1) +#define ACCESSCTRL_PSM_SP_BITS _u(0x00000008) +#define ACCESSCTRL_PSM_SP_MSB _u(3) +#define ACCESSCTRL_PSM_SP_LSB _u(3) +#define ACCESSCTRL_PSM_SP_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_RSM_SU -// Description : If 1, and SP is also set, RSM can be accessed from a Secure, +// Field : ACCESSCTRL_PSM_SU +// Description : If 1, and SP is also set, PSM can be accessed from a Secure, // Unprivileged context. -#define ACCESSCTRL_RSM_SU_RESET _u(0x0) -#define ACCESSCTRL_RSM_SU_BITS _u(0x00000004) -#define ACCESSCTRL_RSM_SU_MSB _u(2) -#define ACCESSCTRL_RSM_SU_LSB _u(2) -#define ACCESSCTRL_RSM_SU_ACCESS "RW" +#define ACCESSCTRL_PSM_SU_RESET _u(0x0) +#define ACCESSCTRL_PSM_SU_BITS _u(0x00000004) +#define ACCESSCTRL_PSM_SU_MSB _u(2) +#define ACCESSCTRL_PSM_SU_LSB _u(2) +#define ACCESSCTRL_PSM_SU_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_RSM_NSP -// Description : If 1, RSM can be accessed from a Non-secure, Privileged +// Field : ACCESSCTRL_PSM_NSP +// Description : If 1, PSM can be accessed from a Non-secure, Privileged // context. -#define ACCESSCTRL_RSM_NSP_RESET _u(0x0) -#define ACCESSCTRL_RSM_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_RSM_NSP_MSB _u(1) -#define ACCESSCTRL_RSM_NSP_LSB _u(1) -#define ACCESSCTRL_RSM_NSP_ACCESS "RW" +#define ACCESSCTRL_PSM_NSP_RESET _u(0x0) +#define ACCESSCTRL_PSM_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_PSM_NSP_MSB _u(1) +#define ACCESSCTRL_PSM_NSP_LSB _u(1) +#define ACCESSCTRL_PSM_NSP_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_RSM_NSU -// Description : If 1, and NSP is also set, RSM can be accessed from a Non- +// Field : ACCESSCTRL_PSM_NSU +// Description : If 1, and NSP is also set, PSM can be accessed from a Non- // secure, Unprivileged context. // // This bit is writable from a Non-secure, Privileged context, if // and only if the NSP bit is set. -#define ACCESSCTRL_RSM_NSU_RESET _u(0x0) -#define ACCESSCTRL_RSM_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_RSM_NSU_MSB _u(0) -#define ACCESSCTRL_RSM_NSU_LSB _u(0) -#define ACCESSCTRL_RSM_NSU_ACCESS "RW" +#define ACCESSCTRL_PSM_NSU_RESET _u(0x0) +#define ACCESSCTRL_PSM_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_PSM_NSU_MSB _u(0) +#define ACCESSCTRL_PSM_NSU_LSB _u(0) +#define ACCESSCTRL_PSM_NSU_ACCESS "RW" // ============================================================================= // Register : ACCESSCTRL_XIP_CTRL // Description : Control whether debugger, DMA, core 0 and core 1 can access
diff --git a/src/rp2350/hardware_regs/include/hardware/regs/busctrl.h b/src/rp2350/hardware_regs/include/hardware/regs/busctrl.h index 4119371..7a5a302 100644 --- a/src/rp2350/hardware_regs/include/hardware/regs/busctrl.h +++ b/src/rp2350/hardware_regs/include/hardware/regs/busctrl.h
@@ -105,14 +105,14 @@ // a stall on the downstream bus; STALL_UPSTREAM, count cycles // where any master stalled for any reason, including contention // from other masters. -// 0x00 -> siob_proc1_stall_upstream -// 0x01 -> siob_proc1_stall_downstream -// 0x02 -> siob_proc1_access_contested -// 0x03 -> siob_proc1_access -// 0x04 -> siob_proc0_stall_upstream -// 0x05 -> siob_proc0_stall_downstream -// 0x06 -> siob_proc0_access_contested -// 0x07 -> siob_proc0_access +// 0x00 -> sio_proc1_stall_upstream +// 0x01 -> sio_proc1_stall_downstream +// 0x02 -> sio_proc1_access_contested +// 0x03 -> sio_proc1_access +// 0x04 -> sio_proc0_stall_upstream +// 0x05 -> sio_proc0_stall_downstream +// 0x06 -> sio_proc0_access_contested +// 0x07 -> sio_proc0_access // 0x08 -> apb_stall_upstream // 0x09 -> apb_stall_downstream // 0x0a -> apb_access_contested @@ -179,14 +179,14 @@ #define BUSCTRL_PERFSEL0_MSB _u(6) #define BUSCTRL_PERFSEL0_LSB _u(0) #define BUSCTRL_PERFSEL0_ACCESS "RW" -#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00) -#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01) -#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02) -#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_ACCESS _u(0x03) -#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04) -#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05) -#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06) -#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_ACCESS _u(0x07) +#define BUSCTRL_PERFSEL0_VALUE_SIO_PROC1_STALL_UPSTREAM _u(0x00) +#define BUSCTRL_PERFSEL0_VALUE_SIO_PROC1_STALL_DOWNSTREAM _u(0x01) +#define BUSCTRL_PERFSEL0_VALUE_SIO_PROC1_ACCESS_CONTESTED _u(0x02) +#define BUSCTRL_PERFSEL0_VALUE_SIO_PROC1_ACCESS _u(0x03) +#define BUSCTRL_PERFSEL0_VALUE_SIO_PROC0_STALL_UPSTREAM _u(0x04) +#define BUSCTRL_PERFSEL0_VALUE_SIO_PROC0_STALL_DOWNSTREAM _u(0x05) +#define BUSCTRL_PERFSEL0_VALUE_SIO_PROC0_ACCESS_CONTESTED _u(0x06) +#define BUSCTRL_PERFSEL0_VALUE_SIO_PROC0_ACCESS _u(0x07) #define BUSCTRL_PERFSEL0_VALUE_APB_STALL_UPSTREAM _u(0x08) #define BUSCTRL_PERFSEL0_VALUE_APB_STALL_DOWNSTREAM _u(0x09) #define BUSCTRL_PERFSEL0_VALUE_APB_ACCESS_CONTESTED _u(0x0a) @@ -272,14 +272,14 @@ // a stall on the downstream bus; STALL_UPSTREAM, count cycles // where any master stalled for any reason, including contention // from other masters. -// 0x00 -> siob_proc1_stall_upstream -// 0x01 -> siob_proc1_stall_downstream -// 0x02 -> siob_proc1_access_contested -// 0x03 -> siob_proc1_access -// 0x04 -> siob_proc0_stall_upstream -// 0x05 -> siob_proc0_stall_downstream -// 0x06 -> siob_proc0_access_contested -// 0x07 -> siob_proc0_access +// 0x00 -> sio_proc1_stall_upstream +// 0x01 -> sio_proc1_stall_downstream +// 0x02 -> sio_proc1_access_contested +// 0x03 -> sio_proc1_access +// 0x04 -> sio_proc0_stall_upstream +// 0x05 -> sio_proc0_stall_downstream +// 0x06 -> sio_proc0_access_contested +// 0x07 -> sio_proc0_access // 0x08 -> apb_stall_upstream // 0x09 -> apb_stall_downstream // 0x0a -> apb_access_contested @@ -346,14 +346,14 @@ #define BUSCTRL_PERFSEL1_MSB _u(6) #define BUSCTRL_PERFSEL1_LSB _u(0) #define BUSCTRL_PERFSEL1_ACCESS "RW" -#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00) -#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01) -#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02) -#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_ACCESS _u(0x03) -#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04) -#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05) -#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06) -#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_ACCESS _u(0x07) +#define BUSCTRL_PERFSEL1_VALUE_SIO_PROC1_STALL_UPSTREAM _u(0x00) +#define BUSCTRL_PERFSEL1_VALUE_SIO_PROC1_STALL_DOWNSTREAM _u(0x01) +#define BUSCTRL_PERFSEL1_VALUE_SIO_PROC1_ACCESS_CONTESTED _u(0x02) +#define BUSCTRL_PERFSEL1_VALUE_SIO_PROC1_ACCESS _u(0x03) +#define BUSCTRL_PERFSEL1_VALUE_SIO_PROC0_STALL_UPSTREAM _u(0x04) +#define BUSCTRL_PERFSEL1_VALUE_SIO_PROC0_STALL_DOWNSTREAM _u(0x05) +#define BUSCTRL_PERFSEL1_VALUE_SIO_PROC0_ACCESS_CONTESTED _u(0x06) +#define BUSCTRL_PERFSEL1_VALUE_SIO_PROC0_ACCESS _u(0x07) #define BUSCTRL_PERFSEL1_VALUE_APB_STALL_UPSTREAM _u(0x08) #define BUSCTRL_PERFSEL1_VALUE_APB_STALL_DOWNSTREAM _u(0x09) #define BUSCTRL_PERFSEL1_VALUE_APB_ACCESS_CONTESTED _u(0x0a) @@ -439,14 +439,14 @@ // a stall on the downstream bus; STALL_UPSTREAM, count cycles // where any master stalled for any reason, including contention // from other masters. -// 0x00 -> siob_proc1_stall_upstream -// 0x01 -> siob_proc1_stall_downstream -// 0x02 -> siob_proc1_access_contested -// 0x03 -> siob_proc1_access -// 0x04 -> siob_proc0_stall_upstream -// 0x05 -> siob_proc0_stall_downstream -// 0x06 -> siob_proc0_access_contested -// 0x07 -> siob_proc0_access +// 0x00 -> sio_proc1_stall_upstream +// 0x01 -> sio_proc1_stall_downstream +// 0x02 -> sio_proc1_access_contested +// 0x03 -> sio_proc1_access +// 0x04 -> sio_proc0_stall_upstream +// 0x05 -> sio_proc0_stall_downstream +// 0x06 -> sio_proc0_access_contested +// 0x07 -> sio_proc0_access // 0x08 -> apb_stall_upstream // 0x09 -> apb_stall_downstream // 0x0a -> apb_access_contested @@ -513,14 +513,14 @@ #define BUSCTRL_PERFSEL2_MSB _u(6) #define BUSCTRL_PERFSEL2_LSB _u(0) #define BUSCTRL_PERFSEL2_ACCESS "RW" -#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00) -#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01) -#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02) -#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_ACCESS _u(0x03) -#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04) -#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05) -#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06) -#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_ACCESS _u(0x07) +#define BUSCTRL_PERFSEL2_VALUE_SIO_PROC1_STALL_UPSTREAM _u(0x00) +#define BUSCTRL_PERFSEL2_VALUE_SIO_PROC1_STALL_DOWNSTREAM _u(0x01) +#define BUSCTRL_PERFSEL2_VALUE_SIO_PROC1_ACCESS_CONTESTED _u(0x02) +#define BUSCTRL_PERFSEL2_VALUE_SIO_PROC1_ACCESS _u(0x03) +#define BUSCTRL_PERFSEL2_VALUE_SIO_PROC0_STALL_UPSTREAM _u(0x04) +#define BUSCTRL_PERFSEL2_VALUE_SIO_PROC0_STALL_DOWNSTREAM _u(0x05) +#define BUSCTRL_PERFSEL2_VALUE_SIO_PROC0_ACCESS_CONTESTED _u(0x06) +#define BUSCTRL_PERFSEL2_VALUE_SIO_PROC0_ACCESS _u(0x07) #define BUSCTRL_PERFSEL2_VALUE_APB_STALL_UPSTREAM _u(0x08) #define BUSCTRL_PERFSEL2_VALUE_APB_STALL_DOWNSTREAM _u(0x09) #define BUSCTRL_PERFSEL2_VALUE_APB_ACCESS_CONTESTED _u(0x0a) @@ -606,14 +606,14 @@ // a stall on the downstream bus; STALL_UPSTREAM, count cycles // where any master stalled for any reason, including contention // from other masters. -// 0x00 -> siob_proc1_stall_upstream -// 0x01 -> siob_proc1_stall_downstream -// 0x02 -> siob_proc1_access_contested -// 0x03 -> siob_proc1_access -// 0x04 -> siob_proc0_stall_upstream -// 0x05 -> siob_proc0_stall_downstream -// 0x06 -> siob_proc0_access_contested -// 0x07 -> siob_proc0_access +// 0x00 -> sio_proc1_stall_upstream +// 0x01 -> sio_proc1_stall_downstream +// 0x02 -> sio_proc1_access_contested +// 0x03 -> sio_proc1_access +// 0x04 -> sio_proc0_stall_upstream +// 0x05 -> sio_proc0_stall_downstream +// 0x06 -> sio_proc0_access_contested +// 0x07 -> sio_proc0_access // 0x08 -> apb_stall_upstream // 0x09 -> apb_stall_downstream // 0x0a -> apb_access_contested @@ -680,14 +680,14 @@ #define BUSCTRL_PERFSEL3_MSB _u(6) #define BUSCTRL_PERFSEL3_LSB _u(0) #define BUSCTRL_PERFSEL3_ACCESS "RW" -#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00) -#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01) -#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02) -#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_ACCESS _u(0x03) -#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04) -#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05) -#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06) -#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_ACCESS _u(0x07) +#define BUSCTRL_PERFSEL3_VALUE_SIO_PROC1_STALL_UPSTREAM _u(0x00) +#define BUSCTRL_PERFSEL3_VALUE_SIO_PROC1_STALL_DOWNSTREAM _u(0x01) +#define BUSCTRL_PERFSEL3_VALUE_SIO_PROC1_ACCESS_CONTESTED _u(0x02) +#define BUSCTRL_PERFSEL3_VALUE_SIO_PROC1_ACCESS _u(0x03) +#define BUSCTRL_PERFSEL3_VALUE_SIO_PROC0_STALL_UPSTREAM _u(0x04) +#define BUSCTRL_PERFSEL3_VALUE_SIO_PROC0_STALL_DOWNSTREAM _u(0x05) +#define BUSCTRL_PERFSEL3_VALUE_SIO_PROC0_ACCESS_CONTESTED _u(0x06) +#define BUSCTRL_PERFSEL3_VALUE_SIO_PROC0_ACCESS _u(0x07) #define BUSCTRL_PERFSEL3_VALUE_APB_STALL_UPSTREAM _u(0x08) #define BUSCTRL_PERFSEL3_VALUE_APB_STALL_DOWNSTREAM _u(0x09) #define BUSCTRL_PERFSEL3_VALUE_APB_ACCESS_CONTESTED _u(0x0a)
diff --git a/src/rp2350/hardware_regs/include/hardware/regs/dma.h b/src/rp2350/hardware_regs/include/hardware/regs/dma.h index e08895e..d1007f8 100644 --- a/src/rp2350/hardware_regs/include/hardware/regs/dma.h +++ b/src/rp2350/hardware_regs/include/hardware/regs/dma.h
@@ -205,6 +205,61 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. +// 0x00 -> Select PIO0's TX FIFO 0 as TREQ +// 0x01 -> Select PIO0's TX FIFO 1 as TREQ +// 0x02 -> Select PIO0's TX FIFO 2 as TREQ +// 0x03 -> Select PIO0's TX FIFO 3 as TREQ +// 0x04 -> Select PIO0's RX FIFO 0 as TREQ +// 0x05 -> Select PIO0's RX FIFO 1 as TREQ +// 0x06 -> Select PIO0's RX FIFO 2 as TREQ +// 0x07 -> Select PIO0's RX FIFO 3 as TREQ +// 0x08 -> Select PIO1's TX FIFO 0 as TREQ +// 0x09 -> Select PIO1's TX FIFO 1 as TREQ +// 0x0a -> Select PIO1's TX FIFO 2 as TREQ +// 0x0b -> Select PIO1's TX FIFO 3 as TREQ +// 0x0c -> Select PIO1's RX FIFO 0 as TREQ +// 0x0d -> Select PIO1's RX FIFO 1 as TREQ +// 0x0e -> Select PIO1's RX FIFO 2 as TREQ +// 0x0f -> Select PIO1's RX FIFO 3 as TREQ +// 0x10 -> Select PIO2's TX FIFO 0 as TREQ +// 0x11 -> Select PIO2's TX FIFO 1 as TREQ +// 0x12 -> Select PIO2's TX FIFO 2 as TREQ +// 0x13 -> Select PIO2's TX FIFO 3 as TREQ +// 0x14 -> Select PIO2's RX FIFO 0 as TREQ +// 0x15 -> Select PIO2's RX FIFO 1 as TREQ +// 0x16 -> Select PIO2's RX FIFO 2 as TREQ +// 0x17 -> Select PIO2's RX FIFO 3 as TREQ +// 0x18 -> Select SPI0's TX FIFO as TREQ +// 0x19 -> Select SPI0's RX FIFO as TREQ +// 0x1a -> Select SPI1's TX FIFO as TREQ +// 0x1b -> Select SPI1's RX FIFO as TREQ +// 0x1c -> Select UART0's TX FIFO as TREQ +// 0x1d -> Select UART0's RX FIFO as TREQ +// 0x1e -> Select UART1's TX FIFO as TREQ +// 0x1f -> Select UART1's RX FIFO as TREQ +// 0x20 -> Select PWM Counter 0's Wrap Value as TREQ +// 0x21 -> Select PWM Counter 1's Wrap Value as TREQ +// 0x22 -> Select PWM Counter 2's Wrap Value as TREQ +// 0x23 -> Select PWM Counter 3's Wrap Value as TREQ +// 0x24 -> Select PWM Counter 4's Wrap Value as TREQ +// 0x25 -> Select PWM Counter 5's Wrap Value as TREQ +// 0x26 -> Select PWM Counter 6's Wrap Value as TREQ +// 0x27 -> Select PWM Counter 7's Wrap Value as TREQ +// 0x28 -> Select PWM Counter 8's Wrap Value as TREQ +// 0x29 -> Select PWM Counter 9's Wrap Value as TREQ +// 0x2a -> Select PWM Counter 10's Wrap Value as TREQ +// 0x2b -> Select PWM Counter 11's Wrap Value as TREQ +// 0x2c -> Select I2C0's TX FIFO as TREQ +// 0x2d -> Select I2C0's RX FIFO as TREQ +// 0x2e -> Select I2C1's TX FIFO as TREQ +// 0x2f -> Select I2C1's RX FIFO as TREQ +// 0x30 -> Select the ADC as TREQ +// 0x31 -> Select the XIP Streaming FIFO as TREQ +// 0x32 -> Select XIP_QMITX as TREQ +// 0x33 -> Select XIP_QMIRX as TREQ +// 0x34 -> Select HSTX as TREQ +// 0x35 -> Select CORESIGHT as TREQ +// 0x36 -> Select SHA256 as TREQ #define DMA_CH0_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) #define DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) #define DMA_CH0_CTRL_TRIG_TREQ_SEL_MSB _u(22) @@ -215,6 +270,61 @@ #define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) #define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX0 _u(0x00) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX1 _u(0x01) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX2 _u(0x02) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX3 _u(0x03) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX0 _u(0x04) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX1 _u(0x05) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX2 _u(0x06) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX3 _u(0x07) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX0 _u(0x08) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX1 _u(0x09) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX2 _u(0x0a) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX3 _u(0x0b) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX0 _u(0x0c) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX1 _u(0x0d) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX2 _u(0x0e) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX3 _u(0x0f) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX0 _u(0x10) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX1 _u(0x11) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX2 _u(0x12) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX3 _u(0x13) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX0 _u(0x14) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX1 _u(0x15) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX2 _u(0x16) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX3 _u(0x17) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_TX _u(0x18) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_RX _u(0x19) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_TX _u(0x1a) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_RX _u(0x1b) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_UART0_TX _u(0x1c) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_UART0_RX _u(0x1d) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_UART1_TX _u(0x1e) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_UART1_RX _u(0x1f) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP0 _u(0x20) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP1 _u(0x21) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP2 _u(0x22) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP3 _u(0x23) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP4 _u(0x24) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP5 _u(0x25) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP6 _u(0x26) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP7 _u(0x27) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP8 _u(0x28) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP9 _u(0x29) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP10 _u(0x2a) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP11 _u(0x2b) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_TX _u(0x2c) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_RX _u(0x2d) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_TX _u(0x2e) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_RX _u(0x2f) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_ADC _u(0x30) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_XIP_STREAM _u(0x31) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMITX _u(0x32) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMIRX _u(0x33) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_HSTX _u(0x34) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_CORESIGHT _u(0x35) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_SHA256 _u(0x36) // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel @@ -658,6 +768,61 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. +// 0x00 -> Select PIO0's TX FIFO 0 as TREQ +// 0x01 -> Select PIO0's TX FIFO 1 as TREQ +// 0x02 -> Select PIO0's TX FIFO 2 as TREQ +// 0x03 -> Select PIO0's TX FIFO 3 as TREQ +// 0x04 -> Select PIO0's RX FIFO 0 as TREQ +// 0x05 -> Select PIO0's RX FIFO 1 as TREQ +// 0x06 -> Select PIO0's RX FIFO 2 as TREQ +// 0x07 -> Select PIO0's RX FIFO 3 as TREQ +// 0x08 -> Select PIO1's TX FIFO 0 as TREQ +// 0x09 -> Select PIO1's TX FIFO 1 as TREQ +// 0x0a -> Select PIO1's TX FIFO 2 as TREQ +// 0x0b -> Select PIO1's TX FIFO 3 as TREQ +// 0x0c -> Select PIO1's RX FIFO 0 as TREQ +// 0x0d -> Select PIO1's RX FIFO 1 as TREQ +// 0x0e -> Select PIO1's RX FIFO 2 as TREQ +// 0x0f -> Select PIO1's RX FIFO 3 as TREQ +// 0x10 -> Select PIO2's TX FIFO 0 as TREQ +// 0x11 -> Select PIO2's TX FIFO 1 as TREQ +// 0x12 -> Select PIO2's TX FIFO 2 as TREQ +// 0x13 -> Select PIO2's TX FIFO 3 as TREQ +// 0x14 -> Select PIO2's RX FIFO 0 as TREQ +// 0x15 -> Select PIO2's RX FIFO 1 as TREQ +// 0x16 -> Select PIO2's RX FIFO 2 as TREQ +// 0x17 -> Select PIO2's RX FIFO 3 as TREQ +// 0x18 -> Select SPI0's TX FIFO as TREQ +// 0x19 -> Select SPI0's RX FIFO as TREQ +// 0x1a -> Select SPI1's TX FIFO as TREQ +// 0x1b -> Select SPI1's RX FIFO as TREQ +// 0x1c -> Select UART0's TX FIFO as TREQ +// 0x1d -> Select UART0's RX FIFO as TREQ +// 0x1e -> Select UART1's TX FIFO as TREQ +// 0x1f -> Select UART1's RX FIFO as TREQ +// 0x20 -> Select PWM Counter 0's Wrap Value as TREQ +// 0x21 -> Select PWM Counter 1's Wrap Value as TREQ +// 0x22 -> Select PWM Counter 2's Wrap Value as TREQ +// 0x23 -> Select PWM Counter 3's Wrap Value as TREQ +// 0x24 -> Select PWM Counter 4's Wrap Value as TREQ +// 0x25 -> Select PWM Counter 5's Wrap Value as TREQ +// 0x26 -> Select PWM Counter 6's Wrap Value as TREQ +// 0x27 -> Select PWM Counter 7's Wrap Value as TREQ +// 0x28 -> Select PWM Counter 8's Wrap Value as TREQ +// 0x29 -> Select PWM Counter 9's Wrap Value as TREQ +// 0x2a -> Select PWM Counter 10's Wrap Value as TREQ +// 0x2b -> Select PWM Counter 11's Wrap Value as TREQ +// 0x2c -> Select I2C0's TX FIFO as TREQ +// 0x2d -> Select I2C0's RX FIFO as TREQ +// 0x2e -> Select I2C1's TX FIFO as TREQ +// 0x2f -> Select I2C1's RX FIFO as TREQ +// 0x30 -> Select the ADC as TREQ +// 0x31 -> Select the XIP Streaming FIFO as TREQ +// 0x32 -> Select XIP_QMITX as TREQ +// 0x33 -> Select XIP_QMIRX as TREQ +// 0x34 -> Select HSTX as TREQ +// 0x35 -> Select CORESIGHT as TREQ +// 0x36 -> Select SHA256 as TREQ #define DMA_CH1_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) #define DMA_CH1_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) #define DMA_CH1_CTRL_TRIG_TREQ_SEL_MSB _u(22) @@ -668,6 +833,61 @@ #define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) #define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX0 _u(0x00) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX1 _u(0x01) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX2 _u(0x02) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX3 _u(0x03) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX0 _u(0x04) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX1 _u(0x05) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX2 _u(0x06) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX3 _u(0x07) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX0 _u(0x08) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX1 _u(0x09) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX2 _u(0x0a) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX3 _u(0x0b) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX0 _u(0x0c) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX1 _u(0x0d) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX2 _u(0x0e) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX3 _u(0x0f) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX0 _u(0x10) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX1 _u(0x11) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX2 _u(0x12) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX3 _u(0x13) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX0 _u(0x14) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX1 _u(0x15) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX2 _u(0x16) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX3 _u(0x17) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_TX _u(0x18) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_RX _u(0x19) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_TX _u(0x1a) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_RX _u(0x1b) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_UART0_TX _u(0x1c) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_UART0_RX _u(0x1d) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_UART1_TX _u(0x1e) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_UART1_RX _u(0x1f) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP0 _u(0x20) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP1 _u(0x21) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP2 _u(0x22) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP3 _u(0x23) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP4 _u(0x24) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP5 _u(0x25) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP6 _u(0x26) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP7 _u(0x27) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP8 _u(0x28) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP9 _u(0x29) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP10 _u(0x2a) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP11 _u(0x2b) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_TX _u(0x2c) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_RX _u(0x2d) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_TX _u(0x2e) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_RX _u(0x2f) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_ADC _u(0x30) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_XIP_STREAM _u(0x31) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMITX _u(0x32) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMIRX _u(0x33) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_HSTX _u(0x34) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_CORESIGHT _u(0x35) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_SHA256 _u(0x36) // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel @@ -1111,6 +1331,61 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. +// 0x00 -> Select PIO0's TX FIFO 0 as TREQ +// 0x01 -> Select PIO0's TX FIFO 1 as TREQ +// 0x02 -> Select PIO0's TX FIFO 2 as TREQ +// 0x03 -> Select PIO0's TX FIFO 3 as TREQ +// 0x04 -> Select PIO0's RX FIFO 0 as TREQ +// 0x05 -> Select PIO0's RX FIFO 1 as TREQ +// 0x06 -> Select PIO0's RX FIFO 2 as TREQ +// 0x07 -> Select PIO0's RX FIFO 3 as TREQ +// 0x08 -> Select PIO1's TX FIFO 0 as TREQ +// 0x09 -> Select PIO1's TX FIFO 1 as TREQ +// 0x0a -> Select PIO1's TX FIFO 2 as TREQ +// 0x0b -> Select PIO1's TX FIFO 3 as TREQ +// 0x0c -> Select PIO1's RX FIFO 0 as TREQ +// 0x0d -> Select PIO1's RX FIFO 1 as TREQ +// 0x0e -> Select PIO1's RX FIFO 2 as TREQ +// 0x0f -> Select PIO1's RX FIFO 3 as TREQ +// 0x10 -> Select PIO2's TX FIFO 0 as TREQ +// 0x11 -> Select PIO2's TX FIFO 1 as TREQ +// 0x12 -> Select PIO2's TX FIFO 2 as TREQ +// 0x13 -> Select PIO2's TX FIFO 3 as TREQ +// 0x14 -> Select PIO2's RX FIFO 0 as TREQ +// 0x15 -> Select PIO2's RX FIFO 1 as TREQ +// 0x16 -> Select PIO2's RX FIFO 2 as TREQ +// 0x17 -> Select PIO2's RX FIFO 3 as TREQ +// 0x18 -> Select SPI0's TX FIFO as TREQ +// 0x19 -> Select SPI0's RX FIFO as TREQ +// 0x1a -> Select SPI1's TX FIFO as TREQ +// 0x1b -> Select SPI1's RX FIFO as TREQ +// 0x1c -> Select UART0's TX FIFO as TREQ +// 0x1d -> Select UART0's RX FIFO as TREQ +// 0x1e -> Select UART1's TX FIFO as TREQ +// 0x1f -> Select UART1's RX FIFO as TREQ +// 0x20 -> Select PWM Counter 0's Wrap Value as TREQ +// 0x21 -> Select PWM Counter 1's Wrap Value as TREQ +// 0x22 -> Select PWM Counter 2's Wrap Value as TREQ +// 0x23 -> Select PWM Counter 3's Wrap Value as TREQ +// 0x24 -> Select PWM Counter 4's Wrap Value as TREQ +// 0x25 -> Select PWM Counter 5's Wrap Value as TREQ +// 0x26 -> Select PWM Counter 6's Wrap Value as TREQ +// 0x27 -> Select PWM Counter 7's Wrap Value as TREQ +// 0x28 -> Select PWM Counter 8's Wrap Value as TREQ +// 0x29 -> Select PWM Counter 9's Wrap Value as TREQ +// 0x2a -> Select PWM Counter 10's Wrap Value as TREQ +// 0x2b -> Select PWM Counter 11's Wrap Value as TREQ +// 0x2c -> Select I2C0's TX FIFO as TREQ +// 0x2d -> Select I2C0's RX FIFO as TREQ +// 0x2e -> Select I2C1's TX FIFO as TREQ +// 0x2f -> Select I2C1's RX FIFO as TREQ +// 0x30 -> Select the ADC as TREQ +// 0x31 -> Select the XIP Streaming FIFO as TREQ +// 0x32 -> Select XIP_QMITX as TREQ +// 0x33 -> Select XIP_QMIRX as TREQ +// 0x34 -> Select HSTX as TREQ +// 0x35 -> Select CORESIGHT as TREQ +// 0x36 -> Select SHA256 as TREQ #define DMA_CH2_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) #define DMA_CH2_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) #define DMA_CH2_CTRL_TRIG_TREQ_SEL_MSB _u(22) @@ -1121,6 +1396,61 @@ #define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) #define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX0 _u(0x00) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX1 _u(0x01) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX2 _u(0x02) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX3 _u(0x03) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX0 _u(0x04) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX1 _u(0x05) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX2 _u(0x06) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX3 _u(0x07) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX0 _u(0x08) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX1 _u(0x09) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX2 _u(0x0a) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX3 _u(0x0b) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX0 _u(0x0c) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX1 _u(0x0d) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX2 _u(0x0e) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX3 _u(0x0f) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX0 _u(0x10) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX1 _u(0x11) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX2 _u(0x12) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX3 _u(0x13) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX0 _u(0x14) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX1 _u(0x15) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX2 _u(0x16) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX3 _u(0x17) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_TX _u(0x18) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_RX _u(0x19) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_TX _u(0x1a) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_RX _u(0x1b) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_UART0_TX _u(0x1c) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_UART0_RX _u(0x1d) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_UART1_TX _u(0x1e) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_UART1_RX _u(0x1f) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP0 _u(0x20) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP1 _u(0x21) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP2 _u(0x22) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP3 _u(0x23) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP4 _u(0x24) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP5 _u(0x25) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP6 _u(0x26) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP7 _u(0x27) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP8 _u(0x28) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP9 _u(0x29) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP10 _u(0x2a) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP11 _u(0x2b) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_TX _u(0x2c) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_RX _u(0x2d) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_TX _u(0x2e) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_RX _u(0x2f) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_ADC _u(0x30) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_XIP_STREAM _u(0x31) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMITX _u(0x32) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMIRX _u(0x33) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_HSTX _u(0x34) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_CORESIGHT _u(0x35) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_SHA256 _u(0x36) // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel @@ -1564,6 +1894,61 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. +// 0x00 -> Select PIO0's TX FIFO 0 as TREQ +// 0x01 -> Select PIO0's TX FIFO 1 as TREQ +// 0x02 -> Select PIO0's TX FIFO 2 as TREQ +// 0x03 -> Select PIO0's TX FIFO 3 as TREQ +// 0x04 -> Select PIO0's RX FIFO 0 as TREQ +// 0x05 -> Select PIO0's RX FIFO 1 as TREQ +// 0x06 -> Select PIO0's RX FIFO 2 as TREQ +// 0x07 -> Select PIO0's RX FIFO 3 as TREQ +// 0x08 -> Select PIO1's TX FIFO 0 as TREQ +// 0x09 -> Select PIO1's TX FIFO 1 as TREQ +// 0x0a -> Select PIO1's TX FIFO 2 as TREQ +// 0x0b -> Select PIO1's TX FIFO 3 as TREQ +// 0x0c -> Select PIO1's RX FIFO 0 as TREQ +// 0x0d -> Select PIO1's RX FIFO 1 as TREQ +// 0x0e -> Select PIO1's RX FIFO 2 as TREQ +// 0x0f -> Select PIO1's RX FIFO 3 as TREQ +// 0x10 -> Select PIO2's TX FIFO 0 as TREQ +// 0x11 -> Select PIO2's TX FIFO 1 as TREQ +// 0x12 -> Select PIO2's TX FIFO 2 as TREQ +// 0x13 -> Select PIO2's TX FIFO 3 as TREQ +// 0x14 -> Select PIO2's RX FIFO 0 as TREQ +// 0x15 -> Select PIO2's RX FIFO 1 as TREQ +// 0x16 -> Select PIO2's RX FIFO 2 as TREQ +// 0x17 -> Select PIO2's RX FIFO 3 as TREQ +// 0x18 -> Select SPI0's TX FIFO as TREQ +// 0x19 -> Select SPI0's RX FIFO as TREQ +// 0x1a -> Select SPI1's TX FIFO as TREQ +// 0x1b -> Select SPI1's RX FIFO as TREQ +// 0x1c -> Select UART0's TX FIFO as TREQ +// 0x1d -> Select UART0's RX FIFO as TREQ +// 0x1e -> Select UART1's TX FIFO as TREQ +// 0x1f -> Select UART1's RX FIFO as TREQ +// 0x20 -> Select PWM Counter 0's Wrap Value as TREQ +// 0x21 -> Select PWM Counter 1's Wrap Value as TREQ +// 0x22 -> Select PWM Counter 2's Wrap Value as TREQ +// 0x23 -> Select PWM Counter 3's Wrap Value as TREQ +// 0x24 -> Select PWM Counter 4's Wrap Value as TREQ +// 0x25 -> Select PWM Counter 5's Wrap Value as TREQ +// 0x26 -> Select PWM Counter 6's Wrap Value as TREQ +// 0x27 -> Select PWM Counter 7's Wrap Value as TREQ +// 0x28 -> Select PWM Counter 8's Wrap Value as TREQ +// 0x29 -> Select PWM Counter 9's Wrap Value as TREQ +// 0x2a -> Select PWM Counter 10's Wrap Value as TREQ +// 0x2b -> Select PWM Counter 11's Wrap Value as TREQ +// 0x2c -> Select I2C0's TX FIFO as TREQ +// 0x2d -> Select I2C0's RX FIFO as TREQ +// 0x2e -> Select I2C1's TX FIFO as TREQ +// 0x2f -> Select I2C1's RX FIFO as TREQ +// 0x30 -> Select the ADC as TREQ +// 0x31 -> Select the XIP Streaming FIFO as TREQ +// 0x32 -> Select XIP_QMITX as TREQ +// 0x33 -> Select XIP_QMIRX as TREQ +// 0x34 -> Select HSTX as TREQ +// 0x35 -> Select CORESIGHT as TREQ +// 0x36 -> Select SHA256 as TREQ #define DMA_CH3_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) #define DMA_CH3_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) #define DMA_CH3_CTRL_TRIG_TREQ_SEL_MSB _u(22) @@ -1574,6 +1959,61 @@ #define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) #define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX0 _u(0x00) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX1 _u(0x01) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX2 _u(0x02) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX3 _u(0x03) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX0 _u(0x04) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX1 _u(0x05) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX2 _u(0x06) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX3 _u(0x07) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX0 _u(0x08) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX1 _u(0x09) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX2 _u(0x0a) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX3 _u(0x0b) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX0 _u(0x0c) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX1 _u(0x0d) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX2 _u(0x0e) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX3 _u(0x0f) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX0 _u(0x10) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX1 _u(0x11) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX2 _u(0x12) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX3 _u(0x13) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX0 _u(0x14) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX1 _u(0x15) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX2 _u(0x16) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX3 _u(0x17) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_TX _u(0x18) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_RX _u(0x19) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_TX _u(0x1a) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_RX _u(0x1b) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_UART0_TX _u(0x1c) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_UART0_RX _u(0x1d) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_UART1_TX _u(0x1e) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_UART1_RX _u(0x1f) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP0 _u(0x20) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP1 _u(0x21) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP2 _u(0x22) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP3 _u(0x23) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP4 _u(0x24) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP5 _u(0x25) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP6 _u(0x26) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP7 _u(0x27) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP8 _u(0x28) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP9 _u(0x29) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP10 _u(0x2a) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP11 _u(0x2b) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_TX _u(0x2c) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_RX _u(0x2d) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_TX _u(0x2e) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_RX _u(0x2f) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_ADC _u(0x30) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_XIP_STREAM _u(0x31) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMITX _u(0x32) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMIRX _u(0x33) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_HSTX _u(0x34) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_CORESIGHT _u(0x35) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_SHA256 _u(0x36) // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel @@ -2017,6 +2457,61 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. +// 0x00 -> Select PIO0's TX FIFO 0 as TREQ +// 0x01 -> Select PIO0's TX FIFO 1 as TREQ +// 0x02 -> Select PIO0's TX FIFO 2 as TREQ +// 0x03 -> Select PIO0's TX FIFO 3 as TREQ +// 0x04 -> Select PIO0's RX FIFO 0 as TREQ +// 0x05 -> Select PIO0's RX FIFO 1 as TREQ +// 0x06 -> Select PIO0's RX FIFO 2 as TREQ +// 0x07 -> Select PIO0's RX FIFO 3 as TREQ +// 0x08 -> Select PIO1's TX FIFO 0 as TREQ +// 0x09 -> Select PIO1's TX FIFO 1 as TREQ +// 0x0a -> Select PIO1's TX FIFO 2 as TREQ +// 0x0b -> Select PIO1's TX FIFO 3 as TREQ +// 0x0c -> Select PIO1's RX FIFO 0 as TREQ +// 0x0d -> Select PIO1's RX FIFO 1 as TREQ +// 0x0e -> Select PIO1's RX FIFO 2 as TREQ +// 0x0f -> Select PIO1's RX FIFO 3 as TREQ +// 0x10 -> Select PIO2's TX FIFO 0 as TREQ +// 0x11 -> Select PIO2's TX FIFO 1 as TREQ +// 0x12 -> Select PIO2's TX FIFO 2 as TREQ +// 0x13 -> Select PIO2's TX FIFO 3 as TREQ +// 0x14 -> Select PIO2's RX FIFO 0 as TREQ +// 0x15 -> Select PIO2's RX FIFO 1 as TREQ +// 0x16 -> Select PIO2's RX FIFO 2 as TREQ +// 0x17 -> Select PIO2's RX FIFO 3 as TREQ +// 0x18 -> Select SPI0's TX FIFO as TREQ +// 0x19 -> Select SPI0's RX FIFO as TREQ +// 0x1a -> Select SPI1's TX FIFO as TREQ +// 0x1b -> Select SPI1's RX FIFO as TREQ +// 0x1c -> Select UART0's TX FIFO as TREQ +// 0x1d -> Select UART0's RX FIFO as TREQ +// 0x1e -> Select UART1's TX FIFO as TREQ +// 0x1f -> Select UART1's RX FIFO as TREQ +// 0x20 -> Select PWM Counter 0's Wrap Value as TREQ +// 0x21 -> Select PWM Counter 1's Wrap Value as TREQ +// 0x22 -> Select PWM Counter 2's Wrap Value as TREQ +// 0x23 -> Select PWM Counter 3's Wrap Value as TREQ +// 0x24 -> Select PWM Counter 4's Wrap Value as TREQ +// 0x25 -> Select PWM Counter 5's Wrap Value as TREQ +// 0x26 -> Select PWM Counter 6's Wrap Value as TREQ +// 0x27 -> Select PWM Counter 7's Wrap Value as TREQ +// 0x28 -> Select PWM Counter 8's Wrap Value as TREQ +// 0x29 -> Select PWM Counter 9's Wrap Value as TREQ +// 0x2a -> Select PWM Counter 10's Wrap Value as TREQ +// 0x2b -> Select PWM Counter 11's Wrap Value as TREQ +// 0x2c -> Select I2C0's TX FIFO as TREQ +// 0x2d -> Select I2C0's RX FIFO as TREQ +// 0x2e -> Select I2C1's TX FIFO as TREQ +// 0x2f -> Select I2C1's RX FIFO as TREQ +// 0x30 -> Select the ADC as TREQ +// 0x31 -> Select the XIP Streaming FIFO as TREQ +// 0x32 -> Select XIP_QMITX as TREQ +// 0x33 -> Select XIP_QMIRX as TREQ +// 0x34 -> Select HSTX as TREQ +// 0x35 -> Select CORESIGHT as TREQ +// 0x36 -> Select SHA256 as TREQ #define DMA_CH4_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) #define DMA_CH4_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) #define DMA_CH4_CTRL_TRIG_TREQ_SEL_MSB _u(22) @@ -2027,6 +2522,61 @@ #define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) #define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX0 _u(0x00) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX1 _u(0x01) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX2 _u(0x02) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX3 _u(0x03) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX0 _u(0x04) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX1 _u(0x05) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX2 _u(0x06) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX3 _u(0x07) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX0 _u(0x08) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX1 _u(0x09) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX2 _u(0x0a) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX3 _u(0x0b) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX0 _u(0x0c) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX1 _u(0x0d) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX2 _u(0x0e) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX3 _u(0x0f) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX0 _u(0x10) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX1 _u(0x11) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX2 _u(0x12) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX3 _u(0x13) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX0 _u(0x14) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX1 _u(0x15) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX2 _u(0x16) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX3 _u(0x17) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_TX _u(0x18) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_RX _u(0x19) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_TX _u(0x1a) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_RX _u(0x1b) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_UART0_TX _u(0x1c) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_UART0_RX _u(0x1d) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_UART1_TX _u(0x1e) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_UART1_RX _u(0x1f) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP0 _u(0x20) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP1 _u(0x21) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP2 _u(0x22) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP3 _u(0x23) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP4 _u(0x24) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP5 _u(0x25) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP6 _u(0x26) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP7 _u(0x27) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP8 _u(0x28) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP9 _u(0x29) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP10 _u(0x2a) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP11 _u(0x2b) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_TX _u(0x2c) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_RX _u(0x2d) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_TX _u(0x2e) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_RX _u(0x2f) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_ADC _u(0x30) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_XIP_STREAM _u(0x31) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMITX _u(0x32) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMIRX _u(0x33) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_HSTX _u(0x34) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_CORESIGHT _u(0x35) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_SHA256 _u(0x36) // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel @@ -2470,6 +3020,61 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. +// 0x00 -> Select PIO0's TX FIFO 0 as TREQ +// 0x01 -> Select PIO0's TX FIFO 1 as TREQ +// 0x02 -> Select PIO0's TX FIFO 2 as TREQ +// 0x03 -> Select PIO0's TX FIFO 3 as TREQ +// 0x04 -> Select PIO0's RX FIFO 0 as TREQ +// 0x05 -> Select PIO0's RX FIFO 1 as TREQ +// 0x06 -> Select PIO0's RX FIFO 2 as TREQ +// 0x07 -> Select PIO0's RX FIFO 3 as TREQ +// 0x08 -> Select PIO1's TX FIFO 0 as TREQ +// 0x09 -> Select PIO1's TX FIFO 1 as TREQ +// 0x0a -> Select PIO1's TX FIFO 2 as TREQ +// 0x0b -> Select PIO1's TX FIFO 3 as TREQ +// 0x0c -> Select PIO1's RX FIFO 0 as TREQ +// 0x0d -> Select PIO1's RX FIFO 1 as TREQ +// 0x0e -> Select PIO1's RX FIFO 2 as TREQ +// 0x0f -> Select PIO1's RX FIFO 3 as TREQ +// 0x10 -> Select PIO2's TX FIFO 0 as TREQ +// 0x11 -> Select PIO2's TX FIFO 1 as TREQ +// 0x12 -> Select PIO2's TX FIFO 2 as TREQ +// 0x13 -> Select PIO2's TX FIFO 3 as TREQ +// 0x14 -> Select PIO2's RX FIFO 0 as TREQ +// 0x15 -> Select PIO2's RX FIFO 1 as TREQ +// 0x16 -> Select PIO2's RX FIFO 2 as TREQ +// 0x17 -> Select PIO2's RX FIFO 3 as TREQ +// 0x18 -> Select SPI0's TX FIFO as TREQ +// 0x19 -> Select SPI0's RX FIFO as TREQ +// 0x1a -> Select SPI1's TX FIFO as TREQ +// 0x1b -> Select SPI1's RX FIFO as TREQ +// 0x1c -> Select UART0's TX FIFO as TREQ +// 0x1d -> Select UART0's RX FIFO as TREQ +// 0x1e -> Select UART1's TX FIFO as TREQ +// 0x1f -> Select UART1's RX FIFO as TREQ +// 0x20 -> Select PWM Counter 0's Wrap Value as TREQ +// 0x21 -> Select PWM Counter 1's Wrap Value as TREQ +// 0x22 -> Select PWM Counter 2's Wrap Value as TREQ +// 0x23 -> Select PWM Counter 3's Wrap Value as TREQ +// 0x24 -> Select PWM Counter 4's Wrap Value as TREQ +// 0x25 -> Select PWM Counter 5's Wrap Value as TREQ +// 0x26 -> Select PWM Counter 6's Wrap Value as TREQ +// 0x27 -> Select PWM Counter 7's Wrap Value as TREQ +// 0x28 -> Select PWM Counter 8's Wrap Value as TREQ +// 0x29 -> Select PWM Counter 9's Wrap Value as TREQ +// 0x2a -> Select PWM Counter 10's Wrap Value as TREQ +// 0x2b -> Select PWM Counter 11's Wrap Value as TREQ +// 0x2c -> Select I2C0's TX FIFO as TREQ +// 0x2d -> Select I2C0's RX FIFO as TREQ +// 0x2e -> Select I2C1's TX FIFO as TREQ +// 0x2f -> Select I2C1's RX FIFO as TREQ +// 0x30 -> Select the ADC as TREQ +// 0x31 -> Select the XIP Streaming FIFO as TREQ +// 0x32 -> Select XIP_QMITX as TREQ +// 0x33 -> Select XIP_QMIRX as TREQ +// 0x34 -> Select HSTX as TREQ +// 0x35 -> Select CORESIGHT as TREQ +// 0x36 -> Select SHA256 as TREQ #define DMA_CH5_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) #define DMA_CH5_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) #define DMA_CH5_CTRL_TRIG_TREQ_SEL_MSB _u(22) @@ -2480,6 +3085,61 @@ #define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) #define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX0 _u(0x00) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX1 _u(0x01) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX2 _u(0x02) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX3 _u(0x03) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX0 _u(0x04) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX1 _u(0x05) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX2 _u(0x06) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX3 _u(0x07) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX0 _u(0x08) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX1 _u(0x09) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX2 _u(0x0a) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX3 _u(0x0b) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX0 _u(0x0c) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX1 _u(0x0d) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX2 _u(0x0e) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX3 _u(0x0f) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX0 _u(0x10) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX1 _u(0x11) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX2 _u(0x12) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX3 _u(0x13) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX0 _u(0x14) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX1 _u(0x15) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX2 _u(0x16) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX3 _u(0x17) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_TX _u(0x18) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_RX _u(0x19) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_TX _u(0x1a) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_RX _u(0x1b) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_UART0_TX _u(0x1c) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_UART0_RX _u(0x1d) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_UART1_TX _u(0x1e) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_UART1_RX _u(0x1f) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP0 _u(0x20) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP1 _u(0x21) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP2 _u(0x22) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP3 _u(0x23) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP4 _u(0x24) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP5 _u(0x25) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP6 _u(0x26) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP7 _u(0x27) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP8 _u(0x28) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP9 _u(0x29) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP10 _u(0x2a) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP11 _u(0x2b) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_TX _u(0x2c) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_RX _u(0x2d) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_TX _u(0x2e) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_RX _u(0x2f) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_ADC _u(0x30) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_XIP_STREAM _u(0x31) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMITX _u(0x32) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMIRX _u(0x33) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_HSTX _u(0x34) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_CORESIGHT _u(0x35) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_SHA256 _u(0x36) // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel @@ -2923,6 +3583,61 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. +// 0x00 -> Select PIO0's TX FIFO 0 as TREQ +// 0x01 -> Select PIO0's TX FIFO 1 as TREQ +// 0x02 -> Select PIO0's TX FIFO 2 as TREQ +// 0x03 -> Select PIO0's TX FIFO 3 as TREQ +// 0x04 -> Select PIO0's RX FIFO 0 as TREQ +// 0x05 -> Select PIO0's RX FIFO 1 as TREQ +// 0x06 -> Select PIO0's RX FIFO 2 as TREQ +// 0x07 -> Select PIO0's RX FIFO 3 as TREQ +// 0x08 -> Select PIO1's TX FIFO 0 as TREQ +// 0x09 -> Select PIO1's TX FIFO 1 as TREQ +// 0x0a -> Select PIO1's TX FIFO 2 as TREQ +// 0x0b -> Select PIO1's TX FIFO 3 as TREQ +// 0x0c -> Select PIO1's RX FIFO 0 as TREQ +// 0x0d -> Select PIO1's RX FIFO 1 as TREQ +// 0x0e -> Select PIO1's RX FIFO 2 as TREQ +// 0x0f -> Select PIO1's RX FIFO 3 as TREQ +// 0x10 -> Select PIO2's TX FIFO 0 as TREQ +// 0x11 -> Select PIO2's TX FIFO 1 as TREQ +// 0x12 -> Select PIO2's TX FIFO 2 as TREQ +// 0x13 -> Select PIO2's TX FIFO 3 as TREQ +// 0x14 -> Select PIO2's RX FIFO 0 as TREQ +// 0x15 -> Select PIO2's RX FIFO 1 as TREQ +// 0x16 -> Select PIO2's RX FIFO 2 as TREQ +// 0x17 -> Select PIO2's RX FIFO 3 as TREQ +// 0x18 -> Select SPI0's TX FIFO as TREQ +// 0x19 -> Select SPI0's RX FIFO as TREQ +// 0x1a -> Select SPI1's TX FIFO as TREQ +// 0x1b -> Select SPI1's RX FIFO as TREQ +// 0x1c -> Select UART0's TX FIFO as TREQ +// 0x1d -> Select UART0's RX FIFO as TREQ +// 0x1e -> Select UART1's TX FIFO as TREQ +// 0x1f -> Select UART1's RX FIFO as TREQ +// 0x20 -> Select PWM Counter 0's Wrap Value as TREQ +// 0x21 -> Select PWM Counter 1's Wrap Value as TREQ +// 0x22 -> Select PWM Counter 2's Wrap Value as TREQ +// 0x23 -> Select PWM Counter 3's Wrap Value as TREQ +// 0x24 -> Select PWM Counter 4's Wrap Value as TREQ +// 0x25 -> Select PWM Counter 5's Wrap Value as TREQ +// 0x26 -> Select PWM Counter 6's Wrap Value as TREQ +// 0x27 -> Select PWM Counter 7's Wrap Value as TREQ +// 0x28 -> Select PWM Counter 8's Wrap Value as TREQ +// 0x29 -> Select PWM Counter 9's Wrap Value as TREQ +// 0x2a -> Select PWM Counter 10's Wrap Value as TREQ +// 0x2b -> Select PWM Counter 11's Wrap Value as TREQ +// 0x2c -> Select I2C0's TX FIFO as TREQ +// 0x2d -> Select I2C0's RX FIFO as TREQ +// 0x2e -> Select I2C1's TX FIFO as TREQ +// 0x2f -> Select I2C1's RX FIFO as TREQ +// 0x30 -> Select the ADC as TREQ +// 0x31 -> Select the XIP Streaming FIFO as TREQ +// 0x32 -> Select XIP_QMITX as TREQ +// 0x33 -> Select XIP_QMIRX as TREQ +// 0x34 -> Select HSTX as TREQ +// 0x35 -> Select CORESIGHT as TREQ +// 0x36 -> Select SHA256 as TREQ #define DMA_CH6_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) #define DMA_CH6_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) #define DMA_CH6_CTRL_TRIG_TREQ_SEL_MSB _u(22) @@ -2933,6 +3648,61 @@ #define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) #define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX0 _u(0x00) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX1 _u(0x01) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX2 _u(0x02) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX3 _u(0x03) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX0 _u(0x04) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX1 _u(0x05) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX2 _u(0x06) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX3 _u(0x07) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX0 _u(0x08) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX1 _u(0x09) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX2 _u(0x0a) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX3 _u(0x0b) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX0 _u(0x0c) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX1 _u(0x0d) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX2 _u(0x0e) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX3 _u(0x0f) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX0 _u(0x10) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX1 _u(0x11) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX2 _u(0x12) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX3 _u(0x13) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX0 _u(0x14) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX1 _u(0x15) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX2 _u(0x16) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX3 _u(0x17) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_TX _u(0x18) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_RX _u(0x19) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_TX _u(0x1a) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_RX _u(0x1b) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_UART0_TX _u(0x1c) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_UART0_RX _u(0x1d) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_UART1_TX _u(0x1e) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_UART1_RX _u(0x1f) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP0 _u(0x20) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP1 _u(0x21) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP2 _u(0x22) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP3 _u(0x23) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP4 _u(0x24) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP5 _u(0x25) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP6 _u(0x26) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP7 _u(0x27) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP8 _u(0x28) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP9 _u(0x29) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP10 _u(0x2a) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP11 _u(0x2b) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_TX _u(0x2c) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_RX _u(0x2d) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_TX _u(0x2e) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_RX _u(0x2f) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_ADC _u(0x30) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_XIP_STREAM _u(0x31) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMITX _u(0x32) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMIRX _u(0x33) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_HSTX _u(0x34) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_CORESIGHT _u(0x35) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_SHA256 _u(0x36) // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel @@ -3376,6 +4146,61 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. +// 0x00 -> Select PIO0's TX FIFO 0 as TREQ +// 0x01 -> Select PIO0's TX FIFO 1 as TREQ +// 0x02 -> Select PIO0's TX FIFO 2 as TREQ +// 0x03 -> Select PIO0's TX FIFO 3 as TREQ +// 0x04 -> Select PIO0's RX FIFO 0 as TREQ +// 0x05 -> Select PIO0's RX FIFO 1 as TREQ +// 0x06 -> Select PIO0's RX FIFO 2 as TREQ +// 0x07 -> Select PIO0's RX FIFO 3 as TREQ +// 0x08 -> Select PIO1's TX FIFO 0 as TREQ +// 0x09 -> Select PIO1's TX FIFO 1 as TREQ +// 0x0a -> Select PIO1's TX FIFO 2 as TREQ +// 0x0b -> Select PIO1's TX FIFO 3 as TREQ +// 0x0c -> Select PIO1's RX FIFO 0 as TREQ +// 0x0d -> Select PIO1's RX FIFO 1 as TREQ +// 0x0e -> Select PIO1's RX FIFO 2 as TREQ +// 0x0f -> Select PIO1's RX FIFO 3 as TREQ +// 0x10 -> Select PIO2's TX FIFO 0 as TREQ +// 0x11 -> Select PIO2's TX FIFO 1 as TREQ +// 0x12 -> Select PIO2's TX FIFO 2 as TREQ +// 0x13 -> Select PIO2's TX FIFO 3 as TREQ +// 0x14 -> Select PIO2's RX FIFO 0 as TREQ +// 0x15 -> Select PIO2's RX FIFO 1 as TREQ +// 0x16 -> Select PIO2's RX FIFO 2 as TREQ +// 0x17 -> Select PIO2's RX FIFO 3 as TREQ +// 0x18 -> Select SPI0's TX FIFO as TREQ +// 0x19 -> Select SPI0's RX FIFO as TREQ +// 0x1a -> Select SPI1's TX FIFO as TREQ +// 0x1b -> Select SPI1's RX FIFO as TREQ +// 0x1c -> Select UART0's TX FIFO as TREQ +// 0x1d -> Select UART0's RX FIFO as TREQ +// 0x1e -> Select UART1's TX FIFO as TREQ +// 0x1f -> Select UART1's RX FIFO as TREQ +// 0x20 -> Select PWM Counter 0's Wrap Value as TREQ +// 0x21 -> Select PWM Counter 1's Wrap Value as TREQ +// 0x22 -> Select PWM Counter 2's Wrap Value as TREQ +// 0x23 -> Select PWM Counter 3's Wrap Value as TREQ +// 0x24 -> Select PWM Counter 4's Wrap Value as TREQ +// 0x25 -> Select PWM Counter 5's Wrap Value as TREQ +// 0x26 -> Select PWM Counter 6's Wrap Value as TREQ +// 0x27 -> Select PWM Counter 7's Wrap Value as TREQ +// 0x28 -> Select PWM Counter 8's Wrap Value as TREQ +// 0x29 -> Select PWM Counter 9's Wrap Value as TREQ +// 0x2a -> Select PWM Counter 10's Wrap Value as TREQ +// 0x2b -> Select PWM Counter 11's Wrap Value as TREQ +// 0x2c -> Select I2C0's TX FIFO as TREQ +// 0x2d -> Select I2C0's RX FIFO as TREQ +// 0x2e -> Select I2C1's TX FIFO as TREQ +// 0x2f -> Select I2C1's RX FIFO as TREQ +// 0x30 -> Select the ADC as TREQ +// 0x31 -> Select the XIP Streaming FIFO as TREQ +// 0x32 -> Select XIP_QMITX as TREQ +// 0x33 -> Select XIP_QMIRX as TREQ +// 0x34 -> Select HSTX as TREQ +// 0x35 -> Select CORESIGHT as TREQ +// 0x36 -> Select SHA256 as TREQ #define DMA_CH7_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) #define DMA_CH7_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) #define DMA_CH7_CTRL_TRIG_TREQ_SEL_MSB _u(22) @@ -3386,6 +4211,61 @@ #define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) #define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX0 _u(0x00) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX1 _u(0x01) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX2 _u(0x02) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX3 _u(0x03) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX0 _u(0x04) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX1 _u(0x05) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX2 _u(0x06) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX3 _u(0x07) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX0 _u(0x08) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX1 _u(0x09) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX2 _u(0x0a) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX3 _u(0x0b) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX0 _u(0x0c) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX1 _u(0x0d) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX2 _u(0x0e) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX3 _u(0x0f) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX0 _u(0x10) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX1 _u(0x11) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX2 _u(0x12) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX3 _u(0x13) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX0 _u(0x14) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX1 _u(0x15) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX2 _u(0x16) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX3 _u(0x17) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_TX _u(0x18) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_RX _u(0x19) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_TX _u(0x1a) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_RX _u(0x1b) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_UART0_TX _u(0x1c) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_UART0_RX _u(0x1d) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_UART1_TX _u(0x1e) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_UART1_RX _u(0x1f) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP0 _u(0x20) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP1 _u(0x21) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP2 _u(0x22) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP3 _u(0x23) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP4 _u(0x24) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP5 _u(0x25) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP6 _u(0x26) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP7 _u(0x27) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP8 _u(0x28) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP9 _u(0x29) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP10 _u(0x2a) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP11 _u(0x2b) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_TX _u(0x2c) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_RX _u(0x2d) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_TX _u(0x2e) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_RX _u(0x2f) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_ADC _u(0x30) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_XIP_STREAM _u(0x31) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMITX _u(0x32) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMIRX _u(0x33) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_HSTX _u(0x34) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_CORESIGHT _u(0x35) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_SHA256 _u(0x36) // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel @@ -3829,6 +4709,61 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. +// 0x00 -> Select PIO0's TX FIFO 0 as TREQ +// 0x01 -> Select PIO0's TX FIFO 1 as TREQ +// 0x02 -> Select PIO0's TX FIFO 2 as TREQ +// 0x03 -> Select PIO0's TX FIFO 3 as TREQ +// 0x04 -> Select PIO0's RX FIFO 0 as TREQ +// 0x05 -> Select PIO0's RX FIFO 1 as TREQ +// 0x06 -> Select PIO0's RX FIFO 2 as TREQ +// 0x07 -> Select PIO0's RX FIFO 3 as TREQ +// 0x08 -> Select PIO1's TX FIFO 0 as TREQ +// 0x09 -> Select PIO1's TX FIFO 1 as TREQ +// 0x0a -> Select PIO1's TX FIFO 2 as TREQ +// 0x0b -> Select PIO1's TX FIFO 3 as TREQ +// 0x0c -> Select PIO1's RX FIFO 0 as TREQ +// 0x0d -> Select PIO1's RX FIFO 1 as TREQ +// 0x0e -> Select PIO1's RX FIFO 2 as TREQ +// 0x0f -> Select PIO1's RX FIFO 3 as TREQ +// 0x10 -> Select PIO2's TX FIFO 0 as TREQ +// 0x11 -> Select PIO2's TX FIFO 1 as TREQ +// 0x12 -> Select PIO2's TX FIFO 2 as TREQ +// 0x13 -> Select PIO2's TX FIFO 3 as TREQ +// 0x14 -> Select PIO2's RX FIFO 0 as TREQ +// 0x15 -> Select PIO2's RX FIFO 1 as TREQ +// 0x16 -> Select PIO2's RX FIFO 2 as TREQ +// 0x17 -> Select PIO2's RX FIFO 3 as TREQ +// 0x18 -> Select SPI0's TX FIFO as TREQ +// 0x19 -> Select SPI0's RX FIFO as TREQ +// 0x1a -> Select SPI1's TX FIFO as TREQ +// 0x1b -> Select SPI1's RX FIFO as TREQ +// 0x1c -> Select UART0's TX FIFO as TREQ +// 0x1d -> Select UART0's RX FIFO as TREQ +// 0x1e -> Select UART1's TX FIFO as TREQ +// 0x1f -> Select UART1's RX FIFO as TREQ +// 0x20 -> Select PWM Counter 0's Wrap Value as TREQ +// 0x21 -> Select PWM Counter 1's Wrap Value as TREQ +// 0x22 -> Select PWM Counter 2's Wrap Value as TREQ +// 0x23 -> Select PWM Counter 3's Wrap Value as TREQ +// 0x24 -> Select PWM Counter 4's Wrap Value as TREQ +// 0x25 -> Select PWM Counter 5's Wrap Value as TREQ +// 0x26 -> Select PWM Counter 6's Wrap Value as TREQ +// 0x27 -> Select PWM Counter 7's Wrap Value as TREQ +// 0x28 -> Select PWM Counter 8's Wrap Value as TREQ +// 0x29 -> Select PWM Counter 9's Wrap Value as TREQ +// 0x2a -> Select PWM Counter 10's Wrap Value as TREQ +// 0x2b -> Select PWM Counter 11's Wrap Value as TREQ +// 0x2c -> Select I2C0's TX FIFO as TREQ +// 0x2d -> Select I2C0's RX FIFO as TREQ +// 0x2e -> Select I2C1's TX FIFO as TREQ +// 0x2f -> Select I2C1's RX FIFO as TREQ +// 0x30 -> Select the ADC as TREQ +// 0x31 -> Select the XIP Streaming FIFO as TREQ +// 0x32 -> Select XIP_QMITX as TREQ +// 0x33 -> Select XIP_QMIRX as TREQ +// 0x34 -> Select HSTX as TREQ +// 0x35 -> Select CORESIGHT as TREQ +// 0x36 -> Select SHA256 as TREQ #define DMA_CH8_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) #define DMA_CH8_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) #define DMA_CH8_CTRL_TRIG_TREQ_SEL_MSB _u(22) @@ -3839,6 +4774,61 @@ #define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) #define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX0 _u(0x00) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX1 _u(0x01) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX2 _u(0x02) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX3 _u(0x03) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX0 _u(0x04) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX1 _u(0x05) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX2 _u(0x06) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX3 _u(0x07) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX0 _u(0x08) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX1 _u(0x09) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX2 _u(0x0a) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX3 _u(0x0b) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX0 _u(0x0c) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX1 _u(0x0d) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX2 _u(0x0e) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX3 _u(0x0f) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX0 _u(0x10) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX1 _u(0x11) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX2 _u(0x12) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX3 _u(0x13) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX0 _u(0x14) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX1 _u(0x15) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX2 _u(0x16) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX3 _u(0x17) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_TX _u(0x18) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_RX _u(0x19) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_TX _u(0x1a) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_RX _u(0x1b) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_UART0_TX _u(0x1c) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_UART0_RX _u(0x1d) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_UART1_TX _u(0x1e) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_UART1_RX _u(0x1f) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP0 _u(0x20) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP1 _u(0x21) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP2 _u(0x22) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP3 _u(0x23) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP4 _u(0x24) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP5 _u(0x25) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP6 _u(0x26) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP7 _u(0x27) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP8 _u(0x28) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP9 _u(0x29) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP10 _u(0x2a) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP11 _u(0x2b) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_TX _u(0x2c) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_RX _u(0x2d) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_TX _u(0x2e) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_RX _u(0x2f) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_ADC _u(0x30) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_XIP_STREAM _u(0x31) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMITX _u(0x32) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMIRX _u(0x33) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_HSTX _u(0x34) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_CORESIGHT _u(0x35) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_SHA256 _u(0x36) // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel @@ -4282,6 +5272,61 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. +// 0x00 -> Select PIO0's TX FIFO 0 as TREQ +// 0x01 -> Select PIO0's TX FIFO 1 as TREQ +// 0x02 -> Select PIO0's TX FIFO 2 as TREQ +// 0x03 -> Select PIO0's TX FIFO 3 as TREQ +// 0x04 -> Select PIO0's RX FIFO 0 as TREQ +// 0x05 -> Select PIO0's RX FIFO 1 as TREQ +// 0x06 -> Select PIO0's RX FIFO 2 as TREQ +// 0x07 -> Select PIO0's RX FIFO 3 as TREQ +// 0x08 -> Select PIO1's TX FIFO 0 as TREQ +// 0x09 -> Select PIO1's TX FIFO 1 as TREQ +// 0x0a -> Select PIO1's TX FIFO 2 as TREQ +// 0x0b -> Select PIO1's TX FIFO 3 as TREQ +// 0x0c -> Select PIO1's RX FIFO 0 as TREQ +// 0x0d -> Select PIO1's RX FIFO 1 as TREQ +// 0x0e -> Select PIO1's RX FIFO 2 as TREQ +// 0x0f -> Select PIO1's RX FIFO 3 as TREQ +// 0x10 -> Select PIO2's TX FIFO 0 as TREQ +// 0x11 -> Select PIO2's TX FIFO 1 as TREQ +// 0x12 -> Select PIO2's TX FIFO 2 as TREQ +// 0x13 -> Select PIO2's TX FIFO 3 as TREQ +// 0x14 -> Select PIO2's RX FIFO 0 as TREQ +// 0x15 -> Select PIO2's RX FIFO 1 as TREQ +// 0x16 -> Select PIO2's RX FIFO 2 as TREQ +// 0x17 -> Select PIO2's RX FIFO 3 as TREQ +// 0x18 -> Select SPI0's TX FIFO as TREQ +// 0x19 -> Select SPI0's RX FIFO as TREQ +// 0x1a -> Select SPI1's TX FIFO as TREQ +// 0x1b -> Select SPI1's RX FIFO as TREQ +// 0x1c -> Select UART0's TX FIFO as TREQ +// 0x1d -> Select UART0's RX FIFO as TREQ +// 0x1e -> Select UART1's TX FIFO as TREQ +// 0x1f -> Select UART1's RX FIFO as TREQ +// 0x20 -> Select PWM Counter 0's Wrap Value as TREQ +// 0x21 -> Select PWM Counter 1's Wrap Value as TREQ +// 0x22 -> Select PWM Counter 2's Wrap Value as TREQ +// 0x23 -> Select PWM Counter 3's Wrap Value as TREQ +// 0x24 -> Select PWM Counter 4's Wrap Value as TREQ +// 0x25 -> Select PWM Counter 5's Wrap Value as TREQ +// 0x26 -> Select PWM Counter 6's Wrap Value as TREQ +// 0x27 -> Select PWM Counter 7's Wrap Value as TREQ +// 0x28 -> Select PWM Counter 8's Wrap Value as TREQ +// 0x29 -> Select PWM Counter 9's Wrap Value as TREQ +// 0x2a -> Select PWM Counter 10's Wrap Value as TREQ +// 0x2b -> Select PWM Counter 11's Wrap Value as TREQ +// 0x2c -> Select I2C0's TX FIFO as TREQ +// 0x2d -> Select I2C0's RX FIFO as TREQ +// 0x2e -> Select I2C1's TX FIFO as TREQ +// 0x2f -> Select I2C1's RX FIFO as TREQ +// 0x30 -> Select the ADC as TREQ +// 0x31 -> Select the XIP Streaming FIFO as TREQ +// 0x32 -> Select XIP_QMITX as TREQ +// 0x33 -> Select XIP_QMIRX as TREQ +// 0x34 -> Select HSTX as TREQ +// 0x35 -> Select CORESIGHT as TREQ +// 0x36 -> Select SHA256 as TREQ #define DMA_CH9_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) #define DMA_CH9_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) #define DMA_CH9_CTRL_TRIG_TREQ_SEL_MSB _u(22) @@ -4292,6 +5337,61 @@ #define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) #define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX0 _u(0x00) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX1 _u(0x01) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX2 _u(0x02) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX3 _u(0x03) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX0 _u(0x04) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX1 _u(0x05) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX2 _u(0x06) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX3 _u(0x07) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX0 _u(0x08) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX1 _u(0x09) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX2 _u(0x0a) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX3 _u(0x0b) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX0 _u(0x0c) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX1 _u(0x0d) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX2 _u(0x0e) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX3 _u(0x0f) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX0 _u(0x10) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX1 _u(0x11) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX2 _u(0x12) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX3 _u(0x13) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX0 _u(0x14) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX1 _u(0x15) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX2 _u(0x16) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX3 _u(0x17) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_TX _u(0x18) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_RX _u(0x19) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_TX _u(0x1a) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_RX _u(0x1b) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_UART0_TX _u(0x1c) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_UART0_RX _u(0x1d) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_UART1_TX _u(0x1e) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_UART1_RX _u(0x1f) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP0 _u(0x20) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP1 _u(0x21) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP2 _u(0x22) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP3 _u(0x23) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP4 _u(0x24) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP5 _u(0x25) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP6 _u(0x26) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP7 _u(0x27) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP8 _u(0x28) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP9 _u(0x29) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP10 _u(0x2a) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP11 _u(0x2b) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_TX _u(0x2c) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_RX _u(0x2d) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_TX _u(0x2e) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_RX _u(0x2f) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_ADC _u(0x30) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_XIP_STREAM _u(0x31) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMITX _u(0x32) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMIRX _u(0x33) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_HSTX _u(0x34) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_CORESIGHT _u(0x35) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_SHA256 _u(0x36) // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel @@ -4735,6 +5835,61 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. +// 0x00 -> Select PIO0's TX FIFO 0 as TREQ +// 0x01 -> Select PIO0's TX FIFO 1 as TREQ +// 0x02 -> Select PIO0's TX FIFO 2 as TREQ +// 0x03 -> Select PIO0's TX FIFO 3 as TREQ +// 0x04 -> Select PIO0's RX FIFO 0 as TREQ +// 0x05 -> Select PIO0's RX FIFO 1 as TREQ +// 0x06 -> Select PIO0's RX FIFO 2 as TREQ +// 0x07 -> Select PIO0's RX FIFO 3 as TREQ +// 0x08 -> Select PIO1's TX FIFO 0 as TREQ +// 0x09 -> Select PIO1's TX FIFO 1 as TREQ +// 0x0a -> Select PIO1's TX FIFO 2 as TREQ +// 0x0b -> Select PIO1's TX FIFO 3 as TREQ +// 0x0c -> Select PIO1's RX FIFO 0 as TREQ +// 0x0d -> Select PIO1's RX FIFO 1 as TREQ +// 0x0e -> Select PIO1's RX FIFO 2 as TREQ +// 0x0f -> Select PIO1's RX FIFO 3 as TREQ +// 0x10 -> Select PIO2's TX FIFO 0 as TREQ +// 0x11 -> Select PIO2's TX FIFO 1 as TREQ +// 0x12 -> Select PIO2's TX FIFO 2 as TREQ +// 0x13 -> Select PIO2's TX FIFO 3 as TREQ +// 0x14 -> Select PIO2's RX FIFO 0 as TREQ +// 0x15 -> Select PIO2's RX FIFO 1 as TREQ +// 0x16 -> Select PIO2's RX FIFO 2 as TREQ +// 0x17 -> Select PIO2's RX FIFO 3 as TREQ +// 0x18 -> Select SPI0's TX FIFO as TREQ +// 0x19 -> Select SPI0's RX FIFO as TREQ +// 0x1a -> Select SPI1's TX FIFO as TREQ +// 0x1b -> Select SPI1's RX FIFO as TREQ +// 0x1c -> Select UART0's TX FIFO as TREQ +// 0x1d -> Select UART0's RX FIFO as TREQ +// 0x1e -> Select UART1's TX FIFO as TREQ +// 0x1f -> Select UART1's RX FIFO as TREQ +// 0x20 -> Select PWM Counter 0's Wrap Value as TREQ +// 0x21 -> Select PWM Counter 1's Wrap Value as TREQ +// 0x22 -> Select PWM Counter 2's Wrap Value as TREQ +// 0x23 -> Select PWM Counter 3's Wrap Value as TREQ +// 0x24 -> Select PWM Counter 4's Wrap Value as TREQ +// 0x25 -> Select PWM Counter 5's Wrap Value as TREQ +// 0x26 -> Select PWM Counter 6's Wrap Value as TREQ +// 0x27 -> Select PWM Counter 7's Wrap Value as TREQ +// 0x28 -> Select PWM Counter 8's Wrap Value as TREQ +// 0x29 -> Select PWM Counter 9's Wrap Value as TREQ +// 0x2a -> Select PWM Counter 10's Wrap Value as TREQ +// 0x2b -> Select PWM Counter 11's Wrap Value as TREQ +// 0x2c -> Select I2C0's TX FIFO as TREQ +// 0x2d -> Select I2C0's RX FIFO as TREQ +// 0x2e -> Select I2C1's TX FIFO as TREQ +// 0x2f -> Select I2C1's RX FIFO as TREQ +// 0x30 -> Select the ADC as TREQ +// 0x31 -> Select the XIP Streaming FIFO as TREQ +// 0x32 -> Select XIP_QMITX as TREQ +// 0x33 -> Select XIP_QMIRX as TREQ +// 0x34 -> Select HSTX as TREQ +// 0x35 -> Select CORESIGHT as TREQ +// 0x36 -> Select SHA256 as TREQ #define DMA_CH10_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) #define DMA_CH10_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) #define DMA_CH10_CTRL_TRIG_TREQ_SEL_MSB _u(22) @@ -4745,6 +5900,61 @@ #define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) #define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX0 _u(0x00) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX1 _u(0x01) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX2 _u(0x02) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX3 _u(0x03) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX0 _u(0x04) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX1 _u(0x05) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX2 _u(0x06) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX3 _u(0x07) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX0 _u(0x08) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX1 _u(0x09) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX2 _u(0x0a) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX3 _u(0x0b) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX0 _u(0x0c) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX1 _u(0x0d) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX2 _u(0x0e) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX3 _u(0x0f) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX0 _u(0x10) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX1 _u(0x11) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX2 _u(0x12) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX3 _u(0x13) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX0 _u(0x14) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX1 _u(0x15) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX2 _u(0x16) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX3 _u(0x17) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_TX _u(0x18) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_RX _u(0x19) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_TX _u(0x1a) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_RX _u(0x1b) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_UART0_TX _u(0x1c) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_UART0_RX _u(0x1d) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_UART1_TX _u(0x1e) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_UART1_RX _u(0x1f) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP0 _u(0x20) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP1 _u(0x21) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP2 _u(0x22) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP3 _u(0x23) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP4 _u(0x24) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP5 _u(0x25) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP6 _u(0x26) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP7 _u(0x27) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP8 _u(0x28) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP9 _u(0x29) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP10 _u(0x2a) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP11 _u(0x2b) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_TX _u(0x2c) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_RX _u(0x2d) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_TX _u(0x2e) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_RX _u(0x2f) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_ADC _u(0x30) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_XIP_STREAM _u(0x31) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMITX _u(0x32) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMIRX _u(0x33) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_HSTX _u(0x34) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_CORESIGHT _u(0x35) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_SHA256 _u(0x36) // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel @@ -5188,6 +6398,61 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. +// 0x00 -> Select PIO0's TX FIFO 0 as TREQ +// 0x01 -> Select PIO0's TX FIFO 1 as TREQ +// 0x02 -> Select PIO0's TX FIFO 2 as TREQ +// 0x03 -> Select PIO0's TX FIFO 3 as TREQ +// 0x04 -> Select PIO0's RX FIFO 0 as TREQ +// 0x05 -> Select PIO0's RX FIFO 1 as TREQ +// 0x06 -> Select PIO0's RX FIFO 2 as TREQ +// 0x07 -> Select PIO0's RX FIFO 3 as TREQ +// 0x08 -> Select PIO1's TX FIFO 0 as TREQ +// 0x09 -> Select PIO1's TX FIFO 1 as TREQ +// 0x0a -> Select PIO1's TX FIFO 2 as TREQ +// 0x0b -> Select PIO1's TX FIFO 3 as TREQ +// 0x0c -> Select PIO1's RX FIFO 0 as TREQ +// 0x0d -> Select PIO1's RX FIFO 1 as TREQ +// 0x0e -> Select PIO1's RX FIFO 2 as TREQ +// 0x0f -> Select PIO1's RX FIFO 3 as TREQ +// 0x10 -> Select PIO2's TX FIFO 0 as TREQ +// 0x11 -> Select PIO2's TX FIFO 1 as TREQ +// 0x12 -> Select PIO2's TX FIFO 2 as TREQ +// 0x13 -> Select PIO2's TX FIFO 3 as TREQ +// 0x14 -> Select PIO2's RX FIFO 0 as TREQ +// 0x15 -> Select PIO2's RX FIFO 1 as TREQ +// 0x16 -> Select PIO2's RX FIFO 2 as TREQ +// 0x17 -> Select PIO2's RX FIFO 3 as TREQ +// 0x18 -> Select SPI0's TX FIFO as TREQ +// 0x19 -> Select SPI0's RX FIFO as TREQ +// 0x1a -> Select SPI1's TX FIFO as TREQ +// 0x1b -> Select SPI1's RX FIFO as TREQ +// 0x1c -> Select UART0's TX FIFO as TREQ +// 0x1d -> Select UART0's RX FIFO as TREQ +// 0x1e -> Select UART1's TX FIFO as TREQ +// 0x1f -> Select UART1's RX FIFO as TREQ +// 0x20 -> Select PWM Counter 0's Wrap Value as TREQ +// 0x21 -> Select PWM Counter 1's Wrap Value as TREQ +// 0x22 -> Select PWM Counter 2's Wrap Value as TREQ +// 0x23 -> Select PWM Counter 3's Wrap Value as TREQ +// 0x24 -> Select PWM Counter 4's Wrap Value as TREQ +// 0x25 -> Select PWM Counter 5's Wrap Value as TREQ +// 0x26 -> Select PWM Counter 6's Wrap Value as TREQ +// 0x27 -> Select PWM Counter 7's Wrap Value as TREQ +// 0x28 -> Select PWM Counter 8's Wrap Value as TREQ +// 0x29 -> Select PWM Counter 9's Wrap Value as TREQ +// 0x2a -> Select PWM Counter 10's Wrap Value as TREQ +// 0x2b -> Select PWM Counter 11's Wrap Value as TREQ +// 0x2c -> Select I2C0's TX FIFO as TREQ +// 0x2d -> Select I2C0's RX FIFO as TREQ +// 0x2e -> Select I2C1's TX FIFO as TREQ +// 0x2f -> Select I2C1's RX FIFO as TREQ +// 0x30 -> Select the ADC as TREQ +// 0x31 -> Select the XIP Streaming FIFO as TREQ +// 0x32 -> Select XIP_QMITX as TREQ +// 0x33 -> Select XIP_QMIRX as TREQ +// 0x34 -> Select HSTX as TREQ +// 0x35 -> Select CORESIGHT as TREQ +// 0x36 -> Select SHA256 as TREQ #define DMA_CH11_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) #define DMA_CH11_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) #define DMA_CH11_CTRL_TRIG_TREQ_SEL_MSB _u(22) @@ -5198,6 +6463,61 @@ #define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) #define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX0 _u(0x00) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX1 _u(0x01) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX2 _u(0x02) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX3 _u(0x03) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX0 _u(0x04) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX1 _u(0x05) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX2 _u(0x06) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX3 _u(0x07) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX0 _u(0x08) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX1 _u(0x09) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX2 _u(0x0a) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX3 _u(0x0b) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX0 _u(0x0c) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX1 _u(0x0d) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX2 _u(0x0e) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX3 _u(0x0f) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX0 _u(0x10) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX1 _u(0x11) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX2 _u(0x12) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX3 _u(0x13) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX0 _u(0x14) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX1 _u(0x15) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX2 _u(0x16) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX3 _u(0x17) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_TX _u(0x18) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_RX _u(0x19) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_TX _u(0x1a) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_RX _u(0x1b) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_UART0_TX _u(0x1c) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_UART0_RX _u(0x1d) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_UART1_TX _u(0x1e) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_UART1_RX _u(0x1f) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP0 _u(0x20) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP1 _u(0x21) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP2 _u(0x22) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP3 _u(0x23) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP4 _u(0x24) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP5 _u(0x25) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP6 _u(0x26) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP7 _u(0x27) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP8 _u(0x28) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP9 _u(0x29) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP10 _u(0x2a) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP11 _u(0x2b) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_TX _u(0x2c) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_RX _u(0x2d) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_TX _u(0x2e) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_RX _u(0x2f) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_ADC _u(0x30) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_XIP_STREAM _u(0x31) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMITX _u(0x32) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMIRX _u(0x33) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_HSTX _u(0x34) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_CORESIGHT _u(0x35) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_SHA256 _u(0x36) // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel @@ -5641,6 +6961,61 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. +// 0x00 -> Select PIO0's TX FIFO 0 as TREQ +// 0x01 -> Select PIO0's TX FIFO 1 as TREQ +// 0x02 -> Select PIO0's TX FIFO 2 as TREQ +// 0x03 -> Select PIO0's TX FIFO 3 as TREQ +// 0x04 -> Select PIO0's RX FIFO 0 as TREQ +// 0x05 -> Select PIO0's RX FIFO 1 as TREQ +// 0x06 -> Select PIO0's RX FIFO 2 as TREQ +// 0x07 -> Select PIO0's RX FIFO 3 as TREQ +// 0x08 -> Select PIO1's TX FIFO 0 as TREQ +// 0x09 -> Select PIO1's TX FIFO 1 as TREQ +// 0x0a -> Select PIO1's TX FIFO 2 as TREQ +// 0x0b -> Select PIO1's TX FIFO 3 as TREQ +// 0x0c -> Select PIO1's RX FIFO 0 as TREQ +// 0x0d -> Select PIO1's RX FIFO 1 as TREQ +// 0x0e -> Select PIO1's RX FIFO 2 as TREQ +// 0x0f -> Select PIO1's RX FIFO 3 as TREQ +// 0x10 -> Select PIO2's TX FIFO 0 as TREQ +// 0x11 -> Select PIO2's TX FIFO 1 as TREQ +// 0x12 -> Select PIO2's TX FIFO 2 as TREQ +// 0x13 -> Select PIO2's TX FIFO 3 as TREQ +// 0x14 -> Select PIO2's RX FIFO 0 as TREQ +// 0x15 -> Select PIO2's RX FIFO 1 as TREQ +// 0x16 -> Select PIO2's RX FIFO 2 as TREQ +// 0x17 -> Select PIO2's RX FIFO 3 as TREQ +// 0x18 -> Select SPI0's TX FIFO as TREQ +// 0x19 -> Select SPI0's RX FIFO as TREQ +// 0x1a -> Select SPI1's TX FIFO as TREQ +// 0x1b -> Select SPI1's RX FIFO as TREQ +// 0x1c -> Select UART0's TX FIFO as TREQ +// 0x1d -> Select UART0's RX FIFO as TREQ +// 0x1e -> Select UART1's TX FIFO as TREQ +// 0x1f -> Select UART1's RX FIFO as TREQ +// 0x20 -> Select PWM Counter 0's Wrap Value as TREQ +// 0x21 -> Select PWM Counter 1's Wrap Value as TREQ +// 0x22 -> Select PWM Counter 2's Wrap Value as TREQ +// 0x23 -> Select PWM Counter 3's Wrap Value as TREQ +// 0x24 -> Select PWM Counter 4's Wrap Value as TREQ +// 0x25 -> Select PWM Counter 5's Wrap Value as TREQ +// 0x26 -> Select PWM Counter 6's Wrap Value as TREQ +// 0x27 -> Select PWM Counter 7's Wrap Value as TREQ +// 0x28 -> Select PWM Counter 8's Wrap Value as TREQ +// 0x29 -> Select PWM Counter 9's Wrap Value as TREQ +// 0x2a -> Select PWM Counter 10's Wrap Value as TREQ +// 0x2b -> Select PWM Counter 11's Wrap Value as TREQ +// 0x2c -> Select I2C0's TX FIFO as TREQ +// 0x2d -> Select I2C0's RX FIFO as TREQ +// 0x2e -> Select I2C1's TX FIFO as TREQ +// 0x2f -> Select I2C1's RX FIFO as TREQ +// 0x30 -> Select the ADC as TREQ +// 0x31 -> Select the XIP Streaming FIFO as TREQ +// 0x32 -> Select XIP_QMITX as TREQ +// 0x33 -> Select XIP_QMIRX as TREQ +// 0x34 -> Select HSTX as TREQ +// 0x35 -> Select CORESIGHT as TREQ +// 0x36 -> Select SHA256 as TREQ #define DMA_CH12_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) #define DMA_CH12_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) #define DMA_CH12_CTRL_TRIG_TREQ_SEL_MSB _u(22) @@ -5651,6 +7026,61 @@ #define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) #define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX0 _u(0x00) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX1 _u(0x01) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX2 _u(0x02) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX3 _u(0x03) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX0 _u(0x04) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX1 _u(0x05) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX2 _u(0x06) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX3 _u(0x07) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX0 _u(0x08) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX1 _u(0x09) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX2 _u(0x0a) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX3 _u(0x0b) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX0 _u(0x0c) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX1 _u(0x0d) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX2 _u(0x0e) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX3 _u(0x0f) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX0 _u(0x10) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX1 _u(0x11) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX2 _u(0x12) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX3 _u(0x13) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX0 _u(0x14) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX1 _u(0x15) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX2 _u(0x16) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX3 _u(0x17) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_TX _u(0x18) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_RX _u(0x19) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_TX _u(0x1a) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_RX _u(0x1b) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_UART0_TX _u(0x1c) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_UART0_RX _u(0x1d) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_UART1_TX _u(0x1e) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_UART1_RX _u(0x1f) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP0 _u(0x20) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP1 _u(0x21) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP2 _u(0x22) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP3 _u(0x23) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP4 _u(0x24) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP5 _u(0x25) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP6 _u(0x26) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP7 _u(0x27) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP8 _u(0x28) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP9 _u(0x29) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP10 _u(0x2a) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP11 _u(0x2b) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_TX _u(0x2c) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_RX _u(0x2d) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_TX _u(0x2e) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_RX _u(0x2f) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_ADC _u(0x30) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_XIP_STREAM _u(0x31) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMITX _u(0x32) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMIRX _u(0x33) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_HSTX _u(0x34) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_CORESIGHT _u(0x35) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_SHA256 _u(0x36) // ----------------------------------------------------------------------------- // Field : DMA_CH12_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel @@ -6094,6 +7524,61 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. +// 0x00 -> Select PIO0's TX FIFO 0 as TREQ +// 0x01 -> Select PIO0's TX FIFO 1 as TREQ +// 0x02 -> Select PIO0's TX FIFO 2 as TREQ +// 0x03 -> Select PIO0's TX FIFO 3 as TREQ +// 0x04 -> Select PIO0's RX FIFO 0 as TREQ +// 0x05 -> Select PIO0's RX FIFO 1 as TREQ +// 0x06 -> Select PIO0's RX FIFO 2 as TREQ +// 0x07 -> Select PIO0's RX FIFO 3 as TREQ +// 0x08 -> Select PIO1's TX FIFO 0 as TREQ +// 0x09 -> Select PIO1's TX FIFO 1 as TREQ +// 0x0a -> Select PIO1's TX FIFO 2 as TREQ +// 0x0b -> Select PIO1's TX FIFO 3 as TREQ +// 0x0c -> Select PIO1's RX FIFO 0 as TREQ +// 0x0d -> Select PIO1's RX FIFO 1 as TREQ +// 0x0e -> Select PIO1's RX FIFO 2 as TREQ +// 0x0f -> Select PIO1's RX FIFO 3 as TREQ +// 0x10 -> Select PIO2's TX FIFO 0 as TREQ +// 0x11 -> Select PIO2's TX FIFO 1 as TREQ +// 0x12 -> Select PIO2's TX FIFO 2 as TREQ +// 0x13 -> Select PIO2's TX FIFO 3 as TREQ +// 0x14 -> Select PIO2's RX FIFO 0 as TREQ +// 0x15 -> Select PIO2's RX FIFO 1 as TREQ +// 0x16 -> Select PIO2's RX FIFO 2 as TREQ +// 0x17 -> Select PIO2's RX FIFO 3 as TREQ +// 0x18 -> Select SPI0's TX FIFO as TREQ +// 0x19 -> Select SPI0's RX FIFO as TREQ +// 0x1a -> Select SPI1's TX FIFO as TREQ +// 0x1b -> Select SPI1's RX FIFO as TREQ +// 0x1c -> Select UART0's TX FIFO as TREQ +// 0x1d -> Select UART0's RX FIFO as TREQ +// 0x1e -> Select UART1's TX FIFO as TREQ +// 0x1f -> Select UART1's RX FIFO as TREQ +// 0x20 -> Select PWM Counter 0's Wrap Value as TREQ +// 0x21 -> Select PWM Counter 1's Wrap Value as TREQ +// 0x22 -> Select PWM Counter 2's Wrap Value as TREQ +// 0x23 -> Select PWM Counter 3's Wrap Value as TREQ +// 0x24 -> Select PWM Counter 4's Wrap Value as TREQ +// 0x25 -> Select PWM Counter 5's Wrap Value as TREQ +// 0x26 -> Select PWM Counter 6's Wrap Value as TREQ +// 0x27 -> Select PWM Counter 7's Wrap Value as TREQ +// 0x28 -> Select PWM Counter 8's Wrap Value as TREQ +// 0x29 -> Select PWM Counter 9's Wrap Value as TREQ +// 0x2a -> Select PWM Counter 10's Wrap Value as TREQ +// 0x2b -> Select PWM Counter 11's Wrap Value as TREQ +// 0x2c -> Select I2C0's TX FIFO as TREQ +// 0x2d -> Select I2C0's RX FIFO as TREQ +// 0x2e -> Select I2C1's TX FIFO as TREQ +// 0x2f -> Select I2C1's RX FIFO as TREQ +// 0x30 -> Select the ADC as TREQ +// 0x31 -> Select the XIP Streaming FIFO as TREQ +// 0x32 -> Select XIP_QMITX as TREQ +// 0x33 -> Select XIP_QMIRX as TREQ +// 0x34 -> Select HSTX as TREQ +// 0x35 -> Select CORESIGHT as TREQ +// 0x36 -> Select SHA256 as TREQ #define DMA_CH13_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) #define DMA_CH13_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) #define DMA_CH13_CTRL_TRIG_TREQ_SEL_MSB _u(22) @@ -6104,6 +7589,61 @@ #define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) #define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX0 _u(0x00) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX1 _u(0x01) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX2 _u(0x02) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX3 _u(0x03) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX0 _u(0x04) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX1 _u(0x05) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX2 _u(0x06) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX3 _u(0x07) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX0 _u(0x08) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX1 _u(0x09) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX2 _u(0x0a) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX3 _u(0x0b) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX0 _u(0x0c) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX1 _u(0x0d) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX2 _u(0x0e) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX3 _u(0x0f) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX0 _u(0x10) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX1 _u(0x11) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX2 _u(0x12) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX3 _u(0x13) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX0 _u(0x14) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX1 _u(0x15) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX2 _u(0x16) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX3 _u(0x17) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_TX _u(0x18) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_RX _u(0x19) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_TX _u(0x1a) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_RX _u(0x1b) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_UART0_TX _u(0x1c) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_UART0_RX _u(0x1d) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_UART1_TX _u(0x1e) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_UART1_RX _u(0x1f) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP0 _u(0x20) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP1 _u(0x21) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP2 _u(0x22) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP3 _u(0x23) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP4 _u(0x24) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP5 _u(0x25) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP6 _u(0x26) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP7 _u(0x27) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP8 _u(0x28) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP9 _u(0x29) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP10 _u(0x2a) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP11 _u(0x2b) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_TX _u(0x2c) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_RX _u(0x2d) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_TX _u(0x2e) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_RX _u(0x2f) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_ADC _u(0x30) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_XIP_STREAM _u(0x31) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMITX _u(0x32) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMIRX _u(0x33) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_HSTX _u(0x34) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_CORESIGHT _u(0x35) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_SHA256 _u(0x36) // ----------------------------------------------------------------------------- // Field : DMA_CH13_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel @@ -6547,6 +8087,61 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. +// 0x00 -> Select PIO0's TX FIFO 0 as TREQ +// 0x01 -> Select PIO0's TX FIFO 1 as TREQ +// 0x02 -> Select PIO0's TX FIFO 2 as TREQ +// 0x03 -> Select PIO0's TX FIFO 3 as TREQ +// 0x04 -> Select PIO0's RX FIFO 0 as TREQ +// 0x05 -> Select PIO0's RX FIFO 1 as TREQ +// 0x06 -> Select PIO0's RX FIFO 2 as TREQ +// 0x07 -> Select PIO0's RX FIFO 3 as TREQ +// 0x08 -> Select PIO1's TX FIFO 0 as TREQ +// 0x09 -> Select PIO1's TX FIFO 1 as TREQ +// 0x0a -> Select PIO1's TX FIFO 2 as TREQ +// 0x0b -> Select PIO1's TX FIFO 3 as TREQ +// 0x0c -> Select PIO1's RX FIFO 0 as TREQ +// 0x0d -> Select PIO1's RX FIFO 1 as TREQ +// 0x0e -> Select PIO1's RX FIFO 2 as TREQ +// 0x0f -> Select PIO1's RX FIFO 3 as TREQ +// 0x10 -> Select PIO2's TX FIFO 0 as TREQ +// 0x11 -> Select PIO2's TX FIFO 1 as TREQ +// 0x12 -> Select PIO2's TX FIFO 2 as TREQ +// 0x13 -> Select PIO2's TX FIFO 3 as TREQ +// 0x14 -> Select PIO2's RX FIFO 0 as TREQ +// 0x15 -> Select PIO2's RX FIFO 1 as TREQ +// 0x16 -> Select PIO2's RX FIFO 2 as TREQ +// 0x17 -> Select PIO2's RX FIFO 3 as TREQ +// 0x18 -> Select SPI0's TX FIFO as TREQ +// 0x19 -> Select SPI0's RX FIFO as TREQ +// 0x1a -> Select SPI1's TX FIFO as TREQ +// 0x1b -> Select SPI1's RX FIFO as TREQ +// 0x1c -> Select UART0's TX FIFO as TREQ +// 0x1d -> Select UART0's RX FIFO as TREQ +// 0x1e -> Select UART1's TX FIFO as TREQ +// 0x1f -> Select UART1's RX FIFO as TREQ +// 0x20 -> Select PWM Counter 0's Wrap Value as TREQ +// 0x21 -> Select PWM Counter 1's Wrap Value as TREQ +// 0x22 -> Select PWM Counter 2's Wrap Value as TREQ +// 0x23 -> Select PWM Counter 3's Wrap Value as TREQ +// 0x24 -> Select PWM Counter 4's Wrap Value as TREQ +// 0x25 -> Select PWM Counter 5's Wrap Value as TREQ +// 0x26 -> Select PWM Counter 6's Wrap Value as TREQ +// 0x27 -> Select PWM Counter 7's Wrap Value as TREQ +// 0x28 -> Select PWM Counter 8's Wrap Value as TREQ +// 0x29 -> Select PWM Counter 9's Wrap Value as TREQ +// 0x2a -> Select PWM Counter 10's Wrap Value as TREQ +// 0x2b -> Select PWM Counter 11's Wrap Value as TREQ +// 0x2c -> Select I2C0's TX FIFO as TREQ +// 0x2d -> Select I2C0's RX FIFO as TREQ +// 0x2e -> Select I2C1's TX FIFO as TREQ +// 0x2f -> Select I2C1's RX FIFO as TREQ +// 0x30 -> Select the ADC as TREQ +// 0x31 -> Select the XIP Streaming FIFO as TREQ +// 0x32 -> Select XIP_QMITX as TREQ +// 0x33 -> Select XIP_QMIRX as TREQ +// 0x34 -> Select HSTX as TREQ +// 0x35 -> Select CORESIGHT as TREQ +// 0x36 -> Select SHA256 as TREQ #define DMA_CH14_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) #define DMA_CH14_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) #define DMA_CH14_CTRL_TRIG_TREQ_SEL_MSB _u(22) @@ -6557,6 +8152,61 @@ #define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) #define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX0 _u(0x00) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX1 _u(0x01) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX2 _u(0x02) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX3 _u(0x03) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX0 _u(0x04) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX1 _u(0x05) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX2 _u(0x06) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX3 _u(0x07) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX0 _u(0x08) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX1 _u(0x09) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX2 _u(0x0a) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX3 _u(0x0b) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX0 _u(0x0c) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX1 _u(0x0d) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX2 _u(0x0e) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX3 _u(0x0f) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX0 _u(0x10) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX1 _u(0x11) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX2 _u(0x12) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX3 _u(0x13) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX0 _u(0x14) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX1 _u(0x15) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX2 _u(0x16) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX3 _u(0x17) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_TX _u(0x18) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_RX _u(0x19) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_TX _u(0x1a) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_RX _u(0x1b) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_UART0_TX _u(0x1c) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_UART0_RX _u(0x1d) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_UART1_TX _u(0x1e) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_UART1_RX _u(0x1f) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP0 _u(0x20) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP1 _u(0x21) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP2 _u(0x22) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP3 _u(0x23) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP4 _u(0x24) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP5 _u(0x25) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP6 _u(0x26) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP7 _u(0x27) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP8 _u(0x28) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP9 _u(0x29) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP10 _u(0x2a) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP11 _u(0x2b) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_TX _u(0x2c) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_RX _u(0x2d) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_TX _u(0x2e) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_RX _u(0x2f) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_ADC _u(0x30) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_XIP_STREAM _u(0x31) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMITX _u(0x32) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMIRX _u(0x33) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_HSTX _u(0x34) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_CORESIGHT _u(0x35) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_SHA256 _u(0x36) // ----------------------------------------------------------------------------- // Field : DMA_CH14_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel @@ -7000,6 +8650,61 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. +// 0x00 -> Select PIO0's TX FIFO 0 as TREQ +// 0x01 -> Select PIO0's TX FIFO 1 as TREQ +// 0x02 -> Select PIO0's TX FIFO 2 as TREQ +// 0x03 -> Select PIO0's TX FIFO 3 as TREQ +// 0x04 -> Select PIO0's RX FIFO 0 as TREQ +// 0x05 -> Select PIO0's RX FIFO 1 as TREQ +// 0x06 -> Select PIO0's RX FIFO 2 as TREQ +// 0x07 -> Select PIO0's RX FIFO 3 as TREQ +// 0x08 -> Select PIO1's TX FIFO 0 as TREQ +// 0x09 -> Select PIO1's TX FIFO 1 as TREQ +// 0x0a -> Select PIO1's TX FIFO 2 as TREQ +// 0x0b -> Select PIO1's TX FIFO 3 as TREQ +// 0x0c -> Select PIO1's RX FIFO 0 as TREQ +// 0x0d -> Select PIO1's RX FIFO 1 as TREQ +// 0x0e -> Select PIO1's RX FIFO 2 as TREQ +// 0x0f -> Select PIO1's RX FIFO 3 as TREQ +// 0x10 -> Select PIO2's TX FIFO 0 as TREQ +// 0x11 -> Select PIO2's TX FIFO 1 as TREQ +// 0x12 -> Select PIO2's TX FIFO 2 as TREQ +// 0x13 -> Select PIO2's TX FIFO 3 as TREQ +// 0x14 -> Select PIO2's RX FIFO 0 as TREQ +// 0x15 -> Select PIO2's RX FIFO 1 as TREQ +// 0x16 -> Select PIO2's RX FIFO 2 as TREQ +// 0x17 -> Select PIO2's RX FIFO 3 as TREQ +// 0x18 -> Select SPI0's TX FIFO as TREQ +// 0x19 -> Select SPI0's RX FIFO as TREQ +// 0x1a -> Select SPI1's TX FIFO as TREQ +// 0x1b -> Select SPI1's RX FIFO as TREQ +// 0x1c -> Select UART0's TX FIFO as TREQ +// 0x1d -> Select UART0's RX FIFO as TREQ +// 0x1e -> Select UART1's TX FIFO as TREQ +// 0x1f -> Select UART1's RX FIFO as TREQ +// 0x20 -> Select PWM Counter 0's Wrap Value as TREQ +// 0x21 -> Select PWM Counter 1's Wrap Value as TREQ +// 0x22 -> Select PWM Counter 2's Wrap Value as TREQ +// 0x23 -> Select PWM Counter 3's Wrap Value as TREQ +// 0x24 -> Select PWM Counter 4's Wrap Value as TREQ +// 0x25 -> Select PWM Counter 5's Wrap Value as TREQ +// 0x26 -> Select PWM Counter 6's Wrap Value as TREQ +// 0x27 -> Select PWM Counter 7's Wrap Value as TREQ +// 0x28 -> Select PWM Counter 8's Wrap Value as TREQ +// 0x29 -> Select PWM Counter 9's Wrap Value as TREQ +// 0x2a -> Select PWM Counter 10's Wrap Value as TREQ +// 0x2b -> Select PWM Counter 11's Wrap Value as TREQ +// 0x2c -> Select I2C0's TX FIFO as TREQ +// 0x2d -> Select I2C0's RX FIFO as TREQ +// 0x2e -> Select I2C1's TX FIFO as TREQ +// 0x2f -> Select I2C1's RX FIFO as TREQ +// 0x30 -> Select the ADC as TREQ +// 0x31 -> Select the XIP Streaming FIFO as TREQ +// 0x32 -> Select XIP_QMITX as TREQ +// 0x33 -> Select XIP_QMIRX as TREQ +// 0x34 -> Select HSTX as TREQ +// 0x35 -> Select CORESIGHT as TREQ +// 0x36 -> Select SHA256 as TREQ #define DMA_CH15_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) #define DMA_CH15_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) #define DMA_CH15_CTRL_TRIG_TREQ_SEL_MSB _u(22) @@ -7010,6 +8715,61 @@ #define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) #define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX0 _u(0x00) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX1 _u(0x01) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX2 _u(0x02) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_TX3 _u(0x03) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX0 _u(0x04) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX1 _u(0x05) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX2 _u(0x06) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PIO0_RX3 _u(0x07) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX0 _u(0x08) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX1 _u(0x09) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX2 _u(0x0a) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_TX3 _u(0x0b) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX0 _u(0x0c) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX1 _u(0x0d) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX2 _u(0x0e) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PIO1_RX3 _u(0x0f) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX0 _u(0x10) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX1 _u(0x11) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX2 _u(0x12) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_TX3 _u(0x13) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX0 _u(0x14) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX1 _u(0x15) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX2 _u(0x16) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PIO2_RX3 _u(0x17) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_TX _u(0x18) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_SPI0_RX _u(0x19) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_TX _u(0x1a) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_SPI1_RX _u(0x1b) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_UART0_TX _u(0x1c) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_UART0_RX _u(0x1d) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_UART1_TX _u(0x1e) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_UART1_RX _u(0x1f) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP0 _u(0x20) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP1 _u(0x21) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP2 _u(0x22) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP3 _u(0x23) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP4 _u(0x24) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP5 _u(0x25) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP6 _u(0x26) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP7 _u(0x27) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP8 _u(0x28) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP9 _u(0x29) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP10 _u(0x2a) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PWM_WRAP11 _u(0x2b) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_TX _u(0x2c) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_I2C0_RX _u(0x2d) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_TX _u(0x2e) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_I2C1_RX _u(0x2f) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_ADC _u(0x30) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_XIP_STREAM _u(0x31) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMITX _u(0x32) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_XIP_QMIRX _u(0x33) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_HSTX _u(0x34) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_CORESIGHT _u(0x35) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_SHA256 _u(0x36) // ----------------------------------------------------------------------------- // Field : DMA_CH15_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel @@ -7619,11 +9379,14 @@ // ----------------------------------------------------------------------------- // Field : DMA_SNIFF_CTRL_CALC // 0x0 -> Calculate a CRC-32 (IEEE802.3 polynomial) -// 0x1 -> Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data +// 0x1 -> Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed +// data // 0x2 -> Calculate a CRC-16-CCITT // 0x3 -> Calculate a CRC-16-CCITT with bit reversed data -// 0xe -> XOR reduction over all data. == 1 if the total 1 population count is odd. -// 0xf -> Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) +// 0xe -> XOR reduction over all data. == 1 if the total 1 population +// count is odd. +// 0xf -> Calculate a simple 32-bit checksum (addition with a 32 bit +// accumulator) #define DMA_SNIFF_CTRL_CALC_RESET _u(0x0) #define DMA_SNIFF_CTRL_CALC_BITS _u(0x000001e0) #define DMA_SNIFF_CTRL_CALC_MSB _u(8) @@ -7711,7 +9474,7 @@ #define DMA_CHAN_ABORT_RESET _u(0x00000000) #define DMA_CHAN_ABORT_MSB _u(15) #define DMA_CHAN_ABORT_LSB _u(0) -#define DMA_CHAN_ABORT_ACCESS "SC" +#define DMA_CHAN_ABORT_ACCESS "WC" // ============================================================================= // Register : DMA_N_CHANNELS // Description : The number of channels this DMA instance is equipped with. This
diff --git a/src/rp2350/hardware_regs/include/hardware/regs/glitch_detector.h b/src/rp2350/hardware_regs/include/hardware/regs/glitch_detector.h index f2f9bb0..024ff3b 100644 --- a/src/rp2350/hardware_regs/include/hardware/regs/glitch_detector.h +++ b/src/rp2350/hardware_regs/include/hardware/regs/glitch_detector.h
@@ -26,7 +26,8 @@ // // This register is Secure read/write only. // 0x5bad -> Do not force the glitch detectors to be armed -// 0x0000 -> Force the glitch detectors to be armed. (Any value other than ARM_NO counts as YES) +// 0x0000 -> Force the glitch detectors to be armed. (Any value other than +// ARM_NO counts as YES) #define GLITCH_DETECTOR_ARM_OFFSET _u(0x00000000) #define GLITCH_DETECTOR_ARM_BITS _u(0x0000ffff) #define GLITCH_DETECTOR_ARM_RESET _u(0x00005bad) @@ -41,7 +42,8 @@ // Ignored if ARM is YES. // // This register is Secure read/write only. -// 0x0000 -> Do not disarm the glitch detectors. (Any value other than DISARM_YES counts as NO) +// 0x0000 -> Do not disarm the glitch detectors. (Any value other than +// DISARM_YES counts as NO) // 0xdcaf -> Disarm the glitch detectors #define GLITCH_DETECTOR_DISARM_OFFSET _u(0x00000004) #define GLITCH_DETECTOR_DISARM_BITS _u(0x0000ffff) @@ -62,8 +64,10 @@ #define GLITCH_DETECTOR_SENSITIVITY_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : GLITCH_DETECTOR_SENSITIVITY_DEFAULT -// 0x00 -> Use the default sensitivity configured in OTP for all detectors. (Any value other than DEFAULT_NO counts as YES) -// 0xde -> Do not use the default sensitivity configured in OTP. Instead use the value from this register. +// 0x00 -> Use the default sensitivity configured in OTP for all +// detectors. (Any value other than DEFAULT_NO counts as YES) +// 0xde -> Do not use the default sensitivity configured in OTP. Instead +// use the value from this register. #define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_RESET _u(0x00) #define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_BITS _u(0xff000000) #define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_MSB _u(31)
diff --git a/src/rp2350/hardware_regs/include/hardware/regs/hstx_ctrl.h b/src/rp2350/hardware_regs/include/hardware/regs/hstx_ctrl.h index 61cd304..0a309c9 100644 --- a/src/rp2350/hardware_regs/include/hardware/regs/hstx_ctrl.h +++ b/src/rp2350/hardware_regs/include/hardware/regs/hstx_ctrl.h
@@ -551,7 +551,8 @@ // Field : HSTX_CTRL_EXPAND_TMDS_L2_NBITS // Description : Number of valid data bits for the lane 2 TMDS encoder, starting // from bit 7 of the rotated data. Field values of 0 -> 7 encode -// counts of 1 -> 8 bits. +// counts of 1 -> 8 bits. Remaining LSBs are masked to 0 after the +// rotate. #define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_RESET _u(0x0) #define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_BITS _u(0x00e00000) #define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_MSB _u(23) @@ -560,7 +561,8 @@ // ----------------------------------------------------------------------------- // Field : HSTX_CTRL_EXPAND_TMDS_L2_ROT // Description : Right-rotate applied to the current shifter data before the -// lane 2 TMDS encoder. +// lane 2 TMDS encoder. Remaining LSBs are masked to 0 after the +// rotate. #define HSTX_CTRL_EXPAND_TMDS_L2_ROT_RESET _u(0x00) #define HSTX_CTRL_EXPAND_TMDS_L2_ROT_BITS _u(0x001f0000) #define HSTX_CTRL_EXPAND_TMDS_L2_ROT_MSB _u(20) @@ -570,7 +572,8 @@ // Field : HSTX_CTRL_EXPAND_TMDS_L1_NBITS // Description : Number of valid data bits for the lane 1 TMDS encoder, starting // from bit 7 of the rotated data. Field values of 0 -> 7 encode -// counts of 1 -> 8 bits. +// counts of 1 -> 8 bits. Remaining LSBs are masked to 0 after the +// rotate. #define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_RESET _u(0x0) #define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_BITS _u(0x0000e000) #define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_MSB _u(15) @@ -579,7 +582,8 @@ // ----------------------------------------------------------------------------- // Field : HSTX_CTRL_EXPAND_TMDS_L1_ROT // Description : Right-rotate applied to the current shifter data before the -// lane 1 TMDS encoder. +// lane 1 TMDS encoder. Remaining LSBs are masked to 0 after the +// rotate. #define HSTX_CTRL_EXPAND_TMDS_L1_ROT_RESET _u(0x00) #define HSTX_CTRL_EXPAND_TMDS_L1_ROT_BITS _u(0x00001f00) #define HSTX_CTRL_EXPAND_TMDS_L1_ROT_MSB _u(12) @@ -589,7 +593,8 @@ // Field : HSTX_CTRL_EXPAND_TMDS_L0_NBITS // Description : Number of valid data bits for the lane 0 TMDS encoder, starting // from bit 7 of the rotated data. Field values of 0 -> 7 encode -// counts of 1 -> 8 bits. +// counts of 1 -> 8 bits. Remaining LSBs are masked to 0 after the +// rotate. #define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_RESET _u(0x0) #define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_BITS _u(0x000000e0) #define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_MSB _u(7) @@ -598,7 +603,8 @@ // ----------------------------------------------------------------------------- // Field : HSTX_CTRL_EXPAND_TMDS_L0_ROT // Description : Right-rotate applied to the current shifter data before the -// lane 0 TMDS encoder. +// lane 0 TMDS encoder. Remaining LSBs are masked to 0 after the +// rotate. #define HSTX_CTRL_EXPAND_TMDS_L0_ROT_RESET _u(0x00) #define HSTX_CTRL_EXPAND_TMDS_L0_ROT_BITS _u(0x0000001f) #define HSTX_CTRL_EXPAND_TMDS_L0_ROT_MSB _u(4)
diff --git a/src/rp2350/hardware_regs/include/hardware/regs/i2c.h b/src/rp2350/hardware_regs/include/hardware/regs/i2c.h index 8196b14..c06a98d 100644 --- a/src/rp2350/hardware_regs/include/hardware/regs/i2c.h +++ b/src/rp2350/hardware_regs/include/hardware/regs/i2c.h
@@ -1960,7 +1960,8 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Slave-Transmitter -// 0x0 -> Slave trying to transmit to remote master in read mode- scenario not present +// 0x0 -> Slave trying to transmit to remote master in read mode- +// scenario not present // 0x1 -> Slave trying to transmit to remote master in read mode #define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_RESET _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_BITS _u(0x00008000) @@ -2001,8 +2002,10 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Slave-Transmitter -// 0x0 -> Slave flushes existing data in TX-FIFO upon getting read command- scenario not present -// 0x1 -> Slave flushes existing data in TX-FIFO upon getting read command +// 0x0 -> Slave flushes existing data in TX-FIFO upon getting read +// command- scenario not present +// 0x1 -> Slave flushes existing data in TX-FIFO upon getting read +// command #define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_RESET _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_BITS _u(0x00002000) #define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_MSB _u(13) @@ -2019,7 +2022,8 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter -// 0x0 -> Master or Slave-Transmitter lost arbitration- scenario not present +// 0x0 -> Master or Slave-Transmitter lost arbitration- scenario not +// present // 0x1 -> Master or Slave-Transmitter lost arbitration #define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_RESET _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_BITS _u(0x00001000) @@ -2036,7 +2040,8 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Master-Transmitter or Master-Receiver -// 0x0 -> User initiating master operation when MASTER disabled- scenario not present +// 0x0 -> User initiating master operation when MASTER disabled- scenario +// not present // 0x1 -> User initiating master operation when MASTER disabled #define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_RESET _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_BITS _u(0x00000800) @@ -2054,8 +2059,10 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Master-Receiver -// 0x0 -> Master not trying to read in 10Bit addressing mode when RESTART disabled -// 0x1 -> Master trying to read in 10Bit addressing mode when RESTART disabled +// 0x0 -> Master not trying to read in 10Bit addressing mode when RESTART +// disabled +// 0x1 -> Master trying to read in 10Bit addressing mode when RESTART +// disabled #define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_RESET _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_BITS _u(0x00000400) #define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_MSB _u(10) @@ -2080,7 +2087,8 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Master -// 0x0 -> User trying to send START byte when RESTART disabled- scenario not present +// 0x0 -> User trying to send START byte when RESTART disabled- scenario +// not present // 0x1 -> User trying to send START byte when RESTART disabled #define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_RESET _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_BITS _u(0x00000200) @@ -2098,7 +2106,8 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Master-Transmitter or Master-Receiver -// 0x0 -> User trying to switch Master to HS mode when RESTART disabled- scenario not present +// 0x0 -> User trying to switch Master to HS mode when RESTART disabled- +// scenario not present // 0x1 -> User trying to switch Master to HS mode when RESTART disabled #define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_RESET _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_BITS _u(0x00000100) @@ -2188,7 +2197,8 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Master-Transmitter -// 0x0 -> Transmitted data non-ACKed by addressed slave-scenario not present +// 0x0 -> Transmitted data non-ACKed by addressed slave-scenario not +// present // 0x1 -> Transmitted data not ACKed by addressed slave #define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_RESET _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS _u(0x00000008)
diff --git a/src/rp2350/hardware_regs/include/hardware/regs/io_bank0.h b/src/rp2350/hardware_regs/include/hardware/regs/io_bank0.h index ef8576a..4f1bd68 100644 --- a/src/rp2350/hardware_regs/include/hardware/regs/io_bank0.h +++ b/src/rp2350/hardware_regs/include/hardware/regs/io_bank0.h
@@ -88,7 +88,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO0_CTRL_OEOVER_RESET _u(0x0) @@ -103,7 +104,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO0_CTRL_OUTOVER_RESET _u(0x0) @@ -124,7 +126,7 @@ // 0x02 -> uart0_tx // 0x03 -> i2c0_sda // 0x04 -> pwm_a_0 -// 0x05 -> siob_proc_0 +// 0x05 -> sio_0 // 0x06 -> pio0_0 // 0x07 -> pio1_0 // 0x08 -> pio2_0 @@ -141,7 +143,7 @@ #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SIOB_PROC_0 _u(0x05) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SIO_0 _u(0x05) #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO0_0 _u(0x06) #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO1_0 _u(0x07) #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO2_0 _u(0x08) @@ -224,7 +226,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO1_CTRL_OEOVER_RESET _u(0x0) @@ -239,7 +242,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO1_CTRL_OUTOVER_RESET _u(0x0) @@ -260,7 +264,7 @@ // 0x02 -> uart0_rx // 0x03 -> i2c0_scl // 0x04 -> pwm_b_0 -// 0x05 -> siob_proc_1 +// 0x05 -> sio_1 // 0x06 -> pio0_1 // 0x07 -> pio1_1 // 0x08 -> pio2_1 @@ -277,7 +281,7 @@ #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SIOB_PROC_1 _u(0x05) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SIO_1 _u(0x05) #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO0_1 _u(0x06) #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO1_1 _u(0x07) #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO2_1 _u(0x08) @@ -360,7 +364,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO2_CTRL_OEOVER_RESET _u(0x0) @@ -375,7 +380,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO2_CTRL_OUTOVER_RESET _u(0x0) @@ -396,7 +402,7 @@ // 0x02 -> uart0_cts // 0x03 -> i2c1_sda // 0x04 -> pwm_a_1 -// 0x05 -> siob_proc_2 +// 0x05 -> sio_2 // 0x06 -> pio0_2 // 0x07 -> pio1_2 // 0x08 -> pio2_2 @@ -414,7 +420,7 @@ #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SIOB_PROC_2 _u(0x05) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SIO_2 _u(0x05) #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO0_2 _u(0x06) #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO1_2 _u(0x07) #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO2_2 _u(0x08) @@ -498,7 +504,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO3_CTRL_OEOVER_RESET _u(0x0) @@ -513,7 +520,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO3_CTRL_OUTOVER_RESET _u(0x0) @@ -534,7 +542,7 @@ // 0x02 -> uart0_rts // 0x03 -> i2c1_scl // 0x04 -> pwm_b_1 -// 0x05 -> siob_proc_3 +// 0x05 -> sio_3 // 0x06 -> pio0_3 // 0x07 -> pio1_3 // 0x08 -> pio2_3 @@ -552,7 +560,7 @@ #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SIOB_PROC_3 _u(0x05) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SIO_3 _u(0x05) #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO0_3 _u(0x06) #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO1_3 _u(0x07) #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO2_3 _u(0x08) @@ -636,7 +644,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO4_CTRL_OEOVER_RESET _u(0x0) @@ -651,7 +660,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO4_CTRL_OUTOVER_RESET _u(0x0) @@ -671,7 +681,7 @@ // 0x02 -> uart1_tx // 0x03 -> i2c0_sda // 0x04 -> pwm_a_2 -// 0x05 -> siob_proc_4 +// 0x05 -> sio_4 // 0x06 -> pio0_4 // 0x07 -> pio1_4 // 0x08 -> pio2_4 @@ -687,7 +697,7 @@ #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SIOB_PROC_4 _u(0x05) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SIO_4 _u(0x05) #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO0_4 _u(0x06) #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO1_4 _u(0x07) #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO2_4 _u(0x08) @@ -770,7 +780,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO5_CTRL_OEOVER_RESET _u(0x0) @@ -785,7 +796,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO5_CTRL_OUTOVER_RESET _u(0x0) @@ -805,7 +817,7 @@ // 0x02 -> uart1_rx // 0x03 -> i2c0_scl // 0x04 -> pwm_b_2 -// 0x05 -> siob_proc_5 +// 0x05 -> sio_5 // 0x06 -> pio0_5 // 0x07 -> pio1_5 // 0x08 -> pio2_5 @@ -821,7 +833,7 @@ #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SIOB_PROC_5 _u(0x05) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SIO_5 _u(0x05) #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO0_5 _u(0x06) #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO1_5 _u(0x07) #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO2_5 _u(0x08) @@ -904,7 +916,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO6_CTRL_OEOVER_RESET _u(0x0) @@ -919,7 +932,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO6_CTRL_OUTOVER_RESET _u(0x0) @@ -939,7 +953,7 @@ // 0x02 -> uart1_cts // 0x03 -> i2c1_sda // 0x04 -> pwm_a_3 -// 0x05 -> siob_proc_6 +// 0x05 -> sio_6 // 0x06 -> pio0_6 // 0x07 -> pio1_6 // 0x08 -> pio2_6 @@ -955,7 +969,7 @@ #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SIOB_PROC_6 _u(0x05) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SIO_6 _u(0x05) #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO0_6 _u(0x06) #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO1_6 _u(0x07) #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO2_6 _u(0x08) @@ -1038,7 +1052,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO7_CTRL_OEOVER_RESET _u(0x0) @@ -1053,7 +1068,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO7_CTRL_OUTOVER_RESET _u(0x0) @@ -1073,7 +1089,7 @@ // 0x02 -> uart1_rts // 0x03 -> i2c1_scl // 0x04 -> pwm_b_3 -// 0x05 -> siob_proc_7 +// 0x05 -> sio_7 // 0x06 -> pio0_7 // 0x07 -> pio1_7 // 0x08 -> pio2_7 @@ -1089,7 +1105,7 @@ #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SIOB_PROC_7 _u(0x05) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SIO_7 _u(0x05) #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO0_7 _u(0x06) #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO1_7 _u(0x07) #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO2_7 _u(0x08) @@ -1172,7 +1188,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO8_CTRL_OEOVER_RESET _u(0x0) @@ -1187,7 +1204,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO8_CTRL_OUTOVER_RESET _u(0x0) @@ -1207,7 +1225,7 @@ // 0x02 -> uart1_tx // 0x03 -> i2c0_sda // 0x04 -> pwm_a_4 -// 0x05 -> siob_proc_8 +// 0x05 -> sio_8 // 0x06 -> pio0_8 // 0x07 -> pio1_8 // 0x08 -> pio2_8 @@ -1223,7 +1241,7 @@ #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SIOB_PROC_8 _u(0x05) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SIO_8 _u(0x05) #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO0_8 _u(0x06) #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO1_8 _u(0x07) #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO2_8 _u(0x08) @@ -1306,7 +1324,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO9_CTRL_OEOVER_RESET _u(0x0) @@ -1321,7 +1340,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO9_CTRL_OUTOVER_RESET _u(0x0) @@ -1341,7 +1361,7 @@ // 0x02 -> uart1_rx // 0x03 -> i2c0_scl // 0x04 -> pwm_b_4 -// 0x05 -> siob_proc_9 +// 0x05 -> sio_9 // 0x06 -> pio0_9 // 0x07 -> pio1_9 // 0x08 -> pio2_9 @@ -1356,7 +1376,7 @@ #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SIOB_PROC_9 _u(0x05) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SIO_9 _u(0x05) #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO0_9 _u(0x06) #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO1_9 _u(0x07) #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO2_9 _u(0x08) @@ -1438,7 +1458,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO10_CTRL_OEOVER_RESET _u(0x0) @@ -1453,7 +1474,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO10_CTRL_OUTOVER_RESET _u(0x0) @@ -1473,7 +1495,7 @@ // 0x02 -> uart1_cts // 0x03 -> i2c1_sda // 0x04 -> pwm_a_5 -// 0x05 -> siob_proc_10 +// 0x05 -> sio_10 // 0x06 -> pio0_10 // 0x07 -> pio1_10 // 0x08 -> pio2_10 @@ -1489,7 +1511,7 @@ #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SIOB_PROC_10 _u(0x05) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SIO_10 _u(0x05) #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO0_10 _u(0x06) #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO1_10 _u(0x07) #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO2_10 _u(0x08) @@ -1572,7 +1594,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO11_CTRL_OEOVER_RESET _u(0x0) @@ -1587,7 +1610,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO11_CTRL_OUTOVER_RESET _u(0x0) @@ -1607,7 +1631,7 @@ // 0x02 -> uart1_rts // 0x03 -> i2c1_scl // 0x04 -> pwm_b_5 -// 0x05 -> siob_proc_11 +// 0x05 -> sio_11 // 0x06 -> pio0_11 // 0x07 -> pio1_11 // 0x08 -> pio2_11 @@ -1623,7 +1647,7 @@ #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SIOB_PROC_11 _u(0x05) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SIO_11 _u(0x05) #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO0_11 _u(0x06) #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO1_11 _u(0x07) #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO2_11 _u(0x08) @@ -1706,7 +1730,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO12_CTRL_OEOVER_RESET _u(0x0) @@ -1721,7 +1746,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO12_CTRL_OUTOVER_RESET _u(0x0) @@ -1742,7 +1768,7 @@ // 0x02 -> uart0_tx // 0x03 -> i2c0_sda // 0x04 -> pwm_a_6 -// 0x05 -> siob_proc_12 +// 0x05 -> sio_12 // 0x06 -> pio0_12 // 0x07 -> pio1_12 // 0x08 -> pio2_12 @@ -1759,7 +1785,7 @@ #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SIOB_PROC_12 _u(0x05) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SIO_12 _u(0x05) #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO0_12 _u(0x06) #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO1_12 _u(0x07) #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO2_12 _u(0x08) @@ -1842,7 +1868,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO13_CTRL_OEOVER_RESET _u(0x0) @@ -1857,7 +1884,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO13_CTRL_OUTOVER_RESET _u(0x0) @@ -1878,7 +1906,7 @@ // 0x02 -> uart0_rx // 0x03 -> i2c0_scl // 0x04 -> pwm_b_6 -// 0x05 -> siob_proc_13 +// 0x05 -> sio_13 // 0x06 -> pio0_13 // 0x07 -> pio1_13 // 0x08 -> pio2_13 @@ -1895,7 +1923,7 @@ #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SIOB_PROC_13 _u(0x05) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SIO_13 _u(0x05) #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO0_13 _u(0x06) #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO1_13 _u(0x07) #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO2_13 _u(0x08) @@ -1978,7 +2006,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO14_CTRL_OEOVER_RESET _u(0x0) @@ -1993,7 +2022,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO14_CTRL_OUTOVER_RESET _u(0x0) @@ -2014,7 +2044,7 @@ // 0x02 -> uart0_cts // 0x03 -> i2c1_sda // 0x04 -> pwm_a_7 -// 0x05 -> siob_proc_14 +// 0x05 -> sio_14 // 0x06 -> pio0_14 // 0x07 -> pio1_14 // 0x08 -> pio2_14 @@ -2032,7 +2062,7 @@ #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PWM_A_7 _u(0x04) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SIOB_PROC_14 _u(0x05) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SIO_14 _u(0x05) #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO0_14 _u(0x06) #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO1_14 _u(0x07) #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO2_14 _u(0x08) @@ -2116,7 +2146,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO15_CTRL_OEOVER_RESET _u(0x0) @@ -2131,7 +2162,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO15_CTRL_OUTOVER_RESET _u(0x0) @@ -2152,7 +2184,7 @@ // 0x02 -> uart0_rts // 0x03 -> i2c1_scl // 0x04 -> pwm_b_7 -// 0x05 -> siob_proc_15 +// 0x05 -> sio_15 // 0x06 -> pio0_15 // 0x07 -> pio1_15 // 0x08 -> pio2_15 @@ -2170,7 +2202,7 @@ #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PWM_B_7 _u(0x04) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SIOB_PROC_15 _u(0x05) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SIO_15 _u(0x05) #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO0_15 _u(0x06) #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO1_15 _u(0x07) #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO2_15 _u(0x08) @@ -2254,7 +2286,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO16_CTRL_OEOVER_RESET _u(0x0) @@ -2269,7 +2302,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO16_CTRL_OUTOVER_RESET _u(0x0) @@ -2290,7 +2324,7 @@ // 0x02 -> uart0_tx // 0x03 -> i2c0_sda // 0x04 -> pwm_a_0 -// 0x05 -> siob_proc_16 +// 0x05 -> sio_16 // 0x06 -> pio0_16 // 0x07 -> pio1_16 // 0x08 -> pio2_16 @@ -2306,7 +2340,7 @@ #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SIOB_PROC_16 _u(0x05) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SIO_16 _u(0x05) #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO0_16 _u(0x06) #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO1_16 _u(0x07) #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO2_16 _u(0x08) @@ -2388,7 +2422,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO17_CTRL_OEOVER_RESET _u(0x0) @@ -2403,7 +2438,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO17_CTRL_OUTOVER_RESET _u(0x0) @@ -2424,7 +2460,7 @@ // 0x02 -> uart0_rx // 0x03 -> i2c0_scl // 0x04 -> pwm_b_0 -// 0x05 -> siob_proc_17 +// 0x05 -> sio_17 // 0x06 -> pio0_17 // 0x07 -> pio1_17 // 0x08 -> pio2_17 @@ -2440,7 +2476,7 @@ #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SIOB_PROC_17 _u(0x05) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SIO_17 _u(0x05) #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO0_17 _u(0x06) #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO1_17 _u(0x07) #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO2_17 _u(0x08) @@ -2522,7 +2558,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO18_CTRL_OEOVER_RESET _u(0x0) @@ -2537,7 +2574,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO18_CTRL_OUTOVER_RESET _u(0x0) @@ -2558,7 +2596,7 @@ // 0x02 -> uart0_cts // 0x03 -> i2c1_sda // 0x04 -> pwm_a_1 -// 0x05 -> siob_proc_18 +// 0x05 -> sio_18 // 0x06 -> pio0_18 // 0x07 -> pio1_18 // 0x08 -> pio2_18 @@ -2575,7 +2613,7 @@ #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SIOB_PROC_18 _u(0x05) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SIO_18 _u(0x05) #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO0_18 _u(0x06) #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO1_18 _u(0x07) #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO2_18 _u(0x08) @@ -2658,7 +2696,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO19_CTRL_OEOVER_RESET _u(0x0) @@ -2673,7 +2712,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO19_CTRL_OUTOVER_RESET _u(0x0) @@ -2694,7 +2734,7 @@ // 0x02 -> uart0_rts // 0x03 -> i2c1_scl // 0x04 -> pwm_b_1 -// 0x05 -> siob_proc_19 +// 0x05 -> sio_19 // 0x06 -> pio0_19 // 0x07 -> pio1_19 // 0x08 -> pio2_19 @@ -2712,7 +2752,7 @@ #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SIOB_PROC_19 _u(0x05) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SIO_19 _u(0x05) #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO0_19 _u(0x06) #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO1_19 _u(0x07) #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO2_19 _u(0x08) @@ -2796,7 +2836,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO20_CTRL_OEOVER_RESET _u(0x0) @@ -2811,7 +2852,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO20_CTRL_OUTOVER_RESET _u(0x0) @@ -2831,7 +2873,7 @@ // 0x02 -> uart1_tx // 0x03 -> i2c0_sda // 0x04 -> pwm_a_2 -// 0x05 -> siob_proc_20 +// 0x05 -> sio_20 // 0x06 -> pio0_20 // 0x07 -> pio1_20 // 0x08 -> pio2_20 @@ -2847,7 +2889,7 @@ #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SIOB_PROC_20 _u(0x05) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SIO_20 _u(0x05) #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO0_20 _u(0x06) #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO1_20 _u(0x07) #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO2_20 _u(0x08) @@ -2930,7 +2972,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO21_CTRL_OEOVER_RESET _u(0x0) @@ -2945,7 +2988,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO21_CTRL_OUTOVER_RESET _u(0x0) @@ -2965,7 +3009,7 @@ // 0x02 -> uart1_rx // 0x03 -> i2c0_scl // 0x04 -> pwm_b_2 -// 0x05 -> siob_proc_21 +// 0x05 -> sio_21 // 0x06 -> pio0_21 // 0x07 -> pio1_21 // 0x08 -> pio2_21 @@ -2981,7 +3025,7 @@ #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SIOB_PROC_21 _u(0x05) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SIO_21 _u(0x05) #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO0_21 _u(0x06) #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO1_21 _u(0x07) #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO2_21 _u(0x08) @@ -3064,7 +3108,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO22_CTRL_OEOVER_RESET _u(0x0) @@ -3079,7 +3124,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO22_CTRL_OUTOVER_RESET _u(0x0) @@ -3099,7 +3145,7 @@ // 0x02 -> uart1_cts // 0x03 -> i2c1_sda // 0x04 -> pwm_a_3 -// 0x05 -> siob_proc_22 +// 0x05 -> sio_22 // 0x06 -> pio0_22 // 0x07 -> pio1_22 // 0x08 -> pio2_22 @@ -3116,7 +3162,7 @@ #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SIOB_PROC_22 _u(0x05) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SIO_22 _u(0x05) #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO0_22 _u(0x06) #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO1_22 _u(0x07) #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO2_22 _u(0x08) @@ -3200,7 +3246,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO23_CTRL_OEOVER_RESET _u(0x0) @@ -3215,7 +3262,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO23_CTRL_OUTOVER_RESET _u(0x0) @@ -3235,7 +3283,7 @@ // 0x02 -> uart1_rts // 0x03 -> i2c1_scl // 0x04 -> pwm_b_3 -// 0x05 -> siob_proc_23 +// 0x05 -> sio_23 // 0x06 -> pio0_23 // 0x07 -> pio1_23 // 0x08 -> pio2_23 @@ -3252,7 +3300,7 @@ #define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) #define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) #define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SIOB_PROC_23 _u(0x05) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SIO_23 _u(0x05) #define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO0_23 _u(0x06) #define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO1_23 _u(0x07) #define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO2_23 _u(0x08) @@ -3336,7 +3384,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO24_CTRL_OEOVER_RESET _u(0x0) @@ -3351,7 +3400,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO24_CTRL_OUTOVER_RESET _u(0x0) @@ -3371,7 +3421,7 @@ // 0x02 -> uart1_tx // 0x03 -> i2c0_sda // 0x04 -> pwm_a_4 -// 0x05 -> siob_proc_24 +// 0x05 -> sio_24 // 0x06 -> pio0_24 // 0x07 -> pio1_24 // 0x08 -> pio2_24 @@ -3387,7 +3437,7 @@ #define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) #define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) #define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SIOB_PROC_24 _u(0x05) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SIO_24 _u(0x05) #define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO0_24 _u(0x06) #define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO1_24 _u(0x07) #define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO2_24 _u(0x08) @@ -3470,7 +3520,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO25_CTRL_OEOVER_RESET _u(0x0) @@ -3485,7 +3536,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO25_CTRL_OUTOVER_RESET _u(0x0) @@ -3505,7 +3557,7 @@ // 0x02 -> uart1_rx // 0x03 -> i2c0_scl // 0x04 -> pwm_b_4 -// 0x05 -> siob_proc_25 +// 0x05 -> sio_25 // 0x06 -> pio0_25 // 0x07 -> pio1_25 // 0x08 -> pio2_25 @@ -3521,7 +3573,7 @@ #define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) #define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) #define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SIOB_PROC_25 _u(0x05) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SIO_25 _u(0x05) #define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO0_25 _u(0x06) #define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO1_25 _u(0x07) #define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO2_25 _u(0x08) @@ -3604,7 +3656,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO26_CTRL_OEOVER_RESET _u(0x0) @@ -3619,7 +3672,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO26_CTRL_OUTOVER_RESET _u(0x0) @@ -3639,7 +3693,7 @@ // 0x02 -> uart1_cts // 0x03 -> i2c1_sda // 0x04 -> pwm_a_5 -// 0x05 -> siob_proc_26 +// 0x05 -> sio_26 // 0x06 -> pio0_26 // 0x07 -> pio1_26 // 0x08 -> pio2_26 @@ -3655,7 +3709,7 @@ #define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) #define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) #define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SIOB_PROC_26 _u(0x05) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SIO_26 _u(0x05) #define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO0_26 _u(0x06) #define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO1_26 _u(0x07) #define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO2_26 _u(0x08) @@ -3738,7 +3792,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO27_CTRL_OEOVER_RESET _u(0x0) @@ -3753,7 +3808,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO27_CTRL_OUTOVER_RESET _u(0x0) @@ -3773,7 +3829,7 @@ // 0x02 -> uart1_rts // 0x03 -> i2c1_scl // 0x04 -> pwm_b_5 -// 0x05 -> siob_proc_27 +// 0x05 -> sio_27 // 0x06 -> pio0_27 // 0x07 -> pio1_27 // 0x08 -> pio2_27 @@ -3789,7 +3845,7 @@ #define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) #define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) #define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SIOB_PROC_27 _u(0x05) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SIO_27 _u(0x05) #define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO0_27 _u(0x06) #define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO1_27 _u(0x07) #define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO2_27 _u(0x08) @@ -3872,7 +3928,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO28_CTRL_OEOVER_RESET _u(0x0) @@ -3887,7 +3944,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO28_CTRL_OUTOVER_RESET _u(0x0) @@ -3907,7 +3965,7 @@ // 0x02 -> uart0_tx // 0x03 -> i2c0_sda // 0x04 -> pwm_a_6 -// 0x05 -> siob_proc_28 +// 0x05 -> sio_28 // 0x06 -> pio0_28 // 0x07 -> pio1_28 // 0x08 -> pio2_28 @@ -3922,7 +3980,7 @@ #define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) #define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) #define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SIOB_PROC_28 _u(0x05) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SIO_28 _u(0x05) #define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO0_28 _u(0x06) #define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO1_28 _u(0x07) #define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO2_28 _u(0x08) @@ -4004,7 +4062,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO29_CTRL_OEOVER_RESET _u(0x0) @@ -4019,7 +4078,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO29_CTRL_OUTOVER_RESET _u(0x0) @@ -4039,7 +4099,7 @@ // 0x02 -> uart0_rx // 0x03 -> i2c0_scl // 0x04 -> pwm_b_6 -// 0x05 -> siob_proc_29 +// 0x05 -> sio_29 // 0x06 -> pio0_29 // 0x07 -> pio1_29 // 0x08 -> pio2_29 @@ -4054,7 +4114,7 @@ #define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) #define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) #define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SIOB_PROC_29 _u(0x05) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SIO_29 _u(0x05) #define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO0_29 _u(0x06) #define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO1_29 _u(0x07) #define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO2_29 _u(0x08) @@ -4136,7 +4196,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO30_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO30_CTRL_OEOVER_RESET _u(0x0) @@ -4151,7 +4212,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO30_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO30_CTRL_OUTOVER_RESET _u(0x0) @@ -4171,7 +4233,7 @@ // 0x02 -> uart0_cts // 0x03 -> i2c1_sda // 0x04 -> pwm_a_7 -// 0x05 -> siob_proc_30 +// 0x05 -> sio_30 // 0x06 -> pio0_30 // 0x07 -> pio1_30 // 0x08 -> pio2_30 @@ -4187,7 +4249,7 @@ #define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) #define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) #define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_PWM_A_7 _u(0x04) -#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_SIOB_PROC_30 _u(0x05) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_SIO_30 _u(0x05) #define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_PIO0_30 _u(0x06) #define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_PIO1_30 _u(0x07) #define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_PIO2_30 _u(0x08) @@ -4270,7 +4332,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO31_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO31_CTRL_OEOVER_RESET _u(0x0) @@ -4285,7 +4348,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO31_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO31_CTRL_OUTOVER_RESET _u(0x0) @@ -4305,7 +4369,7 @@ // 0x02 -> uart0_rts // 0x03 -> i2c1_scl // 0x04 -> pwm_b_7 -// 0x05 -> siob_proc_31 +// 0x05 -> sio_31 // 0x06 -> pio0_31 // 0x07 -> pio1_31 // 0x08 -> pio2_31 @@ -4321,7 +4385,7 @@ #define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) #define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) #define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_PWM_B_7 _u(0x04) -#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_SIOB_PROC_31 _u(0x05) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_SIO_31 _u(0x05) #define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_PIO0_31 _u(0x06) #define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_PIO1_31 _u(0x07) #define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_PIO2_31 _u(0x08) @@ -4404,7 +4468,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO32_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO32_CTRL_OEOVER_RESET _u(0x0) @@ -4419,7 +4484,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO32_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO32_CTRL_OUTOVER_RESET _u(0x0) @@ -4439,7 +4505,7 @@ // 0x02 -> uart0_tx // 0x03 -> i2c0_sda // 0x04 -> pwm_a_8 -// 0x05 -> siob_proc_32 +// 0x05 -> sio_32 // 0x06 -> pio0_32 // 0x07 -> pio1_32 // 0x08 -> pio2_32 @@ -4454,7 +4520,7 @@ #define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) #define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) #define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_PWM_A_8 _u(0x04) -#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_SIOB_PROC_32 _u(0x05) +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_SIO_32 _u(0x05) #define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_PIO0_32 _u(0x06) #define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_PIO1_32 _u(0x07) #define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_PIO2_32 _u(0x08) @@ -4536,7 +4602,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO33_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO33_CTRL_OEOVER_RESET _u(0x0) @@ -4551,7 +4618,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO33_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO33_CTRL_OUTOVER_RESET _u(0x0) @@ -4571,7 +4639,7 @@ // 0x02 -> uart0_rx // 0x03 -> i2c0_scl // 0x04 -> pwm_b_8 -// 0x05 -> siob_proc_33 +// 0x05 -> sio_33 // 0x06 -> pio0_33 // 0x07 -> pio1_33 // 0x08 -> pio2_33 @@ -4586,7 +4654,7 @@ #define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) #define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) #define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_PWM_B_8 _u(0x04) -#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_SIOB_PROC_33 _u(0x05) +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_SIO_33 _u(0x05) #define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_PIO0_33 _u(0x06) #define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_PIO1_33 _u(0x07) #define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_PIO2_33 _u(0x08) @@ -4668,7 +4736,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO34_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO34_CTRL_OEOVER_RESET _u(0x0) @@ -4683,7 +4752,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO34_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO34_CTRL_OUTOVER_RESET _u(0x0) @@ -4703,7 +4773,7 @@ // 0x02 -> uart0_cts // 0x03 -> i2c1_sda // 0x04 -> pwm_a_9 -// 0x05 -> siob_proc_34 +// 0x05 -> sio_34 // 0x06 -> pio0_34 // 0x07 -> pio1_34 // 0x08 -> pio2_34 @@ -4719,7 +4789,7 @@ #define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) #define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) #define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_PWM_A_9 _u(0x04) -#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_SIOB_PROC_34 _u(0x05) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_SIO_34 _u(0x05) #define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_PIO0_34 _u(0x06) #define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_PIO1_34 _u(0x07) #define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_PIO2_34 _u(0x08) @@ -4802,7 +4872,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO35_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO35_CTRL_OEOVER_RESET _u(0x0) @@ -4817,7 +4888,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO35_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO35_CTRL_OUTOVER_RESET _u(0x0) @@ -4837,7 +4909,7 @@ // 0x02 -> uart0_rts // 0x03 -> i2c1_scl // 0x04 -> pwm_b_9 -// 0x05 -> siob_proc_35 +// 0x05 -> sio_35 // 0x06 -> pio0_35 // 0x07 -> pio1_35 // 0x08 -> pio2_35 @@ -4853,7 +4925,7 @@ #define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) #define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) #define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_PWM_B_9 _u(0x04) -#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_SIOB_PROC_35 _u(0x05) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_SIO_35 _u(0x05) #define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_PIO0_35 _u(0x06) #define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_PIO1_35 _u(0x07) #define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_PIO2_35 _u(0x08) @@ -4936,7 +5008,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO36_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO36_CTRL_OEOVER_RESET _u(0x0) @@ -4951,7 +5024,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO36_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO36_CTRL_OUTOVER_RESET _u(0x0) @@ -4971,7 +5045,7 @@ // 0x02 -> uart1_tx // 0x03 -> i2c0_sda // 0x04 -> pwm_a_10 -// 0x05 -> siob_proc_36 +// 0x05 -> sio_36 // 0x06 -> pio0_36 // 0x07 -> pio1_36 // 0x08 -> pio2_36 @@ -4986,7 +5060,7 @@ #define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) #define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) #define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_PWM_A_10 _u(0x04) -#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_SIOB_PROC_36 _u(0x05) +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_SIO_36 _u(0x05) #define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_PIO0_36 _u(0x06) #define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_PIO1_36 _u(0x07) #define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_PIO2_36 _u(0x08) @@ -5068,7 +5142,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO37_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO37_CTRL_OEOVER_RESET _u(0x0) @@ -5083,7 +5158,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO37_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO37_CTRL_OUTOVER_RESET _u(0x0) @@ -5103,7 +5179,7 @@ // 0x02 -> uart1_rx // 0x03 -> i2c0_scl // 0x04 -> pwm_b_10 -// 0x05 -> siob_proc_37 +// 0x05 -> sio_37 // 0x06 -> pio0_37 // 0x07 -> pio1_37 // 0x08 -> pio2_37 @@ -5118,7 +5194,7 @@ #define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) #define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) #define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_PWM_B_10 _u(0x04) -#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_SIOB_PROC_37 _u(0x05) +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_SIO_37 _u(0x05) #define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_PIO0_37 _u(0x06) #define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_PIO1_37 _u(0x07) #define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_PIO2_37 _u(0x08) @@ -5200,7 +5276,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO38_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO38_CTRL_OEOVER_RESET _u(0x0) @@ -5215,7 +5292,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO38_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO38_CTRL_OUTOVER_RESET _u(0x0) @@ -5235,7 +5313,7 @@ // 0x02 -> uart1_cts // 0x03 -> i2c1_sda // 0x04 -> pwm_a_11 -// 0x05 -> siob_proc_38 +// 0x05 -> sio_38 // 0x06 -> pio0_38 // 0x07 -> pio1_38 // 0x08 -> pio2_38 @@ -5251,7 +5329,7 @@ #define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) #define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) #define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_PWM_A_11 _u(0x04) -#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_SIOB_PROC_38 _u(0x05) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_SIO_38 _u(0x05) #define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_PIO0_38 _u(0x06) #define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_PIO1_38 _u(0x07) #define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_PIO2_38 _u(0x08) @@ -5334,7 +5412,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO39_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO39_CTRL_OEOVER_RESET _u(0x0) @@ -5349,7 +5428,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO39_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO39_CTRL_OUTOVER_RESET _u(0x0) @@ -5369,7 +5449,7 @@ // 0x02 -> uart1_rts // 0x03 -> i2c1_scl // 0x04 -> pwm_b_11 -// 0x05 -> siob_proc_39 +// 0x05 -> sio_39 // 0x06 -> pio0_39 // 0x07 -> pio1_39 // 0x08 -> pio2_39 @@ -5385,7 +5465,7 @@ #define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) #define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) #define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_PWM_B_11 _u(0x04) -#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_SIOB_PROC_39 _u(0x05) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_SIO_39 _u(0x05) #define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_PIO0_39 _u(0x06) #define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_PIO1_39 _u(0x07) #define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_PIO2_39 _u(0x08) @@ -5468,7 +5548,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO40_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO40_CTRL_OEOVER_RESET _u(0x0) @@ -5483,7 +5564,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO40_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO40_CTRL_OUTOVER_RESET _u(0x0) @@ -5503,7 +5585,7 @@ // 0x02 -> uart1_tx // 0x03 -> i2c0_sda // 0x04 -> pwm_a_8 -// 0x05 -> siob_proc_40 +// 0x05 -> sio_40 // 0x06 -> pio0_40 // 0x07 -> pio1_40 // 0x08 -> pio2_40 @@ -5518,7 +5600,7 @@ #define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) #define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) #define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_PWM_A_8 _u(0x04) -#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_SIOB_PROC_40 _u(0x05) +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_SIO_40 _u(0x05) #define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_PIO0_40 _u(0x06) #define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_PIO1_40 _u(0x07) #define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_PIO2_40 _u(0x08) @@ -5600,7 +5682,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO41_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO41_CTRL_OEOVER_RESET _u(0x0) @@ -5615,7 +5698,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO41_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO41_CTRL_OUTOVER_RESET _u(0x0) @@ -5635,7 +5719,7 @@ // 0x02 -> uart1_rx // 0x03 -> i2c0_scl // 0x04 -> pwm_b_8 -// 0x05 -> siob_proc_41 +// 0x05 -> sio_41 // 0x06 -> pio0_41 // 0x07 -> pio1_41 // 0x08 -> pio2_41 @@ -5650,7 +5734,7 @@ #define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) #define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) #define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_PWM_B_8 _u(0x04) -#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_SIOB_PROC_41 _u(0x05) +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_SIO_41 _u(0x05) #define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_PIO0_41 _u(0x06) #define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_PIO1_41 _u(0x07) #define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_PIO2_41 _u(0x08) @@ -5732,7 +5816,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO42_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO42_CTRL_OEOVER_RESET _u(0x0) @@ -5747,7 +5832,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO42_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO42_CTRL_OUTOVER_RESET _u(0x0) @@ -5767,7 +5853,7 @@ // 0x02 -> uart1_cts // 0x03 -> i2c1_sda // 0x04 -> pwm_a_9 -// 0x05 -> siob_proc_42 +// 0x05 -> sio_42 // 0x06 -> pio0_42 // 0x07 -> pio1_42 // 0x08 -> pio2_42 @@ -5783,7 +5869,7 @@ #define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) #define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) #define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_PWM_A_9 _u(0x04) -#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_SIOB_PROC_42 _u(0x05) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_SIO_42 _u(0x05) #define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_PIO0_42 _u(0x06) #define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_PIO1_42 _u(0x07) #define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_PIO2_42 _u(0x08) @@ -5866,7 +5952,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO43_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO43_CTRL_OEOVER_RESET _u(0x0) @@ -5881,7 +5968,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO43_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO43_CTRL_OUTOVER_RESET _u(0x0) @@ -5901,7 +5989,7 @@ // 0x02 -> uart1_rts // 0x03 -> i2c1_scl // 0x04 -> pwm_b_9 -// 0x05 -> siob_proc_43 +// 0x05 -> sio_43 // 0x06 -> pio0_43 // 0x07 -> pio1_43 // 0x08 -> pio2_43 @@ -5917,7 +6005,7 @@ #define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) #define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) #define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_PWM_B_9 _u(0x04) -#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_SIOB_PROC_43 _u(0x05) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_SIO_43 _u(0x05) #define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_PIO0_43 _u(0x06) #define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_PIO1_43 _u(0x07) #define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_PIO2_43 _u(0x08) @@ -6000,7 +6088,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO44_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO44_CTRL_OEOVER_RESET _u(0x0) @@ -6015,7 +6104,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO44_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO44_CTRL_OUTOVER_RESET _u(0x0) @@ -6035,7 +6125,7 @@ // 0x02 -> uart0_tx // 0x03 -> i2c0_sda // 0x04 -> pwm_a_10 -// 0x05 -> siob_proc_44 +// 0x05 -> sio_44 // 0x06 -> pio0_44 // 0x07 -> pio1_44 // 0x08 -> pio2_44 @@ -6050,7 +6140,7 @@ #define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) #define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) #define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_PWM_A_10 _u(0x04) -#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_SIOB_PROC_44 _u(0x05) +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_SIO_44 _u(0x05) #define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_PIO0_44 _u(0x06) #define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_PIO1_44 _u(0x07) #define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_PIO2_44 _u(0x08) @@ -6132,7 +6222,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO45_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO45_CTRL_OEOVER_RESET _u(0x0) @@ -6147,7 +6238,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO45_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO45_CTRL_OUTOVER_RESET _u(0x0) @@ -6167,7 +6259,7 @@ // 0x02 -> uart0_rx // 0x03 -> i2c0_scl // 0x04 -> pwm_b_10 -// 0x05 -> siob_proc_45 +// 0x05 -> sio_45 // 0x06 -> pio0_45 // 0x07 -> pio1_45 // 0x08 -> pio2_45 @@ -6182,7 +6274,7 @@ #define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) #define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) #define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_PWM_B_10 _u(0x04) -#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_SIOB_PROC_45 _u(0x05) +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_SIO_45 _u(0x05) #define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_PIO0_45 _u(0x06) #define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_PIO1_45 _u(0x07) #define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_PIO2_45 _u(0x08) @@ -6264,7 +6356,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO46_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO46_CTRL_OEOVER_RESET _u(0x0) @@ -6279,7 +6372,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO46_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO46_CTRL_OUTOVER_RESET _u(0x0) @@ -6299,7 +6393,7 @@ // 0x02 -> uart0_cts // 0x03 -> i2c1_sda // 0x04 -> pwm_a_11 -// 0x05 -> siob_proc_46 +// 0x05 -> sio_46 // 0x06 -> pio0_46 // 0x07 -> pio1_46 // 0x08 -> pio2_46 @@ -6315,7 +6409,7 @@ #define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) #define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) #define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_PWM_A_11 _u(0x04) -#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_SIOB_PROC_46 _u(0x05) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_SIO_46 _u(0x05) #define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_PIO0_46 _u(0x06) #define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_PIO1_46 _u(0x07) #define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_PIO2_46 _u(0x08) @@ -6398,7 +6492,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO47_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_BANK0_GPIO47_CTRL_OEOVER_RESET _u(0x0) @@ -6413,7 +6508,8 @@ // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO47_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_BANK0_GPIO47_CTRL_OUTOVER_RESET _u(0x0) @@ -6433,7 +6529,7 @@ // 0x02 -> uart0_rts // 0x03 -> i2c1_scl // 0x04 -> pwm_b_11 -// 0x05 -> siob_proc_47 +// 0x05 -> sio_47 // 0x06 -> pio0_47 // 0x07 -> pio1_47 // 0x08 -> pio2_47 @@ -6450,7 +6546,7 @@ #define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) #define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) #define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_PWM_B_11 _u(0x04) -#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_SIOB_PROC_47 _u(0x05) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_SIO_47 _u(0x05) #define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_PIO0_47 _u(0x06) #define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_PIO1_47 _u(0x07) #define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_PIO2_47 _u(0x08)
diff --git a/src/rp2350/hardware_regs/include/hardware/regs/io_qspi.h b/src/rp2350/hardware_regs/include/hardware/regs/io_qspi.h index 8ca1de1..2d067f0 100644 --- a/src/rp2350/hardware_regs/include/hardware/regs/io_qspi.h +++ b/src/rp2350/hardware_regs/include/hardware/regs/io_qspi.h
@@ -88,7 +88,8 @@ // ----------------------------------------------------------------------------- // Field : IO_QSPI_USBPHY_DP_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_QSPI_USBPHY_DP_CTRL_OEOVER_RESET _u(0x0) @@ -103,7 +104,8 @@ // ----------------------------------------------------------------------------- // Field : IO_QSPI_USBPHY_DP_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_RESET _u(0x0) @@ -121,7 +123,7 @@ // 31 == NULL // 0x02 -> uart1_tx // 0x03 -> i2c0_sda -// 0x05 -> siob_proc_56 +// 0x05 -> sio_56 // 0x1f -> null #define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_RESET _u(0x1f) #define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_BITS _u(0x0000001f) @@ -130,7 +132,7 @@ #define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_ACCESS "RW" #define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) #define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_VALUE_SIOB_PROC_56 _u(0x05) +#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_VALUE_SIO_56 _u(0x05) #define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_QSPI_USBPHY_DM_STATUS @@ -208,7 +210,8 @@ // ----------------------------------------------------------------------------- // Field : IO_QSPI_USBPHY_DM_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_QSPI_USBPHY_DM_CTRL_OEOVER_RESET _u(0x0) @@ -223,7 +226,8 @@ // ----------------------------------------------------------------------------- // Field : IO_QSPI_USBPHY_DM_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_RESET _u(0x0) @@ -241,7 +245,7 @@ // 31 == NULL // 0x02 -> uart1_rx // 0x03 -> i2c0_scl -// 0x05 -> siob_proc_57 +// 0x05 -> sio_57 // 0x1f -> null #define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_RESET _u(0x1f) #define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_BITS _u(0x0000001f) @@ -250,7 +254,7 @@ #define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_ACCESS "RW" #define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) #define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_VALUE_SIOB_PROC_57 _u(0x05) +#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_VALUE_SIO_57 _u(0x05) #define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SCLK_STATUS @@ -328,7 +332,8 @@ // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_RESET _u(0x0) @@ -343,7 +348,8 @@ // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_RESET _u(0x0) @@ -362,7 +368,7 @@ // 0x00 -> xip_sclk // 0x02 -> uart1_cts // 0x03 -> i2c1_sda -// 0x05 -> siob_proc_58 +// 0x05 -> sio_58 // 0x0b -> uart1_tx // 0x1f -> null #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_RESET _u(0x1f) @@ -373,7 +379,7 @@ #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_XIP_SCLK _u(0x00) #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_SIOB_PROC_58 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_SIO_58 _u(0x05) #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b) #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= @@ -452,7 +458,8 @@ // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_RESET _u(0x0) @@ -467,7 +474,8 @@ // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_RESET _u(0x0) @@ -486,7 +494,7 @@ // 0x00 -> xip_ss_n_0 // 0x02 -> uart1_rts // 0x03 -> i2c1_scl -// 0x05 -> siob_proc_59 +// 0x05 -> sio_59 // 0x0b -> uart1_rx // 0x1f -> null #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_RESET _u(0x1f) @@ -497,7 +505,7 @@ #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_XIP_SS_N_0 _u(0x00) #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_SIOB_PROC_59 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_SIO_59 _u(0x05) #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b) #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= @@ -576,7 +584,8 @@ // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_RESET _u(0x0) @@ -591,7 +600,8 @@ // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_RESET _u(0x0) @@ -610,7 +620,7 @@ // 0x00 -> xip_sd0 // 0x02 -> uart0_tx // 0x03 -> i2c0_sda -// 0x05 -> siob_proc_60 +// 0x05 -> sio_60 // 0x1f -> null #define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_RESET _u(0x1f) #define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_BITS _u(0x0000001f) @@ -620,7 +630,7 @@ #define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_XIP_SD0 _u(0x00) #define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) #define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_SIOB_PROC_60 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_SIO_60 _u(0x05) #define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SD1_STATUS @@ -698,7 +708,8 @@ // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_RESET _u(0x0) @@ -713,7 +724,8 @@ // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_RESET _u(0x0) @@ -732,7 +744,7 @@ // 0x00 -> xip_sd1 // 0x02 -> uart0_rx // 0x03 -> i2c0_scl -// 0x05 -> siob_proc_61 +// 0x05 -> sio_61 // 0x1f -> null #define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_RESET _u(0x1f) #define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_BITS _u(0x0000001f) @@ -742,7 +754,7 @@ #define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_XIP_SD1 _u(0x00) #define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) #define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_SIOB_PROC_61 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_SIO_61 _u(0x05) #define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SD2_STATUS @@ -820,7 +832,8 @@ // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_RESET _u(0x0) @@ -835,7 +848,8 @@ // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_RESET _u(0x0) @@ -854,7 +868,7 @@ // 0x00 -> xip_sd2 // 0x02 -> uart0_cts // 0x03 -> i2c1_sda -// 0x05 -> siob_proc_62 +// 0x05 -> sio_62 // 0x0b -> uart0_tx // 0x1f -> null #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_RESET _u(0x1f) @@ -865,7 +879,7 @@ #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_XIP_SD2 _u(0x00) #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_SIOB_PROC_62 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_SIO_62 _u(0x05) #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b) #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= @@ -944,7 +958,8 @@ // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER // 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected +// by funcsel // 0x2 -> disable output // 0x3 -> enable output #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_RESET _u(0x0) @@ -959,7 +974,8 @@ // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER // 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by +// funcsel // 0x2 -> drive output low // 0x3 -> drive output high #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_RESET _u(0x0) @@ -978,7 +994,7 @@ // 0x00 -> xip_sd3 // 0x02 -> uart0_rts // 0x03 -> i2c1_scl -// 0x05 -> siob_proc_63 +// 0x05 -> sio_63 // 0x0b -> uart0_rx // 0x1f -> null #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_RESET _u(0x1f) @@ -989,7 +1005,7 @@ #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_XIP_SD3 _u(0x00) #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_SIOB_PROC_63 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_SIO_63 _u(0x05) #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b) #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // =============================================================================
diff --git a/src/rp2350/hardware_regs/include/hardware/regs/m33.h b/src/rp2350/hardware_regs/include/hardware/regs/m33.h index 1fafa5d..480e8f1 100644 --- a/src/rp2350/hardware_regs/include/hardware/regs/m33.h +++ b/src/rp2350/hardware_regs/include/hardware/regs/m33.h
@@ -810,7 +810,7 @@ #define M33_ITM_PIDR5_RESET _u(0x00000000) #define M33_ITM_PIDR5_MSB _u(31) #define M33_ITM_PIDR5_LSB _u(0) -#define M33_ITM_PIDR5_ACCESS "RW" +#define M33_ITM_PIDR5_ACCESS "-" // ============================================================================= // Register : M33_ITM_PIDR6 // Description : Provides CoreSight discovery information for the ITM @@ -819,7 +819,7 @@ #define M33_ITM_PIDR6_RESET _u(0x00000000) #define M33_ITM_PIDR6_MSB _u(31) #define M33_ITM_PIDR6_LSB _u(0) -#define M33_ITM_PIDR6_ACCESS "RW" +#define M33_ITM_PIDR6_ACCESS "-" // ============================================================================= // Register : M33_ITM_PIDR7 // Description : Provides CoreSight discovery information for the ITM @@ -828,7 +828,7 @@ #define M33_ITM_PIDR7_RESET _u(0x00000000) #define M33_ITM_PIDR7_MSB _u(31) #define M33_ITM_PIDR7_LSB _u(0) -#define M33_ITM_PIDR7_ACCESS "RW" +#define M33_ITM_PIDR7_ACCESS "-" // ============================================================================= // Register : M33_ITM_PIDR0 // Description : Provides CoreSight discovery information for the ITM @@ -1552,7 +1552,7 @@ #define M33_DWT_PIDR5_RESET _u(0x00000000) #define M33_DWT_PIDR5_MSB _u(31) #define M33_DWT_PIDR5_LSB _u(0) -#define M33_DWT_PIDR5_ACCESS "RW" +#define M33_DWT_PIDR5_ACCESS "-" // ============================================================================= // Register : M33_DWT_PIDR6 // Description : Provides CoreSight discovery information for the DWT @@ -1561,7 +1561,7 @@ #define M33_DWT_PIDR6_RESET _u(0x00000000) #define M33_DWT_PIDR6_MSB _u(31) #define M33_DWT_PIDR6_LSB _u(0) -#define M33_DWT_PIDR6_ACCESS "RW" +#define M33_DWT_PIDR6_ACCESS "-" // ============================================================================= // Register : M33_DWT_PIDR7 // Description : Provides CoreSight discovery information for the DWT @@ -1570,7 +1570,7 @@ #define M33_DWT_PIDR7_RESET _u(0x00000000) #define M33_DWT_PIDR7_MSB _u(31) #define M33_DWT_PIDR7_LSB _u(0) -#define M33_DWT_PIDR7_ACCESS "RW" +#define M33_DWT_PIDR7_ACCESS "-" // ============================================================================= // Register : M33_DWT_PIDR0 // Description : Provides CoreSight discovery information for the DWT @@ -2047,7 +2047,7 @@ #define M33_FP_PIDR5_RESET _u(0x00000000) #define M33_FP_PIDR5_MSB _u(31) #define M33_FP_PIDR5_LSB _u(0) -#define M33_FP_PIDR5_ACCESS "RW" +#define M33_FP_PIDR5_ACCESS "-" // ============================================================================= // Register : M33_FP_PIDR6 // Description : Provides CoreSight discovery information for the FP @@ -2056,7 +2056,7 @@ #define M33_FP_PIDR6_RESET _u(0x00000000) #define M33_FP_PIDR6_MSB _u(31) #define M33_FP_PIDR6_LSB _u(0) -#define M33_FP_PIDR6_ACCESS "RW" +#define M33_FP_PIDR6_ACCESS "-" // ============================================================================= // Register : M33_FP_PIDR7 // Description : Provides CoreSight discovery information for the FP @@ -2065,7 +2065,7 @@ #define M33_FP_PIDR7_RESET _u(0x00000000) #define M33_FP_PIDR7_MSB _u(31) #define M33_FP_PIDR7_LSB _u(0) -#define M33_FP_PIDR7_ACCESS "RW" +#define M33_FP_PIDR7_ACCESS "-" // ============================================================================= // Register : M33_FP_PIDR0 // Description : Provides CoreSight discovery information for the FP @@ -3521,10 +3521,8 @@ #define M33_AIRCR_PRIGROUP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M33_AIRCR_SYSRESETREQS -// Description : System reset request, Secure state only. -// 0 SYSRESETREQ functionality is available to both Security -// states. -// 1 SYSRESETREQ functionality is only available to Secure state. +// Description : This resets only the core on which SYSRESETREQ is asserted, and +// not the wider system. #define M33_AIRCR_SYSRESETREQS_RESET _u(0x0) #define M33_AIRCR_SYSRESETREQS_BITS _u(0x00000008) #define M33_AIRCR_SYSRESETREQS_MSB _u(3) @@ -3532,12 +3530,8 @@ #define M33_AIRCR_SYSRESETREQS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M33_AIRCR_SYSRESETREQ -// Description : Writing 1 to this bit causes the SYSRESETREQ signal to the -// outer system to be asserted to request a reset. The intention -// is to force a large system reset of all major components except -// for debug. The C_HALT bit in the DHCSR is cleared as a result -// of the system reset requested. The debugger does not lose -// contact with the device. +// Description : This resets only the core on which SYSRESETREQ is asserted, and +// not the wider system. #define M33_AIRCR_SYSRESETREQ_RESET _u(0x0) #define M33_AIRCR_SYSRESETREQ_BITS _u(0x00000004) #define M33_AIRCR_SYSRESETREQ_MSB _u(2) @@ -4411,7 +4405,7 @@ #define M33_ID_MMFR1_RESET _u(0x00000000) #define M33_ID_MMFR1_MSB _u(31) #define M33_ID_MMFR1_LSB _u(0) -#define M33_ID_MMFR1_ACCESS "RW" +#define M33_ID_MMFR1_ACCESS "-" // ============================================================================= // Register : M33_ID_MMFR2 // Description : Provides information about the implemented memory model and @@ -4749,7 +4743,7 @@ #define M33_ID_ISAR5_RESET _u(0x00000000) #define M33_ID_ISAR5_MSB _u(31) #define M33_ID_ISAR5_LSB _u(0) -#define M33_ID_ISAR5_ACCESS "RW" +#define M33_ID_ISAR5_ACCESS "-" // ============================================================================= // Register : M33_CTR // Description : Provides information about the architecture of the caches. CTR @@ -6460,7 +6454,7 @@ #define M33_DPIDR5_RESET _u(0x00000000) #define M33_DPIDR5_MSB _u(31) #define M33_DPIDR5_LSB _u(0) -#define M33_DPIDR5_ACCESS "RW" +#define M33_DPIDR5_ACCESS "-" // ============================================================================= // Register : M33_DPIDR6 // Description : Provides CoreSight discovery information for the SCS @@ -6469,7 +6463,7 @@ #define M33_DPIDR6_RESET _u(0x00000000) #define M33_DPIDR6_MSB _u(31) #define M33_DPIDR6_LSB _u(0) -#define M33_DPIDR6_ACCESS "RW" +#define M33_DPIDR6_ACCESS "-" // ============================================================================= // Register : M33_DPIDR7 // Description : Provides CoreSight discovery information for the SCS @@ -6478,7 +6472,7 @@ #define M33_DPIDR7_RESET _u(0x00000000) #define M33_DPIDR7_MSB _u(31) #define M33_DPIDR7_LSB _u(0) -#define M33_DPIDR7_ACCESS "RW" +#define M33_DPIDR7_ACCESS "-" // ============================================================================= // Register : M33_DPIDR0 // Description : Provides CoreSight discovery information for the SCS @@ -7531,7 +7525,7 @@ #define M33_TRCIDR6_RESET _u(0x00000000) #define M33_TRCIDR6_MSB _u(31) #define M33_TRCIDR6_LSB _u(0) -#define M33_TRCIDR6_ACCESS "RW" +#define M33_TRCIDR6_ACCESS "-" // ============================================================================= // Register : M33_TRCIDR7 // Description : TRCIDR7 @@ -7540,7 +7534,7 @@ #define M33_TRCIDR7_RESET _u(0x00000000) #define M33_TRCIDR7_MSB _u(31) #define M33_TRCIDR7_LSB _u(0) -#define M33_TRCIDR7_ACCESS "RW" +#define M33_TRCIDR7_ACCESS "-" // ============================================================================= // Register : M33_TRCRSCTLR2 // Description : The TRCRSCTLR controls the trace resources @@ -7957,7 +7951,7 @@ #define M33_TRCDEVID_RESET _u(0x00000000) #define M33_TRCDEVID_MSB _u(31) #define M33_TRCDEVID_LSB _u(0) -#define M33_TRCDEVID_ACCESS "RW" +#define M33_TRCDEVID_ACCESS "-" // ============================================================================= // Register : M33_TRCDEVTYPE // Description : TRCDEVTYPE @@ -8010,7 +8004,7 @@ #define M33_TRCPIDR5_RESET _u(0x00000000) #define M33_TRCPIDR5_MSB _u(31) #define M33_TRCPIDR5_LSB _u(0) -#define M33_TRCPIDR5_ACCESS "RW" +#define M33_TRCPIDR5_ACCESS "-" // ============================================================================= // Register : M33_TRCPIDR6 // Description : TRCPIDR6 @@ -8019,7 +8013,7 @@ #define M33_TRCPIDR6_RESET _u(0x00000000) #define M33_TRCPIDR6_MSB _u(31) #define M33_TRCPIDR6_LSB _u(0) -#define M33_TRCPIDR6_ACCESS "RW" +#define M33_TRCPIDR6_ACCESS "-" // ============================================================================= // Register : M33_TRCPIDR7 // Description : TRCPIDR7 @@ -8028,7 +8022,7 @@ #define M33_TRCPIDR7_RESET _u(0x00000000) #define M33_TRCPIDR7_MSB _u(31) #define M33_TRCPIDR7_LSB _u(0) -#define M33_TRCPIDR7_ACCESS "RW" +#define M33_TRCPIDR7_ACCESS "-" // ============================================================================= // Register : M33_TRCPIDR0 // Description : TRCPIDR0 @@ -8606,7 +8600,7 @@ #define M33_ASICCTL_RESET _u(0x00000000) #define M33_ASICCTL_MSB _u(31) #define M33_ASICCTL_LSB _u(0) -#define M33_ASICCTL_ACCESS "RW" +#define M33_ASICCTL_ACCESS "-" // ============================================================================= // Register : M33_ITCHOUT // Description : Integration Test Channel Output register @@ -8793,7 +8787,7 @@ #define M33_PIDR5_RESET _u(0x00000000) #define M33_PIDR5_MSB _u(31) #define M33_PIDR5_LSB _u(0) -#define M33_PIDR5_ACCESS "RW" +#define M33_PIDR5_ACCESS "-" // ============================================================================= // Register : M33_PIDR6 // Description : CoreSight Peripheral ID6 @@ -8802,7 +8796,7 @@ #define M33_PIDR6_RESET _u(0x00000000) #define M33_PIDR6_MSB _u(31) #define M33_PIDR6_LSB _u(0) -#define M33_PIDR6_ACCESS "RW" +#define M33_PIDR6_ACCESS "-" // ============================================================================= // Register : M33_PIDR7 // Description : CoreSight Peripheral ID7 @@ -8811,7 +8805,7 @@ #define M33_PIDR7_RESET _u(0x00000000) #define M33_PIDR7_MSB _u(31) #define M33_PIDR7_LSB _u(0) -#define M33_PIDR7_ACCESS "RW" +#define M33_PIDR7_ACCESS "-" // ============================================================================= // Register : M33_PIDR0 // Description : CoreSight Peripheral ID0
diff --git a/src/rp2350/hardware_regs/include/hardware/regs/m33_eppb.h b/src/rp2350/hardware_regs/include/hardware/regs/m33_eppb.h index f7183fe..c7dddf5 100644 --- a/src/rp2350/hardware_regs/include/hardware/regs/m33_eppb.h +++ b/src/rp2350/hardware_regs/include/hardware/regs/m33_eppb.h
@@ -25,8 +25,8 @@ #define M33_EPPB_NMI_MASK0_ACCESS "RW" // ============================================================================= // Register : M33_EPPB_NMI_MASK1 -// Description : NMI mask for IRQs 0 though 51. This register is core-local, and -// is reset by a processor warm reset. +// Description : NMI mask for IRQs 32 though 51. This register is core-local, +// and is reset by a processor warm reset. #define M33_EPPB_NMI_MASK1_OFFSET _u(0x00000004) #define M33_EPPB_NMI_MASK1_BITS _u(0x000fffff) #define M33_EPPB_NMI_MASK1_RESET _u(0x00000000)
diff --git a/src/rp2350/hardware_regs/include/hardware/regs/otp_data.h b/src/rp2350/hardware_regs/include/hardware/regs/otp_data.h index 92a614a..5a1018c 100644 --- a/src/rp2350/hardware_regs/include/hardware/regs/otp_data.h +++ b/src/rp2350/hardware_regs/include/hardware/regs/otp_data.h
@@ -444,7 +444,7 @@ // there are other configurations in OTP that must be valid. // (RBIT-3) #define OTP_DATA_BOOT_FLAGS0_ROW _u(0x00000048) -#define OTP_DATA_BOOT_FLAGS0_BITS _u(0x003fffff) +#define OTP_DATA_BOOT_FLAGS0_BITS _u(0x003ffffe) #define OTP_DATA_BOOT_FLAGS0_RESET _u(0x00000000) #define OTP_DATA_BOOT_FLAGS0_WIDTH _u(24) // ----------------------------------------------------------------------------- @@ -648,13 +648,6 @@ #define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_LED_MSB _u(1) #define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_LED_LSB _u(1) #define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_LED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_EXEC2 -#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_EXEC2_RESET "-" -#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_EXEC2_BITS _u(0x00000001) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_EXEC2_MSB _u(0) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_EXEC2_LSB _u(0) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_EXEC2_ACCESS "RO" // ============================================================================= // Register : OTP_DATA_BOOT_FLAGS0_R1 // Description : Redundant copy of BOOT_FLAGS0 @@ -1447,6 +1440,48 @@ #define OTP_DATA_OTPBOOT_DST1_LSB _u(0) #define OTP_DATA_OTPBOOT_DST1_ACCESS "RO" // ============================================================================= +// Register : OTP_DATA_MAC0 +// Description : Bytes 0 and 1 of MAC address (ECC) +// +// The MAC is stored as bytes in network order, so bits 7:0 of +// this register are the aa in aa:bb:cc:dd:ee:ff, and bits 15:8 +// are the bb. +// +// Multiple interfaces are assigned consecutive addresses from the +// single MAC stored in OTP. +#define OTP_DATA_MAC0_ROW _u(0x00000062) +#define OTP_DATA_MAC0_BITS _u(0x0000ffff) +#define OTP_DATA_MAC0_RESET "-" +#define OTP_DATA_MAC0_MSB _u(15) +#define OTP_DATA_MAC0_LSB _u(0) +#define OTP_DATA_MAC0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_MAC1 +// Description : Bytes 2 and 3 of MAC address (ECC) +// +// The MAC is stored as bytes in network order, so bits 7:0 of +// this register are the cc in aa:bb:cc:dd:ee:ff, and bits 15:8 +// are the dd. +#define OTP_DATA_MAC1_ROW _u(0x00000063) +#define OTP_DATA_MAC1_BITS _u(0x0000ffff) +#define OTP_DATA_MAC1_RESET "-" +#define OTP_DATA_MAC1_MSB _u(15) +#define OTP_DATA_MAC1_LSB _u(0) +#define OTP_DATA_MAC1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_MAC2 +// Description : Bytes 4 and 5 of MAC address (ECC) +// +// The MAC is stored as bytes in network order, so bits 7:0 of +// this register are the ee in aa:bb:cc:dd:ee:ff, and bits 15:8 +// are the ff. +#define OTP_DATA_MAC2_ROW _u(0x00000064) +#define OTP_DATA_MAC2_BITS _u(0x0000ffff) +#define OTP_DATA_MAC2_RESET "-" +#define OTP_DATA_MAC2_MSB _u(15) +#define OTP_DATA_MAC2_LSB _u(0) +#define OTP_DATA_MAC2_ACCESS "RO" +// ============================================================================= // Register : OTP_DATA_BOOTKEY0_0 // Description : Bits 15:0 of SHA-256 hash of boot key 0 (ECC) #define OTP_DATA_BOOTKEY0_0_ROW _u(0x00000080) @@ -2875,7 +2910,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -3025,7 +3061,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -3175,7 +3212,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -3325,7 +3363,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -3475,7 +3514,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -3625,7 +3665,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -3775,7 +3816,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -3925,7 +3967,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -4075,7 +4118,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -4225,7 +4269,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -4375,7 +4420,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -4525,7 +4571,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -4675,7 +4722,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -4825,7 +4873,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -4975,7 +5024,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -5125,7 +5175,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -5275,7 +5326,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -5425,7 +5477,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -5575,7 +5628,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -5725,7 +5779,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -5875,7 +5930,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -6025,7 +6081,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -6175,7 +6232,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -6325,7 +6383,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -6475,7 +6534,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -6625,7 +6685,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -6775,7 +6836,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -6925,7 +6987,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -7075,7 +7138,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -7225,7 +7289,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -7375,7 +7440,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -7525,7 +7591,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -7675,7 +7742,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -7825,7 +7893,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -7975,7 +8044,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -8125,7 +8195,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -8275,7 +8346,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -8425,7 +8497,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -8575,7 +8648,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -8725,7 +8799,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -8875,7 +8950,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -9025,7 +9101,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -9175,7 +9252,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -9325,7 +9403,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -9475,7 +9554,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -9625,7 +9705,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -9775,7 +9856,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -9925,7 +10007,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -10075,7 +10158,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -10225,7 +10309,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -10375,7 +10460,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -10525,7 +10611,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -10675,7 +10762,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -10825,7 +10913,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -10975,7 +11064,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -11125,7 +11215,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -11275,7 +11366,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -11425,7 +11517,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -11575,7 +11668,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -11725,7 +11819,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -11875,7 +11970,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -12025,7 +12121,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -12175,7 +12272,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software. @@ -12335,7 +12433,8 @@ // as the SBPI programming interface is not accessible to Non- // secure software. However, Secure software may check these bits // to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x0 -> Page can be read by Non-secure software, and Secure software +// may permit Non-secure writes. // 0x1 -> Page can be read by Non-secure software // 0x2 -> Do not use. Behaves the same as INACCESSIBLE. // 0x3 -> Page can not be accessed by Non-secure software.
diff --git a/src/rp2350/hardware_regs/include/hardware/regs/pio.h b/src/rp2350/hardware_regs/include/hardware/regs/pio.h index 5ca586e..07d228a 100644 --- a/src/rp2350/hardware_regs/include/hardware/regs/pio.h +++ b/src/rp2350/hardware_regs/include/hardware/regs/pio.h
@@ -941,7 +941,8 @@ // Description : Comparison used for the MOV x, STATUS instruction. // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -// 0x2 -> All-ones if the indexed IRQ flag is raised, otherwise all-zeroes +// 0x2 -> All-ones if the indexed IRQ flag is raised, otherwise all- +// zeroes #define PIO_SM0_EXECCTRL_STATUS_SEL_RESET _u(0x0) #define PIO_SM0_EXECCTRL_STATUS_SEL_BITS _u(0x00000060) #define PIO_SM0_EXECCTRL_STATUS_SEL_MSB _u(6) @@ -1340,7 +1341,8 @@ // Description : Comparison used for the MOV x, STATUS instruction. // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -// 0x2 -> All-ones if the indexed IRQ flag is raised, otherwise all-zeroes +// 0x2 -> All-ones if the indexed IRQ flag is raised, otherwise all- +// zeroes #define PIO_SM1_EXECCTRL_STATUS_SEL_RESET _u(0x0) #define PIO_SM1_EXECCTRL_STATUS_SEL_BITS _u(0x00000060) #define PIO_SM1_EXECCTRL_STATUS_SEL_MSB _u(6) @@ -1739,7 +1741,8 @@ // Description : Comparison used for the MOV x, STATUS instruction. // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -// 0x2 -> All-ones if the indexed IRQ flag is raised, otherwise all-zeroes +// 0x2 -> All-ones if the indexed IRQ flag is raised, otherwise all- +// zeroes #define PIO_SM2_EXECCTRL_STATUS_SEL_RESET _u(0x0) #define PIO_SM2_EXECCTRL_STATUS_SEL_BITS _u(0x00000060) #define PIO_SM2_EXECCTRL_STATUS_SEL_MSB _u(6) @@ -2138,7 +2141,8 @@ // Description : Comparison used for the MOV x, STATUS instruction. // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -// 0x2 -> All-ones if the indexed IRQ flag is raised, otherwise all-zeroes +// 0x2 -> All-ones if the indexed IRQ flag is raised, otherwise all- +// zeroes #define PIO_SM3_EXECCTRL_STATUS_SEL_RESET _u(0x0) #define PIO_SM3_EXECCTRL_STATUS_SEL_BITS _u(0x00000060) #define PIO_SM3_EXECCTRL_STATUS_SEL_MSB _u(6)
diff --git a/src/rp2350/hardware_regs/include/hardware/regs/powman.h b/src/rp2350/hardware_regs/include/hardware/regs/powman.h index dd1df2b..ef3b1c2 100644 --- a/src/rp2350/hardware_regs/include/hardware/regs/powman.h +++ b/src/rp2350/hardware_regs/include/hardware/regs/powman.h
@@ -493,7 +493,7 @@ #define POWMAN_CHIP_RESET_BITS _u(0x1fef0011) #define POWMAN_CHIP_RESET_RESET _u(0x00000000) // ----------------------------------------------------------------------------- -// Field : POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM +// Field : POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_PSM // Description : Last reset was a watchdog timeout which was configured to reset // the power-on state machine // This resets: @@ -506,11 +506,11 @@ // swcore no // psm yes // and does not change the power state -#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_RESET _u(0x0) -#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_BITS _u(0x10000000) -#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_MSB _u(28) -#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_LSB _u(28) -#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_ACCESS "RO" +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_PSM_RESET _u(0x0) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_PSM_BITS _u(0x10000000) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_PSM_MSB _u(28) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_PSM_LSB _u(28) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_PSM_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ // Description : Last reset was a system reset from the hazard debugger @@ -747,25 +747,25 @@ #define POWMAN_WDSEL_BITS _u(0x00001111) #define POWMAN_WDSEL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- -// Field : POWMAN_WDSEL_RESET_RSM +// Field : POWMAN_WDSEL_RESET_PSM // Description : If set to 1, a watchdog reset will run the full power-on state // machine (PSM) sequence // From a user perspective it is the same as setting -// RSM_WDSEL_PROC_COLD +// PSM_WDSEL_PROC_COLD // From a hardware debug perspective it has the same effect as a // reset from a glitch detector -#define POWMAN_WDSEL_RESET_RSM_RESET _u(0x0) -#define POWMAN_WDSEL_RESET_RSM_BITS _u(0x00001000) -#define POWMAN_WDSEL_RESET_RSM_MSB _u(12) -#define POWMAN_WDSEL_RESET_RSM_LSB _u(12) -#define POWMAN_WDSEL_RESET_RSM_ACCESS "RW" +#define POWMAN_WDSEL_RESET_PSM_RESET _u(0x0) +#define POWMAN_WDSEL_RESET_PSM_BITS _u(0x00001000) +#define POWMAN_WDSEL_RESET_PSM_MSB _u(12) +#define POWMAN_WDSEL_RESET_PSM_LSB _u(12) +#define POWMAN_WDSEL_RESET_PSM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : POWMAN_WDSEL_RESET_SWCORE // Description : If set to 1, a watchdog reset will reset the switched core // power domain and run the full power-on state machine (PSM) // sequence // From a user perspective it is the same as setting -// RSM_WDSEL_PROC_COLD +// PSM_WDSEL_PROC_COLD // From a hardware debug perspective it has the same effect as a // power-on reset for the switched core power domain #define POWMAN_WDSEL_RESET_SWCORE_RESET _u(0x0) @@ -1185,10 +1185,10 @@ #define POWMAN_EXT_TIME_REF_DRIVE_LPCK_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : POWMAN_EXT_TIME_REF_SOURCE_SEL -// Description : 0 -> gpio12 -// 1 -> gpio20 -// 2 -> gpio14 -// 3 -> gpio22 +// 0x0 -> gpio12 +// 0x1 -> gpio20 +// 0x2 -> gpio14 +// 0x3 -> gpio22 #define POWMAN_EXT_TIME_REF_SOURCE_SEL_RESET _u(0x0) #define POWMAN_EXT_TIME_REF_SOURCE_SEL_BITS _u(0x00000003) #define POWMAN_EXT_TIME_REF_SOURCE_SEL_MSB _u(1) @@ -1875,7 +1875,7 @@ // ============================================================================= // Register : POWMAN_BOOTDIS // Description : Tell the bootrom to ignore the BOOT0..3 registers following the -// next RSM reset (e.g. the next core power down/up). +// next PSM reset (e.g. the next core power down/up). // // If an early boot stage has soft-locked some OTP pages in order // to protect their contents from later stages, there is a risk @@ -1898,7 +1898,7 @@ // The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the // core is powered down. Simultaneously, the BOOTDIS_NEXT bit is // cleared. Setting this bit means that the BOOT0..3 registers -// will be ignored following the next reset of the RSM by powman. +// will be ignored following the next reset of the PSM by powman. // // This flag should be set by an early boot stage that has soft- // locked OTP pages, to prevent later stages from unlocking it by @@ -1910,7 +1910,7 @@ #define POWMAN_BOOTDIS_NEXT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : POWMAN_BOOTDIS_NOW -// Description : When powman resets the RSM, the current value of BOOTDIS_NEXT +// Description : When powman resets the PSM, the current value of BOOTDIS_NEXT // is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. // // The bootrom checks this flag before reading the BOOT0..3
diff --git a/src/rp2350/hardware_regs/include/hardware/regs/pwm.h b/src/rp2350/hardware_regs/include/hardware/regs/pwm.h index dd18758..1fe5cb7 100644 --- a/src/rp2350/hardware_regs/include/hardware/regs/pwm.h +++ b/src/rp2350/hardware_regs/include/hardware/regs/pwm.h
@@ -30,7 +30,7 @@ #define PWM_CH0_CSR_PH_ADV_BITS _u(0x00000080) #define PWM_CH0_CSR_PH_ADV_MSB _u(7) #define PWM_CH0_CSR_PH_ADV_LSB _u(7) -#define PWM_CH0_CSR_PH_ADV_ACCESS "SC" +#define PWM_CH0_CSR_PH_ADV_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH0_CSR_PH_RET // Description : Retard the phase of the counter by 1 count, while it is @@ -41,7 +41,7 @@ #define PWM_CH0_CSR_PH_RET_BITS _u(0x00000040) #define PWM_CH0_CSR_PH_RET_MSB _u(6) #define PWM_CH0_CSR_PH_RET_LSB _u(6) -#define PWM_CH0_CSR_PH_RET_ACCESS "SC" +#define PWM_CH0_CSR_PH_RET_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH0_CSR_DIVMODE // 0x0 -> Free-running counting at rate dictated by fractional divider @@ -166,7 +166,7 @@ #define PWM_CH1_CSR_PH_ADV_BITS _u(0x00000080) #define PWM_CH1_CSR_PH_ADV_MSB _u(7) #define PWM_CH1_CSR_PH_ADV_LSB _u(7) -#define PWM_CH1_CSR_PH_ADV_ACCESS "SC" +#define PWM_CH1_CSR_PH_ADV_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH1_CSR_PH_RET // Description : Retard the phase of the counter by 1 count, while it is @@ -177,7 +177,7 @@ #define PWM_CH1_CSR_PH_RET_BITS _u(0x00000040) #define PWM_CH1_CSR_PH_RET_MSB _u(6) #define PWM_CH1_CSR_PH_RET_LSB _u(6) -#define PWM_CH1_CSR_PH_RET_ACCESS "SC" +#define PWM_CH1_CSR_PH_RET_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH1_CSR_DIVMODE // 0x0 -> Free-running counting at rate dictated by fractional divider @@ -302,7 +302,7 @@ #define PWM_CH2_CSR_PH_ADV_BITS _u(0x00000080) #define PWM_CH2_CSR_PH_ADV_MSB _u(7) #define PWM_CH2_CSR_PH_ADV_LSB _u(7) -#define PWM_CH2_CSR_PH_ADV_ACCESS "SC" +#define PWM_CH2_CSR_PH_ADV_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH2_CSR_PH_RET // Description : Retard the phase of the counter by 1 count, while it is @@ -313,7 +313,7 @@ #define PWM_CH2_CSR_PH_RET_BITS _u(0x00000040) #define PWM_CH2_CSR_PH_RET_MSB _u(6) #define PWM_CH2_CSR_PH_RET_LSB _u(6) -#define PWM_CH2_CSR_PH_RET_ACCESS "SC" +#define PWM_CH2_CSR_PH_RET_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH2_CSR_DIVMODE // 0x0 -> Free-running counting at rate dictated by fractional divider @@ -438,7 +438,7 @@ #define PWM_CH3_CSR_PH_ADV_BITS _u(0x00000080) #define PWM_CH3_CSR_PH_ADV_MSB _u(7) #define PWM_CH3_CSR_PH_ADV_LSB _u(7) -#define PWM_CH3_CSR_PH_ADV_ACCESS "SC" +#define PWM_CH3_CSR_PH_ADV_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH3_CSR_PH_RET // Description : Retard the phase of the counter by 1 count, while it is @@ -449,7 +449,7 @@ #define PWM_CH3_CSR_PH_RET_BITS _u(0x00000040) #define PWM_CH3_CSR_PH_RET_MSB _u(6) #define PWM_CH3_CSR_PH_RET_LSB _u(6) -#define PWM_CH3_CSR_PH_RET_ACCESS "SC" +#define PWM_CH3_CSR_PH_RET_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH3_CSR_DIVMODE // 0x0 -> Free-running counting at rate dictated by fractional divider @@ -574,7 +574,7 @@ #define PWM_CH4_CSR_PH_ADV_BITS _u(0x00000080) #define PWM_CH4_CSR_PH_ADV_MSB _u(7) #define PWM_CH4_CSR_PH_ADV_LSB _u(7) -#define PWM_CH4_CSR_PH_ADV_ACCESS "SC" +#define PWM_CH4_CSR_PH_ADV_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH4_CSR_PH_RET // Description : Retard the phase of the counter by 1 count, while it is @@ -585,7 +585,7 @@ #define PWM_CH4_CSR_PH_RET_BITS _u(0x00000040) #define PWM_CH4_CSR_PH_RET_MSB _u(6) #define PWM_CH4_CSR_PH_RET_LSB _u(6) -#define PWM_CH4_CSR_PH_RET_ACCESS "SC" +#define PWM_CH4_CSR_PH_RET_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH4_CSR_DIVMODE // 0x0 -> Free-running counting at rate dictated by fractional divider @@ -710,7 +710,7 @@ #define PWM_CH5_CSR_PH_ADV_BITS _u(0x00000080) #define PWM_CH5_CSR_PH_ADV_MSB _u(7) #define PWM_CH5_CSR_PH_ADV_LSB _u(7) -#define PWM_CH5_CSR_PH_ADV_ACCESS "SC" +#define PWM_CH5_CSR_PH_ADV_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH5_CSR_PH_RET // Description : Retard the phase of the counter by 1 count, while it is @@ -721,7 +721,7 @@ #define PWM_CH5_CSR_PH_RET_BITS _u(0x00000040) #define PWM_CH5_CSR_PH_RET_MSB _u(6) #define PWM_CH5_CSR_PH_RET_LSB _u(6) -#define PWM_CH5_CSR_PH_RET_ACCESS "SC" +#define PWM_CH5_CSR_PH_RET_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH5_CSR_DIVMODE // 0x0 -> Free-running counting at rate dictated by fractional divider @@ -846,7 +846,7 @@ #define PWM_CH6_CSR_PH_ADV_BITS _u(0x00000080) #define PWM_CH6_CSR_PH_ADV_MSB _u(7) #define PWM_CH6_CSR_PH_ADV_LSB _u(7) -#define PWM_CH6_CSR_PH_ADV_ACCESS "SC" +#define PWM_CH6_CSR_PH_ADV_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH6_CSR_PH_RET // Description : Retard the phase of the counter by 1 count, while it is @@ -857,7 +857,7 @@ #define PWM_CH6_CSR_PH_RET_BITS _u(0x00000040) #define PWM_CH6_CSR_PH_RET_MSB _u(6) #define PWM_CH6_CSR_PH_RET_LSB _u(6) -#define PWM_CH6_CSR_PH_RET_ACCESS "SC" +#define PWM_CH6_CSR_PH_RET_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH6_CSR_DIVMODE // 0x0 -> Free-running counting at rate dictated by fractional divider @@ -982,7 +982,7 @@ #define PWM_CH7_CSR_PH_ADV_BITS _u(0x00000080) #define PWM_CH7_CSR_PH_ADV_MSB _u(7) #define PWM_CH7_CSR_PH_ADV_LSB _u(7) -#define PWM_CH7_CSR_PH_ADV_ACCESS "SC" +#define PWM_CH7_CSR_PH_ADV_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH7_CSR_PH_RET // Description : Retard the phase of the counter by 1 count, while it is @@ -993,7 +993,7 @@ #define PWM_CH7_CSR_PH_RET_BITS _u(0x00000040) #define PWM_CH7_CSR_PH_RET_MSB _u(6) #define PWM_CH7_CSR_PH_RET_LSB _u(6) -#define PWM_CH7_CSR_PH_RET_ACCESS "SC" +#define PWM_CH7_CSR_PH_RET_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH7_CSR_DIVMODE // 0x0 -> Free-running counting at rate dictated by fractional divider @@ -1118,7 +1118,7 @@ #define PWM_CH8_CSR_PH_ADV_BITS _u(0x00000080) #define PWM_CH8_CSR_PH_ADV_MSB _u(7) #define PWM_CH8_CSR_PH_ADV_LSB _u(7) -#define PWM_CH8_CSR_PH_ADV_ACCESS "SC" +#define PWM_CH8_CSR_PH_ADV_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH8_CSR_PH_RET // Description : Retard the phase of the counter by 1 count, while it is @@ -1129,7 +1129,7 @@ #define PWM_CH8_CSR_PH_RET_BITS _u(0x00000040) #define PWM_CH8_CSR_PH_RET_MSB _u(6) #define PWM_CH8_CSR_PH_RET_LSB _u(6) -#define PWM_CH8_CSR_PH_RET_ACCESS "SC" +#define PWM_CH8_CSR_PH_RET_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH8_CSR_DIVMODE // 0x0 -> Free-running counting at rate dictated by fractional divider @@ -1254,7 +1254,7 @@ #define PWM_CH9_CSR_PH_ADV_BITS _u(0x00000080) #define PWM_CH9_CSR_PH_ADV_MSB _u(7) #define PWM_CH9_CSR_PH_ADV_LSB _u(7) -#define PWM_CH9_CSR_PH_ADV_ACCESS "SC" +#define PWM_CH9_CSR_PH_ADV_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH9_CSR_PH_RET // Description : Retard the phase of the counter by 1 count, while it is @@ -1265,7 +1265,7 @@ #define PWM_CH9_CSR_PH_RET_BITS _u(0x00000040) #define PWM_CH9_CSR_PH_RET_MSB _u(6) #define PWM_CH9_CSR_PH_RET_LSB _u(6) -#define PWM_CH9_CSR_PH_RET_ACCESS "SC" +#define PWM_CH9_CSR_PH_RET_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH9_CSR_DIVMODE // 0x0 -> Free-running counting at rate dictated by fractional divider @@ -1390,7 +1390,7 @@ #define PWM_CH10_CSR_PH_ADV_BITS _u(0x00000080) #define PWM_CH10_CSR_PH_ADV_MSB _u(7) #define PWM_CH10_CSR_PH_ADV_LSB _u(7) -#define PWM_CH10_CSR_PH_ADV_ACCESS "SC" +#define PWM_CH10_CSR_PH_ADV_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH10_CSR_PH_RET // Description : Retard the phase of the counter by 1 count, while it is @@ -1401,7 +1401,7 @@ #define PWM_CH10_CSR_PH_RET_BITS _u(0x00000040) #define PWM_CH10_CSR_PH_RET_MSB _u(6) #define PWM_CH10_CSR_PH_RET_LSB _u(6) -#define PWM_CH10_CSR_PH_RET_ACCESS "SC" +#define PWM_CH10_CSR_PH_RET_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH10_CSR_DIVMODE // 0x0 -> Free-running counting at rate dictated by fractional divider @@ -1526,7 +1526,7 @@ #define PWM_CH11_CSR_PH_ADV_BITS _u(0x00000080) #define PWM_CH11_CSR_PH_ADV_MSB _u(7) #define PWM_CH11_CSR_PH_ADV_LSB _u(7) -#define PWM_CH11_CSR_PH_ADV_ACCESS "SC" +#define PWM_CH11_CSR_PH_ADV_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH11_CSR_PH_RET // Description : Retard the phase of the counter by 1 count, while it is @@ -1537,7 +1537,7 @@ #define PWM_CH11_CSR_PH_RET_BITS _u(0x00000040) #define PWM_CH11_CSR_PH_RET_MSB _u(6) #define PWM_CH11_CSR_PH_RET_LSB _u(6) -#define PWM_CH11_CSR_PH_RET_ACCESS "SC" +#define PWM_CH11_CSR_PH_RET_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_CH11_CSR_DIVMODE // 0x0 -> Free-running counting at rate dictated by fractional divider
diff --git a/src/rp2350/hardware_regs/include/hardware/regs/rvcsr.h b/src/rp2350/hardware_regs/include/hardware/regs/rvcsr.h index 9ae514d..e24978d 100644 --- a/src/rp2350/hardware_regs/include/hardware/regs/rvcsr.h +++ b/src/rp2350/hardware_regs/include/hardware/regs/rvcsr.h
@@ -727,14 +727,25 @@ // mip that caused the trap (3=soft IRQ, 7=timer IRQ, 11=external // IRQ). Otherwise, `code` is set according to the cause of the // exception. -// 0x0 -> Instruction fetch was misaligned. Will never fire on RP2350, since the C extension is enabled. -// 0x1 -> Instruction access fault. Instruction fetch failed a PMP check, or encountered a downstream bus fault, and then passed the point of no speculation. -// 0x2 -> Illegal instruction was executed (including illegal CSR accesses) -// 0x3 -> Breakpoint. An ebreak instruction was executed when the relevant dcsr.ebreak bit was clear. -// 0x4 -> Load address misaligned. Hazard3 requires natural alignment of all accesses. -// 0x5 -> Load access fault. A load failed a PMP check, or encountered a downstream bus error. -// 0x6 -> Store/AMO address misaligned. Hazard3 requires natural alignment of all accesses. -// 0x7 -> Store/AMO access fault. A store/AMO failed a PMP check, or encountered a downstream bus error. Also set if an AMO is attempted on a region that does not support atomics (on RP2350, anything but SRAM). +// 0x0 -> Instruction fetch was misaligned. Will never fire on RP2350, +// since the C extension is enabled. +// 0x1 -> Instruction access fault. Instruction fetch failed a PMP check, +// or encountered a downstream bus fault, and then passed the +// point of no speculation. +// 0x2 -> Illegal instruction was executed (including illegal CSR +// accesses) +// 0x3 -> Breakpoint. An ebreak instruction was executed when the +// relevant dcsr.ebreak bit was clear. +// 0x4 -> Load address misaligned. Hazard3 requires natural alignment of +// all accesses. +// 0x5 -> Load access fault. A load failed a PMP check, or encountered a +// downstream bus error. +// 0x6 -> Store/AMO address misaligned. Hazard3 requires natural +// alignment of all accesses. +// 0x7 -> Store/AMO access fault. A store/AMO failed a PMP check, or +// encountered a downstream bus error. Also set if an AMO is +// attempted on a region that does not support atomics (on RP2350, +// anything but SRAM). // 0x8 -> Environment call from U-mode. // 0xb -> Environment call from M-mode. #define RVCSR_MCAUSE_CODE_RESET _u(0x0) @@ -1903,8 +1914,10 @@ // ----------------------------------------------------------------------------- // Field : RVCSR_TDATA1_ACTION // Description : Select action to be taken when the trigger fires. -// 0x0 -> Raise a breakpoint exception, which can be handled by the M-mode exception handler -// 0x1 -> Enter debug mode. This action is only selectable when `tdata1.dmode` is 1. +// 0x0 -> Raise a breakpoint exception, which can be handled by the +// M-mode exception handler +// 0x1 -> Enter debug mode. This action is only selectable when +// `tdata1.dmode` is 1. #define RVCSR_TDATA1_ACTION_RESET _u(0x0) #define RVCSR_TDATA1_ACTION_BITS _u(0x0000f000) #define RVCSR_TDATA1_ACTION_MSB _u(15) @@ -2049,10 +2062,13 @@ // ----------------------------------------------------------------------------- // Field : RVCSR_DCSR_CAUSE // Description : Set by hardware when entering debug mode. -// 0x1 -> An ebreak instruction was executed when the relevant `dcsr.ebreakx` bit was set. +// 0x1 -> An ebreak instruction was executed when the relevant +// `dcsr.ebreakx` bit was set. // 0x2 -> The trigger module caused a breakpoint exception. -// 0x3 -> Processor entered Debug Mode due to a halt request, or a reset-halt request present when the core reset was released. -// 0x4 -> Processor entered Debug Mode after executing one instruction with single-stepping enabled. +// 0x3 -> Processor entered Debug Mode due to a halt request, or a reset- +// halt request present when the core reset was released. +// 0x4 -> Processor entered Debug Mode after executing one instruction +// with single-stepping enabled. #define RVCSR_DCSR_CAUSE_RESET _u(0x0) #define RVCSR_DCSR_CAUSE_BITS _u(0x000001c0) #define RVCSR_DCSR_CAUSE_MSB _u(8) @@ -3153,7 +3169,7 @@ // Description : Vendor ID #define RVCSR_MVENDORID_OFFSET _u(0x00000f11) #define RVCSR_MVENDORID_BITS _u(0xffffffff) -#define RVCSR_MVENDORID_RESET _u(0x00000000) +#define RVCSR_MVENDORID_RESET _u(0x00000493) // ----------------------------------------------------------------------------- // Field : RVCSR_MVENDORID_BANK // Description : Value of 9 indicates 9 continuation codes, which is JEP106 bank
diff --git a/src/rp2350/hardware_regs/include/hardware/regs/sio.h b/src/rp2350/hardware_regs/include/hardware/regs/sio.h index b2334bf..8020ff4 100644 --- a/src/rp2350/hardware_regs/include/hardware/regs/sio.h +++ b/src/rp2350/hardware_regs/include/hardware/regs/sio.h
@@ -2132,9 +2132,9 @@ #define SIO_MTIME_CTRL_EN_ACCESS "RW" // ============================================================================= // Register : SIO_MTIME -// Description : Read/write access to the high half of RISC-V Machine-mode -// timer. This register is shared between both cores. If both -// cores write on the same cycle, core 1 takes precedence. +// Description : Read/write access to the low half of RISC-V Machine-mode timer. +// This register is shared between both cores. If both cores write +// on the same cycle, core 1 takes precedence. #define SIO_MTIME_OFFSET _u(0x000001b0) #define SIO_MTIME_BITS _u(0xffffffff) #define SIO_MTIME_RESET _u(0x00000000)
diff --git a/src/rp2350/hardware_regs/include/hardware/regs/sysinfo.h b/src/rp2350/hardware_regs/include/hardware/regs/sysinfo.h index a7198a5..924c131 100644 --- a/src/rp2350/hardware_regs/include/hardware/regs/sysinfo.h +++ b/src/rp2350/hardware_regs/include/hardware/regs/sysinfo.h
@@ -17,24 +17,24 @@ // Description : JEDEC JEP-106 compliant chip identifier. #define SYSINFO_CHIP_ID_OFFSET _u(0x00000000) #define SYSINFO_CHIP_ID_BITS _u(0xffffffff) -#define SYSINFO_CHIP_ID_RESET _u(0x00000001) +#define SYSINFO_CHIP_ID_RESET _u(0x30004927) // ----------------------------------------------------------------------------- // Field : SYSINFO_CHIP_ID_REVISION -#define SYSINFO_CHIP_ID_REVISION_RESET "-" +#define SYSINFO_CHIP_ID_REVISION_RESET _u(0x3) #define SYSINFO_CHIP_ID_REVISION_BITS _u(0xf0000000) #define SYSINFO_CHIP_ID_REVISION_MSB _u(31) #define SYSINFO_CHIP_ID_REVISION_LSB _u(28) #define SYSINFO_CHIP_ID_REVISION_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SYSINFO_CHIP_ID_PART -#define SYSINFO_CHIP_ID_PART_RESET "-" +#define SYSINFO_CHIP_ID_PART_RESET _u(0x0004) #define SYSINFO_CHIP_ID_PART_BITS _u(0x0ffff000) #define SYSINFO_CHIP_ID_PART_MSB _u(27) #define SYSINFO_CHIP_ID_PART_LSB _u(12) #define SYSINFO_CHIP_ID_PART_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SYSINFO_CHIP_ID_MANUFACTURER -#define SYSINFO_CHIP_ID_MANUFACTURER_RESET "-" +#define SYSINFO_CHIP_ID_MANUFACTURER_RESET _u(0x493) #define SYSINFO_CHIP_ID_MANUFACTURER_BITS _u(0x00000ffe) #define SYSINFO_CHIP_ID_MANUFACTURER_MSB _u(11) #define SYSINFO_CHIP_ID_MANUFACTURER_LSB _u(1) @@ -48,6 +48,7 @@ #define SYSINFO_CHIP_ID_STOP_BIT_ACCESS "RO" // ============================================================================= // Register : SYSINFO_PACKAGE_SEL +// Description : Package selection indicator, 0 = QFN80, 1 = QFN60 #define SYSINFO_PACKAGE_SEL_OFFSET _u(0x00000004) #define SYSINFO_PACKAGE_SEL_BITS _u(0x00000001) #define SYSINFO_PACKAGE_SEL_RESET _u(0x00000000)
diff --git a/src/rp2350/hardware_regs/include/hardware/regs/tbman.h b/src/rp2350/hardware_regs/include/hardware/regs/tbman.h index 5b6b8a1..a09eb01 100644 --- a/src/rp2350/hardware_regs/include/hardware/regs/tbman.h +++ b/src/rp2350/hardware_regs/include/hardware/regs/tbman.h
@@ -9,7 +9,8 @@ // Register block : TBMAN // Version : 1 // Bus type : apb -// Description : For managing simulation testbenches +// Description : Testbench manager. Allows the programmer to know what +// platform their software is running on. // ============================================================================= #ifndef _HARDWARE_REGS_TBMAN_H #define _HARDWARE_REGS_TBMAN_H
diff --git a/src/rp2350/hardware_regs/include/hardware/regs/timer.h b/src/rp2350/hardware_regs/include/hardware/regs/timer.h index 04e1802..4a13fbf 100644 --- a/src/rp2350/hardware_regs/include/hardware/regs/timer.h +++ b/src/rp2350/hardware_regs/include/hardware/regs/timer.h
@@ -10,27 +10,29 @@ // Version : 1 // Bus type : apb // Description : Controls time and alarms -// // time is a 64 bit value indicating the time since power-on -// // timeh is the top 32 bits of time & timel is the bottom 32 -// bits to change time write to timelw before timehw to read -// time read from timelr before timehr -// +// bits +// to change time write to timelw before timehw +// to read time read from timelr before timehr // An alarm is set by setting alarm_enable and writing to the -// corresponding alarm register When an alarm is pending, the -// corresponding alarm_running signal will be high An alarm can -// be cancelled before it has finished by clearing the -// alarm_enable When an alarm fires, the corresponding -// alarm_irq is set and alarm_running is cleared To clear the -// interrupt write a 1 to the corresponding alarm_irq The timer -// can be locked to prevent writing +// corresponding alarm register +// When an alarm is pending, the corresponding alarm_running +// signal will be high +// An alarm can be cancelled before it has finished by clearing +// the alarm_enable +// When an alarm fires, the corresponding alarm_irq is set and +// alarm_running is cleared +// To clear the interrupt write a 1 to the corresponding +// alarm_irq +// The timer can be locked to prevent writing // ============================================================================= #ifndef _HARDWARE_REGS_TIMER_H #define _HARDWARE_REGS_TIMER_H // ============================================================================= // Register : TIMER_TIMEHW -// Description : Write to bits 63:32 of time always write timelw before timehw +// Description : Write to bits 63:32 of time +// always write timelw before timehw #define TIMER_TIMEHW_OFFSET _u(0x00000000) #define TIMER_TIMEHW_BITS _u(0xffffffff) #define TIMER_TIMEHW_RESET _u(0x00000000) @@ -39,8 +41,8 @@ #define TIMER_TIMEHW_ACCESS "WF" // ============================================================================= // Register : TIMER_TIMELW -// Description : Write to bits 31:0 of time writes do not get copied to time -// until timehw is written +// Description : Write to bits 31:0 of time +// writes do not get copied to time until timehw is written #define TIMER_TIMELW_OFFSET _u(0x00000004) #define TIMER_TIMELW_BITS _u(0xffffffff) #define TIMER_TIMELW_RESET _u(0x00000000) @@ -49,7 +51,8 @@ #define TIMER_TIMELW_ACCESS "WF" // ============================================================================= // Register : TIMER_TIMEHR -// Description : Read from bits 63:32 of time always read timelr before timehr +// Description : Read from bits 63:32 of time +// always read timelr before timehr #define TIMER_TIMEHR_OFFSET _u(0x00000008) #define TIMER_TIMEHR_BITS _u(0xffffffff) #define TIMER_TIMEHR_RESET _u(0x00000000) @@ -67,10 +70,10 @@ #define TIMER_TIMELR_ACCESS "RO" // ============================================================================= // Register : TIMER_ALARM0 -// Description : Arm alarm 0, and configure the time it will fire. Once armed, -// the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will -// disarm itself once it fires, and can be disarmed early using -// the ARMED status register. +// Description : Arm alarm 0, and configure the time it will fire. +// Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. +// The alarm will disarm itself once it fires, and can +// be disarmed early using the ARMED status register. #define TIMER_ALARM0_OFFSET _u(0x00000010) #define TIMER_ALARM0_BITS _u(0xffffffff) #define TIMER_ALARM0_RESET _u(0x00000000) @@ -79,10 +82,10 @@ #define TIMER_ALARM0_ACCESS "RW" // ============================================================================= // Register : TIMER_ALARM1 -// Description : Arm alarm 1, and configure the time it will fire. Once armed, -// the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will -// disarm itself once it fires, and can be disarmed early using -// the ARMED status register. +// Description : Arm alarm 1, and configure the time it will fire. +// Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. +// The alarm will disarm itself once it fires, and can +// be disarmed early using the ARMED status register. #define TIMER_ALARM1_OFFSET _u(0x00000014) #define TIMER_ALARM1_BITS _u(0xffffffff) #define TIMER_ALARM1_RESET _u(0x00000000) @@ -91,10 +94,10 @@ #define TIMER_ALARM1_ACCESS "RW" // ============================================================================= // Register : TIMER_ALARM2 -// Description : Arm alarm 2, and configure the time it will fire. Once armed, -// the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will -// disarm itself once it fires, and can be disarmed early using -// the ARMED status register. +// Description : Arm alarm 2, and configure the time it will fire. +// Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. +// The alarm will disarm itself once it fires, and can +// be disarmed early using the ARMED status register. #define TIMER_ALARM2_OFFSET _u(0x00000018) #define TIMER_ALARM2_BITS _u(0xffffffff) #define TIMER_ALARM2_RESET _u(0x00000000) @@ -103,10 +106,10 @@ #define TIMER_ALARM2_ACCESS "RW" // ============================================================================= // Register : TIMER_ALARM3 -// Description : Arm alarm 3, and configure the time it will fire. Once armed, -// the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will -// disarm itself once it fires, and can be disarmed early using -// the ARMED status register. +// Description : Arm alarm 3, and configure the time it will fire. +// Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. +// The alarm will disarm itself once it fires, and can +// be disarmed early using the ARMED status register. #define TIMER_ALARM3_OFFSET _u(0x0000001c) #define TIMER_ALARM3_BITS _u(0xffffffff) #define TIMER_ALARM3_RESET _u(0x00000000) @@ -115,10 +118,10 @@ #define TIMER_ALARM3_ACCESS "RW" // ============================================================================= // Register : TIMER_ARMED -// Description : Indicates the armed/disarmed status of each alarm. A write to -// the corresponding ALARMx register arms the alarm. Alarms -// automatically disarm upon firing, but writing ones here will -// disarm immediately without waiting to fire. +// Description : Indicates the armed/disarmed status of each alarm. +// A write to the corresponding ALARMx register arms the alarm. +// Alarms automatically disarm upon firing, but writing ones here +// will disarm immediately without waiting to fire. #define TIMER_ARMED_OFFSET _u(0x00000020) #define TIMER_ARMED_BITS _u(0x0000000f) #define TIMER_ARMED_RESET _u(0x00000000) @@ -177,8 +180,8 @@ #define TIMER_PAUSE_ACCESS "RW" // ============================================================================= // Register : TIMER_LOCKED -// Description : Set locked bit to disable write access to timer Once set, -// cannot be cleared (without a reset) +// Description : Set locked bit to disable write access to timer +// Once set, cannot be cleared (without a reset) #define TIMER_LOCKED_OFFSET _u(0x00000034) #define TIMER_LOCKED_BITS _u(0x00000001) #define TIMER_LOCKED_RESET _u(0x00000000)
diff --git a/src/rp2350/hardware_regs/include/hardware/regs/xosc.h b/src/rp2350/hardware_regs/include/hardware/regs/xosc.h index aa7cfc3..1393058 100644 --- a/src/rp2350/hardware_regs/include/hardware/regs/xosc.h +++ b/src/rp2350/hardware_regs/include/hardware/regs/xosc.h
@@ -113,9 +113,9 @@ // This is used to save power by pausing the XOSC // On power-up this field is initialised to WAKE // An invalid write will also select WAKE -// Warning: stop the PLLs before selecting dormant mode -// Warning: setup the irq before selecting dormant mode -// 0x636f6d61 -> dormant +// WARNING: stop the PLLs before selecting dormant mode +// WARNING: setup the irq before selecting dormant mode +// 0x636f6d61 -> DORMANT // 0x77616b65 -> WAKE #define XOSC_DORMANT_OFFSET _u(0x00000008) #define XOSC_DORMANT_BITS _u(0xffffffff) @@ -136,7 +136,7 @@ // Description : Multiplies the startup_delay by 4, just in case. The reset // value is controlled by a mask-programmable tiecell and is // provided in case we are booting from XOSC and the default -// startup delay is insufficient. The reset value is 0x0. +// startup delay is insufficient #define XOSC_STARTUP_X4_RESET "-" #define XOSC_STARTUP_X4_BITS _u(0x00100000) #define XOSC_STARTUP_X4_MSB _u(20)
diff --git a/src/rp2350/hardware_structs/include/hardware/structs/accessctrl.h b/src/rp2350/hardware_structs/include/hardware/structs/accessctrl.h index ba39ecf..14e611d 100644 --- a/src/rp2350/hardware_structs/include/hardware/structs/accessctrl.h +++ b/src/rp2350/hardware_structs/include/hardware/structs/accessctrl.h
@@ -219,17 +219,17 @@ // 0x00000001 [0] NSU (0) If 1, and NSP is also set, BUSCTRL can be accessed from... io_rw_32 busctrl; - _REG_(ACCESSCTRL_ADC0_OFFSET) // ACCESSCTRL_ADC0 - // Control access to ADC0. Defaults to Secure access from any master. - // 0x00000080 [7] DBG (1) If 1, ADC0 can be accessed by the debugger, at... - // 0x00000040 [6] DMA (1) If 1, ADC0 can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, ADC0 can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, ADC0 can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, ADC0 can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (1) If 1, and SP is also set, ADC0 can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, ADC0 can be accessed from a Non-secure, Privileged context - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, ADC0 can be accessed from a... - io_rw_32 adc0; + _REG_(ACCESSCTRL_ADC_OFFSET) // ACCESSCTRL_ADC + // Control access to ADC. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, ADC can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, ADC can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, ADC can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, ADC can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, ADC can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, ADC can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, ADC can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, ADC can be accessed from a... + io_rw_32 adc; _REG_(ACCESSCTRL_HSTX_OFFSET) // ACCESSCTRL_HSTX // Control access to HSTX. Defaults to Secure access from any master. @@ -463,17 +463,17 @@ // 0x00000001 [0] NSU (0) If 1, and NSP is also set, WATCHDOG can be accessed from... io_rw_32 watchdog; - _REG_(ACCESSCTRL_RSM_OFFSET) // ACCESSCTRL_RSM - // Control access to RSM. Defaults to Secure, Privileged processor or debug access only. - // 0x00000080 [7] DBG (1) If 1, RSM can be accessed by the debugger, at... - // 0x00000040 [6] DMA (0) If 1, RSM can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, RSM can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, RSM can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, RSM can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (0) If 1, and SP is also set, RSM can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, RSM can be accessed from a Non-secure, Privileged context - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, RSM can be accessed from a... - io_rw_32 rsm; + _REG_(ACCESSCTRL_PSM_OFFSET) // ACCESSCTRL_PSM + // Control access to PSM. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, PSM can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, PSM can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, PSM can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, PSM can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, PSM can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, PSM can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, PSM can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PSM can be accessed from a... + io_rw_32 psm; _REG_(ACCESSCTRL_XIP_CTRL_OFFSET) // ACCESSCTRL_XIP_CTRL // Control access to XIP_CTRL. Defaults to Secure, Privileged processor or debug access only.
diff --git a/src/rp2350/hardware_structs/include/hardware/structs/clocks.h b/src/rp2350/hardware_structs/include/hardware/structs/clocks.h index 3c21f63..eaf6b2f 100644 --- a/src/rp2350/hardware_structs/include/hardware/structs/clocks.h +++ b/src/rp2350/hardware_structs/include/hardware/structs/clocks.h
@@ -22,7 +22,6 @@ // // Bit-field descriptions are of the form: // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - /** \brief Clock numbers on RP2350 (used as typedef \ref clock_num_t) * \ingroup hardware_clocks */ @@ -223,7 +222,7 @@ struct { _REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0 // enable clock in wake mode - // 0x80000000 [31] CLK_SYS_SIOB (1) + // 0x80000000 [31] CLK_SYS_SIO (1) // 0x40000000 [30] CLK_SYS_SHA256 (1) // 0x20000000 [29] CLK_SYS_RSM (1) // 0x10000000 [28] CLK_SYS_ROSC (1) @@ -334,7 +333,7 @@ struct { _REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0 // enable clock in sleep mode - // 0x80000000 [31] CLK_SYS_SIOB (1) + // 0x80000000 [31] CLK_SYS_SIO (1) // 0x40000000 [30] CLK_SYS_SHA256 (1) // 0x20000000 [29] CLK_SYS_RSM (1) // 0x10000000 [28] CLK_SYS_ROSC (1) @@ -445,7 +444,7 @@ struct { _REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0 // indicates the state of the clock enable - // 0x80000000 [31] CLK_SYS_SIOB (0) + // 0x80000000 [31] CLK_SYS_SIO (0) // 0x40000000 [30] CLK_SYS_SHA256 (0) // 0x20000000 [29] CLK_SYS_RSM (0) // 0x10000000 [28] CLK_SYS_ROSC (0)
diff --git a/src/rp2350/hardware_structs/include/hardware/structs/dma.h b/src/rp2350/hardware_structs/include/hardware/structs/dma.h index 221b346..62bdf88 100644 --- a/src/rp2350/hardware_structs/include/hardware/structs/dma.h +++ b/src/rp2350/hardware_structs/include/hardware/structs/dma.h
@@ -279,7 +279,7 @@ _REG_(DMA_CHAN_ABORT_OFFSET) // DMA_CHAN_ABORT // Abort an in-progress transfer sequence on one or more channels // 0x0000ffff [15:0] CHAN_ABORT (0x0000) Each bit corresponds to a channel - io_wo_32 abort; + io_rw_32 abort; _REG_(DMA_N_CHANNELS_OFFSET) // DMA_N_CHANNELS // The number of channels this DMA instance is equipped with
diff --git a/src/rp2350/hardware_structs/include/hardware/structs/m33.h b/src/rp2350/hardware_structs/include/hardware/structs/m33.h index 6ae393d..2e6f34e 100644 --- a/src/rp2350/hardware_structs/include/hardware/structs/m33.h +++ b/src/rp2350/hardware_structs/include/hardware/structs/m33.h
@@ -112,20 +112,7 @@ // 0x0000000f [3:0] DES_2 (0x4) See CoreSight Architecture Specification io_ro_32 itm_pidr4; - _REG_(M33_ITM_PIDR5_OFFSET) // M33_ITM_PIDR5 - // Provides CoreSight discovery information for the ITM - // 0x00000000 [31:0] ITM_PIDR5 (0x00000000) - io_rw_32 itm_pidr5; - - _REG_(M33_ITM_PIDR6_OFFSET) // M33_ITM_PIDR6 - // Provides CoreSight discovery information for the ITM - // 0x00000000 [31:0] ITM_PIDR6 (0x00000000) - io_rw_32 itm_pidr6; - - _REG_(M33_ITM_PIDR7_OFFSET) // M33_ITM_PIDR7 - // Provides CoreSight discovery information for the ITM - // 0x00000000 [31:0] ITM_PIDR7 (0x00000000) - io_rw_32 itm_pidr7; + uint32_t _pad8[3]; _REG_(M33_ITM_PIDR0_OFFSET) // M33_ITM_PIDR0 // Provides CoreSight discovery information for the ITM @@ -185,14 +172,14 @@ // 0xffffffff [31:0] CYCCNT (0x00000000) Increments one on each processor clock cycle when DWT_CTRL io_rw_32 dwt_cyccnt; - uint32_t _pad8; + uint32_t _pad9; _REG_(M33_DWT_EXCCNT_OFFSET) // M33_DWT_EXCCNT // Counts the total cycles spent in exception processing // 0x000000ff [7:0] EXCCNT (0x00) Counts one on each cycle when all of the following are... io_rw_32 dwt_exccnt; - uint32_t _pad9; + uint32_t _pad10; _REG_(M33_DWT_LSUCNT_OFFSET) // M33_DWT_LSUCNT // Increments on the additional cycles required to execute all load or store instructions @@ -204,14 +191,14 @@ // 0x000000ff [7:0] FOLDCNT (0x00) Counts on each cycle when all of the following are true:... io_rw_32 dwt_foldcnt; - uint32_t _pad10; + uint32_t _pad11; _REG_(M33_DWT_COMP0_OFFSET) // M33_DWT_COMP0 // Provides a reference value for use by watchpoint comparator 0 // 0xffffffff [31:0] DWT_COMP0 (0x00000000) io_rw_32 dwt_comp0; - uint32_t _pad11; + uint32_t _pad12; _REG_(M33_DWT_FUNCTION0_OFFSET) // M33_DWT_FUNCTION0 // Controls the operation of watchpoint comparator 0 @@ -222,14 +209,14 @@ // 0x0000000f [3:0] MATCH (0x0) Controls the type of match generated by this comparator io_rw_32 dwt_function0; - uint32_t _pad12; + uint32_t _pad13; _REG_(M33_DWT_COMP1_OFFSET) // M33_DWT_COMP1 // Provides a reference value for use by watchpoint comparator 1 // 0xffffffff [31:0] DWT_COMP1 (0x00000000) io_rw_32 dwt_comp1; - uint32_t _pad13; + uint32_t _pad14; _REG_(M33_DWT_FUNCTION1_OFFSET) // M33_DWT_FUNCTION1 // Controls the operation of watchpoint comparator 1 @@ -240,14 +227,14 @@ // 0x0000000f [3:0] MATCH (0x8) Controls the type of match generated by this comparator io_rw_32 dwt_function1; - uint32_t _pad14; + uint32_t _pad15; _REG_(M33_DWT_COMP2_OFFSET) // M33_DWT_COMP2 // Provides a reference value for use by watchpoint comparator 2 // 0xffffffff [31:0] DWT_COMP2 (0x00000000) io_rw_32 dwt_comp2; - uint32_t _pad15; + uint32_t _pad16; _REG_(M33_DWT_FUNCTION2_OFFSET) // M33_DWT_FUNCTION2 // Controls the operation of watchpoint comparator 2 @@ -258,14 +245,14 @@ // 0x0000000f [3:0] MATCH (0x0) Controls the type of match generated by this comparator io_rw_32 dwt_function2; - uint32_t _pad16; + uint32_t _pad17; _REG_(M33_DWT_COMP3_OFFSET) // M33_DWT_COMP3 // Provides a reference value for use by watchpoint comparator 3 // 0xffffffff [31:0] DWT_COMP3 (0x00000000) io_rw_32 dwt_comp3; - uint32_t _pad17; + uint32_t _pad18; _REG_(M33_DWT_FUNCTION3_OFFSET) // M33_DWT_FUNCTION3 // Controls the operation of watchpoint comparator 3 @@ -276,7 +263,7 @@ // 0x0000000f [3:0] MATCH (0x0) Controls the type of match generated by this comparator io_rw_32 dwt_function3; - uint32_t _pad18[984]; + uint32_t _pad19[984]; _REG_(M33_DWT_DEVARCH_OFFSET) // M33_DWT_DEVARCH // Provides CoreSight discovery information for the DWT @@ -287,7 +274,7 @@ // 0x00000fff [11:0] ARCHPART (0xa02) Defines the architecture of the component io_ro_32 dwt_devarch; - uint32_t _pad19[3]; + uint32_t _pad20[3]; _REG_(M33_DWT_DEVTYPE_OFFSET) // M33_DWT_DEVTYPE // Provides CoreSight discovery information for the DWT @@ -301,20 +288,7 @@ // 0x0000000f [3:0] DES_2 (0x4) See CoreSight Architecture Specification io_ro_32 dwt_pidr4; - _REG_(M33_DWT_PIDR5_OFFSET) // M33_DWT_PIDR5 - // Provides CoreSight discovery information for the DWT - // 0x00000000 [31:0] DWT_PIDR5 (0x00000000) - io_rw_32 dwt_pidr5; - - _REG_(M33_DWT_PIDR6_OFFSET) // M33_DWT_PIDR6 - // Provides CoreSight discovery information for the DWT - // 0x00000000 [31:0] DWT_PIDR6 (0x00000000) - io_rw_32 dwt_pidr6; - - _REG_(M33_DWT_PIDR7_OFFSET) // M33_DWT_PIDR7 - // Provides CoreSight discovery information for the DWT - // 0x00000000 [31:0] DWT_PIDR7 (0x00000000) - io_rw_32 dwt_pidr7; + uint32_t _pad21[3]; _REG_(M33_DWT_PIDR0_OFFSET) // M33_DWT_PIDR0 // Provides CoreSight discovery information for the DWT @@ -368,7 +342,7 @@ // 0x00000001 [0] BE (0) Selects between flashpatch and breakpoint functionality io_rw_32 fp_comp[8]; - uint32_t _pad20[997]; + uint32_t _pad22[997]; _REG_(M33_FP_DEVARCH_OFFSET) // M33_FP_DEVARCH // Provides CoreSight discovery information for the FPB @@ -379,7 +353,7 @@ // 0x00000fff [11:0] ARCHPART (0xa03) Defines the architecture of the component io_ro_32 fp_devarch; - uint32_t _pad21[3]; + uint32_t _pad23[3]; _REG_(M33_FP_DEVTYPE_OFFSET) // M33_FP_DEVTYPE // Provides CoreSight discovery information for the FPB @@ -393,20 +367,7 @@ // 0x0000000f [3:0] DES_2 (0x4) See CoreSight Architecture Specification io_ro_32 fp_pidr4; - _REG_(M33_FP_PIDR5_OFFSET) // M33_FP_PIDR5 - // Provides CoreSight discovery information for the FP - // 0x00000000 [31:0] FP_PIDR5 (0x00000000) - io_rw_32 fp_pidr5; - - _REG_(M33_FP_PIDR6_OFFSET) // M33_FP_PIDR6 - // Provides CoreSight discovery information for the FP - // 0x00000000 [31:0] FP_PIDR6 (0x00000000) - io_rw_32 fp_pidr6; - - _REG_(M33_FP_PIDR7_OFFSET) // M33_FP_PIDR7 - // Provides CoreSight discovery information for the FP - // 0x00000000 [31:0] FP_PIDR7 (0x00000000) - io_rw_32 fp_pidr7; + uint32_t _pad24[3]; _REG_(M33_FP_PIDR0_OFFSET) // M33_FP_PIDR0 // Provides CoreSight discovery information for the FP @@ -438,7 +399,7 @@ // 0x000000ff [7:0] PRMBL_0 (0x0d) See CoreSight Architecture Specification io_ro_32 fp_cidr[4]; - uint32_t _pad22[11265]; + uint32_t _pad25[11265]; _REG_(M33_ICTR_OFFSET) // M33_ICTR // Provides information about the interrupt controller @@ -455,7 +416,7 @@ // 0x00000001 [0] DISMCYCINT (0) Disable dual-issue io_rw_32 actlr; - uint32_t _pad23; + uint32_t _pad26; _REG_(M33_SYST_CSR_OFFSET) // M33_SYST_CSR // SysTick Control and Status Register @@ -482,7 +443,7 @@ // 0x00ffffff [23:0] TENMS (0x000000) An optional Reload value to be used for 10ms (100Hz)... io_ro_32 syst_calib; - uint32_t _pad24[56]; + uint32_t _pad27[56]; // (Description copied from array index 0 register M33_NVIC_ISER0 applies similarly to other array indexes) _REG_(M33_NVIC_ISER0_OFFSET) // M33_NVIC_ISER0 @@ -490,7 +451,7 @@ // 0xffffffff [31:0] SETENA (0x00000000) For SETENA[m] in NVIC_ISER*n, indicates whether... io_rw_32 nvic_iser[2]; - uint32_t _pad25[30]; + uint32_t _pad28[30]; // (Description copied from array index 0 register M33_NVIC_ICER0 applies similarly to other array indexes) _REG_(M33_NVIC_ICER0_OFFSET) // M33_NVIC_ICER0 @@ -498,7 +459,7 @@ // 0xffffffff [31:0] CLRENA (0x00000000) For CLRENA[m] in NVIC_ICER*n, indicates whether... io_rw_32 nvic_icer[2]; - uint32_t _pad26[30]; + uint32_t _pad29[30]; // (Description copied from array index 0 register M33_NVIC_ISPR0 applies similarly to other array indexes) _REG_(M33_NVIC_ISPR0_OFFSET) // M33_NVIC_ISPR0 @@ -506,7 +467,7 @@ // 0xffffffff [31:0] SETPEND (0x00000000) For SETPEND[m] in NVIC_ISPR*n, indicates whether... io_rw_32 nvic_ispr[2]; - uint32_t _pad27[30]; + uint32_t _pad30[30]; // (Description copied from array index 0 register M33_NVIC_ICPR0 applies similarly to other array indexes) _REG_(M33_NVIC_ICPR0_OFFSET) // M33_NVIC_ICPR0 @@ -514,7 +475,7 @@ // 0xffffffff [31:0] CLRPEND (0x00000000) For CLRPEND[m] in NVIC_ICPR*n, indicates whether... io_rw_32 nvic_icpr[2]; - uint32_t _pad28[30]; + uint32_t _pad31[30]; // (Description copied from array index 0 register M33_NVIC_IABR0 applies similarly to other array indexes) _REG_(M33_NVIC_IABR0_OFFSET) // M33_NVIC_IABR0 @@ -522,7 +483,7 @@ // 0xffffffff [31:0] ACTIVE (0x00000000) For ACTIVE[m] in NVIC_IABR*n, indicates the active state... io_rw_32 nvic_iabr[2]; - uint32_t _pad29[30]; + uint32_t _pad32[30]; // (Description copied from array index 0 register M33_NVIC_ITNS0 applies similarly to other array indexes) _REG_(M33_NVIC_ITNS0_OFFSET) // M33_NVIC_ITNS0 @@ -530,7 +491,7 @@ // 0xffffffff [31:0] ITNS (0x00000000) For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security... io_rw_32 nvic_itns[2]; - uint32_t _pad30[30]; + uint32_t _pad33[30]; // (Description copied from array index 0 register M33_NVIC_IPR0 applies similarly to other array indexes) _REG_(M33_NVIC_IPR0_OFFSET) // M33_NVIC_IPR0 @@ -541,7 +502,7 @@ // 0x000000f0 [7:4] PRI_N0 (0x0) For register NVIC_IPRn, the priority of interrupt number... io_rw_32 nvic_ipr[16]; - uint32_t _pad31[560]; + uint32_t _pad34[560]; _REG_(M33_CPUID_OFFSET) // M33_CPUID // Provides identification information for the PE, including an implementer code for the device and... @@ -580,8 +541,8 @@ // 0x00004000 [14] PRIS (0) Prioritize Secure exceptions // 0x00002000 [13] BFHFNMINS (0) BusFault, HardFault, and NMI Non-secure enable // 0x00000700 [10:8] PRIGROUP (0x0) Interrupt priority grouping field - // 0x00000008 [3] SYSRESETREQS (0) System reset request, Secure state only - // 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to... + // 0x00000008 [3] SYSRESETREQS (0) This resets only the core on which SYSRESETREQ is... + // 0x00000004 [2] SYSRESETREQ (0) This resets only the core on which SYSRESETREQ is... // 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and... io_rw_32 aircr; @@ -685,7 +646,7 @@ // 0xffffffff [31:0] ADDRESS (0x00000000) This register is updated with the address of a location... io_rw_32 bfar; - uint32_t _pad32; + uint32_t _pad35; // (Description copied from array index 0 register M33_ID_PFR0 applies similarly to other array indexes) _REG_(M33_ID_PFR0_OFFSET) // M33_ID_PFR0 @@ -726,9 +687,9 @@ // 0x0000f000 [15:12] CMPBRANCH (0x2) Indicates the supported combined Compare and Branch instructions // 0x00000f00 [11:8] BITFIELD (0x3) Indicates the supported bit field instructions // 0x000000f0 [7:4] BITCOUNT (0x0) Indicates the supported bit count instructions - io_ro_32 id_isar[6]; + io_ro_32 id_isar[5]; - uint32_t _pad33; + uint32_t _pad36[2]; _REG_(M33_CTR_OFFSET) // M33_CTR // Provides information about the architecture of the caches @@ -740,7 +701,7 @@ // 0x0000000f [3:0] IMINLINE (0x0) Log2 of the number of words in the smallest cache line... io_ro_32 ctr; - uint32_t _pad34[2]; + uint32_t _pad37[2]; _REG_(M33_CPACR_OFFSET) // M33_CPACR // Specifies the access privileges for coprocessors and the FP Extension @@ -848,7 +809,7 @@ // 0x00000001 [0] EN (0) Region enable io_rw_32 mpu_rlar_a3; - uint32_t _pad35; + uint32_t _pad38; // (Description copied from array index 0 register M33_MPU_MAIR0 applies similarly to other array indexes) _REG_(M33_MPU_MAIR0_OFFSET) // M33_MPU_MAIR0 @@ -859,7 +820,7 @@ // 0x000000ff [7:0] ATTR0 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 0 io_rw_32 mpu_mair[2]; - uint32_t _pad36[2]; + uint32_t _pad39[2]; _REG_(M33_SAU_CTRL_OFFSET) // M33_SAU_CTRL // Allows enabling of the Security Attribution Unit @@ -906,7 +867,7 @@ // 0xffffffff [31:0] ADDRESS (0x00000000) The address of an access that caused a attribution unit violation io_rw_32 sfar; - uint32_t _pad37; + uint32_t _pad40; _REG_(M33_DHCSR_OFFSET) // M33_DHCSR // Controls halting debug @@ -955,7 +916,7 @@ // 0x00000001 [0] VC_CORERESET (0) Enable Reset Vector Catch io_rw_32 demcr; - uint32_t _pad38[2]; + uint32_t _pad41[2]; _REG_(M33_DSCSR_OFFSET) // M33_DSCSR // Provides control and status information for Secure debug @@ -965,14 +926,14 @@ // 0x00000001 [0] SBRSELEN (0) Controls whether the SBRSEL field or the current... io_rw_32 dscsr; - uint32_t _pad39[61]; + uint32_t _pad42[61]; _REG_(M33_STIR_OFFSET) // M33_STIR // Provides a mechanism for software to generate an interrupt // 0x000001ff [8:0] INTID (0x000) Indicates the interrupt to be pended io_rw_32 stir; - uint32_t _pad40[12]; + uint32_t _pad43[12]; _REG_(M33_FPCCR_OFFSET) // M33_FPCCR // Holds control data for the Floating-point extension @@ -1019,7 +980,7 @@ // 0x0000000f [3:0] SIMDREG (0x1) Indicates size of FP register file io_ro_32 mvfr[3]; - uint32_t _pad41[28]; + uint32_t _pad44[28]; _REG_(M33_DDEVARCH_OFFSET) // M33_DDEVARCH // Provides CoreSight discovery information for the SCS @@ -1030,7 +991,7 @@ // 0x00000fff [11:0] ARCHPART (0xa04) Defines the architecture of the component io_ro_32 ddevarch; - uint32_t _pad42[3]; + uint32_t _pad45[3]; _REG_(M33_DDEVTYPE_OFFSET) // M33_DDEVTYPE // Provides CoreSight discovery information for the SCS @@ -1044,20 +1005,7 @@ // 0x0000000f [3:0] DES_2 (0x4) See CoreSight Architecture Specification io_ro_32 dpidr4; - _REG_(M33_DPIDR5_OFFSET) // M33_DPIDR5 - // Provides CoreSight discovery information for the SCS - // 0x00000000 [31:0] DPIDR5 (0x00000000) - io_rw_32 dpidr5; - - _REG_(M33_DPIDR6_OFFSET) // M33_DPIDR6 - // Provides CoreSight discovery information for the SCS - // 0x00000000 [31:0] DPIDR6 (0x00000000) - io_rw_32 dpidr6; - - _REG_(M33_DPIDR7_OFFSET) // M33_DPIDR7 - // Provides CoreSight discovery information for the SCS - // 0x00000000 [31:0] DPIDR7 (0x00000000) - io_rw_32 dpidr7; + uint32_t _pad46[3]; _REG_(M33_DPIDR0_OFFSET) // M33_DPIDR0 // Provides CoreSight discovery information for the SCS @@ -1089,14 +1037,14 @@ // 0x000000ff [7:0] PRMBL_0 (0x0d) See CoreSight Architecture Specification io_ro_32 dcidr[4]; - uint32_t _pad43[51201]; + uint32_t _pad47[51201]; _REG_(M33_TRCPRGCTLR_OFFSET) // M33_TRCPRGCTLR // Programming Control Register // 0x00000001 [0] EN (0) Trace Unit Enable io_rw_32 trcprgctlr; - uint32_t _pad44; + uint32_t _pad48; _REG_(M33_TRCSTATR_OFFSET) // M33_TRCSTATR // The TRCSTATR indicates the ETM-Teal status @@ -1113,7 +1061,7 @@ // 0x00000008 [3] BB (0) Branch broadcast mode io_rw_32 trcconfigr; - uint32_t _pad45[3]; + uint32_t _pad49[3]; _REG_(M33_TRCEVENTCTL0R_OFFSET) // M33_TRCEVENTCTL0R // The TRCEVENTCTL0R controls the tracing of events in the trace stream @@ -1131,7 +1079,7 @@ // 0x00000001 [0] INSTEN0 (0) One bit per event, to enable generation of an event... io_rw_32 trceventctl1r; - uint32_t _pad46; + uint32_t _pad50; _REG_(M33_TRCSTALLCTLR_OFFSET) // M33_TRCSTALLCTLR // The TRCSTALLCTLR enables ETM-Teal to stall the processor if the ETM-Teal FIFO goes over the... @@ -1156,7 +1104,7 @@ // 0x00000fff [11:0] THRESHOLD (0x000) Instruction trace cycle count threshold io_rw_32 trcccctlr; - uint32_t _pad47[17]; + uint32_t _pad51[17]; _REG_(M33_TRCVICTLR_OFFSET) // M33_TRCVICTLR // The TRCVICTLR controls instruction trace filtering @@ -1169,14 +1117,14 @@ // 0x00000003 [1:0] SEL0 (0x0) Selects the resource number, based on the value of... io_rw_32 trcvictlr; - uint32_t _pad48[47]; + uint32_t _pad52[47]; _REG_(M33_TRCCNTRLDVR0_OFFSET) // M33_TRCCNTRLDVR0 // The TRCCNTRLDVR defines the reload value for the reduced function counter // 0x0000ffff [15:0] VALUE (0x0000) Defines the reload value for the counter io_rw_32 trccntrldvr0; - uint32_t _pad49[15]; + uint32_t _pad53[15]; _REG_(M33_TRCIDR8_OFFSET) // M33_TRCIDR8 // TRCIDR8 @@ -1208,14 +1156,14 @@ // 0xffffffff [31:0] NUMCONDSPC (0x00000000) reads as `ImpDef io_ro_32 trcidr13; - uint32_t _pad50[10]; + uint32_t _pad54[10]; _REG_(M33_TRCIMSPEC_OFFSET) // M33_TRCIMSPEC // The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any... // 0x0000000f [3:0] SUPPORT (0x0) Reserved, RES0 io_ro_32 trcimspec; - uint32_t _pad51[7]; + uint32_t _pad55[7]; _REG_(M33_TRCIDR0_OFFSET) // M33_TRCIDR0 // TRCIDR0 @@ -1291,17 +1239,7 @@ // 0x000001ff [8:0] NUMEXTIN (0x004) reads as `ImpDef io_ro_32 trcidr5; - _REG_(M33_TRCIDR6_OFFSET) // M33_TRCIDR6 - // TRCIDR6 - // 0x00000000 [31:0] TRCIDR6 (0x00000000) - io_rw_32 trcidr6; - - _REG_(M33_TRCIDR7_OFFSET) // M33_TRCIDR7 - // TRCIDR7 - // 0x00000000 [31:0] TRCIDR7 (0x00000000) - io_rw_32 trcidr7; - - uint32_t _pad52[2]; + uint32_t _pad56[4]; // (Description copied from array index 0 register M33_TRCRSCTLR2 applies similarly to other array indexes) _REG_(M33_TRCRSCTLR2_OFFSET) // M33_TRCRSCTLR2 @@ -1312,7 +1250,7 @@ // 0x000000ff [7:0] SELECT (0x00) Selects one or more resources from the wanted group io_rw_32 trcrsctlr[2]; - uint32_t _pad53[36]; + uint32_t _pad57[36]; _REG_(M33_TRCSSCSR_OFFSET) // M33_TRCSSCSR // Controls the corresponding single-shot comparator resource @@ -1323,14 +1261,14 @@ // 0x00000001 [0] INST (0) Reserved, RES0 io_rw_32 trcsscsr; - uint32_t _pad54[7]; + uint32_t _pad58[7]; _REG_(M33_TRCSSPCICR_OFFSET) // M33_TRCSSPCICR // Selects the PE comparator inputs for Single-shot control // 0x0000000f [3:0] PC (0x0) Selects one or more PE comparator inputs for Single-shot control io_rw_32 trcsspcicr; - uint32_t _pad55[19]; + uint32_t _pad59[19]; _REG_(M33_TRCPDCR_OFFSET) // M33_TRCPDCR // Requests the system to provide power to the trace unit @@ -1344,14 +1282,14 @@ // 0x00000001 [0] POWER (1) Power status bit: io_ro_32 trcpdsr; - uint32_t _pad56[755]; + uint32_t _pad60[755]; _REG_(M33_TRCITATBIDR_OFFSET) // M33_TRCITATBIDR // Trace Integration ATB Identification Register // 0x0000007f [6:0] ID (0x00) Trace ID io_rw_32 trcitatbidr; - uint32_t _pad57[3]; + uint32_t _pad61[3]; _REG_(M33_TRCITIATBINR_OFFSET) // M33_TRCITIATBINR // Trace Integration Instruction ATB In Register @@ -1359,7 +1297,7 @@ // 0x00000001 [0] ATREADYM (0) Integration Mode instruction ATREADYM in io_rw_32 trcitiatbinr; - uint32_t _pad58; + uint32_t _pad62; _REG_(M33_TRCITIATBOUTR_OFFSET) // M33_TRCITIATBOUTR // Trace Integration Instruction ATB Out Register @@ -1367,7 +1305,7 @@ // 0x00000001 [0] ATVALID (0) Integration Mode instruction ATVALID out io_rw_32 trcitiatboutr; - uint32_t _pad59[40]; + uint32_t _pad63[40]; _REG_(M33_TRCCLAIMSET_OFFSET) // M33_TRCCLAIMSET // Claim Tag Set Register @@ -1385,7 +1323,7 @@ // 0x00000001 [0] CLR0 (0) When a write to one of these bits occurs, with the value: io_rw_32 trcclaimclr; - uint32_t _pad60[4]; + uint32_t _pad64[4]; _REG_(M33_TRCAUTHSTATUS_OFFSET) // M33_TRCAUTHSTATUS // Returns the level of tracing that the trace unit can support @@ -1403,12 +1341,7 @@ // 0x0000ffff [15:0] ARCHID (0x4a13) reads as 0b0100101000010011 io_ro_32 trcdevarch; - uint32_t _pad61[2]; - - _REG_(M33_TRCDEVID_OFFSET) // M33_TRCDEVID - // TRCDEVID - // 0x00000000 [31:0] TRCDEVID (0x00000000) - io_rw_32 trcdevid; + uint32_t _pad65[3]; _REG_(M33_TRCDEVTYPE_OFFSET) // M33_TRCDEVTYPE // TRCDEVTYPE @@ -1422,20 +1355,7 @@ // 0x0000000f [3:0] DES_2 (0x4) reads as `ImpDef io_ro_32 trcpidr4; - _REG_(M33_TRCPIDR5_OFFSET) // M33_TRCPIDR5 - // TRCPIDR5 - // 0x00000000 [31:0] TRCPIDR5 (0x00000000) - io_rw_32 trcpidr5; - - _REG_(M33_TRCPIDR6_OFFSET) // M33_TRCPIDR6 - // TRCPIDR6 - // 0x00000000 [31:0] TRCPIDR6 (0x00000000) - io_rw_32 trcpidr6; - - _REG_(M33_TRCPIDR7_OFFSET) // M33_TRCPIDR7 - // TRCPIDR7 - // 0x00000000 [31:0] TRCPIDR7 (0x00000000) - io_rw_32 trcpidr7; + uint32_t _pad66[3]; _REG_(M33_TRCPIDR0_OFFSET) // M33_TRCPIDR0 // TRCPIDR0 @@ -1472,7 +1392,7 @@ // 0x00000001 [0] GLBEN (0) Enables or disables the CTI io_rw_32 cticontrol; - uint32_t _pad62[3]; + uint32_t _pad67[3]; _REG_(M33_CTIINTACK_OFFSET) // M33_CTIINTACK // CTI Interrupt Acknowledge Register @@ -1500,7 +1420,7 @@ // 0x0000000f [3:0] TRIGINEN (0x0) Enables a cross trigger event to the corresponding... io_rw_32 ctiinen[8]; - uint32_t _pad63[24]; + uint32_t _pad68[24]; // (Description copied from array index 0 register M33_CTIOUTEN0 applies similarly to other array indexes) _REG_(M33_CTIOUTEN0_OFFSET) // M33_CTIOUTEN0 @@ -1508,7 +1428,7 @@ // 0x0000000f [3:0] TRIGOUTEN (0x0) Enables a cross trigger event to ctitrigout when the... io_rw_32 ctiouten[8]; - uint32_t _pad64[28]; + uint32_t _pad69[28]; _REG_(M33_CTITRIGINSTATUS_OFFSET) // M33_CTITRIGINSTATUS // CTI Trigger to Channel Enable Registers @@ -1525,7 +1445,7 @@ // 0x0000000f [3:0] CTICHOUTSTATUS (0x0) Shows the status of the ctichout outputs io_ro_32 ctichinstatus; - uint32_t _pad65; + uint32_t _pad70; _REG_(M33_CTIGATE_OFFSET) // M33_CTIGATE // Enable CTI Channel Gate register @@ -1535,12 +1455,7 @@ // 0x00000001 [0] CTIGATEEN0 (1) Enable ctichout0 io_rw_32 ctigate; - _REG_(M33_ASICCTL_OFFSET) // M33_ASICCTL - // External Multiplexer Control register - // 0x00000000 [31:0] ASICCTL (0x00000000) - io_rw_32 asicctl; - - uint32_t _pad66[871]; + uint32_t _pad71[872]; _REG_(M33_ITCHOUT_OFFSET) // M33_ITCHOUT // Integration Test Channel Output register @@ -1552,21 +1467,21 @@ // 0x000000ff [7:0] CTTRIGOUT (0x00) Sets the value of the ctitrigout outputs io_rw_32 ittrigout; - uint32_t _pad67[2]; + uint32_t _pad72[2]; _REG_(M33_ITCHIN_OFFSET) // M33_ITCHIN // Integration Test Channel Input register // 0x0000000f [3:0] CTCHIN (0x0) Reads the value of the ctichin inputs io_ro_32 itchin; - uint32_t _pad68[2]; + uint32_t _pad73[2]; _REG_(M33_ITCTRL_OFFSET) // M33_ITCTRL // Integration Mode Control register // 0x00000001 [0] IME (0) Integration Mode Enable io_rw_32 itctrl; - uint32_t _pad69[46]; + uint32_t _pad74[46]; _REG_(M33_DEVARCH_OFFSET) // M33_DEVARCH // Device Architecture register @@ -1576,7 +1491,7 @@ // 0x0000ffff [15:0] ARCHID (0x1a14) Indicates the component io_ro_32 devarch; - uint32_t _pad70[2]; + uint32_t _pad75[2]; _REG_(M33_DEVID_OFFSET) // M33_DEVID // Device Configuration register @@ -1597,20 +1512,7 @@ // 0x0000000f [3:0] DES_2 (0x4) Together, PIDR1 io_ro_32 pidr4; - _REG_(M33_PIDR5_OFFSET) // M33_PIDR5 - // CoreSight Peripheral ID5 - // 0x00000000 [31:0] PIDR5 (0x00000000) - io_rw_32 pidr5; - - _REG_(M33_PIDR6_OFFSET) // M33_PIDR6 - // CoreSight Peripheral ID6 - // 0x00000000 [31:0] PIDR6 (0x00000000) - io_rw_32 pidr6; - - _REG_(M33_PIDR7_OFFSET) // M33_PIDR7 - // CoreSight Peripheral ID7 - // 0x00000000 [31:0] PIDR7 (0x00000000) - io_rw_32 pidr7; + uint32_t _pad76[3]; _REG_(M33_PIDR0_OFFSET) // M33_PIDR0 // CoreSight Peripheral ID0
diff --git a/src/rp2350/hardware_structs/include/hardware/structs/m33_eppb.h b/src/rp2350/hardware_structs/include/hardware/structs/m33_eppb.h index 4d1dd8f..4f08daa 100644 --- a/src/rp2350/hardware_structs/include/hardware/structs/m33_eppb.h +++ b/src/rp2350/hardware_structs/include/hardware/structs/m33_eppb.h
@@ -27,7 +27,6 @@ #error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" #endif - typedef struct { // (Description copied from array index 0 register M33_EPPB_NMI_MASK0 applies similarly to other array indexes) _REG_(M33_EPPB_NMI_MASK0_OFFSET) // M33_EPPB_NMI_MASK0
diff --git a/src/rp2350/hardware_structs/include/hardware/structs/powman.h b/src/rp2350/hardware_structs/include/hardware/structs/powman.h index 003d5b5..dcda4d2 100644 --- a/src/rp2350/hardware_structs/include/hardware/structs/powman.h +++ b/src/rp2350/hardware_structs/include/hardware/structs/powman.h
@@ -96,7 +96,7 @@ _REG_(POWMAN_CHIP_RESET_OFFSET) // POWMAN_CHIP_RESET // Chip reset control and status - // 0x10000000 [28] HAD_WATCHDOG_RESET_RSM (0) Last reset was a watchdog timeout which was configured... + // 0x10000000 [28] HAD_WATCHDOG_RESET_PSM (0) Last reset was a watchdog timeout which was configured... // 0x08000000 [27] HAD_HZD_SYS_RESET_REQ (0) Last reset was a system reset from the hazard debugger + // 0x04000000 [26] HAD_GLITCH_DETECT (0) Last reset was due to a power supply glitch + // 0x02000000 [25] HAD_SWCORE_PD (0) Last reset was a switched core powerdown + @@ -114,7 +114,7 @@ _REG_(POWMAN_WDSEL_OFFSET) // POWMAN_WDSEL // Allows a watchdog reset to reset the internal state of powman in addition to the power-on state... - // 0x00001000 [12] RESET_RSM (0) If set to 1, a watchdog reset will run the full power-on... + // 0x00001000 [12] RESET_PSM (0) If set to 1, a watchdog reset will run the full power-on... // 0x00000100 [8] RESET_SWCORE (0) If set to 1, a watchdog reset will reset the switched... // 0x00000010 [4] RESET_POWMAN (0) If set to 1, a watchdog reset will restore powman... // 0x00000001 [0] RESET_POWMAN_ASYNC (0) If set to 1, a watchdog reset will restore powman... @@ -171,7 +171,7 @@ _REG_(POWMAN_EXT_TIME_REF_OFFSET) // POWMAN_EXT_TIME_REF // Select a GPIO to use as a time reference, the source can be used to drive the low power clock at... // 0x00000010 [4] DRIVE_LPCK (0) Use the selected GPIO to drive the 32kHz low power... - // 0x00000003 [1:0] SOURCE_SEL (0x0) 0 -> gpio12 + + // 0x00000003 [1:0] SOURCE_SEL (0x0) io_rw_32 ext_time_ref; _REG_(POWMAN_LPOSC_FREQ_KHZ_INT_OFFSET) // POWMAN_LPOSC_FREQ_KHZ_INT @@ -279,7 +279,7 @@ _REG_(POWMAN_BOOTDIS_OFFSET) // POWMAN_BOOTDIS // Tell the bootrom to ignore the BOOT0 // 0x00000002 [1] NEXT (0) This flag always ORs writes into its current contents - // 0x00000001 [0] NOW (0) When powman resets the RSM, the current value of... + // 0x00000001 [0] NOW (0) When powman resets the PSM, the current value of... io_rw_32 bootdis; _REG_(POWMAN_DBGCONFIG_OFFSET) // POWMAN_DBGCONFIG
diff --git a/src/rp2350/hardware_structs/include/hardware/structs/scb.h b/src/rp2350/hardware_structs/include/hardware/structs/scb.h index 17d60ee..3240b3a 100644 --- a/src/rp2350/hardware_structs/include/hardware/structs/scb.h +++ b/src/rp2350/hardware_structs/include/hardware/structs/scb.h
@@ -65,8 +65,8 @@ // 0x00004000 [14] PRIS (0) Prioritize Secure exceptions // 0x00002000 [13] BFHFNMINS (0) BusFault, HardFault, and NMI Non-secure enable // 0x00000700 [10:8] PRIGROUP (0x0) Interrupt priority grouping field - // 0x00000008 [3] SYSRESETREQS (0) System reset request, Secure state only - // 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to... + // 0x00000008 [3] SYSRESETREQS (0) This resets only the core on which SYSRESETREQ is... + // 0x00000004 [2] SYSRESETREQ (0) This resets only the core on which SYSRESETREQ is... // 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and... io_rw_32 aircr; @@ -192,7 +192,6 @@ // 0x0000000f [3:0] IMPDEF0 (0x0) IMPLEMENTATION DEFINED meaning io_ro_32 id_afr0; - // (Description copied from array index 0 register M33_ID_MMFR0 applies similarly to other array indexes) _REG_(M33_ID_MMFR0_OFFSET) // M33_ID_MMFR0 // Provides information about the implemented memory model and memory management support // 0x00f00000 [23:20] AUXREG (0x1) Indicates support for Auxiliary Control Registers @@ -200,7 +199,15 @@ // 0x0000f000 [15:12] SHARELVL (0x1) Indicates the number of shareability levels implemented // 0x00000f00 [11:8] OUTERSHR (0xf) Indicates the outermost shareability domain implemented // 0x000000f0 [7:4] PMSA (0x4) Indicates support for the protected memory system... - io_ro_32 id_mmfr[4]; + io_ro_32 id_mmfr0; + + uint32_t _pad1; + + // (Description copied from array index 0 register M33_ID_MMFR2 applies similarly to other array indexes) + _REG_(M33_ID_MMFR2_OFFSET) // M33_ID_MMFR2 + // Provides information about the implemented memory model and memory management support + // 0x0f000000 [27:24] WFISTALL (0x1) Indicates the support for Wait For Interrupt (WFI) stalling + io_ro_32 id_mmfr[2]; // (Description copied from array index 0 register M33_ID_ISAR0 applies similarly to other array indexes) _REG_(M33_ID_ISAR0_OFFSET) // M33_ID_ISAR0 @@ -211,9 +218,9 @@ // 0x0000f000 [15:12] CMPBRANCH (0x2) Indicates the supported combined Compare and Branch instructions // 0x00000f00 [11:8] BITFIELD (0x3) Indicates the supported bit field instructions // 0x000000f0 [7:4] BITCOUNT (0x0) Indicates the supported bit count instructions - io_ro_32 id_isar[6]; + io_ro_32 id_isar[5]; - uint32_t _pad1; + uint32_t _pad2[2]; _REG_(M33_CTR_OFFSET) // M33_CTR // Provides information about the architecture of the caches @@ -225,7 +232,7 @@ // 0x0000000f [3:0] IMINLINE (0x0) Log2 of the number of words in the smallest cache line... io_ro_32 ctr; - uint32_t _pad2[2]; + uint32_t _pad3[2]; _REG_(M33_CPACR_OFFSET) // M33_CPACR // Specifies the access privileges for coprocessors and the FP Extension
diff --git a/src/rp2350/hardware_structs/include/hardware/structs/sio.h b/src/rp2350/hardware_structs/include/hardware/structs/sio.h index d3faaa9..ed4561c 100644 --- a/src/rp2350/hardware_structs/include/hardware/structs/sio.h +++ b/src/rp2350/hardware_structs/include/hardware/structs/sio.h
@@ -249,7 +249,7 @@ uint32_t _pad3[2]; _REG_(SIO_MTIME_OFFSET) // SIO_MTIME - // Read/write access to the high half of RISC-V Machine-mode timer + // Read/write access to the low half of RISC-V Machine-mode timer // 0xffffffff [31:0] MTIME (0x00000000) io_rw_32 mtime;
diff --git a/src/rp2350/hardware_structs/include/hardware/structs/sysinfo.h b/src/rp2350/hardware_structs/include/hardware/structs/sysinfo.h index 705ff36..1bb2948 100644 --- a/src/rp2350/hardware_structs/include/hardware/structs/sysinfo.h +++ b/src/rp2350/hardware_structs/include/hardware/structs/sysinfo.h
@@ -26,13 +26,14 @@ typedef struct { _REG_(SYSINFO_CHIP_ID_OFFSET) // SYSINFO_CHIP_ID // JEDEC JEP-106 compliant chip identifier - // 0xf0000000 [31:28] REVISION (-) - // 0x0ffff000 [27:12] PART (-) - // 0x00000ffe [11:1] MANUFACTURER (-) + // 0xf0000000 [31:28] REVISION (0x3) + // 0x0ffff000 [27:12] PART (0x0004) + // 0x00000ffe [11:1] MANUFACTURER (0x493) // 0x00000001 [0] STOP_BIT (1) io_ro_32 chip_id; _REG_(SYSINFO_PACKAGE_SEL_OFFSET) // SYSINFO_PACKAGE_SEL + // Package selection indicator, 0 = QFN80, 1 = QFN60 // 0x00000001 [0] PACKAGE_SEL (0) io_ro_32 package_sel;
diff --git a/src/rp2350/hardware_structs/include/hardware/structs/tbman.h b/src/rp2350/hardware_structs/include/hardware/structs/tbman.h index 58d80dd..3c63e8c 100644 --- a/src/rp2350/hardware_structs/include/hardware/structs/tbman.h +++ b/src/rp2350/hardware_structs/include/hardware/structs/tbman.h
@@ -36,4 +36,3 @@ static_assert(sizeof (tbman_hw_t) == 0x0004, ""); #endif // _HARDWARE_STRUCTS_TBMAN_H -
diff --git a/src/rp2350/hardware_structs/include/hardware/structs/timer.h b/src/rp2350/hardware_structs/include/hardware/structs/timer.h index b29a3ba..b40908f 100644 --- a/src/rp2350/hardware_structs/include/hardware/structs/timer.h +++ b/src/rp2350/hardware_structs/include/hardware/structs/timer.h
@@ -25,17 +25,17 @@ typedef struct { _REG_(TIMER_TIMEHW_OFFSET) // TIMER_TIMEHW - // Write to bits 63:32 of time always write timelw before timehw + // Write to bits 63:32 of time + // 0xffffffff [31:0] TIMEHW (0x00000000) io_wo_32 timehw; _REG_(TIMER_TIMELW_OFFSET) // TIMER_TIMELW - // Write to bits 31:0 of time writes do not get copied to time until timehw is written + // Write to bits 31:0 of time + // 0xffffffff [31:0] TIMELW (0x00000000) io_wo_32 timelw; _REG_(TIMER_TIMEHR_OFFSET) // TIMER_TIMEHR - // Read from bits 63:32 of time always read timelr before timehr + // Read from bits 63:32 of time + // 0xffffffff [31:0] TIMEHR (0x00000000) io_ro_32 timehr; @@ -77,7 +77,7 @@ io_rw_32 pause; _REG_(TIMER_LOCKED_OFFSET) // TIMER_LOCKED - // Set locked bit to disable write access to timer Once set, cannot be cleared (without a reset) + // Set locked bit to disable write access to timer + // 0x00000001 [0] LOCKED (0) io_rw_32 locked;