commit ee68c78d0afae2b69c03ae1a72bf5cc267a2d94c
author graham sanderson <graham.sanderson@raspberrypi.com> Tue Feb 18 20:08:06 2025 -0600
committer graham sanderson <graham.sanderson@raspberrypi.com> Wed Feb 19 16:32:05 2025 -0600
tree 44efe0c0d741eefbb56473bc36f7d2d30444b554
parent bddd20f928ce76142793bef434d4f75f4af6e433

fix doc for SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_US

src/rp2_common/hardware_clocks/include/hardware/clocks.h

diff --git a/src/rp2_common/hardware_clocks/include/hardware/clocks.h b/src/rp2_common/hardware_clocks/include/hardware/clocks.h
index 8320cea..68f4b1a 100644
--- a/src/rp2_common/hardware_clocks/include/hardware/clocks.h
+++ b/src/rp2_common/hardware_clocks/include/hardware/clocks.h
@@ -231,7 +231,7 @@
 #endif
 #endif // PICO_RP2040 && SYS_CLK_KHZ == 200000 && XOSC_KHZ == 12000 && PLL_COMMON_REFDIV == 1
 
-// PICO_CONFIG: SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_US, Number of microseconds to wait after updating regulator voltage due to SYS_CLK_VREG_VOLTAGE_MIN to allow voltage to settle, type=bool, default=1, advanced=true, group=hardware_clocks
+// PICO_CONFIG: SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_US, Number of microseconds to wait after updating regulator voltage due to SYS_CLK_VREG_VOLTAGE_MIN to allow voltage to settle, type=bool, default=1000, advanced=true, group=hardware_clocks
 #ifndef SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_US
 #define SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_US 1000
 #endif