| /** |
| * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. |
| * |
| * SPDX-License-Identifier: BSD-3-Clause |
| */ |
| // ============================================================================= |
| // Register block : IO_BANK0 |
| // Version : 1 |
| // Bus type : apb |
| // Description : None |
| // ============================================================================= |
| #ifndef HARDWARE_REGS_IO_BANK0_DEFINED |
| #define HARDWARE_REGS_IO_BANK0_DEFINED |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO0_STATUS |
| // Description : GPIO status |
| #define IO_BANK0_GPIO0_STATUS_OFFSET 0x00000000 |
| #define IO_BANK0_GPIO0_STATUS_BITS 0x050a3300 |
| #define IO_BANK0_GPIO0_STATUS_RESET 0x00000000 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO0_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_RESET 0x0 |
| #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_BITS 0x04000000 |
| #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_MSB 26 |
| #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_LSB 26 |
| #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO0_STATUS_IRQFROMPAD |
| // Description : interrupt from pad before override is applied |
| #define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_BITS 0x01000000 |
| #define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_MSB 24 |
| #define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_LSB 24 |
| #define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO0_STATUS_INTOPERI |
| // Description : input signal to peripheral, after override is applied |
| #define IO_BANK0_GPIO0_STATUS_INTOPERI_RESET 0x0 |
| #define IO_BANK0_GPIO0_STATUS_INTOPERI_BITS 0x00080000 |
| #define IO_BANK0_GPIO0_STATUS_INTOPERI_MSB 19 |
| #define IO_BANK0_GPIO0_STATUS_INTOPERI_LSB 19 |
| #define IO_BANK0_GPIO0_STATUS_INTOPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO0_STATUS_INFROMPAD |
| // Description : input signal from pad, before override is applied |
| #define IO_BANK0_GPIO0_STATUS_INFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS 0x00020000 |
| #define IO_BANK0_GPIO0_STATUS_INFROMPAD_MSB 17 |
| #define IO_BANK0_GPIO0_STATUS_INFROMPAD_LSB 17 |
| #define IO_BANK0_GPIO0_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO0_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO0_STATUS_OETOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO0_STATUS_OETOPAD_BITS 0x00002000 |
| #define IO_BANK0_GPIO0_STATUS_OETOPAD_MSB 13 |
| #define IO_BANK0_GPIO0_STATUS_OETOPAD_LSB 13 |
| #define IO_BANK0_GPIO0_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO0_STATUS_OEFROMPERI |
| // Description : output enable from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO0_STATUS_OEFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO0_STATUS_OEFROMPERI_BITS 0x00001000 |
| #define IO_BANK0_GPIO0_STATUS_OEFROMPERI_MSB 12 |
| #define IO_BANK0_GPIO0_STATUS_OEFROMPERI_LSB 12 |
| #define IO_BANK0_GPIO0_STATUS_OEFROMPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO0_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO0_STATUS_OUTTOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO0_STATUS_OUTTOPAD_BITS 0x00000200 |
| #define IO_BANK0_GPIO0_STATUS_OUTTOPAD_MSB 9 |
| #define IO_BANK0_GPIO0_STATUS_OUTTOPAD_LSB 9 |
| #define IO_BANK0_GPIO0_STATUS_OUTTOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO0_STATUS_OUTFROMPERI |
| // Description : output signal from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_BITS 0x00000100 |
| #define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_MSB 8 |
| #define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_LSB 8 |
| #define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO0_CTRL |
| // Description : GPIO control including function select and overrides. |
| #define IO_BANK0_GPIO0_CTRL_OFFSET 0x00000004 |
| #define IO_BANK0_GPIO0_CTRL_BITS 0x3003331f |
| #define IO_BANK0_GPIO0_CTRL_RESET 0x0000001f |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO0_CTRL_IRQOVER |
| // Description : 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO0_CTRL_IRQOVER_RESET 0x0 |
| #define IO_BANK0_GPIO0_CTRL_IRQOVER_BITS 0x30000000 |
| #define IO_BANK0_GPIO0_CTRL_IRQOVER_MSB 29 |
| #define IO_BANK0_GPIO0_CTRL_IRQOVER_LSB 28 |
| #define IO_BANK0_GPIO0_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO0_CTRL_INOVER |
| // Description : 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO0_CTRL_INOVER_RESET 0x0 |
| #define IO_BANK0_GPIO0_CTRL_INOVER_BITS 0x00030000 |
| #define IO_BANK0_GPIO0_CTRL_INOVER_MSB 17 |
| #define IO_BANK0_GPIO0_CTRL_INOVER_LSB 16 |
| #define IO_BANK0_GPIO0_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO0_CTRL_OEOVER |
| // Description : 0x0 -> drive output enable from peripheral signal selected by |
| // funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal |
| // selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO0_CTRL_OEOVER_RESET 0x0 |
| #define IO_BANK0_GPIO0_CTRL_OEOVER_BITS 0x00003000 |
| #define IO_BANK0_GPIO0_CTRL_OEOVER_MSB 13 |
| #define IO_BANK0_GPIO0_CTRL_OEOVER_LSB 12 |
| #define IO_BANK0_GPIO0_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_DISABLE 0x2 |
| #define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_ENABLE 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO0_CTRL_OUTOVER |
| // Description : 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected |
| // by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO0_CTRL_OUTOVER_RESET 0x0 |
| #define IO_BANK0_GPIO0_CTRL_OUTOVER_BITS 0x00000300 |
| #define IO_BANK0_GPIO0_CTRL_OUTOVER_MSB 9 |
| #define IO_BANK0_GPIO0_CTRL_OUTOVER_LSB 8 |
| #define IO_BANK0_GPIO0_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO0_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x00 -> jtag_tck |
| // 0x01 -> spi0_rx |
| // 0x02 -> uart0_tx |
| // 0x03 -> i2c0_sda |
| // 0x04 -> pwm_a_0 |
| // 0x05 -> sio_0 |
| // 0x06 -> pio0_0 |
| // 0x07 -> pio1_0 |
| // 0x09 -> usb_muxing_overcurr_detect |
| // 0x1f -> null |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_RESET 0x1f |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS 0x0000001f |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_MSB 4 |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB 0 |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_JTAG_TCK 0x00 |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SPI0_RX 0x01 |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_UART0_TX 0x02 |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PWM_A_0 0x04 |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SIO_0 0x05 |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO0_0 0x06 |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO1_0 0x07 |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_NULL 0x1f |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO1_STATUS |
| // Description : GPIO status |
| #define IO_BANK0_GPIO1_STATUS_OFFSET 0x00000008 |
| #define IO_BANK0_GPIO1_STATUS_BITS 0x050a3300 |
| #define IO_BANK0_GPIO1_STATUS_RESET 0x00000000 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO1_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO1_STATUS_IRQTOPROC_RESET 0x0 |
| #define IO_BANK0_GPIO1_STATUS_IRQTOPROC_BITS 0x04000000 |
| #define IO_BANK0_GPIO1_STATUS_IRQTOPROC_MSB 26 |
| #define IO_BANK0_GPIO1_STATUS_IRQTOPROC_LSB 26 |
| #define IO_BANK0_GPIO1_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO1_STATUS_IRQFROMPAD |
| // Description : interrupt from pad before override is applied |
| #define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_BITS 0x01000000 |
| #define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_MSB 24 |
| #define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_LSB 24 |
| #define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO1_STATUS_INTOPERI |
| // Description : input signal to peripheral, after override is applied |
| #define IO_BANK0_GPIO1_STATUS_INTOPERI_RESET 0x0 |
| #define IO_BANK0_GPIO1_STATUS_INTOPERI_BITS 0x00080000 |
| #define IO_BANK0_GPIO1_STATUS_INTOPERI_MSB 19 |
| #define IO_BANK0_GPIO1_STATUS_INTOPERI_LSB 19 |
| #define IO_BANK0_GPIO1_STATUS_INTOPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO1_STATUS_INFROMPAD |
| // Description : input signal from pad, before override is applied |
| #define IO_BANK0_GPIO1_STATUS_INFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO1_STATUS_INFROMPAD_BITS 0x00020000 |
| #define IO_BANK0_GPIO1_STATUS_INFROMPAD_MSB 17 |
| #define IO_BANK0_GPIO1_STATUS_INFROMPAD_LSB 17 |
| #define IO_BANK0_GPIO1_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO1_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO1_STATUS_OETOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO1_STATUS_OETOPAD_BITS 0x00002000 |
| #define IO_BANK0_GPIO1_STATUS_OETOPAD_MSB 13 |
| #define IO_BANK0_GPIO1_STATUS_OETOPAD_LSB 13 |
| #define IO_BANK0_GPIO1_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO1_STATUS_OEFROMPERI |
| // Description : output enable from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO1_STATUS_OEFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO1_STATUS_OEFROMPERI_BITS 0x00001000 |
| #define IO_BANK0_GPIO1_STATUS_OEFROMPERI_MSB 12 |
| #define IO_BANK0_GPIO1_STATUS_OEFROMPERI_LSB 12 |
| #define IO_BANK0_GPIO1_STATUS_OEFROMPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO1_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO1_STATUS_OUTTOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO1_STATUS_OUTTOPAD_BITS 0x00000200 |
| #define IO_BANK0_GPIO1_STATUS_OUTTOPAD_MSB 9 |
| #define IO_BANK0_GPIO1_STATUS_OUTTOPAD_LSB 9 |
| #define IO_BANK0_GPIO1_STATUS_OUTTOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO1_STATUS_OUTFROMPERI |
| // Description : output signal from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_BITS 0x00000100 |
| #define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_MSB 8 |
| #define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_LSB 8 |
| #define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO1_CTRL |
| // Description : GPIO control including function select and overrides. |
| #define IO_BANK0_GPIO1_CTRL_OFFSET 0x0000000c |
| #define IO_BANK0_GPIO1_CTRL_BITS 0x3003331f |
| #define IO_BANK0_GPIO1_CTRL_RESET 0x0000001f |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO1_CTRL_IRQOVER |
| // Description : 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO1_CTRL_IRQOVER_RESET 0x0 |
| #define IO_BANK0_GPIO1_CTRL_IRQOVER_BITS 0x30000000 |
| #define IO_BANK0_GPIO1_CTRL_IRQOVER_MSB 29 |
| #define IO_BANK0_GPIO1_CTRL_IRQOVER_LSB 28 |
| #define IO_BANK0_GPIO1_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO1_CTRL_INOVER |
| // Description : 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO1_CTRL_INOVER_RESET 0x0 |
| #define IO_BANK0_GPIO1_CTRL_INOVER_BITS 0x00030000 |
| #define IO_BANK0_GPIO1_CTRL_INOVER_MSB 17 |
| #define IO_BANK0_GPIO1_CTRL_INOVER_LSB 16 |
| #define IO_BANK0_GPIO1_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO1_CTRL_OEOVER |
| // Description : 0x0 -> drive output enable from peripheral signal selected by |
| // funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal |
| // selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO1_CTRL_OEOVER_RESET 0x0 |
| #define IO_BANK0_GPIO1_CTRL_OEOVER_BITS 0x00003000 |
| #define IO_BANK0_GPIO1_CTRL_OEOVER_MSB 13 |
| #define IO_BANK0_GPIO1_CTRL_OEOVER_LSB 12 |
| #define IO_BANK0_GPIO1_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_DISABLE 0x2 |
| #define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_ENABLE 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO1_CTRL_OUTOVER |
| // Description : 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected |
| // by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO1_CTRL_OUTOVER_RESET 0x0 |
| #define IO_BANK0_GPIO1_CTRL_OUTOVER_BITS 0x00000300 |
| #define IO_BANK0_GPIO1_CTRL_OUTOVER_MSB 9 |
| #define IO_BANK0_GPIO1_CTRL_OUTOVER_LSB 8 |
| #define IO_BANK0_GPIO1_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO1_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x00 -> jtag_tms |
| // 0x01 -> spi0_ss_n |
| // 0x02 -> uart0_rx |
| // 0x03 -> i2c0_scl |
| // 0x04 -> pwm_b_0 |
| // 0x05 -> sio_1 |
| // 0x06 -> pio0_1 |
| // 0x07 -> pio1_1 |
| // 0x09 -> usb_muxing_vbus_detect |
| // 0x1f -> null |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_RESET 0x1f |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_BITS 0x0000001f |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_MSB 4 |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_LSB 0 |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_JTAG_TMS 0x00 |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SPI0_SS_N 0x01 |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_UART0_RX 0x02 |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PWM_B_0 0x04 |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SIO_1 0x05 |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO0_1 0x06 |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO1_1 0x07 |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_NULL 0x1f |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO2_STATUS |
| // Description : GPIO status |
| #define IO_BANK0_GPIO2_STATUS_OFFSET 0x00000010 |
| #define IO_BANK0_GPIO2_STATUS_BITS 0x050a3300 |
| #define IO_BANK0_GPIO2_STATUS_RESET 0x00000000 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO2_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO2_STATUS_IRQTOPROC_RESET 0x0 |
| #define IO_BANK0_GPIO2_STATUS_IRQTOPROC_BITS 0x04000000 |
| #define IO_BANK0_GPIO2_STATUS_IRQTOPROC_MSB 26 |
| #define IO_BANK0_GPIO2_STATUS_IRQTOPROC_LSB 26 |
| #define IO_BANK0_GPIO2_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO2_STATUS_IRQFROMPAD |
| // Description : interrupt from pad before override is applied |
| #define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_BITS 0x01000000 |
| #define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_MSB 24 |
| #define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_LSB 24 |
| #define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO2_STATUS_INTOPERI |
| // Description : input signal to peripheral, after override is applied |
| #define IO_BANK0_GPIO2_STATUS_INTOPERI_RESET 0x0 |
| #define IO_BANK0_GPIO2_STATUS_INTOPERI_BITS 0x00080000 |
| #define IO_BANK0_GPIO2_STATUS_INTOPERI_MSB 19 |
| #define IO_BANK0_GPIO2_STATUS_INTOPERI_LSB 19 |
| #define IO_BANK0_GPIO2_STATUS_INTOPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO2_STATUS_INFROMPAD |
| // Description : input signal from pad, before override is applied |
| #define IO_BANK0_GPIO2_STATUS_INFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO2_STATUS_INFROMPAD_BITS 0x00020000 |
| #define IO_BANK0_GPIO2_STATUS_INFROMPAD_MSB 17 |
| #define IO_BANK0_GPIO2_STATUS_INFROMPAD_LSB 17 |
| #define IO_BANK0_GPIO2_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO2_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO2_STATUS_OETOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO2_STATUS_OETOPAD_BITS 0x00002000 |
| #define IO_BANK0_GPIO2_STATUS_OETOPAD_MSB 13 |
| #define IO_BANK0_GPIO2_STATUS_OETOPAD_LSB 13 |
| #define IO_BANK0_GPIO2_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO2_STATUS_OEFROMPERI |
| // Description : output enable from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO2_STATUS_OEFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO2_STATUS_OEFROMPERI_BITS 0x00001000 |
| #define IO_BANK0_GPIO2_STATUS_OEFROMPERI_MSB 12 |
| #define IO_BANK0_GPIO2_STATUS_OEFROMPERI_LSB 12 |
| #define IO_BANK0_GPIO2_STATUS_OEFROMPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO2_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO2_STATUS_OUTTOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO2_STATUS_OUTTOPAD_BITS 0x00000200 |
| #define IO_BANK0_GPIO2_STATUS_OUTTOPAD_MSB 9 |
| #define IO_BANK0_GPIO2_STATUS_OUTTOPAD_LSB 9 |
| #define IO_BANK0_GPIO2_STATUS_OUTTOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO2_STATUS_OUTFROMPERI |
| // Description : output signal from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_BITS 0x00000100 |
| #define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_MSB 8 |
| #define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_LSB 8 |
| #define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO2_CTRL |
| // Description : GPIO control including function select and overrides. |
| #define IO_BANK0_GPIO2_CTRL_OFFSET 0x00000014 |
| #define IO_BANK0_GPIO2_CTRL_BITS 0x3003331f |
| #define IO_BANK0_GPIO2_CTRL_RESET 0x0000001f |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO2_CTRL_IRQOVER |
| // Description : 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO2_CTRL_IRQOVER_RESET 0x0 |
| #define IO_BANK0_GPIO2_CTRL_IRQOVER_BITS 0x30000000 |
| #define IO_BANK0_GPIO2_CTRL_IRQOVER_MSB 29 |
| #define IO_BANK0_GPIO2_CTRL_IRQOVER_LSB 28 |
| #define IO_BANK0_GPIO2_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO2_CTRL_INOVER |
| // Description : 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO2_CTRL_INOVER_RESET 0x0 |
| #define IO_BANK0_GPIO2_CTRL_INOVER_BITS 0x00030000 |
| #define IO_BANK0_GPIO2_CTRL_INOVER_MSB 17 |
| #define IO_BANK0_GPIO2_CTRL_INOVER_LSB 16 |
| #define IO_BANK0_GPIO2_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO2_CTRL_OEOVER |
| // Description : 0x0 -> drive output enable from peripheral signal selected by |
| // funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal |
| // selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO2_CTRL_OEOVER_RESET 0x0 |
| #define IO_BANK0_GPIO2_CTRL_OEOVER_BITS 0x00003000 |
| #define IO_BANK0_GPIO2_CTRL_OEOVER_MSB 13 |
| #define IO_BANK0_GPIO2_CTRL_OEOVER_LSB 12 |
| #define IO_BANK0_GPIO2_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_DISABLE 0x2 |
| #define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_ENABLE 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO2_CTRL_OUTOVER |
| // Description : 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected |
| // by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO2_CTRL_OUTOVER_RESET 0x0 |
| #define IO_BANK0_GPIO2_CTRL_OUTOVER_BITS 0x00000300 |
| #define IO_BANK0_GPIO2_CTRL_OUTOVER_MSB 9 |
| #define IO_BANK0_GPIO2_CTRL_OUTOVER_LSB 8 |
| #define IO_BANK0_GPIO2_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO2_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x00 -> jtag_tdi |
| // 0x01 -> spi0_sclk |
| // 0x02 -> uart0_cts |
| // 0x03 -> i2c1_sda |
| // 0x04 -> pwm_a_1 |
| // 0x05 -> sio_2 |
| // 0x06 -> pio0_2 |
| // 0x07 -> pio1_2 |
| // 0x09 -> usb_muxing_vbus_en |
| // 0x1f -> null |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_RESET 0x1f |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_BITS 0x0000001f |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_MSB 4 |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_LSB 0 |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_JTAG_TDI 0x00 |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SPI0_SCLK 0x01 |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_CTS 0x02 |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PWM_A_1 0x04 |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SIO_2 0x05 |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO0_2 0x06 |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO1_2 0x07 |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_NULL 0x1f |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO3_STATUS |
| // Description : GPIO status |
| #define IO_BANK0_GPIO3_STATUS_OFFSET 0x00000018 |
| #define IO_BANK0_GPIO3_STATUS_BITS 0x050a3300 |
| #define IO_BANK0_GPIO3_STATUS_RESET 0x00000000 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO3_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO3_STATUS_IRQTOPROC_RESET 0x0 |
| #define IO_BANK0_GPIO3_STATUS_IRQTOPROC_BITS 0x04000000 |
| #define IO_BANK0_GPIO3_STATUS_IRQTOPROC_MSB 26 |
| #define IO_BANK0_GPIO3_STATUS_IRQTOPROC_LSB 26 |
| #define IO_BANK0_GPIO3_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO3_STATUS_IRQFROMPAD |
| // Description : interrupt from pad before override is applied |
| #define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_BITS 0x01000000 |
| #define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_MSB 24 |
| #define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_LSB 24 |
| #define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO3_STATUS_INTOPERI |
| // Description : input signal to peripheral, after override is applied |
| #define IO_BANK0_GPIO3_STATUS_INTOPERI_RESET 0x0 |
| #define IO_BANK0_GPIO3_STATUS_INTOPERI_BITS 0x00080000 |
| #define IO_BANK0_GPIO3_STATUS_INTOPERI_MSB 19 |
| #define IO_BANK0_GPIO3_STATUS_INTOPERI_LSB 19 |
| #define IO_BANK0_GPIO3_STATUS_INTOPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO3_STATUS_INFROMPAD |
| // Description : input signal from pad, before override is applied |
| #define IO_BANK0_GPIO3_STATUS_INFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO3_STATUS_INFROMPAD_BITS 0x00020000 |
| #define IO_BANK0_GPIO3_STATUS_INFROMPAD_MSB 17 |
| #define IO_BANK0_GPIO3_STATUS_INFROMPAD_LSB 17 |
| #define IO_BANK0_GPIO3_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO3_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO3_STATUS_OETOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO3_STATUS_OETOPAD_BITS 0x00002000 |
| #define IO_BANK0_GPIO3_STATUS_OETOPAD_MSB 13 |
| #define IO_BANK0_GPIO3_STATUS_OETOPAD_LSB 13 |
| #define IO_BANK0_GPIO3_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO3_STATUS_OEFROMPERI |
| // Description : output enable from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO3_STATUS_OEFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO3_STATUS_OEFROMPERI_BITS 0x00001000 |
| #define IO_BANK0_GPIO3_STATUS_OEFROMPERI_MSB 12 |
| #define IO_BANK0_GPIO3_STATUS_OEFROMPERI_LSB 12 |
| #define IO_BANK0_GPIO3_STATUS_OEFROMPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO3_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO3_STATUS_OUTTOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO3_STATUS_OUTTOPAD_BITS 0x00000200 |
| #define IO_BANK0_GPIO3_STATUS_OUTTOPAD_MSB 9 |
| #define IO_BANK0_GPIO3_STATUS_OUTTOPAD_LSB 9 |
| #define IO_BANK0_GPIO3_STATUS_OUTTOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO3_STATUS_OUTFROMPERI |
| // Description : output signal from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_BITS 0x00000100 |
| #define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_MSB 8 |
| #define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_LSB 8 |
| #define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO3_CTRL |
| // Description : GPIO control including function select and overrides. |
| #define IO_BANK0_GPIO3_CTRL_OFFSET 0x0000001c |
| #define IO_BANK0_GPIO3_CTRL_BITS 0x3003331f |
| #define IO_BANK0_GPIO3_CTRL_RESET 0x0000001f |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO3_CTRL_IRQOVER |
| // Description : 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO3_CTRL_IRQOVER_RESET 0x0 |
| #define IO_BANK0_GPIO3_CTRL_IRQOVER_BITS 0x30000000 |
| #define IO_BANK0_GPIO3_CTRL_IRQOVER_MSB 29 |
| #define IO_BANK0_GPIO3_CTRL_IRQOVER_LSB 28 |
| #define IO_BANK0_GPIO3_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO3_CTRL_INOVER |
| // Description : 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO3_CTRL_INOVER_RESET 0x0 |
| #define IO_BANK0_GPIO3_CTRL_INOVER_BITS 0x00030000 |
| #define IO_BANK0_GPIO3_CTRL_INOVER_MSB 17 |
| #define IO_BANK0_GPIO3_CTRL_INOVER_LSB 16 |
| #define IO_BANK0_GPIO3_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO3_CTRL_OEOVER |
| // Description : 0x0 -> drive output enable from peripheral signal selected by |
| // funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal |
| // selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO3_CTRL_OEOVER_RESET 0x0 |
| #define IO_BANK0_GPIO3_CTRL_OEOVER_BITS 0x00003000 |
| #define IO_BANK0_GPIO3_CTRL_OEOVER_MSB 13 |
| #define IO_BANK0_GPIO3_CTRL_OEOVER_LSB 12 |
| #define IO_BANK0_GPIO3_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_DISABLE 0x2 |
| #define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_ENABLE 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO3_CTRL_OUTOVER |
| // Description : 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected |
| // by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO3_CTRL_OUTOVER_RESET 0x0 |
| #define IO_BANK0_GPIO3_CTRL_OUTOVER_BITS 0x00000300 |
| #define IO_BANK0_GPIO3_CTRL_OUTOVER_MSB 9 |
| #define IO_BANK0_GPIO3_CTRL_OUTOVER_LSB 8 |
| #define IO_BANK0_GPIO3_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO3_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x00 -> jtag_tdo |
| // 0x01 -> spi0_tx |
| // 0x02 -> uart0_rts |
| // 0x03 -> i2c1_scl |
| // 0x04 -> pwm_b_1 |
| // 0x05 -> sio_3 |
| // 0x06 -> pio0_3 |
| // 0x07 -> pio1_3 |
| // 0x09 -> usb_muxing_overcurr_detect |
| // 0x1f -> null |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_RESET 0x1f |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_BITS 0x0000001f |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_MSB 4 |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_LSB 0 |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_JTAG_TDO 0x00 |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SPI0_TX 0x01 |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RTS 0x02 |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PWM_B_1 0x04 |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SIO_3 0x05 |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO0_3 0x06 |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO1_3 0x07 |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_NULL 0x1f |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO4_STATUS |
| // Description : GPIO status |
| #define IO_BANK0_GPIO4_STATUS_OFFSET 0x00000020 |
| #define IO_BANK0_GPIO4_STATUS_BITS 0x050a3300 |
| #define IO_BANK0_GPIO4_STATUS_RESET 0x00000000 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO4_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO4_STATUS_IRQTOPROC_RESET 0x0 |
| #define IO_BANK0_GPIO4_STATUS_IRQTOPROC_BITS 0x04000000 |
| #define IO_BANK0_GPIO4_STATUS_IRQTOPROC_MSB 26 |
| #define IO_BANK0_GPIO4_STATUS_IRQTOPROC_LSB 26 |
| #define IO_BANK0_GPIO4_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO4_STATUS_IRQFROMPAD |
| // Description : interrupt from pad before override is applied |
| #define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_BITS 0x01000000 |
| #define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_MSB 24 |
| #define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_LSB 24 |
| #define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO4_STATUS_INTOPERI |
| // Description : input signal to peripheral, after override is applied |
| #define IO_BANK0_GPIO4_STATUS_INTOPERI_RESET 0x0 |
| #define IO_BANK0_GPIO4_STATUS_INTOPERI_BITS 0x00080000 |
| #define IO_BANK0_GPIO4_STATUS_INTOPERI_MSB 19 |
| #define IO_BANK0_GPIO4_STATUS_INTOPERI_LSB 19 |
| #define IO_BANK0_GPIO4_STATUS_INTOPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO4_STATUS_INFROMPAD |
| // Description : input signal from pad, before override is applied |
| #define IO_BANK0_GPIO4_STATUS_INFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO4_STATUS_INFROMPAD_BITS 0x00020000 |
| #define IO_BANK0_GPIO4_STATUS_INFROMPAD_MSB 17 |
| #define IO_BANK0_GPIO4_STATUS_INFROMPAD_LSB 17 |
| #define IO_BANK0_GPIO4_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO4_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO4_STATUS_OETOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO4_STATUS_OETOPAD_BITS 0x00002000 |
| #define IO_BANK0_GPIO4_STATUS_OETOPAD_MSB 13 |
| #define IO_BANK0_GPIO4_STATUS_OETOPAD_LSB 13 |
| #define IO_BANK0_GPIO4_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO4_STATUS_OEFROMPERI |
| // Description : output enable from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO4_STATUS_OEFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO4_STATUS_OEFROMPERI_BITS 0x00001000 |
| #define IO_BANK0_GPIO4_STATUS_OEFROMPERI_MSB 12 |
| #define IO_BANK0_GPIO4_STATUS_OEFROMPERI_LSB 12 |
| #define IO_BANK0_GPIO4_STATUS_OEFROMPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO4_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO4_STATUS_OUTTOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO4_STATUS_OUTTOPAD_BITS 0x00000200 |
| #define IO_BANK0_GPIO4_STATUS_OUTTOPAD_MSB 9 |
| #define IO_BANK0_GPIO4_STATUS_OUTTOPAD_LSB 9 |
| #define IO_BANK0_GPIO4_STATUS_OUTTOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO4_STATUS_OUTFROMPERI |
| // Description : output signal from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_BITS 0x00000100 |
| #define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_MSB 8 |
| #define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_LSB 8 |
| #define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO4_CTRL |
| // Description : GPIO control including function select and overrides. |
| #define IO_BANK0_GPIO4_CTRL_OFFSET 0x00000024 |
| #define IO_BANK0_GPIO4_CTRL_BITS 0x3003331f |
| #define IO_BANK0_GPIO4_CTRL_RESET 0x0000001f |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO4_CTRL_IRQOVER |
| // Description : 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO4_CTRL_IRQOVER_RESET 0x0 |
| #define IO_BANK0_GPIO4_CTRL_IRQOVER_BITS 0x30000000 |
| #define IO_BANK0_GPIO4_CTRL_IRQOVER_MSB 29 |
| #define IO_BANK0_GPIO4_CTRL_IRQOVER_LSB 28 |
| #define IO_BANK0_GPIO4_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO4_CTRL_INOVER |
| // Description : 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO4_CTRL_INOVER_RESET 0x0 |
| #define IO_BANK0_GPIO4_CTRL_INOVER_BITS 0x00030000 |
| #define IO_BANK0_GPIO4_CTRL_INOVER_MSB 17 |
| #define IO_BANK0_GPIO4_CTRL_INOVER_LSB 16 |
| #define IO_BANK0_GPIO4_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO4_CTRL_OEOVER |
| // Description : 0x0 -> drive output enable from peripheral signal selected by |
| // funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal |
| // selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO4_CTRL_OEOVER_RESET 0x0 |
| #define IO_BANK0_GPIO4_CTRL_OEOVER_BITS 0x00003000 |
| #define IO_BANK0_GPIO4_CTRL_OEOVER_MSB 13 |
| #define IO_BANK0_GPIO4_CTRL_OEOVER_LSB 12 |
| #define IO_BANK0_GPIO4_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_DISABLE 0x2 |
| #define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_ENABLE 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO4_CTRL_OUTOVER |
| // Description : 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected |
| // by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO4_CTRL_OUTOVER_RESET 0x0 |
| #define IO_BANK0_GPIO4_CTRL_OUTOVER_BITS 0x00000300 |
| #define IO_BANK0_GPIO4_CTRL_OUTOVER_MSB 9 |
| #define IO_BANK0_GPIO4_CTRL_OUTOVER_LSB 8 |
| #define IO_BANK0_GPIO4_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO4_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x01 -> spi0_rx |
| // 0x02 -> uart1_tx |
| // 0x03 -> i2c0_sda |
| // 0x04 -> pwm_a_2 |
| // 0x05 -> sio_4 |
| // 0x06 -> pio0_4 |
| // 0x07 -> pio1_4 |
| // 0x09 -> usb_muxing_vbus_detect |
| // 0x1f -> null |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_RESET 0x1f |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_BITS 0x0000001f |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_MSB 4 |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_LSB 0 |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SPI0_RX 0x01 |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_UART1_TX 0x02 |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PWM_A_2 0x04 |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SIO_4 0x05 |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO0_4 0x06 |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO1_4 0x07 |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_NULL 0x1f |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO5_STATUS |
| // Description : GPIO status |
| #define IO_BANK0_GPIO5_STATUS_OFFSET 0x00000028 |
| #define IO_BANK0_GPIO5_STATUS_BITS 0x050a3300 |
| #define IO_BANK0_GPIO5_STATUS_RESET 0x00000000 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO5_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO5_STATUS_IRQTOPROC_RESET 0x0 |
| #define IO_BANK0_GPIO5_STATUS_IRQTOPROC_BITS 0x04000000 |
| #define IO_BANK0_GPIO5_STATUS_IRQTOPROC_MSB 26 |
| #define IO_BANK0_GPIO5_STATUS_IRQTOPROC_LSB 26 |
| #define IO_BANK0_GPIO5_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO5_STATUS_IRQFROMPAD |
| // Description : interrupt from pad before override is applied |
| #define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_BITS 0x01000000 |
| #define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_MSB 24 |
| #define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_LSB 24 |
| #define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO5_STATUS_INTOPERI |
| // Description : input signal to peripheral, after override is applied |
| #define IO_BANK0_GPIO5_STATUS_INTOPERI_RESET 0x0 |
| #define IO_BANK0_GPIO5_STATUS_INTOPERI_BITS 0x00080000 |
| #define IO_BANK0_GPIO5_STATUS_INTOPERI_MSB 19 |
| #define IO_BANK0_GPIO5_STATUS_INTOPERI_LSB 19 |
| #define IO_BANK0_GPIO5_STATUS_INTOPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO5_STATUS_INFROMPAD |
| // Description : input signal from pad, before override is applied |
| #define IO_BANK0_GPIO5_STATUS_INFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO5_STATUS_INFROMPAD_BITS 0x00020000 |
| #define IO_BANK0_GPIO5_STATUS_INFROMPAD_MSB 17 |
| #define IO_BANK0_GPIO5_STATUS_INFROMPAD_LSB 17 |
| #define IO_BANK0_GPIO5_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO5_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO5_STATUS_OETOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO5_STATUS_OETOPAD_BITS 0x00002000 |
| #define IO_BANK0_GPIO5_STATUS_OETOPAD_MSB 13 |
| #define IO_BANK0_GPIO5_STATUS_OETOPAD_LSB 13 |
| #define IO_BANK0_GPIO5_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO5_STATUS_OEFROMPERI |
| // Description : output enable from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO5_STATUS_OEFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO5_STATUS_OEFROMPERI_BITS 0x00001000 |
| #define IO_BANK0_GPIO5_STATUS_OEFROMPERI_MSB 12 |
| #define IO_BANK0_GPIO5_STATUS_OEFROMPERI_LSB 12 |
| #define IO_BANK0_GPIO5_STATUS_OEFROMPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO5_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO5_STATUS_OUTTOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO5_STATUS_OUTTOPAD_BITS 0x00000200 |
| #define IO_BANK0_GPIO5_STATUS_OUTTOPAD_MSB 9 |
| #define IO_BANK0_GPIO5_STATUS_OUTTOPAD_LSB 9 |
| #define IO_BANK0_GPIO5_STATUS_OUTTOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO5_STATUS_OUTFROMPERI |
| // Description : output signal from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_BITS 0x00000100 |
| #define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_MSB 8 |
| #define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_LSB 8 |
| #define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO5_CTRL |
| // Description : GPIO control including function select and overrides. |
| #define IO_BANK0_GPIO5_CTRL_OFFSET 0x0000002c |
| #define IO_BANK0_GPIO5_CTRL_BITS 0x3003331f |
| #define IO_BANK0_GPIO5_CTRL_RESET 0x0000001f |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO5_CTRL_IRQOVER |
| // Description : 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO5_CTRL_IRQOVER_RESET 0x0 |
| #define IO_BANK0_GPIO5_CTRL_IRQOVER_BITS 0x30000000 |
| #define IO_BANK0_GPIO5_CTRL_IRQOVER_MSB 29 |
| #define IO_BANK0_GPIO5_CTRL_IRQOVER_LSB 28 |
| #define IO_BANK0_GPIO5_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO5_CTRL_INOVER |
| // Description : 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO5_CTRL_INOVER_RESET 0x0 |
| #define IO_BANK0_GPIO5_CTRL_INOVER_BITS 0x00030000 |
| #define IO_BANK0_GPIO5_CTRL_INOVER_MSB 17 |
| #define IO_BANK0_GPIO5_CTRL_INOVER_LSB 16 |
| #define IO_BANK0_GPIO5_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO5_CTRL_OEOVER |
| // Description : 0x0 -> drive output enable from peripheral signal selected by |
| // funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal |
| // selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO5_CTRL_OEOVER_RESET 0x0 |
| #define IO_BANK0_GPIO5_CTRL_OEOVER_BITS 0x00003000 |
| #define IO_BANK0_GPIO5_CTRL_OEOVER_MSB 13 |
| #define IO_BANK0_GPIO5_CTRL_OEOVER_LSB 12 |
| #define IO_BANK0_GPIO5_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_DISABLE 0x2 |
| #define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_ENABLE 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO5_CTRL_OUTOVER |
| // Description : 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected |
| // by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO5_CTRL_OUTOVER_RESET 0x0 |
| #define IO_BANK0_GPIO5_CTRL_OUTOVER_BITS 0x00000300 |
| #define IO_BANK0_GPIO5_CTRL_OUTOVER_MSB 9 |
| #define IO_BANK0_GPIO5_CTRL_OUTOVER_LSB 8 |
| #define IO_BANK0_GPIO5_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO5_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x01 -> spi0_ss_n |
| // 0x02 -> uart1_rx |
| // 0x03 -> i2c0_scl |
| // 0x04 -> pwm_b_2 |
| // 0x05 -> sio_5 |
| // 0x06 -> pio0_5 |
| // 0x07 -> pio1_5 |
| // 0x09 -> usb_muxing_vbus_en |
| // 0x1f -> null |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_RESET 0x1f |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_BITS 0x0000001f |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_MSB 4 |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_LSB 0 |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SPI0_SS_N 0x01 |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_UART1_RX 0x02 |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PWM_B_2 0x04 |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SIO_5 0x05 |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO0_5 0x06 |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO1_5 0x07 |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_NULL 0x1f |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO6_STATUS |
| // Description : GPIO status |
| #define IO_BANK0_GPIO6_STATUS_OFFSET 0x00000030 |
| #define IO_BANK0_GPIO6_STATUS_BITS 0x050a3300 |
| #define IO_BANK0_GPIO6_STATUS_RESET 0x00000000 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO6_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO6_STATUS_IRQTOPROC_RESET 0x0 |
| #define IO_BANK0_GPIO6_STATUS_IRQTOPROC_BITS 0x04000000 |
| #define IO_BANK0_GPIO6_STATUS_IRQTOPROC_MSB 26 |
| #define IO_BANK0_GPIO6_STATUS_IRQTOPROC_LSB 26 |
| #define IO_BANK0_GPIO6_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO6_STATUS_IRQFROMPAD |
| // Description : interrupt from pad before override is applied |
| #define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_BITS 0x01000000 |
| #define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_MSB 24 |
| #define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_LSB 24 |
| #define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO6_STATUS_INTOPERI |
| // Description : input signal to peripheral, after override is applied |
| #define IO_BANK0_GPIO6_STATUS_INTOPERI_RESET 0x0 |
| #define IO_BANK0_GPIO6_STATUS_INTOPERI_BITS 0x00080000 |
| #define IO_BANK0_GPIO6_STATUS_INTOPERI_MSB 19 |
| #define IO_BANK0_GPIO6_STATUS_INTOPERI_LSB 19 |
| #define IO_BANK0_GPIO6_STATUS_INTOPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO6_STATUS_INFROMPAD |
| // Description : input signal from pad, before override is applied |
| #define IO_BANK0_GPIO6_STATUS_INFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO6_STATUS_INFROMPAD_BITS 0x00020000 |
| #define IO_BANK0_GPIO6_STATUS_INFROMPAD_MSB 17 |
| #define IO_BANK0_GPIO6_STATUS_INFROMPAD_LSB 17 |
| #define IO_BANK0_GPIO6_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO6_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO6_STATUS_OETOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO6_STATUS_OETOPAD_BITS 0x00002000 |
| #define IO_BANK0_GPIO6_STATUS_OETOPAD_MSB 13 |
| #define IO_BANK0_GPIO6_STATUS_OETOPAD_LSB 13 |
| #define IO_BANK0_GPIO6_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO6_STATUS_OEFROMPERI |
| // Description : output enable from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO6_STATUS_OEFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO6_STATUS_OEFROMPERI_BITS 0x00001000 |
| #define IO_BANK0_GPIO6_STATUS_OEFROMPERI_MSB 12 |
| #define IO_BANK0_GPIO6_STATUS_OEFROMPERI_LSB 12 |
| #define IO_BANK0_GPIO6_STATUS_OEFROMPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO6_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO6_STATUS_OUTTOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO6_STATUS_OUTTOPAD_BITS 0x00000200 |
| #define IO_BANK0_GPIO6_STATUS_OUTTOPAD_MSB 9 |
| #define IO_BANK0_GPIO6_STATUS_OUTTOPAD_LSB 9 |
| #define IO_BANK0_GPIO6_STATUS_OUTTOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO6_STATUS_OUTFROMPERI |
| // Description : output signal from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_BITS 0x00000100 |
| #define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_MSB 8 |
| #define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_LSB 8 |
| #define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO6_CTRL |
| // Description : GPIO control including function select and overrides. |
| #define IO_BANK0_GPIO6_CTRL_OFFSET 0x00000034 |
| #define IO_BANK0_GPIO6_CTRL_BITS 0x3003331f |
| #define IO_BANK0_GPIO6_CTRL_RESET 0x0000001f |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO6_CTRL_IRQOVER |
| // Description : 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO6_CTRL_IRQOVER_RESET 0x0 |
| #define IO_BANK0_GPIO6_CTRL_IRQOVER_BITS 0x30000000 |
| #define IO_BANK0_GPIO6_CTRL_IRQOVER_MSB 29 |
| #define IO_BANK0_GPIO6_CTRL_IRQOVER_LSB 28 |
| #define IO_BANK0_GPIO6_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO6_CTRL_INOVER |
| // Description : 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO6_CTRL_INOVER_RESET 0x0 |
| #define IO_BANK0_GPIO6_CTRL_INOVER_BITS 0x00030000 |
| #define IO_BANK0_GPIO6_CTRL_INOVER_MSB 17 |
| #define IO_BANK0_GPIO6_CTRL_INOVER_LSB 16 |
| #define IO_BANK0_GPIO6_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO6_CTRL_OEOVER |
| // Description : 0x0 -> drive output enable from peripheral signal selected by |
| // funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal |
| // selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO6_CTRL_OEOVER_RESET 0x0 |
| #define IO_BANK0_GPIO6_CTRL_OEOVER_BITS 0x00003000 |
| #define IO_BANK0_GPIO6_CTRL_OEOVER_MSB 13 |
| #define IO_BANK0_GPIO6_CTRL_OEOVER_LSB 12 |
| #define IO_BANK0_GPIO6_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_DISABLE 0x2 |
| #define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_ENABLE 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO6_CTRL_OUTOVER |
| // Description : 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected |
| // by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO6_CTRL_OUTOVER_RESET 0x0 |
| #define IO_BANK0_GPIO6_CTRL_OUTOVER_BITS 0x00000300 |
| #define IO_BANK0_GPIO6_CTRL_OUTOVER_MSB 9 |
| #define IO_BANK0_GPIO6_CTRL_OUTOVER_LSB 8 |
| #define IO_BANK0_GPIO6_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO6_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x01 -> spi0_sclk |
| // 0x02 -> uart1_cts |
| // 0x03 -> i2c1_sda |
| // 0x04 -> pwm_a_3 |
| // 0x05 -> sio_6 |
| // 0x06 -> pio0_6 |
| // 0x07 -> pio1_6 |
| // 0x08 -> usb_muxing_extphy_softcon |
| // 0x09 -> usb_muxing_overcurr_detect |
| // 0x1f -> null |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_RESET 0x1f |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_BITS 0x0000001f |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_MSB 4 |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_LSB 0 |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SPI0_SCLK 0x01 |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_CTS 0x02 |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PWM_A_3 0x04 |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SIO_6 0x05 |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO0_6 0x06 |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO1_6 0x07 |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SOFTCON 0x08 |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_NULL 0x1f |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO7_STATUS |
| // Description : GPIO status |
| #define IO_BANK0_GPIO7_STATUS_OFFSET 0x00000038 |
| #define IO_BANK0_GPIO7_STATUS_BITS 0x050a3300 |
| #define IO_BANK0_GPIO7_STATUS_RESET 0x00000000 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO7_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO7_STATUS_IRQTOPROC_RESET 0x0 |
| #define IO_BANK0_GPIO7_STATUS_IRQTOPROC_BITS 0x04000000 |
| #define IO_BANK0_GPIO7_STATUS_IRQTOPROC_MSB 26 |
| #define IO_BANK0_GPIO7_STATUS_IRQTOPROC_LSB 26 |
| #define IO_BANK0_GPIO7_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO7_STATUS_IRQFROMPAD |
| // Description : interrupt from pad before override is applied |
| #define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_BITS 0x01000000 |
| #define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_MSB 24 |
| #define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_LSB 24 |
| #define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO7_STATUS_INTOPERI |
| // Description : input signal to peripheral, after override is applied |
| #define IO_BANK0_GPIO7_STATUS_INTOPERI_RESET 0x0 |
| #define IO_BANK0_GPIO7_STATUS_INTOPERI_BITS 0x00080000 |
| #define IO_BANK0_GPIO7_STATUS_INTOPERI_MSB 19 |
| #define IO_BANK0_GPIO7_STATUS_INTOPERI_LSB 19 |
| #define IO_BANK0_GPIO7_STATUS_INTOPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO7_STATUS_INFROMPAD |
| // Description : input signal from pad, before override is applied |
| #define IO_BANK0_GPIO7_STATUS_INFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO7_STATUS_INFROMPAD_BITS 0x00020000 |
| #define IO_BANK0_GPIO7_STATUS_INFROMPAD_MSB 17 |
| #define IO_BANK0_GPIO7_STATUS_INFROMPAD_LSB 17 |
| #define IO_BANK0_GPIO7_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO7_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO7_STATUS_OETOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO7_STATUS_OETOPAD_BITS 0x00002000 |
| #define IO_BANK0_GPIO7_STATUS_OETOPAD_MSB 13 |
| #define IO_BANK0_GPIO7_STATUS_OETOPAD_LSB 13 |
| #define IO_BANK0_GPIO7_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO7_STATUS_OEFROMPERI |
| // Description : output enable from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO7_STATUS_OEFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO7_STATUS_OEFROMPERI_BITS 0x00001000 |
| #define IO_BANK0_GPIO7_STATUS_OEFROMPERI_MSB 12 |
| #define IO_BANK0_GPIO7_STATUS_OEFROMPERI_LSB 12 |
| #define IO_BANK0_GPIO7_STATUS_OEFROMPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO7_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO7_STATUS_OUTTOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO7_STATUS_OUTTOPAD_BITS 0x00000200 |
| #define IO_BANK0_GPIO7_STATUS_OUTTOPAD_MSB 9 |
| #define IO_BANK0_GPIO7_STATUS_OUTTOPAD_LSB 9 |
| #define IO_BANK0_GPIO7_STATUS_OUTTOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO7_STATUS_OUTFROMPERI |
| // Description : output signal from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_BITS 0x00000100 |
| #define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_MSB 8 |
| #define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_LSB 8 |
| #define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO7_CTRL |
| // Description : GPIO control including function select and overrides. |
| #define IO_BANK0_GPIO7_CTRL_OFFSET 0x0000003c |
| #define IO_BANK0_GPIO7_CTRL_BITS 0x3003331f |
| #define IO_BANK0_GPIO7_CTRL_RESET 0x0000001f |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO7_CTRL_IRQOVER |
| // Description : 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO7_CTRL_IRQOVER_RESET 0x0 |
| #define IO_BANK0_GPIO7_CTRL_IRQOVER_BITS 0x30000000 |
| #define IO_BANK0_GPIO7_CTRL_IRQOVER_MSB 29 |
| #define IO_BANK0_GPIO7_CTRL_IRQOVER_LSB 28 |
| #define IO_BANK0_GPIO7_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO7_CTRL_INOVER |
| // Description : 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO7_CTRL_INOVER_RESET 0x0 |
| #define IO_BANK0_GPIO7_CTRL_INOVER_BITS 0x00030000 |
| #define IO_BANK0_GPIO7_CTRL_INOVER_MSB 17 |
| #define IO_BANK0_GPIO7_CTRL_INOVER_LSB 16 |
| #define IO_BANK0_GPIO7_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO7_CTRL_OEOVER |
| // Description : 0x0 -> drive output enable from peripheral signal selected by |
| // funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal |
| // selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO7_CTRL_OEOVER_RESET 0x0 |
| #define IO_BANK0_GPIO7_CTRL_OEOVER_BITS 0x00003000 |
| #define IO_BANK0_GPIO7_CTRL_OEOVER_MSB 13 |
| #define IO_BANK0_GPIO7_CTRL_OEOVER_LSB 12 |
| #define IO_BANK0_GPIO7_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_DISABLE 0x2 |
| #define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_ENABLE 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO7_CTRL_OUTOVER |
| // Description : 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected |
| // by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO7_CTRL_OUTOVER_RESET 0x0 |
| #define IO_BANK0_GPIO7_CTRL_OUTOVER_BITS 0x00000300 |
| #define IO_BANK0_GPIO7_CTRL_OUTOVER_MSB 9 |
| #define IO_BANK0_GPIO7_CTRL_OUTOVER_LSB 8 |
| #define IO_BANK0_GPIO7_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO7_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x01 -> spi0_tx |
| // 0x02 -> uart1_rts |
| // 0x03 -> i2c1_scl |
| // 0x04 -> pwm_b_3 |
| // 0x05 -> sio_7 |
| // 0x06 -> pio0_7 |
| // 0x07 -> pio1_7 |
| // 0x08 -> usb_muxing_extphy_oe_n |
| // 0x09 -> usb_muxing_vbus_detect |
| // 0x1f -> null |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_RESET 0x1f |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_BITS 0x0000001f |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_MSB 4 |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_LSB 0 |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SPI0_TX 0x01 |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RTS 0x02 |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PWM_B_3 0x04 |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SIO_7 0x05 |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO0_7 0x06 |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO1_7 0x07 |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_OE_N 0x08 |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_NULL 0x1f |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO8_STATUS |
| // Description : GPIO status |
| #define IO_BANK0_GPIO8_STATUS_OFFSET 0x00000040 |
| #define IO_BANK0_GPIO8_STATUS_BITS 0x050a3300 |
| #define IO_BANK0_GPIO8_STATUS_RESET 0x00000000 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO8_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO8_STATUS_IRQTOPROC_RESET 0x0 |
| #define IO_BANK0_GPIO8_STATUS_IRQTOPROC_BITS 0x04000000 |
| #define IO_BANK0_GPIO8_STATUS_IRQTOPROC_MSB 26 |
| #define IO_BANK0_GPIO8_STATUS_IRQTOPROC_LSB 26 |
| #define IO_BANK0_GPIO8_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO8_STATUS_IRQFROMPAD |
| // Description : interrupt from pad before override is applied |
| #define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_BITS 0x01000000 |
| #define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_MSB 24 |
| #define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_LSB 24 |
| #define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO8_STATUS_INTOPERI |
| // Description : input signal to peripheral, after override is applied |
| #define IO_BANK0_GPIO8_STATUS_INTOPERI_RESET 0x0 |
| #define IO_BANK0_GPIO8_STATUS_INTOPERI_BITS 0x00080000 |
| #define IO_BANK0_GPIO8_STATUS_INTOPERI_MSB 19 |
| #define IO_BANK0_GPIO8_STATUS_INTOPERI_LSB 19 |
| #define IO_BANK0_GPIO8_STATUS_INTOPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO8_STATUS_INFROMPAD |
| // Description : input signal from pad, before override is applied |
| #define IO_BANK0_GPIO8_STATUS_INFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO8_STATUS_INFROMPAD_BITS 0x00020000 |
| #define IO_BANK0_GPIO8_STATUS_INFROMPAD_MSB 17 |
| #define IO_BANK0_GPIO8_STATUS_INFROMPAD_LSB 17 |
| #define IO_BANK0_GPIO8_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO8_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO8_STATUS_OETOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO8_STATUS_OETOPAD_BITS 0x00002000 |
| #define IO_BANK0_GPIO8_STATUS_OETOPAD_MSB 13 |
| #define IO_BANK0_GPIO8_STATUS_OETOPAD_LSB 13 |
| #define IO_BANK0_GPIO8_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO8_STATUS_OEFROMPERI |
| // Description : output enable from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO8_STATUS_OEFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO8_STATUS_OEFROMPERI_BITS 0x00001000 |
| #define IO_BANK0_GPIO8_STATUS_OEFROMPERI_MSB 12 |
| #define IO_BANK0_GPIO8_STATUS_OEFROMPERI_LSB 12 |
| #define IO_BANK0_GPIO8_STATUS_OEFROMPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO8_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO8_STATUS_OUTTOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO8_STATUS_OUTTOPAD_BITS 0x00000200 |
| #define IO_BANK0_GPIO8_STATUS_OUTTOPAD_MSB 9 |
| #define IO_BANK0_GPIO8_STATUS_OUTTOPAD_LSB 9 |
| #define IO_BANK0_GPIO8_STATUS_OUTTOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO8_STATUS_OUTFROMPERI |
| // Description : output signal from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_BITS 0x00000100 |
| #define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_MSB 8 |
| #define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_LSB 8 |
| #define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO8_CTRL |
| // Description : GPIO control including function select and overrides. |
| #define IO_BANK0_GPIO8_CTRL_OFFSET 0x00000044 |
| #define IO_BANK0_GPIO8_CTRL_BITS 0x3003331f |
| #define IO_BANK0_GPIO8_CTRL_RESET 0x0000001f |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO8_CTRL_IRQOVER |
| // Description : 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO8_CTRL_IRQOVER_RESET 0x0 |
| #define IO_BANK0_GPIO8_CTRL_IRQOVER_BITS 0x30000000 |
| #define IO_BANK0_GPIO8_CTRL_IRQOVER_MSB 29 |
| #define IO_BANK0_GPIO8_CTRL_IRQOVER_LSB 28 |
| #define IO_BANK0_GPIO8_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO8_CTRL_INOVER |
| // Description : 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO8_CTRL_INOVER_RESET 0x0 |
| #define IO_BANK0_GPIO8_CTRL_INOVER_BITS 0x00030000 |
| #define IO_BANK0_GPIO8_CTRL_INOVER_MSB 17 |
| #define IO_BANK0_GPIO8_CTRL_INOVER_LSB 16 |
| #define IO_BANK0_GPIO8_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO8_CTRL_OEOVER |
| // Description : 0x0 -> drive output enable from peripheral signal selected by |
| // funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal |
| // selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO8_CTRL_OEOVER_RESET 0x0 |
| #define IO_BANK0_GPIO8_CTRL_OEOVER_BITS 0x00003000 |
| #define IO_BANK0_GPIO8_CTRL_OEOVER_MSB 13 |
| #define IO_BANK0_GPIO8_CTRL_OEOVER_LSB 12 |
| #define IO_BANK0_GPIO8_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_DISABLE 0x2 |
| #define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_ENABLE 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO8_CTRL_OUTOVER |
| // Description : 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected |
| // by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO8_CTRL_OUTOVER_RESET 0x0 |
| #define IO_BANK0_GPIO8_CTRL_OUTOVER_BITS 0x00000300 |
| #define IO_BANK0_GPIO8_CTRL_OUTOVER_MSB 9 |
| #define IO_BANK0_GPIO8_CTRL_OUTOVER_LSB 8 |
| #define IO_BANK0_GPIO8_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO8_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x01 -> spi1_rx |
| // 0x02 -> uart1_tx |
| // 0x03 -> i2c0_sda |
| // 0x04 -> pwm_a_4 |
| // 0x05 -> sio_8 |
| // 0x06 -> pio0_8 |
| // 0x07 -> pio1_8 |
| // 0x08 -> usb_muxing_extphy_rcv |
| // 0x09 -> usb_muxing_vbus_en |
| // 0x1f -> null |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_RESET 0x1f |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_BITS 0x0000001f |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_MSB 4 |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_LSB 0 |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SPI1_RX 0x01 |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_UART1_TX 0x02 |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PWM_A_4 0x04 |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SIO_8 0x05 |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO0_8 0x06 |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO1_8 0x07 |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_RCV 0x08 |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_NULL 0x1f |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO9_STATUS |
| // Description : GPIO status |
| #define IO_BANK0_GPIO9_STATUS_OFFSET 0x00000048 |
| #define IO_BANK0_GPIO9_STATUS_BITS 0x050a3300 |
| #define IO_BANK0_GPIO9_STATUS_RESET 0x00000000 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO9_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO9_STATUS_IRQTOPROC_RESET 0x0 |
| #define IO_BANK0_GPIO9_STATUS_IRQTOPROC_BITS 0x04000000 |
| #define IO_BANK0_GPIO9_STATUS_IRQTOPROC_MSB 26 |
| #define IO_BANK0_GPIO9_STATUS_IRQTOPROC_LSB 26 |
| #define IO_BANK0_GPIO9_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO9_STATUS_IRQFROMPAD |
| // Description : interrupt from pad before override is applied |
| #define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_BITS 0x01000000 |
| #define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_MSB 24 |
| #define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_LSB 24 |
| #define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO9_STATUS_INTOPERI |
| // Description : input signal to peripheral, after override is applied |
| #define IO_BANK0_GPIO9_STATUS_INTOPERI_RESET 0x0 |
| #define IO_BANK0_GPIO9_STATUS_INTOPERI_BITS 0x00080000 |
| #define IO_BANK0_GPIO9_STATUS_INTOPERI_MSB 19 |
| #define IO_BANK0_GPIO9_STATUS_INTOPERI_LSB 19 |
| #define IO_BANK0_GPIO9_STATUS_INTOPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO9_STATUS_INFROMPAD |
| // Description : input signal from pad, before override is applied |
| #define IO_BANK0_GPIO9_STATUS_INFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO9_STATUS_INFROMPAD_BITS 0x00020000 |
| #define IO_BANK0_GPIO9_STATUS_INFROMPAD_MSB 17 |
| #define IO_BANK0_GPIO9_STATUS_INFROMPAD_LSB 17 |
| #define IO_BANK0_GPIO9_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO9_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO9_STATUS_OETOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO9_STATUS_OETOPAD_BITS 0x00002000 |
| #define IO_BANK0_GPIO9_STATUS_OETOPAD_MSB 13 |
| #define IO_BANK0_GPIO9_STATUS_OETOPAD_LSB 13 |
| #define IO_BANK0_GPIO9_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO9_STATUS_OEFROMPERI |
| // Description : output enable from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO9_STATUS_OEFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO9_STATUS_OEFROMPERI_BITS 0x00001000 |
| #define IO_BANK0_GPIO9_STATUS_OEFROMPERI_MSB 12 |
| #define IO_BANK0_GPIO9_STATUS_OEFROMPERI_LSB 12 |
| #define IO_BANK0_GPIO9_STATUS_OEFROMPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO9_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO9_STATUS_OUTTOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO9_STATUS_OUTTOPAD_BITS 0x00000200 |
| #define IO_BANK0_GPIO9_STATUS_OUTTOPAD_MSB 9 |
| #define IO_BANK0_GPIO9_STATUS_OUTTOPAD_LSB 9 |
| #define IO_BANK0_GPIO9_STATUS_OUTTOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO9_STATUS_OUTFROMPERI |
| // Description : output signal from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_BITS 0x00000100 |
| #define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_MSB 8 |
| #define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_LSB 8 |
| #define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO9_CTRL |
| // Description : GPIO control including function select and overrides. |
| #define IO_BANK0_GPIO9_CTRL_OFFSET 0x0000004c |
| #define IO_BANK0_GPIO9_CTRL_BITS 0x3003331f |
| #define IO_BANK0_GPIO9_CTRL_RESET 0x0000001f |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO9_CTRL_IRQOVER |
| // Description : 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO9_CTRL_IRQOVER_RESET 0x0 |
| #define IO_BANK0_GPIO9_CTRL_IRQOVER_BITS 0x30000000 |
| #define IO_BANK0_GPIO9_CTRL_IRQOVER_MSB 29 |
| #define IO_BANK0_GPIO9_CTRL_IRQOVER_LSB 28 |
| #define IO_BANK0_GPIO9_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO9_CTRL_INOVER |
| // Description : 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO9_CTRL_INOVER_RESET 0x0 |
| #define IO_BANK0_GPIO9_CTRL_INOVER_BITS 0x00030000 |
| #define IO_BANK0_GPIO9_CTRL_INOVER_MSB 17 |
| #define IO_BANK0_GPIO9_CTRL_INOVER_LSB 16 |
| #define IO_BANK0_GPIO9_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO9_CTRL_OEOVER |
| // Description : 0x0 -> drive output enable from peripheral signal selected by |
| // funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal |
| // selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO9_CTRL_OEOVER_RESET 0x0 |
| #define IO_BANK0_GPIO9_CTRL_OEOVER_BITS 0x00003000 |
| #define IO_BANK0_GPIO9_CTRL_OEOVER_MSB 13 |
| #define IO_BANK0_GPIO9_CTRL_OEOVER_LSB 12 |
| #define IO_BANK0_GPIO9_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_DISABLE 0x2 |
| #define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_ENABLE 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO9_CTRL_OUTOVER |
| // Description : 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected |
| // by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO9_CTRL_OUTOVER_RESET 0x0 |
| #define IO_BANK0_GPIO9_CTRL_OUTOVER_BITS 0x00000300 |
| #define IO_BANK0_GPIO9_CTRL_OUTOVER_MSB 9 |
| #define IO_BANK0_GPIO9_CTRL_OUTOVER_LSB 8 |
| #define IO_BANK0_GPIO9_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO9_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x01 -> spi1_ss_n |
| // 0x02 -> uart1_rx |
| // 0x03 -> i2c0_scl |
| // 0x04 -> pwm_b_4 |
| // 0x05 -> sio_9 |
| // 0x06 -> pio0_9 |
| // 0x07 -> pio1_9 |
| // 0x08 -> usb_muxing_extphy_vp |
| // 0x09 -> usb_muxing_overcurr_detect |
| // 0x1f -> null |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_RESET 0x1f |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_BITS 0x0000001f |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_MSB 4 |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_LSB 0 |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SPI1_SS_N 0x01 |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_UART1_RX 0x02 |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PWM_B_4 0x04 |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SIO_9 0x05 |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO0_9 0x06 |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO1_9 0x07 |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VP 0x08 |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_NULL 0x1f |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO10_STATUS |
| // Description : GPIO status |
| #define IO_BANK0_GPIO10_STATUS_OFFSET 0x00000050 |
| #define IO_BANK0_GPIO10_STATUS_BITS 0x050a3300 |
| #define IO_BANK0_GPIO10_STATUS_RESET 0x00000000 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO10_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO10_STATUS_IRQTOPROC_RESET 0x0 |
| #define IO_BANK0_GPIO10_STATUS_IRQTOPROC_BITS 0x04000000 |
| #define IO_BANK0_GPIO10_STATUS_IRQTOPROC_MSB 26 |
| #define IO_BANK0_GPIO10_STATUS_IRQTOPROC_LSB 26 |
| #define IO_BANK0_GPIO10_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO10_STATUS_IRQFROMPAD |
| // Description : interrupt from pad before override is applied |
| #define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_BITS 0x01000000 |
| #define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_MSB 24 |
| #define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_LSB 24 |
| #define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO10_STATUS_INTOPERI |
| // Description : input signal to peripheral, after override is applied |
| #define IO_BANK0_GPIO10_STATUS_INTOPERI_RESET 0x0 |
| #define IO_BANK0_GPIO10_STATUS_INTOPERI_BITS 0x00080000 |
| #define IO_BANK0_GPIO10_STATUS_INTOPERI_MSB 19 |
| #define IO_BANK0_GPIO10_STATUS_INTOPERI_LSB 19 |
| #define IO_BANK0_GPIO10_STATUS_INTOPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO10_STATUS_INFROMPAD |
| // Description : input signal from pad, before override is applied |
| #define IO_BANK0_GPIO10_STATUS_INFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO10_STATUS_INFROMPAD_BITS 0x00020000 |
| #define IO_BANK0_GPIO10_STATUS_INFROMPAD_MSB 17 |
| #define IO_BANK0_GPIO10_STATUS_INFROMPAD_LSB 17 |
| #define IO_BANK0_GPIO10_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO10_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO10_STATUS_OETOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO10_STATUS_OETOPAD_BITS 0x00002000 |
| #define IO_BANK0_GPIO10_STATUS_OETOPAD_MSB 13 |
| #define IO_BANK0_GPIO10_STATUS_OETOPAD_LSB 13 |
| #define IO_BANK0_GPIO10_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO10_STATUS_OEFROMPERI |
| // Description : output enable from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO10_STATUS_OEFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO10_STATUS_OEFROMPERI_BITS 0x00001000 |
| #define IO_BANK0_GPIO10_STATUS_OEFROMPERI_MSB 12 |
| #define IO_BANK0_GPIO10_STATUS_OEFROMPERI_LSB 12 |
| #define IO_BANK0_GPIO10_STATUS_OEFROMPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO10_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO10_STATUS_OUTTOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO10_STATUS_OUTTOPAD_BITS 0x00000200 |
| #define IO_BANK0_GPIO10_STATUS_OUTTOPAD_MSB 9 |
| #define IO_BANK0_GPIO10_STATUS_OUTTOPAD_LSB 9 |
| #define IO_BANK0_GPIO10_STATUS_OUTTOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO10_STATUS_OUTFROMPERI |
| // Description : output signal from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_BITS 0x00000100 |
| #define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_MSB 8 |
| #define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_LSB 8 |
| #define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO10_CTRL |
| // Description : GPIO control including function select and overrides. |
| #define IO_BANK0_GPIO10_CTRL_OFFSET 0x00000054 |
| #define IO_BANK0_GPIO10_CTRL_BITS 0x3003331f |
| #define IO_BANK0_GPIO10_CTRL_RESET 0x0000001f |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO10_CTRL_IRQOVER |
| // Description : 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO10_CTRL_IRQOVER_RESET 0x0 |
| #define IO_BANK0_GPIO10_CTRL_IRQOVER_BITS 0x30000000 |
| #define IO_BANK0_GPIO10_CTRL_IRQOVER_MSB 29 |
| #define IO_BANK0_GPIO10_CTRL_IRQOVER_LSB 28 |
| #define IO_BANK0_GPIO10_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO10_CTRL_INOVER |
| // Description : 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO10_CTRL_INOVER_RESET 0x0 |
| #define IO_BANK0_GPIO10_CTRL_INOVER_BITS 0x00030000 |
| #define IO_BANK0_GPIO10_CTRL_INOVER_MSB 17 |
| #define IO_BANK0_GPIO10_CTRL_INOVER_LSB 16 |
| #define IO_BANK0_GPIO10_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO10_CTRL_OEOVER |
| // Description : 0x0 -> drive output enable from peripheral signal selected by |
| // funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal |
| // selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO10_CTRL_OEOVER_RESET 0x0 |
| #define IO_BANK0_GPIO10_CTRL_OEOVER_BITS 0x00003000 |
| #define IO_BANK0_GPIO10_CTRL_OEOVER_MSB 13 |
| #define IO_BANK0_GPIO10_CTRL_OEOVER_LSB 12 |
| #define IO_BANK0_GPIO10_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_DISABLE 0x2 |
| #define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_ENABLE 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO10_CTRL_OUTOVER |
| // Description : 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected |
| // by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO10_CTRL_OUTOVER_RESET 0x0 |
| #define IO_BANK0_GPIO10_CTRL_OUTOVER_BITS 0x00000300 |
| #define IO_BANK0_GPIO10_CTRL_OUTOVER_MSB 9 |
| #define IO_BANK0_GPIO10_CTRL_OUTOVER_LSB 8 |
| #define IO_BANK0_GPIO10_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO10_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x01 -> spi1_sclk |
| // 0x02 -> uart1_cts |
| // 0x03 -> i2c1_sda |
| // 0x04 -> pwm_a_5 |
| // 0x05 -> sio_10 |
| // 0x06 -> pio0_10 |
| // 0x07 -> pio1_10 |
| // 0x08 -> usb_muxing_extphy_vm |
| // 0x09 -> usb_muxing_vbus_detect |
| // 0x1f -> null |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_RESET 0x1f |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_BITS 0x0000001f |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_MSB 4 |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_LSB 0 |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SPI1_SCLK 0x01 |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_CTS 0x02 |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PWM_A_5 0x04 |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SIO_10 0x05 |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO0_10 0x06 |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO1_10 0x07 |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VM 0x08 |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_NULL 0x1f |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO11_STATUS |
| // Description : GPIO status |
| #define IO_BANK0_GPIO11_STATUS_OFFSET 0x00000058 |
| #define IO_BANK0_GPIO11_STATUS_BITS 0x050a3300 |
| #define IO_BANK0_GPIO11_STATUS_RESET 0x00000000 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO11_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO11_STATUS_IRQTOPROC_RESET 0x0 |
| #define IO_BANK0_GPIO11_STATUS_IRQTOPROC_BITS 0x04000000 |
| #define IO_BANK0_GPIO11_STATUS_IRQTOPROC_MSB 26 |
| #define IO_BANK0_GPIO11_STATUS_IRQTOPROC_LSB 26 |
| #define IO_BANK0_GPIO11_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO11_STATUS_IRQFROMPAD |
| // Description : interrupt from pad before override is applied |
| #define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_BITS 0x01000000 |
| #define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_MSB 24 |
| #define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_LSB 24 |
| #define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO11_STATUS_INTOPERI |
| // Description : input signal to peripheral, after override is applied |
| #define IO_BANK0_GPIO11_STATUS_INTOPERI_RESET 0x0 |
| #define IO_BANK0_GPIO11_STATUS_INTOPERI_BITS 0x00080000 |
| #define IO_BANK0_GPIO11_STATUS_INTOPERI_MSB 19 |
| #define IO_BANK0_GPIO11_STATUS_INTOPERI_LSB 19 |
| #define IO_BANK0_GPIO11_STATUS_INTOPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO11_STATUS_INFROMPAD |
| // Description : input signal from pad, before override is applied |
| #define IO_BANK0_GPIO11_STATUS_INFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO11_STATUS_INFROMPAD_BITS 0x00020000 |
| #define IO_BANK0_GPIO11_STATUS_INFROMPAD_MSB 17 |
| #define IO_BANK0_GPIO11_STATUS_INFROMPAD_LSB 17 |
| #define IO_BANK0_GPIO11_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO11_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO11_STATUS_OETOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO11_STATUS_OETOPAD_BITS 0x00002000 |
| #define IO_BANK0_GPIO11_STATUS_OETOPAD_MSB 13 |
| #define IO_BANK0_GPIO11_STATUS_OETOPAD_LSB 13 |
| #define IO_BANK0_GPIO11_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO11_STATUS_OEFROMPERI |
| // Description : output enable from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO11_STATUS_OEFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO11_STATUS_OEFROMPERI_BITS 0x00001000 |
| #define IO_BANK0_GPIO11_STATUS_OEFROMPERI_MSB 12 |
| #define IO_BANK0_GPIO11_STATUS_OEFROMPERI_LSB 12 |
| #define IO_BANK0_GPIO11_STATUS_OEFROMPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO11_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO11_STATUS_OUTTOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO11_STATUS_OUTTOPAD_BITS 0x00000200 |
| #define IO_BANK0_GPIO11_STATUS_OUTTOPAD_MSB 9 |
| #define IO_BANK0_GPIO11_STATUS_OUTTOPAD_LSB 9 |
| #define IO_BANK0_GPIO11_STATUS_OUTTOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO11_STATUS_OUTFROMPERI |
| // Description : output signal from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_BITS 0x00000100 |
| #define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_MSB 8 |
| #define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_LSB 8 |
| #define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO11_CTRL |
| // Description : GPIO control including function select and overrides. |
| #define IO_BANK0_GPIO11_CTRL_OFFSET 0x0000005c |
| #define IO_BANK0_GPIO11_CTRL_BITS 0x3003331f |
| #define IO_BANK0_GPIO11_CTRL_RESET 0x0000001f |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO11_CTRL_IRQOVER |
| // Description : 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO11_CTRL_IRQOVER_RESET 0x0 |
| #define IO_BANK0_GPIO11_CTRL_IRQOVER_BITS 0x30000000 |
| #define IO_BANK0_GPIO11_CTRL_IRQOVER_MSB 29 |
| #define IO_BANK0_GPIO11_CTRL_IRQOVER_LSB 28 |
| #define IO_BANK0_GPIO11_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO11_CTRL_INOVER |
| // Description : 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO11_CTRL_INOVER_RESET 0x0 |
| #define IO_BANK0_GPIO11_CTRL_INOVER_BITS 0x00030000 |
| #define IO_BANK0_GPIO11_CTRL_INOVER_MSB 17 |
| #define IO_BANK0_GPIO11_CTRL_INOVER_LSB 16 |
| #define IO_BANK0_GPIO11_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO11_CTRL_OEOVER |
| // Description : 0x0 -> drive output enable from peripheral signal selected by |
| // funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal |
| // selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO11_CTRL_OEOVER_RESET 0x0 |
| #define IO_BANK0_GPIO11_CTRL_OEOVER_BITS 0x00003000 |
| #define IO_BANK0_GPIO11_CTRL_OEOVER_MSB 13 |
| #define IO_BANK0_GPIO11_CTRL_OEOVER_LSB 12 |
| #define IO_BANK0_GPIO11_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_DISABLE 0x2 |
| #define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_ENABLE 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO11_CTRL_OUTOVER |
| // Description : 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected |
| // by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO11_CTRL_OUTOVER_RESET 0x0 |
| #define IO_BANK0_GPIO11_CTRL_OUTOVER_BITS 0x00000300 |
| #define IO_BANK0_GPIO11_CTRL_OUTOVER_MSB 9 |
| #define IO_BANK0_GPIO11_CTRL_OUTOVER_LSB 8 |
| #define IO_BANK0_GPIO11_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO11_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x01 -> spi1_tx |
| // 0x02 -> uart1_rts |
| // 0x03 -> i2c1_scl |
| // 0x04 -> pwm_b_5 |
| // 0x05 -> sio_11 |
| // 0x06 -> pio0_11 |
| // 0x07 -> pio1_11 |
| // 0x08 -> usb_muxing_extphy_suspnd |
| // 0x09 -> usb_muxing_vbus_en |
| // 0x1f -> null |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_RESET 0x1f |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_BITS 0x0000001f |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_MSB 4 |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_LSB 0 |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SPI1_TX 0x01 |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RTS 0x02 |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PWM_B_5 0x04 |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SIO_11 0x05 |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO0_11 0x06 |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO1_11 0x07 |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SUSPND 0x08 |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_NULL 0x1f |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO12_STATUS |
| // Description : GPIO status |
| #define IO_BANK0_GPIO12_STATUS_OFFSET 0x00000060 |
| #define IO_BANK0_GPIO12_STATUS_BITS 0x050a3300 |
| #define IO_BANK0_GPIO12_STATUS_RESET 0x00000000 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO12_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO12_STATUS_IRQTOPROC_RESET 0x0 |
| #define IO_BANK0_GPIO12_STATUS_IRQTOPROC_BITS 0x04000000 |
| #define IO_BANK0_GPIO12_STATUS_IRQTOPROC_MSB 26 |
| #define IO_BANK0_GPIO12_STATUS_IRQTOPROC_LSB 26 |
| #define IO_BANK0_GPIO12_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO12_STATUS_IRQFROMPAD |
| // Description : interrupt from pad before override is applied |
| #define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_BITS 0x01000000 |
| #define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_MSB 24 |
| #define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_LSB 24 |
| #define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO12_STATUS_INTOPERI |
| // Description : input signal to peripheral, after override is applied |
| #define IO_BANK0_GPIO12_STATUS_INTOPERI_RESET 0x0 |
| #define IO_BANK0_GPIO12_STATUS_INTOPERI_BITS 0x00080000 |
| #define IO_BANK0_GPIO12_STATUS_INTOPERI_MSB 19 |
| #define IO_BANK0_GPIO12_STATUS_INTOPERI_LSB 19 |
| #define IO_BANK0_GPIO12_STATUS_INTOPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO12_STATUS_INFROMPAD |
| // Description : input signal from pad, before override is applied |
| #define IO_BANK0_GPIO12_STATUS_INFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO12_STATUS_INFROMPAD_BITS 0x00020000 |
| #define IO_BANK0_GPIO12_STATUS_INFROMPAD_MSB 17 |
| #define IO_BANK0_GPIO12_STATUS_INFROMPAD_LSB 17 |
| #define IO_BANK0_GPIO12_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO12_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO12_STATUS_OETOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO12_STATUS_OETOPAD_BITS 0x00002000 |
| #define IO_BANK0_GPIO12_STATUS_OETOPAD_MSB 13 |
| #define IO_BANK0_GPIO12_STATUS_OETOPAD_LSB 13 |
| #define IO_BANK0_GPIO12_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO12_STATUS_OEFROMPERI |
| // Description : output enable from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO12_STATUS_OEFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO12_STATUS_OEFROMPERI_BITS 0x00001000 |
| #define IO_BANK0_GPIO12_STATUS_OEFROMPERI_MSB 12 |
| #define IO_BANK0_GPIO12_STATUS_OEFROMPERI_LSB 12 |
| #define IO_BANK0_GPIO12_STATUS_OEFROMPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO12_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO12_STATUS_OUTTOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO12_STATUS_OUTTOPAD_BITS 0x00000200 |
| #define IO_BANK0_GPIO12_STATUS_OUTTOPAD_MSB 9 |
| #define IO_BANK0_GPIO12_STATUS_OUTTOPAD_LSB 9 |
| #define IO_BANK0_GPIO12_STATUS_OUTTOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO12_STATUS_OUTFROMPERI |
| // Description : output signal from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_BITS 0x00000100 |
| #define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_MSB 8 |
| #define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_LSB 8 |
| #define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO12_CTRL |
| // Description : GPIO control including function select and overrides. |
| #define IO_BANK0_GPIO12_CTRL_OFFSET 0x00000064 |
| #define IO_BANK0_GPIO12_CTRL_BITS 0x3003331f |
| #define IO_BANK0_GPIO12_CTRL_RESET 0x0000001f |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO12_CTRL_IRQOVER |
| // Description : 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO12_CTRL_IRQOVER_RESET 0x0 |
| #define IO_BANK0_GPIO12_CTRL_IRQOVER_BITS 0x30000000 |
| #define IO_BANK0_GPIO12_CTRL_IRQOVER_MSB 29 |
| #define IO_BANK0_GPIO12_CTRL_IRQOVER_LSB 28 |
| #define IO_BANK0_GPIO12_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO12_CTRL_INOVER |
| // Description : 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO12_CTRL_INOVER_RESET 0x0 |
| #define IO_BANK0_GPIO12_CTRL_INOVER_BITS 0x00030000 |
| #define IO_BANK0_GPIO12_CTRL_INOVER_MSB 17 |
| #define IO_BANK0_GPIO12_CTRL_INOVER_LSB 16 |
| #define IO_BANK0_GPIO12_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO12_CTRL_OEOVER |
| // Description : 0x0 -> drive output enable from peripheral signal selected by |
| // funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal |
| // selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO12_CTRL_OEOVER_RESET 0x0 |
| #define IO_BANK0_GPIO12_CTRL_OEOVER_BITS 0x00003000 |
| #define IO_BANK0_GPIO12_CTRL_OEOVER_MSB 13 |
| #define IO_BANK0_GPIO12_CTRL_OEOVER_LSB 12 |
| #define IO_BANK0_GPIO12_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_DISABLE 0x2 |
| #define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_ENABLE 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO12_CTRL_OUTOVER |
| // Description : 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected |
| // by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO12_CTRL_OUTOVER_RESET 0x0 |
| #define IO_BANK0_GPIO12_CTRL_OUTOVER_BITS 0x00000300 |
| #define IO_BANK0_GPIO12_CTRL_OUTOVER_MSB 9 |
| #define IO_BANK0_GPIO12_CTRL_OUTOVER_LSB 8 |
| #define IO_BANK0_GPIO12_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO12_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x01 -> spi1_rx |
| // 0x02 -> uart0_tx |
| // 0x03 -> i2c0_sda |
| // 0x04 -> pwm_a_6 |
| // 0x05 -> sio_12 |
| // 0x06 -> pio0_12 |
| // 0x07 -> pio1_12 |
| // 0x08 -> usb_muxing_extphy_speed |
| // 0x09 -> usb_muxing_overcurr_detect |
| // 0x1f -> null |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_RESET 0x1f |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_BITS 0x0000001f |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_MSB 4 |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_LSB 0 |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SPI1_RX 0x01 |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_UART0_TX 0x02 |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PWM_A_6 0x04 |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SIO_12 0x05 |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO0_12 0x06 |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO1_12 0x07 |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SPEED 0x08 |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_NULL 0x1f |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO13_STATUS |
| // Description : GPIO status |
| #define IO_BANK0_GPIO13_STATUS_OFFSET 0x00000068 |
| #define IO_BANK0_GPIO13_STATUS_BITS 0x050a3300 |
| #define IO_BANK0_GPIO13_STATUS_RESET 0x00000000 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO13_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO13_STATUS_IRQTOPROC_RESET 0x0 |
| #define IO_BANK0_GPIO13_STATUS_IRQTOPROC_BITS 0x04000000 |
| #define IO_BANK0_GPIO13_STATUS_IRQTOPROC_MSB 26 |
| #define IO_BANK0_GPIO13_STATUS_IRQTOPROC_LSB 26 |
| #define IO_BANK0_GPIO13_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO13_STATUS_IRQFROMPAD |
| // Description : interrupt from pad before override is applied |
| #define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_BITS 0x01000000 |
| #define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_MSB 24 |
| #define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_LSB 24 |
| #define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO13_STATUS_INTOPERI |
| // Description : input signal to peripheral, after override is applied |
| #define IO_BANK0_GPIO13_STATUS_INTOPERI_RESET 0x0 |
| #define IO_BANK0_GPIO13_STATUS_INTOPERI_BITS 0x00080000 |
| #define IO_BANK0_GPIO13_STATUS_INTOPERI_MSB 19 |
| #define IO_BANK0_GPIO13_STATUS_INTOPERI_LSB 19 |
| #define IO_BANK0_GPIO13_STATUS_INTOPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO13_STATUS_INFROMPAD |
| // Description : input signal from pad, before override is applied |
| #define IO_BANK0_GPIO13_STATUS_INFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO13_STATUS_INFROMPAD_BITS 0x00020000 |
| #define IO_BANK0_GPIO13_STATUS_INFROMPAD_MSB 17 |
| #define IO_BANK0_GPIO13_STATUS_INFROMPAD_LSB 17 |
| #define IO_BANK0_GPIO13_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO13_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO13_STATUS_OETOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO13_STATUS_OETOPAD_BITS 0x00002000 |
| #define IO_BANK0_GPIO13_STATUS_OETOPAD_MSB 13 |
| #define IO_BANK0_GPIO13_STATUS_OETOPAD_LSB 13 |
| #define IO_BANK0_GPIO13_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO13_STATUS_OEFROMPERI |
| // Description : output enable from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO13_STATUS_OEFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO13_STATUS_OEFROMPERI_BITS 0x00001000 |
| #define IO_BANK0_GPIO13_STATUS_OEFROMPERI_MSB 12 |
| #define IO_BANK0_GPIO13_STATUS_OEFROMPERI_LSB 12 |
| #define IO_BANK0_GPIO13_STATUS_OEFROMPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO13_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO13_STATUS_OUTTOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO13_STATUS_OUTTOPAD_BITS 0x00000200 |
| #define IO_BANK0_GPIO13_STATUS_OUTTOPAD_MSB 9 |
| #define IO_BANK0_GPIO13_STATUS_OUTTOPAD_LSB 9 |
| #define IO_BANK0_GPIO13_STATUS_OUTTOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO13_STATUS_OUTFROMPERI |
| // Description : output signal from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_BITS 0x00000100 |
| #define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_MSB 8 |
| #define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_LSB 8 |
| #define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO13_CTRL |
| // Description : GPIO control including function select and overrides. |
| #define IO_BANK0_GPIO13_CTRL_OFFSET 0x0000006c |
| #define IO_BANK0_GPIO13_CTRL_BITS 0x3003331f |
| #define IO_BANK0_GPIO13_CTRL_RESET 0x0000001f |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO13_CTRL_IRQOVER |
| // Description : 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO13_CTRL_IRQOVER_RESET 0x0 |
| #define IO_BANK0_GPIO13_CTRL_IRQOVER_BITS 0x30000000 |
| #define IO_BANK0_GPIO13_CTRL_IRQOVER_MSB 29 |
| #define IO_BANK0_GPIO13_CTRL_IRQOVER_LSB 28 |
| #define IO_BANK0_GPIO13_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO13_CTRL_INOVER |
| // Description : 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO13_CTRL_INOVER_RESET 0x0 |
| #define IO_BANK0_GPIO13_CTRL_INOVER_BITS 0x00030000 |
| #define IO_BANK0_GPIO13_CTRL_INOVER_MSB 17 |
| #define IO_BANK0_GPIO13_CTRL_INOVER_LSB 16 |
| #define IO_BANK0_GPIO13_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO13_CTRL_OEOVER |
| // Description : 0x0 -> drive output enable from peripheral signal selected by |
| // funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal |
| // selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO13_CTRL_OEOVER_RESET 0x0 |
| #define IO_BANK0_GPIO13_CTRL_OEOVER_BITS 0x00003000 |
| #define IO_BANK0_GPIO13_CTRL_OEOVER_MSB 13 |
| #define IO_BANK0_GPIO13_CTRL_OEOVER_LSB 12 |
| #define IO_BANK0_GPIO13_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_DISABLE 0x2 |
| #define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_ENABLE 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO13_CTRL_OUTOVER |
| // Description : 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected |
| // by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO13_CTRL_OUTOVER_RESET 0x0 |
| #define IO_BANK0_GPIO13_CTRL_OUTOVER_BITS 0x00000300 |
| #define IO_BANK0_GPIO13_CTRL_OUTOVER_MSB 9 |
| #define IO_BANK0_GPIO13_CTRL_OUTOVER_LSB 8 |
| #define IO_BANK0_GPIO13_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO13_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x01 -> spi1_ss_n |
| // 0x02 -> uart0_rx |
| // 0x03 -> i2c0_scl |
| // 0x04 -> pwm_b_6 |
| // 0x05 -> sio_13 |
| // 0x06 -> pio0_13 |
| // 0x07 -> pio1_13 |
| // 0x08 -> usb_muxing_extphy_vpo |
| // 0x09 -> usb_muxing_vbus_detect |
| // 0x1f -> null |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_RESET 0x1f |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_BITS 0x0000001f |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_MSB 4 |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_LSB 0 |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SPI1_SS_N 0x01 |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_UART0_RX 0x02 |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PWM_B_6 0x04 |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SIO_13 0x05 |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO0_13 0x06 |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO1_13 0x07 |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VPO 0x08 |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_NULL 0x1f |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO14_STATUS |
| // Description : GPIO status |
| #define IO_BANK0_GPIO14_STATUS_OFFSET 0x00000070 |
| #define IO_BANK0_GPIO14_STATUS_BITS 0x050a3300 |
| #define IO_BANK0_GPIO14_STATUS_RESET 0x00000000 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO14_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO14_STATUS_IRQTOPROC_RESET 0x0 |
| #define IO_BANK0_GPIO14_STATUS_IRQTOPROC_BITS 0x04000000 |
| #define IO_BANK0_GPIO14_STATUS_IRQTOPROC_MSB 26 |
| #define IO_BANK0_GPIO14_STATUS_IRQTOPROC_LSB 26 |
| #define IO_BANK0_GPIO14_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO14_STATUS_IRQFROMPAD |
| // Description : interrupt from pad before override is applied |
| #define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_BITS 0x01000000 |
| #define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_MSB 24 |
| #define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_LSB 24 |
| #define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO14_STATUS_INTOPERI |
| // Description : input signal to peripheral, after override is applied |
| #define IO_BANK0_GPIO14_STATUS_INTOPERI_RESET 0x0 |
| #define IO_BANK0_GPIO14_STATUS_INTOPERI_BITS 0x00080000 |
| #define IO_BANK0_GPIO14_STATUS_INTOPERI_MSB 19 |
| #define IO_BANK0_GPIO14_STATUS_INTOPERI_LSB 19 |
| #define IO_BANK0_GPIO14_STATUS_INTOPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO14_STATUS_INFROMPAD |
| // Description : input signal from pad, before override is applied |
| #define IO_BANK0_GPIO14_STATUS_INFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO14_STATUS_INFROMPAD_BITS 0x00020000 |
| #define IO_BANK0_GPIO14_STATUS_INFROMPAD_MSB 17 |
| #define IO_BANK0_GPIO14_STATUS_INFROMPAD_LSB 17 |
| #define IO_BANK0_GPIO14_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO14_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO14_STATUS_OETOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO14_STATUS_OETOPAD_BITS 0x00002000 |
| #define IO_BANK0_GPIO14_STATUS_OETOPAD_MSB 13 |
| #define IO_BANK0_GPIO14_STATUS_OETOPAD_LSB 13 |
| #define IO_BANK0_GPIO14_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO14_STATUS_OEFROMPERI |
| // Description : output enable from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO14_STATUS_OEFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO14_STATUS_OEFROMPERI_BITS 0x00001000 |
| #define IO_BANK0_GPIO14_STATUS_OEFROMPERI_MSB 12 |
| #define IO_BANK0_GPIO14_STATUS_OEFROMPERI_LSB 12 |
| #define IO_BANK0_GPIO14_STATUS_OEFROMPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO14_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO14_STATUS_OUTTOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO14_STATUS_OUTTOPAD_BITS 0x00000200 |
| #define IO_BANK0_GPIO14_STATUS_OUTTOPAD_MSB 9 |
| #define IO_BANK0_GPIO14_STATUS_OUTTOPAD_LSB 9 |
| #define IO_BANK0_GPIO14_STATUS_OUTTOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO14_STATUS_OUTFROMPERI |
| // Description : output signal from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_BITS 0x00000100 |
| #define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_MSB 8 |
| #define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_LSB 8 |
| #define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO14_CTRL |
| // Description : GPIO control including function select and overrides. |
| #define IO_BANK0_GPIO14_CTRL_OFFSET 0x00000074 |
| #define IO_BANK0_GPIO14_CTRL_BITS 0x3003331f |
| #define IO_BANK0_GPIO14_CTRL_RESET 0x0000001f |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO14_CTRL_IRQOVER |
| // Description : 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO14_CTRL_IRQOVER_RESET 0x0 |
| #define IO_BANK0_GPIO14_CTRL_IRQOVER_BITS 0x30000000 |
| #define IO_BANK0_GPIO14_CTRL_IRQOVER_MSB 29 |
| #define IO_BANK0_GPIO14_CTRL_IRQOVER_LSB 28 |
| #define IO_BANK0_GPIO14_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO14_CTRL_INOVER |
| // Description : 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO14_CTRL_INOVER_RESET 0x0 |
| #define IO_BANK0_GPIO14_CTRL_INOVER_BITS 0x00030000 |
| #define IO_BANK0_GPIO14_CTRL_INOVER_MSB 17 |
| #define IO_BANK0_GPIO14_CTRL_INOVER_LSB 16 |
| #define IO_BANK0_GPIO14_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO14_CTRL_OEOVER |
| // Description : 0x0 -> drive output enable from peripheral signal selected by |
| // funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal |
| // selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO14_CTRL_OEOVER_RESET 0x0 |
| #define IO_BANK0_GPIO14_CTRL_OEOVER_BITS 0x00003000 |
| #define IO_BANK0_GPIO14_CTRL_OEOVER_MSB 13 |
| #define IO_BANK0_GPIO14_CTRL_OEOVER_LSB 12 |
| #define IO_BANK0_GPIO14_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_DISABLE 0x2 |
| #define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_ENABLE 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO14_CTRL_OUTOVER |
| // Description : 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected |
| // by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO14_CTRL_OUTOVER_RESET 0x0 |
| #define IO_BANK0_GPIO14_CTRL_OUTOVER_BITS 0x00000300 |
| #define IO_BANK0_GPIO14_CTRL_OUTOVER_MSB 9 |
| #define IO_BANK0_GPIO14_CTRL_OUTOVER_LSB 8 |
| #define IO_BANK0_GPIO14_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO14_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x01 -> spi1_sclk |
| // 0x02 -> uart0_cts |
| // 0x03 -> i2c1_sda |
| // 0x04 -> pwm_a_7 |
| // 0x05 -> sio_14 |
| // 0x06 -> pio0_14 |
| // 0x07 -> pio1_14 |
| // 0x08 -> usb_muxing_extphy_vmo |
| // 0x09 -> usb_muxing_vbus_en |
| // 0x1f -> null |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_RESET 0x1f |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_BITS 0x0000001f |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_MSB 4 |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_LSB 0 |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SPI1_SCLK 0x01 |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_CTS 0x02 |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PWM_A_7 0x04 |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SIO_14 0x05 |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO0_14 0x06 |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO1_14 0x07 |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VMO 0x08 |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_NULL 0x1f |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO15_STATUS |
| // Description : GPIO status |
| #define IO_BANK0_GPIO15_STATUS_OFFSET 0x00000078 |
| #define IO_BANK0_GPIO15_STATUS_BITS 0x050a3300 |
| #define IO_BANK0_GPIO15_STATUS_RESET 0x00000000 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO15_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO15_STATUS_IRQTOPROC_RESET 0x0 |
| #define IO_BANK0_GPIO15_STATUS_IRQTOPROC_BITS 0x04000000 |
| #define IO_BANK0_GPIO15_STATUS_IRQTOPROC_MSB 26 |
| #define IO_BANK0_GPIO15_STATUS_IRQTOPROC_LSB 26 |
| #define IO_BANK0_GPIO15_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO15_STATUS_IRQFROMPAD |
| // Description : interrupt from pad before override is applied |
| #define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_BITS 0x01000000 |
| #define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_MSB 24 |
| #define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_LSB 24 |
| #define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO15_STATUS_INTOPERI |
| // Description : input signal to peripheral, after override is applied |
| #define IO_BANK0_GPIO15_STATUS_INTOPERI_RESET 0x0 |
| #define IO_BANK0_GPIO15_STATUS_INTOPERI_BITS 0x00080000 |
| #define IO_BANK0_GPIO15_STATUS_INTOPERI_MSB 19 |
| #define IO_BANK0_GPIO15_STATUS_INTOPERI_LSB 19 |
| #define IO_BANK0_GPIO15_STATUS_INTOPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO15_STATUS_INFROMPAD |
| // Description : input signal from pad, before override is applied |
| #define IO_BANK0_GPIO15_STATUS_INFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO15_STATUS_INFROMPAD_BITS 0x00020000 |
| #define IO_BANK0_GPIO15_STATUS_INFROMPAD_MSB 17 |
| #define IO_BANK0_GPIO15_STATUS_INFROMPAD_LSB 17 |
| #define IO_BANK0_GPIO15_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO15_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO15_STATUS_OETOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO15_STATUS_OETOPAD_BITS 0x00002000 |
| #define IO_BANK0_GPIO15_STATUS_OETOPAD_MSB 13 |
| #define IO_BANK0_GPIO15_STATUS_OETOPAD_LSB 13 |
| #define IO_BANK0_GPIO15_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO15_STATUS_OEFROMPERI |
| // Description : output enable from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO15_STATUS_OEFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO15_STATUS_OEFROMPERI_BITS 0x00001000 |
| #define IO_BANK0_GPIO15_STATUS_OEFROMPERI_MSB 12 |
| #define IO_BANK0_GPIO15_STATUS_OEFROMPERI_LSB 12 |
| #define IO_BANK0_GPIO15_STATUS_OEFROMPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO15_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO15_STATUS_OUTTOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO15_STATUS_OUTTOPAD_BITS 0x00000200 |
| #define IO_BANK0_GPIO15_STATUS_OUTTOPAD_MSB 9 |
| #define IO_BANK0_GPIO15_STATUS_OUTTOPAD_LSB 9 |
| #define IO_BANK0_GPIO15_STATUS_OUTTOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO15_STATUS_OUTFROMPERI |
| // Description : output signal from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_BITS 0x00000100 |
| #define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_MSB 8 |
| #define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_LSB 8 |
| #define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO15_CTRL |
| // Description : GPIO control including function select and overrides. |
| #define IO_BANK0_GPIO15_CTRL_OFFSET 0x0000007c |
| #define IO_BANK0_GPIO15_CTRL_BITS 0x3003331f |
| #define IO_BANK0_GPIO15_CTRL_RESET 0x0000001f |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO15_CTRL_IRQOVER |
| // Description : 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO15_CTRL_IRQOVER_RESET 0x0 |
| #define IO_BANK0_GPIO15_CTRL_IRQOVER_BITS 0x30000000 |
| #define IO_BANK0_GPIO15_CTRL_IRQOVER_MSB 29 |
| #define IO_BANK0_GPIO15_CTRL_IRQOVER_LSB 28 |
| #define IO_BANK0_GPIO15_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO15_CTRL_INOVER |
| // Description : 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO15_CTRL_INOVER_RESET 0x0 |
| #define IO_BANK0_GPIO15_CTRL_INOVER_BITS 0x00030000 |
| #define IO_BANK0_GPIO15_CTRL_INOVER_MSB 17 |
| #define IO_BANK0_GPIO15_CTRL_INOVER_LSB 16 |
| #define IO_BANK0_GPIO15_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO15_CTRL_OEOVER |
| // Description : 0x0 -> drive output enable from peripheral signal selected by |
| // funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal |
| // selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO15_CTRL_OEOVER_RESET 0x0 |
| #define IO_BANK0_GPIO15_CTRL_OEOVER_BITS 0x00003000 |
| #define IO_BANK0_GPIO15_CTRL_OEOVER_MSB 13 |
| #define IO_BANK0_GPIO15_CTRL_OEOVER_LSB 12 |
| #define IO_BANK0_GPIO15_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_DISABLE 0x2 |
| #define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_ENABLE 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO15_CTRL_OUTOVER |
| // Description : 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected |
| // by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO15_CTRL_OUTOVER_RESET 0x0 |
| #define IO_BANK0_GPIO15_CTRL_OUTOVER_BITS 0x00000300 |
| #define IO_BANK0_GPIO15_CTRL_OUTOVER_MSB 9 |
| #define IO_BANK0_GPIO15_CTRL_OUTOVER_LSB 8 |
| #define IO_BANK0_GPIO15_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO15_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x01 -> spi1_tx |
| // 0x02 -> uart0_rts |
| // 0x03 -> i2c1_scl |
| // 0x04 -> pwm_b_7 |
| // 0x05 -> sio_15 |
| // 0x06 -> pio0_15 |
| // 0x07 -> pio1_15 |
| // 0x08 -> usb_muxing_digital_dp |
| // 0x09 -> usb_muxing_overcurr_detect |
| // 0x1f -> null |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_RESET 0x1f |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_BITS 0x0000001f |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_MSB 4 |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_LSB 0 |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SPI1_TX 0x01 |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RTS 0x02 |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PWM_B_7 0x04 |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SIO_15 0x05 |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO0_15 0x06 |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO1_15 0x07 |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DP 0x08 |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_NULL 0x1f |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO16_STATUS |
| // Description : GPIO status |
| #define IO_BANK0_GPIO16_STATUS_OFFSET 0x00000080 |
| #define IO_BANK0_GPIO16_STATUS_BITS 0x050a3300 |
| #define IO_BANK0_GPIO16_STATUS_RESET 0x00000000 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO16_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO16_STATUS_IRQTOPROC_RESET 0x0 |
| #define IO_BANK0_GPIO16_STATUS_IRQTOPROC_BITS 0x04000000 |
| #define IO_BANK0_GPIO16_STATUS_IRQTOPROC_MSB 26 |
| #define IO_BANK0_GPIO16_STATUS_IRQTOPROC_LSB 26 |
| #define IO_BANK0_GPIO16_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO16_STATUS_IRQFROMPAD |
| // Description : interrupt from pad before override is applied |
| #define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_BITS 0x01000000 |
| #define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_MSB 24 |
| #define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_LSB 24 |
| #define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO16_STATUS_INTOPERI |
| // Description : input signal to peripheral, after override is applied |
| #define IO_BANK0_GPIO16_STATUS_INTOPERI_RESET 0x0 |
| #define IO_BANK0_GPIO16_STATUS_INTOPERI_BITS 0x00080000 |
| #define IO_BANK0_GPIO16_STATUS_INTOPERI_MSB 19 |
| #define IO_BANK0_GPIO16_STATUS_INTOPERI_LSB 19 |
| #define IO_BANK0_GPIO16_STATUS_INTOPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO16_STATUS_INFROMPAD |
| // Description : input signal from pad, before override is applied |
| #define IO_BANK0_GPIO16_STATUS_INFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO16_STATUS_INFROMPAD_BITS 0x00020000 |
| #define IO_BANK0_GPIO16_STATUS_INFROMPAD_MSB 17 |
| #define IO_BANK0_GPIO16_STATUS_INFROMPAD_LSB 17 |
| #define IO_BANK0_GPIO16_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO16_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO16_STATUS_OETOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO16_STATUS_OETOPAD_BITS 0x00002000 |
| #define IO_BANK0_GPIO16_STATUS_OETOPAD_MSB 13 |
| #define IO_BANK0_GPIO16_STATUS_OETOPAD_LSB 13 |
| #define IO_BANK0_GPIO16_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO16_STATUS_OEFROMPERI |
| // Description : output enable from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO16_STATUS_OEFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO16_STATUS_OEFROMPERI_BITS 0x00001000 |
| #define IO_BANK0_GPIO16_STATUS_OEFROMPERI_MSB 12 |
| #define IO_BANK0_GPIO16_STATUS_OEFROMPERI_LSB 12 |
| #define IO_BANK0_GPIO16_STATUS_OEFROMPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO16_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO16_STATUS_OUTTOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO16_STATUS_OUTTOPAD_BITS 0x00000200 |
| #define IO_BANK0_GPIO16_STATUS_OUTTOPAD_MSB 9 |
| #define IO_BANK0_GPIO16_STATUS_OUTTOPAD_LSB 9 |
| #define IO_BANK0_GPIO16_STATUS_OUTTOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO16_STATUS_OUTFROMPERI |
| // Description : output signal from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_BITS 0x00000100 |
| #define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_MSB 8 |
| #define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_LSB 8 |
| #define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO16_CTRL |
| // Description : GPIO control including function select and overrides. |
| #define IO_BANK0_GPIO16_CTRL_OFFSET 0x00000084 |
| #define IO_BANK0_GPIO16_CTRL_BITS 0x3003331f |
| #define IO_BANK0_GPIO16_CTRL_RESET 0x0000001f |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO16_CTRL_IRQOVER |
| // Description : 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO16_CTRL_IRQOVER_RESET 0x0 |
| #define IO_BANK0_GPIO16_CTRL_IRQOVER_BITS 0x30000000 |
| #define IO_BANK0_GPIO16_CTRL_IRQOVER_MSB 29 |
| #define IO_BANK0_GPIO16_CTRL_IRQOVER_LSB 28 |
| #define IO_BANK0_GPIO16_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO16_CTRL_INOVER |
| // Description : 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO16_CTRL_INOVER_RESET 0x0 |
| #define IO_BANK0_GPIO16_CTRL_INOVER_BITS 0x00030000 |
| #define IO_BANK0_GPIO16_CTRL_INOVER_MSB 17 |
| #define IO_BANK0_GPIO16_CTRL_INOVER_LSB 16 |
| #define IO_BANK0_GPIO16_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO16_CTRL_OEOVER |
| // Description : 0x0 -> drive output enable from peripheral signal selected by |
| // funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal |
| // selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO16_CTRL_OEOVER_RESET 0x0 |
| #define IO_BANK0_GPIO16_CTRL_OEOVER_BITS 0x00003000 |
| #define IO_BANK0_GPIO16_CTRL_OEOVER_MSB 13 |
| #define IO_BANK0_GPIO16_CTRL_OEOVER_LSB 12 |
| #define IO_BANK0_GPIO16_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_DISABLE 0x2 |
| #define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_ENABLE 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO16_CTRL_OUTOVER |
| // Description : 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected |
| // by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO16_CTRL_OUTOVER_RESET 0x0 |
| #define IO_BANK0_GPIO16_CTRL_OUTOVER_BITS 0x00000300 |
| #define IO_BANK0_GPIO16_CTRL_OUTOVER_MSB 9 |
| #define IO_BANK0_GPIO16_CTRL_OUTOVER_LSB 8 |
| #define IO_BANK0_GPIO16_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO16_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x01 -> spi0_rx |
| // 0x02 -> uart0_tx |
| // 0x03 -> i2c0_sda |
| // 0x04 -> pwm_a_0 |
| // 0x05 -> sio_16 |
| // 0x06 -> pio0_16 |
| // 0x07 -> pio1_16 |
| // 0x08 -> usb_muxing_digital_dm |
| // 0x09 -> usb_muxing_vbus_detect |
| // 0x1f -> null |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_RESET 0x1f |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_BITS 0x0000001f |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_MSB 4 |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_LSB 0 |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SPI0_RX 0x01 |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_UART0_TX 0x02 |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PWM_A_0 0x04 |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SIO_16 0x05 |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO0_16 0x06 |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO1_16 0x07 |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DM 0x08 |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_NULL 0x1f |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO17_STATUS |
| // Description : GPIO status |
| #define IO_BANK0_GPIO17_STATUS_OFFSET 0x00000088 |
| #define IO_BANK0_GPIO17_STATUS_BITS 0x050a3300 |
| #define IO_BANK0_GPIO17_STATUS_RESET 0x00000000 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO17_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO17_STATUS_IRQTOPROC_RESET 0x0 |
| #define IO_BANK0_GPIO17_STATUS_IRQTOPROC_BITS 0x04000000 |
| #define IO_BANK0_GPIO17_STATUS_IRQTOPROC_MSB 26 |
| #define IO_BANK0_GPIO17_STATUS_IRQTOPROC_LSB 26 |
| #define IO_BANK0_GPIO17_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO17_STATUS_IRQFROMPAD |
| // Description : interrupt from pad before override is applied |
| #define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_BITS 0x01000000 |
| #define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_MSB 24 |
| #define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_LSB 24 |
| #define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO17_STATUS_INTOPERI |
| // Description : input signal to peripheral, after override is applied |
| #define IO_BANK0_GPIO17_STATUS_INTOPERI_RESET 0x0 |
| #define IO_BANK0_GPIO17_STATUS_INTOPERI_BITS 0x00080000 |
| #define IO_BANK0_GPIO17_STATUS_INTOPERI_MSB 19 |
| #define IO_BANK0_GPIO17_STATUS_INTOPERI_LSB 19 |
| #define IO_BANK0_GPIO17_STATUS_INTOPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO17_STATUS_INFROMPAD |
| // Description : input signal from pad, before override is applied |
| #define IO_BANK0_GPIO17_STATUS_INFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO17_STATUS_INFROMPAD_BITS 0x00020000 |
| #define IO_BANK0_GPIO17_STATUS_INFROMPAD_MSB 17 |
| #define IO_BANK0_GPIO17_STATUS_INFROMPAD_LSB 17 |
| #define IO_BANK0_GPIO17_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO17_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO17_STATUS_OETOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO17_STATUS_OETOPAD_BITS 0x00002000 |
| #define IO_BANK0_GPIO17_STATUS_OETOPAD_MSB 13 |
| #define IO_BANK0_GPIO17_STATUS_OETOPAD_LSB 13 |
| #define IO_BANK0_GPIO17_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO17_STATUS_OEFROMPERI |
| // Description : output enable from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO17_STATUS_OEFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO17_STATUS_OEFROMPERI_BITS 0x00001000 |
| #define IO_BANK0_GPIO17_STATUS_OEFROMPERI_MSB 12 |
| #define IO_BANK0_GPIO17_STATUS_OEFROMPERI_LSB 12 |
| #define IO_BANK0_GPIO17_STATUS_OEFROMPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO17_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO17_STATUS_OUTTOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO17_STATUS_OUTTOPAD_BITS 0x00000200 |
| #define IO_BANK0_GPIO17_STATUS_OUTTOPAD_MSB 9 |
| #define IO_BANK0_GPIO17_STATUS_OUTTOPAD_LSB 9 |
| #define IO_BANK0_GPIO17_STATUS_OUTTOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO17_STATUS_OUTFROMPERI |
| // Description : output signal from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_BITS 0x00000100 |
| #define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_MSB 8 |
| #define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_LSB 8 |
| #define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO17_CTRL |
| // Description : GPIO control including function select and overrides. |
| #define IO_BANK0_GPIO17_CTRL_OFFSET 0x0000008c |
| #define IO_BANK0_GPIO17_CTRL_BITS 0x3003331f |
| #define IO_BANK0_GPIO17_CTRL_RESET 0x0000001f |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO17_CTRL_IRQOVER |
| // Description : 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO17_CTRL_IRQOVER_RESET 0x0 |
| #define IO_BANK0_GPIO17_CTRL_IRQOVER_BITS 0x30000000 |
| #define IO_BANK0_GPIO17_CTRL_IRQOVER_MSB 29 |
| #define IO_BANK0_GPIO17_CTRL_IRQOVER_LSB 28 |
| #define IO_BANK0_GPIO17_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO17_CTRL_INOVER |
| // Description : 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO17_CTRL_INOVER_RESET 0x0 |
| #define IO_BANK0_GPIO17_CTRL_INOVER_BITS 0x00030000 |
| #define IO_BANK0_GPIO17_CTRL_INOVER_MSB 17 |
| #define IO_BANK0_GPIO17_CTRL_INOVER_LSB 16 |
| #define IO_BANK0_GPIO17_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO17_CTRL_OEOVER |
| // Description : 0x0 -> drive output enable from peripheral signal selected by |
| // funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal |
| // selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO17_CTRL_OEOVER_RESET 0x0 |
| #define IO_BANK0_GPIO17_CTRL_OEOVER_BITS 0x00003000 |
| #define IO_BANK0_GPIO17_CTRL_OEOVER_MSB 13 |
| #define IO_BANK0_GPIO17_CTRL_OEOVER_LSB 12 |
| #define IO_BANK0_GPIO17_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_DISABLE 0x2 |
| #define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_ENABLE 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO17_CTRL_OUTOVER |
| // Description : 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected |
| // by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO17_CTRL_OUTOVER_RESET 0x0 |
| #define IO_BANK0_GPIO17_CTRL_OUTOVER_BITS 0x00000300 |
| #define IO_BANK0_GPIO17_CTRL_OUTOVER_MSB 9 |
| #define IO_BANK0_GPIO17_CTRL_OUTOVER_LSB 8 |
| #define IO_BANK0_GPIO17_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO17_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x01 -> spi0_ss_n |
| // 0x02 -> uart0_rx |
| // 0x03 -> i2c0_scl |
| // 0x04 -> pwm_b_0 |
| // 0x05 -> sio_17 |
| // 0x06 -> pio0_17 |
| // 0x07 -> pio1_17 |
| // 0x09 -> usb_muxing_vbus_en |
| // 0x1f -> null |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_RESET 0x1f |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_BITS 0x0000001f |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_MSB 4 |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_LSB 0 |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SPI0_SS_N 0x01 |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_UART0_RX 0x02 |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PWM_B_0 0x04 |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SIO_17 0x05 |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO0_17 0x06 |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO1_17 0x07 |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_NULL 0x1f |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO18_STATUS |
| // Description : GPIO status |
| #define IO_BANK0_GPIO18_STATUS_OFFSET 0x00000090 |
| #define IO_BANK0_GPIO18_STATUS_BITS 0x050a3300 |
| #define IO_BANK0_GPIO18_STATUS_RESET 0x00000000 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO18_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO18_STATUS_IRQTOPROC_RESET 0x0 |
| #define IO_BANK0_GPIO18_STATUS_IRQTOPROC_BITS 0x04000000 |
| #define IO_BANK0_GPIO18_STATUS_IRQTOPROC_MSB 26 |
| #define IO_BANK0_GPIO18_STATUS_IRQTOPROC_LSB 26 |
| #define IO_BANK0_GPIO18_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO18_STATUS_IRQFROMPAD |
| // Description : interrupt from pad before override is applied |
| #define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_BITS 0x01000000 |
| #define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_MSB 24 |
| #define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_LSB 24 |
| #define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO18_STATUS_INTOPERI |
| // Description : input signal to peripheral, after override is applied |
| #define IO_BANK0_GPIO18_STATUS_INTOPERI_RESET 0x0 |
| #define IO_BANK0_GPIO18_STATUS_INTOPERI_BITS 0x00080000 |
| #define IO_BANK0_GPIO18_STATUS_INTOPERI_MSB 19 |
| #define IO_BANK0_GPIO18_STATUS_INTOPERI_LSB 19 |
| #define IO_BANK0_GPIO18_STATUS_INTOPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO18_STATUS_INFROMPAD |
| // Description : input signal from pad, before override is applied |
| #define IO_BANK0_GPIO18_STATUS_INFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO18_STATUS_INFROMPAD_BITS 0x00020000 |
| #define IO_BANK0_GPIO18_STATUS_INFROMPAD_MSB 17 |
| #define IO_BANK0_GPIO18_STATUS_INFROMPAD_LSB 17 |
| #define IO_BANK0_GPIO18_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO18_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO18_STATUS_OETOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO18_STATUS_OETOPAD_BITS 0x00002000 |
| #define IO_BANK0_GPIO18_STATUS_OETOPAD_MSB 13 |
| #define IO_BANK0_GPIO18_STATUS_OETOPAD_LSB 13 |
| #define IO_BANK0_GPIO18_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO18_STATUS_OEFROMPERI |
| // Description : output enable from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO18_STATUS_OEFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO18_STATUS_OEFROMPERI_BITS 0x00001000 |
| #define IO_BANK0_GPIO18_STATUS_OEFROMPERI_MSB 12 |
| #define IO_BANK0_GPIO18_STATUS_OEFROMPERI_LSB 12 |
| #define IO_BANK0_GPIO18_STATUS_OEFROMPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO18_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO18_STATUS_OUTTOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO18_STATUS_OUTTOPAD_BITS 0x00000200 |
| #define IO_BANK0_GPIO18_STATUS_OUTTOPAD_MSB 9 |
| #define IO_BANK0_GPIO18_STATUS_OUTTOPAD_LSB 9 |
| #define IO_BANK0_GPIO18_STATUS_OUTTOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO18_STATUS_OUTFROMPERI |
| // Description : output signal from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_BITS 0x00000100 |
| #define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_MSB 8 |
| #define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_LSB 8 |
| #define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO18_CTRL |
| // Description : GPIO control including function select and overrides. |
| #define IO_BANK0_GPIO18_CTRL_OFFSET 0x00000094 |
| #define IO_BANK0_GPIO18_CTRL_BITS 0x3003331f |
| #define IO_BANK0_GPIO18_CTRL_RESET 0x0000001f |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO18_CTRL_IRQOVER |
| // Description : 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO18_CTRL_IRQOVER_RESET 0x0 |
| #define IO_BANK0_GPIO18_CTRL_IRQOVER_BITS 0x30000000 |
| #define IO_BANK0_GPIO18_CTRL_IRQOVER_MSB 29 |
| #define IO_BANK0_GPIO18_CTRL_IRQOVER_LSB 28 |
| #define IO_BANK0_GPIO18_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO18_CTRL_INOVER |
| // Description : 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO18_CTRL_INOVER_RESET 0x0 |
| #define IO_BANK0_GPIO18_CTRL_INOVER_BITS 0x00030000 |
| #define IO_BANK0_GPIO18_CTRL_INOVER_MSB 17 |
| #define IO_BANK0_GPIO18_CTRL_INOVER_LSB 16 |
| #define IO_BANK0_GPIO18_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO18_CTRL_OEOVER |
| // Description : 0x0 -> drive output enable from peripheral signal selected by |
| // funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal |
| // selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO18_CTRL_OEOVER_RESET 0x0 |
| #define IO_BANK0_GPIO18_CTRL_OEOVER_BITS 0x00003000 |
| #define IO_BANK0_GPIO18_CTRL_OEOVER_MSB 13 |
| #define IO_BANK0_GPIO18_CTRL_OEOVER_LSB 12 |
| #define IO_BANK0_GPIO18_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_DISABLE 0x2 |
| #define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_ENABLE 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO18_CTRL_OUTOVER |
| // Description : 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected |
| // by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO18_CTRL_OUTOVER_RESET 0x0 |
| #define IO_BANK0_GPIO18_CTRL_OUTOVER_BITS 0x00000300 |
| #define IO_BANK0_GPIO18_CTRL_OUTOVER_MSB 9 |
| #define IO_BANK0_GPIO18_CTRL_OUTOVER_LSB 8 |
| #define IO_BANK0_GPIO18_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO18_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x01 -> spi0_sclk |
| // 0x02 -> uart0_cts |
| // 0x03 -> i2c1_sda |
| // 0x04 -> pwm_a_1 |
| // 0x05 -> sio_18 |
| // 0x06 -> pio0_18 |
| // 0x07 -> pio1_18 |
| // 0x09 -> usb_muxing_overcurr_detect |
| // 0x1f -> null |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_RESET 0x1f |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_BITS 0x0000001f |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_MSB 4 |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_LSB 0 |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SPI0_SCLK 0x01 |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_CTS 0x02 |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PWM_A_1 0x04 |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SIO_18 0x05 |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO0_18 0x06 |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO1_18 0x07 |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_NULL 0x1f |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO19_STATUS |
| // Description : GPIO status |
| #define IO_BANK0_GPIO19_STATUS_OFFSET 0x00000098 |
| #define IO_BANK0_GPIO19_STATUS_BITS 0x050a3300 |
| #define IO_BANK0_GPIO19_STATUS_RESET 0x00000000 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO19_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO19_STATUS_IRQTOPROC_RESET 0x0 |
| #define IO_BANK0_GPIO19_STATUS_IRQTOPROC_BITS 0x04000000 |
| #define IO_BANK0_GPIO19_STATUS_IRQTOPROC_MSB 26 |
| #define IO_BANK0_GPIO19_STATUS_IRQTOPROC_LSB 26 |
| #define IO_BANK0_GPIO19_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO19_STATUS_IRQFROMPAD |
| // Description : interrupt from pad before override is applied |
| #define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_BITS 0x01000000 |
| #define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_MSB 24 |
| #define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_LSB 24 |
| #define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO19_STATUS_INTOPERI |
| // Description : input signal to peripheral, after override is applied |
| #define IO_BANK0_GPIO19_STATUS_INTOPERI_RESET 0x0 |
| #define IO_BANK0_GPIO19_STATUS_INTOPERI_BITS 0x00080000 |
| #define IO_BANK0_GPIO19_STATUS_INTOPERI_MSB 19 |
| #define IO_BANK0_GPIO19_STATUS_INTOPERI_LSB 19 |
| #define IO_BANK0_GPIO19_STATUS_INTOPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO19_STATUS_INFROMPAD |
| // Description : input signal from pad, before override is applied |
| #define IO_BANK0_GPIO19_STATUS_INFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO19_STATUS_INFROMPAD_BITS 0x00020000 |
| #define IO_BANK0_GPIO19_STATUS_INFROMPAD_MSB 17 |
| #define IO_BANK0_GPIO19_STATUS_INFROMPAD_LSB 17 |
| #define IO_BANK0_GPIO19_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO19_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO19_STATUS_OETOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO19_STATUS_OETOPAD_BITS 0x00002000 |
| #define IO_BANK0_GPIO19_STATUS_OETOPAD_MSB 13 |
| #define IO_BANK0_GPIO19_STATUS_OETOPAD_LSB 13 |
| #define IO_BANK0_GPIO19_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO19_STATUS_OEFROMPERI |
| // Description : output enable from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO19_STATUS_OEFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO19_STATUS_OEFROMPERI_BITS 0x00001000 |
| #define IO_BANK0_GPIO19_STATUS_OEFROMPERI_MSB 12 |
| #define IO_BANK0_GPIO19_STATUS_OEFROMPERI_LSB 12 |
| #define IO_BANK0_GPIO19_STATUS_OEFROMPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO19_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO19_STATUS_OUTTOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO19_STATUS_OUTTOPAD_BITS 0x00000200 |
| #define IO_BANK0_GPIO19_STATUS_OUTTOPAD_MSB 9 |
| #define IO_BANK0_GPIO19_STATUS_OUTTOPAD_LSB 9 |
| #define IO_BANK0_GPIO19_STATUS_OUTTOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO19_STATUS_OUTFROMPERI |
| // Description : output signal from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_BITS 0x00000100 |
| #define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_MSB 8 |
| #define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_LSB 8 |
| #define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO19_CTRL |
| // Description : GPIO control including function select and overrides. |
| #define IO_BANK0_GPIO19_CTRL_OFFSET 0x0000009c |
| #define IO_BANK0_GPIO19_CTRL_BITS 0x3003331f |
| #define IO_BANK0_GPIO19_CTRL_RESET 0x0000001f |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO19_CTRL_IRQOVER |
| // Description : 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO19_CTRL_IRQOVER_RESET 0x0 |
| #define IO_BANK0_GPIO19_CTRL_IRQOVER_BITS 0x30000000 |
| #define IO_BANK0_GPIO19_CTRL_IRQOVER_MSB 29 |
| #define IO_BANK0_GPIO19_CTRL_IRQOVER_LSB 28 |
| #define IO_BANK0_GPIO19_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO19_CTRL_INOVER |
| // Description : 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO19_CTRL_INOVER_RESET 0x0 |
| #define IO_BANK0_GPIO19_CTRL_INOVER_BITS 0x00030000 |
| #define IO_BANK0_GPIO19_CTRL_INOVER_MSB 17 |
| #define IO_BANK0_GPIO19_CTRL_INOVER_LSB 16 |
| #define IO_BANK0_GPIO19_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO19_CTRL_OEOVER |
| // Description : 0x0 -> drive output enable from peripheral signal selected by |
| // funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal |
| // selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO19_CTRL_OEOVER_RESET 0x0 |
| #define IO_BANK0_GPIO19_CTRL_OEOVER_BITS 0x00003000 |
| #define IO_BANK0_GPIO19_CTRL_OEOVER_MSB 13 |
| #define IO_BANK0_GPIO19_CTRL_OEOVER_LSB 12 |
| #define IO_BANK0_GPIO19_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_DISABLE 0x2 |
| #define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_ENABLE 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO19_CTRL_OUTOVER |
| // Description : 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected |
| // by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO19_CTRL_OUTOVER_RESET 0x0 |
| #define IO_BANK0_GPIO19_CTRL_OUTOVER_BITS 0x00000300 |
| #define IO_BANK0_GPIO19_CTRL_OUTOVER_MSB 9 |
| #define IO_BANK0_GPIO19_CTRL_OUTOVER_LSB 8 |
| #define IO_BANK0_GPIO19_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO19_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x01 -> spi0_tx |
| // 0x02 -> uart0_rts |
| // 0x03 -> i2c1_scl |
| // 0x04 -> pwm_b_1 |
| // 0x05 -> sio_19 |
| // 0x06 -> pio0_19 |
| // 0x07 -> pio1_19 |
| // 0x09 -> usb_muxing_vbus_detect |
| // 0x1f -> null |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_RESET 0x1f |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_BITS 0x0000001f |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_MSB 4 |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_LSB 0 |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SPI0_TX 0x01 |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RTS 0x02 |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PWM_B_1 0x04 |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SIO_19 0x05 |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO0_19 0x06 |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO1_19 0x07 |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_NULL 0x1f |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO20_STATUS |
| // Description : GPIO status |
| #define IO_BANK0_GPIO20_STATUS_OFFSET 0x000000a0 |
| #define IO_BANK0_GPIO20_STATUS_BITS 0x050a3300 |
| #define IO_BANK0_GPIO20_STATUS_RESET 0x00000000 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO20_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO20_STATUS_IRQTOPROC_RESET 0x0 |
| #define IO_BANK0_GPIO20_STATUS_IRQTOPROC_BITS 0x04000000 |
| #define IO_BANK0_GPIO20_STATUS_IRQTOPROC_MSB 26 |
| #define IO_BANK0_GPIO20_STATUS_IRQTOPROC_LSB 26 |
| #define IO_BANK0_GPIO20_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO20_STATUS_IRQFROMPAD |
| // Description : interrupt from pad before override is applied |
| #define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_BITS 0x01000000 |
| #define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_MSB 24 |
| #define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_LSB 24 |
| #define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO20_STATUS_INTOPERI |
| // Description : input signal to peripheral, after override is applied |
| #define IO_BANK0_GPIO20_STATUS_INTOPERI_RESET 0x0 |
| #define IO_BANK0_GPIO20_STATUS_INTOPERI_BITS 0x00080000 |
| #define IO_BANK0_GPIO20_STATUS_INTOPERI_MSB 19 |
| #define IO_BANK0_GPIO20_STATUS_INTOPERI_LSB 19 |
| #define IO_BANK0_GPIO20_STATUS_INTOPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO20_STATUS_INFROMPAD |
| // Description : input signal from pad, before override is applied |
| #define IO_BANK0_GPIO20_STATUS_INFROMPAD_RESET 0x0 |
| #define IO_BANK0_GPIO20_STATUS_INFROMPAD_BITS 0x00020000 |
| #define IO_BANK0_GPIO20_STATUS_INFROMPAD_MSB 17 |
| #define IO_BANK0_GPIO20_STATUS_INFROMPAD_LSB 17 |
| #define IO_BANK0_GPIO20_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO20_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO20_STATUS_OETOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO20_STATUS_OETOPAD_BITS 0x00002000 |
| #define IO_BANK0_GPIO20_STATUS_OETOPAD_MSB 13 |
| #define IO_BANK0_GPIO20_STATUS_OETOPAD_LSB 13 |
| #define IO_BANK0_GPIO20_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO20_STATUS_OEFROMPERI |
| // Description : output enable from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO20_STATUS_OEFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO20_STATUS_OEFROMPERI_BITS 0x00001000 |
| #define IO_BANK0_GPIO20_STATUS_OEFROMPERI_MSB 12 |
| #define IO_BANK0_GPIO20_STATUS_OEFROMPERI_LSB 12 |
| #define IO_BANK0_GPIO20_STATUS_OEFROMPERI_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO20_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO20_STATUS_OUTTOPAD_RESET 0x0 |
| #define IO_BANK0_GPIO20_STATUS_OUTTOPAD_BITS 0x00000200 |
| #define IO_BANK0_GPIO20_STATUS_OUTTOPAD_MSB 9 |
| #define IO_BANK0_GPIO20_STATUS_OUTTOPAD_LSB 9 |
| #define IO_BANK0_GPIO20_STATUS_OUTTOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO20_STATUS_OUTFROMPERI |
| // Description : output signal from selected peripheral, before register |
| // override is applied |
| #define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_RESET 0x0 |
| #define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_BITS 0x00000100 |
| #define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_MSB 8 |
| #define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_LSB 8 |
| #define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO20_CTRL |
| // Description : GPIO control including function select and overrides. |
| #define IO_BANK0_GPIO20_CTRL_OFFSET 0x000000a4 |
| #define IO_BANK0_GPIO20_CTRL_BITS 0x3003331f |
| #define IO_BANK0_GPIO20_CTRL_RESET 0x0000001f |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO20_CTRL_IRQOVER |
| // Description : 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO20_CTRL_IRQOVER_RESET 0x0 |
| #define IO_BANK0_GPIO20_CTRL_IRQOVER_BITS 0x30000000 |
| #define IO_BANK0_GPIO20_CTRL_IRQOVER_MSB 29 |
| #define IO_BANK0_GPIO20_CTRL_IRQOVER_LSB 28 |
| #define IO_BANK0_GPIO20_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO20_CTRL_INOVER |
| // Description : 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO20_CTRL_INOVER_RESET 0x0 |
| #define IO_BANK0_GPIO20_CTRL_INOVER_BITS 0x00030000 |
| #define IO_BANK0_GPIO20_CTRL_INOVER_MSB 17 |
| #define IO_BANK0_GPIO20_CTRL_INOVER_LSB 16 |
| #define IO_BANK0_GPIO20_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_NORMAL 0x0 |
| #define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_INVERT 0x1 |
| #define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_LOW 0x2 |
| #define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_HIGH 0x3 |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO20_CTRL_OEOVER |
