Merge pull request #472 from raspberrypi/release.1.2.0
SDK 1.2.0 release; see release notes for details
diff --git a/.gitmodules b/.gitmodules
index 70b4bfb..4846c9c 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,4 +1,3 @@
[submodule "tinyusb"]
path = lib/tinyusb
- url = https://github.com/raspberrypi/tinyusb.git
- branch = pico
+ url = https://github.com/hathach/tinyusb.git
diff --git a/CMakeLists.txt b/CMakeLists.txt
index da67e37..c270649 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -1,6 +1,10 @@
cmake_minimum_required(VERSION 3.13)
+
+# Note: this CMakeLists.txt can be used as a top-level CMakeLists.txt for the SDK itself. For all other uses
+# it is included as a subdirectory via the pico_sdk_init() method provided by pico_sdk_init.cmake
if (NOT TARGET _pico_sdk_inclusion_marker)
add_library(_pico_sdk_inclusion_marker INTERFACE)
+ # This is a no-op unless we are the top-level CMakeLists.txt
include(pico_sdk_init.cmake)
project(pico_sdk C CXX ASM)
@@ -24,6 +28,7 @@
# allow customization
add_sub_list_dirs(PICO_SDK_PRE_LIST_DIRS)
+ add_sub_list_files(PICO_SDK_PRE_LIST_FILES)
add_subdirectory(tools)
add_subdirectory(src)
@@ -32,6 +37,7 @@
# allow customization
add_sub_list_dirs(PICO_SDK_POST_LIST_DIRS)
+ add_sub_list_files(PICO_SDK_POST_LIST_FILES)
if (PICO_SDK_TOP_LEVEL_PROJECT AND NOT DEFINED PICO_SDK_TESTS_ENABLED)
set(PICO_SDK_TESTS_ENABLED 1)
@@ -44,5 +50,9 @@
# add docs at the end, as we gather documentation dirs as we go
add_subdirectory(docs)
+
+ if (NOT PICO_SDK_TOP_LEVEL_PROJECT)
+ pico_promote_common_scope_vars()
+ endif()
endif()
diff --git a/README.md b/README.md
index 8141c33..db6cef6 100644
--- a/README.md
+++ b/README.md
@@ -4,7 +4,7 @@
necessary to write programs for the RP2040-based devices such as the Raspberry Pi Pico
in C, C++ or assembly language.
-The SDK is designed to provide an API and programming environment that is familiar both to non-embedded C developers and embedded C developers alike.
+The SDK is designed to provide an API and programming environment that is familiar both to non-embedded C developers and embedded C developers alike.
A single program runs on the device at a time and starts with a conventional `main()` method. Standard C/C++ libraries are supported along with
C level libraries/APIs for accessing all of the RP2040's hardware include PIO (Programmable IO).
@@ -38,7 +38,7 @@
1. Install CMake (at least version 3.13), and GCC cross compiler
```
- sudo apt install cmake gcc-arm-none-eabi libnewlib-arm-none-eabi
+ sudo apt install cmake gcc-arm-none-eabi libnewlib-arm-none-eabi libstdc++-arm-none-eabi-newlib
```
1. Set up your project to point to use the Raspberry Pi Pico SDK
diff --git a/cmake/pico_pre_load_toolchain.cmake b/cmake/pico_pre_load_toolchain.cmake
index 6c01357..b77f421 100644
--- a/cmake/pico_pre_load_toolchain.cmake
+++ b/cmake/pico_pre_load_toolchain.cmake
@@ -36,8 +36,8 @@
select one from \"cmake/toolchains\" folder.")
endif ()
endif ()
+ message("PICO compiler is ${PICO_COMPILER}")
endif ()
-message("PICO compiler is ${PICO_COMPILER}")
unset(PICO_COMPILER CACHE)
diff --git a/cmake/preload/toolchains/pico_arm_gcc.cmake b/cmake/preload/toolchains/pico_arm_gcc.cmake
index b0c2648..d8c56fc 100644
--- a/cmake/preload/toolchains/pico_arm_gcc.cmake
+++ b/cmake/preload/toolchains/pico_arm_gcc.cmake
@@ -12,7 +12,7 @@
message("PICO_GCC_TRIPLE set from environment: $ENV{PICO_GCC_TRIPLE}")
else()
set(PICO_GCC_TRIPLE arm-none-eabi)
- message("PICO_GCC_TRIPLE defaulted to arm-none-eabi")
+ #pico_message_debug("PICO_GCC_TRIPLE defaulted to arm-none-eabi")
endif()
endif()
diff --git a/docs/CMakeLists.txt b/docs/CMakeLists.txt
index 4d0ee36..45fd1d6 100644
--- a/docs/CMakeLists.txt
+++ b/docs/CMakeLists.txt
@@ -1,4 +1,4 @@
-find_package(Doxygen)
+find_package(Doxygen QUIET)
if (PICO_SDK_TOP_LEVEL_PROJECT AND ${DOXYGEN_FOUND})
set(PICO_BUILD_DOCS_DEFAULT 1)
endif()
diff --git a/docs/examples.md b/docs/examples.md
index 2e57012..2553591 100644
--- a/docs/examples.md
+++ b/docs/examples.md
@@ -1,6 +1,6 @@
## Examples Index {#examples_page}
-This page links to the various example code fragments in this documentation. For more complete examples, please see the pico_examples repository, which contains complete buildable projects.
+This page links to the various example code fragments in this documentation. For more complete examples, please see the [pico-examples](https://github.com/raspberrypi/pico-examples) repository, which contains complete buildable projects.
- [RTC example](@ref rtc_example)
- [UART example](@ref uart_example)
diff --git a/docs/index.h b/docs/index.h
index 53f4674..c7ef735 100644
--- a/docs/index.h
+++ b/docs/index.h
@@ -17,6 +17,7 @@
* \defgroup hardware_clocks hardware_clocks
* \defgroup hardware_divider hardware_divider
* \defgroup hardware_dma hardware_dma
+ * \defgroup hardware_exception hardware_exception
* \defgroup hardware_flash hardware_flash
* \defgroup hardware_gpio hardware_gpio
* \defgroup hardware_i2c hardware_i2c
diff --git a/docs/mainpage.md b/docs/mainpage.md
index 527d109..e79fb90 100644
--- a/docs/mainpage.md
+++ b/docs/mainpage.md
@@ -25,7 +25,6 @@
## Examples
-This SDK contains a number of example code fragments. An index of these examples can be found [here](@ref examples_page)
-
+This SDK documentation contains a number of example code fragments. An index of these examples can be found [here](@ref examples_page). These examples, and any other source code included in this documentation, is Copyright © 2020 Raspberry Pi (Trading) Ltd. and licensed under the [3-Clause BSD](https://opensource.org/licenses/BSD-3-Clause) license.
diff --git a/lib/tinyusb b/lib/tinyusb
index 11c23f8..d49938d 160000
--- a/lib/tinyusb
+++ b/lib/tinyusb
@@ -1 +1 @@
-Subproject commit 11c23f88bf42f64ce14b8a7b0b2a4e207dc4dd12
+Subproject commit d49938d0f5052bce70e55c652b657c0a6a7e84fe
diff --git a/pico_sdk_init.cmake b/pico_sdk_init.cmake
index 2c501e4..f6b6f81 100644
--- a/pico_sdk_init.cmake
+++ b/pico_sdk_init.cmake
@@ -1,54 +1,94 @@
-# Initialize the Raspberry Pi Pico SDK
+# Pre-initialize the Raspberry Pi Pico SDK, setting up the platform and toolchain and some CMake utility functions
# This file must be included prior to the project() call
-if (_PICO_SDK_INIT)
- return()
-endif ()
-set(_PICO_SDK_INIT 1)
+# Note: this file is perhaps named badly, as it provides a method pico_sdk_init which
+# the enclosing project calls LATER to actually "initialize" the SDK (by including the CMakeLists.txt from this
+# same directory)
-function(pico_is_top_level_project VAR)
- string(TOLOWER ${CMAKE_CURRENT_LIST_DIR} __list_dir)
- string(TOLOWER ${CMAKE_SOURCE_DIR} __source_dir)
- if (__source_dir STREQUAL __list_dir)
- set(${VAR} 1 PARENT_SCOPE)
- else()
- set(${VAR} 0 PARENT_SCOPE)
- endif()
-endfunction()
+if (NOT TARGET _pico_sdk_pre_init_marker)
+ add_library(_pico_sdk_pre_init_marker INTERFACE)
-if (NOT PICO_SDK_PATH)
- set(PICO_SDK_PATH ${CMAKE_CURRENT_LIST_DIR})
-endif ()
+ function(pico_is_top_level_project VAR)
+ string(TOLOWER ${CMAKE_CURRENT_LIST_DIR} __list_dir)
+ string(TOLOWER ${CMAKE_SOURCE_DIR} __source_dir)
+ if (__source_dir STREQUAL __list_dir)
+ set(${VAR} 1 PARENT_SCOPE)
+ else()
+ set(${VAR} 0 PARENT_SCOPE)
+ endif()
+ endfunction()
-get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}")
+ function(pico_message_debug MESSAGE)
+ # The log-level system was added in CMake 3.15.
+ if(${CMAKE_VERSION} VERSION_LESS "3.15.0")
+ message(${MESSAGE})
+ else()
+ message(DEBUG ${MESSAGE})
+ endif()
+ endfunction()
-set(PICO_SDK_PATH ${CMAKE_CURRENT_LIST_DIR} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE)
+ if (NOT PICO_SDK_PATH)
+ set(PICO_SDK_PATH ${CMAKE_CURRENT_LIST_DIR})
+ endif ()
-list(APPEND CMAKE_MODULE_PATH ${PICO_SDK_PATH}/cmake)
+ get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}")
-include(${CMAKE_CURRENT_LIST_DIR}/pico_sdk_version.cmake)
-include(pico_utils)
+ set(PICO_SDK_PATH ${CMAKE_CURRENT_LIST_DIR} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE)
-message("PICO_SDK_PATH is ${CMAKE_CURRENT_LIST_DIR}")
+ list(APPEND CMAKE_MODULE_PATH ${PICO_SDK_PATH}/cmake)
-include(pico_pre_load_platform)
+ include(${CMAKE_CURRENT_LIST_DIR}/pico_sdk_version.cmake)
+ include(pico_utils)
-# todo perhaps this should be included by the platform instead?
-# We want to configure correct toolchain prior to project load
-include(pico_pre_load_toolchain)
+ message("PICO_SDK_PATH is ${CMAKE_CURRENT_LIST_DIR}")
-macro(pico_sdk_init)
- if (NOT CMAKE_PROJECT_NAME)
- message(WARNING "pico_sdk_init() should be called after the project is created (and languages added)")
- endif()
- add_subdirectory(${PICO_SDK_PATH} pico-sdk)
-endmacro()
+ include(pico_pre_load_platform)
-macro(add_sub_list_dirs var)
- foreach(LIST_DIR IN LISTS ${var})
- get_filename_component(SHORT_NAME "${LIST_DIR}" NAME)
- message("Including custom CMakeLists.txt ${SHORT_NAME}")
- add_subdirectory(${LIST_DIR} ${SHORT_NAME})
- endforeach()
-endmacro()
+ # We want to configure correct toolchain prior to project load
+ # todo perhaps this should be included by the platform instead?
+ include(pico_pre_load_toolchain)
+ macro(pico_sdk_init)
+ if (NOT CMAKE_PROJECT_NAME)
+ message(WARNING "pico_sdk_init() should be called after the project is created (and languages added)")
+ endif()
+ add_subdirectory(${PICO_SDK_PATH} pico-sdk)
+ pico_is_top_level_project(ISTOP)
+ endmacro()
+
+ macro(add_sub_list_dirs var)
+ foreach(LIST_DIR IN LISTS ${var})
+ get_filename_component(SHORT_NAME "${LIST_DIR}" NAME)
+ pico_message_debug("Including custom CMakeLists.txt ${SHORT_NAME}")
+ add_subdirectory(${LIST_DIR} ${SHORT_NAME})
+ endforeach()
+ endmacro()
+
+ macro(add_sub_list_files var)
+ foreach(LIST_FILE IN LISTS ${var})
+ pico_message_debug("Including custom CMake file ${LIST_FILE}")
+ include(${LIST_FILE})
+ endforeach()
+ endmacro()
+
+ macro(pico_register_common_scope_var NAME)
+ if (NOT ${NAME} IN_LIST PICO_PROMOTE_COMMON_SCOPE_VARS)
+ list(APPEND PICO_PROMOTE_COMMON_SCOPE_VARS ${NAME})
+ endif()
+ endmacro()
+
+ set(PICO_PROMOTE_COMMON_SCOPE_VARS
+ PICO_INCLUDE_DIRS
+ PICO_SDK_POST_LIST_DIRS
+ PICO_SDK_POST_LIST_FILES
+ PICO_CONFIG_HEADER_FILES
+ PICO_RP2040_CONFIG_HEADER_FILES
+ )
+
+ macro(pico_promote_common_scope_vars)
+ set(PICO_PROMOTE_COMMON_SCOPE_VARS ${PICO_PROMOTE_COMMON_SCOPE_VARS} PARENT_SCOPE)
+ foreach(VAR IN LISTS PICO_PROMOTE_COMMON_SCOPE_VARS)
+ SET(${VAR} ${${VAR}} PARENT_SCOPE)
+ endforeach()
+ endmacro()
+endif()
diff --git a/pico_sdk_version.cmake b/pico_sdk_version.cmake
index 6481637..a2d8444 100644
--- a/pico_sdk_version.cmake
+++ b/pico_sdk_version.cmake
@@ -3,13 +3,12 @@
set(PICO_SDK_VERSION_MAJOR 1)
# PICO_BUILD_DEFINE: PICO_SDK_VERSION_MINOR, SDK minor version number, type=int, group=pico_base
# PICO_CONFIG: PICO_SDK_VERSION_MINOR, SDK minor version number, type=int, group=pico_base
-set(PICO_SDK_VERSION_MINOR 1)
+set(PICO_SDK_VERSION_MINOR 2)
# PICO_BUILD_DEFINE: PICO_SDK_VERSION_REVISION, SDK version revision, type=int, group=pico_base
# PICO_CONFIG: PICO_SDK_VERSION_REVISION, SDK version revision, type=int, group=pico_base
-set(PICO_SDK_VERSION_REVISION 2)
+set(PICO_SDK_VERSION_REVISION 0)
# PICO_BUILD_DEFINE: PICO_SDK_VERSION_PRE_RELEASE_ID, optional SDK pre-release version identifier, type=string, group=pico_base
# PICO_CONFIG: PICO_SDK_VERSION_PRE_RELEASE_ID, optional SDK pre-release version identifier, type=string, group=pico_base
-#set(PICO_SDK_VERSION_PRE_RELEASE_ID develop)
# PICO_BUILD_DEFINE: PICO_SDK_VERSION_STRING, SDK version, type=string, group=pico_base
# PICO_CONFIG: PICO_SDK_VERSION_STRING, SDK version, type=string, group=pico_base
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index 5d7a4c7..59f2933 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -11,10 +11,12 @@
Either specify a valid PICO_PLATFORM (or PICO_PLATFORM_CMAKE_FILE).")
endif ()
+# Initialize board related build/compile settings
include(${CMAKE_CURRENT_LIST_DIR}/board_setup.cmake)
-# todo add option to disable skip flag
+# call add_subdirectory(subdir) unless SKIP_SUBDIR evaluates to true
function(pico_add_subdirectory subdir)
+ # todo add option to disable skip flag
string(TOUPPER ${subdir} subdir_upper)
set(replace_flag SKIP_${subdir_upper})
if (NOT ${replace_flag})
@@ -22,12 +24,15 @@
else ()
message("Not including ${subdir} because ${replace_flag} defined.")
endif ()
+ pico_promote_common_scope_vars()
endfunction()
+# add a link option to wrap the given function name; i.e. -Wl:wrap=FUNCNAME for gcc
function(pico_wrap_function TARGET FUNCNAME)
target_link_options(${TARGET} INTERFACE "LINKER:--wrap=${FUNCNAME}")
endfunction()
+# add map file generation for the given target
function(pico_add_map_output TARGET)
get_target_property(target_type ${TARGET} TYPE)
if ("EXECUTABLE" STREQUAL "${target_type}")
@@ -37,11 +42,23 @@
endif ()
endfunction()
+# create a hardware_NAME_headers target (see pico_pico_simple_hardware_headers_target)
+# create a hardware_NAME target (see pico_pico_simple_hardware_target)
macro(pico_simple_hardware_target NAME)
pico_simple_hardware_headers_target(${NAME})
pico_simple_hardware_impl_target(${NAME})
endmacro()
+# create an INTERFACE library named target, and define LIB_TARGET=1 (upper case) as a compile option
+function(pico_add_impl_library target)
+ add_library(${target} INTERFACE)
+ string(TOUPPER ${target} TARGET_UPPER)
+ target_compile_definitions(${target} INTERFACE LIB_${TARGET_UPPER}=1)
+endfunction()
+
+# create an INTERFACE library named hardware_NAME_headers INTERFACE library if it doesn't already exist,
+# and add include/ relative to the calling directory to the includes.
+# and hardware_structs and hardware_claim as dependencies of the library
macro(pico_simple_hardware_headers_target NAME)
if (NOT TARGET hardware_${NAME}_headers)
add_library(hardware_${NAME}_headers INTERFACE)
@@ -54,8 +71,15 @@
endif()
endmacro()
+# create an INTERFACE library named hardware_NAME if it doesn't exist, along with a hardware_NAME_headers
+# INTERFACE library that it depends on. The hardware_NAME_headers library add include/ relative to
+# and pico_base_headers, and harddware_structs as a dependency of the library
macro(pico_simple_hardware_headers_only_target NAME)
if (NOT TARGET hardware_${NAME})
+ # Choosing not to add LIB_HARDWARE_ defines to avoid command line bloat pending a need (they aren't
+ # super interesting except to determine functionality as they are mostly passive accessors, however
+ # they could be useful to determine if the header is available.
+ # pico_add_sdk_impl_library(hardware_${NAME})
add_library(hardware_${NAME} INTERFACE)
target_include_directories(hardware_${NAME} INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
@@ -66,8 +90,14 @@
endif()
endmacro()
+# create an INTERFACE library named hardware_NAME if it doesn't exist, dependent on a pre-existing hardware_NAME_headers
+# INTERFACE library and pico_platform. The file NAME.c relative to the caller is added to the C sources for the hardware_NAME
macro(pico_simple_hardware_impl_target NAME)
if (NOT TARGET hardware_${NAME})
+ # Choosing not to add LIB_HARDWARE_ defines to avoid command line bloat pending a need (they aren't
+ # super interesting except to determine functionality as they are mostly passive accessors, however
+ # they could be useful to determine if the header is available.
+ # pico_add_sdk_impl_library(hardware_${NAME})
add_library(hardware_${NAME} INTERFACE)
target_sources(hardware_${NAME} INTERFACE
@@ -86,4 +116,6 @@
set(PICO_DOXYGEN_EXCLUDE_PATHS "${PICO_DOXYGEN_EXCLUDE_PATHS} ${SOURCE_DIR}" CACHE INTERNAL "")
endfunction()
-include(${PICO_PLATFORM_CMAKE_FILE})
\ No newline at end of file
+include(${PICO_PLATFORM_CMAKE_FILE})
+
+pico_promote_common_scope_vars()
\ No newline at end of file
diff --git a/src/boards/include/boards/adafruit_feather_rp2040.h b/src/boards/include/boards/adafruit_feather_rp2040.h
index a27f9a3..5049f6b 100644
--- a/src/boards/include/boards/adafruit_feather_rp2040.h
+++ b/src/boards/include/boards/adafruit_feather_rp2040.h
@@ -15,6 +15,11 @@
// For board detection
#define ADAFRUIT_FEATHER_RP2040
+// On some samples, the xosc can take longer to stabilize than is usual
+#ifndef PICO_XOSC_STARTUP_DELAY_MULTIPLIER
+#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 64
+#endif
+
//------------- UART -------------//
#ifndef PICO_DEFAULT_UART
#define PICO_DEFAULT_UART 0
diff --git a/src/boards/include/boards/adafruit_itsybitsy_rp2040.h b/src/boards/include/boards/adafruit_itsybitsy_rp2040.h
index dd29d64..26cde1d 100644
--- a/src/boards/include/boards/adafruit_itsybitsy_rp2040.h
+++ b/src/boards/include/boards/adafruit_itsybitsy_rp2040.h
@@ -15,6 +15,11 @@
// For board detection
#define ADAFRUIT_ITSYBITSY_RP2040
+// On some samples, the xosc can take longer to stabilize than is usual
+#ifndef PICO_XOSC_STARTUP_DELAY_MULTIPLIER
+#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 64
+#endif
+
//------------- UART -------------//
#ifndef PICO_DEFAULT_UART
#define PICO_DEFAULT_UART 0
@@ -80,7 +85,7 @@
#endif
#ifndef PICO_FLASH_SIZE_BYTES
-#define PICO_FLASH_SIZE_BYTES (4 * 1024 * 1024)
+#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024)
#endif
// All boards have B1 RP2040
diff --git a/src/boards/include/boards/adafruit_qtpy_rp2040.h b/src/boards/include/boards/adafruit_qtpy_rp2040.h
index 570fb3d..299249d 100644
--- a/src/boards/include/boards/adafruit_qtpy_rp2040.h
+++ b/src/boards/include/boards/adafruit_qtpy_rp2040.h
@@ -15,6 +15,11 @@
// For board detection
#define ADAFRUIT_QTPY_RP2040
+// On some samples, the xosc can take longer to stabilize than is usual
+#ifndef PICO_XOSC_STARTUP_DELAY_MULTIPLIER
+#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 64
+#endif
+
//------------- UART -------------//
#ifndef PICO_DEFAULT_UART
#define PICO_DEFAULT_UART 1
@@ -25,7 +30,7 @@
#endif
#ifndef PICO_DEFAULT_UART_RX_PIN
-#define PICO_DEFAULT_UART_RX_PIN 9
+#define PICO_DEFAULT_UART_RX_PIN 5
#endif
//------------- LED -------------//
@@ -79,7 +84,7 @@
#endif
#ifndef PICO_FLASH_SIZE_BYTES
-#define PICO_FLASH_SIZE_BYTES (4 * 1024 * 1024)
+#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024)
#endif
// All boards have B1 RP2040
diff --git a/src/boards/include/boards/arduino_nano_rp2040_connect.h b/src/boards/include/boards/arduino_nano_rp2040_connect.h
new file mode 100644
index 0000000..9725cb7
--- /dev/null
+++ b/src/boards/include/boards/arduino_nano_rp2040_connect.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_ARDUINO_NANO_RP2040_CONNECT_H
+#define _BOARDS_ARDUINO_NANO_RP2040_CONNECT_H
+
+// For board detection
+#define ARDUINO_NANO_RP2040_CONNECT
+
+//------------- UART -------------//
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+//------------- LED -------------//
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN 6
+#endif
+// no PICO_DEFAULT_WS2812_PIN
+
+//------------- I2C -------------//
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 0
+#endif
+
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 12
+#endif
+
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 13
+#endif
+
+//------------- SPI -------------//
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 7
+#endif
+
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 4
+#endif
+
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 6
+#endif
+
+//------------- FLASH -------------//
+
+#define PICO_BOOT_STAGE2_CHOOSE_AT25SF128A 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024)
+#endif
+
+// All boards have B1 RP2040
+#ifndef PICO_FLOAT_SUPPORT_ROM_V1
+#define PICO_FLOAT_SUPPORT_ROM_V1 0
+#endif
+
+#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
+#define PICO_DOUBLE_SUPPORT_ROM_V1 0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/pico.h b/src/boards/include/boards/pico.h
index d681dc4..313d085 100644
--- a/src/boards/include/boards/pico.h
+++ b/src/boards/include/boards/pico.h
@@ -14,6 +14,9 @@
#ifndef _BOARDS_PICO_H
#define _BOARDS_PICO_H
+// For board detection
+#define RASPBERRYPI_PICO
+
// --- UART ---
#ifndef PICO_DEFAULT_UART
#define PICO_DEFAULT_UART 0
diff --git a/src/boards/include/boards/pimoroni_keybow2040.h b/src/boards/include/boards/pimoroni_keybow2040.h
index 011212e..8cd6c1b 100644
--- a/src/boards/include/boards/pimoroni_keybow2040.h
+++ b/src/boards/include/boards/pimoroni_keybow2040.h
@@ -15,18 +15,7 @@
// For board detection
#define PIMORONI_KEYBOW2040
-#ifndef PICO_DEFAULT_UART
-#define PICO_DEFAULT_UART 0
-#endif
-
-#ifndef PICO_DEFAULT_UART_TX_PIN
-#define PICO_DEFAULT_UART_TX_PIN 0
-#endif
-
-#ifndef PICO_DEFAULT_UART_RX_PIN
-#define PICO_DEFAULT_UART_RX_PIN 1
-#endif
-
+// --- BOARD SPECIFIC ---
#ifndef KEYBOW2040_I2C_SDA_PIN
#define KEYBOW2040_I2C_SDA_PIN 4
#endif
@@ -111,6 +100,42 @@
#define KEYBOW2040_NUM_SWITCHES_PINS 16
#endif
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// --- LED ---
+// no PICO_DEFAULT_LED_PIN
+// no PICO_DEFAULT_WS2812_PIN
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 0
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN KEYBOW2040_I2C_SDA_PIN
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN KEYBOW2040_I2C_SCL_PIN
+#endif
+
+// --- SPI ---
+// no PICO_DEFAULT_SPI
+// no PICO_DEFAULT_SPI_SCK_PIN
+// no PICO_DEFAULT_SPI_TX_PIN
+// no PICO_DEFAULT_SPI_RX_PIN
+// no PICO_DEFAULT_SPI_CSN_PIN
+
+// --- FLASH ---
#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
#ifndef PICO_FLASH_SPI_CLKDIV
@@ -122,7 +147,6 @@
#endif
// All boards have B1 RP2040
-
#ifndef PICO_FLOAT_SUPPORT_ROM_V1
#define PICO_FLOAT_SUPPORT_ROM_V1 0
#endif
diff --git a/src/boards/include/boards/pimoroni_pga2040.h b/src/boards/include/boards/pimoroni_pga2040.h
new file mode 100644
index 0000000..90340fa
--- /dev/null
+++ b/src/boards/include/boards/pimoroni_pga2040.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_PIMORONI_PGA2040_H
+#define _BOARDS_PIMORONI_PGA2040_H
+
+// For board detection
+#define PIMORONI_PGA2040
+
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// --- LED ---
+// no PICO_DEFAULT_LED_PIN
+// no PICO_DEFAULT_WS2812_PIN
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 0
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 4
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 5
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 18
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 19
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 16
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 17
+#endif
+
+// --- FLASH ---
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024)
+#endif
+
+// All boards have B1 RP2040
+#ifndef PICO_FLOAT_SUPPORT_ROM_V1
+#define PICO_FLOAT_SUPPORT_ROM_V1 0
+#endif
+
+#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
+#define PICO_DOUBLE_SUPPORT_ROM_V1 0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/pimoroni_picolipo_16mb.h b/src/boards/include/boards/pimoroni_picolipo_16mb.h
new file mode 100644
index 0000000..a0310fb
--- /dev/null
+++ b/src/boards/include/boards/pimoroni_picolipo_16mb.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_PIMORONI_PICOLIPO_16MB_H
+#define _BOARDS_PIMORONI_PICOLIPO_16MB_H
+
+// For board detection
+#define PIMORONI_PICOLIPO_16MB
+
+// --- BOARD SPECIFIC ---
+#ifndef PICOLIPO_USER_SW_PIN
+#define PICOLIPO_USER_SW_PIN 23
+#endif
+
+#ifndef PICOLIPO_VBUS_DETECT_PIN
+#define PICOLIPO_VBUS_DETECT_PIN 24
+#endif
+
+#ifndef PICOLIPO_BAT_SENSE_PIN
+#define PICOLIPO_BAT_SENSE_PIN 29
+#endif
+
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// --- LED ---
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN 25
+#endif
+// no PICO_DEFAULT_WS2812_PIN
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 0
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 4
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 5
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 18
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 19
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 16
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 17
+#endif
+
+// --- FLASH ---
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024)
+#endif
+
+// All boards have B1 RP2040
+#ifndef PICO_FLOAT_SUPPORT_ROM_V1
+#define PICO_FLOAT_SUPPORT_ROM_V1 0
+#endif
+
+#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
+#define PICO_DOUBLE_SUPPORT_ROM_V1 0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/pimoroni_picolipo_4mb.h b/src/boards/include/boards/pimoroni_picolipo_4mb.h
new file mode 100644
index 0000000..9374f41
--- /dev/null
+++ b/src/boards/include/boards/pimoroni_picolipo_4mb.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_PIMORONI_PICOLIPO_4MB_H
+#define _BOARDS_PIMORONI_PICOLIPO_4MB_H
+
+// For board detection
+#define PIMORONI_PICOLIPO_4MB
+
+// --- BOARD SPECIFIC ---
+#ifndef PICOLIPO_USER_SW_PIN
+#define PICOLIPO_USER_SW_PIN 23
+#endif
+
+#ifndef PICOLIPO_VBUS_DETECT_PIN
+#define PICOLIPO_VBUS_DETECT_PIN 24
+#endif
+
+#ifndef PICOLIPO_BAT_SENSE_PIN
+#define PICOLIPO_BAT_SENSE_PIN 29
+#endif
+
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// --- LED ---
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN 25
+#endif
+// no PICO_DEFAULT_WS2812_PIN
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 0
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 4
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 5
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 18
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 19
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 16
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 17
+#endif
+
+// --- FLASH ---
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (4 * 1024 * 1024)
+#endif
+
+// All boards have B1 RP2040
+#ifndef PICO_FLOAT_SUPPORT_ROM_V1
+#define PICO_FLOAT_SUPPORT_ROM_V1 0
+#endif
+
+#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
+#define PICO_DOUBLE_SUPPORT_ROM_V1 0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/pimoroni_picosystem.h b/src/boards/include/boards/pimoroni_picosystem.h
index 72d4789..34eb643 100644
--- a/src/boards/include/boards/pimoroni_picosystem.h
+++ b/src/boards/include/boards/pimoroni_picosystem.h
@@ -15,16 +15,21 @@
// For board detection
#define PIMORONI_PICOSYSTEM
+// --- BOARD SPECIFIC ---
#ifndef PICOSYSTEM_VBUS_DETECT_PIN
#define PICOSYSTEM_VBUS_DETECT_PIN 2
#endif
+#ifndef PICOSYSTEM_LCD_SPI
+#define PICOSYSTEM_LCD_SPI 0
+#endif
+
#ifndef PICOSYSTEM_LCD_RESET_PIN
#define PICOSYSTEM_LCD_RESET_PIN 4
#endif
-#ifndef PICOSYSTEM_LCD_CS_PIN
-#define PICOSYSTEM_LCD_CS_PIN 5
+#ifndef PICOSYSTEM_LCD_CSN_PIN
+#define PICOSYSTEM_LCD_CSN_PIN 5
#endif
#ifndef PICOSYSTEM_LCD_SCLK_PIN
@@ -103,6 +108,7 @@
#define PICOSYSTEM_BAT_SENSE_PIN 26
#endif
+// --- UART ---
#ifndef PICO_DEFAULT_UART
#define PICO_DEFAULT_UART 0
#endif
@@ -115,15 +121,30 @@
#define PICO_DEFAULT_UART_RX_PIN 1
#endif
+// --- LED ---
// Included so basic examples will work, and set it to the green LED
#ifndef PICO_DEFAULT_LED_PIN
#define PICO_DEFAULT_LED_PIN PICOSYSTEM_LED_G_PIN
#endif
+// no PICO_DEFAULT_WS2812_PIN
#ifndef PICO_DEFAULT_LED_PIN_INVERTED
#define PICO_DEFAULT_LED_PIN_INVERTED 1
#endif
+// --- I2C ---
+//no PICO_DEFAULT_I2C
+//no PICO_DEFAULT_I2C_SDA_PIN
+//no PICO_DEFAULT_I2C_SCL_PIN
+
+// --- SPI ---
+// no PICO_DEFAULT_SPI
+// no PICO_DEFAULT_SPI_SCK_PIN
+// no PICO_DEFAULT_SPI_TX_PIN
+// no PICO_DEFAULT_SPI_RX_PIN
+// no PICO_DEFAULT_SPI_CSN_PIN
+
+// --- FLASH ---
#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
#ifndef PICO_FLASH_SPI_CLKDIV
@@ -135,7 +156,6 @@
#endif
// All boards have B1 RP2040
-
#ifndef PICO_FLOAT_SUPPORT_ROM_V1
#define PICO_FLOAT_SUPPORT_ROM_V1 0
#endif
diff --git a/src/boards/include/boards/pimoroni_tiny2040.h b/src/boards/include/boards/pimoroni_tiny2040.h
index 6cf86b4..81605b3 100644
--- a/src/boards/include/boards/pimoroni_tiny2040.h
+++ b/src/boards/include/boards/pimoroni_tiny2040.h
@@ -15,18 +15,7 @@
// For board detection
#define PIMORONI_TINY2040
-#ifndef PICO_DEFAULT_UART
-#define PICO_DEFAULT_UART 0
-#endif
-
-#ifndef PICO_DEFAULT_UART_TX_PIN
-#define PICO_DEFAULT_UART_TX_PIN 0
-#endif
-
-#ifndef PICO_DEFAULT_UART_RX_PIN
-#define PICO_DEFAULT_UART_RX_PIN 1
-#endif
-
+// --- BOARD SPECIFIC ---
#ifndef TINY2040_LED_R_PIN
#define TINY2040_LED_R_PIN 18
#endif
@@ -67,15 +56,59 @@
#define TINY2040_NUM_ADC_PINS 4
#endif
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// --- LED ---
// Included so basic examples will work, and set it to the green LED
#ifndef PICO_DEFAULT_LED_PIN
#define PICO_DEFAULT_LED_PIN TINY2040_LED_G_PIN
#endif
+// no PICO_DEFAULT_WS2812_PIN
#ifndef PICO_DEFAULT_LED_PIN_INVERTED
#define PICO_DEFAULT_LED_PIN_INVERTED 1
#endif
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 1
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 2
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 3
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 6
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 7
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 4
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 5
+#endif
+
+// --- FLASH ---
#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
#ifndef PICO_FLASH_SPI_CLKDIV
diff --git a/src/boards/include/boards/sparkfun_micromod.h b/src/boards/include/boards/sparkfun_micromod.h
index d082131..e6ef44f 100644
--- a/src/boards/include/boards/sparkfun_micromod.h
+++ b/src/boards/include/boards/sparkfun_micromod.h
@@ -17,6 +17,9 @@
#ifndef _BOARDS_SPARKFUN_MICROMOD_H
#define _BOARDS_SPARKFUN_MICROMOD_H
+// For board detection
+#define SPARKFUN_MICROMOD
+
#ifndef PICO_DEFAULT_UART
#define PICO_DEFAULT_UART 0
#endif
@@ -46,6 +49,23 @@
#define PICO_DEFAULT_I2C_SCL_PIN 5
#endif
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 22
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 23
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 20
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 21
+#endif
+
// spi flash
#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
diff --git a/src/boards/include/boards/sparkfun_promicro.h b/src/boards/include/boards/sparkfun_promicro.h
index b042d6e..82e96cf 100644
--- a/src/boards/include/boards/sparkfun_promicro.h
+++ b/src/boards/include/boards/sparkfun_promicro.h
@@ -17,6 +17,9 @@
#ifndef _BOARDS_SPARKFUN_PROMICRO_H
#define _BOARDS_SPARKFUN_PROMICRO_H
+// For board detection
+#define SPARKFUN_PROMICRO
+
#ifndef PICO_DEFAULT_UART
#define PICO_DEFAULT_UART 0
#endif
@@ -46,6 +49,23 @@
#define PICO_DEFAULT_I2C_SCL_PIN 17
#endif
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 22
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 23
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 20
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 21
+#endif
+
#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
#ifndef PICO_FLASH_SPI_CLKDIV
diff --git a/src/boards/include/boards/sparkfun_thingplus.h b/src/boards/include/boards/sparkfun_thingplus.h
index d2a0d73..b2e4932 100644
--- a/src/boards/include/boards/sparkfun_thingplus.h
+++ b/src/boards/include/boards/sparkfun_thingplus.h
@@ -17,6 +17,9 @@
#ifndef _BOARDS_SPARKFUN_THINGPLUS_H
#define _BOARDS_SPARKFUN_THINGPLUS_H
+// For board detection
+#define SPARKFUN_THINGPLUS
+
#ifndef PICO_DEFAULT_UART
#define PICO_DEFAULT_UART 0
#endif
@@ -42,6 +45,21 @@
#define PICO_DEFAULT_I2C_SCL_PIN 7
#endif
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 2
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 3
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 4
+#endif
+
+
// spi flash
#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
@@ -54,7 +72,7 @@
#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024)
#endif
-// The thing plus has a SD Card.
+// The thing plus has a SD Card.
#define PICO_SD_CLK_PIN 14
#define PICO_SD_CMD_PIN 15
#define PICO_SD_DAT0_PIN 12
diff --git a/src/boards/include/boards/vgaboard.h b/src/boards/include/boards/vgaboard.h
index d9cb7ac..f0b6f0e 100644
--- a/src/boards/include/boards/vgaboard.h
+++ b/src/boards/include/boards/vgaboard.h
@@ -12,6 +12,9 @@
#ifndef _BOARDS_VGABOARD_H
#define _BOARDS_VGABOARD_H
+// For board detection
+#define RASPBERRYPI_VGABOARD
+
// Audio pins. I2S BCK, LRCK are on the same pins as PWM L/R.
// - When outputting I2S, PWM sees BCK and LRCK, which should sound silent as
// they are constant duty cycle, and above the filter cutoff
diff --git a/src/common/CMakeLists.txt b/src/common/CMakeLists.txt
index 9b256a0..9948db0 100644
--- a/src/common/CMakeLists.txt
+++ b/src/common/CMakeLists.txt
@@ -13,4 +13,6 @@
pico_add_subdirectory(pico_stdlib)
endif()
-pico_add_doxygen(${CMAKE_CURRENT_LIST_DIR})
\ No newline at end of file
+pico_add_doxygen(${CMAKE_CURRENT_LIST_DIR})
+
+pico_promote_common_scope_vars()
\ No newline at end of file
diff --git a/src/common/pico_base/CMakeLists.txt b/src/common/pico_base/CMakeLists.txt
index af04c12..3555dc0 100644
--- a/src/common/pico_base/CMakeLists.txt
+++ b/src/common/pico_base/CMakeLists.txt
@@ -1,40 +1,13 @@
if (NOT TARGET pico_base_headers)
- # build the auto gen config headers
-
- set(header_content "// AUTOGENERATED FROM PICO_CONFIG_HEADER_FILES and then PICO_<PLATFORM>_CONFIG_HEADER_FILES\n// DO NOT EDIT!\n")
- string(TOUPPER ${PICO_PLATFORM} PICO_PLATFORM_UPPER)
-
- macro(add_header_content_from_var VAR)
- set(header_content "${header_content}\n\n// based on ${VAR}:\n")
- foreach(var IN LISTS ${VAR})
- set(header_content "${header_content}\n#include \"${var}\"")
- endforeach()
- endmacro()
-
- # PICO_CMAKE_CONFIG: PICO_CONFIG_HEADER_FILES, List of extra header files to include from pico/config.h for all platforms, type=list, default="", group=pico_base
- add_header_content_from_var(PICO_CONFIG_HEADER_FILES)
-
- # PICO_CMAKE_CONFIG: PICO_CONFIG_RP2040_HEADER_FILES, List of extra header files to include from pico/config.h for rp2040 platform, type=list, default="", group=pico_base
- # PICO_CMAKE_CONFIG: PICO_CONFIG_HOST_HEADER_FILES, List of extra header files to include from pico/config.h for host platform, type=list, default="", group=pico_base
- add_header_content_from_var(PICO_${PICO_PLATFORM_UPPER}_CONFIG_HEADER_FILES)
-
- file(GENERATE
- OUTPUT ${CMAKE_BINARY_DIR}/generated/pico_base/pico/config_autogen.h
- CONTENT "${header_content}"
- )
-
- configure_file( include/pico/version.h.in ${CMAKE_BINARY_DIR}/generated/pico_base/pico/version.h)
-
add_library(pico_base_headers INTERFACE)
target_include_directories(pico_base_headers INTERFACE include ${CMAKE_BINARY_DIR}/generated/pico_base)
- foreach(DIR IN LISTS PICO_INCLUDE_DIRS)
- target_include_directories(pico_base_headers INTERFACE ${DIR})
- endforeach()
-
# PICO_BUILD_DEFINE: PICO_BOARD, Name of board, type=string, default=CMake PICO_BOARD variable, group=pico_base
target_compile_definitions(pico_base_headers INTERFACE
PICO_BOARD="${PICO_BOARD}")
target_link_libraries(pico_base_headers INTERFACE pico_platform_headers)
+
+ list(APPEND PICO_SDK_POST_LIST_FILES ${CMAKE_CURRENT_LIST_DIR}/generate_config_header.cmake)
+ pico_promote_common_scope_vars()
endif()
\ No newline at end of file
diff --git a/src/common/pico_base/generate_config_header.cmake b/src/common/pico_base/generate_config_header.cmake
new file mode 100644
index 0000000..333dfa7
--- /dev/null
+++ b/src/common/pico_base/generate_config_header.cmake
@@ -0,0 +1,29 @@
+# build the auto gen config headers
+
+set(header_content "// AUTOGENERATED FROM PICO_CONFIG_HEADER_FILES and then PICO_<PLATFORM>_CONFIG_HEADER_FILES\n// DO NOT EDIT!\n")
+string(TOUPPER ${PICO_PLATFORM} PICO_PLATFORM_UPPER)
+
+macro(add_header_content_from_var VAR)
+ set(header_content "${header_content}\n\n// based on ${VAR}:\n")
+ foreach(var IN LISTS ${VAR})
+ set(header_content "${header_content}\n#include \"${var}\"")
+ endforeach()
+endmacro()
+
+# PICO_CMAKE_CONFIG: PICO_CONFIG_HEADER_FILES, List of extra header files to include from pico/config.h for all platforms, type=list, default="", group=pico_base
+add_header_content_from_var(PICO_CONFIG_HEADER_FILES)
+
+# PICO_CMAKE_CONFIG: PICO_CONFIG_RP2040_HEADER_FILES, List of extra header files to include from pico/config.h for rp2040 platform, type=list, default="", group=pico_base
+# PICO_CMAKE_CONFIG: PICO_CONFIG_HOST_HEADER_FILES, List of extra header files to include from pico/config.h for host platform, type=list, default="", group=pico_base
+add_header_content_from_var(PICO_${PICO_PLATFORM_UPPER}_CONFIG_HEADER_FILES)
+
+file(GENERATE
+ OUTPUT ${CMAKE_BINARY_DIR}/generated/pico_base/pico/config_autogen.h
+ CONTENT "${header_content}"
+ )
+
+configure_file( ${CMAKE_CURRENT_LIST_DIR}/include/pico/version.h.in ${CMAKE_BINARY_DIR}/generated/pico_base/pico/version.h)
+
+foreach(DIR IN LISTS PICO_INCLUDE_DIRS)
+ target_include_directories(pico_base_headers INTERFACE ${DIR})
+endforeach()
\ No newline at end of file
diff --git a/src/common/pico_binary_info/CMakeLists.txt b/src/common/pico_binary_info/CMakeLists.txt
index 2660e91..eb0c3f6 100644
--- a/src/common/pico_binary_info/CMakeLists.txt
+++ b/src/common/pico_binary_info/CMakeLists.txt
@@ -2,7 +2,11 @@
target_include_directories(pico_binary_info_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
-add_library(pico_binary_info INTERFACE)
+if (COMMAND pico_add_platform_library)
+ pico_add_platform_library(pico_binary_info)
+else()
+ add_library(pico_binary_info INTERFACE)
+endif()
target_link_libraries(pico_binary_info INTERFACE pico_binary_info_headers)
diff --git a/src/common/pico_stdlib/include/pico/stdlib.h b/src/common/pico_stdlib/include/pico/stdlib.h
index a35b64f..da0eef5 100644
--- a/src/common/pico_stdlib/include/pico/stdlib.h
+++ b/src/common/pico_stdlib/include/pico/stdlib.h
@@ -44,15 +44,15 @@
// respective INTERFACE libraries, so these defines are set if the library
// is included for the target executable
-#if PICO_STDIO_UART
+#if LIB_PICO_STDIO_UART
#include "pico/stdio_uart.h"
#endif
-#if PICO_STDIO_USB
+#if LIB_PICO_STDIO_USB
#include "pico/stdio_usb.h"
#endif
-#if PICO_STDIO_SEMIHOSTING
+#if LIB_PICO_STDIO_SEMIHOSTING
#include "pico/stdio_semihosting.h"
#endif
diff --git a/src/common/pico_sync/CMakeLists.txt b/src/common/pico_sync/CMakeLists.txt
index 8d1d0f8..2f8bde2 100644
--- a/src/common/pico_sync/CMakeLists.txt
+++ b/src/common/pico_sync/CMakeLists.txt
@@ -5,7 +5,7 @@
endif()
if (NOT TARGET pico_sync_core)
- add_library(pico_sync_core INTERFACE)
+ pico_add_impl_library(pico_sync_core)
target_sources(pico_sync_core INTERFACE
${CMAKE_CURRENT_LIST_DIR}/lock_core.c
)
@@ -13,7 +13,7 @@
endif()
if (NOT TARGET pico_sync_sem)
- add_library(pico_sync_sem INTERFACE)
+ pico_add_impl_library(pico_sync_sem)
target_sources(pico_sync_sem INTERFACE
${CMAKE_CURRENT_LIST_DIR}/sem.c
)
@@ -21,7 +21,7 @@
endif()
if (NOT TARGET pico_sync_mutex)
- add_library(pico_sync_mutex INTERFACE)
+ pico_add_impl_library(pico_sync_mutex)
target_sources(pico_sync_mutex INTERFACE
${CMAKE_CURRENT_LIST_DIR}/mutex.c
)
@@ -29,7 +29,7 @@
endif()
if (NOT TARGET pico_sync_critical_section)
- add_library(pico_sync_critical_section INTERFACE)
+ pico_add_impl_library(pico_sync_critical_section)
target_sources(pico_sync_critical_section INTERFACE
${CMAKE_CURRENT_LIST_DIR}/critical_section.c
)
@@ -37,7 +37,7 @@
endif()
if (NOT TARGET pico_sync)
- add_library(pico_sync INTERFACE)
+ pico_add_impl_library(pico_sync)
target_link_libraries(pico_sync INTERFACE pico_sync_sem pico_sync_mutex pico_sync_critical_section pico_sync_core)
endif()
diff --git a/src/common/pico_sync/critical_section.c b/src/common/pico_sync/critical_section.c
index 893afb6..f28732b 100644
--- a/src/common/pico_sync/critical_section.c
+++ b/src/common/pico_sync/critical_section.c
@@ -10,15 +10,18 @@
static_assert(sizeof(critical_section_t) == 8, "");
#endif
-void critical_section_init(critical_section_t *critsec) {
- critical_section_init_with_lock_num(critsec, (uint)spin_lock_claim_unused(true));
+void critical_section_init(critical_section_t *crit_sec) {
+ critical_section_init_with_lock_num(crit_sec, (uint)spin_lock_claim_unused(true));
}
-void critical_section_init_with_lock_num(critical_section_t *critsec, uint lock_num) {
- lock_init(&critsec->core, lock_num);
+void critical_section_init_with_lock_num(critical_section_t *crit_sec, uint lock_num) {
+ crit_sec->spin_lock = spin_lock_instance(lock_num);
__mem_fence_release();
}
-void critical_section_deinit(critical_section_t *critsec) {
- spin_lock_unclaim(spin_lock_get_num(critsec->core.spin_lock));
+void critical_section_deinit(critical_section_t *crit_sec) {
+ spin_lock_unclaim(spin_lock_get_num(crit_sec->spin_lock));
+#ifndef NDEBUG
+ crit_sec->spin_lock = (spin_lock_t *)-1;
+#endif
}
\ No newline at end of file
diff --git a/src/common/pico_sync/include/pico/critical_section.h b/src/common/pico_sync/include/pico/critical_section.h
index 17a8b3f..2f94494 100644
--- a/src/common/pico_sync/include/pico/critical_section.h
+++ b/src/common/pico_sync/include/pico/critical_section.h
@@ -22,11 +22,12 @@
* from the other core, and from (higher priority) interrupts on the same core. It does the former
* using a spin lock and the latter by disabling interrupts on the calling core.
*
- * Because interrupts are disabled by this function, uses of the critical_section should be as short as possible.
+ * Because interrupts are disabled when a critical_section is owned, uses of the critical_section
+ * should be as short as possible.
*/
typedef struct __packed_aligned critical_section {
- lock_core_t core;
+ spin_lock_t *spin_lock;
uint32_t save;
} critical_section_t;
@@ -38,16 +39,16 @@
* critical sections, however if you do so you *must* use \ref critical_section_init_with_lock_num
* to ensure that the spin lock's used are different.
*
- * \param critsec Pointer to critical_section structure
+ * \param crit_sec Pointer to critical_section structure
*/
-void critical_section_init(critical_section_t *critsec);
+void critical_section_init(critical_section_t *crit_sec);
/*! \brief Initialise a critical_section structure assigning a specific spin lock number
* \ingroup critical_section
- * \param critsec Pointer to critical_section structure
+ * \param crit_sec Pointer to critical_section structure
* \param lock_num the specific spin lock number to use
*/
-void critical_section_init_with_lock_num(critical_section_t *critsec, uint lock_num);
+void critical_section_init_with_lock_num(critical_section_t *crit_sec, uint lock_num);
/*! \brief Enter a critical_section
* \ingroup critical_section
@@ -55,20 +56,32 @@
* If the spin lock associated with this critical section is in use, then this
* method will block until it is released.
*
- * \param critsec Pointer to critical_section structure
+ * \param crit_sec Pointer to critical_section structure
*/
-static inline void critical_section_enter_blocking(critical_section_t *critsec) {
- critsec->save = spin_lock_blocking(critsec->core.spin_lock);
+static inline void critical_section_enter_blocking(critical_section_t *crit_sec) {
+ crit_sec->save = spin_lock_blocking(crit_sec->spin_lock);
}
/*! \brief Release a critical_section
* \ingroup critical_section
*
- * \param critsec Pointer to critical_section structure
+ * \param crit_sec Pointer to critical_section structure
*/
-static inline void critical_section_exit(critical_section_t *critsec) {
- spin_unlock(critsec->core.spin_lock, critsec->save);
+static inline void critical_section_exit(critical_section_t *crit_sec) {
+ spin_unlock(crit_sec->spin_lock, crit_sec->save);
}
+
+/*! \brief De-Initialise a critical_section created by the critical_section_init method
+ * \ingroup critical_section
+ *
+ * This method is only used to free the associated spin lock allocated via
+ * the critical_section_init method (it should not be used to de-initialize a spin lock
+ * created via critical_section_init_with_lock_num). After this call, the critical section is invalid
+ *
+ * \param crit_sec Pointer to critical_section structure
+ */
+void critical_section_deinit(critical_section_t *crit_sec);
+
#ifdef __cplusplus
}
#endif
diff --git a/src/common/pico_sync/include/pico/lock_core.h b/src/common/pico_sync/include/pico/lock_core.h
index d8f36f2..fc676cc 100644
--- a/src/common/pico_sync/include/pico/lock_core.h
+++ b/src/common/pico_sync/include/pico/lock_core.h
@@ -8,26 +8,183 @@
#define _PICO_LOCK_CORE_H
#include "pico.h"
+#include "pico/time.h"
#include "hardware/sync.h"
+/** \file lock_core.h
+ * \defgroup lock_core lock_core
+ * \ingroup pico_sync
+ * \brief base synchronization/lock primitive support
+ *
+ * Most of the pico_sync locking primitives contain a lock_core_t structure member. This currently just holds a spin
+ * lock which is used only to protect the contents of the rest of the structure as part of implementing the synchronization
+ * primitive. As such, the spin_lock member of lock core is never still held on return from any function for the primitive.
+ *
+ * \ref critical_section is an exceptional case in that it does not have a lock_core_t and simply wraps a spin lock, providing
+ * methods to lock and unlock said spin lock.
+ *
+ * lock_core based structures work by locking the spin lock, checking state, and then deciding whether they additionally need to block
+ * or notify when the spin lock is released. In the blocking case, they will wake up again in the future, and try the process again.
+ *
+ * By default the SDK just uses the processors' events via SEV and WEV for notification and blocking as these are sufficient for
+ * cross core, and notification from interrupt handlers. However macros are defined in this file that abstract the wait
+ * and notify mechanisms to allow the SDK locking functions to effectively be used within an RTOS or other environment.
+ *
+ * When implementing an RTOS, it is desirable for the SDK synchronization primitives that wait, to block the calling task (and immediately yield),
+ * and those that notify, to wake a blocked task which isn't on processor. At least the wait macro implementation needs to be atomic with the protecting
+ * spin_lock unlock from the callers point of view; i.e. the task should unlock the spin lock when it starts its wait. Such implementation is
+ * up to the RTOS integration, however the macros are defined such that such operations are always combined into a single call
+ * (so they can be perfomed atomically) even though the default implementation does not need this, as a WFE which starts
+ * following the corresponding SEV is not missed.
+ */
+
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_LOCK_CORE, Enable/disable assertions in the lock core, type=bool, default=0, group=pico_sync
#ifndef PARAM_ASSERTIONS_ENABLED_LOCK_CORE
#define PARAM_ASSERTIONS_ENABLED_LOCK_CORE 0
#endif
/** \file lock_core.h
- * \ingroup pico_sync
+ * \ingroup lock_core
*
- * Base implementation for locking primitives protected by a spin lock
+ * Base implementation for locking primitives protected by a spin lock. The spin lock is only used to protect
+ * access to the remaining lock state (in primitives using lock_core); it is never left locked outside
+ * of the function implementations
*/
-typedef struct lock_core {
+struct lock_core {
// spin lock protecting this lock's state
spin_lock_t *spin_lock;
// note any lock members in containing structures need not be volatile;
// they are protected by memory/compiler barriers when gaining and release spin locks
-} lock_core_t;
+};
+typedef struct lock_core lock_core_t;
+
+/*! \brief Initialise a lock structure
+ * \ingroup lock_core
+ *
+ * Inititalize a lock structure, providing the spin lock number to use for protecting internal state.
+ *
+ * \param core Pointer to the lock_core to initialize
+ * \param lock_num Spin lock number to use for the lock. As the spin lock is only used internally to the locking primitive
+ * method implementations, this does not need to be globally unique, however could suffer contention
+ */
void lock_init(lock_core_t *core, uint lock_num);
+#ifndef lock_owner_id_t
+/*! \brief type to use to store the 'owner' of a lock.
+ * \ingroup lock_core
+ * By default this is int8_t as it only needs to store the core number or -1, however it may be
+ * overridden if a larger type is required (e.g. for an RTOS task id)
+ */
+#define lock_owner_id_t int8_t
+#endif
+
+#ifndef LOCK_INVALID_OWNER_ID
+/*! \brief marker value to use for a lock_owner_id_t which does not refer to any valid owner
+ * \ingroup lock_core
+ */
+#define LOCK_INVALID_OWNER_ID ((lock_owner_id_t)-1)
+#endif
+
+#ifndef lock_get_caller_owner_id
+/*! \brief return the owner id for the caller
+ * \ingroup lock_core
+ * By default this returns the calling core number, but may be overridden (e.g. to return an RTOS task id)
+ */
+#define lock_get_caller_owner_id() ((lock_owner_id_t)get_core_num())
+#endif
+
+#ifndef lock_internal_spin_unlock_with_wait
+/*! \brief Atomically unlock the lock's spin lock, and wait for a notification.
+ * \ingroup lock_core
+ *
+ * _Atomic_ here refers to the fact that it should not be possible for a concurrent lock_internal_spin_unlock_with_notify
+ * to insert itself between the spin unlock and this wait in a way that the wait does not see the notification (i.e. causing
+ * a missed notification). In other words this method should always wake up in response to a lock_internal_spin_unlock_with_notify
+ * for the same lock, which completes after this call starts.
+ *
+ * In an ideal implementation, this method would return exactly after the corresponding lock_internal_spin_unlock_with_notify
+ * has subsequently been called on the same lock instance, however this method is free to return at _any_ point before that;
+ * this macro is _always_ used in a loop which locks the spin lock, checks the internal locking primitive state and then
+ * waits again if the calling thread should not proceed.
+ *
+ * By default this macro simply unlocks the spin lock, and then performs a WFE, but may be overridden
+ * (e.g. to actually block the RTOS task).
+ *
+ * \param lock the lock_core for the primitive which needs to block
+ * \param save the uint32_t value that should be passed to spin_unlock when the spin lock is unlocked. (i.e. the `PRIMASK`
+ * state when the spin lock was acquire
+ */
+#define lock_internal_spin_unlock_with_wait(lock, save) spin_unlock((lock)->spin_lock, save), __wfe()
+#endif
+
+#ifndef lock_internal_spin_unlock_with_notify
+/*! \brief Atomically unlock the lock's spin lock, and send a notification
+ * \ingroup lock_core
+ *
+ * _Atomic_ here refers to the fact that it should not be possible for this notification to happen during a
+ * lock_internal_spin_unlock_with_wait in a way that that wait does not see the notification (i.e. causing
+ * a missed notification). In other words this method should always wake up any lock_internal_spin_unlock_with_wait
+ * which started before this call completes.
+ *
+ * In an ideal implementation, this method would wake up only the corresponding lock_internal_spin_unlock_with_wait
+ * that has been called on the same lock instance, however it is free to wake up any of them, as they will check
+ * their condition and then re-wait if necessary/
+ *
+ * By default this macro simply unlocks the spin lock, and then performs a SEV, but may be overridden
+ * (e.g. to actually un-block RTOS task(s)).
+ *
+ * \param lock the lock_core for the primitive which needs to block
+ * \param save the uint32_t value that should be passed to spin_unlock when the spin lock is unlocked. (i.e. the PRIMASK
+ * state when the spin lock was acquire)
+ */
+#define lock_internal_spin_unlock_with_notify(lock, save) spin_unlock((lock)->spin_lock, save), __sev()
+#endif
+
+#ifndef lock_internal_spin_unlock_with_best_effort_wait_or_timeout
+/*! \brief Atomically unlock the lock's spin lock, and wait for a notification or a timeout
+ * \ingroup lock_core
+ *
+ * _Atomic_ here refers to the fact that it should not be possible for a concurrent lock_internal_spin_unlock_with_notify
+ * to insert itself between the spin unlock and this wait in a way that the wait does not see the notification (i.e. causing
+ * a missed notification). In other words this method should always wake up in response to a lock_internal_spin_unlock_with_notify
+ * for the same lock, which completes after this call starts.
+ *
+ * In an ideal implementation, this method would return exactly after the corresponding lock_internal_spin_unlock_with_notify
+ * has subsequently been called on the same lock instance or the timeout has been reached, however this method is free to return
+ * at _any_ point before that; this macro is _always_ used in a loop which locks the spin lock, checks the internal locking
+ * primitive state and then waits again if the calling thread should not proceed.
+ *
+ * By default this simply unlocks the spin lock, and then calls \ref best_effort_wfe_or_timeout
+ * but may be overridden (e.g. to actually block the RTOS task with a timeout).
+ *
+ * \param lock the lock_core for the primitive which needs to block
+ * \param save the uint32_t value that should be passed to spin_unlock when the spin lock is unlocked. (i.e. the PRIMASK
+ * state when the spin lock was acquire)
+ * \param until the \ref absolute_time_t value
+ * \return true if the timeout has been reached
+ */
+#define lock_internal_spin_unlock_with_best_effort_wait_or_timeout(lock, save, until) ({ \
+ spin_unlock((lock)->spin_lock, save); \
+ best_effort_wfe_or_timeout(until); \
+})
+#endif
+
+#ifndef sync_internal_yield_until_before
+/*! \brief yield to other processing until some time before the requested time
+ * \ingroup lock_core
+ *
+ * This method is provided for cases where the caller has no useful work to do
+ * until the specified time.
+ *
+ * By default this method does nothing, however it can be overridden (for example by an
+ * RTOS which is able to block the current task until the scheduler tick before
+ * the given time)
+ *
+ * \param until the \ref absolute_time_t value
+ */
+#define sync_internal_yield_until_before(until) ((void)0)
+#endif
+
#endif
diff --git a/src/common/pico_sync/include/pico/mutex.h b/src/common/pico_sync/include/pico/mutex.h
index 4b5d175..22dd19d 100644
--- a/src/common/pico_sync/include/pico/mutex.h
+++ b/src/common/pico_sync/include/pico/mutex.h
@@ -28,12 +28,17 @@
*
* See \ref critical_section.h for protecting access between multiple cores AND IRQ handlers
*/
-
typedef struct __packed_aligned mutex {
lock_core_t core;
- int8_t owner; //! core number or -1 for unowned
+ lock_owner_id_t owner; //! owner id LOCK_INVALID_OWNER_ID for unowned
+ uint8_t recursion_state; //! 0 means non recursive (owner or unowned)
+ //! 1 is a maxed out recursive lock
+ //! 2-254 is an owned lock
+ //! 255 is an un-owned lock
} mutex_t;
+#define MAX_RECURSION_STATE ((uint8_t)255)
+
/*! \brief Initialise a mutex structure
* \ingroup mutex
*
@@ -41,6 +46,15 @@
*/
void mutex_init(mutex_t *mtx);
+/*! \brief Initialise a recursive mutex structure
+ * \ingroup mutex
+ *
+ * A recursive mutex may be entered in a nested fashion by the same owner
+ *
+ * \param mtx Pointer to mutex structure
+ */
+void recursive_mutex_init(mutex_t *mtx);
+
/*! \brief Take ownership of a mutex
* \ingroup mutex
*
@@ -51,13 +65,15 @@
*/
void mutex_enter_blocking(mutex_t *mtx);
-/*! \brief Check to see if a mutex is available
+/*! \brief Attempt to take ownership of a mutex
* \ingroup mutex
*
- * Will return true if the mutex is unowned, false otherwise
+ * If the mutex wasn't owned, this will claim the mutex and return true.
+ * Otherwise (if the mutex was already owned) this will return false and the
+ * calling core will *NOT* own the mutex.
*
* \param mtx Pointer to mutex structure
- * \param owner_out If mutex is owned, and this pointer is non-zero, it will be filled in with the core number of the current owner of the mutex
+ * \param owner_out If mutex was already owned, and this pointer is non-zero, it will be filled in with the core number of the current owner of the mutex
*/
bool mutex_try_enter(mutex_t *mtx, uint32_t *owner_out);
@@ -75,6 +91,20 @@
*/
bool mutex_enter_timeout_ms(mutex_t *mtx, uint32_t timeout_ms);
+/*! \brief Wait for mutex with timeout
+ * \ingroup mutex
+ *
+ * Wait for up to the specific time to take ownership of the mutex. If the calling
+ * core can take ownership of the mutex before the timeout expires, then true will be returned
+ * and the calling core will own the mutex, otherwise false will be returned and the calling
+ * core will *NOT* own the mutex.
+ *
+ * \param mtx Pointer to mutex structure
+ * \param timeout_us The timeout in microseconds.
+ * \return true if mutex now owned, false if timeout occurred before mutex became available
+ */
+bool mutex_enter_timeout_us(mutex_t *mtx, uint32_t timeout_us);
+
/*! \brief Wait for mutex until a specific time
* \ingroup mutex
*
@@ -84,7 +114,7 @@
* core will *NOT* own the mutex.
*
* \param mtx Pointer to mutex structure
- * \param until The time after which to return if the core cannot take owner ship of the mutex
+ * \param until The time after which to return if the core cannot take ownership of the mutex
* \return true if mutex now owned, false if timeout occurred before mutex became available
*/
bool mutex_enter_block_until(mutex_t *mtx, absolute_time_t until);
@@ -129,6 +159,29 @@
*/
#define auto_init_mutex(name) static __attribute__((section(".mutex_array"))) mutex_t name
+/*! \brief Helper macro for static definition of recursive mutexes
+ * \ingroup mutex
+ *
+ * A recursive mutex defined as follows:
+ *
+ * ```c
+ * auto_init_recursive_mutex(my_mutex);
+ * ```
+ *
+ * Is equivalent to doing
+ *
+ * ```c
+ * static mutex_t my_mutex;
+ *
+ * void my_init_function() {
+ * recursive_mutex_init(&my_mutex);
+ * }
+ * ```
+ *
+ * But the initialization of the mutex is performed automatically during runtime initialization
+ */
+#define auto_init_recursive_mutex(name) static __attribute__((section(".mutex_array"))) mutex_t name = { .recursion_state = MAX_RECURSION_STATE }
+
#ifdef __cplusplus
}
#endif
diff --git a/src/common/pico_sync/include/pico/sem.h b/src/common/pico_sync/include/pico/sem.h
index 19ac292..6244e32 100644
--- a/src/common/pico_sync/include/pico/sem.h
+++ b/src/common/pico_sync/include/pico/sem.h
@@ -90,11 +90,38 @@
* return false, otherwise it will return true.
*
* \param sem Pointer to semaphore structure
- * \param timeout_ms Time to wait to acquire the semaphore, in ms.
+ * \param timeout_ms Time to wait to acquire the semaphore, in milliseconds.
* \return false if timeout reached, true if permit was acquired.
*/
bool sem_acquire_timeout_ms(semaphore_t *sem, uint32_t timeout_ms);
+/*! \brief Acquire a permit from a semaphore, with timeout
+ * \ingroup sem
+ *
+ * This function will block and wait if no permits are available, until the
+ * defined timeout has been reached. If the timeout is reached the function will
+ * return false, otherwise it will return true.
+ *
+ * \param sem Pointer to semaphore structure
+ * \param timeout_us Time to wait to acquire the semaphore, in microseconds.
+ * \return false if timeout reached, true if permit was acquired.
+ */
+bool sem_acquire_timeout_us(semaphore_t *sem, uint32_t timeout_us);
+
+/*! \brief Wait to acquire a permit from a semaphore until a specific time
+ * \ingroup sem
+ *
+ * This function will block and wait if no permits are available, until the
+ * specified timeout time. If the timeout is reached the function will
+ * return false, otherwise it will return true.
+ *
+ * \param sem Pointer to semaphore structure
+ * \param until The time after which to return if the sem is not available.
+ * \return true if permit was acquired, false if the until time was reached before
+ * acquiring.
+ */
+bool sem_acquire_block_until(semaphore_t *sem, absolute_time_t until);
+
#ifdef __cplusplus
}
#endif
diff --git a/src/common/pico_sync/mutex.c b/src/common/pico_sync/mutex.c
index 4b4bb27..45ede4d 100644
--- a/src/common/pico_sync/mutex.c
+++ b/src/common/pico_sync/mutex.c
@@ -7,37 +7,53 @@
#include "pico/mutex.h"
#include "pico/time.h"
-#if !PICO_NO_HARDWARE
-static_assert(sizeof(mutex_t) == 8, "");
-#endif
+static void mutex_init_internal(mutex_t *mtx, uint8_t recursion_state) {
+ lock_init(&mtx->core, next_striped_spin_lock_num());
+ mtx->owner = LOCK_INVALID_OWNER_ID;
+ mtx->recursion_state = recursion_state;
+ __mem_fence_release();
+}
void mutex_init(mutex_t *mtx) {
- lock_init(&mtx->core, next_striped_spin_lock_num());
- mtx->owner = -1;
- __mem_fence_release();
+ mutex_init_internal(mtx, 0);
+}
+
+void recursive_mutex_init(mutex_t *mtx) {
+ mutex_init_internal(mtx, MAX_RECURSION_STATE);
}
void __time_critical_func(mutex_enter_blocking)(mutex_t *mtx) {
assert(mtx->core.spin_lock);
- bool block = true;
do {
uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
- if (mtx->owner < 0) {
- mtx->owner = (int8_t)get_core_num();
- block = false;
+ lock_owner_id_t caller = lock_get_caller_owner_id();
+ if (mtx->owner == LOCK_INVALID_OWNER_ID) {
+ mtx->owner = caller;
+ if (mtx->recursion_state) {
+ assert(mtx->recursion_state == MAX_RECURSION_STATE);
+ mtx->recursion_state--;
+ }
+ } else if (mtx->owner == caller && mtx->recursion_state > 1) {
+ mtx->recursion_state--;
+ } else {
+ lock_internal_spin_unlock_with_wait(&mtx->core, save);
+ // spin lock already unlocked, so loop again
+ continue;
}
spin_unlock(mtx->core.spin_lock, save);
- if (block) {
- __wfe();
- }
- } while (block);
+ break;
+ } while (true);
}
bool __time_critical_func(mutex_try_enter)(mutex_t *mtx, uint32_t *owner_out) {
bool entered;
uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
- if (mtx->owner < 0) {
- mtx->owner = (int8_t)get_core_num();
+ lock_owner_id_t caller = lock_get_caller_owner_id();
+ if (mtx->owner == LOCK_INVALID_OWNER_ID) {
+ mtx->owner = lock_get_caller_owner_id();
+ entered = true;
+ } else if (mtx->owner == caller && mtx->recursion_state > 1) {
+ mtx->recursion_state--;
entered = true;
} else {
if (owner_out) *owner_out = (uint32_t) mtx->owner;
@@ -51,29 +67,47 @@
return mutex_enter_block_until(mtx, make_timeout_time_ms(timeout_ms));
}
+bool __time_critical_func(mutex_enter_timeout_us)(mutex_t *mtx, uint32_t timeout_us) {
+ return mutex_enter_block_until(mtx, make_timeout_time_us(timeout_us));
+}
+
bool __time_critical_func(mutex_enter_block_until)(mutex_t *mtx, absolute_time_t until) {
assert(mtx->core.spin_lock);
- bool block = true;
do {
uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
- if (mtx->owner < 0) {
- mtx->owner = (int8_t)get_core_num();
- block = false;
- }
- spin_unlock(mtx->core.spin_lock, save);
- if (block) {
- if (best_effort_wfe_or_timeout(until)) {
+ lock_owner_id_t caller = lock_get_caller_owner_id();
+ if (mtx->owner == LOCK_INVALID_OWNER_ID) {
+ mtx->owner = caller;
+ } else if (mtx->owner == caller && mtx->recursion_state > 1) {
+ mtx->recursion_state--;
+ } else {
+ if (lock_internal_spin_unlock_with_best_effort_wait_or_timeout(&mtx->core, save, until)) {
+ // timed out
return false;
+ } else {
+ // not timed out; spin lock already unlocked, so loop again
+ continue;
}
}
- } while (block);
- return true;
+ spin_unlock(mtx->core.spin_lock, save);
+ return true;
+ } while (true);
}
void __time_critical_func(mutex_exit)(mutex_t *mtx) {
uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
- assert(mtx->owner >= 0);
- mtx->owner = -1;
- __sev();
- spin_unlock(mtx->core.spin_lock, save);
-}
+ assert(mtx->owner != LOCK_INVALID_OWNER_ID);
+ if (!mtx->recursion_state) {
+ mtx->owner = LOCK_INVALID_OWNER_ID;
+ lock_internal_spin_unlock_with_notify(&mtx->core, save);
+ } else {
+ mtx->recursion_state++;
+ assert(mtx->recursion_state);
+ if (mtx->recursion_state == MAX_RECURSION_STATE) {
+ mtx->owner = LOCK_INVALID_OWNER_ID;
+ lock_internal_spin_unlock_with_notify(&mtx->core, save);
+ } else {
+ spin_unlock(mtx->core.spin_lock, save);
+ }
+ }
+}
\ No newline at end of file
diff --git a/src/common/pico_sync/sem.c b/src/common/pico_sync/sem.c
index 195cd9a..06b4946 100644
--- a/src/common/pico_sync/sem.c
+++ b/src/common/pico_sync/sem.c
@@ -19,64 +19,61 @@
}
void __time_critical_func(sem_acquire_blocking)(semaphore_t *sem) {
- bool block = true;
do {
uint32_t save = spin_lock_blocking(sem->core.spin_lock);
if (sem->permits > 0) {
sem->permits--;
- __sev();
- block = false;
+ lock_internal_spin_unlock_with_notify(&sem->core, save);
+ break;
}
- spin_unlock(sem->core.spin_lock, save);
- if (block) {
- __wfe();
- }
- } while (block);
+ lock_internal_spin_unlock_with_wait(&sem->core, save);
+ } while (true);
}
bool __time_critical_func(sem_acquire_timeout_ms)(semaphore_t *sem, uint32_t timeout_ms) {
- bool block = true;
- absolute_time_t target = nil_time;
+ return sem_acquire_block_until(sem, make_timeout_time_ms(timeout_ms));
+}
+
+bool __time_critical_func(sem_acquire_timeout_us)(semaphore_t *sem, uint32_t timeout_us) {
+ return sem_acquire_block_until(sem, make_timeout_time_us(timeout_us));
+}
+
+bool __time_critical_func(sem_acquire_block_until)(semaphore_t *sem, absolute_time_t until) {
do {
uint32_t save = spin_lock_blocking(sem->core.spin_lock);
if (sem->permits > 0) {
sem->permits--;
- __sev();
- block = false;
+ lock_internal_spin_unlock_with_notify(&sem->core, save);
+ return true;
}
- spin_unlock(sem->core.spin_lock, save);
- if (block) {
- if (is_nil_time(target)) {
- target = make_timeout_time_ms(timeout_ms);
- }
- if (best_effort_wfe_or_timeout(target)) {
- return false;
- }
+ if (lock_internal_spin_unlock_with_best_effort_wait_or_timeout(&sem->core, save, until)) {
+ return false;
}
- } while (block);
- return true;
+ } while (true);
}
// todo this should really have a blocking variant for when permits are maxed out
bool __time_critical_func(sem_release)(semaphore_t *sem) {
- bool rc;
uint32_t save = spin_lock_blocking(sem->core.spin_lock);
int32_t count = sem->permits;
if (count < sem->max_permits) {
sem->permits = (int16_t)(count + 1);
- __sev();
- rc = true;
+ lock_internal_spin_unlock_with_notify(&sem->core, save);
+ return true;
} else {
- rc = false;
+ spin_unlock(sem->core.spin_lock, save);
+ return false;
}
- spin_unlock(sem->core.spin_lock, save);
- return rc;
}
void __time_critical_func(sem_reset)(semaphore_t *sem, int16_t permits) {
assert(permits >= 0 && permits <= sem->max_permits);
uint32_t save = spin_lock_blocking(sem->core.spin_lock);
- if (permits > sem->permits) __sev();
- sem->permits = permits;
- spin_unlock(sem->core.spin_lock, save);
+ if (permits > sem->permits) {
+ sem->permits = permits;
+ lock_internal_spin_unlock_with_notify(&sem->core, save);
+ } else {
+ sem->permits = permits;
+ spin_unlock(sem->core.spin_lock, save);
+ }
}
diff --git a/src/common/pico_time/CMakeLists.txt b/src/common/pico_time/CMakeLists.txt
index fe38855..9e497a7 100644
--- a/src/common/pico_time/CMakeLists.txt
+++ b/src/common/pico_time/CMakeLists.txt
@@ -7,7 +7,7 @@
endif()
if (NOT TARGET pico_time)
- add_library(pico_time INTERFACE)
+ pico_add_impl_library(pico_time)
target_sources(pico_time INTERFACE
${CMAKE_CURRENT_LIST_DIR}/time.c
diff --git a/src/common/pico_time/time.c b/src/common/pico_time/time.c
index 2105214..f965ab8 100644
--- a/src/common/pico_time/time.c
+++ b/src/common/pico_time/time.c
@@ -5,12 +5,13 @@
*/
#include <limits.h>
+#include <inttypes.h>
#include <stdio.h>
#include <stdlib.h>
#include "pico.h"
#include "pico/time.h"
#include "pico/util/pheap.h"
-#include "hardware/sync.h"
+#include "pico/sync.h"
const absolute_time_t ABSOLUTE_TIME_INITIALIZED_VAR(nil_time, 0);
const absolute_time_t ABSOLUTE_TIME_INITIALIZED_VAR(at_the_end_of_time, INT64_MAX);
@@ -37,6 +38,7 @@
PHEAP_DEFINE_STATIC(default_alarm_pool_heap, PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS);
static alarm_pool_entry_t default_alarm_pool_entries[PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS];
static uint8_t default_alarm_pool_entry_ids_high[PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS];
+static lock_core_t sleep_notifier;
static alarm_pool_t default_alarm_pool = {
.heap = &default_alarm_pool_heap,
@@ -81,6 +83,7 @@
alarm_pool_post_alloc_init(&default_alarm_pool,
PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM);
}
+ lock_init(&sleep_notifier, PICO_SPINLOCK_ID_TIMER);
#endif
}
@@ -276,11 +279,11 @@
#if PICO_ON_DEVICE
printf("%lld (hi %02x)", to_us_since_boot(get_entry(pool, id)->target), *get_entry_id_high(pool, id));
#else
- printf("%ld", to_us_since_boot(get_entry(pool, id)->target));
+ printf(PRIu64, to_us_since_boot(get_entry(pool, id)->target));
#endif
}
-static int64_t repeating_timer_callback(__unused alarm_id_t id, __unused void *user_data) {
+static int64_t repeating_timer_callback(__unused alarm_id_t id, void *user_data) {
repeating_timer_t *rt = (repeating_timer_t *)user_data;
assert(rt->alarm_id == id);
if (rt->callback(rt)) {
@@ -318,8 +321,9 @@
}
#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
-static int64_t sev_callback(__unused alarm_id_t id, __unused void *user_data) {
- __sev();
+static int64_t sleep_until_callback(__unused alarm_id_t id, __unused void *user_data) {
+ uint32_t save = spin_lock_blocking(sleep_notifier.spin_lock);
+ lock_internal_spin_unlock_with_notify(&sleep_notifier, save);
return 0;
}
#endif
@@ -338,13 +342,17 @@
absolute_time_t t_before;
update_us_since_boot(&t_before, t_before_us);
if (absolute_time_diff_us(get_absolute_time(), t_before) > 0) {
- if (add_alarm_at(t_before, sev_callback, NULL, false) >= 0) {
+ if (add_alarm_at(t_before, sleep_until_callback, NULL, false) >= 0) {
// able to add alarm for just before the time
while (!time_reached(t_before)) {
- __wfe();
+ uint32_t save = spin_lock_blocking(sleep_notifier.spin_lock);
+ lock_internal_spin_unlock_with_wait(&sleep_notifier, save);
}
}
}
+#else
+ // hook in case we're in RTOS; note we assume using the alarm pool is better always if available.
+ sync_internal_yield_until_before(t);
#endif
// now wait until the exact time
busy_wait_until(t);
@@ -354,13 +362,17 @@
#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
sleep_until(make_timeout_time_us(us));
#else
- if (us >> 32u) {
- busy_wait_until(make_timeout_time_us(us));
+ if (us < PICO_TIME_SLEEP_OVERHEAD_ADJUST_US) {
+ busy_wait_us(us);
} else {
- busy_wait_us_32(us);
+ // hook in case we're in RTOS; note we assume using the alarm pool is better always if available.
+ absolute_time_t t = make_timeout_time_us(us - PICO_TIME_SLEEP_OVERHEAD_ADJUST_US);
+ sync_internal_yield_until_before(t);
+
+ // then wait the rest of thw way
+ busy_wait_until(t);
}
#endif
-
}
void sleep_ms(uint32_t ms) {
@@ -370,7 +382,7 @@
bool best_effort_wfe_or_timeout(absolute_time_t timeout_timestamp) {
#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
alarm_id_t id;
- id = add_alarm_at(timeout_timestamp, sev_callback, NULL, false);
+ id = add_alarm_at(timeout_timestamp, sleep_until_callback, NULL, false);
if (id <= 0) {
tight_loop_contents();
return time_reached(timeout_timestamp);
diff --git a/src/common/pico_util/CMakeLists.txt b/src/common/pico_util/CMakeLists.txt
index a829c14..3eb6998 100644
--- a/src/common/pico_util/CMakeLists.txt
+++ b/src/common/pico_util/CMakeLists.txt
@@ -5,7 +5,7 @@
endif()
if (NOT TARGET pico_util)
- add_library(pico_util INTERFACE)
+ pico_add_impl_library(pico_util)
target_sources(pico_util INTERFACE
${CMAKE_CURRENT_LIST_DIR}/datetime.c
${CMAKE_CURRENT_LIST_DIR}/pheap.c
diff --git a/src/common/pico_util/include/pico/util/queue.h b/src/common/pico_util/include/pico/util/queue.h
index 60a450a..097578a 100644
--- a/src/common/pico_util/include/pico/util/queue.h
+++ b/src/common/pico_util/include/pico/util/queue.h
@@ -10,6 +10,11 @@
#include "pico.h"
#include "hardware/sync.h"
+// PICO_CONFIG: PICO_QUEUE_MAX_LEVEL, Maintain a field for the highest level that has been reached by a queue, type=bool, default=0, advanced=true, group=queue
+#ifndef PICO_QUEUE_MAX_LEVEL
+#define PICO_QUEUE_MAX_LEVEL 0
+#endif
+
/** \file queue.h
* \defgroup queue queue
* Multi-core and IRQ safe queue implementation.
@@ -22,13 +27,18 @@
extern "C" {
#endif
+#include "pico/lock_core.h"
+
typedef struct {
- spin_lock_t *lock;
+ lock_core_t core;
uint8_t *data;
uint16_t wptr;
uint16_t rptr;
uint16_t element_size;
uint16_t element_count;
+#if PICO_QUEUE_MAX_LEVEL
+ uint16_t max_level;
+#endif
} queue_t;
/*! \brief Initialise a queue with a specific spinlock for concurrency protection
@@ -85,12 +95,38 @@
* \return Number of entries in the queue
*/
static inline uint queue_get_level(queue_t *q) {
- uint32_t save = spin_lock_blocking(q->lock);
+ uint32_t save = spin_lock_blocking(q->core.spin_lock);
uint level = queue_get_level_unsafe(q);
- spin_unlock(q->lock, save);
+ spin_unlock(q->core.spin_lock, save);
return level;
}
+/*! \brief Returns the highest level reached by the specified queue since it was created
+ * or since the max level was reset
+ * \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ * \return Maximum level of the queue
+ */
+#if PICO_QUEUE_MAX_LEVEL
+static inline uint queue_get_max_level(queue_t *q) {
+ return q->max_level;
+}
+#endif
+
+/*! \brief Reset the highest level reached of the specified queue.
+ * \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ */
+#if PICO_QUEUE_MAX_LEVEL
+static inline void queue_reset_max_level(queue_t *q) {
+ uint32_t save = spin_lock_blocking(q->core.spin_lock);
+ q->max_level = queue_get_level_unsafe(q);
+ spin_unlock(q->core.spin_lock, save);
+}
+#endif
+
/*! \brief Check if queue is empty
* \ingroup queue
*
@@ -127,7 +163,7 @@
* If the queue is full this function will return immediately with false, otherwise
* the data is copied into a new value added to the queue, and this function will return true.
*/
-bool queue_try_add(queue_t *q, void *data);
+bool queue_try_add(queue_t *q, const void *data);
/*! \brief Non-blocking removal of entry from the queue if non empty
* \ingroup queue
@@ -163,7 +199,7 @@
*
* If the queue is full this function will block, until a removal happens on the queue
*/
-void queue_add_blocking(queue_t *q, void *data);
+void queue_add_blocking(queue_t *q, const void *data);
/*! \brief Blocking remove entry from queue
* \ingroup queue
diff --git a/src/common/pico_util/queue.c b/src/common/pico_util/queue.c
index 4b1c27e..a5c8e18 100644
--- a/src/common/pico_util/queue.c
+++ b/src/common/pico_util/queue.c
@@ -9,7 +9,7 @@
#include "pico/util/queue.h"
void queue_init_with_spinlock(queue_t *q, uint element_size, uint element_count, uint spinlock_num) {
- q->lock = spin_lock_instance(spinlock_num);
+ lock_init(&q->core, spinlock_num);
q->data = (uint8_t *)calloc(element_count + 1, element_size);
q->element_count = (uint16_t)element_count;
q->element_size = (uint16_t)element_size;
@@ -30,69 +30,90 @@
if (++index > q->element_count) { // > because we have element_count + 1 elements
index = 0;
}
+
+#if PICO_QUEUE_MAX_LEVEL
+ uint16_t level = queue_get_level_unsafe(q);
+ if (level > q->max_level) {
+ q->max_level = level;
+ }
+#endif
+
return index;
}
-bool queue_try_add(queue_t *q, void *data) {
- bool success = false;
- uint32_t flags = spin_lock_blocking(q->lock);
- if (queue_get_level_unsafe(q) != q->element_count) {
- memcpy(element_ptr(q, q->wptr), data, q->element_size);
- q->wptr = inc_index(q, q->wptr);
- success = true;
- }
- spin_unlock(q->lock, flags);
- if (success) __sev();
- return success;
+static bool queue_add_internal(queue_t *q, const void *data, bool block) {
+ do {
+ uint32_t save = spin_lock_blocking(q->core.spin_lock);
+ if (queue_get_level_unsafe(q) != q->element_count) {
+ memcpy(element_ptr(q, q->wptr), data, q->element_size);
+ q->wptr = inc_index(q, q->wptr);
+ lock_internal_spin_unlock_with_notify(&q->core, save);
+ return true;
+ }
+ if (block) {
+ lock_internal_spin_unlock_with_wait(&q->core, save);
+ } else {
+ spin_unlock(q->core.spin_lock, save);
+ return false;
+ }
+ } while (true);
+}
+
+static bool queue_remove_internal(queue_t *q, void *data, bool block) {
+ do {
+ uint32_t save = spin_lock_blocking(q->core.spin_lock);
+ if (queue_get_level_unsafe(q) != 0) {
+ memcpy(data, element_ptr(q, q->rptr), q->element_size);
+ q->rptr = inc_index(q, q->rptr);
+ lock_internal_spin_unlock_with_notify(&q->core, save);
+ return true;
+ }
+ if (block) {
+ lock_internal_spin_unlock_with_wait(&q->core, save);
+ } else {
+ spin_unlock(q->core.spin_lock, save);
+ return false;
+ }
+ } while (true);
+}
+
+static bool queue_peek_internal(queue_t *q, void *data, bool block) {
+ do {
+ uint32_t save = spin_lock_blocking(q->core.spin_lock);
+ if (queue_get_level_unsafe(q) != 0) {
+ memcpy(data, element_ptr(q, q->rptr), q->element_size);
+ lock_internal_spin_unlock_with_notify(&q->core, save);
+ return true;
+ }
+ if (block) {
+ lock_internal_spin_unlock_with_wait(&q->core, save);
+ } else {
+ spin_unlock(q->core.spin_lock, save);
+ return false;
+ }
+ } while (true);
+}
+
+bool queue_try_add(queue_t *q, const void *data) {
+ return queue_add_internal(q, data, false);
}
bool queue_try_remove(queue_t *q, void *data) {
- bool success = false;
- uint32_t flags = spin_lock_blocking(q->lock);
- if (queue_get_level_unsafe(q) != 0) {
- memcpy(data, element_ptr(q, q->rptr), q->element_size);
- q->rptr = inc_index(q, q->rptr);
- success = true;
- }
- spin_unlock(q->lock, flags);
- if (success) __sev();
- return success;
+ return queue_remove_internal(q, data, false);
}
bool queue_try_peek(queue_t *q, void *data) {
- bool success = false;
- uint32_t flags = spin_lock_blocking(q->lock);
- if (queue_get_level_unsafe(q) != 0) {
- memcpy(data, element_ptr(q, q->rptr), q->element_size);
- success = true;
- }
- spin_unlock(q->lock, flags);
- return success;
+ return queue_peek_internal(q, data, false);
}
-void queue_add_blocking(queue_t *q, void *data) {
- bool done;
- do {
- done = queue_try_add(q, data);
- if (done) break;
- __wfe();
- } while (true);
+void queue_add_blocking(queue_t *q, const void *data) {
+ queue_add_internal(q, data, true);
}
void queue_remove_blocking(queue_t *q, void *data) {
- bool done;
- do {
- done = queue_try_remove(q, data);
- if (done) break;
- __wfe();
- } while (true);
+ queue_remove_internal(q, data, true);
}
void queue_peek_blocking(queue_t *q, void *data) {
- bool done;
- do {
- done = queue_try_peek(q, data);
- if (done) break;
- __wfe();
- } while (true);
+ queue_peek_internal(q, data, true);
}
diff --git a/src/host/CMakeLists.txt b/src/host/CMakeLists.txt
index 13a73ad..9edcd7b 100644
--- a/src/host/CMakeLists.txt
+++ b/src/host/CMakeLists.txt
@@ -32,4 +32,6 @@
set(PICO_HOST_DIR "${CMAKE_CURRENT_LIST_DIR}" CACHE INTERNAL "")
function(pico_define_boot_stage2 NAME)
add_executable(${NAME} ${PICO_HOST_DIR}/boot_stage2.c)
-endfunction()
\ No newline at end of file
+endfunction()
+
+pico_promote_common_scope_vars()
\ No newline at end of file
diff --git a/src/host/hardware_divider/include/hardware/divider.h b/src/host/hardware_divider/include/hardware/divider.h
index 4d81874..c126688 100644
--- a/src/host/hardware_divider/include/hardware/divider.h
+++ b/src/host/hardware_divider/include/hardware/divider.h
@@ -78,7 +78,7 @@
}
static inline uint32_t hw_divider_u32_quotient(uint32_t a, uint32_t b) {
- return b ? (a / b) : -1;
+ return b ? (a / b) : (uint32_t)(-1);
}
static inline uint32_t hw_divider_u32_remainder(uint32_t a, uint32_t b) {
diff --git a/src/host/hardware_gpio/gpio.c b/src/host/hardware_gpio/gpio.c
index d5f4996..1cbcbed 100644
--- a/src/host/hardware_gpio/gpio.c
+++ b/src/host/hardware_gpio/gpio.c
@@ -27,6 +27,10 @@
}
+void gpio_set_irqover(uint gpio, uint value) {
+
+}
+
void gpio_set_outover(uint gpio, uint value) {
}
@@ -39,6 +43,31 @@
}
+void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled){
+
+}
+
+bool gpio_is_input_hysteresis_enabled(uint gpio){
+ return true;
+}
+
+void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew){
+
+}
+
+enum gpio_slew_rate gpio_get_slew_rate(uint gpio){
+ return GPIO_SLEW_RATE_FAST;
+}
+
+void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive){
+
+}
+
+enum gpio_drive_strength gpio_get_drive_strength(uint gpio){
+ return GPIO_DRIVE_STRENGTH_4MA;
+}
+
+
void gpio_set_irq_enabled(uint gpio, uint32_t events, bool enable) {
}
@@ -115,4 +144,4 @@
void gpio_init_mask(uint gpio_mask) {
-}
\ No newline at end of file
+}
diff --git a/src/host/hardware_gpio/include/hardware/gpio.h b/src/host/hardware_gpio/include/hardware/gpio.h
index d1b14ba..223c472 100644
--- a/src/host/hardware_gpio/include/hardware/gpio.h
+++ b/src/host/hardware_gpio/include/hardware/gpio.h
@@ -27,6 +27,17 @@
GPIO_FUNC_NULL = 0xf,
};
+enum gpio_slew_rate {
+ GPIO_SLEW_RATE_SLOW = 0, ///< Slew rate limiting enabled
+ GPIO_SLEW_RATE_FAST = 1 ///< Slew rate limiting disabled
+};
+
+enum gpio_drive_strength {
+ GPIO_DRIVE_STRENGTH_2MA = 0, ///< 2 mA nominal drive strength
+ GPIO_DRIVE_STRENGTH_4MA = 1, ///< 4 mA nominal drive strength
+ GPIO_DRIVE_STRENGTH_8MA = 2, ///< 8 mA nominal drive strength
+ GPIO_DRIVE_STRENGTH_12MA = 3 ///< 12 mA nominal drive strength
+};
#define GPIO_OUT 1
#define GPIO_IN 0
@@ -50,6 +61,8 @@
void gpio_set_pulls(uint gpio, bool up, bool down);
+void gpio_set_irqover(uint gpio, uint value);
+
void gpio_set_outover(uint gpio, uint value);
void gpio_set_inover(uint gpio, uint value);
@@ -58,6 +71,18 @@
void gpio_set_input_enabled(uint gpio, bool enable);
+void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled);
+
+bool gpio_is_input_hysteresis_enabled(uint gpio);
+
+void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew);
+
+enum gpio_slew_rate gpio_get_slew_rate(uint gpio);
+
+void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive);
+
+enum gpio_drive_strength gpio_get_drive_strength(uint gpio);
+
// Configure a GPIO for direct input/output from software
void gpio_init(uint gpio);
diff --git a/src/host/hardware_uart/uart.c b/src/host/hardware_uart/uart.c
index 2e5dae3..e610402 100644
--- a/src/host/hardware_uart/uart.c
+++ b/src/host/hardware_uart/uart.c
@@ -24,7 +24,7 @@
static tcflag_t _res_oflg = 0;
static tcflag_t _res_lflg = 0;
-void _resetty(void) {
+void _resettty(void) {
if (!isatty(STDIN_FILENO))
return;
@@ -49,7 +49,7 @@
tcsetattr(STDIN_FILENO, TCSANOW, &_tty);
fcntl(STDIN_FILENO, F_SETFL, FNONBLOCK);
- atexit(_resetty);
+ atexit(_resettty);
}
#else
@@ -88,10 +88,18 @@
}
// Write len bytes directly from src to the UART
-//void uart_write_blocking(uart_inst_t uart, const uint8_t *src, size_t len);
+void uart_write_blocking(uart_inst_t *uart, const uint8_t *src, size_t len) {
+ for (size_t i = 0; i < len; i++) {
+ uart_putc(uart, src[i]);
+ }
+}
// Read len bytes directly from the UART to dst
-//void uart_read_blocking(uart_inst_t uart, uint8_t *dst, size_t len);
+void uart_read_blocking(uart_inst_t *uart, uint8_t *dst, size_t len) {
+ for (size_t i = 0; i < len; i++) {
+ dst[i] = uart_getc(uart);
+ }
+}
// ----------------------------------------------------------------------------
// UART-specific operations and aliases
diff --git a/src/host/pico_bit_ops/CMakeLists.txt b/src/host/pico_bit_ops/CMakeLists.txt
index e4f8829..7732b1e 100644
--- a/src/host/pico_bit_ops/CMakeLists.txt
+++ b/src/host/pico_bit_ops/CMakeLists.txt
@@ -1,4 +1,4 @@
-add_library(pico_bit_ops INTERFACE)
+pico_add_impl_library(pico_bit_ops)
target_sources(pico_bit_ops INTERFACE
${CMAKE_CURRENT_LIST_DIR}/bit_ops.c)
diff --git a/src/host/pico_divider/CMakeLists.txt b/src/host/pico_divider/CMakeLists.txt
index 7a26204..f6936dd 100644
--- a/src/host/pico_divider/CMakeLists.txt
+++ b/src/host/pico_divider/CMakeLists.txt
@@ -1,4 +1,4 @@
-add_library(pico_divider INTERFACE)
+pico_add_impl_library(pico_divider)
target_sources(pico_divider INTERFACE
${CMAKE_CURRENT_LIST_DIR}/divider.c)
diff --git a/src/host/pico_multicore/CMakeLists.txt b/src/host/pico_multicore/CMakeLists.txt
index c5eabda..5b90fa3 100644
--- a/src/host/pico_multicore/CMakeLists.txt
+++ b/src/host/pico_multicore/CMakeLists.txt
@@ -1,5 +1,5 @@
if (NOT TARGET pico_multicore)
- add_library(pico_multicore INTERFACE)
+ pico_add_impl_library(pico_multicore)
target_include_directories(pico_multicore INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
endif()
diff --git a/src/host/pico_multicore/include/pico/multicore.h b/src/host/pico_multicore/include/pico/multicore.h
index f4d8364..1be1694 100644
--- a/src/host/pico_multicore/include/pico/multicore.h
+++ b/src/host/pico_multicore/include/pico/multicore.h
@@ -20,11 +20,13 @@
bool multicore_fifo_rvalid(void);
bool multicore_fifo_wready(void);
-void multicore_fifo_push(uint32_t data);
+void multicore_fifo_push_blocking(uint32_t data);
+bool multicore_fifo_push_timeout_us(uint32_t data, uint64_t timeout_us);
uint32_t multicore_fifo_pop_blocking();
+bool multicore_fifo_pop_timeout_us(uint64_t timeout_us, uint32_t *out);
void multicore_fifo_drain(void);
void multicore_fifo_clear_irq(void);
-int32_t multicore_fifo_get_status(void);
+uint32_t multicore_fifo_get_status(void);
// call this from the lockout victim thread
void multicore_lockout_victim_init(void);
diff --git a/src/host/pico_platform/CMakeLists.txt b/src/host/pico_platform/CMakeLists.txt
index 92ae6a2..c78e330 100644
--- a/src/host/pico_platform/CMakeLists.txt
+++ b/src/host/pico_platform/CMakeLists.txt
@@ -1,3 +1,5 @@
+# This file may be included directly by a build to get common SDK macros and types
+
if (NOT TARGET pico_platform_headers)
add_library(pico_platform_headers INTERFACE)
@@ -11,7 +13,11 @@
endif()
if (NOT TARGET pico_platform)
- add_library(pico_platform INTERFACE)
+ if (COMMAND pico_add_platform_library)
+ pico_add_platform_library(pico_platform)
+ else()
+ add_library(pico_platform INTERFACE)
+ endif()
target_sources(pico_platform INTERFACE
${CMAKE_CURRENT_LIST_DIR}/platform_base.c
@@ -22,4 +28,4 @@
function(pico_add_platform_library TARGET)
target_link_libraries(pico_platform INTERFACE ${TARGET})
-endfunction()
\ No newline at end of file
+endfunction()
diff --git a/src/host/pico_platform/include/pico/platform.h b/src/host/pico_platform/include/pico/platform.h
index da060a6..499bdf6 100644
--- a/src/host/pico_platform/include/pico/platform.h
+++ b/src/host/pico_platform/include/pico/platform.h
@@ -36,6 +36,10 @@
//int running_on_fpga() { return false; }
extern void tight_loop_contents();
+#ifndef __STRING
+#define __STRING(x) #x
+#endif
+
#ifndef _MSC_VER
#ifndef __noreturn
#define __noreturn __attribute((noreturn))
@@ -77,10 +81,6 @@
#define __CONCAT(x,y) x ## y
#endif
-#ifndef __STRING
-#define __STRING(x) #x
-#endif()
-
#define __thread __declspec( thread )
#define PICO_WEAK_FUNCTION_DEF(x) __pragma(comment(linker, __STRING(/alternatename:_##x=_##x##__weak)));
diff --git a/src/host/pico_printf/CMakeLists.txt b/src/host/pico_printf/CMakeLists.txt
index 2151746..8bfbdee 100644
--- a/src/host/pico_printf/CMakeLists.txt
+++ b/src/host/pico_printf/CMakeLists.txt
@@ -1,5 +1,5 @@
if (NOT TARGET pico_printf)
- add_library(pico_printf INTERFACE)
+ pico_add_impl_library(pico_printf)
function(pico_set_printf_implementation)
endfunction()
endif()
diff --git a/src/host/pico_stdio/CMakeLists.txt b/src/host/pico_stdio/CMakeLists.txt
index 8ab5ed4..428c1a9 100644
--- a/src/host/pico_stdio/CMakeLists.txt
+++ b/src/host/pico_stdio/CMakeLists.txt
@@ -1,14 +1,14 @@
if (NOT TARGET pico_stdio)
- add_library(pico_stdio INTERFACE)
+ pico_add_impl_library(pico_stdio)
target_include_directories(pico_stdio INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
target_sources(pico_stdio INTERFACE
${CMAKE_CURRENT_LIST_DIR}/stdio.c
)
- add_library(pico_stdio_usb INTERFACE)
- add_library(pico_stdio_uart INTERFACE)
- add_library(pico_stdio_semihosting INTERFACE)
+ pico_add_impl_library(pico_stdio_usb)
+ pico_add_impl_library(pico_stdio_uart)
+ pico_add_impl_library(pico_stdio_semihosting)
function(pico_enable_stdio_uart)
endfunction()
diff --git a/src/host/pico_stdlib/CMakeLists.txt b/src/host/pico_stdlib/CMakeLists.txt
index f4dac4d..257798c 100644
--- a/src/host/pico_stdlib/CMakeLists.txt
+++ b/src/host/pico_stdlib/CMakeLists.txt
@@ -1,5 +1,5 @@
if (NOT TARGET pico_stdlib)
- add_library(pico_stdlib INTERFACE)
+ pico_add_impl_library(pico_stdlib)
target_sources(pico_stdlib INTERFACE
${CMAKE_CURRENT_LIST_DIR}/stdlib.c
diff --git a/src/rp2040/CMakeLists.txt b/src/rp2040/CMakeLists.txt
index a6089de..a19ea5c 100644
--- a/src/rp2040/CMakeLists.txt
+++ b/src/rp2040/CMakeLists.txt
@@ -4,3 +4,5 @@
pico_add_doxygen(${CMAKE_CURRENT_LIST_DIR})
pico_add_doxygen_exclude(${CMAKE_CURRENT_LIST_DIR}/hardware_regs) # very very big
+
+pico_promote_common_scope_vars()
\ No newline at end of file
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/i2c.h b/src/rp2040/hardware_regs/include/hardware/regs/i2c.h
index f797044..9384bed 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/i2c.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/i2c.h
@@ -585,24 +585,9 @@
// matching interrupt clear register. The unmasked raw versions of
// these bits are available in the IC_RAW_INTR_STAT register.
#define I2C_IC_INTR_STAT_OFFSET _u(0x0000002c)
-#define I2C_IC_INTR_STAT_BITS _u(0x00003fff)
+#define I2C_IC_INTR_STAT_BITS _u(0x00001fff)
#define I2C_IC_INTR_STAT_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
-// Field : I2C_IC_INTR_STAT_R_MASTER_ON_HOLD
-// Description : See IC_RAW_INTR_STAT for a detailed description of
-// R_MASTER_ON_HOLD bit.
-//
-// Reset value: 0x0
-// 0x0 -> R_MASTER_ON_HOLD interrupt is inactive
-// 0x1 -> R_MASTER_ON_HOLD interrupt is active
-#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_RESET _u(0x0)
-#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_BITS _u(0x00002000)
-#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_MSB _u(13)
-#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_LSB _u(13)
-#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_ACCESS "RO"
-#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_VALUE_INACTIVE _u(0x0)
-#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_VALUE_ACTIVE _u(0x1)
-// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_STAT_R_RESTART_DET
// Description : See IC_RAW_INTR_STAT for a detailed description of
// R_RESTART_DET bit.
@@ -805,24 +790,9 @@
// register is active low; a value of 0 masks the interrupt,
// whereas a value of 1 unmasks the interrupt.
#define I2C_IC_INTR_MASK_OFFSET _u(0x00000030)
-#define I2C_IC_INTR_MASK_BITS _u(0x00003fff)
+#define I2C_IC_INTR_MASK_BITS _u(0x00001fff)
#define I2C_IC_INTR_MASK_RESET _u(0x000008ff)
// -----------------------------------------------------------------------------
-// Field : I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY
-// Description : This M_MASTER_ON_HOLD_read_only bit masks the R_MASTER_ON_HOLD
-// interrupt in IC_INTR_STAT register.
-//
-// Reset value: 0x0
-// 0x0 -> MASTER_ON_HOLD interrupt is masked
-// 0x1 -> MASTER_ON_HOLD interrupt is unmasked
-#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_RESET _u(0x0)
-#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_BITS _u(0x00002000)
-#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_MSB _u(13)
-#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_LSB _u(13)
-#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_ACCESS "RO"
-#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_VALUE_ENABLED _u(0x0)
-#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_VALUE_DISABLED _u(0x1)
-// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_MASK_M_RESTART_DET
// Description : This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT
// register.
@@ -1023,25 +993,9 @@
// Unlike the IC_INTR_STAT register, these bits are not masked so
// they always show the true status of the DW_apb_i2c.
#define I2C_IC_RAW_INTR_STAT_OFFSET _u(0x00000034)
-#define I2C_IC_RAW_INTR_STAT_BITS _u(0x00003fff)
+#define I2C_IC_RAW_INTR_STAT_BITS _u(0x00001fff)
#define I2C_IC_RAW_INTR_STAT_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
-// Field : I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD
-// Description : Indicates whether master is holding the bus and TX FIFO is
-// empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and
-// IC_EMPTYFIFO_HOLD_MASTER_EN=1.
-//
-// Reset value: 0x0
-// 0x0 -> MASTER_ON_HOLD interrupt is inactive
-// 0x1 -> MASTER_ON_HOLD interrupt is active
-#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_RESET _u(0x0)
-#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_BITS _u(0x00002000)
-#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_MSB _u(13)
-#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_LSB _u(13)
-#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_ACCESS "RO"
-#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_VALUE_INACTIVE _u(0x0)
-#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_VALUE_ACTIVE _u(0x1)
-// -----------------------------------------------------------------------------
// Field : I2C_IC_RAW_INTR_STAT_RESTART_DET
// Description : Indicates whether a RESTART condition has occurred on the I2C
// interface when DW_apb_i2c is operating in Slave mode and the
@@ -1839,8 +1793,8 @@
//
// The values in this register are in units of ic_clk period. The
// value programmed in IC_SDA_TX_HOLD must be greater than the
-// minimum hold time in each mode one cycle in master mode, seven
-// cycles in slave mode for the value to be implemented.
+// minimum hold time in each mode (one cycle in master mode, seven
+// cycles in slave mode) for the value to be implemented.
//
// The programmed SDA hold time during transmit (IC_SDA_TX_HOLD)
// cannot exceed at any time the duration of the low part of scl.
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/rosc.h b/src/rp2040/hardware_regs/include/hardware/regs/rosc.h
index 694f749..5501e7e 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/rosc.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/rosc.h
@@ -190,7 +190,7 @@
// set to 0xaa0 + div where
// div = 0 divides by 32
// div = 1-31 divides by div
-// any other value sets div=0 and therefore divides by 32
+// any other value sets div=31
// this register resets to div=16
// 0xaa0 -> PASS
#define ROSC_DIV_OFFSET _u(0x00000010)
@@ -208,7 +208,7 @@
#define ROSC_PHASE_RESET _u(0x00000008)
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_PASSWD
-// Description : set to 0xaa0
+// Description : set to 0xaa
// any other value enables the output with shift=0
#define ROSC_PHASE_PASSWD_RESET _u(0x00)
#define ROSC_PHASE_PASSWD_BITS _u(0x00000ff0)
@@ -260,7 +260,7 @@
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_BADWRITE
// Description : An invalid value has been written to CTRL_ENABLE or
-// CTRL_FREQ_RANGE or FRFEQA or FREQB or DORMANT
+// CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT
#define ROSC_STATUS_BADWRITE_RESET _u(0x0)
#define ROSC_STATUS_BADWRITE_BITS _u(0x01000000)
#define ROSC_STATUS_BADWRITE_MSB _u(24)
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/usb_device_dpram.h b/src/rp2040/hardware_regs/include/hardware/regs/usb_device_dpram.h
new file mode 100644
index 0000000..6422774
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/usb_device_dpram.h
@@ -0,0 +1,6807 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : USB_DEVICE_DPRAM
+// Version : 1
+// Bus type : ahbl
+// Description : DPRAM layout for USB device.
+// =============================================================================
+#ifndef HARDWARE_REGS_USB_DEVICE_DPRAM_DEFINED
+#define HARDWARE_REGS_USB_DEVICE_DPRAM_DEFINED
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_SETUP_PACKET_LOW
+// Description : Bytes 0-3 of the SETUP packet from the host.
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_OFFSET _u(0x00000000)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE
+// Description : None
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_BITS _u(0xffff0000)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_MSB _u(31)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_LSB _u(16)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST
+// Description : None
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_RESET _u(0x00)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_BITS _u(0x0000ff00)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_MSB _u(15)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_LSB _u(8)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE
+// Description : None
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_RESET _u(0x00)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_BITS _u(0x000000ff)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_MSB _u(7)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_LSB _u(0)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH
+// Description : Bytes 4-7 of the setup packet from the host.
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_OFFSET _u(0x00000004)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH
+// Description : None
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_BITS _u(0xffff0000)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_MSB _u(31)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_LSB _u(16)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX
+// Description : None
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_MSB _u(15)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_LSB _u(0)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP1_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_OFFSET _u(0x00000008)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP1_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_OFFSET _u(0x0000000c)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP2_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_OFFSET _u(0x00000010)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP2_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_OFFSET _u(0x00000014)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP3_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_OFFSET _u(0x00000018)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP3_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_OFFSET _u(0x0000001c)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP4_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_OFFSET _u(0x00000020)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP4_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_OFFSET _u(0x00000024)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP5_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_OFFSET _u(0x00000028)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP5_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_OFFSET _u(0x0000002c)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP6_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_OFFSET _u(0x00000030)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP6_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_OFFSET _u(0x00000034)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP7_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_OFFSET _u(0x00000038)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP7_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_OFFSET _u(0x0000003c)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP8_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_OFFSET _u(0x00000040)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP8_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_OFFSET _u(0x00000044)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP9_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_OFFSET _u(0x00000048)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP9_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_OFFSET _u(0x0000004c)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP10_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_OFFSET _u(0x00000050)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP10_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_OFFSET _u(0x00000054)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP11_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_OFFSET _u(0x00000058)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP11_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_OFFSET _u(0x0000005c)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP12_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_OFFSET _u(0x00000060)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP12_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_OFFSET _u(0x00000064)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP13_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_OFFSET _u(0x00000068)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP13_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_OFFSET _u(0x0000006c)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP14_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_OFFSET _u(0x00000070)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP14_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_OFFSET _u(0x00000074)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP15_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_OFFSET _u(0x00000078)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP15_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_OFFSET _u(0x0000007c)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_OFFSET _u(0x00000080)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_OFFSET _u(0x00000084)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_OFFSET _u(0x00000088)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_OFFSET _u(0x0000008c)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_OFFSET _u(0x00000090)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_OFFSET _u(0x00000094)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_OFFSET _u(0x00000098)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_OFFSET _u(0x0000009c)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_OFFSET _u(0x000000a0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_OFFSET _u(0x000000a4)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_OFFSET _u(0x000000a8)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_OFFSET _u(0x000000ac)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_OFFSET _u(0x000000b0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_OFFSET _u(0x000000b4)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_OFFSET _u(0x000000b8)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_OFFSET _u(0x000000bc)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_OFFSET _u(0x000000c0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_OFFSET _u(0x000000c4)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_OFFSET _u(0x000000c8)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_OFFSET _u(0x000000cc)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_OFFSET _u(0x000000d0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_OFFSET _u(0x000000d4)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS
+// ET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_OFFSET _u(0x000000d8)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_OFFSET _u(0x000000dc)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS
+// ET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_OFFSET _u(0x000000e0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_OFFSET _u(0x000000e4)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS
+// ET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_OFFSET _u(0x000000e8)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_OFFSET _u(0x000000ec)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS
+// ET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_OFFSET _u(0x000000f0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_OFFSET _u(0x000000f4)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS
+// ET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_OFFSET _u(0x000000f8)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_OFFSET _u(0x000000fc)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS
+// ET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+#endif // HARDWARE_REGS_USB_DEVICE_DPRAM_DEFINED
diff --git a/src/rp2040/hardware_regs/rp2040.svd b/src/rp2040/hardware_regs/rp2040.svd
index 9d44dd1..f600d47 100644
--- a/src/rp2040/hardware_regs/rp2040.svd
+++ b/src/rp2040/hardware_regs/rp2040.svd
@@ -24675,25 +24675,6 @@
<fields>
<field>
<access>read-only</access>
- <bitRange>[13:13]</bitRange>
- <description>See IC_RAW_INTR_STAT for a detailed description of R_MASTER_ON_HOLD bit.\n\n
- Reset value: 0x0</description>
- <enumeratedValues>
- <enumeratedValue>
- <description>R_MASTER_ON_HOLD interrupt is inactive</description>
- <name>INACTIVE</name>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <description>R_MASTER_ON_HOLD interrupt is active</description>
- <name>ACTIVE</name>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- <name>R_MASTER_ON_HOLD</name>
- </field>
- <field>
- <access>read-only</access>
<bitRange>[12:12]</bitRange>
<description>See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit.\n\n
Reset value: 0x0</description>
@@ -24949,25 +24930,6 @@
These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt.</description>
<fields>
<field>
- <access>read-only</access>
- <bitRange>[13:13]</bitRange>
- <description>This M_MASTER_ON_HOLD_read_only bit masks the R_MASTER_ON_HOLD interrupt in IC_INTR_STAT register.\n\n
- Reset value: 0x0</description>
- <enumeratedValues>
- <enumeratedValue>
- <description>MASTER_ON_HOLD interrupt is masked</description>
- <name>ENABLED</name>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <description>MASTER_ON_HOLD interrupt is unmasked</description>
- <name>DISABLED</name>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- <name>M_MASTER_ON_HOLD_READ_ONLY</name>
- </field>
- <field>
<access>read-write</access>
<bitRange>[12:12]</bitRange>
<description>This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.\n\n
@@ -25225,25 +25187,6 @@
<fields>
<field>
<access>read-only</access>
- <bitRange>[13:13]</bitRange>
- <description>Indicates whether master is holding the bus and TX FIFO is empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and IC_EMPTYFIFO_HOLD_MASTER_EN=1.\n\n
- Reset value: 0x0</description>
- <enumeratedValues>
- <enumeratedValue>
- <description>MASTER_ON_HOLD interrupt is inactive</description>
- <name>INACTIVE</name>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <description>MASTER_ON_HOLD interrupt is active</description>
- <name>ACTIVE</name>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- <name>MASTER_ON_HOLD</name>
- </field>
- <field>
- <access>read-only</access>
<bitRange>[12:12]</bitRange>
<description>Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1.\n\n
Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt.\n\n
@@ -25931,7 +25874,7 @@
The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW).\n\n
The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode.\n\n
Writes to this register succeed only when IC_ENABLE[0]=0.\n\n
- The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode one cycle in master mode, seven cycles in slave mode for the value to be implemented.\n\n
+ The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented.\n\n
The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles.</description>
<fields>
<field>
@@ -29321,7 +29264,7 @@
<description>set to 0xaa0 + div where\n
div = 0 divides by 32\n
div = 1-31 divides by div\n
- any other value sets div=0 and therefore divides by 32\n
+ any other value sets div=31\n
this register resets to div=16</description>
<enumeratedValues>
<enumeratedValue>
@@ -29342,7 +29285,7 @@
<field>
<access>read-write</access>
<bitRange>[11:4]</bitRange>
- <description>set to 0xaa0\n
+ <description>set to 0xaa\n
any other value enables the output with shift=0</description>
<name>PASSWD</name>
</field>
@@ -29385,7 +29328,7 @@
<field>
<access>read-write</access>
<bitRange>[24:24]</bitRange>
- <description>An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FRFEQA or FREQB or DORMANT</description>
+ <description>An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT</description>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<name>BADWRITE</name>
</field>
@@ -33633,6 +33576,5613 @@
<peripheral>
<addressBlock>
<offset>0</offset>
+ <size>0x0100</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <baseAddress>0x50100000</baseAddress>
+ <description>DPRAM layout for USB device.</description>
+ <name>USBCTRL_DPRAM</name>
+ <registers>
+ <register>
+ <addressOffset>0x0000</addressOffset>
+ <description>Bytes 0-3 of the SETUP packet from the host.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:16]</bitRange>
+ <name>WVALUE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:8]</bitRange>
+ <name>BREQUEST</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[7:0]</bitRange>
+ <name>BMREQUESTTYPE</name>
+ </field>
+ </fields>
+ <name>SETUP_PACKET_LOW</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0004</addressOffset>
+ <description>Bytes 4-7 of the setup packet from the host.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:16]</bitRange>
+ <name>WLENGTH</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <name>WINDEX</name>
+ </field>
+ </fields>
+ <name>SETUP_PACKET_HIGH</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0008</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP1_IN_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x000c</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP1_OUT_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0010</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP2_IN_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0014</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP2_OUT_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0018</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP3_IN_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x001c</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP3_OUT_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0020</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP4_IN_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0024</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP4_OUT_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0028</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP5_IN_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x002c</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP5_OUT_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0030</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP6_IN_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0034</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP6_OUT_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0038</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP7_IN_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x003c</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP7_OUT_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0040</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP8_IN_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0044</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP8_OUT_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0048</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP9_IN_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x004c</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP9_OUT_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0050</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP10_IN_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0054</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP10_OUT_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0058</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP11_IN_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x005c</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP11_OUT_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0060</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP12_IN_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0064</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP12_OUT_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0068</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP13_IN_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x006c</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP13_OUT_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0070</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP14_IN_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0074</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP14_OUT_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0078</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP15_IN_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x007c</addressOffset>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+ <name>ENABLE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>This endpoint is double buffered.</description>
+ <name>DOUBLE_BUFFERED</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>Trigger an interrupt each time a buffer is done.</description>
+ <name>INTERRUPT_PER_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:28]</bitRange>
+ <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+ <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Control</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Isochronous</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Bulk</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Interrupt</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>ENDPOINT_TYPE</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[17:17]</bitRange>
+ <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[16:16]</bitRange>
+ <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+ <name>INTERRUPT_ON_NAK</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:0]</bitRange>
+ <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+ <name>BUFFER_ADDRESS</name>
+ </field>
+ </fields>
+ <name>EP15_OUT_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0080</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP0_IN_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0084</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP0_OUT_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0088</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP1_IN_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x008c</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP1_OUT_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0090</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP2_IN_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0094</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP2_OUT_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x0098</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP3_IN_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x009c</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP3_OUT_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x00a0</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP4_IN_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x00a4</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP4_OUT_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x00a8</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP5_IN_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x00ac</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP5_OUT_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x00b0</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP6_IN_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x00b4</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP6_OUT_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x00b8</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP7_IN_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x00bc</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP7_OUT_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x00c0</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP8_IN_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x00c4</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP8_OUT_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x00c8</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP9_IN_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x00cc</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP9_OUT_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x00d0</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP10_IN_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x00d4</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP10_OUT_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x00d8</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP11_IN_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x00dc</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP11_OUT_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x00e0</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP12_IN_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x00e4</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP12_OUT_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x00e8</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP13_IN_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x00ec</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP13_OUT_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x00f0</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP14_IN_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x00f4</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP14_OUT_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x00f8</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP15_IN_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ <register>
+ <addressOffset>0x00fc</addressOffset>
+ <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+ Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+ <fields>
+ <field>
+ <access>read-write</access>
+ <bitRange>[31:31]</bitRange>
+ <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[30:30]</bitRange>
+ <description>Buffer 1 is the last buffer of the transfer.</description>
+ <name>LAST_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[29:29]</bitRange>
+ <description>The data pid of buffer 1.</description>
+ <name>PID_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[28:27]</bitRange>
+ <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+ For a non Isochronous endpoint the offset is always 64 bytes.</description>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>128</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>256</name>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>512</name>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>1024</name>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[26:26]</bitRange>
+ <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[25:16]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_1</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[15:15]</bitRange>
+ <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+ <name>FULL_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[14:14]</bitRange>
+ <description>Buffer 0 is the last buffer of the transfer.</description>
+ <name>LAST_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[13:13]</bitRange>
+ <description>The data pid of buffer 0.</description>
+ <name>PID_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[12:12]</bitRange>
+ <description>Reset the buffer selector to buffer 0.</description>
+ <name>RESET</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[11:11]</bitRange>
+ <description>Reply with a stall (valid for both buffers).</description>
+ <name>STALL</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[10:10]</bitRange>
+ <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+ <name>AVAILABLE_0</name>
+ </field>
+ <field>
+ <access>read-write</access>
+ <bitRange>[9:0]</bitRange>
+ <description>The length of the data in buffer 1.</description>
+ <name>LENGTH_0</name>
+ </field>
+ </fields>
+ <name>EP15_OUT_BUFFER_CONTROL</name>
+ <resetValue>0x00000000</resetValue>
+ </register>
+ </registers>
+ <size>32</size>
+ <version>1</version>
+ </peripheral>
+ <peripheral>
+ <addressBlock>
+ <offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/i2c.h b/src/rp2040/hardware_structs/include/hardware/structs/i2c.h
index 4bc501f..1a58c50 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/i2c.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/i2c.h
@@ -62,80 +62,73 @@
// references to these in I2C register header; these are *fixed* values,
// set at hardware design time):
-// SLAVE_INTERFACE_TYPE .............. 0
-// REG_TIMEOUT_WIDTH ................. 4
-// REG_TIMEOUT_VALUE ................. 8
// IC_ULTRA_FAST_MODE ................ 0x0
// IC_UFM_TBUF_CNT_DEFAULT ........... 0x8
+// IC_UFM_SCL_LOW_COUNT .............. 0x0008
// IC_UFM_SCL_HIGH_COUNT ............. 0x0006
// IC_TX_TL .......................... 0x0
-// IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0
-// IC_SS_SCL_LOW_COUNT ............... 0x01d6
+// IC_TX_CMD_BLOCK ................... 0x1
// IC_HAS_DMA ........................ 0x1
-// IC_RX_FULL_GEN_NACK ............... 0x0
-// IC_CLOCK_PERIOD ................... 100
-// IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1
+// IC_HAS_ASYNC_FIFO ................. 0x0
// IC_SMBUS_ARP ...................... 0x0
// IC_FIRST_DATA_BYTE_STATUS ......... 0x1
// IC_INTR_IO ........................ 0x1
// IC_MASTER_MODE .................... 0x1
-// IC_DEFAULT_ACK_GENERAL_CALL ....... 0x0
+// IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1
// IC_INTR_POL ....................... 0x1
// IC_OPTIONAL_SAR ................... 0x0
// IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055
// IC_DEFAULT_SLAVE_ADDR ............. 0x055
// IC_DEFAULT_HS_SPKLEN .............. 0x1
-// IC_FS_SCL_HIGH_COUNT .............. 0x003c
-// IC_HS_SCL_LOW_COUNT ............... 0x0010
+// IC_FS_SCL_HIGH_COUNT .............. 0x0006
+// IC_HS_SCL_LOW_COUNT ............... 0x0008
// IC_DEVICE_ID_VALUE ................ 0x0
// IC_10BITADDR_MASTER ............... 0x0
// IC_CLK_FREQ_OPTIMIZATION .......... 0x0
-// IC_DEFAULT_FS_SPKLEN .............. 0xf
-// IC_ADD_ENCODED_PARAMS ............. 0x1
+// IC_DEFAULT_FS_SPKLEN .............. 0x7
+// IC_ADD_ENCODED_PARAMS ............. 0x0
// IC_DEFAULT_SDA_HOLD ............... 0x000001
// IC_DEFAULT_SDA_SETUP .............. 0x64
// IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0
-// SLVERR_RESP_EN .................... 0
+// IC_CLOCK_PERIOD ................... 100
+// IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1
// IC_RESTART_EN ..................... 0x1
-// IC_TX_CMD_BLOCK ................... 0x1
-// HC_REG_TIMEOUT_VALUE .............. 0
-// IC_BUS_CLEAR_FEATURE .............. 0x1
+// IC_TX_CMD_BLOCK_DEFAULT ........... 0x0
+// IC_BUS_CLEAR_FEATURE .............. 0x0
// IC_CAP_LOADING .................... 100
-// IC_HAS_ASYNC_FIFO ................. 0x0
-// IC_FS_SCL_LOW_COUNT ............... 0x0082
+// IC_FS_SCL_LOW_COUNT ............... 0x000d
// APB_DATA_WIDTH .................... 32
// IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
// IC_SLV_DATA_NACK_ONLY ............. 0x1
// IC_10BITADDR_SLAVE ................ 0x0
-// IC_TX_BUFFER_DEPTH ................ 32
-// IC_DEFAULT_UFM_SPKLEN ............. 0x1
// IC_CLK_TYPE ....................... 0x0
-// IC_TX_CMD_BLOCK_DEFAULT ........... 0x0
// IC_SMBUS_UDID_MSB ................. 0x0
// IC_SMBUS_SUSPEND_ALERT ............ 0x0
// IC_HS_SCL_HIGH_COUNT .............. 0x0006
// IC_SLV_RESTART_DET_EN ............. 0x1
-// IC_SMBUS .......................... 0x1
-// IC_STAT_FOR_CLK_STRETCH ........... 0x1
-// IC_MAX_SPEED_MODE ................. 0x2
+// IC_SMBUS .......................... 0x0
// IC_OPTIONAL_SAR_DEFAULT ........... 0x0
// IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0
-// IC_USE_COUNTS ..................... 0x1
-// IC_RX_BUFFER_DEPTH ................ 32
+// IC_USE_COUNTS ..................... 0x0
+// IC_RX_BUFFER_DEPTH ................ 16
// IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
// IC_RX_FULL_HLD_BUS_EN ............. 0x1
// IC_SLAVE_DISABLE .................. 0x1
// IC_RX_TL .......................... 0x0
// IC_DEVICE_ID ...................... 0x0
// IC_HC_COUNT_VALUES ................ 0x0
-// I2C_DYNAMIC_TAR_UPDATE ............ 1
+// I2C_DYNAMIC_TAR_UPDATE ............ 0
// IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff
// IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff
// IC_HS_MASTER_CODE ................. 0x1
// IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff
-// IC_UFM_SCL_LOW_COUNT .............. 0x0008
-// IC_SMBUS_UDID_HC .................. 0x1
// IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff
-// IC_SS_SCL_HIGH_COUNT .............. 0x0190
+// IC_SS_SCL_HIGH_COUNT .............. 0x0028
+// IC_SS_SCL_LOW_COUNT ............... 0x002f
+// IC_MAX_SPEED_MODE ................. 0x2
+// IC_STAT_FOR_CLK_STRETCH ........... 0x0
+// IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0
+// IC_DEFAULT_UFM_SPKLEN ............. 0x1
+// IC_TX_BUFFER_DEPTH ................ 16
#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/sio.h b/src/rp2040/hardware_structs/include/hardware/structs/sio.h
index 400083f..bc277af 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/sio.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/sio.h
@@ -17,7 +17,7 @@
io_ro_32 gpio_hi_in;
uint32_t _pad;
- io_wo_32 gpio_out;
+ io_rw_32 gpio_out;
io_wo_32 gpio_set;
io_wo_32 gpio_clr;
io_wo_32 gpio_togl;
@@ -27,7 +27,7 @@
io_wo_32 gpio_oe_clr;
io_wo_32 gpio_oe_togl;
- io_wo_32 gpio_hi_out;
+ io_rw_32 gpio_hi_out;
io_wo_32 gpio_hi_set;
io_wo_32 gpio_hi_clr;
io_wo_32 gpio_hi_togl;
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/usb.h b/src/rp2040/hardware_structs/include/hardware/structs/usb.h
index 5c3c453..0254e61 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/usb.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/usb.h
@@ -79,6 +79,7 @@
} usb_device_dpram_t;
static_assert(sizeof(usb_device_dpram_t) == USB_DPRAM_MAX, "");
+static_assert(offsetof(usb_device_dpram_t, epx_data) == 0x180, "");
typedef struct {
// 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses
@@ -108,6 +109,7 @@
} usb_host_dpram_t;
static_assert(sizeof(usb_host_dpram_t) == USB_DPRAM_MAX, "");
+static_assert(offsetof(usb_host_dpram_t, epx_data) == 0x180, "");
typedef struct {
io_rw_32 dev_addr_ctrl;
diff --git a/src/rp2_common/CMakeLists.txt b/src/rp2_common/CMakeLists.txt
index 5cd20a7..0277c8d 100644
--- a/src/rp2_common/CMakeLists.txt
+++ b/src/rp2_common/CMakeLists.txt
@@ -10,6 +10,7 @@
pico_add_subdirectory(hardware_clocks)
pico_add_subdirectory(hardware_dma)
pico_add_subdirectory(hardware_divider)
+pico_add_subdirectory(hardware_exception)
pico_add_subdirectory(hardware_flash)
pico_add_subdirectory(hardware_gpio)
pico_add_subdirectory(hardware_i2c)
@@ -53,6 +54,7 @@
pico_add_subdirectory(pico_stdio_semihosting)
pico_add_subdirectory(pico_stdio_uart)
+ pico_add_subdirectory(cmsis)
pico_add_subdirectory(tinyusb)
pico_add_subdirectory(pico_stdio_usb)
@@ -70,3 +72,5 @@
set(CMAKE_EXECUTABLE_SUFFIX "${CMAKE_EXECUTABLE_SUFFIX}" PARENT_SCOPE)
pico_add_doxygen(${CMAKE_CURRENT_LIST_DIR})
+
+pico_promote_common_scope_vars()
\ No newline at end of file
diff --git a/src/rp2_common/boot_stage2/boot2_at25sf128a.S b/src/rp2_common/boot_stage2/boot2_at25sf128a.S
new file mode 100644
index 0000000..be232ff
--- /dev/null
+++ b/src/rp2_common/boot_stage2/boot2_at25sf128a.S
@@ -0,0 +1,285 @@
+// ----------------------------------------------------------------------------
+// Second stage boot code
+// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd.
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// Device: Adesto AT25SF128A
+// Based on W25Q080 code: main difference is the QE bit is being set
+// via command 0x31
+//
+// Description: Configures AT25SF128A to run in Quad I/O continuous read XIP mode
+//
+// Details: * Check status register 2 to determine if QSPI mode is enabled,
+// and perform an SR2 programming cycle if necessary.
+// * Use SSI to perform a dummy 0xEB read command, with the mode
+// continuation bits set, so that the flash will not require
+// 0xEB instruction prefix on subsequent reads.
+// * Configure SSI to write address, mode bits, but no instruction.
+// SSI + flash are now jointly in a state where continuous reads
+// can take place.
+// * Jump to exit pointer passed in via lr. Bootrom passes null,
+// in which case this code uses a default 256 byte flash offset
+//
+// Building: * This code must be position-independent, and use stack only
+// * The code will be padded to a size of 256 bytes, including a
+// 4-byte checksum. Therefore code size cannot exceed 252 bytes.
+// ----------------------------------------------------------------------------
+
+#include "pico/asm_helper.S"
+#include "hardware/regs/addressmap.h"
+#include "hardware/regs/ssi.h"
+#include "hardware/regs/pads_qspi.h"
+
+// ----------------------------------------------------------------------------
+// Config section
+// ----------------------------------------------------------------------------
+// It should be possible to support most flash devices by modifying this section
+
+// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV.
+// This must be a positive, even integer.
+// The bootrom is very conservative with SPI frequency, but here we should be
+// as aggressive as possible.
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 4
+#endif
+#if PICO_FLASH_SPI_CLKDIV & 1
+#error PICO_FLASH_SPI_CLKDIV must be even
+#endif
+
+// Define interface width: single/dual/quad IO
+#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD
+
+// For W25Q080 this is the "Read data fast quad IO" instruction:
+#define CMD_READ 0xeb
+
+// "Mode bits" are 8 special bits sent immediately after
+// the address bits in a "Read Data Fast Quad I/O" command sequence.
+// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the
+// next read does not require the 0xeb instruction prefix.
+#define MODE_CONTINUOUS_READ 0x20
+
+// The number of address + mode bits, divided by 4 (always 4, not function of
+// interface width).
+#define ADDR_L 8
+
+// How many clocks of Hi-Z following the mode bits. For W25Q080, 4 dummy cycles
+// are required.
+#define WAIT_CYCLES 4
+
+// If defined, we will read status reg, compare to SREG_DATA, and overwrite
+// with our value if the SR doesn't match.
+// We do a two-byte write to SR1 (01h cmd) rather than a one-byte write to
+// SR2 (31h cmd) as the latter command isn't supported by WX25Q080.
+// This isn't great because it will remove block protections.
+// A better solution is to use a volatile SR write if your device supports it.
+#define PROGRAM_STATUS_REG
+
+#define CMD_WRITE_ENABLE 0x06
+#define CMD_READ_STATUS 0x05
+#define CMD_READ_STATUS2 0x35
+#define CMD_WRITE_STATUS 0x01
+#define CMD_WRITE_STATUS2 0x31
+#define SREG_DATA 0x02 // Enable quad-SPI mode
+
+// ----------------------------------------------------------------------------
+// Start of 2nd Stage Boot Code
+// ----------------------------------------------------------------------------
+
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+.section .text
+
+// The exit point is passed in lr. If entered from bootrom, this will be the
+// flash address immediately following this second stage (0x10000100).
+// Otherwise it will be a return address -- second stage being called as a
+// function by user code, after copying out of XIP region. r3 holds SSI base,
+// r0...2 used as temporaries. Other GPRs not used.
+.global _stage2_boot
+.type _stage2_boot,%function
+.thumb_func
+_stage2_boot:
+ push {lr}
+
+ // Set pad configuration:
+ // - SCLK 8mA drive, no slew limiting
+ // - SDx disable input Schmitt to reduce delay
+
+ ldr r3, =PADS_QSPI_BASE
+ movs r0, #(2 << PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB | PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS)
+ str r0, [r3, #PADS_QSPI_GPIO_QSPI_SCLK_OFFSET]
+ ldr r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]
+ movs r1, #PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS
+ bics r0, r1
+ str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]
+ str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD1_OFFSET]
+ str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD2_OFFSET]
+ str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD3_OFFSET]
+
+ ldr r3, =XIP_SSI_BASE
+
+ // Disable SSI to allow further config
+ movs r1, #0
+ str r1, [r3, #SSI_SSIENR_OFFSET]
+
+ // Set baud rate
+ movs r1, #PICO_FLASH_SPI_CLKDIV
+ str r1, [r3, #SSI_BAUDR_OFFSET]
+
+ // Set 1-cycle sample delay. If PICO_FLASH_SPI_CLKDIV == 2 then this means,
+ // if the flash launches data on SCLK posedge, we capture it at the time that
+ // the next SCLK posedge is launched. This is shortly before that posedge
+ // arrives at the flash, so data hold time should be ok. For
+ // PICO_FLASH_SPI_CLKDIV > 2 this pretty much has no effect.
+
+ movs r1, #1
+ movs r2, #SSI_RX_SAMPLE_DLY_OFFSET // == 0xf0 so need 8 bits of offset significance
+ str r1, [r3, r2]
+
+
+// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode
+// (i.e. turn WPn and HOLDn into IO2/IO3)
+#ifdef PROGRAM_STATUS_REG
+program_sregs:
+#define CTRL0_SPI_TXRX \
+ (7 << SSI_CTRLR0_DFS_32_LSB) | /* 8 bits per data frame */ \
+ (SSI_CTRLR0_TMOD_VALUE_TX_AND_RX << SSI_CTRLR0_TMOD_LSB)
+
+ ldr r1, =(CTRL0_SPI_TXRX)
+ str r1, [r3, #SSI_CTRLR0_OFFSET]
+
+ // Enable SSI and select slave 0
+ movs r1, #1
+ str r1, [r3, #SSI_SSIENR_OFFSET]
+
+ // Check whether SR needs updating
+ movs r0, #CMD_READ_STATUS2
+ bl read_flash_sreg
+ movs r2, #SREG_DATA
+ cmp r0, r2
+ beq skip_sreg_programming
+
+ // Send write enable command
+ movs r1, #CMD_WRITE_ENABLE
+ str r1, [r3, #SSI_DR0_OFFSET]
+
+ // Poll for completion and discard RX
+ bl wait_ssi_ready
+ ldr r1, [r3, #SSI_DR0_OFFSET]
+
+ // Send status write command followed by data bytes
+ movs r1, #CMD_WRITE_STATUS2
+ str r1, [r3, #SSI_DR0_OFFSET]
+ str r2, [r3, #SSI_DR0_OFFSET]
+
+ bl wait_ssi_ready
+ ldr r1, [r3, #SSI_DR0_OFFSET]
+ ldr r1, [r3, #SSI_DR0_OFFSET]
+ ldr r1, [r3, #SSI_DR0_OFFSET]
+
+ // Poll status register for write completion
+1:
+ movs r0, #CMD_READ_STATUS
+ bl read_flash_sreg
+ movs r1, #1
+ tst r0, r1
+ bne 1b
+
+skip_sreg_programming:
+
+ // Disable SSI again so that it can be reconfigured
+ movs r1, #0
+ str r1, [r3, #SSI_SSIENR_OFFSET]
+#endif
+
+// Currently the flash expects an 8 bit serial command prefix on every
+// transfer, which is a waste of cycles. Perform a dummy Fast Read Quad I/O
+// command, with mode bits set such that the flash will not expect a serial
+// command prefix on *subsequent* transfers. We don't care about the results
+// of the read, the important part is the mode bits.
+
+dummy_read:
+#define CTRLR0_ENTER_XIP \
+ (FRAME_FORMAT /* Quad I/O mode */ \
+ << SSI_CTRLR0_SPI_FRF_LSB) | \
+ (31 << SSI_CTRLR0_DFS_32_LSB) | /* 32 data bits */ \
+ (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ /* Send INST/ADDR, Receive Data */ \
+ << SSI_CTRLR0_TMOD_LSB)
+
+ ldr r1, =(CTRLR0_ENTER_XIP)
+ str r1, [r3, #SSI_CTRLR0_OFFSET]
+
+ movs r1, #0x0 // NDF=0 (single 32b read)
+ str r1, [r3, #SSI_CTRLR1_OFFSET]
+
+#define SPI_CTRLR0_ENTER_XIP \
+ (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Address + mode bits */ \
+ (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \
+ (SSI_SPI_CTRLR0_INST_L_VALUE_8B \
+ << SSI_SPI_CTRLR0_INST_L_LSB) | /* 8-bit instruction */ \
+ (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A /* Send Command in serial mode then address in Quad I/O mode */ \
+ << SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
+
+ ldr r1, =(SPI_CTRLR0_ENTER_XIP)
+ ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
+ str r1, [r0]
+
+ movs r1, #1 // Re-enable SSI
+ str r1, [r3, #SSI_SSIENR_OFFSET]
+
+ movs r1, #CMD_READ
+ str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
+ movs r1, #MODE_CONTINUOUS_READ // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010
+ str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction
+
+ // Poll for completion
+ bl wait_ssi_ready
+
+// The flash is in a state where we can blast addresses in parallel, and get
+// parallel data back. Now configure the SSI to translate XIP bus accesses
+// into QSPI transfers of this form.
+
+ movs r1, #0
+ str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config
+
+// Note that the INST_L field is used to select what XIP data gets pushed into
+// the TX FIFO:
+// INST_L_0_BITS {ADDR[23:0],XIP_CMD[7:0]} Load "mode bits" into XIP_CMD
+// Anything else {XIP_CMD[7:0],ADDR[23:0]} Load SPI command into XIP_CMD
+configure_ssi:
+#define SPI_CTRLR0_XIP \
+ (MODE_CONTINUOUS_READ /* Mode bits to keep flash in continuous read mode */ \
+ << SSI_SPI_CTRLR0_XIP_CMD_LSB) | \
+ (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Total number of address + mode bits */ \
+ (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \
+ (SSI_SPI_CTRLR0_INST_L_VALUE_NONE /* Do not send a command, instead send XIP_CMD as mode bits after address */ \
+ << SSI_SPI_CTRLR0_INST_L_LSB) | \
+ (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A /* Send Address in Quad I/O mode (and Command but that is zero bits long) */ \
+ << SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
+
+ ldr r1, =(SPI_CTRLR0_XIP)
+ ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
+ str r1, [r0]
+
+ movs r1, #1
+ str r1, [r3, #SSI_SSIENR_OFFSET] // Re-enable SSI
+
+// Bus accesses to the XIP window will now be transparently serviced by the
+// external flash on cache miss. We are ready to run code from flash.
+
+// Pull in standard exit routine
+#include "boot2_helpers/exit_from_boot2.S"
+
+// Common functions
+#include "boot2_helpers/wait_ssi_ready.S"
+#ifdef PROGRAM_STATUS_REG
+#include "boot2_helpers/read_flash_sreg.S"
+#endif
+
+.global literals
+literals:
+.ltorg
+
+.end
diff --git a/src/rp2_common/boot_stage2/include/boot_stage2/config.h b/src/rp2_common/boot_stage2/include/boot_stage2/config.h
index a8179b9..5e57f95 100644
--- a/src/rp2_common/boot_stage2/include/boot_stage2/config.h
+++ b/src/rp2_common/boot_stage2/include/boot_stage2/config.h
@@ -44,6 +44,16 @@
#endif
#define _BOOT_STAGE2_SELECTED
#endif
+// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_AT25SF128A, Select boot2_at25sf128a as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=0, group=boot_stage2
+#ifndef PICO_BOOT_STAGE2_CHOOSE_AT25SF128A
+ #define PICO_BOOT_STAGE2_CHOOSE_AT25SF128A 0
+#elif PICO_BOOT_STAGE2_CHOOSE_AT25SF128A
+ #ifdef _BOOT_STAGE2_SELECTED
+ #error multiple boot stage 2 options chosen
+ #endif
+ #define _BOOT_STAGE2_SELECTED
+#endif
+
// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H, Select boot2_generic_03h as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=1, group=boot_stage2
#if defined(PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H) && PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H
#ifdef _BOOT_STAGE2_SELECTED
@@ -65,6 +75,8 @@
#define _BOOT_STAGE2 boot2_w25q080
#elif PICO_BOOT_STAGE2_CHOOSE_W25X10CL
#define _BOOT_STAGE2 boot2_w25x10cl
+ #elif PICO_BOOT_STAGE2_CHOOSE_AT25SF128A
+ #define _BOOT_STAGE2 boot2_at25sf128a
#elif !defined(PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H) || PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H
#undef PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H
#define PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H 1
diff --git a/src/rp2_common/cmsis/CMakeLists.txt b/src/rp2_common/cmsis/CMakeLists.txt
new file mode 100644
index 0000000..0d663e1
--- /dev/null
+++ b/src/rp2_common/cmsis/CMakeLists.txt
@@ -0,0 +1,66 @@
+# Deferring this config until we decide how to include other CMSIS libraries... it is likely that we always want to use the stub version of the core
+# at least if the vendor/device is RaspberryPi/RP2040...
+
+## PICO_CMAKE_CONFIG: PICO_CMSIS_PATH, directory to locate CMSIS installation, default="included stub CORE only impl", group=build
+#if (DEFINED PICO_CMSIS_PATH)
+# set(PICO_CMSIS_PATH "${PICO_CMSIS_PATH}" CACHE PATH "Path to the CMSIS tree to use with Raspberry Pi Pico SDK")
+# message("Using specified PICO_CMSIS_PATH for CMSIS ('${PICO_CMSIS_PATH}')")
+#elseif (DEFINED ENV{PICO_CMSIS_PATH})
+# set(PICO_CMSIS_PATH $ENV{PICO_CMSIS_PATH})
+# message("Using PICO_CMSIS_PATH from environment for CMSIS ('${PICO_CMSIS_PATH}')")
+#endif()
+#
+## PICO_CMAKE_CONFIG: PICO_CMSIS_VENDOR, vendor name for CMSIS, default="RaspberryPi", group=build
+#if (DEFINED PICO_CMSIS_VENDOR)
+# set(PICO_CMSIS_VENDOR "${PICO_CMSIS_VENDOR}" CACHE STRING "CMSIS vendor name to use")
+# message("Using specified PICO_CMSIS_VENDOR for CMSIS ('${PICO_CMSIS_VENDOR}')")
+#elseif (DEFINED ENV{PICO_CMSIS_VENDOR})
+# set(PICO_CMSIS_VENDOR $ENV{PICO_CMSIS_VENDOR})
+# message("Using PICO_CMSIS_VENDOR from environment for CMSIS ('${PICO_CMSIS_VENDOR}')")
+#else()
+# set(PICO_CMSIS_VENDOR RaspberryPi)
+#endif()
+#
+## PICO_CMAKE_CONFIG: PICO_CMSIS_DEVICE, device name for CMSIS, default="RP2040", group=build
+#if (DEFINED PICO_CMSIS_DEVICE)
+# set(PICO_CMSIS_DEVICE "${PICO_CMSIS_DEVICE}" CACHE STRING "CMSIS device name to use")
+# message("Using specified PICO_CMSIS_DEVICE for CMSIS ('${PICO_CMSIS_DEVICE}')")
+#elseif (DEFINED ENV{PICO_CMSIS_DEVICE})
+# set(PICO_CMSIS_DEVICE $ENV{PICO_CMSIS_DEVICE})
+# message("Using PICO_CMSIS_DEVICE from environment for CMSIS ('${PICO_CMSIS_DEVICE}')")
+#else()
+# set(PICO_CMSIS_DEVICE RP2040)
+#endif()
+#
+#if (PICO_CMSIS_PATH AND EXISTS ${PICO_CMSIS_PATH}/CMSIS/Core/${PICO_CMSIS_VENDOR}/${PICO_CMSIS_DEVICE})
+# message("CMSIS Core found for path ${PICO_CMSIS_PATH}, vendor ${PICO_CMSIS_VENDOR}, device ${PICO_CMSIS_DEVICE}")
+# set(PICO_CMSIS_CORE_PATH ${PICO_CMSIS_PATH}/CMSIS/Core)
+#elseif (PICO_CMSIS_VENDOR STREQUAL "RaspberryPi" AND PICO_CMSIS_DEVICE STREQUAL "RP2040")
+# set(PICO_CMSIS_CORE_PATH ${CMAKE_CURRENT_LIST_DIR}/stub)
+#elseif (PICO_CMSIS_PATH)
+# message(WARNING "CMSIS core not found in ${PICO_CMSIS_PATH} for vendor ${PICO_CMSIS_VENDOR}, device ${PICO_CMSIS_DEVICE}")
+# set(PICO_CMSIS_CORE_PATH)
+#else()
+# message(WARNING "Non-standard vendor ${PICO_CMSIS_VENDOR} amd device ${PICO_CMSIS_DEVICE} specified, but PICO_CMSIS_PATH was not set")
+#endif()
+
+# ... using these 3 lines instead
+set(PICO_CMSIS_CORE_PATH ${CMAKE_CURRENT_LIST_DIR}/stub)
+set(PICO_CMSIS_VENDOR RaspberryPi)
+set(PICO_CMSIS_DEVICE RP2040)
+
+if (PICO_CMSIS_CORE_PATH)
+ pico_add_impl_library(cmsis_core)
+ target_sources(cmsis_core INTERFACE
+ ${PICO_CMSIS_CORE_PATH}/CMSIS/Device/${PICO_CMSIS_VENDOR}/${PICO_CMSIS_DEVICE}/Source/system_${PICO_CMSIS_DEVICE}.c
+ )
+ target_include_directories(cmsis_core INTERFACE
+ ${PICO_CMSIS_CORE_PATH}/CMSIS/Core/Include
+ ${PICO_CMSIS_CORE_PATH}/CMSIS/Device/${PICO_CMSIS_VENDOR}/${PICO_CMSIS_DEVICE}/Include
+ )
+ target_link_libraries(cmsis_core INTERFACE hardware_clocks pico_platform)
+
+ list(APPEND PICO_RP2040_CONFIG_HEADER_FILES ${CMAKE_CURRENT_LIST_DIR}/include/cmsis/rename_exceptions.h)
+ pico_promote_common_scope_vars()
+endif()
+
diff --git a/src/rp2_common/cmsis/include/cmsis/rename_exceptions.h b/src/rp2_common/cmsis/include/cmsis/rename_exceptions.h
new file mode 100644
index 0000000..a523d27
--- /dev/null
+++ b/src/rp2_common/cmsis/include/cmsis/rename_exceptions.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _CMSIS_RENAME_EXCEPTIONS_H
+#define _CMSIS_RENAME_EXCEPTIONS_H
+
+#if LIB_CMSIS_CORE
+// PICO_CONFIG: PICO_CMSIS_RENAME_EXCEPTIONS, Whether to rename SDK exceptions such as isr_nmi to their CMSIS equivalent i.e. NMI_Handler, type=bool, default=1, group=cmsis_core
+
+// Note that since this header is included at the config stage, if you wish to override this you should do so via build compiler define
+#ifndef PICO_CMSIS_RENAME_EXCEPTIONS
+#define PICO_CMSIS_RENAME_EXCEPTIONS 1
+#endif
+
+#if PICO_CMSIS_RENAME_EXCEPTIONS
+#define isr_nmi NMI_Handler
+#define isr_hardfault HardFault_Handler
+#define isr_svcall SVC_Handler
+#define isr_pendsv PendSV_Handler
+#define isr_systick SysTick_Handler
+#define isr_irq0 TIMER_IRQ_0_Handler
+#define isr_irq1 TIMER_IRQ_1_Handler
+#define isr_irq2 TIMER_IRQ_2_Handler
+#define isr_irq3 TIMER_IRQ_3_Handler
+#define isr_irq4 PWM_IRQ_WRAP_Handler
+#define isr_irq5 USBCTRL_IRQ_Handler
+#define isr_irq6 XIP_IRQ_Handler
+#define isr_irq7 PIO0_IRQ_0_Handler
+#define isr_irq8 PIO0_IRQ_1_Handler
+#define isr_irq9 PIO1_IRQ_0_Handler
+#define isr_irq10 PIO1_IRQ_1_Handler
+#define isr_irq11 DMA_IRQ_0_Handler
+#define isr_irq12 DMA_IRQ_1_Handler
+#define isr_irq13 IO_IRQ_BANK0_Handler
+#define isr_irq14 IO_IRQ_QSPI_Handler
+#define isr_irq15 SIO_IRQ_PROC0_Handler
+#define isr_irq16 SIO_IRQ_PROC1_Handler
+#define isr_irq17 CLOCKS_IRQ_Handler
+#define isr_irq18 SPI0_IRQ_Handler
+#define isr_irq19 SPI1_IRQ_Handler
+#define isr_irq20 UART0_IRQ_Handler
+#define isr_irq21 UART1_IRQ_Handler
+#define isr_irq22 ADC_IRQ_FIFO_Handler
+#define isr_irq23 I2C0_IRQ_Handler
+#define isr_irq24 I2C1_IRQ_Handler
+#define isr_irq25 RTC_IRQ_Handler
+#endif
+
+#endif
+#endif /* _CMSIS_RENAME_EXCEPTIONS_H */
diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armcc.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armcc.h
new file mode 100644
index 0000000..237ff6e
--- /dev/null
+++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armcc.h
@@ -0,0 +1,885 @@
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version V5.2.1
+ * @date 26. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+ #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
+ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
+ #define __ARM_ARCH_6M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
+ #define __ARM_ARCH_7M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+ #define __ARM_ARCH_7EM__ 1
+#endif
+
+ /* __ARM_ARCH_8M_BASE__ not applicable */
+ /* __ARM_ARCH_8M_MAIN__ not applicable */
+ /* __ARM_ARCH_8_1M_MAIN__ not applicable */
+
+/* CMSIS compiler control DSP macros */
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __ARM_FEATURE_DSP 1
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE static __forceinline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __declspec(noreturn)
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT __packed struct
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION __packed union
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __memory_changed()
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+ return result;
+}
+#endif
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXB(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXH(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXW(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
+
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang.h
new file mode 100644
index 0000000..90de9db
--- /dev/null
+++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang.h
@@ -0,0 +1,1467 @@
+/**************************************************************************//**
+ * @file cmsis_armclang.h
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V5.3.1
+ * @date 26. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF)
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+#define __SADD8 __builtin_arm_sadd8
+#define __QADD8 __builtin_arm_qadd8
+#define __SHADD8 __builtin_arm_shadd8
+#define __UADD8 __builtin_arm_uadd8
+#define __UQADD8 __builtin_arm_uqadd8
+#define __UHADD8 __builtin_arm_uhadd8
+#define __SSUB8 __builtin_arm_ssub8
+#define __QSUB8 __builtin_arm_qsub8
+#define __SHSUB8 __builtin_arm_shsub8
+#define __USUB8 __builtin_arm_usub8
+#define __UQSUB8 __builtin_arm_uqsub8
+#define __UHSUB8 __builtin_arm_uhsub8
+#define __SADD16 __builtin_arm_sadd16
+#define __QADD16 __builtin_arm_qadd16
+#define __SHADD16 __builtin_arm_shadd16
+#define __UADD16 __builtin_arm_uadd16
+#define __UQADD16 __builtin_arm_uqadd16
+#define __UHADD16 __builtin_arm_uhadd16
+#define __SSUB16 __builtin_arm_ssub16
+#define __QSUB16 __builtin_arm_qsub16
+#define __SHSUB16 __builtin_arm_shsub16
+#define __USUB16 __builtin_arm_usub16
+#define __UQSUB16 __builtin_arm_uqsub16
+#define __UHSUB16 __builtin_arm_uhsub16
+#define __SASX __builtin_arm_sasx
+#define __QASX __builtin_arm_qasx
+#define __SHASX __builtin_arm_shasx
+#define __UASX __builtin_arm_uasx
+#define __UQASX __builtin_arm_uqasx
+#define __UHASX __builtin_arm_uhasx
+#define __SSAX __builtin_arm_ssax
+#define __QSAX __builtin_arm_qsax
+#define __SHSAX __builtin_arm_shsax
+#define __USAX __builtin_arm_usax
+#define __UQSAX __builtin_arm_uqsax
+#define __UHSAX __builtin_arm_uhsax
+#define __USAD8 __builtin_arm_usad8
+#define __USADA8 __builtin_arm_usada8
+#define __SSAT16 __builtin_arm_ssat16
+#define __USAT16 __builtin_arm_usat16
+#define __UXTB16 __builtin_arm_uxtb16
+#define __UXTAB16 __builtin_arm_uxtab16
+#define __SXTB16 __builtin_arm_sxtb16
+#define __SXTAB16 __builtin_arm_sxtab16
+#define __SMUAD __builtin_arm_smuad
+#define __SMUADX __builtin_arm_smuadx
+#define __SMLAD __builtin_arm_smlad
+#define __SMLADX __builtin_arm_smladx
+#define __SMLALD __builtin_arm_smlald
+#define __SMLALDX __builtin_arm_smlaldx
+#define __SMUSD __builtin_arm_smusd
+#define __SMUSDX __builtin_arm_smusdx
+#define __SMLSD __builtin_arm_smlsd
+#define __SMLSDX __builtin_arm_smlsdx
+#define __SMLSLD __builtin_arm_smlsld
+#define __SMLSLDX __builtin_arm_smlsldx
+#define __SEL __builtin_arm_sel
+#define __QADD __builtin_arm_qadd
+#define __QSUB __builtin_arm_qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang_ltm.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang_ltm.h
new file mode 100644
index 0000000..0e5c734
--- /dev/null
+++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang_ltm.h
@@ -0,0 +1,1893 @@
+/**************************************************************************//**
+ * @file cmsis_armclang_ltm.h
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V1.3.0
+ * @date 26. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF)
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_compiler.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_compiler.h
new file mode 100644
index 0000000..adbf296
--- /dev/null
+++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_compiler.h
@@ -0,0 +1,283 @@
+/**************************************************************************//**
+ * @file cmsis_compiler.h
+ * @brief CMSIS compiler generic header file
+ * @version V5.1.0
+ * @date 09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+ #include "cmsis_armclang_ltm.h"
+
+ /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+ #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+ #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+ #include <cmsis_ccs.h>
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed))
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed))
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #endif
+ #ifndef __RESTRICT
+ #define __RESTRICT __restrict
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __packed__
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __packed__
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __packed__
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __packed__ T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __align(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+ #include <cmsis_csm.h>
+
+ #ifndef __ASM
+ #define __ASM _asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ // NO RETURN is automatically detected hence no warning here
+ #define __NO_RETURN
+ #endif
+ #ifndef __USED
+ #warning No compiler specific solution for __USED. __USED is ignored.
+ #define __USED
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __weak
+ #endif
+ #ifndef __PACKED
+ #define __PACKED @packed
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT @packed struct
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION @packed union
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ @packed struct T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+#else
+ #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_gcc.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_gcc.h
new file mode 100644
index 0000000..a2778f5
--- /dev/null
+++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_gcc.h
@@ -0,0 +1,2177 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS compiler GCC header file
+ * @version V5.3.0
+ * @date 26. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+ #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+
+/**
+ \brief Initializes data and bss sections
+ \details This default implementations initialized all data and additional bss
+ sections relying on .copy.table and .zero.table specified properly
+ in the used linker script.
+
+ */
+__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
+{
+ extern void _start(void) __NO_RETURN;
+
+ typedef struct {
+ uint32_t const* src;
+ uint32_t* dest;
+ uint32_t wlen;
+ } __copy_table_t;
+
+ typedef struct {
+ uint32_t* dest;
+ uint32_t wlen;
+ } __zero_table_t;
+
+ extern const __copy_table_t __copy_table_start__;
+ extern const __copy_table_t __copy_table_end__;
+ extern const __zero_table_t __zero_table_start__;
+ extern const __zero_table_t __zero_table_end__;
+
+ for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {
+ for(uint32_t i=0u; i<pTable->wlen; ++i) {
+ pTable->dest[i] = pTable->src[i];
+ }
+ }
+
+ for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
+ for(uint32_t i=0u; i<pTable->wlen; ++i) {
+ pTable->dest[i] = 0u;
+ }
+ }
+
+ _start();
+}
+
+#define __PROGRAM_START __cmsis_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP __StackTop
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT __StackLimit
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors")))
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_get_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ return __builtin_arm_get_fpscr();
+#else
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#endif
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ __builtin_arm_set_fpscr(fpscr);
+#else
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP() __ASM volatile ("nop")
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI() __ASM volatile ("wfi":::"memory")
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE() __ASM volatile ("wfe":::"memory")
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV() __ASM volatile ("sev")
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (int16_t)__builtin_bswap16(value);
+#else
+ int16_t result;
+
+ __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return result;
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1, ARG2) \
+__extension__ \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1, ARG2) \
+ __extension__ \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+ return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1, ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1, ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)
+{
+ uint32_t result;
+
+ __ASM ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) );
+
+ return result;
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_iccarm.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_iccarm.h
new file mode 100644
index 0000000..7eeffca
--- /dev/null
+++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_iccarm.h
@@ -0,0 +1,968 @@
+/**************************************************************************//**
+ * @file cmsis_iccarm.h
+ * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version V5.2.0
+ * @date 28. January 2020
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2019 IAR Systems
+// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+ #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+ #define __ICCARM_V8 1
+#else
+ #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+ #if __ICCARM_V8
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #elif (__VER__ >= 7080000)
+ /* Needs IAR language extensions */
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #else
+ #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+ #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+ #if __ARM_ARCH == 6
+ #define __ARM_ARCH_6M__ 1
+ #elif __ARM_ARCH == 7
+ #if __ARM_FEATURE_DSP
+ #define __ARM_ARCH_7EM__ 1
+ #else
+ #define __ARM_ARCH_7M__ 1
+ #endif
+ #endif /* __ARM_ARCH */
+ #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+ #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+ #define __ARM_ARCH_6M__ 1
+ #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+ #define __ARM_ARCH_7M__ 1
+ #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+ #define __ARM_ARCH_7EM__ 1
+ #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #else
+ #error "Unknown target."
+ #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+ #define __IAR_M0_FAMILY 1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+ #define __IAR_M0_FAMILY 1
+#else
+ #define __IAR_M0_FAMILY 0
+#endif
+
+
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+
+#ifndef __NO_RETURN
+ #if __ICCARM_V8
+ #define __NO_RETURN __attribute__((__noreturn__))
+ #else
+ #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+ #endif
+#endif
+
+#ifndef __PACKED
+ #if __ICCARM_V8
+ #define __PACKED __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED __packed
+ #endif
+#endif
+
+#ifndef __PACKED_STRUCT
+ #if __ICCARM_V8
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_STRUCT __packed struct
+ #endif
+#endif
+
+#ifndef __PACKED_UNION
+ #if __ICCARM_V8
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_UNION __packed union
+ #endif
+#endif
+
+#ifndef __RESTRICT
+ #if __ICCARM_V8
+ #define __RESTRICT __restrict
+ #else
+ /* Needs IAR language extensions */
+ #define __RESTRICT restrict
+ #endif
+#endif
+
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+
+#ifndef __FORCEINLINE
+ #define __FORCEINLINE _Pragma("inline=forced")
+#endif
+
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+ return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+ *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+ return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+ *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef __USED
+ #if __ICCARM_V8
+ #define __USED __attribute__((used))
+ #else
+ #define __USED _Pragma("__root")
+ #endif
+#endif
+
+#ifndef __WEAK
+ #if __ICCARM_V8
+ #define __WEAK __attribute__((weak))
+ #else
+ #define __WEAK _Pragma("__weak")
+ #endif
+#endif
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __iar_program_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP CSTACK$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT CSTACK$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __vector_table
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
+#endif
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+ #define __ICCARM_INTRINSICS_VERSION__ 0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+ #if defined(__CLZ)
+ #undef __CLZ
+ #endif
+ #if defined(__REVSH)
+ #undef __REVSH
+ #endif
+ #if defined(__RBIT)
+ #undef __RBIT
+ #endif
+ #if defined(__SSAT)
+ #undef __SSAT
+ #endif
+ #if defined(__USAT)
+ #undef __USAT
+ #endif
+
+ #include "iccarm_builtin.h"
+
+ #define __disable_fault_irq __iar_builtin_disable_fiq
+ #define __disable_irq __iar_builtin_disable_interrupt
+ #define __enable_fault_irq __iar_builtin_enable_fiq
+ #define __enable_irq __iar_builtin_enable_interrupt
+ #define __arm_rsr __iar_builtin_rsr
+ #define __arm_wsr __iar_builtin_wsr
+
+
+ #define __get_APSR() (__arm_rsr("APSR"))
+ #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
+ #define __get_CONTROL() (__arm_rsr("CONTROL"))
+ #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
+
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ #define __get_FPSCR() (__arm_rsr("FPSCR"))
+ #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
+ #else
+ #define __get_FPSCR() ( 0 )
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #define __get_IPSR() (__arm_rsr("IPSR"))
+ #define __get_MSP() (__arm_rsr("MSP"))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __get_MSPLIM() (0U)
+ #else
+ #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
+ #endif
+ #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
+ #define __get_PSP() (__arm_rsr("PSP"))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __get_PSPLIM() (0U)
+ #else
+ #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
+ #endif
+
+ #define __get_xPSR() (__arm_rsr("xPSR"))
+
+ #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
+ #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
+ #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
+ #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
+ #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __set_MSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
+ #endif
+ #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
+ #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __set_PSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
+ #endif
+
+ #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
+ #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
+ #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
+ #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
+ #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
+ #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
+ #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
+ #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
+ #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
+ #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
+ #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
+ #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
+ #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
+ #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __TZ_get_PSPLIM_NS() (0U)
+ #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+ #else
+ #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
+ #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+ #endif
+
+ #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
+ #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+ #define __NOP __iar_builtin_no_operation
+
+ #define __CLZ __iar_builtin_CLZ
+ #define __CLREX __iar_builtin_CLREX
+
+ #define __DMB __iar_builtin_DMB
+ #define __DSB __iar_builtin_DSB
+ #define __ISB __iar_builtin_ISB
+
+ #define __LDREXB __iar_builtin_LDREXB
+ #define __LDREXH __iar_builtin_LDREXH
+ #define __LDREXW __iar_builtin_LDREX
+
+ #define __RBIT __iar_builtin_RBIT
+ #define __REV __iar_builtin_REV
+ #define __REV16 __iar_builtin_REV16
+
+ __IAR_FT int16_t __REVSH(int16_t val)
+ {
+ return (int16_t) __iar_builtin_REVSH(val);
+ }
+
+ #define __ROR __iar_builtin_ROR
+ #define __RRX __iar_builtin_RRX
+
+ #define __SEV __iar_builtin_SEV
+
+ #if !__IAR_M0_FAMILY
+ #define __SSAT __iar_builtin_SSAT
+ #endif
+
+ #define __STREXB __iar_builtin_STREXB
+ #define __STREXH __iar_builtin_STREXH
+ #define __STREXW __iar_builtin_STREX
+
+ #if !__IAR_M0_FAMILY
+ #define __USAT __iar_builtin_USAT
+ #endif
+
+ #define __WFE __iar_builtin_WFE
+ #define __WFI __iar_builtin_WFI
+
+ #if __ARM_MEDIA__
+ #define __SADD8 __iar_builtin_SADD8
+ #define __QADD8 __iar_builtin_QADD8
+ #define __SHADD8 __iar_builtin_SHADD8
+ #define __UADD8 __iar_builtin_UADD8
+ #define __UQADD8 __iar_builtin_UQADD8
+ #define __UHADD8 __iar_builtin_UHADD8
+ #define __SSUB8 __iar_builtin_SSUB8
+ #define __QSUB8 __iar_builtin_QSUB8
+ #define __SHSUB8 __iar_builtin_SHSUB8
+ #define __USUB8 __iar_builtin_USUB8
+ #define __UQSUB8 __iar_builtin_UQSUB8
+ #define __UHSUB8 __iar_builtin_UHSUB8
+ #define __SADD16 __iar_builtin_SADD16
+ #define __QADD16 __iar_builtin_QADD16
+ #define __SHADD16 __iar_builtin_SHADD16
+ #define __UADD16 __iar_builtin_UADD16
+ #define __UQADD16 __iar_builtin_UQADD16
+ #define __UHADD16 __iar_builtin_UHADD16
+ #define __SSUB16 __iar_builtin_SSUB16
+ #define __QSUB16 __iar_builtin_QSUB16
+ #define __SHSUB16 __iar_builtin_SHSUB16
+ #define __USUB16 __iar_builtin_USUB16
+ #define __UQSUB16 __iar_builtin_UQSUB16
+ #define __UHSUB16 __iar_builtin_UHSUB16
+ #define __SASX __iar_builtin_SASX
+ #define __QASX __iar_builtin_QASX
+ #define __SHASX __iar_builtin_SHASX
+ #define __UASX __iar_builtin_UASX
+ #define __UQASX __iar_builtin_UQASX
+ #define __UHASX __iar_builtin_UHASX
+ #define __SSAX __iar_builtin_SSAX
+ #define __QSAX __iar_builtin_QSAX
+ #define __SHSAX __iar_builtin_SHSAX
+ #define __USAX __iar_builtin_USAX
+ #define __UQSAX __iar_builtin_UQSAX
+ #define __UHSAX __iar_builtin_UHSAX
+ #define __USAD8 __iar_builtin_USAD8
+ #define __USADA8 __iar_builtin_USADA8
+ #define __SSAT16 __iar_builtin_SSAT16
+ #define __USAT16 __iar_builtin_USAT16
+ #define __UXTB16 __iar_builtin_UXTB16
+ #define __UXTAB16 __iar_builtin_UXTAB16
+ #define __SXTB16 __iar_builtin_SXTB16
+ #define __SXTAB16 __iar_builtin_SXTAB16
+ #define __SMUAD __iar_builtin_SMUAD
+ #define __SMUADX __iar_builtin_SMUADX
+ #define __SMMLA __iar_builtin_SMMLA
+ #define __SMLAD __iar_builtin_SMLAD
+ #define __SMLADX __iar_builtin_SMLADX
+ #define __SMLALD __iar_builtin_SMLALD
+ #define __SMLALDX __iar_builtin_SMLALDX
+ #define __SMUSD __iar_builtin_SMUSD
+ #define __SMUSDX __iar_builtin_SMUSDX
+ #define __SMLSD __iar_builtin_SMLSD
+ #define __SMLSDX __iar_builtin_SMLSDX
+ #define __SMLSLD __iar_builtin_SMLSLD
+ #define __SMLSLDX __iar_builtin_SMLSLDX
+ #define __SEL __iar_builtin_SEL
+ #define __QADD __iar_builtin_QADD
+ #define __QSUB __iar_builtin_QSUB
+ #define __PKHBT __iar_builtin_PKHBT
+ #define __PKHTB __iar_builtin_PKHTB
+ #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #define __CLZ __cmsis_iar_clz_not_active
+ #define __SSAT __cmsis_iar_ssat_not_active
+ #define __USAT __cmsis_iar_usat_not_active
+ #define __RBIT __cmsis_iar_rbit_not_active
+ #define __get_APSR __cmsis_iar_get_APSR_not_active
+ #endif
+
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+ #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+ #endif
+
+ #ifdef __INTRINSICS_INCLUDED
+ #error intrinsics.h is already included previously!
+ #endif
+
+ #include <intrinsics.h>
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #undef __CLZ
+ #undef __SSAT
+ #undef __USAT
+ #undef __RBIT
+ #undef __get_APSR
+
+ __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+ {
+ if (data == 0U) { return 32U; }
+
+ uint32_t count = 0U;
+ uint32_t mask = 0x80000000U;
+
+ while ((data & mask) == 0U)
+ {
+ count += 1U;
+ mask = mask >> 1U;
+ }
+ return count;
+ }
+
+ __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+ {
+ uint8_t sc = 31U;
+ uint32_t r = v;
+ for (v >>= 1U; v; v >>= 1U)
+ {
+ r <<= 1U;
+ r |= v & 1U;
+ sc--;
+ }
+ return (r << sc);
+ }
+
+ __STATIC_INLINE uint32_t __get_APSR(void)
+ {
+ uint32_t res;
+ __asm("MRS %0,APSR" : "=r" (res));
+ return res;
+ }
+
+ #endif
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #undef __get_FPSCR
+ #undef __set_FPSCR
+ #define __get_FPSCR() (0)
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #pragma diag_suppress=Pe940
+ #pragma diag_suppress=Pe177
+
+ #define __enable_irq __enable_interrupt
+ #define __disable_irq __disable_interrupt
+ #define __NOP __no_operation
+
+ #define __get_xPSR __get_PSR
+
+ #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+ __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+ {
+ return __LDREX((unsigned long *)ptr);
+ }
+
+ __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+ {
+ return __STREX(value, (unsigned long *)ptr);
+ }
+ #endif
+
+
+ /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+ #if (__CORTEX_M >= 0x03)
+
+ __IAR_FT uint32_t __RRX(uint32_t value)
+ {
+ uint32_t result;
+ __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value));
+ return(result);
+ }
+
+ __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
+ }
+
+
+ #define __enable_fault_irq __enable_fiq
+ #define __disable_fault_irq __disable_fiq
+
+
+ #endif /* (__CORTEX_M >= 0x03) */
+
+ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+ {
+ return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+ }
+
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+ __IAR_FT uint32_t __get_MSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,MSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_MSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR MSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __get_PSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_PSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
+ {
+ __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR PSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_SP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,SP_NS" : "=r" (res));
+ return res;
+ }
+ __IAR_FT void __TZ_set_SP_NS(uint32_t value)
+ {
+ __asm volatile("MSR SP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
+ }
+
+ #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+ __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+ {
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+ }
+
+ __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+ {
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+ }
+#endif
+
+#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+ {
+ __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+ {
+ __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+ {
+ __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+ }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+
+ __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+ {
+ __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+ {
+ __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+ {
+ __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
+#endif /* __CMSIS_ICCARM_H__ */
diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_version.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_version.h
new file mode 100644
index 0000000..2f048e4
--- /dev/null
+++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file cmsis_version.h
+ * @brief CMSIS Core(M) Version definitions
+ * @version V5.0.4
+ * @date 23. July 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/* CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
+#endif
diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/core_cm0plus.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/core_cm0plus.h
new file mode 100644
index 0000000..4e7179a
--- /dev/null
+++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/core_cm0plus.h
@@ -0,0 +1,1087 @@
+/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V5.0.9
+ * @date 21. August 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex-M0+
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+ __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (0U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0PLUS_REV
+ #define __CM0PLUS_REV 0x0000U
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0+ header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+#else
+ uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
+ *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */
+#endif
+ /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+#else
+ uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
+ return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */
+#endif
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/mpu_armv7.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/mpu_armv7.h
new file mode 100644
index 0000000..791a8da
--- /dev/null
+++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/mpu_armv7.h
@@ -0,0 +1,275 @@
+/******************************************************************************
+ * @file mpu_armv7.h
+ * @brief CMSIS MPU API for Armv7-M MPU
+ * @version V5.1.1
+ * @date 10. February 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
+ ((Region) & MPU_RBAR_REGION_Msk) | \
+ (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+*
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
+ ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
+ (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
+ (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
+ (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
+ ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
+ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
+ (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
+ (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
+ (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
+ (((MPU_RASR_ENABLE_Msk))))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+* - TEX: 000b
+* - Shareable
+* - Non-cacheable
+* - Non-bufferable
+*/
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+* - TEX: 000b (if shareable) or 010b (if non-shareable)
+* - Shareable or non-shareable
+* - Non-cacheable
+* - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+* - TEX: 1BBb (reflecting outer cacheability rules)
+* - Shareable or non-shareable
+* - Cacheable or non-cacheable (reflecting inner cacheability rules)
+* - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+ uint32_t RBAR; //!< The region base address register value (RBAR)
+ uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+ __DMB();
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ __DSB();
+ __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+ __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+ __DSB();
+ __ISB();
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+ MPU->RNR = rnr;
+ MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+ MPU->RNR = rnr;
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+ uint32_t i;
+ for (i = 0U; i < len; ++i)
+ {
+ dst[i] = src[i];
+ }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+ while (cnt > MPU_TYPE_RALIASES) {
+ ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+ table += MPU_TYPE_RALIASES;
+ cnt -= MPU_TYPE_RALIASES;
+ }
+ ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
diff --git a/src/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Include/RP2040.h b/src/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Include/RP2040.h
new file mode 100644
index 0000000..a29b9e0
--- /dev/null
+++ b/src/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Include/RP2040.h
@@ -0,0 +1,109 @@
+/*************************************************************************//**
+ * @file RP2040.h
+ * @brief CMSIS-Core(M) Device Peripheral Access Layer Header File for
+ * Device RP2040
+ * @version V1.0.0
+ * @date 5. May 2021
+ *****************************************************************************/
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _CMSIS_RP2040_H_
+#define _CMSIS_RP2040_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* =========================================================================================================================== */
+/* ================ Interrupt Number Definition ================ */
+/* =========================================================================================================================== */
+
+typedef enum
+{
+ /* ======================================= ARM Cortex-M0+ Specific Interrupt Numbers ======================================= */
+ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
+ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
+ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< -1 System Tick Timer */
+ /* =========================================== RP2040 Specific Interrupt Numbers =========================================== */
+ TIMER_IRQ_0_IRQn = 0, /*!< 0 TIMER_IRQ_0 */
+ TIMER_IRQ_1_IRQn = 1, /*!< 1 TIMER_IRQ_1 */
+ TIMER_IRQ_2_IRQn = 2, /*!< 2 TIMER_IRQ_2 */
+ TIMER_IRQ_3_IRQn = 3, /*!< 3 TIMER_IRQ_3 */
+ PWM_IRQ_WRAP_IRQn = 4, /*!< 4 PWM_IRQ_WRAP */
+ USBCTRL_IRQ_IRQn = 5, /*!< 5 USBCTRL_IRQ */
+ XIP_IRQ_IRQn = 6, /*!< 6 XIP_IRQ */
+ PIO0_IRQ_0_IRQn = 7, /*!< 7 PIO0_IRQ_0 */
+ PIO0_IRQ_1_IRQn = 8, /*!< 8 PIO0_IRQ_1 */
+ PIO1_IRQ_0_IRQn = 9, /*!< 9 PIO1_IRQ_0 */
+ PIO1_IRQ_1_IRQn = 10, /*!< 10 PIO1_IRQ_1 */
+ DMA_IRQ_0_IRQn = 11, /*!< 11 DMA_IRQ_0 */
+ DMA_IRQ_1_IRQn = 12, /*!< 12 DMA_IRQ_1 */
+ IO_IRQ_BANK0_IRQn = 13, /*!< 13 IO_IRQ_BANK0 */
+ IO_IRQ_QSPI_IRQn = 14, /*!< 14 IO_IRQ_QSPI */
+ SIO_IRQ_PROC0_IRQn = 15, /*!< 15 SIO_IRQ_PROC0 */
+ SIO_IRQ_PROC1_IRQn = 16, /*!< 16 SIO_IRQ_PROC1 */
+ CLOCKS_IRQ_IRQn = 17, /*!< 17 CLOCKS_IRQ */
+ SPI0_IRQ_IRQn = 18, /*!< 18 SPI0_IRQ */
+ SPI1_IRQ_IRQn = 19, /*!< 19 SPI1_IRQ */
+ UART0_IRQ_IRQn = 20, /*!< 20 UART0_IRQ */
+ UART1_IRQ_IRQn = 21, /*!< 21 UART1_IRQ */
+ ADC_IRQ_FIFO_IRQn = 22, /*!< 22 ADC_IRQ_FIFO */
+ I2C0_IRQ_IRQn = 23, /*!< 23 I2C0_IRQ */
+ I2C1_IRQ_IRQn = 24, /*!< 24 I2C1_IRQ */
+ RTC_IRQ_IRQn = 25 /*!< 25 RTC_IRQ */
+} IRQn_Type;
+
+/* =========================================================================================================================== */
+/* ================ Processor and Core Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+/* ========================== Configuration of the ARM Cortex-M0+ Processor and Core Peripherals =========================== */
+#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
+#define __MPU_PRESENT 1 /*!< MPU present */
+#define __FPU_PRESENT 0 /*!< FPU present */
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */
+#include "system_RP2040.h" /*!< RP2040 System */
+
+#ifndef __IM /*!< Fallback for older CMSIS versions */
+#define __IM __I
+#endif
+#ifndef __OM /*!< Fallback for older CMSIS versions */
+#define __OM __O
+#endif
+#ifndef __IOM /*!< Fallback for older CMSIS versions */
+#define __IOM __IO
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CMSIS_RP2040_H */
diff --git a/src/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Include/system_RP2040.h b/src/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Include/system_RP2040.h
new file mode 100644
index 0000000..30881cc
--- /dev/null
+++ b/src/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Include/system_RP2040.h
@@ -0,0 +1,65 @@
+/*************************************************************************//**
+ * @file system_RP2040.h
+ * @brief CMSIS-Core(M) Device Peripheral Access Layer Header File for
+ * Device RP2040
+ * @version V1.0.0
+ * @date 5. May 2021
+ *****************************************************************************/
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _CMSIS_SYSTEM_RP2040_H
+#define _CMSIS_SYSTEM_RP2040_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ \brief Exception / Interrupt Handler Function Prototype
+*/
+typedef void(*VECTOR_TABLE_Type)(void);
+
+/**
+ \brief System Clock Frequency (Core Clock)
+*/
+extern uint32_t SystemCoreClock;
+
+/**
+ \brief Setup the microcontroller system.
+
+ Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+ \brief Update SystemCoreClock variable.
+
+ Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CMSIS_SYSTEM_RP2040_H */
diff --git a/src/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Source/system_RP2040.c b/src/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Source/system_RP2040.c
new file mode 100644
index 0000000..055a075
--- /dev/null
+++ b/src/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Source/system_RP2040.c
@@ -0,0 +1,52 @@
+/*************************************************************************//**
+ * @file system_RP2040.c
+ * @brief CMSIS-Core(M) Device Peripheral Access Layer Header File for
+ * Device RP2040
+ * @version V1.0.0
+ * @date 5. May 2021
+ *****************************************************************************/
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include "RP2040.h"
+#include "hardware/clocks.h"
+
+/*---------------------------------------------------------------------------
+ System Core Clock Variable
+ *---------------------------------------------------------------------------*/
+uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock)*/
+
+/*---------------------------------------------------------------------------
+ System Core Clock function
+ *---------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = clock_get_hz(clk_sys);
+}
+
+/*---------------------------------------------------------------------------
+ System initialization function
+ *---------------------------------------------------------------------------*/
+void __attribute__((constructor)) SystemInit (void)
+{
+ SystemCoreClockUpdate();
+}
\ No newline at end of file
diff --git a/src/rp2_common/cmsis/stub/CMSIS/LICENSE.txt b/src/rp2_common/cmsis/stub/CMSIS/LICENSE.txt
new file mode 100644
index 0000000..8dada3e
--- /dev/null
+++ b/src/rp2_common/cmsis/stub/CMSIS/LICENSE.txt
@@ -0,0 +1,201 @@
+ Apache License
+ Version 2.0, January 2004
+ http://www.apache.org/licenses/
+
+ TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+ 1. Definitions.
+
+ "License" shall mean the terms and conditions for use, reproduction,
+ and distribution as defined by Sections 1 through 9 of this document.
+
+ "Licensor" shall mean the copyright owner or entity authorized by
+ the copyright owner that is granting the License.
+
+ "Legal Entity" shall mean the union of the acting entity and all
+ other entities that control, are controlled by, or are under common
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+ "control" means (i) the power, direct or indirect, to cause the
+ direction or management of such entity, whether by contract or
+ otherwise, or (ii) ownership of fifty percent (50%) or more of the
+ outstanding shares, or (iii) beneficial ownership of such entity.
+
+ "You" (or "Your") shall mean an individual or Legal Entity
+ exercising permissions granted by this License.
+
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+ including but not limited to software source code, documentation
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+
+ "Object" form shall mean any form resulting from mechanical
+ transformation or translation of a Source form, including but
+ not limited to compiled object code, generated documentation,
+ and conversions to other media types.
+
+ "Work" shall mean the work of authorship, whether in Source or
+ Object form, made available under the License, as indicated by a
+ copyright notice that is included in or attached to the work
+ (an example is provided in the Appendix below).
+
+ "Derivative Works" shall mean any work, whether in Source or Object
+ form, that is based on (or derived from) the Work and for which the
+ editorial revisions, annotations, elaborations, or other modifications
+ represent, as a whole, an original work of authorship. For the purposes
+ of this License, Derivative Works shall not include works that remain
+ separable from, or merely link (or bind by name) to the interfaces of,
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+
+ "Contribution" shall mean any work of authorship, including
+ the original version of the Work and any modifications or additions
+ to that Work or Derivative Works thereof, that is intentionally
+ submitted to Licensor for inclusion in the Work by the copyright owner
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+ excluding communication that is conspicuously marked or otherwise
+ designated in writing by the copyright owner as "Not a Contribution."
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+ "Contributor" shall mean Licensor and any individual or Legal Entity
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+ 2. Grant of Copyright License. Subject to the terms and conditions of
+ this License, each Contributor hereby grants to You a perpetual,
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+ copyright license to reproduce, prepare Derivative Works of,
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diff --git a/src/rp2_common/hardware_adc/include/hardware/adc.h b/src/rp2_common/hardware_adc/include/hardware/adc.h
index 8e1ff22..35586a6 100644
--- a/src/rp2_common/hardware_adc/include/hardware/adc.h
+++ b/src/rp2_common/hardware_adc/include/hardware/adc.h
@@ -88,6 +88,15 @@
hw_write_masked(&adc_hw->cs, input << ADC_CS_AINSEL_LSB, ADC_CS_AINSEL_BITS);
}
+/*! \brief Get the currently selected ADC input channel
+ * \ingroup hardware_adc
+ *
+ * \return The currently selected input channel. 0...3 are GPIOs 26...29 respectively. Input 4 is the onboard temperature sensor.
+ */
+static inline uint adc_get_selected_input(void) {
+ return (adc_hw->cs & ADC_CS_AINSEL_BITS) >> ADC_CS_AINSEL_LSB;
+}
+
/*! \brief Round Robin sampling selector
* \ingroup hardware_adc
*
diff --git a/src/rp2_common/hardware_base/include/hardware/address_mapped.h b/src/rp2_common/hardware_base/include/hardware/address_mapped.h
index 1c1b29c..b58f1e5 100644
--- a/src/rp2_common/hardware_base/include/hardware/address_mapped.h
+++ b/src/rp2_common/hardware_base/include/hardware/address_mapped.h
@@ -84,7 +84,7 @@
* \param addr Address of writable register
* \param mask Bit-mask specifying bits to set
*/
-inline static void hw_set_bits(io_rw_32 *addr, uint32_t mask) {
+__force_inline static void hw_set_bits(io_rw_32 *addr, uint32_t mask) {
*(io_rw_32 *) hw_set_alias_untyped((volatile void *) addr) = mask;
}
@@ -94,7 +94,7 @@
* \param addr Address of writable register
* \param mask Bit-mask specifying bits to clear
*/
-inline static void hw_clear_bits(io_rw_32 *addr, uint32_t mask) {
+__force_inline static void hw_clear_bits(io_rw_32 *addr, uint32_t mask) {
*(io_rw_32 *) hw_clear_alias_untyped((volatile void *) addr) = mask;
}
@@ -104,7 +104,7 @@
* \param addr Address of writable register
* \param mask Bit-mask specifying bits to invert
*/
-inline static void hw_xor_bits(io_rw_32 *addr, uint32_t mask) {
+__force_inline static void hw_xor_bits(io_rw_32 *addr, uint32_t mask) {
*(io_rw_32 *) hw_xor_alias_untyped((volatile void *) addr) = mask;
}
@@ -120,7 +120,7 @@
* \param values Bits values
* \param write_mask Mask of bits to change
*/
-inline static void hw_write_masked(io_rw_32 *addr, uint32_t values, uint32_t write_mask) {
+__force_inline static void hw_write_masked(io_rw_32 *addr, uint32_t values, uint32_t write_mask) {
hw_xor_bits(addr, (*addr ^ values) & write_mask);
}
diff --git a/src/rp2_common/hardware_claim/CMakeLists.txt b/src/rp2_common/hardware_claim/CMakeLists.txt
index 33213fa..63f4806 100644
--- a/src/rp2_common/hardware_claim/CMakeLists.txt
+++ b/src/rp2_common/hardware_claim/CMakeLists.txt
@@ -1,6 +1,2 @@
-add_library(hardware_claim INTERFACE)
-target_include_directories(hardware_claim INTERFACE include)
-target_sources(hardware_claim INTERFACE
- ${CMAKE_CURRENT_LIST_DIR}/claim.c)
-
+pico_simple_hardware_target(claim)
target_link_libraries(hardware_claim INTERFACE hardware_sync)
\ No newline at end of file
diff --git a/src/rp2_common/hardware_claim/claim.c b/src/rp2_common/hardware_claim/claim.c
index 96f341e..c96764f 100644
--- a/src/rp2_common/hardware_claim/claim.c
+++ b/src/rp2_common/hardware_claim/claim.c
@@ -14,22 +14,13 @@
spin_unlock(spin_lock_instance(PICO_SPINLOCK_ID_HARDWARE_CLAIM), save);
}
-bool hw_is_claimed(uint8_t *bits, uint bit_index) {
- bool rc;
- uint32_t save = hw_claim_lock();
- if (bits[bit_index >> 3u] & (1u << (bit_index & 7u))) {
- rc = false;
- } else {
- bits[bit_index >> 3u] |= (uint8_t)(1u << (bit_index & 7u));
- rc = true;
- }
- hw_claim_unlock(save);
- return rc;
+inline bool hw_is_claimed(const uint8_t *bits, uint bit_index) {
+ return (bits[bit_index >> 3u] & (1u << (bit_index & 7u)));
}
void hw_claim_or_assert(uint8_t *bits, uint bit_index, const char *message) {
uint32_t save = hw_claim_lock();
- if (bits[bit_index >> 3u] & (1u << (bit_index & 7u))) {
+ if (hw_is_claimed(bits, bit_index)) {
panic(message, bit_index);
} else {
bits[bit_index >> 3u] |= (uint8_t)(1u << (bit_index & 7u));
@@ -42,7 +33,7 @@
uint32_t save = hw_claim_lock();
int found_bit = -1;
for(uint bit=bit_lsb; bit <= bit_msb; bit++) {
- if (!(bits[bit >> 3u] & (1u << (bit & 7u)))) {
+ if (!hw_is_claimed(bits, bit)) {
bits[bit >> 3u] |= (uint8_t)(1u << (bit & 7u));
found_bit = (int)bit;
break;
@@ -57,7 +48,7 @@
void hw_claim_clear(uint8_t *bits, uint bit_index) {
uint32_t save = hw_claim_lock();
- assert(bits[bit_index >> 3u] & (1u << (bit_index & 7u)));
+ assert(hw_is_claimed(bits, bit_index));
bits[bit_index >> 3u] &= (uint8_t) ~(1u << (bit_index & 7u));
hw_claim_unlock(save);
}
diff --git a/src/rp2_common/hardware_claim/include/hardware/claim.h b/src/rp2_common/hardware_claim/include/hardware/claim.h
index 681962a..5c93453 100644
--- a/src/rp2_common/hardware_claim/include/hardware/claim.h
+++ b/src/rp2_common/hardware_claim/include/hardware/claim.h
@@ -65,10 +65,10 @@
* The resource ownership is indicated by the bit_index bit in an array of bits.
*
* \param bits pointer to an array of bits (8 bits per byte)
- * \param bit_index resource to unclaim (bit index into array of bits)
+ * \param bit_index resource to check (bit index into array of bits)
* \return true if the resource is claimed
*/
-bool hw_is_claimed(uint8_t *bits, uint bit_index);
+bool hw_is_claimed(const uint8_t *bits, uint bit_index);
/*! \brief Atomically unclaim a resource
* \ingroup hardware_claim
diff --git a/src/rp2_common/hardware_clocks/CMakeLists.txt b/src/rp2_common/hardware_clocks/CMakeLists.txt
index 3718d83..ceb29e2 100644
--- a/src/rp2_common/hardware_clocks/CMakeLists.txt
+++ b/src/rp2_common/hardware_clocks/CMakeLists.txt
@@ -1,11 +1,13 @@
pico_simple_hardware_target(clocks)
target_link_libraries(hardware_clocks INTERFACE
+ hardware_gpio
+ hardware_irq
hardware_resets
- hardware_watchdog
- hardware_xosc
hardware_pll
# not currently used by clocks.c, but sensibly bundled here
# as changing frequencies may require upping voltage
hardware_vreg
+ hardware_watchdog
+ hardware_xosc
)
\ No newline at end of file
diff --git a/src/rp2_common/hardware_clocks/clocks.c b/src/rp2_common/hardware_clocks/clocks.c
index ac11680..f51331a 100644
--- a/src/rp2_common/hardware_clocks/clocks.c
+++ b/src/rp2_common/hardware_clocks/clocks.c
@@ -7,7 +7,6 @@
#include "pico.h"
#include "hardware/regs/clocks.h"
#include "hardware/platform_defs.h"
-#include "hardware/resets.h"
#include "hardware/clocks.h"
#include "hardware/watchdog.h"
#include "hardware/pll.h"
@@ -71,6 +70,8 @@
// propagating when changing aux mux. Note it would be a really bad idea
// to do this on one of the glitchless clocks (clk_sys, clk_ref).
else {
+ // Disable clock. On clk_ref and clk_sys this does nothing,
+ // all other clocks have the ENABLE bit in the same position.
hw_clear_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS);
if (configured_freq[clk_index] > 0) {
// Delay for 3 cycles of the target clock, for ENABLE propagation.
@@ -102,6 +103,8 @@
tight_loop_contents();
}
+ // Enable clock. On clk_ref and clk_sys this does nothing,
+ // all other clocks have the ENABLE bit in the same position.
hw_set_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS);
// Now that the source is configured, we can trust that the user-supplied
@@ -109,7 +112,7 @@
clock->div = div;
// Store the configured frequency
- configured_freq[clk_index] = freq;
+ configured_freq[clk_index] = (uint32_t)(((uint64_t) src_freq << 8) / div);
return true;
}
@@ -149,9 +152,6 @@
// PLL USB: 12 / 1 = 12MHz * 40 = 480 MHz / 5 / 2 = 48MHz
/// \end::pll_settings[]
- reset_block(RESETS_RESET_PLL_SYS_BITS | RESETS_RESET_PLL_USB_BITS);
- unreset_block_wait(RESETS_RESET_PLL_SYS_BITS | RESETS_RESET_PLL_USB_BITS);
-
/// \tag::pll_init[]
pll_init(pll_sys, 1, 1500 * MHZ, 6, 2);
pll_init(pll_usb, 1, 480 * MHZ, 5, 2);
diff --git a/src/rp2_common/hardware_divider/CMakeLists.txt b/src/rp2_common/hardware_divider/CMakeLists.txt
index 3bbdded..296a1ef 100644
--- a/src/rp2_common/hardware_divider/CMakeLists.txt
+++ b/src/rp2_common/hardware_divider/CMakeLists.txt
@@ -1,4 +1,3 @@
-add_library(hardware_divider INTERFACE)
+pico_simple_hardware_headers_only_target(divider)
target_sources(hardware_divider INTERFACE ${CMAKE_CURRENT_LIST_DIR}/divider.S)
-target_include_directories(hardware_divider INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
target_link_libraries(hardware_divider INTERFACE hardware_structs)
\ No newline at end of file
diff --git a/src/rp2_common/hardware_divider/include/hardware/divider_helper.S b/src/rp2_common/hardware_divider/include/hardware/divider_helper.S
new file mode 100644
index 0000000..062e12d
--- /dev/null
+++ b/src/rp2_common/hardware_divider/include/hardware/divider_helper.S
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hardware/regs/addressmap.h"
+#include "hardware/regs/sio.h"
+
+#if SIO_DIV_CSR_READY_LSB == 0
+.equ SIO_DIV_CSR_READY_SHIFT_FOR_CARRY, 1
+#else
+need to change SHIFT above
+#endif
+#if SIO_DIV_CSR_DIRTY_LSB == 1
+.equ SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY, 2
+#else
+need to change SHIFT above
+#endif
+
+// SIO_BASE ptr in r2; pushes r4-r7, lr to stack
+// requires that division started at least 2 cycles prior to the start of the macro
+.macro save_div_state_and_lr
+// originally we did this, however a) it uses r3, and b) the push takes 6 cycles, b)
+// any IRQ which uses the divider will necessarily put the data back, which will
+// immediately make it ready
+//
+// // ldr r3, [r2, #SIO_DIV_CSR_OFFSET]
+// // // wait for results as we can't save signed-ness of operation
+// // 1:
+// // lsrs r3, #SIO_DIV_CSR_READY_SHIFT_FOR_CARRY
+// // bcc 1b
+
+// 6 cycles
+push {r4, r5, r6, r7, lr}
+// note we must read quotient last, and since it isn't the last reg, we'll not use ldmia!
+ldr r4, [r2, #SIO_DIV_UDIVIDEND_OFFSET]
+ldr r5, [r2, #SIO_DIV_UDIVISOR_OFFSET]
+ldr r7, [r2, #SIO_DIV_REMAINDER_OFFSET]
+ldr r6, [r2, #SIO_DIV_QUOTIENT_OFFSET]
+.endm
+
+// restores divider state from r4-r7, then pops them and pc
+.macro restore_div_state_and_return
+// writing sdividend (r4), sdivisor (r5), quotient (r6), remainder (r7) in that order
+//
+// it is worth considering what happens if we are interrupted
+//
+// after writing r4: we are DIRTY and !READY
+// ... interruptor using div will complete based on incorrect inputs, but dividend at least will be
+// saved/restored correctly and we'll restore the rest ourselves
+// after writing r4, r5: we are DIRTY and !READY
+// ... interruptor using div will complete based on possibly wrongly signed inputs, but dividend, divisor
+// at least will be saved/restored correctly and and we'll restore the rest ourselves
+// after writing r4, r5, r6: we are DIRTY and READY
+// ... interruptor using div will dividend, divisor, quotient registers as is (what we just restored ourselves),
+// and we'll restore the remainder after the fact
+
+// note we are not use STM not because it can be restarted due to interrupt which is harmless, more because this is 1 cycle IO space
+// and so 4 reads is cheaper (and we don't have to adjust r2)
+// note also, that we must restore via UDIVI* rather than SDIVI* to prevent the quotient/remainder being negated on read based
+// on the signs of the inputs
+str r4, [r2, #SIO_DIV_UDIVIDEND_OFFSET]
+str r5, [r2, #SIO_DIV_UDIVISOR_OFFSET]
+str r7, [r2, #SIO_DIV_REMAINDER_OFFSET]
+str r6, [r2, #SIO_DIV_QUOTIENT_OFFSET]
+pop {r4, r5, r6, r7, pc}
+.endm
\ No newline at end of file
diff --git a/src/rp2_common/hardware_dma/dma.c b/src/rp2_common/hardware_dma/dma.c
index d648bfb..230fa16 100644
--- a/src/rp2_common/hardware_dma/dma.c
+++ b/src/rp2_common/hardware_dma/dma.c
@@ -39,6 +39,11 @@
return hw_claim_unused_from_range((uint8_t*)&_claimed, required, 0, NUM_DMA_CHANNELS-1, "No DMA channels are available");
}
+bool dma_channel_is_claimed(uint channel) {
+ check_dma_channel_param(channel);
+ return hw_is_claimed((uint8_t *) &_claimed, channel);
+}
+
#ifndef NDEBUG
void print_dma_ctrl(dma_channel_hw_t *channel) {
diff --git a/src/rp2_common/hardware_dma/include/hardware/dma.h b/src/rp2_common/hardware_dma/include/hardware/dma.h
index 7c04728..526d632 100644
--- a/src/rp2_common/hardware_dma/include/hardware/dma.h
+++ b/src/rp2_common/hardware_dma/include/hardware/dma.h
@@ -34,8 +34,12 @@
* * Memory to memory
*/
-// this is not defined in generated dreq.h
-#define DREQ_FORCE 63
+// these are not defined in generated dreq.h
+#define DREQ_DMA_TIMER0 DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0
+#define DREQ_DMA_TIMER1 DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1
+#define DREQ_DMA_TIMER2 DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2
+#define DREQ_DMA_TIMER3 DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3
+#define DREQ_FORCE DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_DMA, Enable/disable DMA assertions, type=bool, default=0, group=hardware_dma
#ifndef PARAM_ASSERTIONS_ENABLED_DMA
@@ -94,6 +98,16 @@
*/
int dma_claim_unused_channel(bool required);
+/*! \brief Determine if a dma channel is claimed
+ * \ingroup hardware_dma
+ *
+ * \param channel the dma channel
+ * \return true if the channel is claimed, false otherwise
+ * \see dma_channel_claim
+ * \see dma_channel_claim_mask
+ */
+bool dma_channel_is_claimed(uint channel);
+
/** \brief DMA channel configuration
* \defgroup channel_config channel_config
* \ingroup hardware_dma
@@ -353,7 +367,7 @@
}
}
-/*! \brief Set the DMA initial read address
+/*! \brief Set the DMA initial write address
* \ingroup hardware_dma
*
* \param channel DMA channel
@@ -409,7 +423,8 @@
* \param read_addr Sets the initial read address
* \param transfer_count Number of transfers to make. Not bytes, but the number of transfers of channel_config_set_transfer_data_size() to be sent.
*/
-inline static void __attribute__((always_inline)) dma_channel_transfer_from_buffer_now(uint channel, void *read_addr,
+inline static void __attribute__((always_inline)) dma_channel_transfer_from_buffer_now(uint channel,
+ const volatile void *read_addr,
uint32_t transfer_count) {
// check_dma_channel_param(channel);
dma_channel_hw_t *hw = dma_channel_hw_addr(channel);
@@ -424,7 +439,7 @@
* \param write_addr Sets the initial write address
* \param transfer_count Number of transfers to make. Not bytes, but the number of transfers of channel_config_set_transfer_data_size() to be sent.
*/
-inline static void dma_channel_transfer_to_buffer_now(uint channel, void *write_addr, uint32_t transfer_count) {
+inline static void dma_channel_transfer_to_buffer_now(uint channel, volatile void *write_addr, uint32_t transfer_count) {
dma_channel_hw_t *hw = dma_channel_hw_addr(channel);
hw->write_addr = (uintptr_t) write_addr;
hw->al1_transfer_count_trig = transfer_count;
@@ -464,7 +479,7 @@
while (dma_hw->abort & (1ul << channel)) tight_loop_contents();
}
-/*! \brief Enable single DMA channel interrupt 0
+/*! \brief Enable single DMA channel's interrupt via DMA_IRQ_0
* \ingroup hardware_dma
*
* \param channel DMA channel
@@ -479,7 +494,7 @@
hw_clear_bits(&dma_hw->inte0, 1u << channel);
}
-/*! \brief Enable multiple DMA channels interrupt 0
+/*! \brief Enable multiple DMA channels' interrupts via DMA_IRQ_0
* \ingroup hardware_dma
*
* \param channel_mask Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc.
@@ -493,7 +508,7 @@
}
}
-/*! \brief Enable single DMA channel interrupt 1
+/*! \brief Enable single DMA channel's interrupt via DMA_IRQ_1
* \ingroup hardware_dma
*
* \param channel DMA channel
@@ -508,7 +523,7 @@
hw_clear_bits(&dma_hw->inte1, 1u << channel);
}
-/*! \brief Enable multiple DMA channels interrupt 0
+/*! \brief Enable multiple DMA channels' interrupts via DMA_IRQ_1
* \ingroup hardware_dma
*
* \param channel_mask Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc.
@@ -522,6 +537,105 @@
}
}
+/*! \brief Enable single DMA channel interrupt on either DMA_IRQ_0 or DMA_IRQ_1
+ * \ingroup hardware_dma
+ *
+ * \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1
+ * \param channel DMA channel
+ * \param enabled true to enable interrupt via irq_index for specified channel, false to disable.
+ */
+static inline void dma_irqn_set_channel_enabled(uint irq_index, uint channel, bool enabled) {
+ invalid_params_if(DMA, irq_index > 1);
+ if (irq_index) {
+ dma_channel_set_irq1_enabled(channel, enabled);
+ } else {
+ dma_channel_set_irq0_enabled(channel, enabled);
+ }
+}
+
+/*! \brief Enable multiple DMA channels' interrupt via either DMA_IRQ_0 or DMA_IRQ_1
+ * \ingroup hardware_dma
+ *
+ * \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1
+ * \param channel_mask Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc.
+ * \param enabled true to enable all the interrupts specified in the mask, false to disable all the interrupts specified in the mask.
+ */
+static inline void dma_irqn_set_channel_mask_enabled(uint irq_index, uint32_t channel_mask, bool enabled) {
+ invalid_params_if(DMA, irq_index > 1);
+ if (irq_index) {
+ dma_set_irq1_channel_mask_enabled(channel_mask, enabled);
+ } else {
+ dma_set_irq0_channel_mask_enabled(channel_mask, enabled);
+ }
+}
+
+/*! \brief Determine if a particular channel is a cause of DMA_IRQ_0
+ * \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ * \return true if the channel is a cause of DMA_IRQ_0, false otherwise
+ */
+static inline bool dma_channel_get_irq0_status(uint channel) {
+ check_dma_channel_param(channel);
+ return dma_hw->ints0 & (1u << channel);
+}
+
+/*! \brief Determine if a particular channel is a cause of DMA_IRQ_1
+ * \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ * \return true if the channel is a cause of DMA_IRQ_1, false otherwise
+ */
+static inline bool dma_channel_get_irq1_status(uint channel) {
+ check_dma_channel_param(channel);
+ return dma_hw->ints1 & (1u << channel);
+}
+
+/*! \brief Determine if a particular channel is a cause of DMA_IRQ_N
+ * \ingroup hardware_dma
+ *
+ * \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1
+ * \param channel DMA channel
+ * \return true if the channel is a cause of the DMA_IRQ_N, false otherwise
+ */
+static inline bool dma_irqn_get_channel_status(uint irq_index, uint channel) {
+ invalid_params_if(DMA, irq_index > 1);
+ check_dma_channel_param(channel);
+ return (irq_index ? dma_hw->ints1 : dma_hw->ints0) & (1u << channel);
+}
+
+/*! \brief Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_0
+ * \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ */
+static inline void dma_channel_acknowledge_irq0(uint channel) {
+ check_dma_channel_param(channel);
+ hw_set_bits(&dma_hw->ints0, (1u << channel));
+}
+
+/*! \brief Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_1
+ * \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ */
+static inline void dma_channel_acknowledge_irq1(uint channel) {
+ check_dma_channel_param(channel);
+ hw_set_bits(&dma_hw->ints1, (1u << channel));
+}
+
+/*! \brief Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_N
+ * \ingroup hardware_dma
+ *
+ * \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1
+ * \param channel DMA channel
+ */
+static inline void dma_irqn_acknowledge_channel(uint irq_index, uint channel) {
+ invalid_params_if(DMA, irq_index > 1);
+ check_dma_channel_param(channel);
+ hw_set_bits(irq_index ? &dma_hw->ints1 : &dma_hw->ints0, (1u << channel));
+}
+
/*! \brief Check if DMA channel is busy
* \ingroup hardware_dma
*
diff --git a/src/rp2_common/hardware_exception/CMakeLists.txt b/src/rp2_common/hardware_exception/CMakeLists.txt
new file mode 100644
index 0000000..a994dc0
--- /dev/null
+++ b/src/rp2_common/hardware_exception/CMakeLists.txt
@@ -0,0 +1 @@
+pico_simple_hardware_target(exception)
\ No newline at end of file
diff --git a/src/rp2_common/hardware_exception/exception.c b/src/rp2_common/hardware_exception/exception.c
new file mode 100644
index 0000000..8a9a108
--- /dev/null
+++ b/src/rp2_common/hardware_exception/exception.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hardware/exception.h"
+#include "hardware/regs/m0plus.h"
+#include "hardware/platform_defs.h"
+#include "hardware/structs/scb.h"
+
+#include "pico/mutex.h"
+#include "pico/assert.h"
+
+#ifndef exception_is_compile_time_default
+static bool exception_is_compile_time_default(exception_handler_t handler) {
+ extern char __default_isrs_start;
+ extern char __default_isrs_end;
+ return ((uintptr_t)handler) >= (uintptr_t)&__default_isrs_start &&
+ ((uintptr_t)handler) < (uintptr_t)&__default_isrs_end;
+}
+#endif
+
+static inline exception_handler_t *get_vtable(void) {
+ return (exception_handler_t *) scb_hw->vtor;
+}
+
+static void set_raw_exception_handler_and_restore_interrupts(enum exception_number num, exception_handler_t handler, uint32_t save) {
+ // update vtable (vtable_handler may be same or updated depending on cases, but we do it anyway for compactness)
+ get_vtable()[16 + num] = handler;
+ __dmb();
+ restore_interrupts(save);
+}
+
+static inline void check_exception_param(__unused enum exception_number num) {
+ invalid_params_if(EXCEPTION, num < NMI_EXCEPTION || num >=0);
+}
+
+exception_handler_t exception_get_vtable_handler(enum exception_number num) {
+ check_exception_param(num);
+ return get_vtable()[16 + num];
+}
+
+exception_handler_t exception_set_exclusive_handler(enum exception_number num, exception_handler_t handler) {
+ check_exception_param(num);
+#if !PICO_NO_RAM_VECTOR_TABLE
+ uint32_t save = save_and_disable_interrupts();
+ exception_handler_t current = exception_get_vtable_handler(num);
+ hard_assert(handler == current || exception_is_compile_time_default(current));
+ set_raw_exception_handler_and_restore_interrupts(num, handler, save);
+#else
+ panic_unsupported();
+#endif
+ return current;
+}
+
+void exception_restore_handler(enum exception_number num, exception_handler_t original_handler) {
+ hard_assert(exception_is_compile_time_default(original_handler));
+#if !PICO_NO_RAM_VECTOR_TABLE
+ uint32_t save = save_and_disable_interrupts();
+ set_raw_exception_handler_and_restore_interrupts(num, original_handler, save);
+#else
+ panic_unsupported();
+#endif
+}
\ No newline at end of file
diff --git a/src/rp2_common/hardware_exception/include/hardware/exception.h b/src/rp2_common/hardware_exception/include/hardware/exception.h
new file mode 100644
index 0000000..0b805d7
--- /dev/null
+++ b/src/rp2_common/hardware_exception/include/hardware/exception.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_EXCEPTION_H_
+#define _HARDWARE_EXCEPTION_H_
+
+#include "pico.h"
+#include "hardware/address_mapped.h"
+#include "hardware/regs/m0plus.h"
+
+/** \file exception.h
+ * \defgroup hardware_exception hardware_exception
+ *
+ * Methods for setting processor exception handlers
+ *
+ * Exceptions are identified by a \ref exception_num which is a number from -15 to -1; these are the numbers relative to
+ * the index of the first IRQ vector in the vector table. (i.e. vector table index is exception_num plus 16)
+ *
+ * There is one set of exception handlers per core, so the exception handlers for each core as set by these methods are independent.
+ *
+ * \note That all exception APIs affect the executing core only (i.e. the core calling the function).
+ */
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_EXCEPTION, Enable/disable assertions in the exception module, type=bool, default=0, group=hardware_exception
+#ifndef PARAM_ASSERTIONS_ENABLED_EXCEPTION
+#define PARAM_ASSERTIONS_ENABLED_EXCEPTION 0
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*! \brief Exception number definitions
+ *
+ * Note for consistency with irq numbers, these numbers are defined to be negative. The VTABLE index is
+ * the number here plus 16.
+ *
+ * Name | Value | Exception
+ * ---------------------|-------|----------
+ * NMI_EXCEPTION | -14 | Non Maskable Interrupt
+ * HARDFAULT_EXCEPTION | -13 | HardFault
+ * SVCALL_EXCEPTION | -5 | SV Call
+ * PENDSV_EXCEPTION | -2 | Pend SV
+ * SYSTICK_EXCEPTION | -1 | System Tick
+ *
+ * \ingroup hardware_exception
+ */
+enum exception_number {
+ NMI_EXCEPTION = -14, /* Non Maskable Interrupt */
+ HARDFAULT_EXCEPTION = -13, /* HardFault Interrupt */
+ SVCALL_EXCEPTION = -5, /* SV Call Interrupt */
+ PENDSV_EXCEPTION = -2, /* Pend SV Interrupt */
+ SYSTICK_EXCEPTION = -1, /* System Tick Interrupt */
+};
+
+/*! \brief Exception handler function type
+ * \ingroup hardware_exception
+ *
+ * All exception handlers should be of this type, and follow normal ARM EABI register saving conventions
+ */
+typedef void (*exception_handler_t)(void);
+
+/*! \brief Set the exception handler for an exception on the executing core.
+ * \ingroup hardware_exception
+ *
+ * This method will assert if an exception handler has been set for this exception number on this core via
+ * this method, without an intervening restore via exception_restore_handler.
+ *
+ * \note this method may not be used to override an exception handler that was specified at link time by
+ * providing a strong replacement for the weakly defined stub exception handlers. It will assert in this case too.
+ *
+ * \param num Exception number
+ * \param handler The handler to set
+ * \see exception_number
+ */
+exception_handler_t exception_set_exclusive_handler(enum exception_number num, exception_handler_t handler);
+
+/*! \brief Restore the original exception handler for an exception on this core
+ * \ingroup hardware_exception
+ *
+ * This method may be used to restore the exception handler for an exception on this core to the state
+ * prior to the call to exception_set_exclusive_handler(), so that exception_set_exclusive_handler()
+ * may be called again in the future.
+ *
+ * \param num Exception number \ref exception_nums
+ * \param original_handler The original handler returned from \ref exception_set_exclusive_handler
+ * \see exception_set_exclusive_handler()
+ */
+void exception_restore_handler(enum exception_number, exception_handler_t original_handler);
+
+/*! \brief Get the current exception handler for the specified exception from the currently installed vector table
+ * of the execution core
+ * \ingroup hardware_exception
+ *
+ * \param num Exception number
+ * \return the address stored in the VTABLE for the given exception number
+ */
+exception_handler_t exception_get_vtable_handler(enum exception_number num);
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/rp2_common/hardware_flash/CMakeLists.txt b/src/rp2_common/hardware_flash/CMakeLists.txt
index 1ccab33..9682566 100644
--- a/src/rp2_common/hardware_flash/CMakeLists.txt
+++ b/src/rp2_common/hardware_flash/CMakeLists.txt
@@ -1,8 +1,2 @@
-add_library(hardware_flash INTERFACE)
-
-target_sources(hardware_flash INTERFACE
- ${CMAKE_CURRENT_LIST_DIR}/flash.c
- )
-
-target_include_directories(hardware_flash INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
-target_link_libraries(hardware_flash INTERFACE pico_base_headers pico_bootrom)
+pico_simple_hardware_target(flash)
+target_link_libraries(hardware_flash INTERFACE pico_bootrom)
diff --git a/src/rp2_common/hardware_flash/flash.c b/src/rp2_common/hardware_flash/flash.c
index c397fbb..dc9d833 100644
--- a/src/rp2_common/hardware_flash/flash.c
+++ b/src/rp2_common/hardware_flash/flash.c
@@ -123,9 +123,7 @@
);
}
-// May want to expose this at some point but this is unlikely to be the right
-// interface to do so. Keep it static
-static void __no_inline_not_in_flash_func(flash_do_cmd)(const uint8_t *txbuf, uint8_t *rxbuf, size_t count) {
+void __no_inline_not_in_flash_func(flash_do_cmd)(const uint8_t *txbuf, uint8_t *rxbuf, size_t count) {
void (*connect_internal_flash)(void) = (void(*)(void))rom_func_lookup(rom_table_code('I', 'F'));
void (*flash_exit_xip)(void) = (void(*)(void))rom_func_lookup(rom_table_code('E', 'X'));
void (*flash_flush_cache)(void) = (void(*)(void))rom_func_lookup(rom_table_code('F', 'C'));
diff --git a/src/rp2_common/hardware_flash/include/hardware/flash.h b/src/rp2_common/hardware_flash/include/hardware/flash.h
index d015db4..e6cd229 100644
--- a/src/rp2_common/hardware_flash/include/hardware/flash.h
+++ b/src/rp2_common/hardware_flash/include/hardware/flash.h
@@ -80,6 +80,32 @@
*/
void flash_get_unique_id(uint8_t *id_out);
+/*! \brief Execute bidirectional flash command
+ * \ingroup hardware_flash
+ *
+ * Low-level function to execute a serial command on a flash device attached
+ * to the QSPI interface. Bytes are simultaneously transmitted and received
+ * from txbuf and to rxbuf. Therefore, both buffers must be the same length,
+ * count, which is the length of the overall transaction. This is useful for
+ * reading metadata from the flash chip, such as device ID or SFDP
+ * parameters.
+ *
+ * The XIP cache is flushed following each command, in case flash state
+ * has been modified. Like other hardware_flash functions, the flash is not
+ * accessible for execute-in-place transfers whilst the command is in
+ * progress, so entering a flash-resident interrupt handler or executing flash
+ * code on the second core concurrently will be fatal. To avoid these pitfalls
+ * it is recommended that this function only be used to extract flash metadata
+ * during startup, before the main application begins to run: see the
+ * implementation of pico_get_unique_id() for an example of this.
+ *
+ * \param txbuf Pointer to a byte buffer which will be transmitted to the flash
+ * \param rxbuf Pointer to a byte buffer where data received from the flash will be written. txbuf and rxbuf may be the same buffer.
+ * \param count Length in bytes of txbuf and of rxbuf
+ */
+void flash_do_cmd(const uint8_t *txbuf, uint8_t *rxbuf, size_t count);
+
+
#ifdef __cplusplus
}
#endif
diff --git a/src/rp2_common/hardware_gpio/gpio.c b/src/rp2_common/hardware_gpio/gpio.c
index a9b953b..10b1502 100644
--- a/src/rp2_common/hardware_gpio/gpio.c
+++ b/src/rp2_common/hardware_gpio/gpio.c
@@ -10,7 +10,9 @@
#include "hardware/structs/iobank0.h"
#include "hardware/irq.h"
+#if LIB_PICO_BINARY_INFO
#include "pico/binary_info.h"
+#endif
static gpio_irq_callback_t _callbacks[NUM_CORES];
@@ -55,6 +57,15 @@
);
}
+// Direct override for per-GPIO IRQ signal
+void gpio_set_irqover(uint gpio, uint value) {
+ invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+ hw_write_masked(&iobank0_hw->io[gpio].ctrl,
+ value << IO_BANK0_GPIO0_CTRL_IRQOVER_LSB,
+ IO_BANK0_GPIO0_CTRL_IRQOVER_BITS
+ );
+}
+
// Direct overrides for pad controls
void gpio_set_inover(uint gpio, uint value) {
invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
@@ -80,6 +91,53 @@
);
}
+void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled) {
+ invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+ if (enabled)
+ hw_set_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_SCHMITT_BITS);
+ else
+ hw_clear_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_SCHMITT_BITS);
+}
+
+
+bool gpio_is_input_hysteresis_enabled(uint gpio) {
+ invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+ return (padsbank0_hw->io[gpio] & PADS_BANK0_GPIO0_SCHMITT_BITS) != 0;
+}
+
+void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew) {
+ invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+ hw_write_masked(&padsbank0_hw->io[gpio],
+ (uint)slew << PADS_BANK0_GPIO0_SLEWFAST_LSB,
+ PADS_BANK0_GPIO0_SLEWFAST_BITS
+ );
+}
+
+enum gpio_slew_rate gpio_get_slew_rate(uint gpio) {
+ invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+ return (enum gpio_slew_rate)((padsbank0_hw->io[gpio]
+ & PADS_BANK0_GPIO0_SLEWFAST_BITS)
+ >> PADS_BANK0_GPIO0_SLEWFAST_LSB);
+}
+
+
+// Enum encoding should match hardware encoding on RP2040
+static_assert(PADS_BANK0_GPIO0_DRIVE_VALUE_8MA == GPIO_DRIVE_STRENGTH_8MA, "");
+void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive) {
+ invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+ hw_write_masked(&padsbank0_hw->io[gpio],
+ (uint)drive << PADS_BANK0_GPIO0_DRIVE_LSB,
+ PADS_BANK0_GPIO0_DRIVE_BITS
+ );
+}
+
+enum gpio_drive_strength gpio_get_drive_strength(uint gpio) {
+ invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+ return (enum gpio_drive_strength)((padsbank0_hw->io[gpio]
+ & PADS_BANK0_GPIO0_DRIVE_BITS)
+ >> PADS_BANK0_GPIO0_DRIVE_LSB);
+}
+
static void gpio_irq_handler(void) {
io_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ?
&iobank0_hw->proc1_irq_ctrl : &iobank0_hw->proc0_irq_ctrl;
@@ -141,7 +199,9 @@
void gpio_debug_pins_init() {
gpio_init_mask(DEBUG_PIN_MASK);
gpio_set_dir_masked(DEBUG_PIN_MASK, DEBUG_PIN_MASK);
+#if LIB_PICO_BINARY_INFO
bi_decl_if_func_used(bi_pin_mask_with_names(DEBUG_PIN_MASK, "Debug"));
+#endif
}
void gpio_set_input_enabled(uint gpio, bool enabled) {
diff --git a/src/rp2_common/hardware_gpio/include/hardware/gpio.h b/src/rp2_common/hardware_gpio/include/hardware/gpio.h
index 1a7314c..e90be27 100644
--- a/src/rp2_common/hardware_gpio/include/hardware/gpio.h
+++ b/src/rp2_common/hardware_gpio/include/hardware/gpio.h
@@ -96,7 +96,7 @@
GPIO_FUNC_PIO1 = 7,
GPIO_FUNC_GPCK = 8,
GPIO_FUNC_USB = 9,
- GPIO_FUNC_NULL = 0xf,
+ GPIO_FUNC_NULL = 0x1f,
};
#define GPIO_OUT 1
@@ -140,6 +140,31 @@
GPIO_OVERRIDE_HIGH = 3, ///< drive high/enable output
};
+/*! \brief Slew rate limiting levels for GPIO outputs
+ * \ingroup hardware_gpio
+ *
+ * Slew rate limiting increases the minimum rise/fall time when a GPIO output
+ * is lightly loaded, which can help to reduce electromagnetic emissions.
+ * \sa gpio_set_slew_rate
+ */
+enum gpio_slew_rate {
+ GPIO_SLEW_RATE_SLOW = 0, ///< Slew rate limiting enabled
+ GPIO_SLEW_RATE_FAST = 1 ///< Slew rate limiting disabled
+};
+
+/*! \brief Drive strength levels for GPIO outputs
+ * \ingroup hardware_gpio
+ *
+ * Drive strength levels for GPIO outputs.
+ * \sa gpio_set_drive_strength
+ */
+enum gpio_drive_strength {
+ GPIO_DRIVE_STRENGTH_2MA = 0, ///< 2 mA nominal drive strength
+ GPIO_DRIVE_STRENGTH_4MA = 1, ///< 4 mA nominal drive strength
+ GPIO_DRIVE_STRENGTH_8MA = 2, ///< 8 mA nominal drive strength
+ GPIO_DRIVE_STRENGTH_12MA = 3 ///< 12 mA nominal drive strength
+};
+
// ----------------------------------------------------------------------------
// Pad Controls + IO Muxing
// ----------------------------------------------------------------------------
@@ -214,6 +239,16 @@
gpio_set_pulls(gpio, false, false);
}
+/*! \brief Set GPIO IRQ override
+ * \ingroup hardware_gpio
+ *
+ * Optionally invert a GPIO IRQ signal, or drive it high or low
+ *
+ * \param gpio GPIO number
+ * \param value See \ref gpio_override
+ */
+void gpio_set_irqover(uint gpio, uint value);
+
/*! \brief Set GPIO output override
* \ingroup hardware_gpio
*
@@ -246,6 +281,65 @@
*/
void gpio_set_input_enabled(uint gpio, bool enabled);
+/*! \brief Enable/disable GPIO input hysteresis (Schmitt trigger)
+ * \ingroup hardware_gpio
+ *
+ * Enable or disable the Schmitt trigger hysteresis on a given GPIO. This is
+ * enabled on all GPIOs by default. Disabling input hysteresis can lead to
+ * inconsistent readings when the input signal has very long rise or fall
+ * times, but slightly reduces the GPIO's input delay.
+ *
+ * \sa gpio_is_input_hysteresis_enabled
+ * \param gpio GPIO number
+ * \param enabled true to enable input hysteresis on specified GPIO
+ */
+void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled);
+
+/*! \brief Determine whether input hysteresis is enabled on a specified GPIO
+ * \ingroup hardware_gpio
+ *
+ * \sa gpio_set_input_hysteresis_enabled
+ * \param gpio GPIO number
+ */
+bool gpio_is_input_hysteresis_enabled(uint gpio);
+
+
+/*! \brief Set slew rate for a specified GPIO
+ * \ingroup hardware_gpio
+ *
+ * \sa gpio_get_slew_rate
+ * \param gpio GPIO number
+ * \param slew GPIO output slew rate
+ */
+void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew);
+
+/*! \brief Determine current slew rate for a specified GPIO
+ * \ingroup hardware_gpio
+ *
+ * \sa gpio_set_slew_rate
+ * \param gpio GPIO number
+ * \return Current slew rate of that GPIO
+ */
+enum gpio_slew_rate gpio_get_slew_rate(uint gpio);
+
+/*! \brief Set drive strength for a specified GPIO
+ * \ingroup hardware_gpio
+ *
+ * \sa gpio_get_drive_strength
+ * \param gpio GPIO number
+ * \param drive GPIO output drive strength
+ */
+void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive);
+
+/*! \brief Determine current slew rate for a specified GPIO
+ * \ingroup hardware_gpio
+ *
+ * \sa gpio_set_drive_strength
+ * \param gpio GPIO number
+ * \return Current drive strength of that GPIO
+ */
+enum gpio_drive_strength gpio_get_drive_strength(uint gpio);
+
/*! \brief Enable or disable interrupts for specified GPIO
* \ingroup hardware_gpio
*
@@ -415,6 +509,26 @@
gpio_clr_mask(mask);
}
+/*! \brief Determine whether a GPIO is currently driven high or low
+ * \ingroup hardware_gpio
+ *
+ * This function returns the high/low output level most recently assigned to a
+ * GPIO via gpio_put() or similar. This is the value that is presented outward
+ * to the IO muxing, *not* the input level back from the pad (which can be
+ * read using gpio_get()).
+ *
+ * To avoid races, this function must not be used for read-modify-write
+ * sequences when driving GPIOs -- instead functions like gpio_put() should be
+ * used to atomically update GPIOs. This accessor is intended for debug use
+ * only.
+ *
+ * \param gpio GPIO number
+ * \return true if the GPIO output level is high, false if low.
+ */
+static inline bool gpio_get_out_level(uint gpio) {
+ return !!(sio_hw->gpio_out & (1u << gpio));
+}
+
// ----------------------------------------------------------------------------
// Direction
// ----------------------------------------------------------------------------
diff --git a/src/rp2_common/hardware_i2c/i2c.c b/src/rp2_common/hardware_i2c/i2c.c
index bcd9054..9d2e931 100644
--- a/src/rp2_common/hardware_i2c/i2c.c
+++ b/src/rp2_common/hardware_i2c/i2c.c
@@ -43,7 +43,8 @@
I2C_IC_CON_SPEED_VALUE_FAST << I2C_IC_CON_SPEED_LSB |
I2C_IC_CON_MASTER_MODE_BITS |
I2C_IC_CON_IC_SLAVE_DISABLE_BITS |
- I2C_IC_CON_IC_RESTART_EN_BITS;
+ I2C_IC_CON_IC_RESTART_EN_BITS |
+ I2C_IC_CON_TX_EMPTY_CTRL_BITS;
// Set FIFO watermarks to 1 to make things simpler. This is encoded by a register value of 0.
i2c->hw->tx_tl = 0;
@@ -67,14 +68,32 @@
// TODO there are some subtleties to I2C timing which we are completely ignoring here
uint period = (freq_in + baudrate / 2) / baudrate;
- uint hcnt = period * 3 / 5; // oof this one hurts
- uint lcnt = period - hcnt;
+ uint lcnt = period * 3 / 5; // oof this one hurts
+ uint hcnt = period - lcnt;
// Check for out-of-range divisors:
invalid_params_if(I2C, hcnt > I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_BITS);
invalid_params_if(I2C, lcnt > I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_BITS);
invalid_params_if(I2C, hcnt < 8);
invalid_params_if(I2C, lcnt < 8);
+ // Per I2C-bus specification a device in standard or fast mode must
+ // internally provide a hold time of at least 300ns for the SDA signal to
+ // bridge the undefined region of the falling edge of SCL. A smaller hold
+ // time of 120ns is used for fast mode plus.
+ uint sda_tx_hold_count;
+ if (baudrate < 1000000) {
+ // sda_tx_hold_count = freq_in [cycles/s] * 300ns * (1s / 1e9ns)
+ // Reduce 300/1e9 to 3/1e7 to avoid numbers that don't fit in uint.
+ // Add 1 to avoid division truncation.
+ sda_tx_hold_count = ((freq_in * 3) / 10000000) + 1;
+ } else {
+ // sda_tx_hold_count = freq_in [cycles/s] * 120ns * (1s / 1e9ns)
+ // Reduce 120/1e9 to 3/25e6 to avoid numbers that don't fit in uint.
+ // Add 1 to avoid division truncation.
+ sda_tx_hold_count = ((freq_in * 3) / 25000000) + 1;
+ }
+ assert(sda_tx_hold_count <= lcnt - 2);
+
i2c->hw->enable = 0;
// Always use "fast" mode (<= 400 kHz, works fine for standard mode too)
hw_write_masked(&i2c->hw->con,
@@ -84,6 +103,9 @@
i2c->hw->fs_scl_hcnt = hcnt;
i2c->hw->fs_scl_lcnt = lcnt;
i2c->hw->fs_spklen = lcnt < 16 ? 1 : lcnt / 16;
+ hw_write_masked(&i2c->hw->sda_hold,
+ sda_tx_hold_count << I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_LSB,
+ I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_BITS);
i2c->hw->enable = 1;
return freq_in / period;
@@ -124,7 +146,7 @@
bool abort = false;
bool timeout = false;
- uint32_t abort_reason;
+ uint32_t abort_reason = 0;
int byte_ctr;
int ilen = (int)len;
@@ -137,17 +159,50 @@
bool_to_bit(last && !nostop) << I2C_IC_DATA_CMD_STOP_LSB |
*src++;
+ // Wait until the transmission of the address/data from the internal
+ // shift register has completed. For this to function correctly, the
+ // TX_EMPTY_CTRL flag in IC_CON must be set. The TX_EMPTY_CTRL flag
+ // was set in i2c_init.
do {
- // Note clearing the abort flag also clears the reason, and this
- // instance of flag is clear-on-read!
- abort_reason = i2c->hw->tx_abrt_source;
- abort = (bool) i2c->hw->clr_tx_abrt;
if (timeout_check) {
timeout = timeout_check(ts);
abort |= timeout;
}
tight_loop_contents();
- } while (!abort && !(i2c->hw->status & I2C_IC_STATUS_TFE_BITS));
+ } while (!timeout && !(i2c->hw->raw_intr_stat & I2C_IC_RAW_INTR_STAT_TX_EMPTY_BITS));
+
+ // If there was a timeout, don't attempt to do anything else.
+ if (!timeout) {
+ abort_reason = i2c->hw->tx_abrt_source;
+ if (abort_reason) {
+ // Note clearing the abort flag also clears the reason, and
+ // this instance of flag is clear-on-read! Note also the
+ // IC_CLR_TX_ABRT register always reads as 0.
+ i2c->hw->clr_tx_abrt;
+ abort = true;
+ }
+
+ if (abort || (last && !nostop)) {
+ // If the transaction was aborted or if it completed
+ // successfully wait until the STOP condition has occured.
+
+ // TODO Could there be an abort while waiting for the STOP
+ // condition here? If so, additional code would be needed here
+ // to take care of the abort.
+ do {
+ if (timeout_check) {
+ timeout = timeout_check(ts);
+ abort |= timeout;
+ }
+ tight_loop_contents();
+ } while (!timeout && !(i2c->hw->raw_intr_stat & I2C_IC_RAW_INTR_STAT_STOP_DET_BITS));
+
+ // If there was a timeout, don't attempt to do anything else.
+ if (!timeout) {
+ i2c->hw->clr_stop_det;
+ }
+ }
+ }
// Note the hardware issues a STOP automatically on an abort condition.
// Note also the hardware clears RX FIFO as well as TX on abort,
diff --git a/src/rp2_common/hardware_i2c/include/hardware/i2c.h b/src/rp2_common/hardware_i2c/include/hardware/i2c.h
index c049937..5cce6f8 100644
--- a/src/rp2_common/hardware_i2c/include/hardware/i2c.h
+++ b/src/rp2_common/hardware_i2c/include/hardware/i2c.h
@@ -257,7 +257,7 @@
* least that many bytes can be written without blocking.
*/
static inline size_t i2c_get_write_available(i2c_inst_t *i2c) {
- const size_t IC_TX_BUFFER_DEPTH = 32;
+ const size_t IC_TX_BUFFER_DEPTH = 16;
return IC_TX_BUFFER_DEPTH - i2c_get_hw(i2c)->txflr;
}
diff --git a/src/rp2_common/hardware_interp/include/hardware/interp.h b/src/rp2_common/hardware_interp/include/hardware/interp.h
index 5f5014b..35372e9 100644
--- a/src/rp2_common/hardware_interp/include/hardware/interp.h
+++ b/src/rp2_common/hardware_interp/include/hardware/interp.h
@@ -55,7 +55,7 @@
} interp_config;
static inline uint interp_index(interp_hw_t *interp) {
- assert(interp == interp0 || interp == interp1);
+ valid_params_if(INTERP, interp == interp0 || interp == interp1);
return interp == interp1 ? 1 : 0;
}
@@ -70,6 +70,8 @@
* \param lane The lane number, 0 or 1.
*/
void interp_claim_lane(interp_hw_t *interp, uint lane);
+// The above really should be called this for consistency
+#define interp_lane_claim interp_claim_lane
/*! \brief Claim the interpolator lanes specified in the mask
* \ingroup hardware_interp
@@ -86,6 +88,27 @@
* \param lane The lane number, 0 or 1
*/
void interp_unclaim_lane(interp_hw_t *interp, uint lane);
+// The above really should be called this for consistency
+#define interp_lane_unclaim interp_unclaim_lane
+
+/*! \brief Determine if an interpolator lane is claimed
+ * \ingroup hardware_interp
+ *
+ * \param interp Interpolator whose lane to check
+ * \param lane The lane number, 0 or 1
+ * \return true if claimed, false otherwise
+ * \see interp_claim_lane
+ * \see interp_claim_lane_mask
+ */
+bool interp_lane_is_claimed(interp_hw_t *interp, uint lane);
+
+/*! \brief Release previously claimed interpolator lanes \see interp_claim_lane_mask
+ * \ingroup hardware_interp
+ *
+ * \param interp Interpolator on which to release lanes. interp0 or interp1
+ * \param lane_mask Bit pattern of lanes to unclaim (only bits 0 and 1 are valid)
+ */
+void interp_unclaim_lane_mask(interp_hw_t *interp, uint lane_mask);
/*! \brief Set the interpolator shift value
* \ingroup interp_config
@@ -277,9 +300,9 @@
}
typedef struct {
- io_rw_32 accum[2];
- io_rw_32 base[3];
- io_rw_32 ctrl[2];
+ uint32_t accum[2];
+ uint32_t base[3];
+ uint32_t ctrl[2];
} interp_hw_save_t;
/*! \brief Save the specified interpolator state
diff --git a/src/rp2_common/hardware_interp/interp.c b/src/rp2_common/hardware_interp/interp.c
index 5fdad93..37e8a91 100644
--- a/src/rp2_common/hardware_interp/interp.c
+++ b/src/rp2_common/hardware_interp/interp.c
@@ -16,10 +16,13 @@
static uint8_t _claimed;
+static inline uint interp_lane_bit(interp_hw_t * interp, uint lane) {
+ return (interp_index(interp) << 1u) | lane;
+}
+
void interp_claim_lane(interp_hw_t *interp, uint lane) {
valid_params_if(INTERP, lane < 2);
- uint bit = (interp_index(interp) << 1u) | lane;
- hw_claim_or_assert((uint8_t *) &_claimed, bit, "Lane is already claimed");
+ hw_claim_or_assert((uint8_t *) &_claimed, interp_lane_bit(interp, lane), "Lane is already claimed");
}
void interp_claim_lane_mask(interp_hw_t *interp, uint lane_mask) {
@@ -30,8 +33,18 @@
void interp_unclaim_lane(interp_hw_t *interp, uint lane) {
valid_params_if(INTERP, lane < 2);
- uint bit = (interp_index(interp) << 1u) | lane;
- hw_claim_clear((uint8_t *) &_claimed, bit);
+ hw_claim_clear((uint8_t *) &_claimed, interp_lane_bit(interp, lane));
+}
+
+bool interp_lane_is_claimed(interp_hw_t *interp, uint lane) {
+ valid_params_if(INTERP, lane < 2);
+ return hw_is_claimed((uint8_t *) &_claimed, interp_lane_bit(interp, lane));
+}
+
+void interp_unclaim_lane_mask(interp_hw_t *interp, uint lane_mask) {
+ valid_params_if(INTERP, lane_mask <= 0x3);
+ if (lane_mask & 1u) interp_unclaim_lane(interp, 0);
+ if (lane_mask & 2u) interp_unclaim_lane(interp, 1);
}
void interp_save(interp_hw_t *interp, interp_hw_save_t *saver) {
diff --git a/src/rp2_common/hardware_irq/include/hardware/irq.h b/src/rp2_common/hardware_irq/include/hardware/irq.h
index ffdc6db..d82ad54 100644
--- a/src/rp2_common/hardware_irq/include/hardware/irq.h
+++ b/src/rp2_common/hardware_irq/include/hardware/irq.h
@@ -95,8 +95,8 @@
#define PICO_DEFAULT_IRQ_PRIORITY 0x80
#endif
-#define PICO_LOWEST_IRQ_PRIORITY 0x01
-#define PICO_HIGHEST_IRQ_PRIORITY 0xff
+#define PICO_LOWEST_IRQ_PRIORITY 0xff
+#define PICO_HIGHEST_IRQ_PRIORITY 0x00
// PICO_CONFIG: PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY, Set default shared IRQ order priority, default=0x80, group=hardware_irq
#ifndef PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY
@@ -123,9 +123,12 @@
* \ingroup hardware_irq
*
* \param num Interrupt number
- * \param hardware_priority Priority to set. Hardware priorities range from 0 (lowest) to 255 (highest) though only
- * the top 2 bits are significant on ARM Cortex M0+. To make it easier to specify higher or lower priorities
- * than the default, all IRQ priorities are initialized to PICO_DEFAULT_IRQ_PRIORITY by the SDK runtime at startup.
+ * \param hardware_priority Priority to set.
+ * Numerically-lower values indicate a higher priority. Hardware priorities
+ * range from 0 (highest priority) to 255 (lowest priority) though only the
+ * top 2 bits are significant on ARM Cortex-M0+. To make it easier to specify
+ * higher or lower priorities than the default, all IRQ priorities are
+ * initialized to PICO_DEFAULT_IRQ_PRIORITY by the SDK runtime at startup.
* PICO_DEFAULT_IRQ_PRIORITY defaults to 0x80
*/
void irq_set_priority(uint num, uint8_t hardware_priority);
@@ -252,7 +255,7 @@
void irq_set_pending(uint num);
-/*! \brief Perform IRQ priority intiialization for the current core
+/*! \brief Perform IRQ priority initialization for the current core
*
* \note This is an internal method and user should generally not call it.
*/
diff --git a/src/rp2_common/hardware_pio/include/hardware/pio.h b/src/rp2_common/hardware_pio/include/hardware/pio.h
index 1fc00f1..07d0669 100644
--- a/src/rp2_common/hardware_pio/include/hardware/pio.h
+++ b/src/rp2_common/hardware_pio/include/hardware/pio.h
@@ -111,6 +111,11 @@
valid_params_if(PIO, sm < NUM_PIO_STATE_MACHINES);
}
+static inline void check_sm_mask(__unused uint mask) {
+ valid_params_if(PIO, mask < (1u << NUM_PIO_STATE_MACHINES));
+}
+
+
static inline void check_pio_param(__unused PIO pio) {
valid_params_if(PIO, pio == pio0 || pio == pio1);
}
@@ -267,7 +272,7 @@
* \ingroup sm_config
*
* \param c Pointer to the configuration structure to modify
- * \param pin The raw GPIO pin number to use as the source for a `jmp pin` instruction
+ * \param pin The raw GPIO pin number to use as the source for a `jmp pin` instruction
*/
static inline void sm_config_set_jmp_pin(pio_sm_config *c, uint pin) {
valid_params_if(PIO, pin < 32);
@@ -281,7 +286,7 @@
* \param c Pointer to the configuration structure to modify
* \param shift_right true to shift ISR to right, false to shift ISR to left
* \param autopush whether autopush is enabled
- * \param push_threshold threshold in bits to shift in before auto/conditional re-pushing of the ISR
+ * \param push_threshold threshold in bits to shift in before auto/conditional re-pushing of the ISR
*/
static inline void sm_config_set_in_shift(pio_sm_config *c, bool shift_right, bool autopush, uint push_threshold) {
valid_params_if(PIO, push_threshold <= 32);
@@ -300,7 +305,7 @@
* \param c Pointer to the configuration structure to modify
* \param shift_right true to shift OSR to right, false to shift OSR to left
* \param autopull whether autopull is enabled
- * \param pull_threshold threshold in bits to shift out before auto/conditional re-pulling of the OSR
+ * \param pull_threshold threshold in bits to shift out before auto/conditional re-pulling of the OSR
*/
static inline void sm_config_set_out_shift(pio_sm_config *c, bool shift_right, bool autopull, uint pull_threshold) {
valid_params_if(PIO, pull_threshold <= 32);
@@ -330,7 +335,7 @@
*
* \param c Pointer to the configuration structure to modify
* \param sticky to enable 'sticky' output (i.e. re-asserting most recent OUT/SET pin values on subsequent cycles)
- * \param has_enable_pin true to enable auxiliary OUT enable pin
+ * \param has_enable_pin true to enable auxiliary OUT enable pin
* \param enable_pin_index pin index for auxiliary OUT enable
*/
static inline void sm_config_set_out_special(pio_sm_config *c, bool sticky, bool has_enable_pin, uint enable_pin_index) {
@@ -352,7 +357,7 @@
static inline void sm_config_set_mov_status(pio_sm_config *c, enum pio_mov_status_type status_sel, uint status_n) {
valid_params_if(PIO, status_sel == STATUS_TX_LESSTHAN || status_sel == STATUS_RX_LESSTHAN);
c->execctrl = (c->execctrl
- & ~(PIO_SM0_EXECCTRL_STATUS_SEL_BITS | PIO_SM0_EXECCTRL_STATUS_N_BITS))
+ & ~(PIO_SM0_EXECCTRL_STATUS_SEL_BITS | PIO_SM0_EXECCTRL_STATUS_N_BITS))
| ((((uint)status_sel) << PIO_SM0_EXECCTRL_STATUS_SEL_LSB) & PIO_SM0_EXECCTRL_STATUS_SEL_BITS)
| ((status_n << PIO_SM0_EXECCTRL_STATUS_N_LSB) & PIO_SM0_EXECCTRL_STATUS_N_BITS);
}
@@ -372,7 +377,7 @@
* In Shift | shift_direction=right, autopush=false, push_thrshold=32
* Out Shift | shift_direction=right, autopull=false, pull_thrshold=32
* Jmp Pin | 0
- * Out Special | sticky=false, has_enable_pin=false, enable_pin_index=0
+ * Out Special | sticky=false, has_enable_pin=false, enable_pin_index=0
* Mov Status | status_sel=STATUS_TX_LESSTHAN, n=0
*
* \return the default state machine configuration which can then be modified.
@@ -413,7 +418,7 @@
return pio == pio1 ? 1 : 0;
}
-/*! \brief Setup the function select for a GPIO to use output from the given PIO instance
+/*! \brief Setup the function select for a GPIO to use output from the given PIO instance
* \ingroup hardware_pio
*
* PIO appears as an alternate function in the GPIO muxing, just like an SPI
@@ -554,6 +559,7 @@
*/
static inline void pio_set_sm_mask_enabled(PIO pio, uint32_t mask, bool enabled) {
check_pio_param(pio);
+ check_sm_mask(mask);
pio->ctrl = (pio->ctrl & ~mask) | (enabled ? mask : 0u);
}
@@ -583,6 +589,7 @@
*/
static inline void pio_restart_sm_mask(PIO pio, uint32_t mask) {
check_pio_param(pio);
+ check_sm_mask(mask);
pio->ctrl |= (mask << PIO_CTRL_SM_RESTART_LSB) & PIO_CTRL_SM_RESTART_BITS;
}
@@ -644,6 +651,7 @@
*/
static inline void pio_clkdiv_restart_sm_mask(PIO pio, uint32_t mask) {
check_pio_param(pio);
+ check_sm_mask(mask);
pio->ctrl |= (mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS;
}
@@ -660,10 +668,154 @@
*/
static inline void pio_enable_sm_mask_in_sync(PIO pio, uint32_t mask) {
check_pio_param(pio);
+ check_sm_mask(mask);
pio->ctrl |= ((mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS) |
((mask << PIO_CTRL_SM_ENABLE_LSB) & PIO_CTRL_SM_ENABLE_BITS);
}
+/*! \brief PIO interrupt source numbers for pio related IRQs
+ * \ingroup hardware_pio
+ */
+enum pio_interrupt_source {
+ pis_interrupt0 = PIO_INTR_SM0_LSB,
+ pis_interrupt1 = PIO_INTR_SM1_LSB,
+ pis_interrupt2 = PIO_INTR_SM2_LSB,
+ pis_interrupt3 = PIO_INTR_SM3_LSB,
+ pis_sm0_tx_fifo_not_full = PIO_INTR_SM0_TXNFULL_LSB,
+ pis_sm1_tx_fifo_not_full = PIO_INTR_SM1_TXNFULL_LSB,
+ pis_sm2_tx_fifo_not_full = PIO_INTR_SM2_TXNFULL_LSB,
+ pis_sm3_tx_fifo_not_full = PIO_INTR_SM3_TXNFULL_LSB,
+ pis_sm0_rx_fifo_not_empty = PIO_INTR_SM0_RXNEMPTY_LSB,
+ pis_sm1_rx_fifo_not_empty = PIO_INTR_SM1_RXNEMPTY_LSB,
+ pis_sm2_rx_fifo_not_empty = PIO_INTR_SM2_RXNEMPTY_LSB,
+ pis_sm3_rx_fifo_not_empty = PIO_INTR_SM3_RXNEMPTY_LSB,
+};
+
+/*! \brief Enable/Disable a single source on a PIO's IRQ 0
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param source the source number (see \ref pio_interrupt_source)
+ * \param enabled true to enable IRQ 0 for the source, false to disable.
+ */
+static inline void pio_set_irq0_source_enabled(PIO pio, enum pio_interrupt_source source, bool enabled) {
+ check_pio_param(pio);
+ invalid_params_if(PIO, source >= 12);
+ if (enabled)
+ hw_set_bits(&pio->inte0, 1u << source);
+ else
+ hw_clear_bits(&pio->inte0, 1u << source);
+}
+
+/*! \brief Enable/Disable a single source on a PIO's IRQ 1
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param source the source number (see \ref pio_interrupt_source)
+ * \param enabled true to enable IRQ 0 for the source, false to disable.
+ */
+static inline void pio_set_irq1_source_enabled(PIO pio, enum pio_interrupt_source source, bool enabled) {
+ check_pio_param(pio);
+ invalid_params_if(PIO, source >= 12);
+ if (enabled)
+ hw_set_bits(&pio->inte1, 1u << source);
+ else
+ hw_clear_bits(&pio->inte1, 1u << source);
+}
+
+/*! \brief Enable/Disable multiple sources on a PIO's IRQ 0
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param source_mask Mask of bits, one for each source number (see \ref pio_interrupt_source) to affect
+ * \param enabled true to enable all the sources specified in the mask on IRQ 0, false to disable all the sources specified in the mask on IRQ 0
+ */
+static inline void pio_set_irq0_source_mask_enabled(PIO pio, uint32_t source_mask, bool enabled) {
+ check_pio_param(pio);
+ invalid_params_if(PIO, source_mask > PIO_INTR_BITS);
+ if (enabled) {
+ hw_set_bits(&pio->inte0, source_mask);
+ } else {
+ hw_clear_bits(&pio->inte0, source_mask);
+ }
+}
+
+/*! \brief Enable/Disable multiple sources on a PIO's IRQ 1
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param source_mask Mask of bits, one for each source number (see \ref pio_interrupt_source) to affect
+ * \param enabled true to enable all the sources specified in the mask on IRQ 1, false to disable all the source specified in the mask on IRQ 1
+ */
+static inline void pio_set_irq1_source_mask_enabled(PIO pio, uint32_t source_mask, bool enabled) {
+ check_pio_param(pio);
+ invalid_params_if(PIO, source_mask > PIO_INTR_BITS);
+ if (enabled) {
+ hw_set_bits(&pio->inte1, source_mask);
+ } else {
+ hw_clear_bits(&pio->inte1, source_mask);
+ }
+}
+
+/*! \brief Enable/Disable a single source on a PIO's specified (0/1) IRQ index
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param irq_index the IRQ index; either 0 or 1
+ * \param source the source number (see \ref pio_interrupt_source)
+ * \param enabled true to enable the source on the specified IRQ, false to disable.
+ */
+static inline void pio_set_irqn_source_enabled(PIO pio, uint irq_index, enum pio_interrupt_source source, bool enabled) {
+ invalid_params_if(PIO, irq_index > 1);
+ if (irq_index) {
+ pio_set_irq1_source_enabled(pio, source, enabled);
+ } else {
+ pio_set_irq0_source_enabled(pio, source, enabled);
+ }
+}
+
+/*! \brief Enable/Disable multiple sources on a PIO's specified (0/1) IRQ index
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param irq_index the IRQ index; either 0 or 1
+ * \param source_mask Mask of bits, one for each source number (see \ref pio_interrupt_source) to affect
+ * \param enabled true to enable all the sources specified in the mask on the specified IRQ, false to disable all the sources specified in the mask on the specified IRQ
+ */
+static inline void pio_set_irqn_source_mask_enabled(PIO pio, uint irq_index, uint32_t source_mask, bool enabled) {
+ invalid_params_if(PIO, irq_index > 1);
+ if (irq_index) {
+ pio_set_irq0_source_mask_enabled(pio, source_mask, enabled);
+ } else {
+ pio_set_irq1_source_mask_enabled(pio, source_mask, enabled);
+ }
+}
+
+/*! \brief Determine if a particular PIO interrupt is set
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param pio_interrupt_num the PIO interrupt number 0-7
+ * \return true if corresponding PIO interrupt is currently set
+ */
+static inline bool pio_interrupt_get(PIO pio, uint pio_interrupt_num) {
+ check_pio_param(pio);
+ invalid_params_if(PIO, pio_interrupt_num >= 8);
+ return pio->irq & (1u << pio_interrupt_num);
+}
+
+/*! \brief Clear a particular PIO interrupt
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param pio_interrupt_num the PIO interrupt number 0-7
+ */
+static inline void pio_interrupt_clear(PIO pio, uint pio_interrupt_num) {
+ check_pio_param(pio);
+ invalid_params_if(PIO, pio_interrupt_num >= 8);
+ hw_set_bits(&pio->irq, (1u << pio_interrupt_num));
+}
+
/*! \brief Return the current program counter for a state machine
* \ingroup hardware_pio
*
@@ -1136,6 +1288,17 @@
*/
int pio_claim_unused_sm(PIO pio, bool required);
+/*! \brief Determine if a PIO state machine is claimed
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \return true if claimed, false otherwise
+ * \see pio_sm_claim
+ * \see pio_claim_sm_mask
+ */
+bool pio_sm_is_claimed(PIO pio, uint sm);
+
#ifdef __cplusplus
}
#endif
diff --git a/src/rp2_common/hardware_pio/include/hardware/pio_instructions.h b/src/rp2_common/hardware_pio/include/hardware/pio_instructions.h
index f7ed52a..07df65b 100644
--- a/src/rp2_common/hardware_pio/include/hardware/pio_instructions.h
+++ b/src/rp2_common/hardware_pio/include/hardware/pio_instructions.h
@@ -80,19 +80,20 @@
}
inline static uint pio_encode_delay(uint cycles) {
+ // note that the maximum cycles will be smaller if sideset_bit_count > 0
valid_params_if(PIO_INSTRUCTIONS, cycles <= 0x1f);
return cycles << 8u;
}
inline static uint pio_encode_sideset(uint sideset_bit_count, uint value) {
valid_params_if(PIO_INSTRUCTIONS, sideset_bit_count >= 1 && sideset_bit_count <= 5);
- valid_params_if(PIO_INSTRUCTIONS, value <= (0x1fu >> sideset_bit_count));
+ valid_params_if(PIO_INSTRUCTIONS, value <= ((1u << sideset_bit_count) - 1));
return value << (13u - sideset_bit_count);
}
inline static uint pio_encode_sideset_opt(uint sideset_bit_count, uint value) {
- valid_params_if(PIO_INSTRUCTIONS, sideset_bit_count >= 2 && sideset_bit_count <= 5);
- valid_params_if(PIO_INSTRUCTIONS, value <= (0x1fu >> sideset_bit_count));
+ valid_params_if(PIO_INSTRUCTIONS, sideset_bit_count >= 1 && sideset_bit_count <= 4);
+ valid_params_if(PIO_INSTRUCTIONS, value <= ((1u << sideset_bit_count) - 1));
return 0x1000u | value << (12u - sideset_bit_count);
}
diff --git a/src/rp2_common/hardware_pio/pio.c b/src/rp2_common/hardware_pio/pio.c
index 7a94111..0744110 100644
--- a/src/rp2_common/hardware_pio/pio.c
+++ b/src/rp2_common/hardware_pio/pio.c
@@ -35,6 +35,7 @@
if (sm_mask & 1u) pio_sm_claim(pio, i);
}
}
+
void pio_sm_unclaim(PIO pio, uint sm) {
check_sm_param(sm);
uint which = pio_get_index(pio);
@@ -50,11 +51,17 @@
return index >= (int)base ? index - (int)base : -1;
}
+bool pio_sm_is_claimed(PIO pio, uint sm) {
+ check_sm_param(sm);
+ uint which = pio_get_index(pio);
+ return hw_is_claimed(&claimed, which * NUM_PIO_STATE_MACHINES + sm);
+}
+
static_assert(PIO_INSTRUCTION_COUNT <= 32, "");
static uint32_t _used_instruction_space[2];
static int _pio_find_offset_for_program(PIO pio, const pio_program_t *program) {
- assert(program->length < PIO_INSTRUCTION_COUNT);
+ assert(program->length <= PIO_INSTRUCTION_COUNT);
uint32_t used_mask = _used_instruction_space[pio_get_index(pio)];
uint32_t program_mask = (1u << program->length) - 1;
if (program->origin >= 0) {
diff --git a/src/rp2_common/hardware_pll/pll.c b/src/rp2_common/hardware_pll/pll.c
index 4daeb51..6cc6184 100644
--- a/src/rp2_common/hardware_pll/pll.c
+++ b/src/rp2_common/hardware_pll/pll.c
@@ -7,15 +7,11 @@
// For MHZ definitions etc
#include "hardware/clocks.h"
#include "hardware/pll.h"
+#include "hardware/resets.h"
/// \tag::pll_init_calculations[]
void pll_init(PLL pll, uint refdiv, uint vco_freq, uint post_div1, uint post_div2) {
- // Turn off PLL in case it is already running
- pll->pwr = 0xffffffff;
- pll->fbdiv_int = 0;
-
uint32_t ref_mhz = XOSC_MHZ / refdiv;
- pll->cs = refdiv;
// What are we multiplying the reference clock by to get the vco freq
// (The regs are called div, because you divide the vco output and compare it to the refclk)
@@ -34,11 +30,28 @@
// than postdiv2
assert(post_div2 <= post_div1);
-/// \tag::pll_init_finish[]
// Check that reference frequency is no greater than vco / 16
assert(ref_mhz <= (vco_freq / 16));
- // Put calculated value into feedback divider
+ // div1 feeds into div2 so if div1 is 5 and div2 is 2 then you get a divide by 10
+ uint32_t pdiv = (post_div1 << PLL_PRIM_POSTDIV1_LSB) |
+ (post_div2 << PLL_PRIM_POSTDIV2_LSB);
+
+/// \tag::pll_init_finish[]
+ if ((pll->cs & PLL_CS_LOCK_BITS) &&
+ (refdiv == (pll->cs & PLL_CS_REFDIV_BITS)) &&
+ (fbdiv == (pll->fbdiv_int & PLL_FBDIV_INT_BITS)) &&
+ (pdiv == (pll->prim & (PLL_PRIM_POSTDIV1_BITS & PLL_PRIM_POSTDIV2_BITS)))) {
+ // do not disrupt PLL that is already correctly configured and operating
+ return;
+ }
+
+ uint32_t pll_reset = (pll_usb_hw == pll) ? RESETS_RESET_PLL_USB_BITS : RESETS_RESET_PLL_SYS_BITS;
+ reset_block(pll_reset);
+ unreset_block_wait(pll_reset);
+
+ // Load VCO-related dividers before starting VCO
+ pll->cs = refdiv;
pll->fbdiv_int = fbdiv;
// Turn on PLL
@@ -50,9 +63,7 @@
// Wait for PLL to lock
while (!(pll->cs & PLL_CS_LOCK_BITS)) tight_loop_contents();
- // Set up post dividers - div1 feeds into div2 so if div1 is 5 and div2 is 2 then you get a divide by 10
- uint32_t pdiv = (post_div1 << PLL_PRIM_POSTDIV1_LSB) |
- (post_div2 << PLL_PRIM_POSTDIV2_LSB);
+ // Set up post dividers
pll->prim = pdiv;
// Turn on post divider
@@ -63,4 +74,4 @@
void pll_deinit(PLL pll) {
// todo: Make sure there are no sources running from this pll?
pll->pwr = PLL_PWR_BITS;
-}
\ No newline at end of file
+}
diff --git a/src/rp2_common/hardware_pwm/include/hardware/pwm.h b/src/rp2_common/hardware_pwm/include/hardware/pwm.h
index e071b72..ed696e7 100644
--- a/src/rp2_common/hardware_pwm/include/hardware/pwm.h
+++ b/src/rp2_common/hardware_pwm/include/hardware/pwm.h
@@ -14,7 +14,7 @@
extern "C" {
#endif
-// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PWM, Enable/disable assertions in the PWM module, type=bool, default=0, group=hadrware_pwm
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PWM, Enable/disable assertions in the PWM module, type=bool, default=0, group=hardware_pwm
#ifndef PARAM_ASSERTIONS_ENABLED_PWM
#define PARAM_ASSERTIONS_ENABLED_PWM 0
#endif
diff --git a/src/rp2_common/hardware_resets/CMakeLists.txt b/src/rp2_common/hardware_resets/CMakeLists.txt
index 0b31457..e0712e7 100644
--- a/src/rp2_common/hardware_resets/CMakeLists.txt
+++ b/src/rp2_common/hardware_resets/CMakeLists.txt
@@ -1,2 +1 @@
-add_library(hardware_resets INTERFACE)
-target_include_directories(hardware_resets INTERFACE include)
\ No newline at end of file
+pico_simple_hardware_headers_only_target(resets)
diff --git a/src/rp2_common/hardware_spi/include/hardware/spi.h b/src/rp2_common/hardware_spi/include/hardware/spi.h
index 595a922..b766f74 100644
--- a/src/rp2_common/hardware_spi/include/hardware/spi.h
+++ b/src/rp2_common/hardware_spi/include/hardware/spi.h
@@ -102,14 +102,14 @@
* Puts the SPI into a known state, and enable it. Must be called before other
* functions.
*
- * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
- * \param baudrate Baudrate required in Hz
+ * \note There is no guarantee that the baudrate requested can be achieved exactly; the nearest will be chosen
+ * and returned
*
- * \note There is no guarantee that the baudrate requested will be possible, the nearest will be chosen,
- * and this function does not return any indication of this. You can use the \ref spi_set_baudrate function
- * which will return the actual baudrate selected if this is important.
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \param baudrate Baudrate requested in Hz
+ * \return the actual baud rate set
*/
-void spi_init(spi_inst_t *spi, uint baudrate);
+uint spi_init(spi_inst_t *spi, uint baudrate);
/*! \brief Deinitialise SPI instances
* \ingroup hardware_spi
@@ -132,13 +132,23 @@
*/
uint spi_set_baudrate(spi_inst_t *spi, uint baudrate);
+/*! \brief Get SPI baudrate
+ * \ingroup hardware_spi
+ *
+ * Get SPI baudrate which was set by \see spi_set_baudrate
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \return The actual baudrate set
+ */
+uint spi_get_baudrate(const spi_inst_t *spi);
+
/*! \brief Convert SPI instance to hardware instance number
* \ingroup hardware_spi
*
* \param spi SPI instance
* \return Number of SPI, 0 or 1.
*/
-static inline uint spi_get_index(spi_inst_t *spi) {
+static inline uint spi_get_index(const spi_inst_t *spi) {
invalid_params_if(SPI, spi != spi0 && spi != spi1);
return spi == spi1 ? 1 : 0;
}
@@ -148,6 +158,11 @@
return (spi_hw_t *)spi;
}
+static inline const spi_hw_t *spi_get_const_hw(const spi_inst_t *spi) {
+ spi_get_index(spi); // check it is a hw spi
+ return (const spi_hw_t *)spi;
+}
+
/*! \brief Configure SPI
* \ingroup hardware_spi
*
@@ -197,27 +212,30 @@
* \ingroup hardware_spi
*
* \param spi SPI instance specifier, either \ref spi0 or \ref spi1
- * \return 0 if no space is available to write. Non-zero if a write is possible
- *
- * \note Although the controllers each have a 8 deep TX FIFO, the current HW implementation can only return 0 or 1
- * rather than the space available.
+ * \return false if no space is available to write. True if a write is possible
*/
-static inline size_t spi_is_writable(spi_inst_t *spi) {
- // PL022 doesn't expose levels directly, so return values are only 0 or 1
- return (spi_get_hw(spi)->sr & SPI_SSPSR_TNF_BITS) >> SPI_SSPSR_TNF_LSB;
+static inline bool spi_is_writable(const spi_inst_t *spi) {
+ return (spi_get_const_hw(spi)->sr & SPI_SSPSR_TNF_BITS);
}
/*! \brief Check whether a read can be done on SPI device
* \ingroup hardware_spi
*
* \param spi SPI instance specifier, either \ref spi0 or \ref spi1
- * \return Non-zero if a read is possible i.e. data is present
- *
- * \note Although the controllers each have a 8 deep RX FIFO, the current HW implementation can only return 0 or 1
- * rather than the data available.
+ * \return true if a read is possible i.e. data is present
*/
-static inline size_t spi_is_readable(spi_inst_t *spi) {
- return (spi_get_hw(spi)->sr & SPI_SSPSR_RNE_BITS) >> SPI_SSPSR_RNE_LSB;
+static inline bool spi_is_readable(const spi_inst_t *spi) {
+ return (spi_get_const_hw(spi)->sr & SPI_SSPSR_RNE_BITS);
+}
+
+/*! \brief Check whether SPI is busy
+ * \ingroup hardware_spi
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \return true if SPI is busy
+ */
+static inline bool spi_is_busy(const spi_inst_t *spi) {
+ return (spi_get_const_hw(spi)->sr & SPI_SSPSR_BSY_BITS);
}
/*! \brief Write/Read to/from an SPI device
diff --git a/src/rp2_common/hardware_spi/spi.c b/src/rp2_common/hardware_spi/spi.c
index 175d199..880b534 100644
--- a/src/rp2_common/hardware_spi/spi.c
+++ b/src/rp2_common/hardware_spi/spi.c
@@ -18,18 +18,18 @@
unreset_block_wait(spi == spi0 ? RESETS_RESET_SPI0_BITS : RESETS_RESET_SPI1_BITS);
}
-void spi_init(spi_inst_t *spi, uint baudrate) {
+uint spi_init(spi_inst_t *spi, uint baudrate) {
spi_reset(spi);
spi_unreset(spi);
- (void) spi_set_baudrate(spi, baudrate);
+ uint baud = spi_set_baudrate(spi, baudrate);
spi_set_format(spi, 8, SPI_CPOL_0, SPI_CPHA_0, SPI_MSB_FIRST);
// Always enable DREQ signals -- harmless if DMA is not listening
hw_set_bits(&spi_get_hw(spi)->dmacr, SPI_SSPDMACR_TXDMAE_BITS | SPI_SSPDMACR_RXDMAE_BITS);
- spi_set_format(spi, 8, SPI_CPOL_0, SPI_CPHA_0, SPI_MSB_FIRST);
// Finally enable the SPI
hw_set_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_SSE_BITS);
+ return baud;
}
void spi_deinit(spi_inst_t *spi) {
@@ -65,6 +65,12 @@
return freq_in / (prescale * postdiv);
}
+uint spi_get_baudrate(const spi_inst_t *spi) {
+ uint prescale = spi_get_const_hw(spi)->cpsr;
+ uint postdiv = ((spi_get_const_hw(spi)->cr0 & SPI_SSPCR0_SCR_BITS) >> SPI_SSPCR0_SCR_LSB) + 1;
+ return clock_get_hz(clk_peri) / (prescale * postdiv);
+}
+
// Write len bytes from src to SPI. Simultaneously read len bytes from SPI to dst.
// Note this function is guaranteed to exit in a known amount of time (bits sent * time per bit)
int __not_in_flash_func(spi_write_read_blocking)(spi_inst_t *spi, const uint8_t *src, uint8_t *dst, size_t len) {
@@ -76,7 +82,7 @@
size_t rx_remaining = len, tx_remaining = len;
while (rx_remaining || tx_remaining) {
- if (tx_remaining && spi_is_writable(spi) && rx_remaining - tx_remaining < fifo_depth) {
+ if (tx_remaining && spi_is_writable(spi) && rx_remaining < tx_remaining + fifo_depth) {
spi_get_hw(spi)->dr = (uint32_t) *src++;
--tx_remaining;
}
@@ -125,7 +131,7 @@
size_t rx_remaining = len, tx_remaining = len;
while (rx_remaining || tx_remaining) {
- if (tx_remaining && spi_is_writable(spi) && rx_remaining - tx_remaining < fifo_depth) {
+ if (tx_remaining && spi_is_writable(spi) && rx_remaining < tx_remaining + fifo_depth) {
spi_get_hw(spi)->dr = (uint32_t) repeated_tx_data;
--tx_remaining;
}
@@ -147,7 +153,7 @@
size_t rx_remaining = len, tx_remaining = len;
while (rx_remaining || tx_remaining) {
- if (tx_remaining && spi_is_writable(spi) && rx_remaining - tx_remaining < fifo_depth) {
+ if (tx_remaining && spi_is_writable(spi) && rx_remaining < tx_remaining + fifo_depth) {
spi_get_hw(spi)->dr = (uint32_t) *src++;
--tx_remaining;
}
@@ -192,7 +198,7 @@
size_t rx_remaining = len, tx_remaining = len;
while (rx_remaining || tx_remaining) {
- if (tx_remaining && spi_is_writable(spi) && rx_remaining - tx_remaining < fifo_depth) {
+ if (tx_remaining && spi_is_writable(spi) && rx_remaining < tx_remaining + fifo_depth) {
spi_get_hw(spi)->dr = (uint32_t) repeated_tx_data;
--tx_remaining;
}
diff --git a/src/rp2_common/hardware_sync/include/hardware/sync.h b/src/rp2_common/hardware_sync/include/hardware/sync.h
index b206346..8f91d55 100644
--- a/src/rp2_common/hardware_sync/include/hardware/sync.h
+++ b/src/rp2_common/hardware_sync/include/hardware/sync.h
@@ -18,15 +18,31 @@
/** \file hardware/sync.h
* \defgroup hardware_sync hardware_sync
*
- * Low level hardware spin-lock, barrier and processor event API
+ * Low level hardware spin locks, barrier and processor event APIs
*
- * Functions for synchronisation between core's, HW, etc
+ * Spin Locks
+ * ----------
*
* The RP2040 provides 32 hardware spin locks, which can be used to manage mutually-exclusive access to shared software
- * resources.
+ * and hardware resources.
*
- * \note spin locks 0-15 are currently reserved for fixed uses by the SDK - i.e. if you use them other
- * functionality may break or not function optimally
+ * Generally each spin lock itself is a shared resource,
+ * i.e. the same hardware spin lock can be used by multiple higher level primitives (as long as the spin locks are neither held for long periods, nor
+ * held concurrently with other spin locks by the same core - which could lead to deadlock). A hardware spin lock that is exclusively owned can be used
+ * individually without more flexibility and without regard to other software. Note that no hardware spin lock may
+ * be acquired re-entrantly (i.e. hardware spin locks are not on their own safe for use by both thread code and IRQs) however the default spinlock related
+ * methods here (e.g. \ref spin_lock_blocking) always disable interrupts while the lock is held as use by IRQ handlers and user code is common/desirable,
+ * and spin locks are only expected to be held for brief periods.
+ *
+ * The SDK uses the following default spin lock assignments, classifying which spin locks are reserved for exclusive/special purposes
+ * vs those suitable for more general shared use:
+ *
+ * Number (ID) | Description
+ * :---------: | -----------
+ * 0-13 | Currently reserved for exclusive use by the SDK and other libraries. If you use these spin locks, you risk breaking SDK or other library functionality. Each reserved spin lock used individually has its own PICO_SPINLOCK_ID so you can search for those.
+ * 14,15 | (\ref PICO_SPINLOCK_ID_OS1 and \ref PICO_SPINLOCK_ID_OS2). Currently reserved for exclusive use by an operating system (or other system level software) co-existing with the SDK.
+ * 16-23 | (\ref PICO_SPINLOCK_ID_STRIPED_FIRST - \ref PICO_SPINLOCK_ID_STRIPED_LAST). Spin locks from this range are assigned in a round-robin fashion via \ref next_striped_spin_lock_num(). These spin locks are shared, but assigning numbers from a range reduces the probability that two higher level locking primitives using _striped_ spin locks will actually be using the same spin lock.
+ * 24-31 | (\ref PICO_SPINLOCK_ID_CLAIM_FREE_FIRST - \ref PICO_SPINLOCK_ID_CLAIM_FREE_LAST). These are reserved for exclusive use and are allocated on a first come first served basis at runtime via \ref spin_lock_claim_unused()
*/
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_SYNC, Enable/disable assertions in the HW sync module, type=bool, default=0, group=hardware_sync
@@ -54,33 +70,46 @@
#define PICO_SPINLOCK_ID_HARDWARE_CLAIM 11
#endif
-// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_FIRST, Spinlock ID for striped first, min=16, max=31, default=16, group=hardware_sync
+// PICO_CONFIG: PICO_SPINLOCK_ID_OS1, First Spinlock ID reserved for use by low level OS style software, min=0, max=31, default=14, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_OS1
+#define PICO_SPINLOCK_ID_OS1 14
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_OS2, Second Spinlock ID reserved for use by low level OS style software, min=0, max=31, default=15, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_OS2
+#define PICO_SPINLOCK_ID_OS2 15
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_FIRST, Lowest Spinlock ID in the 'striped' range, min=0, max=31, default=16, group=hardware_sync
#ifndef PICO_SPINLOCK_ID_STRIPED_FIRST
#define PICO_SPINLOCK_ID_STRIPED_FIRST 16
#endif
-// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_LAST, Spinlock ID for striped last, min=16, max=31, default=23, group=hardware_sync
+// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_LAST, Highest Spinlock ID in the 'striped' range, min=0, max=31, default=23, group=hardware_sync
#ifndef PICO_SPINLOCK_ID_STRIPED_LAST
#define PICO_SPINLOCK_ID_STRIPED_LAST 23
#endif
-// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_FIRST, Spinlock ID for claim free first, min=16, max=31, default=24, group=hardware_sync
+// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_FIRST, Lowest Spinlock ID in the 'claim free' range, min=0, max=31, default=24, group=hardware_sync
#ifndef PICO_SPINLOCK_ID_CLAIM_FREE_FIRST
#define PICO_SPINLOCK_ID_CLAIM_FREE_FIRST 24
#endif
-// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_END, Spinlock ID for claim free end, min=16, max=31, default=31, group=hardware_sync
-#ifndef PICO_SPINLOCK_ID_CLAIM_FREE_END
-#define PICO_SPINLOCK_ID_CLAIM_FREE_END 31
+#ifdef PICO_SPINLOCK_ID_CLAIM_FREE_END
+#warning PICO_SPINLOCK_ID_CLAIM_FREE_END has been renamed to PICO_SPINLOCK_ID_CLAIM_FREE_LAST
#endif
+// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_LAST, Highest Spinlock ID in the 'claim free' range, min=0, max=31, default=31, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_CLAIM_FREE_LAST
+#define PICO_SPINLOCK_ID_CLAIM_FREE_LAST 31
+#endif
/*! \brief Insert a SEV instruction in to the code path.
* \ingroup hardware_sync
* The SEV (send event) instruction sends an event to both cores.
*/
-inline static void __sev(void) {
+__force_inline static void __sev(void) {
__asm volatile ("sev");
}
@@ -90,7 +119,7 @@
* The WFE (wait for event) instruction waits until one of a number of
* events occurs, including events signalled by the SEV instruction on either core.
*/
-inline static void __wfe(void) {
+__force_inline static void __wfe(void) {
__asm volatile ("wfe");
}
@@ -99,7 +128,7 @@
*
* The WFI (wait for interrupt) instruction waits for a interrupt to wake up the core.
*/
-inline static void __wfi(void) {
+__force_inline static void __wfi(void) {
__asm volatile ("wfi");
}
@@ -109,7 +138,7 @@
* The DMB (data memory barrier) acts as a memory barrier, all memory accesses prior to this
* instruction will be observed before any explicit access after the instruction.
*/
-inline static void __dmb(void) {
+__force_inline static void __dmb(void) {
__asm volatile ("dmb" : : : "memory");
}
@@ -120,7 +149,7 @@
* memory barrier (DMB). The DSB operation completes when all explicit memory
* accesses before this instruction complete.
*/
-inline static void __dsb(void) {
+__force_inline static void __dsb(void) {
__asm volatile ("dsb" : : : "memory");
}
@@ -131,14 +160,14 @@
* so that all instructions following the ISB are fetched from cache or memory again, after
* the ISB instruction has been completed.
*/
-inline static void __isb(void) {
+__force_inline static void __isb(void) {
__asm volatile ("isb");
}
/*! \brief Acquire a memory fence
* \ingroup hardware_sync
*/
-inline static void __mem_fence_acquire(void) {
+__force_inline static void __mem_fence_acquire(void) {
// the original code below makes it hard for us to be included from C++ via a header
// which itself is in an extern "C", so just use __dmb instead, which is what
// is required on Cortex M0+
@@ -154,7 +183,7 @@
* \ingroup hardware_sync
*
*/
-inline static void __mem_fence_release(void) {
+__force_inline static void __mem_fence_release(void) {
// the original code below makes it hard for us to be included from C++ via a header
// which itself is in an extern "C", so just use __dmb instead, which is what
// is required on Cortex M0+
@@ -171,7 +200,7 @@
*
* \return The prior interrupt enable status for restoration later via restore_interrupts()
*/
-inline static uint32_t save_and_disable_interrupts(void) {
+__force_inline static uint32_t save_and_disable_interrupts(void) {
uint32_t status;
__asm volatile ("mrs %0, PRIMASK" : "=r" (status)::);
__asm volatile ("cpsid i");
@@ -183,7 +212,7 @@
*
* \param status Previous interrupt status from save_and_disable_interrupts()
*/
-inline static void restore_interrupts(uint32_t status) {
+__force_inline static void restore_interrupts(uint32_t status) {
__asm volatile ("msr PRIMASK,%0"::"r" (status) : );
}
@@ -193,7 +222,8 @@
* \param lock_num Spinlock ID
* \return The spinlock instance
*/
-inline static spin_lock_t *spin_lock_instance(uint lock_num) {
+__force_inline static spin_lock_t *spin_lock_instance(uint lock_num) {
+ invalid_params_if(SYNC, lock_num >= NUM_SPIN_LOCKS);
return (spin_lock_t *) (SIO_BASE + SIO_SPINLOCK0_OFFSET + lock_num * 4);
}
@@ -203,7 +233,7 @@
* \param lock The Spinlock instance
* \return The Spinlock ID
*/
-inline static uint spin_lock_get_num(spin_lock_t *lock) {
+__force_inline static uint spin_lock_get_num(spin_lock_t *lock) {
invalid_params_if(SYNC, (uint) lock < SIO_BASE + SIO_SPINLOCK0_OFFSET ||
(uint) lock >= NUM_SPIN_LOCKS * sizeof(spin_lock_t) + SIO_BASE + SIO_SPINLOCK0_OFFSET ||
((uint) lock - SIO_BASE + SIO_SPINLOCK0_OFFSET) % sizeof(spin_lock_t) != 0);
@@ -215,7 +245,7 @@
*
* \param lock Spinlock instance
*/
-inline static void spin_lock_unsafe_blocking(spin_lock_t *lock) {
+__force_inline static void spin_lock_unsafe_blocking(spin_lock_t *lock) {
// Note we don't do a wfe or anything, because by convention these spin_locks are VERY SHORT LIVED and NEVER BLOCK and run
// with INTERRUPTS disabled (to ensure that)... therefore nothing on our core could be blocking us, so we just need to wait on another core
// anyway which should be finished soon
@@ -228,7 +258,7 @@
*
* \param lock Spinlock instance
*/
-inline static void spin_unlock_unsafe(spin_lock_t *lock) {
+__force_inline static void spin_unlock_unsafe(spin_lock_t *lock) {
__mem_fence_release();
*lock = 0;
}
@@ -241,7 +271,7 @@
* \param lock Spinlock instance
* \return interrupt status to be used when unlocking, to restore to original state
*/
-inline static uint32_t spin_lock_blocking(spin_lock_t *lock) {
+__force_inline static uint32_t spin_lock_blocking(spin_lock_t *lock) {
uint32_t save = save_and_disable_interrupts();
spin_lock_unsafe_blocking(lock);
return save;
@@ -269,7 +299,7 @@
*
* \sa spin_lock_blocking()
*/
-inline static void spin_unlock(spin_lock_t *lock, uint32_t saved_irq) {
+__force_inline static void spin_unlock(spin_lock_t *lock, uint32_t saved_irq) {
spin_unlock_unsafe(lock);
restore_interrupts(saved_irq);
}
@@ -279,7 +309,7 @@
*
* \return The core number the call was made from
*/
-static inline uint get_core_num(void) {
+__force_inline static uint get_core_num(void) {
return (*(uint32_t *) (SIO_BASE + SIO_CPUID_OFFSET));
}
@@ -298,7 +328,21 @@
*/
void spin_locks_reset(void);
-// this number is not claimed
+/*! \brief Return a spin lock number from the _striped_ range
+ * \ingroup hardware_sync
+ *
+ * Returns a spin lock number in the range PICO_SPINLOCK_ID_STRIPED_FIRST to PICO_SPINLOCK_ID_STRIPED_LAST
+ * in a round robin fashion. This does not grant the caller exclusive access to the spin lock, so the caller
+ * must:
+ *
+ * -# Abide (with other callers) by the contract of only holding this spin lock briefly (and with IRQs disabled - the default via \ref spin_lock_blocking()),
+ * and not whilst holding other spin locks.
+ * -# Be OK with any contention caused by the - brief due to the above requirement - contention with other possible users of the spin lock.
+ *
+ * \return lock_num a spin lock number the caller may use (non exclusively)
+ * \see PICO_SPINLOCK_ID_STRIPED_FIRST
+ * \see PICO_SPINLOCK_ID_STRIPED_LAST
+ */
uint next_striped_spin_lock_num(void);
/*! \brief Mark a spin lock as used
@@ -340,6 +384,16 @@
*/
int spin_lock_claim_unused(bool required);
+/*! \brief Determine if a spin lock is claimed
+ * \ingroup hardware_sync
+ *
+ * \param lock_num the spin lock number
+ * \return true if claimed, false otherwise
+ * \see spin_lock_claim
+ * \see spin_lock_claim_mask
+ */
+bool spin_lock_is_claimed(uint lock_num);
+
#define remove_volatile_cast(t, x) ({__mem_fence_acquire(); (t)(x); })
#ifdef __cplusplus
diff --git a/src/rp2_common/hardware_sync/sync.c b/src/rp2_common/hardware_sync/sync.c
index c032a27..a15c8d6 100644
--- a/src/rp2_common/hardware_sync/sync.c
+++ b/src/rp2_common/hardware_sync/sync.c
@@ -49,10 +49,16 @@
void spin_lock_unclaim(uint lock_num) {
check_lock_num(lock_num);
+ spin_unlock_unsafe(spin_lock_instance(lock_num));
hw_claim_clear((uint8_t *) &claimed, lock_num);
}
int spin_lock_claim_unused(bool required) {
- return hw_claim_unused_from_range((uint8_t*)&claimed, required, PICO_SPINLOCK_ID_CLAIM_FREE_FIRST, PICO_SPINLOCK_ID_CLAIM_FREE_END, "No spinlocks are available");
+ return hw_claim_unused_from_range((uint8_t*)&claimed, required, PICO_SPINLOCK_ID_CLAIM_FREE_FIRST, PICO_SPINLOCK_ID_CLAIM_FREE_LAST, "No spinlocks are available");
+}
+
+bool spin_lock_is_claimed(uint lock_num) {
+ check_lock_num(lock_num);
+ return hw_is_claimed((uint8_t *) &claimed, lock_num);
}
diff --git a/src/rp2_common/hardware_timer/include/hardware/timer.h b/src/rp2_common/hardware_timer/include/hardware/timer.h
index 4665ae5..1799cd0 100644
--- a/src/rp2_common/hardware_timer/include/hardware/timer.h
+++ b/src/rp2_common/hardware_timer/include/hardware/timer.h
@@ -80,17 +80,24 @@
/*! \brief Busy wait wasting cycles for the given (32 bit) number of microseconds
* \ingroup hardware_timer
*
- * \param delay_us delay amount
+ * \param delay_us delay amount in microseconds
*/
void busy_wait_us_32(uint32_t delay_us);
/*! \brief Busy wait wasting cycles for the given (64 bit) number of microseconds
* \ingroup hardware_timer
*
- * \param delay_us delay amount
+ * \param delay_us delay amount in microseconds
*/
void busy_wait_us(uint64_t delay_us);
+/*! \brief Busy wait wasting cycles for the given number of milliseconds
+ * \ingroup hardware_timer
+ *
+ * \param delay_ms delay amount in milliseconds
+ */
+void busy_wait_ms(uint32_t delay_ms);
+
/*! \brief Busy wait wasting cycles until after the specified timestamp
* \ingroup hardware_timer
*
@@ -137,6 +144,15 @@
*/
void hardware_alarm_unclaim(uint alarm_num);
+/*! \brief Determine if a hardware alarm has been claimed
+ * \ingroup hardware_timer
+ *
+ * \param alarm_num the hardware alarm number
+ * \return true if claimed, false otherwise
+ * \see hardware_alarm_claim
+ */
+bool hardware_alarm_is_claimed(uint alarm_num);
+
/*! \brief Enable/Disable a callback for a hardware timer on this core
* \ingroup hardware_timer
*
diff --git a/src/rp2_common/hardware_timer/timer.c b/src/rp2_common/hardware_timer/timer.c
index 23bea05..f13d249 100644
--- a/src/rp2_common/hardware_timer/timer.c
+++ b/src/rp2_common/hardware_timer/timer.c
@@ -28,6 +28,11 @@
hw_claim_clear(&claimed, alarm_num);
}
+bool hardware_alarm_is_claimed(uint alarm_num) {
+ check_hardware_alarm_num_param(alarm_num);
+ return hw_is_claimed(&claimed, alarm_num);
+}
+
/// tag::time_us_64[]
uint64_t time_us_64() {
// Need to make sure that the upper 32 bits of the timer
@@ -73,6 +78,15 @@
busy_wait_until(t);
}
+void busy_wait_ms(uint32_t delay_ms)
+{
+ if (delay_ms <= 0x7fffffffu / 1000) {
+ busy_wait_us_32(delay_ms * 1000);
+ } else {
+ busy_wait_us(delay_ms * 1000ull);
+ }
+}
+
void busy_wait_until(absolute_time_t t) {
uint64_t target = to_us_since_boot(t);
uint32_t hi_target = (uint32_t)(target >> 32u);
diff --git a/src/rp2_common/hardware_uart/include/hardware/uart.h b/src/rp2_common/hardware_uart/include/hardware/uart.h
index d37c1b7..02fdd1f 100644
--- a/src/rp2_common/hardware_uart/include/hardware/uart.h
+++ b/src/rp2_common/hardware_uart/include/hardware/uart.h
@@ -101,6 +101,12 @@
return uart == uart1 ? 1 : 0;
}
+static inline uart_inst_t *uart_get_instance(uint instance) {
+ static_assert(NUM_UARTS == 2, "");
+ invalid_params_if(UART, instance >= NUM_UARTS);
+ return instance ? uart1 : uart0;
+}
+
static inline uart_hw_t *uart_get_hw(uart_inst_t *uart) {
uart_get_index(uart); // check it is a hw uart
return (uart_hw_t *)uart;
diff --git a/src/rp2_common/hardware_uart/uart.c b/src/rp2_common/hardware_uart/uart.c
index 51d8d74..ba48e87 100644
--- a/src/rp2_common/hardware_uart/uart.c
+++ b/src/rp2_common/hardware_uart/uart.c
@@ -74,7 +74,7 @@
invalid_params_if(UART, baudrate == 0);
uint32_t baud_rate_div = (8 * clock_get_hz(clk_peri) / baudrate);
uint32_t baud_ibrd = baud_rate_div >> 7;
- uint32_t baud_fbrd = ((baud_rate_div & 0x7f) + 1) / 2;
+ uint32_t baud_fbrd;
if (baud_ibrd == 0) {
baud_ibrd = 1;
@@ -82,6 +82,8 @@
} else if (baud_ibrd >= 65535) {
baud_ibrd = 65535;
baud_fbrd = 0;
+ } else {
+ baud_fbrd = ((baud_rate_div & 0x7f) + 1) / 2;
}
// Load PL011's baud divisor registers
diff --git a/src/rp2_common/hardware_xosc/include/hardware/xosc.h b/src/rp2_common/hardware_xosc/include/hardware/xosc.h
index 0aa0842..a5e33b0 100644
--- a/src/rp2_common/hardware_xosc/include/hardware/xosc.h
+++ b/src/rp2_common/hardware_xosc/include/hardware/xosc.h
@@ -10,6 +10,15 @@
#include "pico.h"
#include "hardware/structs/xosc.h"
+
+// Allow lengthening startup delay to accommodate slow-starting oscillators
+
+// PICO_CONFIG: PICO_XOSC_STARTUP_DELAY_MULTIPLIER, Multiplier to lengthen xosc startup delay to accommodate slow-starting oscillators, type=int, min=1, default=1, group=hardware_xosc
+#ifndef PICO_XOSC_STARTUP_DELAY_MULTIPLIER
+#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 1
+#endif
+
+
#ifdef __cplusplus
extern "C" {
#endif
diff --git a/src/rp2_common/hardware_xosc/xosc.c b/src/rp2_common/hardware_xosc/xosc.c
index 977f0bd..9a95e37 100644
--- a/src/rp2_common/hardware_xosc/xosc.c
+++ b/src/rp2_common/hardware_xosc/xosc.c
@@ -11,16 +11,25 @@
#include "hardware/platform_defs.h"
#include "hardware/regs/xosc.h"
-#include "hardware/structs/xosc.h"
+#include "hardware/xosc.h"
+
+#if XOSC_MHZ < 1 || XOSC_MHZ > 15
+#error XOSC_MHZ must be in the range 1-15
+#endif
+
+#define STARTUP_DELAY (((((XOSC_MHZ * MHZ) / 1000) + 128) / 256) * PICO_XOSC_STARTUP_DELAY_MULTIPLIER)
+
+// The DELAY field in xosc_hw->startup is 14 bits wide.
+#if STARTUP_DELAY >= (1 << 13)
+#error PICO_XOSC_STARTUP_DELAY_MULTIPLIER is too large: XOSC STARTUP.DELAY must be < 8192
+#endif
void xosc_init(void) {
- // Assumes 1-15 MHz input
- assert(XOSC_MHZ <= 15);
+ // Assumes 1-15 MHz input, checked above.
xosc_hw->ctrl = XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ;
// Set xosc startup delay
- uint32_t startup_delay = (((12 * MHZ) / 1000) + 128) / 256;
- xosc_hw->startup = startup_delay;
+ xosc_hw->startup = STARTUP_DELAY;
// Set the enable bit now that we have set freq range and startup delay
hw_set_bits(&xosc_hw->ctrl, XOSC_CTRL_ENABLE_VALUE_ENABLE << XOSC_CTRL_ENABLE_LSB);
@@ -43,4 +52,4 @@
xosc_hw->dormant = XOSC_DORMANT_VALUE_DORMANT;
// Wait for it to become stable once woken up
while(!(xosc_hw->status & XOSC_STATUS_STABLE_BITS));
-}
\ No newline at end of file
+}
diff --git a/src/rp2_common/pico_bit_ops/CMakeLists.txt b/src/rp2_common/pico_bit_ops/CMakeLists.txt
index 7e5f2b9..962c307 100644
--- a/src/rp2_common/pico_bit_ops/CMakeLists.txt
+++ b/src/rp2_common/pico_bit_ops/CMakeLists.txt
@@ -1,13 +1,9 @@
if (NOT TARGET pico_bit_ops)
#shims for ROM functions for -lgcc functions (listed below)
- add_library(pico_bit_ops INTERFACE)
+ pico_add_impl_library(pico_bit_ops)
# no custom implementation; falls thru to compiler
- add_library(pico_bit_ops_compiler INTERFACE)
- # PICO_BUILD_DEFINE: PICO_BIT_OPS_COMPILER, whether compiler provided bit_ops bit functions support is being used, type=bool, default=0, but dependent on CMake options, group=pico_bit_ops
- target_compile_definitions(pico_bit_ops_compiler INTERFACE
- PICO_BIT_OPS_COMPILER=1
- )
+ pico_add_impl_library(pico_bit_ops_compiler)
# add alias "default" which is just pico.
add_library(pico_bit_ops_default INTERFACE)
@@ -15,15 +11,10 @@
set(PICO_DEFAULT_BIT_OPS_IMPL pico_bit_ops_default)
- add_library(pico_bit_ops_pico INTERFACE)
+ pico_add_impl_library(pico_bit_ops_pico)
target_link_libraries(pico_bit_ops INTERFACE
$<IF:$<BOOL:$<TARGET_PROPERTY:PICO_TARGET_BIT_OPS_IMPL>>,$<TARGET_PROPERTY:PICO_TARGET_BIT_OPS_IMPL>,${PICO_DEFAULT_BIT_OPS_IMPL}>)
- # PICO_BUILD_DEFINE: PICO_BIT_OPS_PICO, whether optimized pico/bootrom provided bit_ops bit functions support is being used, type=bool, default=1, but dependent on CMake options, group=pico_bit_ops
- target_compile_definitions(pico_bit_ops_pico INTERFACE
- PICO_BIT_OPS_PICO=1
- )
-
target_sources(pico_bit_ops_pico INTERFACE
${CMAKE_CURRENT_LIST_DIR}/bit_ops_aeabi.S
)
diff --git a/src/rp2_common/pico_bootsel_via_double_reset/CMakeLists.txt b/src/rp2_common/pico_bootsel_via_double_reset/CMakeLists.txt
index 74384c6..17b4042 100644
--- a/src/rp2_common/pico_bootsel_via_double_reset/CMakeLists.txt
+++ b/src/rp2_common/pico_bootsel_via_double_reset/CMakeLists.txt
@@ -1,4 +1,4 @@
-add_library(pico_bootsel_via_double_reset INTERFACE)
+pico_add_impl_library(pico_bootsel_via_double_reset)
target_sources(pico_bootsel_via_double_reset INTERFACE
${CMAKE_CURRENT_LIST_DIR}/pico_bootsel_via_double_reset.c
diff --git a/src/rp2_common/pico_divider/CMakeLists.txt b/src/rp2_common/pico_divider/CMakeLists.txt
index 9eda235..813d1c1 100644
--- a/src/rp2_common/pico_divider/CMakeLists.txt
+++ b/src/rp2_common/pico_divider/CMakeLists.txt
@@ -1,12 +1,9 @@
if (NOT TARGET pico_divider)
# library to be depended on - we make this depend on particular implementations using per target generator expressions
- add_library(pico_divider INTERFACE)
+ pico_add_impl_library(pico_divider)
# no custom implementation; falls thru to compiler
- add_library(pico_divider_compiler INTERFACE)
- target_compile_definitions(pico_divider_compiler INTERFACE
- PICO_DIVIDER_COMPILER=1
- )
+ pico_add_impl_library(pico_divider_compiler)
# add alias "default" which is just hardware.
add_library(pico_divider_default INTERFACE)
@@ -27,10 +24,7 @@
hardware_regs
)
- add_library(pico_divider_hardware INTERFACE)
- target_compile_definitions(pico_divider_hardware INTERFACE
- PICO_DIVIDER_HARDWARE=1
- )
+ pico_add_impl_library(pico_divider_hardware)
target_link_libraries(pico_divider_hardware INTERFACE pico_divider_hardware_explicit)
diff --git a/src/rp2_common/pico_divider/divider.S b/src/rp2_common/pico_divider/divider.S
index 12eae38..ac67a5e 100644
--- a/src/rp2_common/pico_divider/divider.S
+++ b/src/rp2_common/pico_divider/divider.S
@@ -4,23 +4,28 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include "hardware/regs/sio.h"
#include "hardware/regs/addressmap.h"
+#include "hardware/divider_helper.S"
.syntax unified
.cpu cortex-m0plus
.thumb
+// PICO_CONFIG: PICO_DIVIDER_DISABLE_INTERRUPTS, Disable interrupts around division such that divider state need not be saved/restored in exception handlers, default=0, group=pico_divider
+
#include "pico/asm_helper.S"
+// PICO_CONFIG: PICO_DIVIDER_CALL_IDIV0, Whether 32 bit division by zero should call __aeabi_idiv0, default=1, group=pico_divider
#ifndef PICO_DIVIDER_CALL_IDIV0
#define PICO_DIVIDER_CALL_IDIV0 1
#endif
+// PICO_CONFIG: PICO_DIVIDER_CALL_IDIV0, Whether 64 bit division by zero should call __aeabi_ldiv0, default=1, group=pico_divider
#ifndef PICO_DIVIDER_CALL_LDIV0
#define PICO_DIVIDER_CALL_LDIV0 1
#endif
+// PICO_CONFIG: PICO_DIVIDER_IN_RAM, Whether divider functions should be placed in RAM, default=0, group=pico_divider
.macro div_section name
#if PICO_DIVIDER_IN_RAM
.section RAM_SECTION_NAME(\name), "ax"
@@ -29,17 +34,6 @@
#endif
.endm
-#if SIO_DIV_CSR_READY_LSB == 0
-.equ SIO_DIV_CSR_READY_SHIFT_FOR_CARRY, 1
-#else
-need to change SHIFT above
-#endif
-#if SIO_DIV_CSR_DIRTY_LSB == 1
-.equ SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY, 2
-#else
-need to change SHIFT above
-#endif
-
@ wait 8-n cycles for the hardware divider
.macro wait_div n
.rept (8-\n) / 2
@@ -51,56 +45,17 @@
.endif
.endm
-
#if (SIO_DIV_SDIVISOR_OFFSET != SIO_DIV_SDIVIDEND_OFFSET + 4) || (SIO_DIV_QUOTIENT_OFFSET != SIO_DIV_SDIVISOR_OFFSET + 4) || (SIO_DIV_REMAINDER_OFFSET != SIO_DIV_QUOTIENT_OFFSET + 4)
#error register layout has changed - we rely on this order to make sure we save/restore in the right order
#endif
-# SIO_BASE ptr in r2
-.macro save_div_state_and_lr
- ldr r3, [r2, #SIO_DIV_CSR_OFFSET]
- # wait for results as we can't save signed-ness of operation
-1:
- lsrs r3, #SIO_DIV_CSR_READY_SHIFT_FOR_CARRY
- bcc 1b
- push {r4, r5, r6, r7, lr}
- // note we must read quotient last, and since it isn't the last reg, we'll not use ldmia!
- ldr r4, [r2, #SIO_DIV_SDIVIDEND_OFFSET]
- ldr r5, [r2, #SIO_DIV_SDIVISOR_OFFSET]
- ldr r7, [r2, #SIO_DIV_REMAINDER_OFFSET]
- ldr r6, [r2, #SIO_DIV_QUOTIENT_OFFSET]
-.endm
-
-.macro restore_div_state_and_return
- // writing sdividend (r4), sdivisor (r5), quotient (r6), remainder (r7) in that order
- //
- // it is worth considering what happens if we are interrupted
- //
- // after writing r4: we are DIRTY and !READY
- // ... interruptor using div will complete based on incorrect inputs, but dividend at least will be
- // saved/restored correctly and we'll restore the rest ourselves
- // after writing r4, r5: we are DIRTY and !READY
- // ... interruptor using div will complete based on possibly wrongly signed inputs, but dividend, divisor
- // at least will be saved/restored correctly and and we'll restore the rest ourselves
- // after writing r4, r5, r6: we are DIRTY and READY
- // ... interruptor using div will dividend, divisor, quotient registers as is (what we just restored ourselves),
- // and we'll restore the remainder after the fact
-
- // note we are not use STM not because it can be restarted due to interrupt which is harmless, more because this is 1 cycle IO space
- // and so 4 reads is cheaper (and we don't have to adjust r2)
- str r4, [r2, #SIO_DIV_SDIVIDEND_OFFSET]
- str r5, [r2, #SIO_DIV_SDIVISOR_OFFSET]
- str r7, [r2, #SIO_DIV_REMAINDER_OFFSET]
- str r6, [r2, #SIO_DIV_QUOTIENT_OFFSET]
- pop {r4, r5, r6, r7, pc}
-.endm
-
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
.macro save_div_state_and_lr_64
push {r4, r5, r6, r7, lr}
ldr r6, =SIO_BASE
1:
ldr r5, [r6, #SIO_DIV_CSR_OFFSET]
- # wait for results as we can't save signed-ness of operation
+ // wait for results as we can't save signed-ness of operation
lsrs r5, #SIO_DIV_CSR_READY_SHIFT_FOR_CARRY
bcc 1b
// note we must read quotient last, and since it isn't the last reg, we'll not use ldmia!
@@ -137,6 +92,7 @@
pop {r4, r5, r6, r7, pc}
.endm
+#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */
// since idiv and idivmod only differ by a cycle, we'll make them the same!
div_section WRAPPER_FUNC_NAME(__aeabi_idiv)
@@ -145,12 +101,23 @@
wrapper_func __aeabi_idivmod
regular_func div_s32s32
regular_func divmod_s32s32
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
+ // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty
ldr r2, =(SIO_BASE)
- # to support IRQ usage we must save/restore
ldr r3, [r2, #SIO_DIV_CSR_OFFSET]
lsrs r3, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY
bcs divmod_s32s32_savestate
regular_func divmod_s32s32_unsafe
+#else
+// to avoid too much source code spaghetti with restoring interrupts, we make this the same as the other funcs
+// in the PICO_DIVIDER_DISABLE_INTERRUPTS case; i.e. it is not a faster function; this seems reasonable as there
+// are the hardware_divider functions that can be used instead anyway
+regular_func divmod_s32s32_unsafe
+ // to avoid worrying about IRQs (or context switches), simply disable interrupts around call
+ ldr r2, =(SIO_BASE)
+ mrs r3, PRIMASK
+ cpsid i
+#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */
str r0, [r2, #SIO_DIV_SDIVIDEND_OFFSET]
str r1, [r2, #SIO_DIV_SDIVISOR_OFFSET]
cmp r1, #0
@@ -159,8 +126,14 @@
// return 64 bit value so we can efficiently return both (note read order is important since QUOTIENT must be read last)
ldr r1, [r2, #SIO_DIV_REMAINDER_OFFSET]
ldr r0, [r2, #SIO_DIV_QUOTIENT_OFFSET]
+#if PICO_DIVIDER_DISABLE_INTERRUPTS
+ msr PRIMASK, r3
+#endif /* PICO_DIVIDER_DISABLE_INTERRUPTS */
bx lr
1:
+#if PICO_DIVIDER_DISABLE_INTERRUPTS
+ msr PRIMASK, r3
+#endif /* PICO_DIVIDER_DISABLE_INTERRUPTS */
push {r2, lr}
movs r1, #0x80
lsls r1, #24
@@ -176,11 +149,15 @@
movs r1, #0 // remainder 0
// need to restore saved r2 as it hold SIO ptr
pop {r2, pc}
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
.align 2
regular_func divmod_s32s32_savestate
+ // note that we must be at least 2 cycles into division at this point,
+ // which we are because of the firty check before getting here (and of course the function call before that)
save_div_state_and_lr
bl divmod_s32s32_unsafe
restore_div_state_and_return
+#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */
// since uidiv and uidivmod only differ by a cycle, we'll make them the same!
div_section WRAPPER_FUNC_NAME(__aeabi_uidiv)
@@ -188,12 +165,23 @@
regular_func divmod_u32u32
wrapper_func __aeabi_uidiv
wrapper_func __aeabi_uidivmod
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
+ // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty
ldr r2, =(SIO_BASE)
- # to support IRQ usage we must save/restore
ldr r3, [r2, #SIO_DIV_CSR_OFFSET]
lsrs r3, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY
bcs divmod_u32u32_savestate
regular_func divmod_u32u32_unsafe
+#else
+// to avoid too much source code spaghetti with restoring interrupts, we make this the same as the other funcs
+// in the PICO_DIVIDER_DISABLE_INTERRUPTS case; i.e. it is not a faster function; this seems reasonable as there
+// are the hardware_divider functions that can be used instead anyway
+regular_func divmod_u32u32_unsafe
+ // to avoid worrying about IRQs (or context switches), simply disable interrupts around call
+ ldr r2, =(SIO_BASE)
+ mrs r3, PRIMASK
+ cpsid i
+#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */
str r0, [r2, #SIO_DIV_UDIVIDEND_OFFSET]
str r1, [r2, #SIO_DIV_UDIVISOR_OFFSET]
cmp r1, #0
@@ -202,8 +190,14 @@
// return 64 bit value so we can efficiently return both (note read order is important since QUOTIENT must be read last)
ldr r1, [r2, #SIO_DIV_REMAINDER_OFFSET]
ldr r0, [r2, #SIO_DIV_QUOTIENT_OFFSET]
+#if PICO_DIVIDER_DISABLE_INTERRUPTS
+ msr PRIMASK, r3
+#endif /* PICO_DIVIDER_DISABLE_INTERRUPTS */
bx lr
1:
+#if PICO_DIVIDER_DISABLE_INTERRUPTS
+ msr PRIMASK, r3
+#endif /* PICO_DIVIDER_DISABLE_INTERRUPTS */
push {r2, lr}
cmp r0, #0
beq 1f
@@ -216,11 +210,13 @@
movs r1, #0 // remainder 0
// need to restore saved r2 as it hold SIO ptr
pop {r2, pc}
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
.align 2
regular_func divmod_u32u32_savestate
save_div_state_and_lr
bl divmod_u32u32_unsafe
restore_div_state_and_return
+#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */
div_section WRAPPER_FUNC_NAME(__aeabi_ldiv)
@@ -228,9 +224,10 @@
wrapper_func __aeabi_ldivmod
regular_func div_s64s64
regular_func divmod_s64s64
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
+ // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty
mov ip, r2
ldr r2, =(SIO_BASE)
- # to support IRQ usage we must save/restore
ldr r2, [r2, #SIO_DIV_CSR_OFFSET]
lsrs r2, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY
mov r2, ip
@@ -241,14 +238,24 @@
save_div_state_and_lr_64
bl divmod_s64s64_unsafe
restore_div_state_and_return_64
+#else
+ // to avoid worrying about IRQs (or context switches), simply disable interrupts around call
+ push {r4, lr}
+ mrs r4, PRIMASK
+ cpsid i
+ bl divmod_s64s64_unsafe
+ msr PRIMASK, r4
+ pop {r4, pc}
+#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */
.align 2
wrapper_func __aeabi_uldivmod
regular_func div_u64u64
regular_func divmod_u64u64
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
+ // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty
mov ip, r2
ldr r2, =(SIO_BASE)
- # to support IRQ usage we must save/restore
ldr r2, [r2, #SIO_DIV_CSR_OFFSET]
lsrs r2, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY
mov r2, ip
@@ -259,6 +266,16 @@
save_div_state_and_lr_64
bl divmod_u64u64_unsafe
restore_div_state_and_return_64
+#else
+ // to avoid worrying about IRQs (or context switches), simply disable interrupts around call
+ push {r4, lr}
+ mrs r4, PRIMASK
+ cpsid i
+ bl divmod_u64u64_unsafe
+ msr PRIMASK, r4
+ pop {r4, pc}
+#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */
+
.macro dneg lo,hi
mvns \hi,\hi
rsbs \lo,#0
diff --git a/src/rp2_common/pico_double/CMakeLists.txt b/src/rp2_common/pico_double/CMakeLists.txt
index a707385..efe1b63 100644
--- a/src/rp2_common/pico_double/CMakeLists.txt
+++ b/src/rp2_common/pico_double/CMakeLists.txt
@@ -1,13 +1,9 @@
if (NOT TARGET pico_double)
# library to be depended on - we make this depend on particular implementations using per target generator expressions
- add_library(pico_double INTERFACE)
+ pico_add_impl_library(pico_double)
# no custom implementation; falls thru to compiler
- add_library(pico_double_compiler INTERFACE)
- # PICO_BUILD_DEFINE: PICO_DOUBLE_COMPILER, whether compiler provided double support is being used, type=bool, default=0, but dependent on CMake options, group=pico_double
- target_compile_definitions(pico_double_compiler INTERFACE
- PICO_DOUBLE_COMPILER=1
- )
+ pico_add_impl_library(pico_double_compiler)
add_library(pico_double_headers INTERFACE)
target_include_directories(pico_double_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
@@ -21,30 +17,24 @@
target_link_libraries(pico_double INTERFACE
$<IF:$<BOOL:$<TARGET_PROPERTY:PICO_TARGET_DOUBLE_IMPL>>,$<TARGET_PROPERTY:PICO_TARGET_DOUBLE_IMPL>,${PICO_DEFAULT_DOUBLE_IMPL}>)
- add_library(pico_double_pico INTERFACE)
+ pico_add_impl_library(pico_double_pico)
target_sources(pico_double_pico INTERFACE
${CMAKE_CURRENT_LIST_DIR}/double_aeabi.S
${CMAKE_CURRENT_LIST_DIR}/double_init_rom.c
${CMAKE_CURRENT_LIST_DIR}/double_math.c
${CMAKE_CURRENT_LIST_DIR}/double_v1_rom_shim.S
)
- # PICO_BUILD_DEFINE: PICO_DOUBLE_PICO, whether optimized pico/bootrom provided double support is being used, type=bool, default=1, but dependent on CMake options, group=pico_double
- target_compile_definitions(pico_double_pico INTERFACE
- PICO_DOUBLE_PICO=1
- )
target_link_libraries(pico_double_pico INTERFACE pico_bootrom pico_double_headers)
- add_library(pico_double_none INTERFACE)
+ pico_add_impl_library(pico_double_none)
target_sources(pico_double_none INTERFACE
${CMAKE_CURRENT_LIST_DIR}/double_none.S
)
target_link_libraries(pico_double_none INTERFACE pico_double_headers)
- # PICO_BUILD_DEFINE: PICO_DOUBLE_NONE, whether double support is disabled and functions will panic, type=bool, default=0, but dependent on CMake options, group=pico_double
target_compile_definitions(pico_double_none INTERFACE
- PICO_DOUBLE_NONE=1
PICO_PRINTF_SUPPORT_FLOAT=0 # printing floats/doubles won't work, so we can save space by removing it
)
diff --git a/src/rp2_common/pico_double/double_aeabi.S b/src/rp2_common/pico_double/double_aeabi.S
index 1e1250f..a871e43 100644
--- a/src/rp2_common/pico_double/double_aeabi.S
+++ b/src/rp2_common/pico_double/double_aeabi.S
@@ -6,6 +6,7 @@
#include "pico/asm_helper.S"
#include "pico/bootrom/sf_table.h"
+#include "hardware/divider_helper.S"
__pre_init __aeabi_double_init, 00020
@@ -131,16 +132,16 @@
mov r11,r7
bx r14
-# note generally each function is in a separate section unless there is fall thru or branching between them
-# note fadd, fsub, fmul, fdiv are so tiny and just defer to rom so are lumped together so they can share constant pool
+// note generally each function is in a separate section unless there is fall thru or branching between them
+// note fadd, fsub, fmul, fdiv are so tiny and just defer to rom so are lumped together so they can share constant pool
-# note functions are word aligned except where they are an odd number of linear instructions
+// note functions are word aligned except where they are an odd number of linear instructions
// double FUNC_NAME(__aeabi_dadd)(double, double) double-precision addition
double_wrapper_section __aeabi_darithmetic
// double FUNC_NAME(__aeabi_drsub)(double x, double y) double-precision reverse subtraction, y - x
-# frsub first because it is the only one that needs alignment
+// frsub first because it is the only one that needs alignment
.align 2
wrapper_func __aeabi_drsub
eors r0, r1
@@ -177,7 +178,35 @@
b ddiv_dsub_nan_helper
1:
#endif
- shimmable_table_tail_call SF_TABLE_FDIV ddiv_shim
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
+ // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty
+ mov ip, r2
+ ldr r2, =(SIO_BASE)
+ ldr r2, [r2, #SIO_DIV_CSR_OFFSET]
+ lsrs r2, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY
+ bcs ddiv_save_state
+ mov r2, ip
+#else
+ // to avoid worrying about IRQs (or context switches), simply disable interrupts around call
+ push {r4, lr}
+ mrs r4, PRIMASK
+ cpsid i
+ bl ddiv_shim_call
+ msr PRIMASK, r4
+ pop {r4, pc}
+#endif
+ddiv_shim_call:
+ shimmable_table_tail_call SF_TABLE_FDIV ddiv_shim
+
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
+ddiv_save_state:
+ ldr r2, =(SIO_BASE)
+ save_div_state_and_lr
+ mov r2, ip
+ bl ddiv_shim_call
+ ldr r2, =(SIO_BASE)
+ restore_div_state_and_return
+#endif
ddiv_dsub_nan_helper:
#if PICO_DOUBLE_PROPAGATE_NANS
@@ -592,6 +621,8 @@
ldr r2, =0x54442D18 // 2 * M_PI
ldr r3, =0x401921FB
push {lr}
+ // note remainder only uses the divider thru integer divider functions
+ // which save and restore themselves
bl remainder
pop {pc}
@@ -752,13 +783,40 @@
wrapper_func tan
// rom version only works for -1024 < angle < 1024
lsls r2, r1, #2
- bcc 1f
+ bcc dtan_in_range
lsrs r2, #22
cmp r2, #9
- bge 2f
-1:
+ bge dtan_angle_out_of_range
+dtan_in_range:
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
+ // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty
+ mov ip, r2
+ ldr r2, =(SIO_BASE)
+ ldr r2, [r2, #SIO_DIV_CSR_OFFSET]
+ lsrs r2, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY
+ bcs dtan_save_state
+ mov r2, ip
+#else
+ // to avoid worrying about IRQs (or context switches), simply disable interrupts around call
+ push {r4, lr}
+ mrs r4, PRIMASK
+ cpsid i
+ bl dtan_shim_call
+ msr PRIMASK, r4
+ pop {r4, pc}
+#endif
+dtan_shim_call:
shimmable_table_tail_call SF_TABLE_FTAN dtan_shim
-2:
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
+dtan_save_state:
+ ldr r2, =(SIO_BASE)
+ save_div_state_and_lr
+ mov r2, ip
+ bl dtan_shim_call
+ ldr r2, =(SIO_BASE)
+ restore_div_state_and_return
+#endif
+dtan_angle_out_of_range:
#if PICO_DOUBLE_PROPAGATE_NANS
lsls r2, r1, #1
asrs r2, #21
@@ -775,7 +833,7 @@
bl sincostan_remainder
pop {r2}
mov lr, r2
- b 1b
+ b dtan_in_range
double_wrapper_section atan2
wrapper_func_d2 atan2
diff --git a/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/CMakeLists.txt b/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/CMakeLists.txt
index 0d682ab..18fdc28 100644
--- a/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/CMakeLists.txt
+++ b/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/CMakeLists.txt
@@ -1,4 +1,4 @@
-add_library(pico_fix_rp2040_usb_device_enumeration INTERFACE)
+pico_add_impl_library(pico_fix_rp2040_usb_device_enumeration)
target_sources(pico_fix_rp2040_usb_device_enumeration INTERFACE
${CMAKE_CURRENT_LIST_DIR}/rp2040_usb_device_enumeration.c
diff --git a/src/rp2_common/pico_float/CMakeLists.txt b/src/rp2_common/pico_float/CMakeLists.txt
index a6e7895..3543b03 100644
--- a/src/rp2_common/pico_float/CMakeLists.txt
+++ b/src/rp2_common/pico_float/CMakeLists.txt
@@ -1,13 +1,9 @@
if (NOT TARGET pico_float)
# library to be depended on - we make this depend on particular implementations using per target generator expressions
- add_library(pico_float INTERFACE)
+ pico_add_impl_library(pico_float)
# no custom implementation; falls thru to compiler
- add_library(pico_float_compiler INTERFACE)
- # PICO_BUILD_DEFINE: PICO_FLOAT_COMPILER, whether compiler provided float support is being used, type=bool, default=0, but dependent on CMake options, group=pico_float
- target_compile_definitions(pico_float_compiler INTERFACE
- PICO_FLOAT_COMPILER=1
- )
+ pico_add_impl_library(pico_float_compiler)
add_library(pico_float_headers INTERFACE)
target_include_directories(pico_float_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
@@ -21,32 +17,23 @@
target_link_libraries(pico_float INTERFACE
$<IF:$<BOOL:$<TARGET_PROPERTY:PICO_TARGET_FLOAT_IMPL>>,$<TARGET_PROPERTY:PICO_TARGET_FLOAT_IMPL>,${PICO_DEFAULT_FLOAT_IMPL}>)
- add_library(pico_float_pico INTERFACE)
+ pico_add_impl_library(pico_float_pico)
target_sources(pico_float_pico INTERFACE
${CMAKE_CURRENT_LIST_DIR}/float_aeabi.S
${CMAKE_CURRENT_LIST_DIR}/float_init_rom.c
${CMAKE_CURRENT_LIST_DIR}/float_math.c
${CMAKE_CURRENT_LIST_DIR}/float_v1_rom_shim.S
)
- # PICO_BUILD_DEFINE: PICO_FLOAT_PICO, whether optimized pico/bootrom provided float support is being used, type=bool, default=1, but dependent on CMake options, group=pico_float
- target_compile_definitions(pico_float_pico INTERFACE
- PICO_FLOAT_PICO=1
- )
target_link_libraries(pico_float_pico INTERFACE pico_bootrom pico_float_headers)
- add_library(pico_float_none INTERFACE)
+ pico_add_impl_library(pico_float_none)
target_sources(pico_float_none INTERFACE
${CMAKE_CURRENT_LIST_DIR}/float_none.S
)
target_link_libraries(pico_float_none INTERFACE pico_float_headers)
- # PICO_BUILD_DEFINE: PICO_FLOAT_NONE, whether float support is disabled and functions will panic, type=bool, default=0, but dependent on CMake options, group=pico_float
- target_compile_definitions(pico_float_none INTERFACE
- PICO_FLOAT_NONE=1
- )
-
function(wrap_float_functions TARGET)
pico_wrap_function(${TARGET} __aeabi_fadd)
pico_wrap_function(${TARGET} __aeabi_fdiv)
diff --git a/src/rp2_common/pico_float/float_aeabi.S b/src/rp2_common/pico_float/float_aeabi.S
index 2aee5f2..b901d30 100644
--- a/src/rp2_common/pico_float/float_aeabi.S
+++ b/src/rp2_common/pico_float/float_aeabi.S
@@ -6,6 +6,7 @@
#include "pico/asm_helper.S"
#include "pico/bootrom/sf_table.h"
+#include "hardware/divider_helper.S"
__pre_init __aeabi_float_init, 00020
@@ -104,16 +105,16 @@
.endm
-# note generally each function is in a separate section unless there is fall thru or branching between them
-# note fadd, fsub, fmul, fdiv are so tiny and just defer to rom so are lumped together so they can share constant pool
+// note generally each function is in a separate section unless there is fall thru or branching between them
+// note fadd, fsub, fmul, fdiv are so tiny and just defer to rom so are lumped together so they can share constant pool
-# note functions are word aligned except where they are an odd number of linear instructions
+// note functions are word aligned except where they are an odd number of linear instructions
// float FUNC_NAME(__aeabi_fadd)(float, float) single-precision addition
float_wrapper_section __aeabi_farithmetic
// float FUNC_NAME(__aeabi_frsub)(float x, float y) single-precision reverse subtraction, y - x
-# frsub first because it is the only one that needs alignment
+// frsub first because it is the only one that needs alignment
.align 2
wrapper_func __aeabi_frsub
eors r0, r1
@@ -146,7 +147,30 @@
b fdiv_fsub_nan_helper
1:
#endif
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
+ // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty
+ ldr r2, =(SIO_BASE)
+ ldr r3, [r2, #SIO_DIV_CSR_OFFSET]
+ lsrs r3, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY
+ bcs fdiv_save_state
+#else
+ // to avoid worrying about IRQs (or context switches), simply disable interrupts around call
+ push {r4, lr}
+ mrs r4, PRIMASK
+ cpsid i
+ bl fdiv_shim_call
+ msr PRIMASK, r4
+ pop {r4, pc}
+#endif
+fdiv_shim_call:
table_tail_call SF_TABLE_FDIV
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
+fdiv_save_state:
+ save_div_state_and_lr
+ bl fdiv_shim_call
+ ldr r2, =(SIO_BASE)
+ restore_div_state_and_return
+#endif
fdiv_fsub_nan_helper:
#if PICO_FLOAT_PROPAGATE_NANS
@@ -689,10 +713,33 @@
lsls r1, r0, #1
lsrs r1, #24
cmp r1, #127 + 7
- bge 1f
-2:
+ bge ftan_out_of_range
+ftan_in_range:
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
+ // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty
+ ldr r2, =(SIO_BASE)
+ ldr r3, [r2, #SIO_DIV_CSR_OFFSET]
+ lsrs r3, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY
+ bcs ftan_save_state
+#else
+ // to avoid worrying about IRQs (or context switches), simply disable interrupts around call
+ push {r4, lr}
+ mrs r4, PRIMASK
+ cpsid i
+ bl ftan_shim_call
+ msr PRIMASK, r4
+ pop {r4, pc}
+#endif
+ftan_shim_call:
table_tail_call SF_TABLE_FTAN
-1:
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
+ftan_save_state:
+ save_div_state_and_lr
+ bl ftan_shim_call
+ ldr r2, =(SIO_BASE)
+ restore_div_state_and_return
+#endif
+ftan_out_of_range:
#if PICO_FLOAT_PROPAGATE_NANS
// also check for infinites
cmp r1, #255
@@ -709,7 +756,7 @@
bl remainderf
pop {r1}
mov lr, r1
- b 2b
+ b ftan_in_range
float_wrapper_section atan2f
wrapper_func_f2 atan2f
diff --git a/src/rp2_common/pico_float/float_none.S b/src/rp2_common/pico_float/float_none.S
index 743a75e..55baf29 100644
--- a/src/rp2_common/pico_float/float_none.S
+++ b/src/rp2_common/pico_float/float_none.S
@@ -34,6 +34,7 @@
wrapper_func __aeabi_f2lz
wrapper_func __aeabi_f2uiz
wrapper_func __aeabi_f2ulz
+wrapper_func __aeabi_f2d
wrapper_func sqrtf
wrapper_func cosf
wrapper_func sinf
diff --git a/src/rp2_common/pico_int64_ops/CMakeLists.txt b/src/rp2_common/pico_int64_ops/CMakeLists.txt
index b589bed..73e7d17 100644
--- a/src/rp2_common/pico_int64_ops/CMakeLists.txt
+++ b/src/rp2_common/pico_int64_ops/CMakeLists.txt
@@ -1,14 +1,10 @@
if (NOT TARGET pico_int64_ops)
#shims for ROM functions for -lgcc functions (listed below)
- add_library(pico_int64_ops INTERFACE)
+ pico_add_impl_library(pico_int64_ops)
# no custom implementation; falls thru to compiler
- add_library(pico_int64_ops_compiler INTERFACE)
- # PICO_BUILD_DEFINE: PICO_INT64_OPS_COMPILER, whether compiler provided int64_ops multiplication support is being used, type=bool, default=0, but dependent on CMake options, group=pico_int64_ops
- target_compile_definitions(pico_int64_ops_compiler INTERFACE
- PICO_INT64_OPS_COMPILER=1
- )
+ pico_add_impl_library(pico_int64_ops_compiler)
# add alias "default" which is just pico.
add_library(pico_int64_ops_default INTERFACE)
@@ -19,18 +15,13 @@
target_link_libraries(pico_int64_ops INTERFACE
$<IF:$<BOOL:$<TARGET_PROPERTY:PICO_TARGET_INT64_OPS_IMPL>>,$<TARGET_PROPERTY:PICO_TARGET_INT64_OPS_IMPL>,${PICO_DEFAULT_INT64_OPS_IMPL}>)
- add_library(pico_int64_ops_pico INTERFACE)
+ pico_add_impl_library(pico_int64_ops_pico)
target_include_directories(pico_int64_ops_pico INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
target_sources(pico_int64_ops_pico INTERFACE
${CMAKE_CURRENT_LIST_DIR}/pico_int64_ops_aeabi.S
)
- # PICO_BUILD_DEFINE: PICO_INT64_OPS_PICO, whether optimized pico/bootrom provided int64_ops multiplication support is being used, type=bool, default=1, but dependent on CMake options, group=pico_int64_ops
- target_compile_definitions(pico_int64_ops_pico INTERFACE
- PICO_INT64_OPS_PICO=1
- )
-
pico_wrap_function(pico_int64_ops_pico __aeabi_lmul)
macro(pico_set_int64_ops_implementation TARGET IMPL)
diff --git a/src/rp2_common/pico_int64_ops/pico_int64_ops_aeabi.S b/src/rp2_common/pico_int64_ops/pico_int64_ops_aeabi.S
index 903820b..0dbc67c 100644
--- a/src/rp2_common/pico_int64_ops/pico_int64_ops_aeabi.S
+++ b/src/rp2_common/pico_int64_ops/pico_int64_ops_aeabi.S
@@ -10,7 +10,11 @@
#include "pico/asm_helper.S"
+#if PICO_INT64_OPS_IN_RAM
+.section RAM_SECTION_NAME(__aeabi_lmul)
+#else
.section SECTION_NAME(__aeabi_lmul)
+#endif
wrapper_func __aeabi_lmul
muls r1, r2
muls r3, r0
diff --git a/src/rp2_common/pico_malloc/CMakeLists.txt b/src/rp2_common/pico_malloc/CMakeLists.txt
index de7f858..deeb30f 100644
--- a/src/rp2_common/pico_malloc/CMakeLists.txt
+++ b/src/rp2_common/pico_malloc/CMakeLists.txt
@@ -1,6 +1,6 @@
if (NOT TARGET pico_malloc)
#shims for ROM functions for -lgcc functions (listed below)
- add_library(pico_malloc INTERFACE)
+ pico_add_impl_library(pico_malloc)
target_sources(pico_malloc INTERFACE
${CMAKE_CURRENT_LIST_DIR}/pico_malloc.c
diff --git a/src/rp2_common/pico_malloc/include/pico/malloc.h b/src/rp2_common/pico_malloc/include/pico/malloc.h
index e84dd4d..b4ae2b6 100644
--- a/src/rp2_common/pico_malloc/include/pico/malloc.h
+++ b/src/rp2_common/pico_malloc/include/pico/malloc.h
@@ -16,7 +16,7 @@
*/
// PICO_CONFIG: PICO_USE_MALLOC_MUTEX, Whether to protect malloc etc with a mutex, type=bool, default=1 with pico_multicore, 0 otherwise, group=pico_malloc
-#if PICO_MULTICORE && !defined(PICO_USE_MALLOC_MUTEX)
+#if LIB_PICO_MULTICORE && !defined(PICO_USE_MALLOC_MUTEX)
#define PICO_USE_MALLOC_MUTEX 1
#endif
diff --git a/src/rp2_common/pico_mem_ops/CMakeLists.txt b/src/rp2_common/pico_mem_ops/CMakeLists.txt
index 20d410a..997bb20 100644
--- a/src/rp2_common/pico_mem_ops/CMakeLists.txt
+++ b/src/rp2_common/pico_mem_ops/CMakeLists.txt
@@ -1,13 +1,9 @@
if (NOT TARGET pico_mem_ops)
#shims for ROM functions for -lgcc functions (listed below)
- add_library(pico_mem_ops INTERFACE)
+ pico_add_impl_library(pico_mem_ops)
# no custom implementation; falls thru to compiler
- add_library(pico_mem_ops_compiler INTERFACE)
- # PICO_BUILD_DEFINE: PICO_MEM_OPS_COMPILER, whether compiler provided mem_ops memcpy etc. support is being used, type=bool, default=0, but dependent on CMake options, group=pico_mem_ops
- target_compile_definitions(pico_mem_ops_compiler INTERFACE
- PICO_MEM_OPS_COMPILER=1
- )
+ pico_add_impl_library(pico_mem_ops_compiler)
# add alias "default" which is just pico.
add_library(pico_mem_ops_default INTERFACE)
@@ -15,16 +11,10 @@
set(PICO_DEFAULT_MEM_OPS_IMPL pico_mem_ops_default)
- add_library(pico_mem_ops_pico INTERFACE)
+ pico_add_impl_library(pico_mem_ops_pico)
target_link_libraries(pico_mem_ops INTERFACE
$<IF:$<BOOL:$<TARGET_PROPERTY:PICO_TARGET_MEM_OPS_IMPL>>,$<TARGET_PROPERTY:PICO_TARGET_MEM_OPS_IMPL>,${PICO_DEFAULT_MEM_OPS_IMPL}>)
- # PICO_BUILD_DEFINE: PICO_MEM_OPS_PICO, whether optimized pico/bootrom provided mem_ops memcpy etc. support is being used, type=bool, default=1, but dependent on CMake options, group=pico_mem_ops
- target_compile_definitions(pico_mem_ops_pico INTERFACE
- PICO_MEM_OPS_PICO=1
- )
-
-
target_sources(pico_mem_ops_pico INTERFACE
${CMAKE_CURRENT_LIST_DIR}/mem_ops_aeabi.S
)
diff --git a/src/rp2_common/pico_multicore/CMakeLists.txt b/src/rp2_common/pico_multicore/CMakeLists.txt
index 06f3782..2401061 100644
--- a/src/rp2_common/pico_multicore/CMakeLists.txt
+++ b/src/rp2_common/pico_multicore/CMakeLists.txt
@@ -1,16 +1,12 @@
if (NOT TARGET pico_multicore)
- add_library(pico_multicore INTERFACE)
+ pico_add_impl_library(pico_multicore)
target_sources(pico_multicore INTERFACE
${CMAKE_CURRENT_LIST_DIR}/multicore.c)
target_include_directories(pico_multicore INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
- target_compile_definitions(pico_multicore INTERFACE
- PICO_MULTICORE=1
- )
-
- target_link_libraries(pico_multicore INTERFACE pico_sync)
+ target_link_libraries(pico_multicore INTERFACE pico_sync hardware_irq)
endif()
diff --git a/src/rp2_common/pico_multicore/include/pico/multicore.h b/src/rp2_common/pico_multicore/include/pico/multicore.h
index 3d52654..1c91a86 100644
--- a/src/rp2_common/pico_multicore/include/pico/multicore.h
+++ b/src/rp2_common/pico_multicore/include/pico/multicore.h
@@ -24,7 +24,7 @@
* \include multicore.c
*/
-// PICO_CONFIG: PICO_CORE1_STACK_SIZE, Stack size for core 1, min=0x100, max=0x10000, default=PICO_STACK_SIZE/0x800, group=pico_multicore
+// PICO_CONFIG: PICO_CORE1_STACK_SIZE, Stack size for core 1, min=0x100, max=0x10000, default=PICO_STACK_SIZE (0x800), group=pico_multicore
#ifndef PICO_CORE1_STACK_SIZE
#ifdef PICO_STACK_SIZE
#define PICO_CORE1_STACK_SIZE PICO_STACK_SIZE
@@ -84,10 +84,10 @@
return !!(sio_hw->fifo_st & SIO_FIFO_ST_VLD_BITS);
}
-/*! \brief Check the FIFO to see if the write FIFO is full
+/*! \brief Check the write FIFO to see if it is ready for more data
* \ingroup multicore_fifo
*
- * @return true if the FIFO is full, false otherwise
+ * @return true if the FIFO has room for more data, false otherwise
*/
static inline bool multicore_fifo_wready(void) {
return !!(sio_hw->fifo_st & SIO_FIFO_ST_RDY_BITS);
@@ -119,7 +119,7 @@
bool multicore_fifo_pop_timeout_us(uint64_t timeout_us, uint32_t *out);
-/*! \brief Flush any data in the outgoing FIFO
+/*! \brief Flush any data in the incoming FIFO
* \ingroup multicore_fifo
*
*/
@@ -130,9 +130,12 @@
/*! \brief Clear FIFO interrupt
* \ingroup multicore_fifo
+ *
+ * Note that this only clears an interrupt that was caused by the ROE or WOF flags.
+ * To clear the VLD flag you need to use one of the 'pop' or 'drain' functions.
*/
static inline void multicore_fifo_clear_irq(void) {
- // Write any value to clear any interrupts
+ // Write any value to clear the error flags
sio_hw->fifo_st = 0xff;
}
diff --git a/src/rp2_common/pico_multicore/multicore.c b/src/rp2_common/pico_multicore/multicore.c
index 53be1ee..531e294 100644
--- a/src/rp2_common/pico_multicore/multicore.c
+++ b/src/rp2_common/pico_multicore/multicore.c
@@ -4,7 +4,6 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include "pico/stdlib.h"
#include "pico/multicore.h"
#include "hardware/sync.h"
#include "hardware/irq.h"
@@ -127,7 +126,10 @@
}
void multicore_launch_core1_raw(void (*entry)(void), uint32_t *sp, uint32_t vector_table) {
- uint32_t cmd_sequence[] = {0, 0, 1, (uintptr_t) vector_table, (uintptr_t) sp, (uintptr_t) entry};
+ const uint32_t cmd_sequence[] = {0, 0, 1, (uintptr_t) vector_table, (uintptr_t) sp, (uintptr_t) entry};
+
+ bool enabled = irq_is_enabled(SIO_IRQ_PROC0);
+ irq_set_enabled(SIO_IRQ_PROC0, false);
uint seq = 0;
do {
@@ -142,6 +144,8 @@
// move to next state on correct response otherwise start over
seq = cmd == response ? seq + 1 : 0;
} while (seq < count_of(cmd_sequence));
+
+ irq_set_enabled(SIO_IRQ_PROC0, enabled);
}
#define LOCKOUT_MAGIC_START 0x73a8831eu
diff --git a/src/rp2_common/pico_platform/CMakeLists.txt b/src/rp2_common/pico_platform/CMakeLists.txt
index 00000f3..8a6f1d2 100644
--- a/src/rp2_common/pico_platform/CMakeLists.txt
+++ b/src/rp2_common/pico_platform/CMakeLists.txt
@@ -13,7 +13,7 @@
endif()
if (NOT TARGET pico_platform)
- add_library(pico_platform INTERFACE)
+ pico_add_impl_library(pico_platform)
target_sources(pico_platform INTERFACE
${CMAKE_CURRENT_LIST_DIR}/platform.c)
diff --git a/src/rp2_common/pico_platform/include/pico/platform.h b/src/rp2_common/pico_platform/include/pico/platform.h
index e17dbca..c008b95 100644
--- a/src/rp2_common/pico_platform/include/pico/platform.h
+++ b/src/rp2_common/pico_platform/include/pico/platform.h
@@ -45,10 +45,15 @@
* Decorates a function name, such that the function will execute from RAM, explicitly marking it as
* noinline to prevent it being inlined into a flash function by the compiler
*/
-#define __no_inline_not_in_flash_func(func_name) __attribute__((noinline)) __not_in_flash_func(func_name)
+#define __no_inline_not_in_flash_func(func_name) __noinline __not_in_flash_func(func_name)
#define __packed_aligned __packed __aligned(4)
+#if defined(__GNUC__) && __GNUC__ < 7
+#define __force_inline inline __always_inline
+#else
+#define __force_inline __always_inline
+#endif
#ifndef count_of
#define count_of(a) (sizeof(a)/sizeof((a)[0]))
#endif
@@ -71,7 +76,7 @@
/**
* Ensure that the compiler does not move memory access across this method call
*/
-static inline void __compiler_memory_barrier(void) {
+__force_inline static void __compiler_memory_barrier(void) {
__asm__ volatile ("" : : : "memory");
}
@@ -140,9 +145,9 @@
* \param b the second operand
* \return a * b
*/
-inline static int32_t __mul_instruction(int32_t a, int32_t b) {
-asm ("mul %0, %1" : "+l" (a) : "l" (b) : );
-return a;
+__force_inline static int32_t __mul_instruction(int32_t a, int32_t b) {
+ asm ("mul %0, %1" : "+l" (a) : "l" (b) : );
+ return a;
}
/**
@@ -167,7 +172,7 @@
* Get the current exception level on this core
* \return the exception number if the CPU is handling an exception, or 0 otherwise
*/
-extern uint __get_current_exception(void);
+uint __get_current_exception(void);
#ifdef __cplusplus
}
diff --git a/src/rp2_common/pico_printf/CMakeLists.txt b/src/rp2_common/pico_printf/CMakeLists.txt
index cf2082e..989dcd1 100644
--- a/src/rp2_common/pico_printf/CMakeLists.txt
+++ b/src/rp2_common/pico_printf/CMakeLists.txt
@@ -1,12 +1,9 @@
if (NOT TARGET pico_printf)
# library to be depended on - we make this depend on particular implementations using per target generator expressions
- add_library(pico_printf INTERFACE)
+ pico_add_impl_library(pico_printf)
# no custom implementation; falls thru to compiler
- add_library(pico_printf_compiler INTERFACE)
- target_compile_definitions(pico_printf_compiler INTERFACE
- PICO_PRINTF_COMPILER=1
- )
+ pico_add_impl_library(pico_printf_compiler)
add_library(pico_printf_headers INTERFACE)
target_include_directories(pico_printf_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
@@ -20,28 +17,20 @@
target_link_libraries(pico_printf INTERFACE
$<IF:$<BOOL:$<TARGET_PROPERTY:PICO_TARGET_PRINTF_IMPL>>,$<TARGET_PROPERTY:PICO_TARGET_PRINTF_IMPL>,${PICO_DEFAULT_PRINTF_IMPL}>)
- add_library(pico_printf_pico INTERFACE)
+ pico_add_impl_library(pico_printf_pico)
target_sources(pico_printf_pico INTERFACE
${CMAKE_CURRENT_LIST_DIR}/printf.c
)
- target_compile_definitions(pico_printf_pico INTERFACE
- PICO_PRINTF_PICO=1
- )
-
target_link_libraries(pico_printf_pico INTERFACE pico_printf_headers)
- add_library(pico_printf_none INTERFACE)
+ pico_add_impl_library(pico_printf_none)
target_sources(pico_printf_none INTERFACE
${CMAKE_CURRENT_LIST_DIR}/printf_none.S
)
target_link_libraries(pico_printf_none INTERFACE pico_printf_headers)
- target_compile_definitions(pico_printf_none INTERFACE
- PICO_PRINTF_NONE=1
- )
-
function(wrap_printf_functions TARGET)
# note that printf and vprintf are in pico_stdio so we can provide thread safety
pico_wrap_function(${TARGET} sprintf)
diff --git a/src/rp2_common/pico_printf/include/pico/printf.h b/src/rp2_common/pico_printf/include/pico/printf.h
index 6a82b8d..25cea48 100644
--- a/src/rp2_common/pico_printf/include/pico/printf.h
+++ b/src/rp2_common/pico_printf/include/pico/printf.h
@@ -55,7 +55,7 @@
#endif
#endif
-#if PICO_PRINTF_PICO
+#if LIB_PICO_PRINTF_PICO
// weak raw printf may be a puts if printf has not been called,
// so that we can support gc of printf when it isn't called
//
diff --git a/src/rp2_common/pico_printf/printf.c b/src/rp2_common/pico_printf/printf.c
index b8f3cb1..2594c57 100644
--- a/src/rp2_common/pico_printf/printf.c
+++ b/src/rp2_common/pico_printf/printf.c
@@ -51,13 +51,13 @@
#define PICO_PRINTF_FTOA_BUFFER_SIZE 32U
#endif
-// PICO_CONFIG: PICO_PRINTF_SUPPORT_FLOAT, Enable floating point printing, default=1, group=pico_printf
+// PICO_CONFIG: PICO_PRINTF_SUPPORT_FLOAT, Enable floating point printing, type=bool, default=1, group=pico_printf
// support for the floating point type (%f)
#ifndef PICO_PRINTF_SUPPORT_FLOAT
#define PICO_PRINTF_SUPPORT_FLOAT 1
#endif
-// PICO_CONFIG: PICO_PRINTF_SUPPORT_EXPONENTIAL, Enable exponential floating point printing, default=1, group=pico_printf
+// PICO_CONFIG: PICO_PRINTF_SUPPORT_EXPONENTIAL, Enable exponential floating point printing, type=bool, default=1, group=pico_printf
// support for exponential floating point notation (%e/%g)
#ifndef PICO_PRINTF_SUPPORT_EXPONENTIAL
#define PICO_PRINTF_SUPPORT_EXPONENTIAL 1
@@ -73,12 +73,12 @@
#define PICO_PRINTF_MAX_FLOAT 1e9
#endif
-// PICO_CONFIG: PICO_PRINTF_SUPPORT_LONG_LONG, Enable support for long long types (%llu or %p), default=1, group=pico_printf
+// PICO_CONFIG: PICO_PRINTF_SUPPORT_LONG_LONG, Enable support for long long types (%llu or %p), type=bool, default=1, group=pico_printf
#ifndef PICO_PRINTF_SUPPORT_LONG_LONG
#define PICO_PRINTF_SUPPORT_LONG_LONG 1
#endif
-// PICO_CONFIG: PICO_PRINTF_SUPPORT_PTRDIFF_T, Enable support for the ptrdiff_t type (%t), default=1, group=pico_printf
+// PICO_CONFIG: PICO_PRINTF_SUPPORT_PTRDIFF_T, Enable support for the ptrdiff_t type (%t), type=bool, default=1, group=pico_printf
// ptrdiff_t is normally defined in <stddef.h> as long or long long type
#ifndef PICO_PRINTF_SUPPORT_PTRDIFF_T
#define PICO_PRINTF_SUPPORT_PTRDIFF_T 1
@@ -918,7 +918,7 @@
return _vsnprintf(_out_fct, (char *) (uintptr_t) &out_fct_wrap, (size_t) -1, format, va);
}
-#if PICO_PRINTF_PICO
+#if LIB_PICO_PRINTF_PICO
#if !PICO_PRINTF_ALWAYS_INCLUDED
bool weak_raw_printf(const char *fmt, ...) {
va_list va;
diff --git a/src/rp2_common/pico_runtime/CMakeLists.txt b/src/rp2_common/pico_runtime/CMakeLists.txt
index 83c08f6..3b6cc18 100644
--- a/src/rp2_common/pico_runtime/CMakeLists.txt
+++ b/src/rp2_common/pico_runtime/CMakeLists.txt
@@ -1,4 +1,4 @@
-add_library(pico_runtime INTERFACE)
+pico_add_impl_library(pico_runtime)
target_sources(pico_runtime INTERFACE
${CMAKE_CURRENT_LIST_DIR}/runtime.c
diff --git a/src/rp2_common/pico_runtime/runtime.c b/src/rp2_common/pico_runtime/runtime.c
index 2340ba7..6628934 100644
--- a/src/rp2_common/pico_runtime/runtime.c
+++ b/src/rp2_common/pico_runtime/runtime.c
@@ -63,10 +63,13 @@
// Reset all peripherals to put system into a known state,
// - except for QSPI pads and the XIP IO bank, as this is fatal if running from flash
// - and the PLLs, as this is fatal if clock muxing has not been reset on this boot
+ // - and USB, syscfg, as this disturbs USB-to-SWD on core 1
reset_block(~(
RESETS_RESET_IO_QSPI_BITS |
RESETS_RESET_PADS_QSPI_BITS |
RESETS_RESET_PLL_USB_BITS |
+ RESETS_RESET_USBCTRL_BITS |
+ RESETS_RESET_SYSCFG_BITS |
RESETS_RESET_PLL_SYS_BITS
));
@@ -115,7 +118,11 @@
// the first function pointer, not the address of it.
for (mutex_t *m = &__mutex_array_start; m < &__mutex_array_end; m++) {
- mutex_init(m);
+ if (m->recursion_state) {
+ recursive_mutex_init(m);
+ } else {
+ mutex_init(m);
+ }
}
#if !(PICO_NO_RAM_VECTOR_TABLE || PICO_NO_FLASH)
@@ -213,16 +220,38 @@
panic("not supported");
}
+// PICO_CONFIG: PICO_PANIC_FUNCTION, Name of a function to use in place of the stock panic function or empty string to simply breakpoint on panic, group=pico_runtime
+// note the default is not "panic" it is undefined
+#ifdef PICO_PANIC_FUNCTION
+#define PICO_PANIC_FUNCTION_EMPTY (__CONCAT(PICO_PANIC_FUNCTION, 1) == 1)
+#if !PICO_PANIC_FUNCTION_EMPTY
+extern void __attribute__((noreturn)) __printflike(1, 0) PICO_PANIC_FUNCTION(__unused const char *fmt, ...);
+#endif
+// Use a forwarding method here as it is a little simpler than renaming the symbol as it is used from assembler
+void __attribute__((naked, noreturn)) __printflike(1, 0) panic(__unused const char *fmt, ...) {
+ // if you get an undefined reference here, you didn't define your PICO_PANIC_FUNCTION!
+ asm (
+ "push {lr}\n"
+#if !PICO_PANIC_FUNCTION_EMPTY
+ "bl " __XSTRING(PICO_PANIC_FUNCTION) "\n"
+#endif
+ "bkpt #0\n"
+ "1: b 1b\n" // loop for ever as we are no return
+ :
+ :
+ :
+ );
+}
+#else
// todo consider making this try harder to output if we panic early
// right now, print mutex may be uninitialised (in which case it deadlocks - although after printing "PANIC")
// more importantly there may be no stdout/UART initialized yet
// todo we may want to think about where we print panic messages to; writing to USB appears to work
// though it doesn't seem like we can expect it to... fine for now
-//
void __attribute__((noreturn)) __printflike(1, 0) panic(const char *fmt, ...) {
puts("\n*** PANIC ***\n");
if (fmt) {
-#if PICO_PRINTF_NONE
+#if LIB_PICO_PRINTF_NONE
puts(fmt);
#else
va_list args;
@@ -239,6 +268,7 @@
_exit(1);
}
+#endif
void hard_assertion_failure(void) {
panic("Hard assert");
diff --git a/src/rp2_common/pico_standard_link/CMakeLists.txt b/src/rp2_common/pico_standard_link/CMakeLists.txt
index c58096d..78de372 100644
--- a/src/rp2_common/pico_standard_link/CMakeLists.txt
+++ b/src/rp2_common/pico_standard_link/CMakeLists.txt
@@ -1,5 +1,5 @@
if (NOT TARGET pico_standard_link)
- add_library(pico_standard_link INTERFACE)
+ pico_add_impl_library(pico_standard_link)
target_sources(pico_standard_link INTERFACE
${CMAKE_CURRENT_LIST_DIR}/crt0.S
diff --git a/src/rp2_common/pico_standard_link/crt0.S b/src/rp2_common/pico_standard_link/crt0.S
index 95a44ff..4134f0b 100644
--- a/src/rp2_common/pico_standard_link/crt0.S
+++ b/src/rp2_common/pico_standard_link/crt0.S
@@ -9,6 +9,7 @@
#include "hardware/regs/addressmap.h"
#include "hardware/regs/sio.h"
#include "pico/binary_info/defs.h"
+#include "pico/config.h"
#ifdef NDEBUG
#ifndef COLLAPSE_IRQS
@@ -23,7 +24,8 @@
.section .vectors, "ax"
.align 2
-.global __vectors
+.global __vectors, __VECTOR_TABLE
+__VECTOR_TABLE:
__vectors:
.word __StackTop
.word _reset_handler
@@ -74,6 +76,11 @@
.word isr_irq30
.word isr_irq31
+// all default exception handlers do nothing, and we can check for them being set to our
+// default values by seeing if they point to somewhere between __defaults_isrs_start and __default_isrs_end
+.global __default_isrs_start
+__default_isrs_start:
+
// Declare a weak symbol for each ISR.
// By default, they will fall through to the undefined IRQ handler below (breakpoint),
// but can be overridden by C functions with correct name.
@@ -94,6 +101,9 @@
decl_isr_bkpt isr_pendsv
decl_isr_bkpt isr_systick
+.global __default_isrs_end
+__default_isrs_end:
+
.macro decl_isr name
.weak \name
.type \name,%function
diff --git a/src/rp2_common/pico_standard_link/new_delete.cpp b/src/rp2_common/pico_standard_link/new_delete.cpp
index a7dd3b0..c122dc0 100644
--- a/src/rp2_common/pico_standard_link/new_delete.cpp
+++ b/src/rp2_common/pico_standard_link/new_delete.cpp
@@ -17,10 +17,16 @@
return std::malloc(n);
}
-void operator delete(void *p, __unused std::size_t n) noexcept { std::free(p); }
-
void operator delete(void *p) { std::free(p); }
void operator delete[](void *p) noexcept { std::free(p); }
+#if __cpp_sized_deallocation
+
+void operator delete(void *p, __unused std::size_t n) noexcept { std::free(p); }
+
+void operator delete[](void *p, __unused std::size_t n) noexcept { std::free(p); }
+
+#endif
+
#endif
diff --git a/src/rp2_common/pico_stdio/CMakeLists.txt b/src/rp2_common/pico_stdio/CMakeLists.txt
index 15ca07b..cdc9c3b 100644
--- a/src/rp2_common/pico_stdio/CMakeLists.txt
+++ b/src/rp2_common/pico_stdio/CMakeLists.txt
@@ -1,5 +1,5 @@
if (NOT TARGET pico_stdio)
- add_library(pico_stdio INTERFACE)
+ pico_add_impl_library(pico_stdio)
target_include_directories(pico_stdio INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
@@ -11,6 +11,7 @@
pico_wrap_function(pico_stdio vprintf)
pico_wrap_function(pico_stdio puts)
pico_wrap_function(pico_stdio putchar)
+ pico_wrap_function(pico_stdio getchar)
if (TARGET pico_printf)
target_link_libraries(pico_stdio INTERFACE pico_printf)
diff --git a/src/rp2_common/pico_stdio/include/pico/stdio.h b/src/rp2_common/pico_stdio/include/pico/stdio.h
index a895875..9f01ae9 100644
--- a/src/rp2_common/pico_stdio/include/pico/stdio.h
+++ b/src/rp2_common/pico_stdio/include/pico/stdio.h
@@ -47,7 +47,7 @@
* \ingroup pico_stdio
*
* Call this method once you have set up your clocks to enable the stdio support for UART, USB
- * and semihosting based on the presence of the respective librariess in the binary.
+ * and semihosting based on the presence of the respective libraries in the binary.
*
* \see stdio_uart, stdio_usb, stdio_semihosting
*/
@@ -57,7 +57,7 @@
* \ingroup pico_stdio
*
* Call this method once you have set up your clocks to enable the stdio support for UART, USB
- * and semihosting based on the presence of the respective librariess in the binary.
+ * and semihosting based on the presence of the respective libraries in the binary.
*
* \see stdio_uart, stdio_usb, stdio_semihosting
*/
diff --git a/src/rp2_common/pico_stdio/stdio.c b/src/rp2_common/pico_stdio/stdio.c
index 074f288..4f520ca 100644
--- a/src/rp2_common/pico_stdio/stdio.c
+++ b/src/rp2_common/pico_stdio/stdio.c
@@ -15,15 +15,15 @@
#include "pico/stdio/driver.h"
#include "pico/time.h"
-#if PICO_STDIO_UART
+#if LIB_PICO_STDIO_UART
#include "pico/stdio_uart.h"
#endif
-#if PICO_STDIO_USB
+#if LIB_PICO_STDIO_USB
#include "pico/stdio_usb.h"
#endif
-#if PICO_STDIO_SEMIHOSTING
+#if LIB_PICO_STDIO_SEMIHOSTING
#include "pico/stdio_semihosting.h"
#endif
@@ -34,13 +34,15 @@
auto_init_mutex(print_mutex);
bool stdout_serialize_begin(void) {
- uint core_num = get_core_num();
+ lock_owner_id_t caller = lock_get_caller_owner_id();
+ // not using lock_owner_id_t to avoid backwards incompatibility change to mutex_try_enter API
+ static_assert(sizeof(lock_owner_id_t) <= 4, "");
uint32_t owner;
if (!mutex_try_enter(&print_mutex, &owner)) {
- if (owner == core_num) {
+ if (owner == (uint32_t)caller) {
return false;
}
- // other core owns the mutex, so lets wait
+ // we are not a nested call, so lets wait
mutex_enter_blocking(&print_mutex);
}
return true;
@@ -88,8 +90,8 @@
}
static bool stdio_put_string(const char *s, int len, bool newline) {
- bool serialzed = stdout_serialize_begin();
- if (!serialzed) {
+ bool serialized = stdout_serialize_begin();
+ if (!serialized) {
#if PICO_STDIO_IGNORE_NESTED_STDOUT
return false;
#endif
@@ -104,7 +106,7 @@
stdio_out_chars_crlf(driver, &c, 1);
}
}
- if (serialzed) {
+ if (serialized) {
stdout_serialize_end();
}
return len;
@@ -123,7 +125,9 @@
}
}
}
- // todo maybe a little sleep here?
+ // we sleep here in case the in_chars methods acquire mutexes or disable IRQs and
+ // potentially starve out what they are waiting on (have seen this with USB)
+ busy_wait_us(1);
} while (!time_reached(until));
return PICO_ERROR_TIMEOUT;
}
@@ -212,12 +216,12 @@
#endif
}
int ret;
-#if PICO_PRINTF_PICO
+#if LIB_PICO_PRINTF_PICO
struct stdio_stack_buffer buffer = {.used = 0};
ret = vfctprintf(stdio_buffered_printer, &buffer, format, va);
stdio_stack_buffer_flush(&buffer);
stdio_flush();
-#elif PICO_PRINTF_NONE
+#elif LIB_PICO_PRINTF_NONE
extern void printf_none_assert();
printf_none_assert();
#else
@@ -242,24 +246,24 @@
void stdio_init_all() {
// todo add explicit custom, or registered although you can call stdio_enable_driver explicitly anyway
// These are well known ones
-#if PICO_STDIO_UART
+#if LIB_PICO_STDIO_UART
stdio_uart_init();
#endif
-#if PICO_STDIO_SEMIHOSTING
+#if LIB_PICO_STDIO_SEMIHOSTING
stdio_semihosting_init();
#endif
-#if PICO_STDIO_USB
+#if LIB_PICO_STDIO_USB
stdio_usb_init();
#endif
}
int WRAPPER_FUNC(getchar)(void) {
char buf[1];
- if (0 == stdio_get_until(buf, sizeof(buf), at_the_end_of_time)) {
- return PICO_ERROR_TIMEOUT;
- }
+ int len = stdio_get_until(buf, 1, at_the_end_of_time);
+ if (len < 0) return len;
+ assert(len == 1);
return (uint8_t)buf[0];
}
diff --git a/src/rp2_common/pico_stdio_semihosting/CMakeLists.txt b/src/rp2_common/pico_stdio_semihosting/CMakeLists.txt
index c65aa91..699170e 100644
--- a/src/rp2_common/pico_stdio_semihosting/CMakeLists.txt
+++ b/src/rp2_common/pico_stdio_semihosting/CMakeLists.txt
@@ -1,4 +1,4 @@
-add_library(pico_stdio_semihosting INTERFACE)
+pico_add_impl_library(pico_stdio_semihosting)
target_sources(pico_stdio_semihosting INTERFACE
${CMAKE_CURRENT_LIST_DIR}/stdio_semihosting.c
@@ -6,8 +6,4 @@
target_include_directories(pico_stdio_semihosting INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
-target_compile_definitions(pico_stdio_semihosting INTERFACE
- PICO_STDIO_SEMIHOSTING=1
-)
-
target_link_libraries(pico_stdio_semihosting INTERFACE pico_stdio)
\ No newline at end of file
diff --git a/src/rp2_common/pico_stdio_uart/CMakeLists.txt b/src/rp2_common/pico_stdio_uart/CMakeLists.txt
index 1103366..d10507b 100644
--- a/src/rp2_common/pico_stdio_uart/CMakeLists.txt
+++ b/src/rp2_common/pico_stdio_uart/CMakeLists.txt
@@ -1,4 +1,4 @@
-add_library(pico_stdio_uart INTERFACE)
+pico_add_impl_library(pico_stdio_uart)
target_sources(pico_stdio_uart INTERFACE
${CMAKE_CURRENT_LIST_DIR}/stdio_uart.c
@@ -6,8 +6,4 @@
target_include_directories(pico_stdio_uart INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
-target_compile_definitions(pico_stdio_uart INTERFACE
- PICO_STDIO_UART=1
-)
-
target_link_libraries(pico_stdio_uart INTERFACE pico_stdio)
\ No newline at end of file
diff --git a/src/rp2_common/pico_stdio_usb/CMakeLists.txt b/src/rp2_common/pico_stdio_usb/CMakeLists.txt
index 8bc8853..2e33f5a 100644
--- a/src/rp2_common/pico_stdio_usb/CMakeLists.txt
+++ b/src/rp2_common/pico_stdio_usb/CMakeLists.txt
@@ -1,5 +1,5 @@
if (TARGET tinyusb_device_unmarked)
- add_library(pico_stdio_usb INTERFACE)
+ pico_add_impl_library(pico_stdio_usb)
target_include_directories(pico_stdio_usb INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
@@ -13,9 +13,6 @@
tinyusb_device_unmarked
pico_stdio
pico_time
+ pico_unique_id
)
-
- target_compile_definitions(pico_stdio_usb INTERFACE
- PICO_STDIO_USB=1
- )
-endif()
\ No newline at end of file
+endif()
diff --git a/src/rp2_common/pico_stdio_usb/reset_interface.c b/src/rp2_common/pico_stdio_usb/reset_interface.c
index 1232857..2f2e72b 100644
--- a/src/rp2_common/pico_stdio_usb/reset_interface.c
+++ b/src/rp2_common/pico_stdio_usb/reset_interface.c
@@ -38,7 +38,10 @@
}
// Support for parameterized reset via vendor interface control request
-static bool resetd_control_request_cb(uint8_t __unused rhport, tusb_control_request_t const *request) {
+static bool resetd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request) {
+ // nothing to do with DATA & ACK stage
+ if (stage != CONTROL_STAGE_SETUP) return true;
+
if (request->wIndex == itf_num) {
#if PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_BOOTSEL
@@ -69,10 +72,6 @@
return false;
}
-static bool resetd_control_complete_cb(uint8_t __unused rhport, tusb_control_request_t __unused const *request) {
- return true;
-}
-
static bool resetd_xfer_cb(uint8_t __unused rhport, uint8_t __unused ep_addr, xfer_result_t __unused result, uint32_t __unused xferred_bytes) {
return true;
}
@@ -85,8 +84,7 @@
.init = resetd_init,
.reset = resetd_reset,
.open = resetd_open,
- .control_request = resetd_control_request_cb,
- .control_complete = resetd_control_complete_cb,
+ .control_xfer_cb = resetd_control_xfer_cb,
.xfer_cb = resetd_xfer_cb,
.sof = NULL
};
@@ -100,7 +98,7 @@
#if PICO_STDIO_USB_ENABLE_RESET_VIA_BAUD_RATE
// Support for default BOOTSEL reset by changing baud rate
-void tud_cdc_line_coding_cb(uint8_t itf, cdc_line_coding_t const* p_line_coding) {
+void tud_cdc_line_coding_cb(__unused uint8_t itf, cdc_line_coding_t const* p_line_coding) {
if (p_line_coding->bit_rate == PICO_STDIO_USB_RESET_MAGIC_BAUD_RATE) {
#ifdef PICO_STDIO_USB_RESET_BOOTSEL_ACTIVITY_LED
const uint gpio_mask = 1u << PICO_STDIO_USB_RESET_BOOTSEL_ACTIVITY_LED;
diff --git a/src/rp2_common/pico_stdio_usb/stdio_usb.c b/src/rp2_common/pico_stdio_usb/stdio_usb.c
index d86879f..2cca2c2 100644
--- a/src/rp2_common/pico_stdio_usb/stdio_usb.c
+++ b/src/rp2_common/pico_stdio_usb/stdio_usb.c
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#if !defined(TINYUSB_HOST_LINKED) && !defined(TINYUSB_DEVICE_LINKED)
+#if !defined(LIB_TINYUSB_HOST) && !defined(LIB_TINYUSB_DEVICE)
#include "tusb.h"
#include "pico/time.h"
diff --git a/src/rp2_common/pico_stdio_usb/stdio_usb_descriptors.c b/src/rp2_common/pico_stdio_usb/stdio_usb_descriptors.c
index 622a1fc..d06d700 100644
--- a/src/rp2_common/pico_stdio_usb/stdio_usb_descriptors.c
+++ b/src/rp2_common/pico_stdio_usb/stdio_usb_descriptors.c
@@ -26,10 +26,11 @@
* THE SOFTWARE.
*/
-#if !defined(TINYUSB_HOST_LINKED) && !defined(TINYUSB_DEVICE_LINKED)
+#if !defined(LIB_TINYUSB_HOST) && !defined(LIB_TINYUSB_DEVICE)
#include "tusb.h"
#include "pico/stdio_usb/reset_interface.h"
+#include "pico/unique_id.h"
#define USBD_VID (0x2E8A) // Raspberry Pi
#define USBD_PID (0x000a) // Raspberry Pi Pico SDK CDC
@@ -98,10 +99,12 @@
#endif
};
+static char usbd_serial_str[PICO_UNIQUE_BOARD_ID_SIZE_BYTES * 2 + 1];
+
static const char *const usbd_desc_str[] = {
[USBD_STR_MANUF] = "Raspberry Pi",
[USBD_STR_PRODUCT] = "Pico",
- [USBD_STR_SERIAL] = "000000000000", // TODO
+ [USBD_STR_SERIAL] = usbd_serial_str,
[USBD_STR_CDC] = "Board CDC",
#if PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE
[USBD_STR_RPI_RESET] = "Reset",
@@ -112,15 +115,19 @@
return (const uint8_t *)&usbd_desc_device;
}
-const uint8_t *tud_descriptor_configuration_cb(uint8_t index) {
- (void)index;
+const uint8_t *tud_descriptor_configuration_cb(__unused uint8_t index) {
return usbd_desc_cfg;
}
-const uint16_t *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+const uint16_t *tud_descriptor_string_cb(uint8_t index, __unused uint16_t langid) {
#define DESC_STR_MAX (20)
static uint16_t desc_str[DESC_STR_MAX];
+ // Assign the SN using the unique flash id
+ if (!usbd_serial_str[0]) {
+ pico_get_unique_board_id_string(usbd_serial_str, sizeof(usbd_serial_str));
+ }
+
uint8_t len;
if (index == 0) {
desc_str[1] = 0x0409; // supported language is English
@@ -141,4 +148,4 @@
return desc_str;
}
-#endif
\ No newline at end of file
+#endif
diff --git a/src/rp2_common/pico_stdlib/CMakeLists.txt b/src/rp2_common/pico_stdlib/CMakeLists.txt
index 900ae09..b54639b 100644
--- a/src/rp2_common/pico_stdlib/CMakeLists.txt
+++ b/src/rp2_common/pico_stdlib/CMakeLists.txt
@@ -6,7 +6,7 @@
option(PICO_STDIO_USB "Globablly enable stdio semihosting " 0)
if (NOT TARGET pico_stdlib)
- add_library(pico_stdlib INTERFACE)
+ pico_add_impl_library(pico_stdlib)
target_sources(pico_stdlib INTERFACE
${CMAKE_CURRENT_LIST_DIR}/stdlib.c
)
diff --git a/src/rp2_common/pico_stdlib/stdlib.c b/src/rp2_common/pico_stdlib/stdlib.c
index 28d5d38..7c9854e 100644
--- a/src/rp2_common/pico_stdlib/stdlib.c
+++ b/src/rp2_common/pico_stdlib/stdlib.c
@@ -7,7 +7,7 @@
#include "pico/stdlib.h"
#include "hardware/pll.h"
#include "hardware/clocks.h"
-#if PICO_STDIO_UART
+#if LIB_PICO_STDIO_UART
#include "pico/stdio_uart.h"
#else
#include "pico/binary_info.h"
@@ -90,7 +90,7 @@
}
void setup_default_uart() {
-#if PICO_STDIO_UART
+#if LIB_PICO_STDIO_UART
stdio_uart_init();
#elif defined(PICO_DEFAULT_UART_BAUD_RATE) && defined(PICO_DEFAULT_UART_TX_PIN) && defined(PICO_DEFAULT_UART_RX_PIN)
// this is mostly for backwards compatibility - stdio_uart_init is a bit more nuanced, and usually likely to be present
diff --git a/src/rp2_common/pico_unique_id/CMakeLists.txt b/src/rp2_common/pico_unique_id/CMakeLists.txt
index 4c367d7..4c69074 100644
--- a/src/rp2_common/pico_unique_id/CMakeLists.txt
+++ b/src/rp2_common/pico_unique_id/CMakeLists.txt
@@ -1,4 +1,4 @@
-add_library(pico_unique_id INTERFACE)
+pico_add_impl_library(pico_unique_id)
target_sources(pico_unique_id INTERFACE
${CMAKE_CURRENT_LIST_DIR}/unique_id.c
diff --git a/src/rp2_common/pico_unique_id/include/pico/unique_id.h b/src/rp2_common/pico_unique_id/include/pico/unique_id.h
index be956ca..31b09ed 100644
--- a/src/rp2_common/pico_unique_id/include/pico/unique_id.h
+++ b/src/rp2_common/pico_unique_id/include/pico/unique_id.h
@@ -57,6 +57,21 @@
*/
void pico_get_unique_board_id(pico_unique_board_id_t *id_out);
+/*! \brief Get unique ID in string format
+ * \ingroup pico_unique_id
+ *
+ * Get the unique 64-bit device identifier which was retrieved from the
+ * external NOR flash device at boot, formatted as an ASCII hex string.
+ * Will always 0-terminate.
+ *
+ * On PICO_NO_FLASH builds the unique identifier is set to all 0xEE.
+ *
+ * \param id_out a pointer to a char buffer of size len, to which the identifier will be written
+ * \param len the size of id_out. For full serial, len >= 2 * PICO_UNIQUE_BOARD_ID_SIZE_BYTES + 1
+ */
+void pico_get_unique_board_id_string(char *id_out, uint len);
+
+
#ifdef __cplusplus
}
#endif
diff --git a/src/rp2_common/pico_unique_id/unique_id.c b/src/rp2_common/pico_unique_id/unique_id.c
index fb39fb2..2e652c8 100644
--- a/src/rp2_common/pico_unique_id/unique_id.c
+++ b/src/rp2_common/pico_unique_id/unique_id.c
@@ -26,3 +26,14 @@
void pico_get_unique_board_id(pico_unique_board_id_t *id_out) {
*id_out = retrieved_id;
}
+
+void pico_get_unique_board_id_string(char *id_out, uint len) {
+ assert(len > 0);
+ size_t i;
+ // Generate hex one nibble at a time
+ for (i = 0; (i < len - 1) && (i < PICO_UNIQUE_BOARD_ID_SIZE_BYTES * 2); i++) {
+ int nibble = (retrieved_id.id[i/2] >> (4 - 4 * (i&1))) & 0xf;
+ id_out[i] = (char)(nibble < 10 ? nibble + '0' : nibble + 'A' - 10);
+ }
+ id_out[i] = 0;
+}
diff --git a/src/rp2_common/tinyusb/CMakeLists.txt b/src/rp2_common/tinyusb/CMakeLists.txt
index db18397..c4d238d 100644
--- a/src/rp2_common/tinyusb/CMakeLists.txt
+++ b/src/rp2_common/tinyusb/CMakeLists.txt
@@ -17,95 +17,32 @@
if (EXISTS ${PICO_TINYUSB_PATH}/${TINYUSB_TEST_PATH})
message("TinyUSB available at ${PICO_TINYUSB_PATH}/${TINYUSB_TEST_PATH}; adding USB support.")
+ pico_register_common_scope_var(PICO_TINYUSB_PATH)
+
+ set(BOARD pico_sdk)
+ include(${PICO_TINYUSB_PATH}/hw/bsp/rp2040/family.cmake)
+
add_library(tinyusb_common INTERFACE)
- target_link_libraries(tinyusb_common INTERFACE
- hardware_structs
- hardware_irq
- hardware_resets
- pico_sync
- )
-
- target_sources(tinyusb_common INTERFACE
- ${PICO_TINYUSB_PATH}/src/tusb.c
- ${PICO_TINYUSB_PATH}/src/common/tusb_fifo.c
- )
-
- set(TINYUSB_DEBUG_LEVEL 0)
- if (CMAKE_BUILD_TYPE STREQUAL "Debug")
- message("Compiling TinyUSB with CFG_TUSB_DEBUG=1")
- set(TINYUSB_DEBUG_LEVEL 1)
- endif ()
-
- target_compile_definitions(tinyusb_common INTERFACE
- CFG_TUSB_MCU=OPT_MCU_RP2040
- CFG_TUSB_OS=OPT_OS_PICO #seems examples are hard coded to OPT_OS_NONE
- CFG_TUSB_DEBUG=${TINYUSB_DEBUG_LEVEL}
- )
-
- target_include_directories(tinyusb_common INTERFACE
- ${PICO_TINYUSB_PATH}/src
- ${PICO_TINYUSB_PATH}/src/common
- ${PICO_TINYUSB_PATH}/hw
- )
+ target_link_libraries(tinyusb_common INTERFACE tinyusb_common_base)
add_library(tinyusb_device_unmarked INTERFACE)
- target_sources(tinyusb_device_unmarked INTERFACE
- ${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/dcd_rp2040.c
- ${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/rp2040_usb.c
- ${PICO_TINYUSB_PATH}/src/device/usbd.c
- ${PICO_TINYUSB_PATH}/src/device/usbd_control.c
- ${PICO_TINYUSB_PATH}/src/class/audio/audio_device.c
- ${PICO_TINYUSB_PATH}/src/class/cdc/cdc_device.c
- ${PICO_TINYUSB_PATH}/src/class/dfu/dfu_rt_device.c
- ${PICO_TINYUSB_PATH}/src/class/hid/hid_device.c
- ${PICO_TINYUSB_PATH}/src/class/midi/midi_device.c
- ${PICO_TINYUSB_PATH}/src/class/msc/msc_device.c
- ${PICO_TINYUSB_PATH}/src/class/net/net_device.c
- ${PICO_TINYUSB_PATH}/src/class/usbtmc/usbtmc_device.c
- ${PICO_TINYUSB_PATH}/src/class/vendor/vendor_device.c
- )
-
+ target_link_libraries(tinyusb_device_unmarked INTERFACE tinyusb_device_base)
target_compile_definitions(tinyusb_device_unmarked INTERFACE
# off by default note TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX defaults from PICO_RP2040_USB_DEVICE_ENUMERATION_FIX
# TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX=1
)
# unmarked version used by stdio USB
- target_link_libraries(tinyusb_device_unmarked INTERFACE tinyusb_common pico_fix_rp2040_usb_device_enumeration)
+ target_link_libraries(tinyusb_device_unmarked INTERFACE tinyusb_common pico_fix_rp2040_usb_device_enumeration tinyusb_device_base)
- add_library(tinyusb_device INTERFACE)
+ pico_add_impl_library(tinyusb_device)
target_link_libraries(tinyusb_device INTERFACE tinyusb_device_unmarked)
- target_compile_definitions(tinyusb_device INTERFACE
- RP2040_USB_DEVICE_MODE=1
- TINYUSB_DEVICE_LINKED=1
- )
- add_library(tinyusb_host INTERFACE)
- target_sources(tinyusb_host INTERFACE
- ${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/hcd_rp2040.c
- ${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/rp2040_usb.c
- ${PICO_TINYUSB_PATH}/src/host/usbh.c
- ${PICO_TINYUSB_PATH}/src/host/usbh_control.c
- ${PICO_TINYUSB_PATH}/src/host/hub.c
- ${PICO_TINYUSB_PATH}/src/class/cdc/cdc_host.c
- ${PICO_TINYUSB_PATH}/src/class/hid/hid_host.c
- ${PICO_TINYUSB_PATH}/src/class/msc/msc_host.c
- ${PICO_TINYUSB_PATH}/src/class/vendor/vendor_host.c
- )
+ pico_add_impl_library(tinyusb_host)
+ target_link_libraries(tinyusb_host INTERFACE tinyusb_host_base tinyusb_common)
- # Sometimes have to do host specific actions in mostly
- # common functions
- target_compile_definitions(tinyusb_host INTERFACE
- RP2040_USB_HOST_MODE=1
- TINYUSB_HOST_LINKED=1
- )
+ pico_add_impl_library(tinyusb_board)
+ target_link_libraries(tinyusb_board INTERFACE tinyusb_bsp)
- target_link_libraries(tinyusb_host INTERFACE tinyusb_common)
-
- add_library(tinyusb_board INTERFACE)
- target_sources(tinyusb_board INTERFACE
- ${PICO_TINYUSB_PATH}/hw/bsp/raspberry_pi_pico/board_raspberry_pi_pico.c
- )
-
+ pico_promote_common_scope_vars()
endif()
-
diff --git a/test/CMakeLists.txt b/test/CMakeLists.txt
index 22852e7..7ed2a00 100644
--- a/test/CMakeLists.txt
+++ b/test/CMakeLists.txt
@@ -7,4 +7,5 @@
add_subdirectory(pico_float_test)
add_subdirectory(kitchen_sink)
add_subdirectory(hardware_pwm_test)
+ add_subdirectory(cmsis_test)
endif()
\ No newline at end of file
diff --git a/test/cmsis_test/CMakeLists.txt b/test/cmsis_test/CMakeLists.txt
new file mode 100644
index 0000000..da8ecbf
--- /dev/null
+++ b/test/cmsis_test/CMakeLists.txt
@@ -0,0 +1,4 @@
+add_executable(cmsis_test cmsis_test.c)
+
+target_link_libraries(cmsis_test PRIVATE pico_stdlib cmsis_core)
+pico_add_extra_outputs(cmsis_test)
\ No newline at end of file
diff --git a/test/cmsis_test/cmsis_test.c b/test/cmsis_test/cmsis_test.c
new file mode 100644
index 0000000..a436391
--- /dev/null
+++ b/test/cmsis_test/cmsis_test.c
@@ -0,0 +1,23 @@
+#include <stdio.h>
+
+#include "RP2040.h"
+#include "pico/stdio.h"
+
+__STATIC_FORCEINLINE int some_function(int i) {
+ return __CLZ(i);
+}
+
+static bool pendsv_called;
+
+void PendSV_Handler(void) {
+ pendsv_called = true;
+}
+
+int main(void) {
+ stdio_init_all();
+ for(int i=0;i<10;i++) {
+ printf("%d %d\n", i, some_function(i));
+ }
+ SCB->ICSR = SCB_ICSR_PENDSVSET_Msk;
+ puts(pendsv_called ? "SUCCESS" : "FAILURE");
+}
diff --git a/test/kitchen_sink/CMakeLists.txt b/test/kitchen_sink/CMakeLists.txt
index a0bfe1a..68d7a61 100644
--- a/test/kitchen_sink/CMakeLists.txt
+++ b/test/kitchen_sink/CMakeLists.txt
@@ -6,6 +6,7 @@
hardware_adc
hardware_clocks
hardware_divider
+ hardware_exception
hardware_dma
hardware_flash
hardware_gpio
diff --git a/test/kitchen_sink/kitchen_sink.c b/test/kitchen_sink/kitchen_sink.c
index 3fc7b53..e607b80 100644
--- a/test/kitchen_sink/kitchen_sink.c
+++ b/test/kitchen_sink/kitchen_sink.c
@@ -11,6 +11,7 @@
#include "hardware/clocks.h"
#include "hardware/divider.h"
#include "hardware/dma.h"
+#include "hardware/exception.h"
#include "hardware/flash.h"
#include "hardware/gpio.h"
#include "hardware/i2c.h"
diff --git a/test/pico_divider_test/CMakeLists.txt b/test/pico_divider_test/CMakeLists.txt
index 4e922a4..d2ab012 100644
--- a/test/pico_divider_test/CMakeLists.txt
+++ b/test/pico_divider_test/CMakeLists.txt
@@ -12,6 +12,27 @@
pico_add_extra_outputs(pico_divider_test)
target_compile_definitions(pico_divider_test PRIVATE
+# PICO_DIVIDER_DISABLE_INTERRUPTS=1
# TURBO
)
+
+ # this is a separate test as hardware_explicit above causes it not to be tested at all!
+ add_library(pico_divider_nesting_test_core INTERFACE)
+ target_sources(pico_divider_nesting_test_core INTERFACE
+ pico_divider_nesting_test.c
+ )
+ target_link_libraries(pico_divider_nesting_test_core INTERFACE pico_stdlib hardware_dma)
+
+ add_executable(pico_divider_nesting_test_with_dirty_check)
+ target_link_libraries(pico_divider_nesting_test_with_dirty_check pico_divider_nesting_test_core)
+ pico_set_divider_implementation(pico_divider_nesting_test_with_dirty_check hardware)
+ pico_add_extra_outputs(pico_divider_nesting_test_with_dirty_check)
+
+ add_executable(pico_divider_nesting_test_with_disable_irq)
+ target_link_libraries(pico_divider_nesting_test_with_disable_irq pico_divider_nesting_test_core)
+ target_compile_definitions(pico_divider_nesting_test_with_disable_irq PRIVATE
+ PICO_DIVIDER_DISABLE_INTERRUPTS=1)
+ pico_set_divider_implementation(pico_divider_nesting_test_with_disable_irq hardware)
+ pico_add_extra_outputs(pico_divider_nesting_test_with_disable_irq)
+
endif()
\ No newline at end of file
diff --git a/test/pico_divider_test/pico_divider_nesting_test.c b/test/pico_divider_test/pico_divider_nesting_test.c
new file mode 100644
index 0000000..0e0db94
--- /dev/null
+++ b/test/pico_divider_test/pico_divider_nesting_test.c
@@ -0,0 +1,199 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <math.h>
+#include "pico/stdlib.h"
+#include "hardware/dma.h"
+#include "hardware/irq.h"
+
+volatile bool failed;
+volatile uint32_t count[3];
+volatile bool done;
+
+#define FAILED() ({ failed = true; })
+//#define FAILED() ({ failed = true; __breakpoint(); })
+
+bool timer_callback(repeating_timer_t *t) {
+ count[0]++;
+ static int z;
+ for (int i=0; i<100;i++) {
+ z += 23;
+ int a = z / 7;
+ int b = z % 7;
+ if (z != a * 7 + b) {
+ FAILED();
+ }
+ a = z / -7;
+ b = z % -7;
+ if (z != a * -7 + b) {
+ FAILED();
+ }
+ }
+ float fz = z;
+ float fa = fz / 11.0f;
+ float fb = fmodf(fz, 11.0f);
+ if (fabsf(fz - (fa * 11.0 + fb) > 1e-9)) {
+ FAILED();
+ }
+ double dz = z;
+ double da = dz / 11.0;
+ double db = fmod(dz, 11.0);
+ if (fabsf(dz - (da * 11.0 + db) > 1e-9)) {
+ FAILED();
+ }
+
+ return !done;
+}
+
+void do_dma_start(uint ch) {
+ static uint32_t word[2];
+ assert(ch < 2);
+ dma_channel_config c = dma_channel_get_default_config(ch);
+ // todo remove this; landing in a separate PR
+#ifndef DREQ_DMA_TIMER0
+#define DREQ_DMA_TIMER0 0x3b
+#endif
+ channel_config_set_dreq(&c, DREQ_DMA_TIMER0);
+ dma_channel_configure(ch, &c, &word[ch], &word[ch], 513 + ch * 23, true);
+}
+
+double d0c, d0s, d0t, dz;
+float f0c, f0s, f0t, fz;
+
+void test_irq_handler0() {
+ count[1]++;
+ dma_hw->ints0 |= 1u;
+ static uint z;
+ static uint dz;
+ for (int i=0; i<80;i++) {
+ z += 31;
+ uint a = z / 11;
+ uint b = z % 11;
+ if (z != a * 11 + b) {
+ FAILED();
+ }
+ }
+ if (done) dma_channel_abort(0);
+ else do_dma_start(0);
+}
+
+void test_irq_handler1() {
+ static uint z;
+ dma_hw->ints1 |= 2u;
+ count[2]++;
+ for (int i=0; i<130;i++) {
+ z += 47;
+ uint a = z / -13;
+ uint b = z % -13;
+ if (z != a * -13 + b) {
+ FAILED();
+ }
+ static uint64_t z64;
+ z64 -= 47;
+ uint64_t a64 = z64 / -13;
+ uint64_t b64 = z64 % -13;
+ if (z64 != a64 * -13 + b64) {
+ FAILED();
+ }
+ }
+
+ if (done) dma_channel_abort(1);
+ else do_dma_start(1);
+}
+
+void test_nesting() {
+ uint z = 0;
+
+ // We have 3 different IRQ handlers, one for timer, two for DMA completion (on DMA_IRQ0/1)
+ // thus we expect re-entrancy even between IRQs
+ //
+ // They all busily make use of the dividers, to expose any issues with nested use
+
+ repeating_timer_t timer;
+ add_repeating_timer_us(929, timer_callback, NULL, &timer);
+ irq_set_exclusive_handler(DMA_IRQ_0, test_irq_handler0);
+ irq_set_exclusive_handler(DMA_IRQ_1, test_irq_handler1);
+
+ dma_set_irq0_channel_mask_enabled(1u, true);
+ dma_set_irq1_channel_mask_enabled(2u, true);
+ dma_hw->timer[0] = (1 << 16) | 32; // run at 1/32 system clock
+
+ irq_set_enabled(DMA_IRQ_0, 1);
+ irq_set_enabled(DMA_IRQ_1, 1);
+ do_dma_start(0);
+ do_dma_start(1);
+ absolute_time_t end = delayed_by_ms(get_absolute_time(), 10000);
+ int count_local=0;
+ while (!time_reached(end)) {
+ for(uint i=0;i<100;i++) {
+ z += 31;
+ uint a = z / 11;
+ uint b = z % 11;
+ if (z != a * 11 + b) {
+ FAILED();
+ }
+ int zz = (int)z;
+ int aa = zz / -11;
+ int bb = zz % -11;
+ if (zz != aa * -11 + bb) {
+ FAILED();
+ }
+ aa = -zz / -11;
+ bb = -zz % -11;
+ if (-zz != aa * -11 + bb) {
+ FAILED();
+ }
+ aa = -zz / 11;
+ bb = -zz % 11;
+ if (-zz != aa * 11 + bb) {
+ FAILED();
+ }
+ a = 0xffffffffu / 11;
+ b = 0xffffffffu % 11;
+ if (0xffffffffu != a * 11 + b) {
+ FAILED();
+ }
+ }
+ // these use the divider
+ for(uint i=0;i<=100;i+=20) {
+ // both in and out bootrom range (we perform mod in wrapper code if necessarry)
+ f0t = tanf(i * 50);
+ f0c = cosf(i * 50);
+ f0s = sinf(i * 50);
+ d0t = tan(i * 1000);
+ d0c = cos(i * 1000);
+ d0s = sin(i * 1000);
+ }
+ count_local++;
+ }
+ done = true;
+ cancel_repeating_timer(&timer);
+ printf("%d: %d %d %d\n", count_local, (int)count[0], (int)count[1], (int)count[2]);
+
+ // make sure all the IRQs ran
+ if (!(count_local && count[0] && count[1] && count[2])) {
+ printf("DID NOT RUN\n");
+ exit(1);
+ }
+ if (failed) {
+ printf("FAILED\n");
+ exit(1);
+ }
+}
+
+int main() {
+#ifndef uart_default
+#warning test/pico_divider requires a default uart
+#else
+ stdio_init_all();
+#endif
+ test_nesting();
+ printf("PASSED\n");
+ return 0;
+}
+
diff --git a/test/pico_float_test/CMakeLists.txt b/test/pico_float_test/CMakeLists.txt
index 0ff1f60..26204d3 100644
--- a/test/pico_float_test/CMakeLists.txt
+++ b/test/pico_float_test/CMakeLists.txt
@@ -11,15 +11,19 @@
)
+#todo split out variants with different flags
target_compile_definitions(pico_float_test PRIVATE
PICO_USE_CRT_PRINTF=1 # want full precision output
# PICO_FLOAT_PROPAGATE_NANS=1
+# PICO_DIVIDER_DISABLE_INTERRUPTS=1
)
+#todo split out variants with different flags
target_compile_definitions(pico_double_test PRIVATE
PICO_USE_CRT_PRINTF=1 # want full precision output
PICO_FLOAT_PROPAGATE_NANS=1
- PICO_DOUBLE_PROPAGATE_NANS=1
+ #PICO_DOUBLE_PROPAGATE_NANS=1
+ #PICO_DIVIDER_DISABLE_INTERRUPTS=1
)
# handy for testing we aren't pulling in extra stuff
diff --git a/test/pico_float_test/pico_double_test.c b/test/pico_float_test/pico_double_test.c
index 708ab25..6c095e7 100644
--- a/test/pico_float_test/pico_double_test.c
+++ b/test/pico_float_test/pico_double_test.c
@@ -282,6 +282,51 @@
return 0;
}
+#define assert_nan(a) assert(isnan(a))
+#define check_nan(a) ({ assert_nan(a); a; })
+
+double __aeabi_i2d(int32_t);
+double __aeabi_ui2d(int32_t);
+double __aeabi_l2d(int64_t);
+double __aeabi_ul2d(int64_t);
+int32_t __aeabi_d2iz(double);
+int64_t __aeabi_d2lz(double);
+double __aeabi_dmul(double, double);
+double __aeabi_ddiv(double, double);
+#if LIB_PICO_DOUBLE_PICO
+double __real___aeabi_i2d(int);
+double __real___aeabi_ui2d(int);
+double __real___aeabi_l2d(int64_t);
+double __real___aeabi_ul2d(int64_t);
+double __real___aeabi_dmul(double, double);
+double __real___aeabi_ddiv(double, double);
+int32_t __real___aeabi_d2iz(double);
+int64_t __real___aeabi_d2lz(double);
+double __real_sqrt(double);
+double __real_cos(double);
+double __real_sin(double);
+double __real_tan(double);
+double __real_exp(double);
+double __real_log(double);
+double __real_atan2(double, double);
+double __real_pow(double, double);
+double __real_trunc(double);
+double __real_ldexp(double, int);
+double __real_fmod(double, double);
+
+#define EPSILON 1e-9
+#define assert_close(a, b) assert(((b - a) < EPSILON || (a - b) < EPSILON) || (isinf(a) && isinf(b) && (a < 0) == (b < 0)))
+#define check1(func,p0) ({ typeof(p0) r = func(p0), r2 = __CONCAT(__real_, func)(p0); assert(r == r2); r; })
+#define check2(func,p0,p1) ({ typeof(p0) r = func(p0,p1), r2 = __CONCAT(__real_, func)(p0,p1); assert(r == r2); r; })
+#define check_close1(func,p0) ({ typeof(p0) r = func(p0), r2 = __CONCAT(__real_, func)(p0); if (isnan(p0)) assert_nan(r); else assert_close(r, r2); r; })
+#define check_close2(func,p0,p1) ({ typeof(p0) r = func(p0,p1), r2 = __CONCAT(__real_, func)(p0,p1); if (isnan(p0) || isnan(p1)) assert_nan(r); else assert_close(r, r2); r; })
+#else
+#define check1(func,p0) func(p0)
+#define check2(func,p0,p1) func(p0,p1)
+#define check_close1(func,p0) func(p0)
+#define check_close2(func,p0,p1) func(p0,p1)
+#endif
+
double aa = 0.5;
double bb = 1;
@@ -305,14 +350,18 @@
#if 1
for (double x = 0; x < 3; x++) {
printf("\n ----- %g\n", x);
- printf("SQRT %10.18g\n", sqrt(x));
- printf("COS %10.18g\n", cos(x));
- printf("SIN %10.18g\n", sin(x));
- printf("TAN %10.18g\n", tan(x));
- printf("ATAN2 %10.18g\n", atan2(x, 10));
- printf("ATAN2 %10.18g\n", atan2(10, x));
- printf("EXP %10.18g\n", exp(x));
- printf("LN %10.18g\n", log(x));
+ printf("SQRT %10.18g\n", check_close1(sqrt, x));
+ printf("COS %10.18g\n", check_close1(cos, x));
+ printf("SIN %10.18g\n", check_close1(sin, x));
+ printf("TAN %10.18g\n", check_close1(tan, x));
+ printf("ATAN2 %10.18g\n", check_close2(atan2, x, 10.0));
+ printf("ATAN2 %10.18g\n", check_close2(atan2, 10.0, x));
+ printf("EXP %10.18g\n", check_close1(exp, x));
+ printf("LN %10.18g\n", check_close1(log, x));
+ printf("POW %10.18f\n", check_close2(pow, x, x));
+ printf("TRUNC %10.18f\n", check_close1(trunc, x));
+ printf("LDEXP %10.18f\n", check_close2(ldexp, x, x));
+ printf("FMOD %10.18f\n", check_close2(fmod, x, 3.0f));
double s, c;
sincos(x, &s, &c);
printf("SINCOS %10.18f %10.18f\n", s, c);
@@ -325,22 +374,21 @@
#if PICO_DOUBLE_PROPAGATE_NANS
{
float x = NAN;
- printf("NANO %10.18f\n", x);
- printf("SQRT %10.18f\n", sqrt(x));
- printf("COS %10.18f\n", cos(x));
- printf("SIN %10.18f\n", sin(x));
- printf("TAN %10.18f\n", tan(x));
- printf("ATAN2 %10.18f\n", atan2(x, 10));
- printf("ATAN2 %10.18f\n", atan2(10, x));
- printf("EXP %10.18f\n", exp(x));
- printf("LN %10.18f\n", log(x));
- printf("POW %10.18f\n", pow(x, x));
- printf("TRUNC %10.18f\n", trunc(x));
- printf("LDEXP %10.18f\n", ldexp(x, x));
- printf("FMOD %10.18f\n", fmod(x, 3.0f));
+ printf("SQRT %10.18g\n", check_close1(sqrt, x));
+ printf("COS %10.18g\n", check_close1(cos, x));
+ printf("SIN %10.18g\n", check_close1(sin, x));
+ printf("TAN %10.18g\n", check_close1(tan, x));
+ printf("ATAN2 %10.18g\n", check_close2(atan2, x, 10.0));
+ printf("ATAN2 %10.18g\n", check_close2(atan2, 10.0, x));
+ printf("EXP %10.18g\n", check_close1(exp, x));
+ printf("LN %10.18g\n", check_close1(log, x));
+ printf("POW %10.18f\n", check_nan(pow(x, x)));
+ printf("TRUNC %10.18f\n", check_nan(trunc(x)));
+ printf("LDEXP %10.18f\n", check_nan(ldexp(x, x)));
+ printf("FMOD %10.18f\n", check_nan(fmod(x, 3.0f)));
double s, c;
sincos(x, &s, &c);
- printf("SINCOS %10.18f %10.18f\n", s, c);
+ printf("SINCOS %10.18f %10.18f\n", check_nan(s), check_nan(c));
for(int j=0;j<2;j++) {
for (int i = 1; i < 4; i++) {
@@ -372,17 +420,21 @@
// }
for (int32_t x = -1; x; x <<= 1) {
printf("i %d->%f\n", x, (double) x);
+ check1(__aeabi_i2d, x);
}
for (int32_t x = 1; x; x <<= 1) {
printf("i %d->%f\n", x, (double) x);
+ check1(__aeabi_i2d, x);
y = x << 1;
}
for (int64_t x = 1; x; x <<= 1) {
printf("i %lld->%f\n", x, (double) x);
+ check1(__aeabi_l2d, x);
y = x << 1;
}
for (int64_t x = -1; x; x <<= 1) {
printf("i %lld->%f\n", x, (double) x);
+ check1(__aeabi_l2d, x);
y = x << 1;
}
printf("d %d->%f\n", y, (float) y);
@@ -392,24 +444,40 @@
uint32_t y;
for(uint32_t x = 1; x; x <<= 1) {
printf("u %u->%f\n", x, (double)x);
+ check1(__aeabi_ui2d, x);
y = x << 1;
}
printf("u %u->%f\n", y, (double)y);
}
for(int64_t x = 1; x !=0; x <<= 1u) {
printf("%lld->%f\n", x, (double)x);
+ check1(__aeabi_l2d, x);
}
- for(double x = -4294967296.f * 4294967296.f; x<=-0.5f; x/=2.f) {
+ for(double x = -4294967296.f * 4294967296.f * 2.f; x<=-0.5f; x/=2.f) {
printf("d2i64 %f->%lld\n", x, (int64_t)x);
+ if (x < INT64_MIN) {
+ // seems like there is a bug in the gcc version!
+ assert(__aeabi_d2lz(x) == INT64_MIN);
+ } else {
+ check1(__aeabi_d2lz, x);
+ }
}
- for(double x = 4294967296.f * 4294967296.f; x>=0.5f; x/=2.f) {
+ for(double x = 4294967296.f * 4294967296.f * 2.f; x>=0.5f; x/=2.f) {
printf("d2i64 %f->%lld\n", x, (int64_t)x);
+ if (x >= INT64_MAX) {
+ // seems like there is a bug in the gcc version!
+ assert(__aeabi_d2lz(x) == INT64_MAX);
+ } else {
+ check1(__aeabi_d2lz, x);
+ }
}
for(double x = -4294967296.f * 4294967296.f; x<=-0.5f; x/=2.f) {
printf("d2i32 %f->%d\n", x, (int32_t)x);
+ check1(__aeabi_d2iz, x);
}
for(double x = 4294967296.f * 4294967296.f; x>=0.5f; x/=2.f) {
printf("d2i32 %f->%d\n", x, (int32_t)x);
+ check1(__aeabi_d2iz, x);
}
for (double x = 1; x < 11; x += 2) {
@@ -417,6 +485,8 @@
double g = 1.0 / x;
printf("%g %10.18g %10.18g, %10.18g, %10.18g %10.18g\n", x, f, x + 0.37777777777777777777777777777,
x - 0.377777777777777777777777777777, g, 123456789.0 / x);
+ check2(__aeabi_dmul, x, x);
+ check2(__aeabi_ddiv, 1.0, x);
}
if (fail ||
diff --git a/test/pico_float_test/pico_float_test.c b/test/pico_float_test/pico_float_test.c
index 75a37a8..5da23d2 100644
--- a/test/pico_float_test/pico_float_test.c
+++ b/test/pico_float_test/pico_float_test.c
@@ -16,7 +16,6 @@
#include <stdlib.h>
#include <math.h>
#include <pico/float.h>
-//#include <pico/float.h>
#include "pico/stdlib.h"
#include "inttypes.h"
@@ -283,12 +282,58 @@
return 0;
}
+#define assert_nan(a) assert(isnan(a))
+#define check_nan(a) ({ assert_nan(a); a; })
+
+float __aeabi_i2f(int32_t);
+float __aeabi_ui2f(int32_t);
+float __aeabi_l2f(int64_t);
+float __aeabi_ul2f(int64_t);
+int32_t __aeabi_f2iz(float);
+int64_t __aeabi_f2lz(float);
+float __aeabi_fmul(float, float);
+float __aeabi_fdiv(float, float);
+#if LIB_PICO_FLOAT_PICO
+float __real___aeabi_i2f(int);
+float __real___aeabi_ui2f(int);
+float __real___aeabi_l2f(int64_t);
+float __real___aeabi_ul2f(int64_t);
+float __real___aeabi_fmul(float, float);
+float __real___aeabi_fdiv(float, float);
+int32_t __real___aeabi_f2iz(float);
+int64_t __real___aeabi_f2lz(float);
+float __real_sqrtf(float);
+float __real_cosf(float);
+float __real_sinf(float);
+float __real_tanf(float);
+float __real_expf(float);
+float __real_logf(float);
+float __real_atan2f(float, float);
+float __real_powf(float, float);
+float __real_truncf(float);
+float __real_ldexpf(float, int);
+float __real_fmodf(float, float);
+#define EPSILON 1e-9
+#define assert_close(a, b) assert(((b - a) < EPSILON || (a - b) < EPSILON) || (isinf(a) && isinf(b) && (a < 0) == (b < 0)))
+#define check1(func,p0) ({ typeof(p0) r = func(p0), r2 = __CONCAT(__real_, func)(p0); assert(r == r2); r; })
+#define check2(func,p0,p1) ({ typeof(p0) r = func(p0,p1), r2 = __CONCAT(__real_, func)(p0,p1); assert(r == r2); r; })
+#define check_close1(func,p0) ({ typeof(p0) r = func(p0), r2 = __CONCAT(__real_, func)(p0); if (isnan(p0)) assert_nan(r); else assert_close(r, r2); r; })
+#define check_close2(func,p0,p1) ({ typeof(p0) r = func(p0,p1), r2 = __CONCAT(__real_, func)(p0,p1); if (isnan(p0) || isnan(p1)) assert_nan(r); else assert_close(r, r2); r; })
+#else
+#define check1(func,p0) func(p0)
+#define check2(func,p0,p1) func(p0,p1)
+#define check_close1(func,p0) func(p0)
+#define check_close2(func,p0,p1) func(p0,p1)
+#endif
+
double aa = 0.5;
double bb = 1;
int main() {
setup_default_uart();
+ bool fail = false;
+
printf("%d\n", aa < bb);
for(float a = -1; a <= 1; a++) {
for(float b = -1; b <= 1; b++) {
@@ -341,21 +386,27 @@
#if 1
for (float x = 0; x < 3; x++) {
printf("\n ----- %f\n", x);
- printf("FSQRT %10.18f\n", sqrtf(x));
- printf("FCOS %10.18f\n", cosf(x));
- printf("FSIN %10.18f\n", sinf(x));
+ printf("FSQRT %10.18f\n", check_close1(sqrtf, x));
+ printf("FCOS %10.18f\n", check_close1(cosf, x));
+ printf("FSIN %10.18f\n", check_close1(sinf, x));
float s, c;
sincosf(x, &s, &c);
printf("FSINCOS %10.18f %10.18f\n", s, c);
- printf("FTAN %10.18f\n", tanf(x));
- printf("FATAN2 %10.18f\n", atan2f(x, 10));
- printf("FATAN2 %10.18f\n", atan2f(10, x));
- printf("FEXP %10.18f\n", expf(x));
- printf("FLN %10.18f\n", logf(x));
- printf("POWF %10.18f\n", powf(x, x));
- printf("TRUNCF %10.18f\n", truncf(x));
- printf("LDEXPF %10.18f\n", ldexpf(x, x));
- printf("FMODF %10.18f\n", fmodf(x, 3.0f));
+ printf("FTAN %10.18f\n", check_close1(tanf, x));
+ printf("FATAN2 %10.18f\n", check_close2(atan2f, x, 10.f));
+ printf("FATAN2 %10.18f\n", check_close2(atan2f, 10.f, x));
+ printf("FEXP %10.18f\n", check_close1(expf, x));
+ printf("FLN %10.18f\n", check_close1(logf, x));
+ printf("POWF %10.18f\n", check_close2(powf, x, x));
+ printf("TRUNCF %10.18f\n", check_close1(truncf, x));
+ printf("LDEXPF %10.18f\n", check_close2(ldexpf, x, x));
+ printf("FMODF %10.18f\n", check_close2(fmodf, x, 3.0f));
+ sincosf(x, &s, &c);
+ printf("SINCOS %10.18f %10.18f\n", s, c);
+ if (s != sin(x) || c != cos(x)) {
+ printf("SINCOS mismatch\n");
+ fail = true;
+ }
}
for (double x = 0; x < 3; x++) {
@@ -390,18 +441,25 @@
// sincosf(x, &s, &c);
printf("FSINCOS %10.18f %10.18f\n", s, c);
- for(int i=1; i<4; i++) {
- char buf[4];
- sprintf(buf, "%d", i);
- float f0 = -nanf(buf);
- double d0 = -nan(buf);
- // hmm
- *(uint64_t *)&d0 |= i;
- *(uint32_t *)&f0 |= i;
- float f = (float)d0;
- double d = (double)f0;
- printf("f2d %08"PRIx32" -> %g %016"PRIx64"\n", *(uint32_t*)&f0, d, *(uint64_t*)&d);
- printf("d2f %016"PRIx64" -> %f %08"PRIx32"\n", *(uint64_t*)&d0, f, *(uint32_t*)&f);
+ for(int j=0;j<2;j++) {
+ for (int i = 1; i < 4; i++) {
+ char buf[4];
+ sprintf(buf, "%d", i);
+ float f0 = -nanf(buf);
+ double d0 = -nan(buf);
+ // hmm nanf/nan seem to ignore payload
+ *(uint64_t *) &d0 |= i;
+ *(uint32_t *) &f0 |= i;
+ if (j) {
+ // try without top bit set
+ *(uint64_t *) &d0 &= ~0x0008000000000000ull;
+ *(uint32_t *) &f0 &= ~0x00400000u;
+ }
+ float f = (float) d0;
+ double d = (double) f0;
+ printf("f2d %f %08"PRIx32" -> %g %016"PRIx64"\n", f0, *(uint32_t *) &f0, d, *(uint64_t *) &d);
+ printf("d2f %f %016"PRIx64" -> %f %08"PRIx32"\n", d0, *(uint64_t *) &d0, f, *(uint32_t *) &f);
+ }
}
}
#endif
@@ -413,17 +471,21 @@
// }
for (int32_t x = -1; x; x <<= 1) {
printf("i %d->%f\n", x, (float) x);
+ check1(__aeabi_i2f, x);
}
for (int32_t x = 1; x; x <<= 1) {
printf("i %d->%f\n", x, (float) x);
+ check1(__aeabi_i2f, x);
y = x << 1;
}
for (int64_t x = 1; x; x <<= 1) {
printf("i %lld->%f\n", x, (float) x);
+ check1(__aeabi_l2f, x);
y = x << 1;
}
for (int64_t x = -1; x; x <<= 1) {
printf("i %lld->%f\n", x, (float) x);
+ check1(__aeabi_l2f, x);
y = x << 1;
}
printf("d %d->%f\n", y, (float) y);
@@ -433,40 +495,63 @@
uint32_t y;
for(uint32_t x = 1; x; x <<= 1) {
printf("u %u->%f\n", x, (float)x);
+ check1(__aeabi_ui2f, x);
y = x << 1;
}
printf("u %u->%f\n", y, (float)y);
}
for(int64_t x = 1; x !=0; x <<= 1u) {
printf("%lld->%f\n", x, (float)x);
+ check1(__aeabi_l2f, x);
+ }
+ for(float x = -4294967296.f * 4294967296.f; x>=0.5f; x/=2.f) {
+ printf("f %f->%lld\n", x, (int64_t)x);
+ if (x < INT64_MIN) {
+ // seems like there is a bug in the gcc version!
+ assert(__aeabi_f2lz(x) == INT64_MIN);
+ } else {
+ check1(__aeabi_f2lz, x);
+ }
+ }
+ for(float x = 4294967296.f * 4294967296.f * 2.f; x>=0.5f; x/=2.f) {
+ printf("f2i64 %f->%lld\n", x, (int64_t)x);
+ if (x >= INT64_MAX) {
+ // seems like there is a bug in the gcc version!
+ assert(__aeabi_f2lz(x) == INT64_MAX);
+ } else {
+ check1(__aeabi_f2lz, x);
+ }
+ }
+ for(float x = -4294967296.f * 4294967296.f; x<=-0.5f; x/=2.f) {
+ printf("d2i32 %f->%d\n", x, (int32_t)x);
+ check1(__aeabi_f2iz, x);
}
for(float x = 4294967296.f * 4294967296.f; x>=0.5f; x/=2.f) {
- printf("f %f->%lld\n", x, (int64_t)x);
+ printf("d2i32 %f->%d\n", x, (int32_t)x);
+ check1(__aeabi_f2iz, x);
}
- for (double x = 1; x < 11; x += 2) {
- double f = x * x;
- double g = 1.0 / x;
- printf("%g %10.18g %10.18g, %10.18g, %10.18g %10.18g\n", x, f, x + 0.37777777777777777777777777777,
- x - 0.377777777777777777777777777777, g, 123456789.0 / x);
+
+ for (float x = 1; x < 11; x += 2) {
+ float f = x * x;
+ float g = 1.0f / x;
+ printf("%g %10.18g %10.18g, %10.18g, %10.18g %10.18g\n", x, f, x + 0.37777777777777777777777777777f,
+ x - 0.377777777777777777777777777777f, g, 123456789.0f / x);
+ check2(__aeabi_fmul, x, x);
+ check2(__aeabi_fdiv, 1.0f, x);
}
- if (test_cfcmpeq() || test_cfcmple() ||
- test_fcmpun() || test_cmple_gt() || test_cmplt_ge()) {
+
+ if (fail ||
+ test_cfcmpeq() ||
+ test_cfcmple() ||
+ test_fcmpun() ||
+ test_cmple_gt() ||
+ test_cmplt_ge()) {
printf("FAILED\n");
return 1;
} else {
printf("PASSED\n");
return 0;
}
-
- if (test_cfcmpeq() || test_cfcmple() ||
- test_fcmpun() || test_cmple_gt() || test_cmplt_ge()) {
- printf("FAILED\n");
- return 1;
- } else {
- printf("PASSED\n");
- return 0;
- }
-
#endif
}
diff --git a/tools/CMakeLists.txt b/tools/CMakeLists.txt
index 9ac6f6f..2e908b2 100644
--- a/tools/CMakeLists.txt
+++ b/tools/CMakeLists.txt
@@ -44,17 +44,3 @@
COMMAND ELF2UF2 ${TARGET}${CMAKE_EXECUTABLE_SUFFIX} ${TARGET}.uf2)
endif()
endfunction()
-
-if (NOT DEFINED PICO_BUILD_PICOFLASH)
- if (DEFINED ENV{PICO_BUILD_PICOFLASH})
- set(PICO_BUILD_PICOFLASH $ENV{PICO_BUILD_PICOFLASH})
- else()
- # for now
- set(PICO_BUILD_PICOFLASH 1)
- endif()
-endif()
-
-if (PICO_BUILD_PICOTOOL)
- set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${PICO_SDK_PATH}/tools)
- find_package(Picotool REQUIRED)
-endif()
diff --git a/tools/FindELF2UF2.cmake b/tools/FindELF2UF2.cmake
index fdf3626..fb5dd97 100644
--- a/tools/FindELF2UF2.cmake
+++ b/tools/FindELF2UF2.cmake
@@ -22,7 +22,7 @@
set(ELF2UF2_TARGET ELF2UF2)
if (NOT TARGET ${ELF2UF2_BUILD_TARGET})
- message("ELF2UF2 will need to be built")
+ pico_message_debug("ELF2UF2 will need to be built")
ExternalProject_Add(${ELF2UF2_BUILD_TARGET}
PREFIX elf2uf2 SOURCE_DIR ${ELF2UF2_SOURCE_DIR}
BINARY_DIR ${ELF2UF2_BINARY_DIR}
@@ -40,4 +40,4 @@
add_dependencies(${ELF2UF2_TARGET} ${ELF2UF2_BUILD_TARGET})
set(ELF2UF2_FOUND 1)
-endif()
\ No newline at end of file
+endif()
diff --git a/tools/FindPicotool.cmake b/tools/FindPicotool.cmake
deleted file mode 100644
index 3e28f03..0000000
--- a/tools/FindPicotool.cmake
+++ /dev/null
@@ -1,43 +0,0 @@
-# Finds (or builds) the PICOTOOL executable
-#
-# This will define the following variables
-#
-# PICOTOOL_FOUND
-#
-# and the following imported targets
-#
-# PICOTOOL
-#
-
-if (NOT PICOTOOL_FOUND)
- # todo we would like to use pckgconfig to look for it first
- # see https://pabloariasal.github.io/2018/02/19/its-time-to-do-cmake-right/
-
- include(ExternalProject)
-
- set(PICOTOOL_SOURCE_DIR ${PICO_SDK_PATH}/tools/picotool)
- set(PICOTOOL_BINARY_DIR ${CMAKE_BINARY_DIR}/picotool)
-
- set(PICOTOOL_BUILD_TARGET PicotoolBuild)
- set(PICOTOOL_TARGET Picotool)
-
- if (NOT TARGET ${PICOTOOL_BUILD_TARGET})
- message("PICOTOOL will need to be built")
- ExternalProject_Add(${PICOTOOL_BUILD_TARGET}
- PREFIX picotool SOURCE_DIR ${PICOTOOL_SOURCE_DIR}
- BINARY_DIR ${PICOTOOL_BINARY_DIR}
- BUILD_ALWAYS 1 # force dependency checking
- INSTALL_COMMAND ""
- )
- endif()
-
- set(PICOTOOL_EXECUTABLE ${PICOTOOL_BINARY_DIR}/picotool)
- if(NOT TARGET ${PICOTOOL_TARGET})
- add_executable(${PICOTOOL_TARGET} IMPORTED)
- endif()
- set_property(TARGET ${PICOTOOL_TARGET} PROPERTY IMPORTED_LOCATION
- ${PICOTOOL_EXECUTABLE})
-
- add_dependencies(${PICOTOOL_TARGET} ${PICOTOOL_BUILD_TARGET})
- set(PICOTOOL_FOUND 1)
-endif()
\ No newline at end of file
diff --git a/tools/FindPioasm.cmake b/tools/FindPioasm.cmake
index c548263..91b9021 100644
--- a/tools/FindPioasm.cmake
+++ b/tools/FindPioasm.cmake
@@ -22,7 +22,7 @@
set(Pioasm_TARGET Pioasm)
if (NOT TARGET ${PioasmBuild_TARGET})
- message("PIOASM will need to be built")
+ pico_message_debug("PIOASM will need to be built")
# message("Adding external project ${PioasmBuild_Target} in ${CMAKE_CURRENT_LIST_DIR}}")
ExternalProject_Add(${PioasmBuild_TARGET}
PREFIX pioasm SOURCE_DIR ${PIOASM_SOURCE_DIR}
diff --git a/tools/pioasm/c_sdk_output.cpp b/tools/pioasm/c_sdk_output.cpp
index 9e2dc22..9388c0d 100644
--- a/tools/pioasm/c_sdk_output.cpp
+++ b/tools/pioasm/c_sdk_output.cpp
@@ -68,6 +68,8 @@
header(out, "This file is autogenerated by pioasm; do not edit!");
+ fprintf(out, "#pragma once\n");
+ fprintf(out, "\n");
fprintf(out, "#if !PICO_NO_HARDWARE\n");
fprintf(out, "#include \"hardware/pio.h\"\n");
fprintf(out, "#endif\n");
