Fix some enc_bootloader compile warnings

enc_bootloader/enc_bootloader.c

diff --git a/enc_bootloader/enc_bootloader.c b/enc_bootloader/enc_bootloader.c
index bd72828..4b7e40f 100644
--- a/enc_bootloader/enc_bootloader.c
+++ b/enc_bootloader/enc_bootloader.c
@@ -44,8 +44,8 @@
     rosc_hw->div = rosc_div | ROSC_DIV_VALUE_PASS; // set divider
     // Increment the freqency range one step at a time - this is safe provided the current config is not TOOHIGH
     // because ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM | ROSC_CTRL_FREQ_RANGE_VALUE_HIGH == ROSC_CTRL_FREQ_RANGE_VALUE_HIGH
-    static_assert(ROSC_CTRL_FREQ_RANGE_VALUE_LOW | ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM == ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM);
-    static_assert(ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM | ROSC_CTRL_FREQ_RANGE_VALUE_HIGH == ROSC_CTRL_FREQ_RANGE_VALUE_HIGH);
+    static_assert((ROSC_CTRL_FREQ_RANGE_VALUE_LOW | ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM) == ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM);
+    static_assert((ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM | ROSC_CTRL_FREQ_RANGE_VALUE_HIGH) == ROSC_CTRL_FREQ_RANGE_VALUE_HIGH);
     hw_set_bits(&rosc_hw->ctrl, ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM);
     hw_set_bits(&rosc_hw->ctrl, ROSC_CTRL_FREQ_RANGE_VALUE_HIGH);
 

enc_bootloader/mbedtls_aes.c

diff --git a/enc_bootloader/mbedtls_aes.c b/enc_bootloader/mbedtls_aes.c
index e6c7ab3..9f19c9b 100644
--- a/enc_bootloader/mbedtls_aes.c
+++ b/enc_bootloader/mbedtls_aes.c
@@ -69,6 +69,5 @@
 
     uint8_t xor_working_block[16] = {0};
     uint8_t stream_block[16] = {0};
-    size_t nc_off = 0;
     mb_aes_crypt_ctr_xor(&aes, len, (uint8_t*)iv, xor_working_block, stream_block, (uint8_t*)buf, (uint8_t*)buf);
 }