| commit | 0144ed6b63b1d67fba18f18c00c334f97e818fcc | [log] [tgz] |
|---|---|---|
| author | Aleksandar Cecaric <aleksandar.cecaric@nextsilicon.com> | Wed Mar 27 11:19:32 2024 +0100 |
| committer | Anas Nashif <anas.nashif@intel.com> | Sat Apr 13 07:03:23 2024 -0400 |
| tree | 0cd1c60d234858a86142d40f23726989f5b3c8f1 | |
| parent | 325f22a16fa6aca931e9196d7bf8d589ef975370 [diff] |
arch: riscv: update coredump for 64BIT RISCV Add RISCV 64bit registers and parse them in coredump script. Signed-off-by: Aleksandar Cecaric <aleksandar.cecaric@nextsilicon.com>