| commit | 03cafbdaefeeddec0f0bd3ab61360ae6bf87d3dd | [log] [tgz] |
|---|---|---|
| author | Andy Ross <andyross@google.com> | Mon May 13 17:38:53 2024 -0700 |
| committer | Anas Nashif <anas.nashif@intel.com> | Mon May 20 20:50:55 2024 -0400 |
| tree | b13f3ea9fb2e86d914802003882f43b9334a5eff | |
| parent | 6ab7735774d0f4db3661b54d631ebd45fad141f5 [diff] |
arch/xtensa: "NMILEVEL" is an optional feature Some oddballs cores can be generated without an "NMI" interrupt, in which case core-isa.h will not define XCHAL_NMILEVEL. This code is trying to unconditionally mask interrupts, so XCHAL_EXCM_LEVEL is the pedantically correct choice anyway (NMI's by definition, cannot be masked). Signed-off-by: Andy Ross <andyross@google.com>