dts: arm: st: stm32g4: remove U suffix from "resets" in DTSI
STM32 reset controller position argument provided to STM32_RESET()
macro sometime uses an unnecessary U suffix. Remove these useless
suffixes for this series for consistency among STM32 SoCs DTSI files.
No functional change.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
diff --git a/dts/arm/st/g4/stm32g4.dtsi b/dts/arm/st/g4/stm32g4.dtsi
index 3a448a2..6c7a23d 100644
--- a/dts/arm/st/g4/stm32g4.dtsi
+++ b/dts/arm/st/g4/stm32g4.dtsi
@@ -275,7 +275,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 14)>;
- resets = <&rctl STM32_RESET(APB2, 14U)>;
+ resets = <&rctl STM32_RESET(APB2, 14)>;
interrupts = <37 0>;
status = "disabled";
};
@@ -284,7 +284,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 17)>;
- resets = <&rctl STM32_RESET(APB1L, 17U)>;
+ resets = <&rctl STM32_RESET(APB1L, 17)>;
interrupts = <38 0>;
status = "disabled";
};
@@ -293,7 +293,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
- resets = <&rctl STM32_RESET(APB1L, 18U)>;
+ resets = <&rctl STM32_RESET(APB1L, 18)>;
interrupts = <39 0>;
status = "disabled";
};
@@ -302,7 +302,7 @@
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 19)>;
- resets = <&rctl STM32_RESET(APB1L, 19U)>;
+ resets = <&rctl STM32_RESET(APB1L, 19)>;
interrupts = <52 0>;
status = "disabled";
};
@@ -311,7 +311,7 @@
compatible = "st,stm32-lpuart", "st,stm32-uart";
reg = <0x40008000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1_2, 0)>;
- resets = <&rctl STM32_RESET(APB1H, 0U)>;
+ resets = <&rctl STM32_RESET(APB1H, 0)>;
interrupts = <91 0>;
status = "disabled";
};
@@ -423,7 +423,7 @@
reg = <0x40012c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 11)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 11U)>;
+ resets = <&rctl STM32_RESET(APB2, 11)>;
interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
st,prescaler = <0>;
@@ -447,7 +447,7 @@
reg = <0x40000000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 0)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 0U)>;
+ resets = <&rctl STM32_RESET(APB1L, 0)>;
interrupts = <28 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -476,7 +476,7 @@
reg = <0x40000400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 1)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 1U)>;
+ resets = <&rctl STM32_RESET(APB1L, 1)>;
interrupts = <29 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -505,7 +505,7 @@
reg = <0x40000800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 2)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 2U)>;
+ resets = <&rctl STM32_RESET(APB1L, 2)>;
interrupts = <30 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -534,7 +534,7 @@
reg = <0x40001000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 4)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 4U)>;
+ resets = <&rctl STM32_RESET(APB1L, 4)>;
interrupts = <54 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -546,7 +546,7 @@
reg = <0x40001400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 5)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 5U)>;
+ resets = <&rctl STM32_RESET(APB1L, 5)>;
interrupts = <55 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -558,7 +558,7 @@
reg = <0x40013400 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 13)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 13U)>;
+ resets = <&rctl STM32_RESET(APB2, 13)>;
interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
st,prescaler = <0>;
@@ -582,7 +582,7 @@
reg = <0x40014000 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 16)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 16U)>;
+ resets = <&rctl STM32_RESET(APB2, 16)>;
interrupts = <24 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -605,7 +605,7 @@
reg = <0x40014400 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 17)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 17U)>;
+ resets = <&rctl STM32_RESET(APB2, 17)>;
interrupts = <25 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -628,7 +628,7 @@
reg = <0x40014800 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 18)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 18U)>;
+ resets = <&rctl STM32_RESET(APB2, 18)>;
interrupts = <26 0>;
interrupt-names = "global";
st,prescaler = <0>;
diff --git a/dts/arm/st/g4/stm32g473.dtsi b/dts/arm/st/g4/stm32g473.dtsi
index ac4980c..72392aa 100644
--- a/dts/arm/st/g4/stm32g473.dtsi
+++ b/dts/arm/st/g4/stm32g473.dtsi
@@ -16,7 +16,7 @@
reg = <0x40000c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 3)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 3U)>;
+ resets = <&rctl STM32_RESET(APB1L, 3)>;
interrupts = <50 0>;
interrupt-names = "global";
st,prescaler = <0>;
diff --git a/dts/arm/st/g4/stm32g491.dtsi b/dts/arm/st/g4/stm32g491.dtsi
index a27157f..2fed23d 100644
--- a/dts/arm/st/g4/stm32g491.dtsi
+++ b/dts/arm/st/g4/stm32g491.dtsi
@@ -27,7 +27,7 @@
reg = <0x40015000 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 20)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 20U)>;
+ resets = <&rctl STM32_RESET(APB2, 20)>;
interrupts = <77 0>, <78 0>, <79 0>, <80 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
st,prescaler = <0>;
@@ -84,7 +84,7 @@
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 20)>;
- resets = <&rctl STM32_RESET(APB1L, 20U)>;
+ resets = <&rctl STM32_RESET(APB1L, 20)>;
interrupts = <53 0>;
status = "disabled";
};
