commit 07ff2d580b3c0880aafb05417bd7c890a26a5642
author Anas Nashif <anas.nashif@intel.com> Mon Sep 17 14:47:17 2018 -0500
committer Anas Nashif <anas.nashif@intel.com> Mon Oct 08 17:49:12 2018 -0400
tree aeab4ab8fb84e1f7f2fceaff649b57b0a7a3b6c8
parent f7dac85d15fbecaa5736a1c4cb807a6c8b5e8afe

drivers: dma: move to new logger

Move to new logger and adapt samples.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>

drivers/dma/dma_nios2_msgdma.c

diff --git a/drivers/dma/dma_nios2_msgdma.c b/drivers/dma/dma_nios2_msgdma.c
index 455a274..967e293 100644
--- a/drivers/dma/dma_nios2_msgdma.c
+++ b/drivers/dma/dma_nios2_msgdma.c
@@ -15,8 +15,9 @@
 #include "altera_msgdma_descriptor_regs.h"
 #include "altera_msgdma.h"
 
-#define SYS_LOG_LEVEL CONFIG_SYS_LOG_DMA_LEVEL
-#include <logging/sys_log.h>
+#define LOG_LEVEL CONFIG_DMA_LOG_LEVEL
+#include <logging/log.h>
+LOG_MODULE_REGISTER(dma_nios2)
 
 /* Device configuration parameters */
 struct nios2_msgdma_dev_cfg {
@@ -58,7 +59,7 @@
 		err_code = 0;
 	}
 
-	SYS_LOG_DBG("msgdma csr status Reg: 0x%x", status);
+	LOG_DBG("msgdma csr status Reg: 0x%x", status);
 
 	dev_cfg->dma_callback((struct device *)context, 0, err_code);
 }
@@ -73,29 +74,29 @@
 
 	/* Nios-II MSGDMA supports only one channel per DMA core */
 	if (channel != 0) {
-		SYS_LOG_ERR("invalid channel number");
+		LOG_ERR("invalid channel number");
 		return -EINVAL;
 	}
 
 #if MSGDMA_0_CSR_PREFETCHER_ENABLE
 	if (cfg->block_count > 1) {
-		SYS_LOG_ERR("driver yet add support multiple descriptors");
+		LOG_ERR("driver yet add support multiple descriptors");
 		return -EINVAL;
 	}
 #else
 	if (cfg->block_count != 1) {
-		SYS_LOG_ERR("invalid block count!!");
+		LOG_ERR("invalid block count!!");
 		return -EINVAL;
 	}
 #endif
 
 	if (cfg->head_block == NULL) {
-		SYS_LOG_ERR("head_block ptr NULL!!");
+		LOG_ERR("head_block ptr NULL!!");
 		return -EINVAL;
 	}
 
 	if (cfg->head_block->block_size > MSGDMA_0_DESCRIPTOR_SLAVE_MAX_BYTE) {
-		SYS_LOG_ERR("DMA error: Data size too big: %d",
+		LOG_ERR("DMA error: Data size too big: %d",
 			    cfg->head_block->block_size);
 		return -EINVAL;
 	}
@@ -127,7 +128,7 @@
 			dma_block->block_size,
 			control);
 	} else {
-		SYS_LOG_ERR("invalid channel direction");
+		LOG_ERR("invalid channel direction");
 		status = -EINVAL;
 	}
 
@@ -154,7 +155,7 @@
 
 	/* Nios-II mSGDMA supports only one channel per DMA core */
 	if (channel != 0) {
-		SYS_LOG_ERR("Invalid channel number");
+		LOG_ERR("Invalid channel number");
 		return -EINVAL;
 	}
 
@@ -164,7 +165,7 @@
 	k_sem_give(&cfg->sem_lock);
 
 	if (status < 0) {
-		SYS_LOG_ERR("DMA transfer error (%d)", status);
+		LOG_ERR("DMA transfer error (%d)", status);
 	}
 
 	return status;
@@ -185,11 +186,11 @@
 	k_sem_give(&cfg->sem_lock);
 
 	if (status & ALTERA_MSGDMA_CSR_STOP_STATE_MASK) {
-		SYS_LOG_DBG("DMA Dispatcher stopped");
+		LOG_DBG("DMA Dispatcher stopped");
 		ret = 0;
 	}
 
-	SYS_LOG_DBG("msgdma csr status Reg: 0x%x", status);
+	LOG_DBG("msgdma csr status Reg: 0x%x", status);
 
 	return status;
 }