dts: arm: st: stm32f0: remove U suffix from "resets" in DTSI
STM32 reset controller position argument provided to STM32_RESET()
macro sometime uses an unnecessary U suffix. Remove these useless
suffixes for this series for consistency among STM32 SoCs DTSI files.
No functional change.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
diff --git a/dts/arm/st/f0/stm32f0.dtsi b/dts/arm/st/f0/stm32f0.dtsi
index 2078664..26bc60a 100644
--- a/dts/arm/st/f0/stm32f0.dtsi
+++ b/dts/arm/st/f0/stm32f0.dtsi
@@ -176,7 +176,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 14)>;
- resets = <&rctl STM32_RESET(APB2, 14U)>;
+ resets = <&rctl STM32_RESET(APB2, 14)>;
interrupts = <27 0>;
status = "disabled";
};
@@ -237,7 +237,7 @@
reg = <0x40012c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 11)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 11U)>;
+ resets = <&rctl STM32_RESET(APB2, 11)>;
interrupts = <13 0>, <14 0>;
interrupt-names = "brk_up_trg_com", "cc";
st,prescaler = <0>;
@@ -255,7 +255,7 @@
reg = <0x40000400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 1)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1, 1U)>;
+ resets = <&rctl STM32_RESET(APB1, 1)>;
interrupts = <16 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -278,7 +278,7 @@
reg = <0x40002000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 8)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1, 8U)>;
+ resets = <&rctl STM32_RESET(APB1, 8)>;
interrupts = <19 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -301,7 +301,7 @@
reg = <0x40014400 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 17)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 17U)>;
+ resets = <&rctl STM32_RESET(APB2, 17)>;
interrupts = <21 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -324,7 +324,7 @@
reg = <0x40014800 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 18)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 18U)>;
+ resets = <&rctl STM32_RESET(APB2, 18)>;
interrupts = <22 0>;
interrupt-names = "global";
st,prescaler = <0>;
diff --git a/dts/arm/st/f0/stm32f030X8.dtsi b/dts/arm/st/f0/stm32f030X8.dtsi
index a440d8d..f0fe64e 100644
--- a/dts/arm/st/f0/stm32f030X8.dtsi
+++ b/dts/arm/st/f0/stm32f030X8.dtsi
@@ -22,7 +22,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 17)>;
- resets = <&rctl STM32_RESET(APB1, 17U)>;
+ resets = <&rctl STM32_RESET(APB1, 17)>;
interrupts = <28 0>;
status = "disabled";
};
@@ -54,7 +54,7 @@
reg = <0x40001000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 4)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1, 4U)>;
+ resets = <&rctl STM32_RESET(APB1, 4)>;
interrupts = <17 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -66,7 +66,7 @@
reg = <0x40014000 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 16)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 16U)>;
+ resets = <&rctl STM32_RESET(APB2, 16)>;
interrupts = <20 0>;
interrupt-names = "global";
st,prescaler = <0>;
diff --git a/dts/arm/st/f0/stm32f030Xc.dtsi b/dts/arm/st/f0/stm32f030Xc.dtsi
index 6b0b9df..53cf999 100644
--- a/dts/arm/st/f0/stm32f030Xc.dtsi
+++ b/dts/arm/st/f0/stm32f030Xc.dtsi
@@ -30,7 +30,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
- resets = <&rctl STM32_RESET(APB1, 18U)>;
+ resets = <&rctl STM32_RESET(APB1, 18)>;
interrupts = <29 0>;
status = "disabled";
};
@@ -39,7 +39,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 19)>;
- resets = <&rctl STM32_RESET(APB1, 19U)>;
+ resets = <&rctl STM32_RESET(APB1, 19)>;
interrupts = <29 0>;
status = "disabled";
};
@@ -48,7 +48,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 20)>;
- resets = <&rctl STM32_RESET(APB1, 20U)>;
+ resets = <&rctl STM32_RESET(APB1, 20)>;
interrupts = <29 0>;
status = "disabled";
};
@@ -57,7 +57,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011400 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 5)>;
- resets = <&rctl STM32_RESET(APB2, 5U)>;
+ resets = <&rctl STM32_RESET(APB2, 5)>;
interrupts = <29 0>;
status = "disabled";
};
@@ -67,7 +67,7 @@
reg = <0x40001400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 5)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1, 5U)>;
+ resets = <&rctl STM32_RESET(APB1, 5)>;
interrupts = <18 0>;
interrupt-names = "global";
st,prescaler = <0>;
diff --git a/dts/arm/st/f0/stm32f031.dtsi b/dts/arm/st/f0/stm32f031.dtsi
index 9c08dd1..f1183b2 100644
--- a/dts/arm/st/f0/stm32f031.dtsi
+++ b/dts/arm/st/f0/stm32f031.dtsi
@@ -15,7 +15,7 @@
reg = <0x40000000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 0)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1, 0U)>;
+ resets = <&rctl STM32_RESET(APB1, 0)>;
interrupts = <15 0>;
interrupt-names = "global";
st,prescaler = <0>;
diff --git a/dts/arm/st/f0/stm32f042.dtsi b/dts/arm/st/f0/stm32f042.dtsi
index 89e7878..0622134 100644
--- a/dts/arm/st/f0/stm32f042.dtsi
+++ b/dts/arm/st/f0/stm32f042.dtsi
@@ -23,7 +23,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 17)>;
- resets = <&rctl STM32_RESET(APB1, 17U)>;
+ resets = <&rctl STM32_RESET(APB1, 17)>;
interrupts = <28 0>;
status = "disabled";
};
@@ -51,7 +51,7 @@
reg = <0x40014000 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 16)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 16U)>;
+ resets = <&rctl STM32_RESET(APB2, 16)>;
interrupts = <20 0>;
interrupt-names = "global";
st,prescaler = <0>;
diff --git a/dts/arm/st/f0/stm32f051.dtsi b/dts/arm/st/f0/stm32f051.dtsi
index f73e92b..05f4fac 100644
--- a/dts/arm/st/f0/stm32f051.dtsi
+++ b/dts/arm/st/f0/stm32f051.dtsi
@@ -14,7 +14,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 17)>;
- resets = <&rctl STM32_RESET(APB1, 17U)>;
+ resets = <&rctl STM32_RESET(APB1, 17)>;
interrupts = <28 0>;
status = "disabled";
};
@@ -46,7 +46,7 @@
reg = <0x40001000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 4)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1, 4U)>;
+ resets = <&rctl STM32_RESET(APB1, 4)>;
interrupts = <17 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -58,7 +58,7 @@
reg = <0x40014000 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 16)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 16U)>;
+ resets = <&rctl STM32_RESET(APB2, 16)>;
interrupts = <20 0>;
interrupt-names = "global";
st,prescaler = <0>;
diff --git a/dts/arm/st/f0/stm32f070.dtsi b/dts/arm/st/f0/stm32f070.dtsi
index e9a5a38..b5a7227 100644
--- a/dts/arm/st/f0/stm32f070.dtsi
+++ b/dts/arm/st/f0/stm32f070.dtsi
@@ -14,7 +14,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 17)>;
- resets = <&rctl STM32_RESET(APB1, 17U)>;
+ resets = <&rctl STM32_RESET(APB1, 17)>;
interrupts = <28 0>;
status = "disabled";
};
@@ -24,7 +24,7 @@
reg = <0x40014000 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 16)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 16U)>;
+ resets = <&rctl STM32_RESET(APB2, 16)>;
interrupts = <20 0>;
interrupt-names = "global";
st,prescaler = <0>;
diff --git a/dts/arm/st/f0/stm32f070Xb.dtsi b/dts/arm/st/f0/stm32f070Xb.dtsi
index b7c8abe..e8226c4 100644
--- a/dts/arm/st/f0/stm32f070Xb.dtsi
+++ b/dts/arm/st/f0/stm32f070Xb.dtsi
@@ -29,7 +29,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
- resets = <&rctl STM32_RESET(APB1, 18U)>;
+ resets = <&rctl STM32_RESET(APB1, 18)>;
interrupts = <29 0>;
status = "disabled";
};
@@ -38,7 +38,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 19)>;
- resets = <&rctl STM32_RESET(APB1, 19U)>;
+ resets = <&rctl STM32_RESET(APB1, 19)>;
interrupts = <29 0>;
status = "disabled";
};
@@ -70,7 +70,7 @@
reg = <0x40001000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 4)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1, 4U)>;
+ resets = <&rctl STM32_RESET(APB1, 4)>;
interrupts = <17 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -82,7 +82,7 @@
reg = <0x40001400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 5)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1, 5U)>;
+ resets = <&rctl STM32_RESET(APB1, 5)>;
interrupts = <18 0>;
interrupt-names = "global";
st,prescaler = <0>;
diff --git a/dts/arm/st/f0/stm32f071.dtsi b/dts/arm/st/f0/stm32f071.dtsi
index bd0d2dd..a8ecaa0 100644
--- a/dts/arm/st/f0/stm32f071.dtsi
+++ b/dts/arm/st/f0/stm32f071.dtsi
@@ -45,7 +45,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
- resets = <&rctl STM32_RESET(APB1, 18U)>;
+ resets = <&rctl STM32_RESET(APB1, 18)>;
interrupts = <29 0>;
status = "disabled";
};
@@ -54,7 +54,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 19)>;
- resets = <&rctl STM32_RESET(APB1, 19U)>;
+ resets = <&rctl STM32_RESET(APB1, 19)>;
interrupts = <29 0>;
status = "disabled";
};
@@ -64,7 +64,7 @@
reg = <0x40001400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 5)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1, 5U)>;
+ resets = <&rctl STM32_RESET(APB1, 5)>;
interrupts = <18 0>;
interrupt-names = "global";
st,prescaler = <0>;
diff --git a/dts/arm/st/f0/stm32f091.dtsi b/dts/arm/st/f0/stm32f091.dtsi
index ff6fcd9..335aec3 100644
--- a/dts/arm/st/f0/stm32f091.dtsi
+++ b/dts/arm/st/f0/stm32f091.dtsi
@@ -20,7 +20,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 20)>;
- resets = <&rctl STM32_RESET(APB1, 20U)>;
+ resets = <&rctl STM32_RESET(APB1, 20)>;
interrupts = <29 0>;
status = "disabled";
};
@@ -29,7 +29,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011400 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 5)>;
- resets = <&rctl STM32_RESET(APB2, 5U)>;
+ resets = <&rctl STM32_RESET(APB2, 5)>;
interrupts = <29 0>;
status = "disabled";
};
@@ -38,7 +38,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011800 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 6)>;
- resets = <&rctl STM32_RESET(APB2, 6U)>;
+ resets = <&rctl STM32_RESET(APB2, 6)>;
interrupts = <29 0>;
status = "disabled";
};
@@ -47,7 +47,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 7)>;
- resets = <&rctl STM32_RESET(APB2, 7U)>;
+ resets = <&rctl STM32_RESET(APB2, 7)>;
interrupts = <29 0>;
status = "disabled";
};
