| commit | 0a5b25916c9a91814bb9583b4085d3decf247dc5 | [log] [tgz] |
|---|---|---|
| author | Alexandre Mergnat <amergnat@baylibre.com> | Tue Nov 03 15:27:15 2020 +0100 |
| committer | Anas Nashif <anas.nashif@intel.com> | Mon Nov 09 15:37:11 2020 -0500 |
| tree | be0ac45d7b3a4a8be13550225013c44feb1ec30e | |
| parent | 39208c2700ffb0c62df6e1ea4f73773f8d6d5385 [diff] |
tests: protection: add riscv support Execute tests are disabled for RISC-V because is isn't able to set an execution restriction. From RISC-V documentation: "Instruction address-translation and protection are unaffected by the setting of MPRV" MPRV is used to apply memory protection restriction when CPU is running in machine mode (kernel). Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>