| commit | 0a6918d064befdbd9addf503ecf63fe36574ae54 | [log] [tgz] |
|---|---|---|
| author | Katsuhiro Suzuki <katsuhiro@katsuster.net> | Thu Oct 22 10:49:12 2020 +0900 |
| committer | Anas Nashif <anas.nashif@intel.com> | Thu Nov 19 12:45:14 2020 -0500 |
| tree | fa29213694725010f4b513de6170850596d989ec | |
| parent | a43db40da3a18770c45e914588c3a03a28b7951c [diff] |
dts: riscv32-fe310: add missing clint properties RISC-V clint is an interrupt controller but it has no required properties (#interrupt-cells and interrupt-controller). This patch just adds missing properties. Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>