soc: riscv: litex: Add helpers for accessing CSRs
Depending on LiteX configuration, CSRs
(control&status registers) might be split
into several consecutive registers.
This introduces common helper functions
for all LiteX drivers providing access
to CSRs for a default LiteX configuration
(data_width = 8bit, bus_width = 32bit).
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
diff --git a/soc/riscv/litex-vexriscv/soc.h b/soc/riscv/litex-vexriscv/soc.h
index 5451f51..49a71fa 100644
--- a/soc/riscv/litex-vexriscv/soc.h
+++ b/soc/riscv/litex-vexriscv/soc.h
@@ -14,4 +14,46 @@
#define RISCV_RAM_BASE DT_INST_0_MMIO_SRAM_BASE_ADDRESS
#define RISCV_RAM_SIZE DT_INST_0_MMIO_SRAM_SIZE
+#ifndef _ASMLANGUAGE
+/* CSR access helpers */
+
+static inline unsigned char litex_read8(unsigned long addr)
+{
+ return sys_read8(addr);
+}
+
+static inline unsigned short litex_read16(unsigned long addr)
+{
+ return (sys_read8(addr) << 8)
+ | sys_read8(addr + 0x4);
+}
+
+static inline unsigned int litex_read32(unsigned long addr)
+{
+ return (sys_read8(addr) << 24)
+ | (sys_read8(addr + 0x4) << 16)
+ | (sys_read8(addr + 0x8) << 8)
+ | sys_read8(addr + 0xc);
+}
+
+static inline void litex_write8(unsigned char value, unsigned long addr)
+{
+ sys_write8(value, addr);
+}
+
+static inline void litex_write16(unsigned short value, unsigned long addr)
+{
+ sys_write8(value >> 8, addr);
+ sys_write8(value, addr + 0x4);
+}
+
+static inline void litex_write32(unsigned int value, unsigned long addr)
+{
+ sys_write8(value >> 24, addr);
+ sys_write8(value >> 16, addr + 0x4);
+ sys_write8(value >> 8, addr + 0x8);
+ sys_write8(value, addr + 0xC);
+}
+#endif /* _ASMLANGUAGE */
+
#endif /* __RISCV32_LITEX_VEXRISCV_SOC_H_ */
