| commit | 10500f1b419d56bc4f908aa35ae2fb81c589bed4 | [log] [tgz] |
|---|---|---|
| author | Nicolas Pitre <npitre@baylibre.com> | Sun Jan 29 12:09:05 2023 -0500 |
| committer | Fabio Baltieri <fabio.baltieri@gmail.com> | Mon Jan 30 23:47:36 2023 +0000 |
| tree | 798bda900fd31bf1a9266ae84932f46c0a24d348 | |
| parent | 83f849e00e875dcc96fb0d86af1a07a92ead1221 [diff] |
riscv: cope with MTVAL not updated on illegal instruction faults Some implementations may not capture the faulting instruction in mtval and set it to zero when an illegal instruction fault is raised This is notably the case with QEMU version 7.0.0 when a CSR instruction is involved. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>