| commit | 112bcb229cd28b385b322f9b048eb9182052fb07 | [log] [tgz] |
|---|---|---|
| author | Jan Bylicki <jbylicki@antmicro.com> | Wed Dec 13 13:53:17 2023 +0100 |
| committer | Henrik Brix Andersen <henrik@brixandersen.dk> | Mon Mar 04 22:14:48 2024 +0100 |
| tree | 051b0da4111fe588e3a00e0453898fb5e13fbf1f | |
| parent | cfa7e38378a9023cd6b4e1bc093de8f82e4b413b [diff] |
soc/arm/renesas_rzt2m: set default System Clock Control register values Introduced changes to set the default values for clock control registers Signed-off-by: Jan Bylicki <jbylicki@antmicro.com>