board: mcx_nx4x: format board.c
- format mcx_nx4x_evk board.c which is not formatted according to the
coding standards
- improve code readability and maintainability
Signed-off-by: Tomas Barak <tomas.barak@nxp.com>
diff --git a/boards/nxp/mcx_nx4x_evk/board.c b/boards/nxp/mcx_nx4x_evk/board.c
index bf55c08..1389e7b 100644
--- a/boards/nxp/mcx_nx4x_evk/board.c
+++ b/boards/nxp/mcx_nx4x_evk/board.c
@@ -18,14 +18,16 @@
#define BOARD_USB_PHY_TXCAL45DM (0x07U)
usb_phy_config_struct_t usbPhyConfig = {
- BOARD_USB_PHY_D_CAL, BOARD_USB_PHY_TXCAL45DP, BOARD_USB_PHY_TXCAL45DM,
+ BOARD_USB_PHY_D_CAL,
+ BOARD_USB_PHY_TXCAL45DP,
+ BOARD_USB_PHY_TXCAL45DM,
};
#endif
/* Board xtal frequency in Hz */
-#define BOARD_XTAL0_CLK_HZ 24000000U
+#define BOARD_XTAL0_CLK_HZ 24000000U
/* Core clock frequency: 150MHz */
-#define CLOCK_INIT_CORE_CLOCK 150000000U
+#define CLOCK_INIT_CORE_CLOCK 150000000U
/* System clock frequency. */
extern uint32_t SystemCoreClock;
@@ -34,21 +36,21 @@
{
/* Set the DCDC VDD regulator to 1.2 V voltage level */
spc_active_mode_dcdc_option_t opt = {
- .DCDCVoltage = kSPC_DCDC_OverdriveVoltage,
+ .DCDCVoltage = kSPC_DCDC_OverdriveVoltage,
.DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength,
};
SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &opt);
/* Set the LDO_CORE VDD regulator to 1.2 V voltage level */
spc_active_mode_core_ldo_option_t ldo_opt = {
- .CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage,
+ .CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage,
.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength,
};
SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldo_opt);
/* Specifies the 1.2V operating voltage for the SRAM's read/write timing margin */
spc_sram_voltage_config_t cfg = {
- .operateVoltage = kSPC_sramOperateAt1P2V,
+ .operateVoltage = kSPC_sramOperateAt1P2V,
.requestVoltageUpdate = true,
};
SPC_SetSRAMOperateVoltage(SPC0, &cfg);
@@ -115,14 +117,12 @@
#endif
/* Set up PLL0 */
- const pll_setup_t pll0Setup = {
- .pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) |
- SCG_APLLCTRL_SELP(13U),
- .pllndiv = SCG_APLLNDIV_NDIV(8U),
- .pllpdiv = SCG_APLLPDIV_PDIV(1U),
- .pllmdiv = SCG_APLLMDIV_MDIV(50U),
- .pllRate = 150000000U
- };
+ const pll_setup_t pll0Setup = {.pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) |
+ SCG_APLLCTRL_SELP(13U),
+ .pllndiv = SCG_APLLNDIV_NDIV(8U),
+ .pllpdiv = SCG_APLLPDIV_PDIV(1U),
+ .pllmdiv = SCG_APLLMDIV_MDIV(50U),
+ .pllRate = 150000000U};
/* Configure PLL0 to the desired values */
CLOCK_SetPLL0Freq(&pll0Setup);
/* PLL0 Monitor is disabled */
@@ -136,15 +136,15 @@
CLOCK_SetupExtClocking(BOARD_XTAL0_CLK_HZ);
-#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(micfil))
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1)) || \
+ DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(micfil))
/* < Set up PLL1 */
- const pll_setup_t pll1_Setup = {
- .pllctrl = SCG_SPLLCTRL_SOURCE(1U) | SCG_SPLLCTRL_SELI(3U) |
- SCG_SPLLCTRL_SELP(1U),
- .pllndiv = SCG_SPLLNDIV_NDIV(25U),
- .pllpdiv = SCG_SPLLPDIV_PDIV(10U),
- .pllmdiv = SCG_SPLLMDIV_MDIV(256U),
- .pllRate = 24576000U};
+ const pll_setup_t pll1_Setup = {.pllctrl = SCG_SPLLCTRL_SOURCE(1U) | SCG_SPLLCTRL_SELI(3U) |
+ SCG_SPLLCTRL_SELP(1U),
+ .pllndiv = SCG_SPLLNDIV_NDIV(25U),
+ .pllpdiv = SCG_SPLLPDIV_PDIV(10U),
+ .pllmdiv = SCG_SPLLMDIV_MDIV(256U),
+ .pllRate = 24576000U};
/* Configure PLL1 to the desired values */
CLOCK_SetPLL1Freq(&pll1_Setup);
@@ -355,8 +355,8 @@
while (0U == (SCG0->LDOCSR & SCG_LDOCSR_VOUT_OK_MASK)) {
};
}
- SYSCON->AHBCLKCTRLSET[2] |= SYSCON_AHBCLKCTRL2_USB_HS_MASK |
- SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK;
+ SYSCON->AHBCLKCTRLSET[2] |=
+ SYSCON_AHBCLKCTRL2_USB_HS_MASK | SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK;
SCG0->SOSCCFG &= ~(SCG_SOSCCFG_RANGE_MASK | SCG_SOSCCFG_EREFS_MASK);
/* xtal = 20 ~ 30MHz */
SCG0->SOSCCFG = (1U << SCG_SOSCCFG_RANGE_SHIFT) | (1U << SCG_SOSCCFG_EREFS_SHIFT);
@@ -366,8 +366,8 @@
break;
}
}
- SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK |
- SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK;
+ SYSCON->CLOCK_CTRL |=
+ SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK | SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK;
CLOCK_EnableClock(kCLOCK_UsbHs);
CLOCK_EnableClock(kCLOCK_UsbHsPhy);
CLOCK_EnableUsbhsPhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ);
