| commit | 13f8d809300299cb56abf763d289e0b2eec0d4dc | [log] [tgz] |
|---|---|---|
| author | Conor Paxton <conor.paxton@microchip.com> | Sat Dec 02 18:19:18 2023 +0000 |
| committer | Fabio Baltieri <fabio.baltieri@gmail.com> | Wed Dec 06 17:54:29 2023 +0000 |
| tree | 253970895b5ea09f231056d0dc2eb7f8a090111b | |
| parent | 3c7f10f8e1174ce03f7ccc6568ba7c1c342791ae [diff] |
dts: riscv: add all contexts and devices to the plic on mpfs Microchip's PolarFire SoC has a total of 9 contexts associated with the Platform Interrupt controller (PLIC). the E51 core has a single context (M Mode), and the application processor U54 cores have two each (M mode and S mode, respectively) While we are at it, there are a total of 186 interrupts, not 187. Signed-off-by: Conor Paxton <conor.paxton@microchip.com>