dts: bindings: mbox: Add AMD-Xilinx IPI mailbox

Add device tree bindings for the AMD-Xilinx Inter Processor Interrupts
(IPI) mailbox.

The IPI architecture allows the passing of messages across the system
without the complications of autonomous read-write transactions and
polling inefficiency. The notification of the interrupt is also
possible without message buffers on some platforms. Some IPI channels
are hard-wired to particular core while others can be configured to
assign to any core on AMD-Xilinx heterogenous multiprocessor platform.

Signed-off-by: Ajay Neeli <ajay.neeli@amd.com>