152d3e46adebd2c55adde2006eed3cb69061b124 - third_party/github/zephyrproject-rtos/zephyr

commit	152d3e46adebd2c55adde2006eed3cb69061b124	[log] [tgz]
author	Martin Åberg <martin.aberg@gaisler.com>	Tue Dec 08 18:54:43 2020 +0100
committer	Anas Nashif <anas.nashif@intel.com>	Fri Jan 15 13:06:33 2021 -0500
tree	ce344205b4014e982b8f0fdb9e3577c0a330a69f
parent	d2e9568543496459373c14a74147e31b1e1b264e [diff]

soc/riscv: add the QEMU "RISC-V VirtIO board"

The QEMU RISC-V VirtIO board is capable:
- 8 x CPU
- 256 MiB RAM
- PMP
- PCI
- ISA string: RVnnIMAFDCSU
  - mul/div
  - FPU with double precision
  - MMU
  - Compressed instructions

Devicetree was extracted from QEMU as described in virt.dtsi.
The same .dtsi SOC description is used for 32-bit and 64-bit.

Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>

CODEOWNERS[diff]
dts/riscv/virt.dtsi[Added - diff]
soc/riscv/riscv-privilege/virt/CMakeLists.txt[Added - diff]
soc/riscv/riscv-privilege/virt/Kconfig.defconfig.series[Added - diff]
soc/riscv/riscv-privilege/virt/Kconfig.series[Added - diff]
soc/riscv/riscv-privilege/virt/Kconfig.soc[Added - diff]
soc/riscv/riscv-privilege/virt/linker.ld[Added - diff]
soc/riscv/riscv-privilege/virt/soc.h[Added - diff]

8 files changed